You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/07/22 09:44:40 UTC
[GitHub] [incubator-nuttx] PetervdPerk-NXP opened a new pull request, #6687: Add support for NXP S32K3XX MCU family and boards
PetervdPerk-NXP opened a new pull request, #6687:
URL: https://github.com/apache/incubator-nuttx/pull/6687
## Summary
Initial support for NXP S32K3XX MCU family including many drivers
- UART
- I2C
- SPI
- CAN
- Ethernet
- QSPI
- GPIO (+ interrupt)
Add support for following boards:
S32k3X4EVB-Q257
MR-CANHUBK3 (To be released soon)
## Impact
Also changes MX25RXX driver to support MX25LXX as well.
Bug fixes in net/can receiving with multiple applications.
SocketCAN add non-blocking write support
## Testing
Tested on S32k3X4EVB-Q257 & MR-CANHUBK3
## Note
This the first commit since we've signed the CCLA & ICLA, we're still required by company policy to include a NXP Copyright header, is this included in the correct way? Furthermore do the NOTICE and AUTHOR files have to updated and what's the policy to do so?
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6687: Add support for NXP S32K3XX MCU family and boards
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6687:
URL: https://github.com/apache/incubator-nuttx/pull/6687#discussion_r928112331
##########
arch/arm/src/s32k3xx/s32k3xx_edma.c:
##########
@@ -1623,4 +1659,4 @@ void s32k3xx_dmadump(const struct s32k3xx_dmaregs_s *regs, const char *msg)
dmainfo(" DMAMUX: %08x\n", (unsigned int)regs->dmamux);
}
#endif /* CONFIG_DEBUG_DMA */
-#endif /* CONFIG_S32K3XX_EDMA */
+#endif /* CONFIG_S32K3XX_EDMA */
Review Comment:
why all header file remove the last \n?
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] PetervdPerk-NXP commented on pull request #6687: Add support for NXP S32K3XX MCU family and boards
Posted by GitBox <gi...@apache.org>.
PetervdPerk-NXP commented on PR #6687:
URL: https://github.com/apache/incubator-nuttx/pull/6687#issuecomment-1192690328
> @PetervdPerk-NXP Are those Doxygen tags?
>
> `Deoxygen Information. NuttX does not use Deoxygen for documentation and no file should contain Doxygen tags or Doxygen style comments.`
Thanks there were some files using wrong comment style indeed, I've fixed them.
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] davids5 commented on a diff in pull request #6687: Add support for NXP S32K3XX MCU family and boards
Posted by GitBox <gi...@apache.org>.
davids5 commented on code in PR #6687:
URL: https://github.com/apache/incubator-nuttx/pull/6687#discussion_r927870796
##########
arch/arm/src/s32k3xx/s32k3xx_edma.c:
##########
@@ -0,0 +1,1626 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/s32k3xx_edma.c
+ *
+ * Copyright (C) 2019, 2021 Gregory Nutt. All rights reserved.
+ * Copyright 2022 NXP
+ * Authors: Gregory Nutt <gn...@nuttx.org>
+ * David Sidrane <da...@nscdg.com>
+ * Peter van der Perk <pe...@nxp.com>
+ *
+ * This file was leveraged from the NuttX S32K1 port. Portions of that eDMA
+ * logic derived from NXP sample code which has a compatible BSD 3-clause
+ * license:
+ *
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
Review Comment:
Fine by me - We have all already lost the credits for all the work we have done.
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] davids5 commented on pull request #6687: Add support for NXP S32K3XX MCU family and boards
Posted by GitBox <gi...@apache.org>.
davids5 commented on PR #6687:
URL: https://github.com/apache/incubator-nuttx/pull/6687#issuecomment-1192679448
@PetervdPerk-NXP Are those Doxygen tags?
`Deoxygen Information. NuttX does not use Deoxygen for documentation and no file should contain Doxygen tags or Doxygen style comments.`
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] davids5 closed pull request #6687: Add support for NXP S32K3XX MCU family and boards
Posted by GitBox <gi...@apache.org>.
davids5 closed pull request #6687: Add support for NXP S32K3XX MCU family and boards
URL: https://github.com/apache/incubator-nuttx/pull/6687
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6687: Add support for NXP S32K3XX MCU family and boards
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6687:
URL: https://github.com/apache/incubator-nuttx/pull/6687#discussion_r927607234
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h:
##########
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DMAMUX_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DMAMUX_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* DMAMUX Register Offsets **************************************************/
+
+#define S32K3XX_DMAMUX_CHCFG3_OFFSET (0x00) /* Channel Configuration Register 3 (CHCFG3) */
+#define S32K3XX_DMAMUX_CHCFG2_OFFSET (0x01) /* Channel Configuration Register 2 (CHCFG2) */
+#define S32K3XX_DMAMUX_CHCFG1_OFFSET (0x02) /* Channel Configuration Register 1 (CHCFG1) */
+#define S32K3XX_DMAMUX_CHCFG0_OFFSET (0x03) /* Channel Configuration Register 0 (CHCFG0) */
+#define S32K3XX_DMAMUX_CHCFG7_OFFSET (0x04) /* Channel Configuration Register 7 (CHCFG7) */
+#define S32K3XX_DMAMUX_CHCFG6_OFFSET (0x05) /* Channel Configuration Register 6 (CHCFG6) */
+#define S32K3XX_DMAMUX_CHCFG5_OFFSET (0x06) /* Channel Configuration Register 5 (CHCFG5) */
+#define S32K3XX_DMAMUX_CHCFG4_OFFSET (0x07) /* Channel Configuration Register 4 (CHCFG4) */
+#define S32K3XX_DMAMUX_CHCFG11_OFFSET (0x08) /* Channel Configuration Register 11 (CHCFG11) */
+#define S32K3XX_DMAMUX_CHCFG10_OFFSET (0x09) /* Channel Configuration Register 10 (CHCFG10) */
+#define S32K3XX_DMAMUX_CHCFG9_OFFSET (0x0a) /* Channel Configuration Register 9 (CHCFG9) */
+#define S32K3XX_DMAMUX_CHCFG8_OFFSET (0x0b) /* Channel Configuration Register 8 (CHCFG8) */
+#define S32K3XX_DMAMUX_CHCFG15_OFFSET (0x0c) /* Channel Configuration Register 15 (CHCFG15) */
+#define S32K3XX_DMAMUX_CHCFG14_OFFSET (0x0d) /* Channel Configuration Register 14 (CHCFG14) */
+#define S32K3XX_DMAMUX_CHCFG13_OFFSET (0x0e) /* Channel Configuration Register 13 (CHCFG13) */
+#define S32K3XX_DMAMUX_CHCFG12_OFFSET (0x0f) /* Channel Configuration Register 12 (CHCFG12) */
+
+#define S32K3XX_DMAMUX_CHCFG_OFFSET(n) ((n) + 3 - 2 * ((n) % 4))
+
+#define S32K3XX_DMAMUX0_CHCFG(n) (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG_OFFSET(n))
+#define S32K3XX_DMAMUX1_CHCFG(n) (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG_OFFSET(n))
+
+/* DMAMUX Register Addresses ************************************************/
+
+#define S32K3XX_DMAMUX0_CHCFG3 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG3_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG2 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG2_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG1 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG1_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG0 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG0_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG7 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG7_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG6 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG6_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG5 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG5_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG4 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG4_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG11 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG11_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG10 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG10_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG9 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG9_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG8 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG8_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG15 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG15_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG14 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG14_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG13 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG13_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG12 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG12_OFFSET)
+
+#define S32K3XX_DMAMUX1_CHCFG3 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG3_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG2 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG2_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG1 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG1_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG0 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG0_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG7 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG7_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG6 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG6_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG5 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG5_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG4 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG4_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG11 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG11_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG10 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG10_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG9 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG9_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG8 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG8_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG15 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG15_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG14 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG14_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG13 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG13_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG12 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG12_OFFSET)
+
+/* DMAMUX Register Bitfield Definitions *************************************/
+
+#define DMAMUX_CHCFG_SOURCE_SHIFT (0) /* Bits 0-5: DMA Channel Source (SOURCE) */
+#define DMAMUX_CHCFG_SOURCE_MASK (0x3f << DMAMUX_CHCFG_SOURCE_SHIFT)
+#define DMAMUX_CHCFG_TRIG (1 << 6) /* Bit 6: DMA Channel Trigger Enable (TRIG) */
+#define DMAMUX_CHCFG_ENBL (1 << 7) /* Bit 7: DMA Channel Enable (ENBL) */
+#define DMAMUX_CHCFG_MASK (0xff) /* Bits 0-7 */
+
+#define DMAMUX_CHCFG_DMAMUX1 (1 << 15) /* Bit 15: DMAMUX1 Selection */
+
+/* DMA Request sources */
+
+/** edma_mux0 **/
+
+#define DMA_REQ_DISABLED0 0 ///< Channel disabled (default)
+#define DMA_REQ_SIUL_0 1 ///< SIUL DMA request 0
+#define DMA_REQ_SIUL_1 2 ///< SIUL DMA request 1
+#define DMA_REQ_SIUL_2 3 ///< SIUL DMA request 2
+#define DMA_REQ_SIUL_3 4 ///< SIUL DMA request 3
+#define DMA_REQ_SIUL_4 5 ///< SIUL DMA request 4
+#define DMA_REQ_SIUL_5 6 ///< SIUL DMA request 5
+#define DMA_REQ_SIUL_6 7 ///< SIUL DMA request 6
+#define DMA_REQ_SIUL_7 8 ///< SIUL DMA request 7
+#define DMA_REQ_BCTU_FIFO1 10 ///< BCTU DMA FIFO1 request
+#define DMA_REQ_BCTU_0 10 ///< BCTU DMA request 0
+#define DMA_REQ_BCTU_1 11 ///< BCTU DMA request 1
+#define DMA_REQ_EMIOS0_0 12 ///< eMIOS0 DMA request ch0
+#define DMA_REQ_EMIOS0_1 13 ///< eMIOS0 DMA request ch1
+#define DMA_REQ_EMIOS0_9 14 ///< eMIOS0 DMA request ch9
+#define DMA_REQ_EMIOS0_10 15 ///< eMIOS0 DMA request ch10
+#define DMA_REQ_EMIOS1_0 16 ///< eMIOS1 DMA request ch0
+#define DMA_REQ_EMIOS1_1 17 ///< eMIOS1 DMA request ch1
+#define DMA_REQ_EMIOS1_9 18 ///< eMIOS1 DMA request ch9
+#define DMA_REQ_EMIOS1_10 19 ///< eMIOS1 DMA request ch10
+#define DMA_REQ_EMIOS2_0 20 ///< eMIOS2 DMA request ch0
+#define DMA_REQ_EMIOS2_1 21 ///< eMIOS2 DMA request ch1
+#define DMA_REQ_EMIOS2_9 22 ///< eMIOS2 DMA request ch9
+#define DMA_REQ_EMIOS2_10 23 ///< eMIOS2 DMA request ch10
+#define DMA_REQ_LCU0_0 24 ///< LCU0 DMA request 0
+#define DMA_REQ_LCU1_0 25 ///< LCU1 DMA request 0
+#define DMA_REQ_RESERVED1 26 ///< RESERVED
+#define DMA_REQ_RESERVED2 27 ///< RESERVED
+#define DMA_REQ_RESERVED3 28 ///< RESERVED
+#define DMA_REQ_FLEXCAN0 29 ///< FLEXCAN0 DMA request
+#define DMA_REQ_FLEXCAN1 30 ///< FLEXCAN1 DMA request
+#define DMA_REQ_FLEXCAN2 31 ///< FLEXCAN2 DMA request
+#define DMA_REQ_FLEXCAN3 32 ///< FLEXCAN3 DMA request
+#define DMA_REQ_FLEXIO_0 33 ///< FLEXIO DMA shifter0 | timer0 request
+#define DMA_REQ_FLEXIO_1 34 ///< FLEXIO DMA shifter1 | timer1 request
+#define DMA_REQ_FLEXIO_2 35 ///< FLEXIO DMA shifter2 | timer2 request
+#define DMA_REQ_FLEXIO_3 36 ///< FLEXIO DMA shifter3 | timer3 request
+#define DMA_REQ_LPUART08_TX 37 ///< LPUART0 | LPUART8 DMA transmit request
+#define DMA_REQ_LPUART08_RX 38 ///< LPUART0 | LPUART8 DMA receive request
+#define DMA_REQ_LPUART19_TX 39 ///< LPUART1 | LPUART9 DMA transmit request
+#define DMA_REQ_LPUART19_RX 40 ///< LPUART1 | LPUART9 DMA receive request
+#define DMA_REQ_LPI2C0_RX 41 ///< LPI2C0 DMA receive | receive slave request
+#define DMA_REQ_LPI2C0_TX 42 ///< LPI2C0 DMA transmit | transmit slave request
+#define DMA_REQ_LPSPI0_TX 43 ///< LPSPI0 DMA transmit request
+#define DMA_REQ_LPSPI0_RX 44 ///< LPSPI0 DMA receive request
+#define DMA_REQ_LPSPI1_TX 45 ///< LPSPI1 DMA transmit request
+#define DMA_REQ_LPSPI1_RX 46 ///< LPSPI1 DMA receive request
+#define DMA_REQ_LPSPI2_TX 47 ///< LPSPI2 DMA transmit request
+#define DMA_REQ_LPSPI2_RX 48 ///< LPSPI2 DMA receive request
+#define DMA_REQ_LPSPI3_TX 49 ///< LPSPI3 DMA transmit request
+#define DMA_REQ_LPSPI3_RX 50 ///< LPSPI3 DMA receive request
+#define DMA_REQ_I3C0_RX 51 ///< I3C0 DMA receive request
+#define DMA_REQ_I3C0_TX 52 ///< I3C0 DMA transmit request
+#define DMA_REQ_QSPI_RX 53 ///< QSPI DMA receive buffer drain request
+#define DMA_REQ_QSPI_TX 54 ///< QSPI DMA transmit buffer fill request
+#define DMA_REQ_SAI0_RX 55 ///< SAI0 DMA receive request
+#define DMA_REQ_SAI0_TX 56 ///< SAI0 DMA transmit request
+#define DMA_REQ_RESERVED4 57 ///< RESERVED
+#define DMA_REQ_ADC0 58 ///< ADC0 DMA request
+#define DMA_REQ_ADC1 59 ///< ADC1 DMA request
+#define DMA_REQ_ADC2 60 ///< ADC2 DMA request
+#define DMA_REQ_LPCMP0 61 ///< LPCMP0 DMA request
+#define DMA_REQ_ENABLED0 62 ///< Always enabled
+#define DMA_REQ_ENABLED1 63 ///< Always enabled */
+
+/** edma_mux1 **/
+
+#define DMA_REQ_DISABLED1 DMAMUX_CHCFG_DMAMUX1 | 0 ///< Channel disabled (default)
+#define DMA_REQ_SIUL_8 DMAMUX_CHCFG_DMAMUX1 | 1 ///< SIUL DMA request 8
+#define DMA_REQ_SIUL_9 DMAMUX_CHCFG_DMAMUX1 | 2 ///< SIUL DMA request 9
+#define DMA_REQ_SIUL_10 DMAMUX_CHCFG_DMAMUX1 | 3 ///< SIUL DMA request 10
+#define DMA_REQ_SIUL_11 DMAMUX_CHCFG_DMAMUX1 | 4 ///< SIUL DMA request 11
+#define DMA_REQ_SIUL_12 DMAMUX_CHCFG_DMAMUX1 | 5 ///< SIUL DMA request 12
+#define DMA_REQ_SIUL_13 DMAMUX_CHCFG_DMAMUX1 | 6 ///< SIUL DMA request 13
+#define DMA_REQ_SIUL_14 DMAMUX_CHCFG_DMAMUX1 | 7 ///< SIUL DMA request 14
+#define DMA_REQ_SIUL_15 DMAMUX_CHCFG_DMAMUX1 | 8 ///< SIUL DMA request 15
+#define DMA_REQ_BCTU_FIFO2 DMAMUX_CHCFG_DMAMUX1 | 9 ///< BCTU DMA FIFO2 request
+#define DMA_REQ_BCTU_2 DMAMUX_CHCFG_DMAMUX1 | 10 ///< BCTU DMA request 2
+#define DMA_REQ_EMIOS0_16 DMAMUX_CHCFG_DMAMUX1 | 11 ///< eMIOS0 DMA request ch16
+#define DMA_REQ_EMIOS0_17 DMAMUX_CHCFG_DMAMUX1 | 12 ///< eMIOS0 DMA request ch17
Review Comment:
I think it is good to wrap with `()`
##########
drivers/mtd/mx25rxx.c:
##########
@@ -100,7 +100,11 @@
/* JEDEC Read ID register values */
#define MX25R_JEDEC_MANUFACTURER 0xc2 /* Macronix manufacturer ID */
+#ifdef CONFIG_MX25RXX_LXX
+#define MX25R_JEDEC_MEMORY_TYPE 0x20 /* MX25Lx memory type */
Review Comment:
```suggestion
# define MX25R_JEDEC_MEMORY_TYPE 0x20 /* MX25Lx memory type */
```
##########
drivers/mtd/mx25rxx.c:
##########
@@ -112,7 +116,12 @@
#define MX25R6435F_SECTOR_SHIFT (12)
#define MX25R6435F_SECTOR_COUNT (2048)
#define MX25R6435F_PAGE_SIZE (256)
+
+#ifdef CONFIG_MX25RXX_PAGE128
+#define MX25R6435F_PAGE_SHIFT (7)
+#else
#define MX25R6435F_PAGE_SHIFT (8)
Review Comment:
```suggestion
# define MX25R6435F_PAGE_SHIFT (8)
```
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h:
##########
@@ -0,0 +1,1433 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define S32K3XX_EDMA_NCHANNELS 32
+
+/* eDMA Register Offsets ****************************************************/
+
+#define S32K3XX_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */
+#define S32K3XX_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */
+#define S32K3XX_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */
+#define S32K3XX_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */
+
+#define S32K3XX_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */
+
+/* eDMA Register Addresses **************************************************/
+
+#define S32K3XX_EDMA_CSR (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CSR_OFFSET)
+#define S32K3XX_EDMA_ES (S32K3XX_EDMA_BASE + S32K3XX_EDMA_ES_OFFSET)
+#define S32K3XX_EDMA_INT (S32K3XX_EDMA_BASE + S32K3XX_EDMA_INT_OFFSET)
+#define S32K3XX_EDMA_HRS (S32K3XX_EDMA_BASE + S32K3XX_EDMA_HRS_OFFSET)
+#define S32K3XX_EDMA_CH_GRPRI(n) (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CH_GRPRI_OFFSET(n))
+
+/* eDMA Transfer Control Descriptor (TCD) Register Offsets ******************/
+
+#define S32K3XX_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH0_CSR_OFFSET (0x000000) /* Channel 0 Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH0_ES_OFFSET (0x000004) /* Channel 0 Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH0_INT_OFFSET (0x000008) /* Channel 0 Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH0_SBR_OFFSET (0x00000c) /* Channel 0 System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH0_PRI_OFFSET (0x000010) /* Channel 0 Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD0_SADDR_OFFSET (0x000020) /* TCD0 Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD0_SOFF_OFFSET (0x000024) /* TCD0 Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD0_ATTR_OFFSET (0x000026) /* TCD0 Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD0_NBYTES_OFFSET (0x000028) /* TCD0 Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET (0x00002c) /* TCD0 Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD0_DADDR_OFFSET (0x000030) /* TCD0 Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD0_DOFF_OFFSET (0x000034) /* TCD0 Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD0_CITER_OFFSET (0x000036) /* TCD0 Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET (0x000038) /* TCD0 Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD0_CSR_OFFSET (0x00003c) /* TCD0 Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD0_BITER_OFFSET (0x00003e) /* TCD0 Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH1_CSR_OFFSET (0x004000) /* Channel 1 Control and Status Register (CH1_CSR) */
+#define S32K3XX_EDMA_CH1_ES_OFFSET (0x004004) /* Channel 1 Error Status Register (CH1_ES) */
+#define S32K3XX_EDMA_CH1_INT_OFFSET (0x004008) /* Channel 1 Interrupt Status Register (CH1_INT) */
+#define S32K3XX_EDMA_CH1_SBR_OFFSET (0x00400c) /* Channel 1 System Bus Register (CH1_SBR) */
+#define S32K3XX_EDMA_CH1_PRI_OFFSET (0x004010) /* Channel 1 Priority Register (CH1_PRI) */
+#define S32K3XX_EDMA_TCD1_SADDR_OFFSET (0x004020) /* TCD1 Source Address Register (TCD1_SADDR) */
+#define S32K3XX_EDMA_TCD1_SOFF_OFFSET (0x004024) /* TCD1 Signed Source Address Offset Register (TCD1_SOFF) */
+#define S32K3XX_EDMA_TCD1_ATTR_OFFSET (0x004026) /* TCD1 Transfer Attributes (TCD1_ATTR) */
+#define S32K3XX_EDMA_TCD1_NBYTES_OFFSET (0x004028) /* TCD1 Transfer Size (TCD1_NBYTES) */
+#define S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET (0x00402c) /* TCD1 Last Source Address Adjustment / Store DADDR Address Register (TCD1_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD1_DADDR_OFFSET (0x004030) /* TCD1 Destination Address Register (TCD1_DADDR) */
+#define S32K3XX_EDMA_TCD1_DOFF_OFFSET (0x004034) /* TCD1 Signed Destination Address Offset Register (TCD1_DOFF) */
+#define S32K3XX_EDMA_TCD1_CITER_OFFSET (0x004036) /* TCD1 Current Major Loop Count Register (TCD1_CITER) */
+#define S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET (0x004038) /* TCD1 Last Destination Address Adjustment / Scatter Gather Address Register (TCD1_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD1_CSR_OFFSET (0x00403c) /* TCD1 Control and Status Register (TCD1_CSR) */
+#define S32K3XX_EDMA_TCD1_BITER_OFFSET (0x00403e) /* TCD1 Beginning Major Loop Count Register (TCD1_BITER) */
+
+#define S32K3XX_EDMA_CH2_CSR_OFFSET (0x008000) /* Channel 2 Control and Status Register (CH2_CSR) */
+#define S32K3XX_EDMA_CH2_ES_OFFSET (0x008004) /* Channel 2 Error Status Register (CH2_ES) */
+#define S32K3XX_EDMA_CH2_INT_OFFSET (0x008008) /* Channel 2 Interrupt Status Register (CH2_INT) */
+#define S32K3XX_EDMA_CH2_SBR_OFFSET (0x00800c) /* Channel 2 System Bus Register (CH2_SBR) */
+#define S32K3XX_EDMA_CH2_PRI_OFFSET (0x008010) /* Channel 2 Priority Register (CH2_PRI) */
+#define S32K3XX_EDMA_TCD2_SADDR_OFFSET (0x008020) /* TCD2 Source Address Register (TCD2_SADDR) */
+#define S32K3XX_EDMA_TCD2_SOFF_OFFSET (0x008024) /* TCD2 Signed Source Address Offset Register (TCD2_SOFF) */
+#define S32K3XX_EDMA_TCD2_ATTR_OFFSET (0x008026) /* TCD2 Transfer Attributes (TCD2_ATTR) */
+#define S32K3XX_EDMA_TCD2_NBYTES_OFFSET (0x008028) /* TCD2 Transfer Size (TCD2_NBYTES) */
+#define S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET (0x00802c) /* TCD2 Last Source Address Adjustment / Store DADDR Address Register (TCD2_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD2_DADDR_OFFSET (0x008030) /* TCD2 Destination Address Register (TCD2_DADDR) */
+#define S32K3XX_EDMA_TCD2_DOFF_OFFSET (0x008034) /* TCD2 Signed Destination Address Offset Register (TCD2_DOFF) */
+#define S32K3XX_EDMA_TCD2_CITER_OFFSET (0x008036) /* TCD2 Current Major Loop Count Register (TCD2_CITER) */
+#define S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET (0x008038) /* TCD2 Last Destination Address Adjustment / Scatter Gather Address Register (TCD2_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD2_CSR_OFFSET (0x00803c) /* TCD2 Control and Status Register (TCD2_CSR) */
+#define S32K3XX_EDMA_TCD2_BITER_OFFSET (0x00803e) /* TCD2 Beginning Major Loop Count Register (TCD2_BITER) */
+
+#define S32K3XX_EDMA_CH3_CSR_OFFSET (0x00c000) /* Channel 3 Control and Status Register (CH3_CSR) */
+#define S32K3XX_EDMA_CH3_ES_OFFSET (0x00c004) /* Channel 3 Error Status Register (CH3_ES) */
+#define S32K3XX_EDMA_CH3_INT_OFFSET (0x00c008) /* Channel 3 Interrupt Status Register (CH3_INT) */
+#define S32K3XX_EDMA_CH3_SBR_OFFSET (0x00c00c) /* Channel 3 System Bus Register (CH3_SBR) */
+#define S32K3XX_EDMA_CH3_PRI_OFFSET (0x00c010) /* Channel 3 Priority Register (CH3_PRI) */
+#define S32K3XX_EDMA_TCD3_SADDR_OFFSET (0x00c020) /* TCD3 Source Address Register (TCD3_SADDR) */
+#define S32K3XX_EDMA_TCD3_SOFF_OFFSET (0x00c024) /* TCD3 Signed Source Address Offset Register (TCD3_SOFF) */
+#define S32K3XX_EDMA_TCD3_ATTR_OFFSET (0x00c026) /* TCD3 Transfer Attributes (TCD3_ATTR) */
+#define S32K3XX_EDMA_TCD3_NBYTES_OFFSET (0x00c028) /* TCD3 Transfer Size (TCD3_NBYTES) */
+#define S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET (0x00c02c) /* TCD3 Last Source Address Adjustment / Store DADDR Address Register (TCD3_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD3_DADDR_OFFSET (0x00c030) /* TCD3 Destination Address Register (TCD3_DADDR) */
+#define S32K3XX_EDMA_TCD3_DOFF_OFFSET (0x00c034) /* TCD3 Signed Destination Address Offset Register (TCD3_DOFF) */
+#define S32K3XX_EDMA_TCD3_CITER_OFFSET (0x00c036) /* TCD3 Current Major Loop Count Register (TCD3_CITER) */
+#define S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET (0x00c038) /* TCD3 Last Destination Address Adjustment / Scatter Gather Address Register (TCD3_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD3_CSR_OFFSET (0x00c03c) /* TCD3 Control and Status Register (TCD3_CSR) */
+#define S32K3XX_EDMA_TCD3_BITER_OFFSET (0x00c03e) /* TCD3 Beginning Major Loop Count Register (TCD3_BITER) */
+
+#define S32K3XX_EDMA_CH4_CSR_OFFSET (0x010000) /* Channel 4 Control and Status Register (CH4_CSR) */
+#define S32K3XX_EDMA_CH4_ES_OFFSET (0x010004) /* Channel 4 Error Status Register (CH4_ES) */
+#define S32K3XX_EDMA_CH4_INT_OFFSET (0x010008) /* Channel 4 Interrupt Status Register (CH4_INT) */
+#define S32K3XX_EDMA_CH4_SBR_OFFSET (0x01000c) /* Channel 4 System Bus Register (CH4_SBR) */
+#define S32K3XX_EDMA_CH4_PRI_OFFSET (0x010010) /* Channel 4 Priority Register (CH4_PRI) */
+#define S32K3XX_EDMA_TCD4_SADDR_OFFSET (0x010020) /* TCD4 Source Address Register (TCD4_SADDR) */
+#define S32K3XX_EDMA_TCD4_SOFF_OFFSET (0x010024) /* TCD4 Signed Source Address Offset Register (TCD4_SOFF) */
+#define S32K3XX_EDMA_TCD4_ATTR_OFFSET (0x010026) /* TCD4 Transfer Attributes (TCD4_ATTR) */
+#define S32K3XX_EDMA_TCD4_NBYTES_OFFSET (0x010028) /* TCD4 Transfer Size (TCD4_NBYTES) */
+#define S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET (0x01002c) /* TCD4 Last Source Address Adjustment / Store DADDR Address Register (TCD4_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD4_DADDR_OFFSET (0x010030) /* TCD4 Destination Address Register (TCD4_DADDR) */
+#define S32K3XX_EDMA_TCD4_DOFF_OFFSET (0x010034) /* TCD4 Signed Destination Address Offset Register (TCD4_DOFF) */
+#define S32K3XX_EDMA_TCD4_CITER_OFFSET (0x010036) /* TCD4 Current Major Loop Count Register (TCD4_CITER) */
+#define S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET (0x010038) /* TCD4 Last Destination Address Adjustment / Scatter Gather Address Register (TCD4_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD4_CSR_OFFSET (0x01003c) /* TCD4 Control and Status Register (TCD4_CSR) */
+#define S32K3XX_EDMA_TCD4_BITER_OFFSET (0x01003e) /* TCD4 Beginning Major Loop Count Register (TCD4_BITER) */
+
+#define S32K3XX_EDMA_CH5_CSR_OFFSET (0x014000) /* Channel 5 Control and Status Register (CH5_CSR) */
+#define S32K3XX_EDMA_CH5_ES_OFFSET (0x014004) /* Channel 5 Error Status Register (CH5_ES) */
+#define S32K3XX_EDMA_CH5_INT_OFFSET (0x014008) /* Channel 5 Interrupt Status Register (CH5_INT) */
+#define S32K3XX_EDMA_CH5_SBR_OFFSET (0x01400c) /* Channel 5 System Bus Register (CH5_SBR) */
+#define S32K3XX_EDMA_CH5_PRI_OFFSET (0x014010) /* Channel 5 Priority Register (CH5_PRI) */
+#define S32K3XX_EDMA_TCD5_SADDR_OFFSET (0x014020) /* TCD5 Source Address Register (TCD5_SADDR) */
+#define S32K3XX_EDMA_TCD5_SOFF_OFFSET (0x014024) /* TCD5 Signed Source Address Offset Register (TCD5_SOFF) */
+#define S32K3XX_EDMA_TCD5_ATTR_OFFSET (0x014026) /* TCD5 Transfer Attributes (TCD5_ATTR) */
+#define S32K3XX_EDMA_TCD5_NBYTES_OFFSET (0x014028) /* TCD5 Transfer Size (TCD5_NBYTES) */
+#define S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET (0x01402c) /* TCD5 Last Source Address Adjustment / Store DADDR Address Register (TCD5_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD5_DADDR_OFFSET (0x014030) /* TCD5 Destination Address Register (TCD5_DADDR) */
+#define S32K3XX_EDMA_TCD5_DOFF_OFFSET (0x014034) /* TCD5 Signed Destination Address Offset Register (TCD5_DOFF) */
+#define S32K3XX_EDMA_TCD5_CITER_OFFSET (0x014036) /* TCD5 Current Major Loop Count Register (TCD5_CITER) */
+#define S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET (0x014038) /* TCD5 Last Destination Address Adjustment / Scatter Gather Address Register (TCD5_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD5_CSR_OFFSET (0x01403c) /* TCD5 Control and Status Register (TCD5_CSR) */
+#define S32K3XX_EDMA_TCD5_BITER_OFFSET (0x01403e) /* TCD5 Beginning Major Loop Count Register (TCD5_BITER) */
+
+#define S32K3XX_EDMA_CH6_CSR_OFFSET (0x018000) /* Channel 6 Control and Status Register (CH6_CSR) */
+#define S32K3XX_EDMA_CH6_ES_OFFSET (0x018004) /* Channel 6 Error Status Register (CH6_ES) */
+#define S32K3XX_EDMA_CH6_INT_OFFSET (0x018008) /* Channel 6 Interrupt Status Register (CH6_INT) */
+#define S32K3XX_EDMA_CH6_SBR_OFFSET (0x01800c) /* Channel 6 System Bus Register (CH6_SBR) */
+#define S32K3XX_EDMA_CH6_PRI_OFFSET (0x018010) /* Channel 6 Priority Register (CH6_PRI) */
+#define S32K3XX_EDMA_TCD6_SADDR_OFFSET (0x018020) /* TCD6 Source Address Register (TCD6_SADDR) */
+#define S32K3XX_EDMA_TCD6_SOFF_OFFSET (0x018024) /* TCD6 Signed Source Address Offset Register (TCD6_SOFF) */
+#define S32K3XX_EDMA_TCD6_ATTR_OFFSET (0x018026) /* TCD6 Transfer Attributes (TCD6_ATTR) */
+#define S32K3XX_EDMA_TCD6_NBYTES_OFFSET (0x018028) /* TCD6 Transfer Size (TCD6_NBYTES) */
+#define S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET (0x01802c) /* TCD6 Last Source Address Adjustment / Store DADDR Address Register (TCD6_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD6_DADDR_OFFSET (0x018030) /* TCD6 Destination Address Register (TCD6_DADDR) */
+#define S32K3XX_EDMA_TCD6_DOFF_OFFSET (0x018034) /* TCD6 Signed Destination Address Offset Register (TCD6_DOFF) */
+#define S32K3XX_EDMA_TCD6_CITER_OFFSET (0x018036) /* TCD6 Current Major Loop Count Register (TCD6_CITER) */
+#define S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET (0x018038) /* TCD6 Last Destination Address Adjustment / Scatter Gather Address Register (TCD6_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD6_CSR_OFFSET (0x01803c) /* TCD6 Control and Status Register (TCD6_CSR) */
+#define S32K3XX_EDMA_TCD6_BITER_OFFSET (0x01803e) /* TCD6 Beginning Major Loop Count Register (TCD6_BITER) */
+
+#define S32K3XX_EDMA_CH7_CSR_OFFSET (0x01c000) /* Channel 7 Control and Status Register (CH7_CSR) */
+#define S32K3XX_EDMA_CH7_ES_OFFSET (0x01c004) /* Channel 7 Error Status Register (CH7_ES) */
+#define S32K3XX_EDMA_CH7_INT_OFFSET (0x01c008) /* Channel 7 Interrupt Status Register (CH7_INT) */
+#define S32K3XX_EDMA_CH7_SBR_OFFSET (0x01c00c) /* Channel 7 System Bus Register (CH7_SBR) */
+#define S32K3XX_EDMA_CH7_PRI_OFFSET (0x01c010) /* Channel 7 Priority Register (CH7_PRI) */
+#define S32K3XX_EDMA_TCD7_SADDR_OFFSET (0x01c020) /* TCD7 Source Address Register (TCD7_SADDR) */
+#define S32K3XX_EDMA_TCD7_SOFF_OFFSET (0x01c024) /* TCD7 Signed Source Address Offset Register (TCD7_SOFF) */
+#define S32K3XX_EDMA_TCD7_ATTR_OFFSET (0x01c026) /* TCD7 Transfer Attributes (TCD7_ATTR) */
+#define S32K3XX_EDMA_TCD7_NBYTES_OFFSET (0x01c028) /* TCD7 Transfer Size (TCD7_NBYTES) */
+#define S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET (0x01c02c) /* TCD7 Last Source Address Adjustment / Store DADDR Address Register (TCD7_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD7_DADDR_OFFSET (0x01c030) /* TCD7 Destination Address Register (TCD7_DADDR) */
+#define S32K3XX_EDMA_TCD7_DOFF_OFFSET (0x01c034) /* TCD7 Signed Destination Address Offset Register (TCD7_DOFF) */
+#define S32K3XX_EDMA_TCD7_CITER_OFFSET (0x01c036) /* TCD7 Current Major Loop Count Register (TCD7_CITER) */
+#define S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET (0x01c038) /* TCD7 Last Destination Address Adjustment / Scatter Gather Address Register (TCD7_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD7_CSR_OFFSET (0x01c03c) /* TCD7 Control and Status Register (TCD7_CSR) */
+#define S32K3XX_EDMA_TCD7_BITER_OFFSET (0x01c03e) /* TCD7 Beginning Major Loop Count Register (TCD7_BITER) */
+
+#define S32K3XX_EDMA_CH8_CSR_OFFSET (0x020000) /* Channel 8 Control and Status Register (CH8_CSR) */
+#define S32K3XX_EDMA_CH8_ES_OFFSET (0x020004) /* Channel 8 Error Status Register (CH8_ES) */
+#define S32K3XX_EDMA_CH8_INT_OFFSET (0x020008) /* Channel 8 Interrupt Status Register (CH8_INT) */
+#define S32K3XX_EDMA_CH8_SBR_OFFSET (0x02000c) /* Channel 8 System Bus Register (CH8_SBR) */
+#define S32K3XX_EDMA_CH8_PRI_OFFSET (0x020010) /* Channel 8 Priority Register (CH8_PRI) */
+#define S32K3XX_EDMA_TCD8_SADDR_OFFSET (0x020020) /* TCD8 Source Address Register (TCD8_SADDR) */
+#define S32K3XX_EDMA_TCD8_SOFF_OFFSET (0x020024) /* TCD8 Signed Source Address Offset Register (TCD8_SOFF) */
+#define S32K3XX_EDMA_TCD8_ATTR_OFFSET (0x020026) /* TCD8 Transfer Attributes (TCD8_ATTR) */
+#define S32K3XX_EDMA_TCD8_NBYTES_OFFSET (0x020028) /* TCD8 Transfer Size (TCD8_NBYTES) */
+#define S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET (0x02002c) /* TCD8 Last Source Address Adjustment / Store DADDR Address Register (TCD8_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD8_DADDR_OFFSET (0x020030) /* TCD8 Destination Address Register (TCD8_DADDR) */
+#define S32K3XX_EDMA_TCD8_DOFF_OFFSET (0x020034) /* TCD8 Signed Destination Address Offset Register (TCD8_DOFF) */
+#define S32K3XX_EDMA_TCD8_CITER_OFFSET (0x020036) /* TCD8 Current Major Loop Count Register (TCD8_CITER) */
+#define S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET (0x020038) /* TCD8 Last Destination Address Adjustment / Scatter Gather Address Register (TCD8_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD8_CSR_OFFSET (0x02003c) /* TCD8 Control and Status Register (TCD8_CSR) */
+#define S32K3XX_EDMA_TCD8_BITER_OFFSET (0x02003e) /* TCD8 Beginning Major Loop Count Register (TCD8_BITER) */
+
+#define S32K3XX_EDMA_CH9_CSR_OFFSET (0x024000) /* Channel 9 Control and Status Register (CH9_CSR) */
+#define S32K3XX_EDMA_CH9_ES_OFFSET (0x024004) /* Channel 9 Error Status Register (CH9_ES) */
+#define S32K3XX_EDMA_CH9_INT_OFFSET (0x024008) /* Channel 9 Interrupt Status Register (CH9_INT) */
+#define S32K3XX_EDMA_CH9_SBR_OFFSET (0x02400c) /* Channel 9 System Bus Register (CH9_SBR) */
+#define S32K3XX_EDMA_CH9_PRI_OFFSET (0x024010) /* Channel 9 Priority Register (CH9_PRI) */
+#define S32K3XX_EDMA_TCD9_SADDR_OFFSET (0x024020) /* TCD9 Source Address Register (TCD9_SADDR) */
+#define S32K3XX_EDMA_TCD9_SOFF_OFFSET (0x024024) /* TCD9 Signed Source Address Offset Register (TCD9_SOFF) */
+#define S32K3XX_EDMA_TCD9_ATTR_OFFSET (0x024026) /* TCD9 Transfer Attributes (TCD9_ATTR) */
+#define S32K3XX_EDMA_TCD9_NBYTES_OFFSET (0x024028) /* TCD9 Transfer Size (TCD9_NBYTES) */
+#define S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET (0x02402c) /* TCD9 Last Source Address Adjustment / Store DADDR Address Register (TCD9_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD9_DADDR_OFFSET (0x024030) /* TCD9 Destination Address Register (TCD9_DADDR) */
+#define S32K3XX_EDMA_TCD9_DOFF_OFFSET (0x024034) /* TCD9 Signed Destination Address Offset Register (TCD9_DOFF) */
+#define S32K3XX_EDMA_TCD9_CITER_OFFSET (0x024036) /* TCD9 Current Major Loop Count Register (TCD9_CITER) */
+#define S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET (0x024038) /* TCD9 Last Destination Address Adjustment / Scatter Gather Address Register (TCD9_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD9_CSR_OFFSET (0x02403c) /* TCD9 Control and Status Register (TCD9_CSR) */
+#define S32K3XX_EDMA_TCD9_BITER_OFFSET (0x02403e) /* TCD9 Beginning Major Loop Count Register (TCD9_BITER) */
+
+#define S32K3XX_EDMA_CH10_CSR_OFFSET (0x028000) /* Channel 10 Control and Status Register (CH10_CSR) */
+#define S32K3XX_EDMA_CH10_ES_OFFSET (0x028004) /* Channel 10 Error Status Register (CH10_ES) */
+#define S32K3XX_EDMA_CH10_INT_OFFSET (0x028008) /* Channel 10 Interrupt Status Register (CH10_INT) */
+#define S32K3XX_EDMA_CH10_SBR_OFFSET (0x02800c) /* Channel 10 System Bus Register (CH10_SBR) */
+#define S32K3XX_EDMA_CH10_PRI_OFFSET (0x028010) /* Channel 10 Priority Register (CH10_PRI) */
+#define S32K3XX_EDMA_TCD10_SADDR_OFFSET (0x028020) /* TCD10 Source Address Register (TCD10_SADDR) */
+#define S32K3XX_EDMA_TCD10_SOFF_OFFSET (0x028024) /* TCD10 Signed Source Address Offset Register (TCD10_SOFF) */
+#define S32K3XX_EDMA_TCD10_ATTR_OFFSET (0x028026) /* TCD10 Transfer Attributes (TCD10_ATTR) */
+#define S32K3XX_EDMA_TCD10_NBYTES_OFFSET (0x028028) /* TCD10 Transfer Size (TCD10_NBYTES) */
+#define S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET (0x02802c) /* TCD10 Last Source Address Adjustment / Store DADDR Address Register (TCD10_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD10_DADDR_OFFSET (0x028030) /* TCD10 Destination Address Register (TCD10_DADDR) */
+#define S32K3XX_EDMA_TCD10_DOFF_OFFSET (0x028034) /* TCD10 Signed Destination Address Offset Register (TCD10_DOFF) */
+#define S32K3XX_EDMA_TCD10_CITER_OFFSET (0x028036) /* TCD10 Current Major Loop Count Register (TCD10_CITER) */
+#define S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET (0x028038) /* TCD10 Last Destination Address Adjustment / Scatter Gather Address Register (TCD10_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD10_CSR_OFFSET (0x02803c) /* TCD10 Control and Status Register (TCD10_CSR) */
+#define S32K3XX_EDMA_TCD10_BITER_OFFSET (0x02803e) /* TCD10 Beginning Major Loop Count Register (TCD10_BITER) */
+#define S32K3XX_EDMA_CH11_CSR_OFFSET (0x02c000) /* Channel 11 Control and Status Register (CH11_CSR) */
+#define S32K3XX_EDMA_CH11_ES_OFFSET (0x02c004) /* Channel 11 Error Status Register (CH11_ES) */
+#define S32K3XX_EDMA_CH11_INT_OFFSET (0x02c008) /* Channel 11 Interrupt Status Register (CH11_INT) */
+#define S32K3XX_EDMA_CH11_SBR_OFFSET (0x02c00c) /* Channel 11 System Bus Register (CH11_SBR) */
+#define S32K3XX_EDMA_CH11_PRI_OFFSET (0x02c010) /* Channel 11 Priority Register (CH11_PRI) */
+#define S32K3XX_EDMA_TCD11_SADDR_OFFSET (0x02c020) /* TCD11 Source Address Register (TCD11_SADDR) */
+#define S32K3XX_EDMA_TCD11_SOFF_OFFSET (0x02c024) /* TCD11 Signed Source Address Offset Register (TCD11_SOFF) */
+#define S32K3XX_EDMA_TCD11_ATTR_OFFSET (0x02c026) /* TCD11 Transfer Attributes (TCD11_ATTR) */
+#define S32K3XX_EDMA_TCD11_NBYTES_OFFSET (0x02c028) /* TCD11 Transfer Size (TCD11_NBYTES) */
+#define S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET (0x02c02c) /* TCD11 Last Source Address Adjustment / Store DADDR Address Register (TCD11_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD11_DADDR_OFFSET (0x02c030) /* TCD11 Destination Address Register (TCD11_DADDR) */
+#define S32K3XX_EDMA_TCD11_DOFF_OFFSET (0x02c034) /* TCD11 Signed Destination Address Offset Register (TCD11_DOFF) */
+#define S32K3XX_EDMA_TCD11_CITER_OFFSET (0x02c036) /* TCD11 Current Major Loop Count Register (TCD11_CITER) */
+#define S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET (0x02c038) /* TCD11 Last Destination Address Adjustment / Scatter Gather Address Register (TCD11_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD11_CSR_OFFSET (0x02c03c) /* TCD11 Control and Status Register (TCD11_CSR) */
+#define S32K3XX_EDMA_TCD11_BITER_OFFSET (0x02c03e) /* TCD11 Beginning Major Loop Count Register (TCD11_BITER) */
+
+#define S32K3XX_EDMA_CH12_CSR_OFFSET (0x200000) /* Channel 12 Control and Status Register (CH12_CSR) */
+#define S32K3XX_EDMA_CH12_ES_OFFSET (0x200004) /* Channel 12 Error Status Register (CH12_ES) */
+#define S32K3XX_EDMA_CH12_INT_OFFSET (0x200008) /* Channel 12 Interrupt Status Register (CH12_INT) */
+#define S32K3XX_EDMA_CH12_SBR_OFFSET (0x20000c) /* Channel 12 System Bus Register (CH12_SBR) */
+#define S32K3XX_EDMA_CH12_PRI_OFFSET (0x200010) /* Channel 12 Priority Register (CH12_PRI) */
+#define S32K3XX_EDMA_TCD12_SADDR_OFFSET (0x200020) /* TCD12 Source Address Register (TCD12_SADDR) */
+#define S32K3XX_EDMA_TCD12_SOFF_OFFSET (0x200024) /* TCD12 Signed Source Address Offset Register (TCD12_SOFF) */
+#define S32K3XX_EDMA_TCD12_ATTR_OFFSET (0x200026) /* TCD12 Transfer Attributes (TCD12_ATTR) */
+#define S32K3XX_EDMA_TCD12_NBYTES_OFFSET (0x200028) /* TCD12 Transfer Size (TCD12_NBYTES) */
+#define S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET (0x20002c) /* TCD12 Last Source Address Adjustment / Store DADDR Address Register (TCD12_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD12_DADDR_OFFSET (0x200030) /* TCD12 Destination Address Register (TCD12_DADDR) */
+#define S32K3XX_EDMA_TCD12_DOFF_OFFSET (0x200034) /* TCD12 Signed Destination Address Offset Register (TCD12_DOFF) */
+#define S32K3XX_EDMA_TCD12_CITER_OFFSET (0x200036) /* TCD12 Current Major Loop Count Register (TCD12_CITER) */
+#define S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET (0x200038) /* TCD12 Last Destination Address Adjustment / Scatter Gather Address Register (TCD12_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD12_CSR_OFFSET (0x20003c) /* TCD12 Control and Status Register (TCD12_CSR) */
+#define S32K3XX_EDMA_TCD12_BITER_OFFSET (0x20003e) /* TCD12 Beginning Major Loop Count Register (TCD12_BITER) */
+
+#define S32K3XX_EDMA_CH13_CSR_OFFSET (0x204000) /* Channel 13 Control and Status Register (CH13_CSR) */
+#define S32K3XX_EDMA_CH13_ES_OFFSET (0x204004) /* Channel 13 Error Status Register (CH13_ES) */
+#define S32K3XX_EDMA_CH13_INT_OFFSET (0x204008) /* Channel 13 Interrupt Status Register (CH13_INT) */
+#define S32K3XX_EDMA_CH13_SBR_OFFSET (0x20400c) /* Channel 13 System Bus Register (CH13_SBR) */
+#define S32K3XX_EDMA_CH13_PRI_OFFSET (0x204010) /* Channel 13 Priority Register (CH13_PRI) */
+#define S32K3XX_EDMA_TCD13_SADDR_OFFSET (0x204020) /* TCD13 Source Address Register (TCD13_SADDR) */
+#define S32K3XX_EDMA_TCD13_SOFF_OFFSET (0x204024) /* TCD13 Signed Source Address Offset Register (TCD13_SOFF) */
+#define S32K3XX_EDMA_TCD13_ATTR_OFFSET (0x204026) /* TCD13 Transfer Attributes (TCD13_ATTR) */
+#define S32K3XX_EDMA_TCD13_NBYTES_OFFSET (0x204028) /* TCD13 Transfer Size (TCD13_NBYTES) */
+#define S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET (0x20402c) /* TCD13 Last Source Address Adjustment / Store DADDR Address Register (TCD13_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD13_DADDR_OFFSET (0x204030) /* TCD13 Destination Address Register (TCD13_DADDR) */
+#define S32K3XX_EDMA_TCD13_DOFF_OFFSET (0x204034) /* TCD13 Signed Destination Address Offset Register (TCD13_DOFF) */
+#define S32K3XX_EDMA_TCD13_CITER_OFFSET (0x204036) /* TCD13 Current Major Loop Count Register (TCD13_CITER) */
+#define S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET (0x204038) /* TCD13 Last Destination Address Adjustment / Scatter Gather Address Register (TCD13_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD13_CSR_OFFSET (0x20403c) /* TCD13 Control and Status Register (TCD13_CSR) */
+#define S32K3XX_EDMA_TCD13_BITER_OFFSET (0x20403e) /* TCD13 Beginning Major Loop Count Register (TCD13_BITER) */
+
+#define S32K3XX_EDMA_CH14_CSR_OFFSET (0x208000) /* Channel 14 Control and Status Register (CH14_CSR) */
+#define S32K3XX_EDMA_CH14_ES_OFFSET (0x208004) /* Channel 14 Error Status Register (CH14_ES) */
+#define S32K3XX_EDMA_CH14_INT_OFFSET (0x208008) /* Channel 14 Interrupt Status Register (CH14_INT) */
+#define S32K3XX_EDMA_CH14_SBR_OFFSET (0x20800c) /* Channel 14 System Bus Register (CH14_SBR) */
+#define S32K3XX_EDMA_CH14_PRI_OFFSET (0x208010) /* Channel 14 Priority Register (CH14_PRI) */
+#define S32K3XX_EDMA_TCD14_SADDR_OFFSET (0x208020) /* TCD14 Source Address Register (TCD14_SADDR) */
+#define S32K3XX_EDMA_TCD14_SOFF_OFFSET (0x208024) /* TCD14 Signed Source Address Offset Register (TCD14_SOFF) */
+#define S32K3XX_EDMA_TCD14_ATTR_OFFSET (0x208026) /* TCD14 Transfer Attributes (TCD14_ATTR) */
+#define S32K3XX_EDMA_TCD14_NBYTES_OFFSET (0x208028) /* TCD14 Transfer Size (TCD14_NBYTES) */
+#define S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET (0x20802c) /* TCD14 Last Source Address Adjustment / Store DADDR Address Register (TCD14_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD14_DADDR_OFFSET (0x208030) /* TCD14 Destination Address Register (TCD14_DADDR) */
+#define S32K3XX_EDMA_TCD14_DOFF_OFFSET (0x208034) /* TCD14 Signed Destination Address Offset Register (TCD14_DOFF) */
+#define S32K3XX_EDMA_TCD14_CITER_OFFSET (0x208036) /* TCD14 Current Major Loop Count Register (TCD14_CITER) */
+#define S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET (0x208038) /* TCD14 Last Destination Address Adjustment / Scatter Gather Address Register (TCD14_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD14_CSR_OFFSET (0x20803c) /* TCD14 Control and Status Register (TCD14_CSR) */
+#define S32K3XX_EDMA_TCD14_BITER_OFFSET (0x20803e) /* TCD14 Beginning Major Loop Count Register (TCD14_BITER) */
+
+#define S32K3XX_EDMA_CH15_CSR_OFFSET (0x20c000) /* Channel 15 Control and Status Register (CH15_CSR) */
+#define S32K3XX_EDMA_CH15_ES_OFFSET (0x20c004) /* Channel 15 Error Status Register (CH15_ES) */
+#define S32K3XX_EDMA_CH15_INT_OFFSET (0x20c008) /* Channel 15 Interrupt Status Register (CH15_INT) */
+#define S32K3XX_EDMA_CH15_SBR_OFFSET (0x20c00c) /* Channel 15 System Bus Register (CH15_SBR) */
+#define S32K3XX_EDMA_CH15_PRI_OFFSET (0x20c010) /* Channel 15 Priority Register (CH15_PRI) */
+#define S32K3XX_EDMA_TCD15_SADDR_OFFSET (0x20c020) /* TCD15 Source Address Register (TCD15_SADDR) */
+#define S32K3XX_EDMA_TCD15_SOFF_OFFSET (0x20c024) /* TCD15 Signed Source Address Offset Register (TCD15_SOFF) */
+#define S32K3XX_EDMA_TCD15_ATTR_OFFSET (0x20c026) /* TCD15 Transfer Attributes (TCD15_ATTR) */
+#define S32K3XX_EDMA_TCD15_NBYTES_OFFSET (0x20c028) /* TCD15 Transfer Size (TCD15_NBYTES) */
+#define S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET (0x20c02c) /* TCD15 Last Source Address Adjustment / Store DADDR Address Register (TCD15_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD15_DADDR_OFFSET (0x20c030) /* TCD15 Destination Address Register (TCD15_DADDR) */
+#define S32K3XX_EDMA_TCD15_DOFF_OFFSET (0x20c034) /* TCD15 Signed Destination Address Offset Register (TCD15_DOFF) */
+#define S32K3XX_EDMA_TCD15_CITER_OFFSET (0x20c036) /* TCD15 Current Major Loop Count Register (TCD15_CITER) */
+#define S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET (0x20c038) /* TCD15 Last Destination Address Adjustment / Scatter Gather Address Register (TCD15_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD15_CSR_OFFSET (0x20c03c) /* TCD15 Control and Status Register (TCD15_CSR) */
+#define S32K3XX_EDMA_TCD15_BITER_OFFSET (0x20c03e) /* TCD15 Beginning Major Loop Count Register (TCD15_BITER) */
+
+#define S32K3XX_EDMA_CH16_CSR_OFFSET (0x210000) /* Channel 16 Control and Status Register (CH16_CSR) */
+#define S32K3XX_EDMA_CH16_ES_OFFSET (0x210004) /* Channel 16 Error Status Register (CH16_ES) */
+#define S32K3XX_EDMA_CH16_INT_OFFSET (0x210008) /* Channel 16 Interrupt Status Register (CH16_INT) */
+#define S32K3XX_EDMA_CH16_SBR_OFFSET (0x21000c) /* Channel 16 System Bus Register (CH16_SBR) */
+#define S32K3XX_EDMA_CH16_PRI_OFFSET (0x210010) /* Channel 16 Priority Register (CH16_PRI) */
+#define S32K3XX_EDMA_TCD16_SADDR_OFFSET (0x210020) /* TCD16 Source Address Register (TCD16_SADDR) */
+#define S32K3XX_EDMA_TCD16_SOFF_OFFSET (0x210024) /* TCD16 Signed Source Address Offset Register (TCD16_SOFF) */
+#define S32K3XX_EDMA_TCD16_ATTR_OFFSET (0x210026) /* TCD16 Transfer Attributes (TCD16_ATTR) */
+#define S32K3XX_EDMA_TCD16_NBYTES_OFFSET (0x210028) /* TCD16 Transfer Size (TCD16_NBYTES) */
+#define S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET (0x21002c) /* TCD16 Last Source Address Adjustment / Store DADDR Address Register (TCD16_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD16_DADDR_OFFSET (0x210030) /* TCD16 Destination Address Register (TCD16_DADDR) */
+#define S32K3XX_EDMA_TCD16_DOFF_OFFSET (0x210034) /* TCD16 Signed Destination Address Offset Register (TCD16_DOFF) */
+#define S32K3XX_EDMA_TCD16_CITER_OFFSET (0x210036) /* TCD16 Current Major Loop Count Register (TCD16_CITER) */
+#define S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET (0x210038) /* TCD16 Last Destination Address Adjustment / Scatter Gather Address Register (TCD16_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD16_CSR_OFFSET (0x21003c) /* TCD16 Control and Status Register (TCD16_CSR) */
+#define S32K3XX_EDMA_TCD16_BITER_OFFSET (0x21003e) /* TCD16 Beginning Major Loop Count Register (TCD16_BITER) */
+
+#define S32K3XX_EDMA_CH17_CSR_OFFSET (0x214000) /* Channel 17 Control and Status Register (CH17_CSR) */
+#define S32K3XX_EDMA_CH17_ES_OFFSET (0x214004) /* Channel 17 Error Status Register (CH17_ES) */
+#define S32K3XX_EDMA_CH17_INT_OFFSET (0x214008) /* Channel 17 Interrupt Status Register (CH17_INT) */
+#define S32K3XX_EDMA_CH17_SBR_OFFSET (0x21400c) /* Channel 17 System Bus Register (CH17_SBR) */
+#define S32K3XX_EDMA_CH17_PRI_OFFSET (0x214010) /* Channel 17 Priority Register (CH17_PRI) */
+#define S32K3XX_EDMA_TCD17_SADDR_OFFSET (0x214020) /* TCD17 Source Address Register (TCD17_SADDR) */
+#define S32K3XX_EDMA_TCD17_SOFF_OFFSET (0x214024) /* TCD17 Signed Source Address Offset Register (TCD17_SOFF) */
+#define S32K3XX_EDMA_TCD17_ATTR_OFFSET (0x214026) /* TCD17 Transfer Attributes (TCD17_ATTR) */
+#define S32K3XX_EDMA_TCD17_NBYTES_OFFSET (0x214028) /* TCD17 Transfer Size (TCD17_NBYTES) */
+#define S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET (0x21402c) /* TCD17 Last Source Address Adjustment / Store DADDR Address Register (TCD17_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD17_DADDR_OFFSET (0x214030) /* TCD17 Destination Address Register (TCD17_DADDR) */
+#define S32K3XX_EDMA_TCD17_DOFF_OFFSET (0x214034) /* TCD17 Signed Destination Address Offset Register (TCD17_DOFF) */
+#define S32K3XX_EDMA_TCD17_CITER_OFFSET (0x214036) /* TCD17 Current Major Loop Count Register (TCD17_CITER) */
+#define S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET (0x214038) /* TCD17 Last Destination Address Adjustment / Scatter Gather Address Register (TCD17_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD17_CSR_OFFSET (0x21403c) /* TCD17 Control and Status Register (TCD17_CSR) */
+#define S32K3XX_EDMA_TCD17_BITER_OFFSET (0x21403e) /* TCD17 Beginning Major Loop Count Register (TCD17_BITER) */
+
+#define S32K3XX_EDMA_CH18_CSR_OFFSET (0x218000) /* Channel 18 Control and Status Register (CH18_CSR) */
+#define S32K3XX_EDMA_CH18_ES_OFFSET (0x218004) /* Channel 18 Error Status Register (CH18_ES) */
+#define S32K3XX_EDMA_CH18_INT_OFFSET (0x218008) /* Channel 18 Interrupt Status Register (CH18_INT) */
+#define S32K3XX_EDMA_CH18_SBR_OFFSET (0x21800c) /* Channel 18 System Bus Register (CH18_SBR) */
+#define S32K3XX_EDMA_CH18_PRI_OFFSET (0x218010) /* Channel 18 Priority Register (CH18_PRI) */
+#define S32K3XX_EDMA_TCD18_SADDR_OFFSET (0x218020) /* TCD18 Source Address Register (TCD18_SADDR) */
+#define S32K3XX_EDMA_TCD18_SOFF_OFFSET (0x218024) /* TCD18 Signed Source Address Offset Register (TCD18_SOFF) */
+#define S32K3XX_EDMA_TCD18_ATTR_OFFSET (0x218026) /* TCD18 Transfer Attributes (TCD18_ATTR) */
+#define S32K3XX_EDMA_TCD18_NBYTES_OFFSET (0x218028) /* TCD18 Transfer Size (TCD18_NBYTES) */
+#define S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET (0x21802c) /* TCD18 Last Source Address Adjustment / Store DADDR Address Register (TCD18_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD18_DADDR_OFFSET (0x218030) /* TCD18 Destination Address Register (TCD18_DADDR) */
+#define S32K3XX_EDMA_TCD18_DOFF_OFFSET (0x218034) /* TCD18 Signed Destination Address Offset Register (TCD18_DOFF) */
+#define S32K3XX_EDMA_TCD18_CITER_OFFSET (0x218036) /* TCD18 Current Major Loop Count Register (TCD18_CITER) */
+#define S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET (0x218038) /* TCD18 Last Destination Address Adjustment / Scatter Gather Address Register (TCD18_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD18_CSR_OFFSET (0x21803c) /* TCD18 Control and Status Register (TCD18_CSR) */
+#define S32K3XX_EDMA_TCD18_BITER_OFFSET (0x21803e) /* TCD18 Beginning Major Loop Count Register (TCD18_BITER) */
+
+#define S32K3XX_EDMA_CH19_CSR_OFFSET (0x21c000) /* Channel 19 Control and Status Register (CH19_CSR) */
+#define S32K3XX_EDMA_CH19_ES_OFFSET (0x21c004) /* Channel 19 Error Status Register (CH19_ES) */
+#define S32K3XX_EDMA_CH19_INT_OFFSET (0x21c008) /* Channel 19 Interrupt Status Register (CH19_INT) */
+#define S32K3XX_EDMA_CH19_SBR_OFFSET (0x21c00c) /* Channel 19 System Bus Register (CH19_SBR) */
+#define S32K3XX_EDMA_CH19_PRI_OFFSET (0x21c010) /* Channel 19 Priority Register (CH19_PRI) */
+#define S32K3XX_EDMA_TCD19_SADDR_OFFSET (0x21c020) /* TCD19 Source Address Register (TCD19_SADDR) */
+#define S32K3XX_EDMA_TCD19_SOFF_OFFSET (0x21c024) /* TCD19 Signed Source Address Offset Register (TCD19_SOFF) */
+#define S32K3XX_EDMA_TCD19_ATTR_OFFSET (0x21c026) /* TCD19 Transfer Attributes (TCD19_ATTR) */
+#define S32K3XX_EDMA_TCD19_NBYTES_OFFSET (0x21c028) /* TCD19 Transfer Size (TCD19_NBYTES) */
+#define S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET (0x21c02c) /* TCD19 Last Source Address Adjustment / Store DADDR Address Register (TCD19_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD19_DADDR_OFFSET (0x21c030) /* TCD19 Destination Address Register (TCD19_DADDR) */
+#define S32K3XX_EDMA_TCD19_DOFF_OFFSET (0x21c034) /* TCD19 Signed Destination Address Offset Register (TCD19_DOFF) */
+#define S32K3XX_EDMA_TCD19_CITER_OFFSET (0x21c036) /* TCD19 Current Major Loop Count Register (TCD19_CITER) */
+#define S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET (0x21c038) /* TCD19 Last Destination Address Adjustment / Scatter Gather Address Register (TCD19_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD19_CSR_OFFSET (0x21c03c) /* TCD19 Control and Status Register (TCD19_CSR) */
+#define S32K3XX_EDMA_TCD19_BITER_OFFSET (0x21c03e) /* TCD19 Beginning Major Loop Count Register (TCD19_BITER) */
+
+#define S32K3XX_EDMA_CH20_CSR_OFFSET (0x220000) /* Channel 20 Control and Status Register (CH20_CSR) */
+#define S32K3XX_EDMA_CH20_ES_OFFSET (0x220004) /* Channel 20 Error Status Register (CH20_ES) */
+#define S32K3XX_EDMA_CH20_INT_OFFSET (0x220008) /* Channel 20 Interrupt Status Register (CH20_INT) */
+#define S32K3XX_EDMA_CH20_SBR_OFFSET (0x22000c) /* Channel 20 System Bus Register (CH20_SBR) */
+#define S32K3XX_EDMA_CH20_PRI_OFFSET (0x220010) /* Channel 20 Priority Register (CH20_PRI) */
+#define S32K3XX_EDMA_TCD20_SADDR_OFFSET (0x220020) /* TCD20 Source Address Register (TCD20_SADDR) */
+#define S32K3XX_EDMA_TCD20_SOFF_OFFSET (0x220024) /* TCD20 Signed Source Address Offset Register (TCD20_SOFF) */
+#define S32K3XX_EDMA_TCD20_ATTR_OFFSET (0x220026) /* TCD20 Transfer Attributes (TCD20_ATTR) */
+#define S32K3XX_EDMA_TCD20_NBYTES_OFFSET (0x220028) /* TCD20 Transfer Size (TCD20_NBYTES) */
+#define S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET (0x22002c) /* TCD20 Last Source Address Adjustment / Store DADDR Address Register (TCD20_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD20_DADDR_OFFSET (0x220030) /* TCD20 Destination Address Register (TCD20_DADDR) */
+#define S32K3XX_EDMA_TCD20_DOFF_OFFSET (0x220034) /* TCD20 Signed Destination Address Offset Register (TCD20_DOFF) */
+#define S32K3XX_EDMA_TCD20_CITER_OFFSET (0x220036) /* TCD20 Current Major Loop Count Register (TCD20_CITER) */
+#define S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET (0x220038) /* TCD20 Last Destination Address Adjustment / Scatter Gather Address Register (TCD20_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD20_CSR_OFFSET (0x22003c) /* TCD20 Control and Status Register (TCD20_CSR) */
+#define S32K3XX_EDMA_TCD20_BITER_OFFSET (0x22003e) /* TCD20 Beginning Major Loop Count Register (TCD20_BITER) */
+
+#define S32K3XX_EDMA_CH21_CSR_OFFSET (0x224000) /* Channel 21 Control and Status Register (CH21_CSR) */
+#define S32K3XX_EDMA_CH21_ES_OFFSET (0x224004) /* Channel 21 Error Status Register (CH21_ES) */
+#define S32K3XX_EDMA_CH21_INT_OFFSET (0x224008) /* Channel 21 Interrupt Status Register (CH21_INT) */
+#define S32K3XX_EDMA_CH21_SBR_OFFSET (0x22400c) /* Channel 21 System Bus Register (CH21_SBR) */
+#define S32K3XX_EDMA_CH21_PRI_OFFSET (0x224010) /* Channel 21 Priority Register (CH21_PRI) */
+#define S32K3XX_EDMA_TCD21_SADDR_OFFSET (0x224020) /* TCD21 Source Address Register (TCD21_SADDR) */
+#define S32K3XX_EDMA_TCD21_SOFF_OFFSET (0x224024) /* TCD21 Signed Source Address Offset Register (TCD21_SOFF) */
+#define S32K3XX_EDMA_TCD21_ATTR_OFFSET (0x224026) /* TCD21 Transfer Attributes (TCD21_ATTR) */
+#define S32K3XX_EDMA_TCD21_NBYTES_OFFSET (0x224028) /* TCD21 Transfer Size (TCD21_NBYTES) */
+#define S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET (0x22402c) /* TCD21 Last Source Address Adjustment / Store DADDR Address Register (TCD21_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD21_DADDR_OFFSET (0x224030) /* TCD21 Destination Address Register (TCD21_DADDR) */
+#define S32K3XX_EDMA_TCD21_DOFF_OFFSET (0x224034) /* TCD21 Signed Destination Address Offset Register (TCD21_DOFF) */
+#define S32K3XX_EDMA_TCD21_CITER_OFFSET (0x224036) /* TCD21 Current Major Loop Count Register (TCD21_CITER) */
+#define S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET (0x224038) /* TCD21 Last Destination Address Adjustment / Scatter Gather Address Register (TCD21_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD21_CSR_OFFSET (0x22403c) /* TCD21 Control and Status Register (TCD21_CSR) */
+#define S32K3XX_EDMA_TCD21_BITER_OFFSET (0x22403e) /* TCD21 Beginning Major Loop Count Register (TCD21_BITER) */
+
+#define S32K3XX_EDMA_CH22_CSR_OFFSET (0x228000) /* Channel 22 Control and Status Register (CH22_CSR) */
+#define S32K3XX_EDMA_CH22_ES_OFFSET (0x228004) /* Channel 22 Error Status Register (CH22_ES) */
+#define S32K3XX_EDMA_CH22_INT_OFFSET (0x228008) /* Channel 22 Interrupt Status Register (CH22_INT) */
+#define S32K3XX_EDMA_CH22_SBR_OFFSET (0x22800c) /* Channel 22 System Bus Register (CH22_SBR) */
+#define S32K3XX_EDMA_CH22_PRI_OFFSET (0x228010) /* Channel 22 Priority Register (CH22_PRI) */
+#define S32K3XX_EDMA_TCD22_SADDR_OFFSET (0x228020) /* TCD22 Source Address Register (TCD22_SADDR) */
+#define S32K3XX_EDMA_TCD22_SOFF_OFFSET (0x228024) /* TCD22 Signed Source Address Offset Register (TCD22_SOFF) */
+#define S32K3XX_EDMA_TCD22_ATTR_OFFSET (0x228026) /* TCD22 Transfer Attributes (TCD22_ATTR) */
+#define S32K3XX_EDMA_TCD22_NBYTES_OFFSET (0x228028) /* TCD22 Transfer Size (TCD22_NBYTES) */
+#define S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET (0x22802c) /* TCD22 Last Source Address Adjustment / Store DADDR Address Register (TCD22_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD22_DADDR_OFFSET (0x228030) /* TCD22 Destination Address Register (TCD22_DADDR) */
+#define S32K3XX_EDMA_TCD22_DOFF_OFFSET (0x228034) /* TCD22 Signed Destination Address Offset Register (TCD22_DOFF) */
+#define S32K3XX_EDMA_TCD22_CITER_OFFSET (0x228036) /* TCD22 Current Major Loop Count Register (TCD22_CITER) */
+#define S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET (0x228038) /* TCD22 Last Destination Address Adjustment / Scatter Gather Address Register (TCD22_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD22_CSR_OFFSET (0x22803c) /* TCD22 Control and Status Register (TCD22_CSR) */
+#define S32K3XX_EDMA_TCD22_BITER_OFFSET (0x22803e) /* TCD22 Beginning Major Loop Count Register (TCD22_BITER) */
+
+#define S32K3XX_EDMA_CH23_CSR_OFFSET (0x22c000) /* Channel 23 Control and Status Register (CH23_CSR) */
+#define S32K3XX_EDMA_CH23_ES_OFFSET (0x22c004) /* Channel 23 Error Status Register (CH23_ES) */
+#define S32K3XX_EDMA_CH23_INT_OFFSET (0x22c008) /* Channel 23 Interrupt Status Register (CH23_INT) */
+#define S32K3XX_EDMA_CH23_SBR_OFFSET (0x22c00c) /* Channel 23 System Bus Register (CH23_SBR) */
+#define S32K3XX_EDMA_CH23_PRI_OFFSET (0x22c010) /* Channel 23 Priority Register (CH23_PRI) */
+#define S32K3XX_EDMA_TCD23_SADDR_OFFSET (0x22c020) /* TCD23 Source Address Register (TCD23_SADDR) */
+#define S32K3XX_EDMA_TCD23_SOFF_OFFSET (0x22c024) /* TCD23 Signed Source Address Offset Register (TCD23_SOFF) */
+#define S32K3XX_EDMA_TCD23_ATTR_OFFSET (0x22c026) /* TCD23 Transfer Attributes (TCD23_ATTR) */
+#define S32K3XX_EDMA_TCD23_NBYTES_OFFSET (0x22c028) /* TCD23 Transfer Size (TCD23_NBYTES) */
+#define S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET (0x22c02c) /* TCD23 Last Source Address Adjustment / Store DADDR Address Register (TCD23_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD23_DADDR_OFFSET (0x22c030) /* TCD23 Destination Address Register (TCD23_DADDR) */
+#define S32K3XX_EDMA_TCD23_DOFF_OFFSET (0x22c034) /* TCD23 Signed Destination Address Offset Register (TCD23_DOFF) */
+#define S32K3XX_EDMA_TCD23_CITER_OFFSET (0x22c036) /* TCD23 Current Major Loop Count Register (TCD23_CITER) */
+#define S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET (0x22c038) /* TCD23 Last Destination Address Adjustment / Scatter Gather Address Register (TCD23_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD23_CSR_OFFSET (0x22c03c) /* TCD23 Control and Status Register (TCD23_CSR) */
+#define S32K3XX_EDMA_TCD23_BITER_OFFSET (0x22c03e) /* TCD23 Beginning Major Loop Count Register (TCD23_BITER) */
+
+#define S32K3XX_EDMA_CH24_CSR_OFFSET (0x230000) /* Channel 24 Control and Status Register (CH24_CSR) */
+#define S32K3XX_EDMA_CH24_ES_OFFSET (0x230004) /* Channel 24 Error Status Register (CH24_ES) */
+#define S32K3XX_EDMA_CH24_INT_OFFSET (0x230008) /* Channel 24 Interrupt Status Register (CH24_INT) */
+#define S32K3XX_EDMA_CH24_SBR_OFFSET (0x23000c) /* Channel 24 System Bus Register (CH24_SBR) */
+#define S32K3XX_EDMA_CH24_PRI_OFFSET (0x230010) /* Channel 24 Priority Register (CH24_PRI) */
+#define S32K3XX_EDMA_TCD24_SADDR_OFFSET (0x230020) /* TCD24 Source Address Register (TCD24_SADDR) */
+#define S32K3XX_EDMA_TCD24_SOFF_OFFSET (0x230024) /* TCD24 Signed Source Address Offset Register (TCD24_SOFF) */
+#define S32K3XX_EDMA_TCD24_ATTR_OFFSET (0x230026) /* TCD24 Transfer Attributes (TCD24_ATTR) */
+#define S32K3XX_EDMA_TCD24_NBYTES_OFFSET (0x230028) /* TCD24 Transfer Size (TCD24_NBYTES) */
+#define S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET (0x23002c) /* TCD24 Last Source Address Adjustment / Store DADDR Address Register (TCD24_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD24_DADDR_OFFSET (0x230030) /* TCD24 Destination Address Register (TCD24_DADDR) */
+#define S32K3XX_EDMA_TCD24_DOFF_OFFSET (0x230034) /* TCD24 Signed Destination Address Offset Register (TCD24_DOFF) */
+#define S32K3XX_EDMA_TCD24_CITER_OFFSET (0x230036) /* TCD24 Current Major Loop Count Register (TCD24_CITER) */
+#define S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET (0x230038) /* TCD24 Last Destination Address Adjustment / Scatter Gather Address Register (TCD24_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD24_CSR_OFFSET (0x23003c) /* TCD24 Control and Status Register (TCD24_CSR) */
+#define S32K3XX_EDMA_TCD24_BITER_OFFSET (0x23003e) /* TCD24 Beginning Major Loop Count Register (TCD24_BITER) */
+
+#define S32K3XX_EDMA_CH25_CSR_OFFSET (0x234000) /* Channel 25 Control and Status Register (CH25_CSR) */
+#define S32K3XX_EDMA_CH25_ES_OFFSET (0x234004) /* Channel 25 Error Status Register (CH25_ES) */
+#define S32K3XX_EDMA_CH25_INT_OFFSET (0x234008) /* Channel 25 Interrupt Status Register (CH25_INT) */
+#define S32K3XX_EDMA_CH25_SBR_OFFSET (0x23400c) /* Channel 25 System Bus Register (CH25_SBR) */
+#define S32K3XX_EDMA_CH25_PRI_OFFSET (0x234010) /* Channel 25 Priority Register (CH25_PRI) */
+#define S32K3XX_EDMA_TCD25_SADDR_OFFSET (0x234020) /* TCD25 Source Address Register (TCD25_SADDR) */
+#define S32K3XX_EDMA_TCD25_SOFF_OFFSET (0x234024) /* TCD25 Signed Source Address Offset Register (TCD25_SOFF) */
+#define S32K3XX_EDMA_TCD25_ATTR_OFFSET (0x234026) /* TCD25 Transfer Attributes (TCD25_ATTR) */
+#define S32K3XX_EDMA_TCD25_NBYTES_OFFSET (0x234028) /* TCD25 Transfer Size (TCD25_NBYTES) */
+#define S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET (0x23402c) /* TCD25 Last Source Address Adjustment / Store DADDR Address Register (TCD25_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD25_DADDR_OFFSET (0x234030) /* TCD25 Destination Address Register (TCD25_DADDR) */
+#define S32K3XX_EDMA_TCD25_DOFF_OFFSET (0x234034) /* TCD25 Signed Destination Address Offset Register (TCD25_DOFF) */
+#define S32K3XX_EDMA_TCD25_CITER_OFFSET (0x234036) /* TCD25 Current Major Loop Count Register (TCD25_CITER) */
+#define S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET (0x234038) /* TCD25 Last Destination Address Adjustment / Scatter Gather Address Register (TCD25_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD25_CSR_OFFSET (0x23403c) /* TCD25 Control and Status Register (TCD25_CSR) */
+#define S32K3XX_EDMA_TCD25_BITER_OFFSET (0x23403e) /* TCD25 Beginning Major Loop Count Register (TCD25_BITER) */
+
+#define S32K3XX_EDMA_CH26_CSR_OFFSET (0x238000) /* Channel 26 Control and Status Register (CH26_CSR) */
+#define S32K3XX_EDMA_CH26_ES_OFFSET (0x238004) /* Channel 26 Error Status Register (CH26_ES) */
+#define S32K3XX_EDMA_CH26_INT_OFFSET (0x238008) /* Channel 26 Interrupt Status Register (CH26_INT) */
+#define S32K3XX_EDMA_CH26_SBR_OFFSET (0x23800c) /* Channel 26 System Bus Register (CH26_SBR) */
+#define S32K3XX_EDMA_CH26_PRI_OFFSET (0x238010) /* Channel 26 Priority Register (CH26_PRI) */
+#define S32K3XX_EDMA_TCD26_SADDR_OFFSET (0x238020) /* TCD26 Source Address Register (TCD26_SADDR) */
+#define S32K3XX_EDMA_TCD26_SOFF_OFFSET (0x238024) /* TCD26 Signed Source Address Offset Register (TCD26_SOFF) */
+#define S32K3XX_EDMA_TCD26_ATTR_OFFSET (0x238026) /* TCD26 Transfer Attributes (TCD26_ATTR) */
+#define S32K3XX_EDMA_TCD26_NBYTES_OFFSET (0x238028) /* TCD26 Transfer Size (TCD26_NBYTES) */
+#define S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET (0x23802c) /* TCD26 Last Source Address Adjustment / Store DADDR Address Register (TCD26_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD26_DADDR_OFFSET (0x238030) /* TCD26 Destination Address Register (TCD26_DADDR) */
+#define S32K3XX_EDMA_TCD26_DOFF_OFFSET (0x238034) /* TCD26 Signed Destination Address Offset Register (TCD26_DOFF) */
+#define S32K3XX_EDMA_TCD26_CITER_OFFSET (0x238036) /* TCD26 Current Major Loop Count Register (TCD26_CITER) */
+#define S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET (0x238038) /* TCD26 Last Destination Address Adjustment / Scatter Gather Address Register (TCD26_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD26_CSR_OFFSET (0x23803c) /* TCD26 Control and Status Register (TCD26_CSR) */
+#define S32K3XX_EDMA_TCD26_BITER_OFFSET (0x23803e) /* TCD26 Beginning Major Loop Count Register (TCD26_BITER) */
+
+#define S32K3XX_EDMA_CH27_CSR_OFFSET (0x23c000) /* Channel 27 Control and Status Register (CH27_CSR) */
+#define S32K3XX_EDMA_CH27_ES_OFFSET (0x23c004) /* Channel 27 Error Status Register (CH27_ES) */
+#define S32K3XX_EDMA_CH27_INT_OFFSET (0x23c008) /* Channel 27 Interrupt Status Register (CH27_INT) */
+#define S32K3XX_EDMA_CH27_SBR_OFFSET (0x23c00c) /* Channel 27 System Bus Register (CH27_SBR) */
+#define S32K3XX_EDMA_CH27_PRI_OFFSET (0x23c010) /* Channel 27 Priority Register (CH27_PRI) */
+#define S32K3XX_EDMA_TCD27_SADDR_OFFSET (0x23c020) /* TCD27 Source Address Register (TCD27_SADDR) */
+#define S32K3XX_EDMA_TCD27_SOFF_OFFSET (0x23c024) /* TCD27 Signed Source Address Offset Register (TCD27_SOFF) */
+#define S32K3XX_EDMA_TCD27_ATTR_OFFSET (0x23c026) /* TCD27 Transfer Attributes (TCD27_ATTR) */
+#define S32K3XX_EDMA_TCD27_NBYTES_OFFSET (0x23c028) /* TCD27 Transfer Size (TCD27_NBYTES) */
+#define S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET (0x23c02c) /* TCD27 Last Source Address Adjustment / Store DADDR Address Register (TCD27_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD27_DADDR_OFFSET (0x23c030) /* TCD27 Destination Address Register (TCD27_DADDR) */
+#define S32K3XX_EDMA_TCD27_DOFF_OFFSET (0x23c034) /* TCD27 Signed Destination Address Offset Register (TCD27_DOFF) */
+#define S32K3XX_EDMA_TCD27_CITER_OFFSET (0x23c036) /* TCD27 Current Major Loop Count Register (TCD27_CITER) */
+#define S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET (0x23c038) /* TCD27 Last Destination Address Adjustment / Scatter Gather Address Register (TCD27_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD27_CSR_OFFSET (0x23c03c) /* TCD27 Control and Status Register (TCD27_CSR) */
+#define S32K3XX_EDMA_TCD27_BITER_OFFSET (0x23c03e) /* TCD27 Beginning Major Loop Count Register (TCD27_BITER) */
+
+#define S32K3XX_EDMA_CH28_CSR_OFFSET (0x240000) /* Channel 28 Control and Status Register (CH28_CSR) */
+#define S32K3XX_EDMA_CH28_ES_OFFSET (0x240004) /* Channel 28 Error Status Register (CH28_ES) */
+#define S32K3XX_EDMA_CH28_INT_OFFSET (0x240008) /* Channel 28 Interrupt Status Register (CH28_INT) */
+#define S32K3XX_EDMA_CH28_SBR_OFFSET (0x24000c) /* Channel 28 System Bus Register (CH28_SBR) */
+#define S32K3XX_EDMA_CH28_PRI_OFFSET (0x240010) /* Channel 28 Priority Register (CH28_PRI) */
+#define S32K3XX_EDMA_TCD28_SADDR_OFFSET (0x240020) /* TCD28 Source Address Register (TCD28_SADDR) */
+#define S32K3XX_EDMA_TCD28_SOFF_OFFSET (0x240024) /* TCD28 Signed Source Address Offset Register (TCD28_SOFF) */
+#define S32K3XX_EDMA_TCD28_ATTR_OFFSET (0x240026) /* TCD28 Transfer Attributes (TCD28_ATTR) */
+#define S32K3XX_EDMA_TCD28_NBYTES_OFFSET (0x240028) /* TCD28 Transfer Size (TCD28_NBYTES) */
+#define S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET (0x24002c) /* TCD28 Last Source Address Adjustment / Store DADDR Address Register (TCD28_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD28_DADDR_OFFSET (0x240030) /* TCD28 Destination Address Register (TCD28_DADDR) */
+#define S32K3XX_EDMA_TCD28_DOFF_OFFSET (0x240034) /* TCD28 Signed Destination Address Offset Register (TCD28_DOFF) */
+#define S32K3XX_EDMA_TCD28_CITER_OFFSET (0x240036) /* TCD28 Current Major Loop Count Register (TCD28_CITER) */
+#define S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET (0x240038) /* TCD28 Last Destination Address Adjustment / Scatter Gather Address Register (TCD28_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD28_CSR_OFFSET (0x24003c) /* TCD28 Control and Status Register (TCD28_CSR) */
+#define S32K3XX_EDMA_TCD28_BITER_OFFSET (0x24003e) /* TCD28 Beginning Major Loop Count Register (TCD28_BITER) */
+
+#define S32K3XX_EDMA_CH29_CSR_OFFSET (0x244000) /* Channel 29 Control and Status Register (CH29_CSR) */
+#define S32K3XX_EDMA_CH29_ES_OFFSET (0x244004) /* Channel 29 Error Status Register (CH29_ES) */
+#define S32K3XX_EDMA_CH29_INT_OFFSET (0x244008) /* Channel 29 Interrupt Status Register (CH29_INT) */
+#define S32K3XX_EDMA_CH29_SBR_OFFSET (0x24400c) /* Channel 29 System Bus Register (CH29_SBR) */
+#define S32K3XX_EDMA_CH29_PRI_OFFSET (0x244010) /* Channel 29 Priority Register (CH29_PRI) */
+#define S32K3XX_EDMA_TCD29_SADDR_OFFSET (0x244020) /* TCD29 Source Address Register (TCD29_SADDR) */
+#define S32K3XX_EDMA_TCD29_SOFF_OFFSET (0x244024) /* TCD29 Signed Source Address Offset Register (TCD29_SOFF) */
+#define S32K3XX_EDMA_TCD29_ATTR_OFFSET (0x244026) /* TCD29 Transfer Attributes (TCD29_ATTR) */
+#define S32K3XX_EDMA_TCD29_NBYTES_OFFSET (0x244028) /* TCD29 Transfer Size (TCD29_NBYTES) */
+#define S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET (0x24402c) /* TCD29 Last Source Address Adjustment / Store DADDR Address Register (TCD29_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD29_DADDR_OFFSET (0x244030) /* TCD29 Destination Address Register (TCD29_DADDR) */
+#define S32K3XX_EDMA_TCD29_DOFF_OFFSET (0x244034) /* TCD29 Signed Destination Address Offset Register (TCD29_DOFF) */
+#define S32K3XX_EDMA_TCD29_CITER_OFFSET (0x244036) /* TCD29 Current Major Loop Count Register (TCD29_CITER) */
+#define S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET (0x244038) /* TCD29 Last Destination Address Adjustment / Scatter Gather Address Register (TCD29_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD29_CSR_OFFSET (0x24403c) /* TCD29 Control and Status Register (TCD29_CSR) */
+#define S32K3XX_EDMA_TCD29_BITER_OFFSET (0x24403e) /* TCD29 Beginning Major Loop Count Register (TCD29_BITER) */
+
+#define S32K3XX_EDMA_CH30_CSR_OFFSET (0x248000) /* Channel 30 Control and Status Register (CH30_CSR) */
+#define S32K3XX_EDMA_CH30_ES_OFFSET (0x248004) /* Channel 30 Error Status Register (CH30_ES) */
+#define S32K3XX_EDMA_CH30_INT_OFFSET (0x248008) /* Channel 30 Interrupt Status Register (CH30_INT) */
+#define S32K3XX_EDMA_CH30_SBR_OFFSET (0x24800c) /* Channel 30 System Bus Register (CH30_SBR) */
+#define S32K3XX_EDMA_CH30_PRI_OFFSET (0x248010) /* Channel 30 Priority Register (CH30_PRI) */
+#define S32K3XX_EDMA_TCD30_SADDR_OFFSET (0x248020) /* TCD30 Source Address Register (TCD30_SADDR) */
+#define S32K3XX_EDMA_TCD30_SOFF_OFFSET (0x248024) /* TCD30 Signed Source Address Offset Register (TCD30_SOFF) */
+#define S32K3XX_EDMA_TCD30_ATTR_OFFSET (0x248026) /* TCD30 Transfer Attributes (TCD30_ATTR) */
+#define S32K3XX_EDMA_TCD30_NBYTES_OFFSET (0x248028) /* TCD30 Transfer Size (TCD30_NBYTES) */
+#define S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET (0x24802c) /* TCD30 Last Source Address Adjustment / Store DADDR Address Register (TCD30_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD30_DADDR_OFFSET (0x248030) /* TCD30 Destination Address Register (TCD30_DADDR) */
+#define S32K3XX_EDMA_TCD30_DOFF_OFFSET (0x248034) /* TCD30 Signed Destination Address Offset Register (TCD30_DOFF) */
+#define S32K3XX_EDMA_TCD30_CITER_OFFSET (0x248036) /* TCD30 Current Major Loop Count Register (TCD30_CITER) */
+#define S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET (0x248038) /* TCD30 Last Destination Address Adjustment / Scatter Gather Address Register (TCD30_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD30_CSR_OFFSET (0x24803c) /* TCD30 Control and Status Register (TCD30_CSR) */
+#define S32K3XX_EDMA_TCD30_BITER_OFFSET (0x24803e) /* TCD30 Beginning Major Loop Count Register (TCD30_BITER) */
+
+#define S32K3XX_EDMA_CH31_CSR_OFFSET (0x24c000) /* Channel 31 Control and Status Register (CH31_CSR) */
+#define S32K3XX_EDMA_CH31_ES_OFFSET (0x24c004) /* Channel 31 Error Status Register (CH31_ES) */
+#define S32K3XX_EDMA_CH31_INT_OFFSET (0x24c008) /* Channel 31 Interrupt Status Register (CH31_INT) */
+#define S32K3XX_EDMA_CH31_SBR_OFFSET (0x24c00c) /* Channel 31 System Bus Register (CH31_SBR) */
+#define S32K3XX_EDMA_CH31_PRI_OFFSET (0x24c010) /* Channel 31 Priority Register (CH31_PRI) */
+#define S32K3XX_EDMA_TCD31_SADDR_OFFSET (0x24c020) /* TCD31 Source Address Register (TCD31_SADDR) */
+#define S32K3XX_EDMA_TCD31_SOFF_OFFSET (0x24c024) /* TCD31 Signed Source Address Offset Register (TCD31_SOFF) */
+#define S32K3XX_EDMA_TCD31_ATTR_OFFSET (0x24c026) /* TCD31 Transfer Attributes (TCD31_ATTR) */
+#define S32K3XX_EDMA_TCD31_NBYTES_OFFSET (0x24c028) /* TCD31 Transfer Size (TCD31_NBYTES) */
+#define S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET (0x24c02c) /* TCD31 Last Source Address Adjustment / Store DADDR Address Register (TCD31_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD31_DADDR_OFFSET (0x24c030) /* TCD31 Destination Address Register (TCD31_DADDR) */
+#define S32K3XX_EDMA_TCD31_DOFF_OFFSET (0x24c034) /* TCD31 Signed Destination Address Offset Register (TCD31_DOFF) */
+#define S32K3XX_EDMA_TCD31_CITER_OFFSET (0x24c036) /* TCD31 Current Major Loop Count Register (TCD31_CITER) */
+#define S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET (0x24c038) /* TCD31 Last Destination Address Adjustment / Scatter Gather Address Register (TCD31_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD31_CSR_OFFSET (0x24c03c) /* TCD31 Control and Status Register (TCD31_CSR) */
+#define S32K3XX_EDMA_TCD31_BITER_OFFSET (0x24c03e) /* TCD31 Beginning Major Loop Count Register (TCD31_BITER) */
+
+/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/
+
+#define S32K3XX_EDMA_CH0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_CSR_OFFSET)
+#define S32K3XX_EDMA_CH0_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_ES_OFFSET)
+#define S32K3XX_EDMA_CH0_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_INT_OFFSET)
+#define S32K3XX_EDMA_CH0_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_SBR_OFFSET)
+#define S32K3XX_EDMA_CH0_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD0_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD0_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD0_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD0_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD0_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD0_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_CSR_OFFSET)
+#define S32K3XX_EDMA_CH1_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_ES_OFFSET)
+#define S32K3XX_EDMA_CH1_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_INT_OFFSET)
+#define S32K3XX_EDMA_CH1_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_SBR_OFFSET)
+#define S32K3XX_EDMA_CH1_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD1_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD1_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD1_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD1_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD1_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD1_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_CSR_OFFSET)
+#define S32K3XX_EDMA_CH2_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_ES_OFFSET)
+#define S32K3XX_EDMA_CH2_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_INT_OFFSET)
+#define S32K3XX_EDMA_CH2_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_SBR_OFFSET)
+#define S32K3XX_EDMA_CH2_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD2_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD2_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD2_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD2_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD2_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD2_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_CSR_OFFSET)
+#define S32K3XX_EDMA_CH3_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_ES_OFFSET)
+#define S32K3XX_EDMA_CH3_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_INT_OFFSET)
+#define S32K3XX_EDMA_CH3_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_SBR_OFFSET)
+#define S32K3XX_EDMA_CH3_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD3_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD3_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD3_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD3_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD3_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD3_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_CSR_OFFSET)
+#define S32K3XX_EDMA_CH4_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_ES_OFFSET)
+#define S32K3XX_EDMA_CH4_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_INT_OFFSET)
+#define S32K3XX_EDMA_CH4_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_SBR_OFFSET)
+#define S32K3XX_EDMA_CH4_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD4_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD4_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD4_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD4_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD4_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD4_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_CSR_OFFSET)
+#define S32K3XX_EDMA_CH5_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_ES_OFFSET)
+#define S32K3XX_EDMA_CH5_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_INT_OFFSET)
+#define S32K3XX_EDMA_CH5_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_SBR_OFFSET)
+#define S32K3XX_EDMA_CH5_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD5_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD5_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD5_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD5_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD5_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD5_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_CSR_OFFSET)
+#define S32K3XX_EDMA_CH6_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_ES_OFFSET)
+#define S32K3XX_EDMA_CH6_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_INT_OFFSET)
+#define S32K3XX_EDMA_CH6_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_SBR_OFFSET)
+#define S32K3XX_EDMA_CH6_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD6_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD6_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD6_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD6_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD6_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD6_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_CSR_OFFSET)
+#define S32K3XX_EDMA_CH7_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_ES_OFFSET)
+#define S32K3XX_EDMA_CH7_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_INT_OFFSET)
+#define S32K3XX_EDMA_CH7_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_SBR_OFFSET)
+#define S32K3XX_EDMA_CH7_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD7_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD7_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD7_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD7_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD7_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD7_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_CSR_OFFSET)
+#define S32K3XX_EDMA_CH8_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_ES_OFFSET)
+#define S32K3XX_EDMA_CH8_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_INT_OFFSET)
+#define S32K3XX_EDMA_CH8_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_SBR_OFFSET)
+#define S32K3XX_EDMA_CH8_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD8_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD8_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD8_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD8_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD8_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD8_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_CSR_OFFSET)
+#define S32K3XX_EDMA_CH9_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_ES_OFFSET)
+#define S32K3XX_EDMA_CH9_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_INT_OFFSET)
+#define S32K3XX_EDMA_CH9_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_SBR_OFFSET)
+#define S32K3XX_EDMA_CH9_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD9_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD9_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD9_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD9_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD9_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD9_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_CSR_OFFSET)
+#define S32K3XX_EDMA_CH10_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_ES_OFFSET)
+#define S32K3XX_EDMA_CH10_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_INT_OFFSET)
+#define S32K3XX_EDMA_CH10_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_SBR_OFFSET)
+#define S32K3XX_EDMA_CH10_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD10_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD10_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD10_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD10_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD10_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD10_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_CSR_OFFSET)
+#define S32K3XX_EDMA_CH11_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_ES_OFFSET)
+#define S32K3XX_EDMA_CH11_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_INT_OFFSET)
+#define S32K3XX_EDMA_CH11_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_SBR_OFFSET)
+#define S32K3XX_EDMA_CH11_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD11_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD11_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD11_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD11_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD11_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD11_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_CSR_OFFSET)
+#define S32K3XX_EDMA_CH12_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_ES_OFFSET)
+#define S32K3XX_EDMA_CH12_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_INT_OFFSET)
+#define S32K3XX_EDMA_CH12_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_SBR_OFFSET)
+#define S32K3XX_EDMA_CH12_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD12_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD12_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD12_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD12_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD12_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD12_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_CSR_OFFSET)
+#define S32K3XX_EDMA_CH13_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_ES_OFFSET)
+#define S32K3XX_EDMA_CH13_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_INT_OFFSET)
+#define S32K3XX_EDMA_CH13_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_SBR_OFFSET)
+#define S32K3XX_EDMA_CH13_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD13_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD13_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD13_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD13_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD13_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD13_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_CSR_OFFSET)
+#define S32K3XX_EDMA_CH14_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_ES_OFFSET)
+#define S32K3XX_EDMA_CH14_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_INT_OFFSET)
+#define S32K3XX_EDMA_CH14_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_SBR_OFFSET)
+#define S32K3XX_EDMA_CH14_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD14_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD14_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD14_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD14_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD14_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD14_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_CSR_OFFSET)
+#define S32K3XX_EDMA_CH15_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_ES_OFFSET)
+#define S32K3XX_EDMA_CH15_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_INT_OFFSET)
+#define S32K3XX_EDMA_CH15_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_SBR_OFFSET)
+#define S32K3XX_EDMA_CH15_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD15_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD15_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD15_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD15_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD15_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD15_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_CSR_OFFSET)
+#define S32K3XX_EDMA_CH16_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_ES_OFFSET)
+#define S32K3XX_EDMA_CH16_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_INT_OFFSET)
+#define S32K3XX_EDMA_CH16_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_SBR_OFFSET)
+#define S32K3XX_EDMA_CH16_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD16_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD16_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD16_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD16_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD16_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD16_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_CSR_OFFSET)
+#define S32K3XX_EDMA_CH17_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_ES_OFFSET)
+#define S32K3XX_EDMA_CH17_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_INT_OFFSET)
+#define S32K3XX_EDMA_CH17_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_SBR_OFFSET)
+#define S32K3XX_EDMA_CH17_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD17_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD17_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD17_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD17_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD17_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD17_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_CSR_OFFSET)
+#define S32K3XX_EDMA_CH18_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_ES_OFFSET)
+#define S32K3XX_EDMA_CH18_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_INT_OFFSET)
+#define S32K3XX_EDMA_CH18_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_SBR_OFFSET)
+#define S32K3XX_EDMA_CH18_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD18_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD18_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD18_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD18_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD18_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD18_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_CSR_OFFSET)
+#define S32K3XX_EDMA_CH19_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_ES_OFFSET)
+#define S32K3XX_EDMA_CH19_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_INT_OFFSET)
+#define S32K3XX_EDMA_CH19_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_SBR_OFFSET)
+#define S32K3XX_EDMA_CH19_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD19_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD19_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD19_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD19_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD19_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD19_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_CSR_OFFSET)
+#define S32K3XX_EDMA_CH20_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_ES_OFFSET)
+#define S32K3XX_EDMA_CH20_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_INT_OFFSET)
+#define S32K3XX_EDMA_CH20_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_SBR_OFFSET)
+#define S32K3XX_EDMA_CH20_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD20_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD20_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD20_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD20_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD20_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD20_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_CSR_OFFSET)
+#define S32K3XX_EDMA_CH21_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_ES_OFFSET)
+#define S32K3XX_EDMA_CH21_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_INT_OFFSET)
+#define S32K3XX_EDMA_CH21_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_SBR_OFFSET)
+#define S32K3XX_EDMA_CH21_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD21_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD21_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD21_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD21_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD21_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD21_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_CSR_OFFSET)
+#define S32K3XX_EDMA_CH22_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_ES_OFFSET)
+#define S32K3XX_EDMA_CH22_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_INT_OFFSET)
+#define S32K3XX_EDMA_CH22_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_SBR_OFFSET)
+#define S32K3XX_EDMA_CH22_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD22_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD22_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD22_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD22_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD22_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD22_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_CSR_OFFSET)
+#define S32K3XX_EDMA_CH23_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_ES_OFFSET)
+#define S32K3XX_EDMA_CH23_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_INT_OFFSET)
+#define S32K3XX_EDMA_CH23_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_SBR_OFFSET)
+#define S32K3XX_EDMA_CH23_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD23_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD23_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD23_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD23_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD23_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD23_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_CSR_OFFSET)
+#define S32K3XX_EDMA_CH24_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_ES_OFFSET)
+#define S32K3XX_EDMA_CH24_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_INT_OFFSET)
+#define S32K3XX_EDMA_CH24_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_SBR_OFFSET)
+#define S32K3XX_EDMA_CH24_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD24_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD24_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD24_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD24_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD24_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD24_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_CSR_OFFSET)
+#define S32K3XX_EDMA_CH25_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_ES_OFFSET)
+#define S32K3XX_EDMA_CH25_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_INT_OFFSET)
+#define S32K3XX_EDMA_CH25_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_SBR_OFFSET)
+#define S32K3XX_EDMA_CH25_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD25_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD25_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD25_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD25_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD25_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD25_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_CSR_OFFSET)
+#define S32K3XX_EDMA_CH26_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_ES_OFFSET)
+#define S32K3XX_EDMA_CH26_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_INT_OFFSET)
+#define S32K3XX_EDMA_CH26_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_SBR_OFFSET)
+#define S32K3XX_EDMA_CH26_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD26_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD26_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD26_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD26_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD26_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD26_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_CSR_OFFSET)
+#define S32K3XX_EDMA_CH27_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_ES_OFFSET)
+#define S32K3XX_EDMA_CH27_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_INT_OFFSET)
+#define S32K3XX_EDMA_CH27_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_SBR_OFFSET)
+#define S32K3XX_EDMA_CH27_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD27_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD27_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD27_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD27_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD27_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD27_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_CSR_OFFSET)
+#define S32K3XX_EDMA_CH28_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_ES_OFFSET)
+#define S32K3XX_EDMA_CH28_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_INT_OFFSET)
+#define S32K3XX_EDMA_CH28_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_SBR_OFFSET)
+#define S32K3XX_EDMA_CH28_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD28_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD28_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD28_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD28_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD28_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD28_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_CSR_OFFSET)
+#define S32K3XX_EDMA_CH29_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_ES_OFFSET)
+#define S32K3XX_EDMA_CH29_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_INT_OFFSET)
+#define S32K3XX_EDMA_CH29_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_SBR_OFFSET)
+#define S32K3XX_EDMA_CH29_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD29_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD29_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD29_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD29_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD29_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD29_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_CSR_OFFSET)
+#define S32K3XX_EDMA_CH30_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_ES_OFFSET)
+#define S32K3XX_EDMA_CH30_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_INT_OFFSET)
+#define S32K3XX_EDMA_CH30_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_SBR_OFFSET)
+#define S32K3XX_EDMA_CH30_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD30_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD30_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD30_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD30_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD30_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD30_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_CSR_OFFSET)
+#define S32K3XX_EDMA_CH31_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_ES_OFFSET)
+#define S32K3XX_EDMA_CH31_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_INT_OFFSET)
+#define S32K3XX_EDMA_CH31_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_SBR_OFFSET)
+#define S32K3XX_EDMA_CH31_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD31_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD31_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD31_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD31_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD31_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD31_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_BITER_OFFSET)
+
+uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
+{
+ S32K3XX_EDMA_CH0_CSR,
+ S32K3XX_EDMA_CH1_CSR,
+ S32K3XX_EDMA_CH2_CSR,
+ S32K3XX_EDMA_CH3_CSR,
+ S32K3XX_EDMA_CH4_CSR,
+ S32K3XX_EDMA_CH5_CSR,
+ S32K3XX_EDMA_CH6_CSR,
+ S32K3XX_EDMA_CH7_CSR,
+ S32K3XX_EDMA_CH8_CSR,
+ S32K3XX_EDMA_CH9_CSR,
+ S32K3XX_EDMA_CH10_CSR,
+ S32K3XX_EDMA_CH11_CSR,
+ S32K3XX_EDMA_CH12_CSR,
+ S32K3XX_EDMA_CH13_CSR,
+ S32K3XX_EDMA_CH14_CSR,
+ S32K3XX_EDMA_CH15_CSR,
+ S32K3XX_EDMA_CH16_CSR,
+ S32K3XX_EDMA_CH17_CSR,
+ S32K3XX_EDMA_CH18_CSR,
+ S32K3XX_EDMA_CH19_CSR,
+ S32K3XX_EDMA_CH20_CSR,
+ S32K3XX_EDMA_CH21_CSR,
+ S32K3XX_EDMA_CH22_CSR,
+ S32K3XX_EDMA_CH23_CSR,
+ S32K3XX_EDMA_CH24_CSR,
+ S32K3XX_EDMA_CH25_CSR,
+ S32K3XX_EDMA_CH26_CSR,
+ S32K3XX_EDMA_CH27_CSR,
+ S32K3XX_EDMA_CH28_CSR,
+ S32K3XX_EDMA_CH29_CSR,
+ S32K3XX_EDMA_CH30_CSR,
+ S32K3XX_EDMA_CH31_CSR
+};
+
+/* eDMA Register Bitfield Definitions ***************************************/
+
+/* Management Page Control Register (CSR) */
+
+ /* Bit 0: Reserved */
+#define EDMA_CSR_EDBG (1 << 1) /* Bit 1: Enable Debug (EDBG) */
+#define EDMA_CSR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration (ERCA) */
+ /* Bit 3: Reserved */
+#define EDMA_CSR_HAE (1 << 4) /* Bit 4: Halt After Error (HAE) */
+#define EDMA_CSR_HALT (1 << 5) /* Bit 5: Halt DMA Operations (HALT) */
+#define EDMA_CSR_GCLC (1 << 6) /* Bit 6: Global Channel Linking Control (GCLC) */
+#define EDMA_CSR_GMRC (1 << 7) /* Bit 7: Global Master ID Replication Control (GMRC) */
+#define EDMA_CSR_ECX (1 << 8) /* Bit 8: Cancel Transfer With Error (ECX) */
+#define EDMA_CSR_CX (1 << 9) /* Bit 9: Cancel Transfer (CX) */
+ /* Bits 10-23: Reserved */
+#define EDMA_CSR_ACTIVE_ID_SHIFT (24) /* Bits 24-28: Active Channel ID (ACTIVE_ID) */
+#define EDMA_CSR_ACTIVE_ID_MASK (0x1f << EDMA_CSR_ACTIVE_ID_SHIFT)
+ /* Bits 29-30: Reserved */
+#define EDMA_CSR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status (ACTIVE) */
+
+/* Management Page Error Status Register (ES) */
+
+#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
+#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
+#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
+#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
+#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
+#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
+#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
+#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
+#define EDMA_ES_ECX (1 << 8) /* Bit 8: Transfer Canceled (ECX) */
+#define EDMA_ES_UCE (1 << 9) /* Bit 9: Uncorrectable TCD Error During Channel Execution (UCE) */
+ /* Bits 10-23: Reserved */
+#define EDMA_ES_ERRCHN_SHIFT (8) /* Bits 24-28: Error Channel Number or Canceled Channel Number (ERRCHN) */
+#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT)
+ /* Bits 29-30: Reserved */
+#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status fields (VALID) */
+
+/* Management Page Interrupt Request Status Register (INT) */
+
+#define EDMA_INT(n) (1 << (n)) /* Bit n: Interrupt Request Status (INT) */
+
+/* Management Page Hardware Request Status Register (HRS) */
+
+#define EDMA_HRS(n) (1 << (n)) /* Bit n: Hardware Request Status (HRS) */
+
+/* Channel n Arbitration Group Register (CHn_GRPRI) */
+
+#define EDMA_CH_GRPRI_SHIFT (0) /* Bits 0-4: Arbitration Group For Channel n (GRPRI) */
+#define EDMA_CH_GRPRI_MASK (0x1f << EDMA_CH_GRPRI_SHIFT)
+ /* Bits 5-31: Reserved */
+
+/* eDMA Transfer Control Descriptor (TCD) Bitfield Definitions **************/
+
+/* Channel n Control and Status Register (CHn_CSR) */
+
+#define EDMA_CH_CSR_ERQ (1 << 0) /* Bit 0: Enable DMA Request (ERQ) */
+#define EDMA_CH_CSR_EARQ (1 << 1) /* Bit 1: Enable Asynchronous DMA Request in Stop Mode for Channel (EARQ) */
+#define EDMA_CH_CSR_EEI (1 << 2) /* Bit 2: Enable Error Interrupt (EEI) */
+#define EDMA_CH_CSR_EBW (1 << 3) /* Bit 3: Enable Buffered Writes (EBW) */
+ /* Bit 4-29: Reserved */
+#define EDMA_CH_CSR_DONE (1 << 30) /* Bit 30: Channel Done (DONE) */
+#define EDMA_CH_CSR_ACTIVE (1 << 31) /* Bit 31: CHannel Active (ACTIVE) */
+
+/* Channel n Error Status Register (CHn_ES) */
+
+#define EDMA_CH_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
+#define EDMA_CH_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
+#define EDMA_CH_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
+#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
+#define EDMA_CH_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
+#define EDMA_CH_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
+#define EDMA_CH_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
+#define EDMA_CH_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
+ /* Bit 8-30: Reserved */
+#define EDMA_CH_ES_ERR (1 << 31) /* Bit 31: Error in this channel (ERR) */
+
+/* Channel n Interrupt Status Register (CHn_INT) */
+
+#define EDMA_CH_INT (1 << 0) /* Bit 0: Interrupt Request (INT) */
+ /* Bits 1-31: Reserved */
+
+/* Channel n System Bus Register (CHn_SBR) */
+
+#define EDMA_CH_SBR_MID_SHIFT (0) /* Bits 0-3: Master ID (MID) */
+#define EDMA_CH_SBR_MID_MASK (0x0f << EDMA_CH_SBR_MID_SHIFT)
+ /* Bits 4-14: Reserved */
+#define EDMA_CH_SBR_PAL (1 << 15) /* Bit 15: Privileged Access Level (PAL) */
+#define EDMA_CH_SBR_EMI (1 << 16) /* Bit 16: Enable Master ID Replication (EMI) */
+#define EDMA_CH_SBR_ATTR_SHIFT (17) /* Bits 17-19: Attribute Output (ATTR) */
+#define EDMA_CH_SBR_ATTR_MASK (0x07 << EDMA_CH_SBR_ATTR_SHIFT)
+ /* Bits 20-31: Reserved */
+
+/* Channel n Priority Register (CHn_PRI) */
+
+#define EDMA_CH_PRI_APL_SHIFT (0) /* Bits 0-2: Arbitration Priority Level (APL) */
+#define EDMA_CH_PRI_APL_MASK (0x07 << EDMA_CH_PRI_APL_SHIFT)
+ /* Bits 3-29: Reserved */
+#define EDMA_CH_PRI_DPA (1 << 30) /* Bit 30: Disable Preempt Ability (DPA) */
+#define EDMA_CH_PRI_ECP (1 << 31) /* Bit 31: Enable Channel Preemption (ECP) */
+
+/* TCDn Source Address Register (TCDn_SADDR) */
+
+#define EDMA_TCD_SADDR_SHIFT (0) /* Bits 0-31: Source Address (SADDR) */
+#define EDMA_TCD_SADDR_MASK (0xffffffff << EDMA_TCD_SADDR_SHIFT)
+
+/* TCDn Signed Source Address Offset Register (TCDn_SOFF) */
+
+#define EDMA_TCD_SOFF_SHIFT (0) /* Bits 0-31: Source Address Signed Offset (SOFF) */
+#define EDMA_TCD_SOFF_MASK (0xffffffff << EDMA_TCD_SOFF_SHIFT)
+
+/* TCDn Transfer Attributes (TCDn_ATTR) */
+
+#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */
+#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT)
+#define EDMA_TCD_ATTR_DSIZE(n) ((n << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK)
+#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */
+#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT)
+#define EDMA_TCD_ATTR_DMOD(n) ((n << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK)
+#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */
+#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT)
+#define EDMA_TCD_ATTR_SSIZE(n) ((n << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK)
+# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
+# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
+# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
+# define EDMA_TCD_ATTR_SSIZE_64BIT (0x03 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */
+# define EDMA_TCD_ATTR_SSIZE_16BYTE (0x04 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */
+# define EDMA_TCD_ATTR_SSIZE_32BYTE (0x05 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte */
+# define EDMA_TCD_ATTR_SSIZE_64BYTE (0x06 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-byte */
+
+#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */
+#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT)
+#define EDMA_TCD_ATTR_SMOD(n) ((n << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK)
Review Comment:
```suggestion
#define EDMA_TCD_ATTR_SMOD(n) (((n) << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK)
```
##########
net/can/can_input.c:
##########
@@ -155,48 +155,44 @@ int can_input(struct net_driver_s *dev)
{
FAR struct can_conn_s *conn = NULL;
int ret = OK;
+ uint16_t buflen = dev->d_len;
do
{
- /* FIXME Support for multiple sockets??? */
-
conn = can_nextconn(conn);
- }
- while (conn && conn->dev != 0 && dev != conn->dev);
-
- if (conn)
- {
- uint16_t flags;
- /* Setup for the application callback */
+ if (conn && (conn->dev == 0x0 || dev == conn->dev))
Review Comment:
```suggestion
if (conn && (conn->dev == NULL || dev == conn->dev))
```
##########
drivers/mtd/mx25rxx.c:
##########
@@ -100,7 +100,11 @@
/* JEDEC Read ID register values */
#define MX25R_JEDEC_MANUFACTURER 0xc2 /* Macronix manufacturer ID */
+#ifdef CONFIG_MX25RXX_LXX
+#define MX25R_JEDEC_MEMORY_TYPE 0x20 /* MX25Lx memory type */
+#else
#define MX25R_JEDEC_MEMORY_TYPE 0x28 /* MX25Rx memory type */
Review Comment:
```suggestion
# define MX25R_JEDEC_MEMORY_TYPE 0x28 /* MX25Rx memory type */
```
##########
boards/arm/s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c:
##########
@@ -0,0 +1,157 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+
+#include "s32k3xx_clockconfig.h"
+#include "s32k3xx_start.h"
+
+#include "s32k344evb.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Each S32K3XX board must provide the following initialized structure.
+ * This is needed to establish the initial board clocking.
+ */
+
+const struct clock_configuration_s g_initial_clkconfig =
+{
+ .cgm =
+ {
+ .sirc =
+ {
+ .range = CGM_FIRC_RANGE_32K, /* Slow IRC is trimmed to 32 kHz */
+ },
+ .firc =
+ {
+ .range = CGM_FIRC_RANGE_HIGH, /* RANGE */
+ .div = CGM_CLOCK_DIV_BY_1, /* FIRCDIV1 */
+ },
+ .scs =
+ {
+ .scs_source = CGM_SCS_SOURCE_PLL_PHI0,
+ .core_clk =
+ {
+ .div = CGM_MUX_DIV_BY_1,
+ .trigger = false,
+ },
+ .aips_plat_clk =
+ {
+ .div = CGM_MUX_DIV_BY_2,
+ .trigger = false,
Review Comment:
Optional: `false` init is redundant
##########
boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c:
##########
@@ -0,0 +1,124 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <nuttx/board.h>
+
+#include "s32k3xx_pin.h"
+
+#include <arch/board/board.h>
+
+#include "s32k344evb.h"
+
+#ifndef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_userled_initialize
+ ****************************************************************************/
+
+uint32_t board_userled_initialize(void)
+{
+ /* Configure LED GPIOs for output */
+
+ s32k3xx_pinconfig(GPIO_LED0_R);
+ s32k3xx_pinconfig(GPIO_LED0_G);
+ s32k3xx_pinconfig(GPIO_LED0_B);
+
+ s32k3xx_pinconfig(GPIO_LED1_R);
+ s32k3xx_pinconfig(GPIO_LED1_G);
+ s32k3xx_pinconfig(GPIO_LED1_B);
+
+ return BOARD_NLEDS;
+}
+
+/****************************************************************************
+ * Name: board_userled
+ ****************************************************************************/
+
+void board_userled(int led, bool ledon)
+{
+ uint32_t ledcfg;
+
+ if (led == BOARD_LED0_R)
Review Comment:
better to use switch/case
##########
drivers/mtd/mx25rxx.c:
##########
@@ -112,7 +116,12 @@
#define MX25R6435F_SECTOR_SHIFT (12)
#define MX25R6435F_SECTOR_COUNT (2048)
#define MX25R6435F_PAGE_SIZE (256)
+
+#ifdef CONFIG_MX25RXX_PAGE128
+#define MX25R6435F_PAGE_SHIFT (7)
Review Comment:
```suggestion
# define MX25R6435F_PAGE_SHIFT (7)
```
##########
boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c:
##########
@@ -0,0 +1,82 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/board.h>
+
+#include <stdint.h>
+
+#include "s32k344evb.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef OK
+# define OK 0
+#endif
Review Comment:
is this really needed?
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h:
##########
@@ -0,0 +1,3084 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EMAC_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EMAC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* EMAC Register Offsets ****************************************************/
+
+#define S32K3XX_EMAC_MAC_CONFIGURATION_OFFSET (0x0000)
+#define S32K3XX_EMAC_MAC_EXT_CONFIGURATION_OFFSET (0x0004)
+#define S32K3XX_EMAC_MAC_PACKET_FILTER_OFFSET (0x0008)
+#define S32K3XX_EMAC_MAC_WATCHDOG_TIMEOUT_OFFSET (0x000c)
+#define S32K3XX_EMAC_MAC_HASH_TABLE_REG0_OFFSET (0x0010)
+#define S32K3XX_EMAC_MAC_HASH_TABLE_REG1_OFFSET (0x0014)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_OFFSET (0x0050)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_CTRL_OFFSET (0x0050)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_DATA_OFFSET (0x0054)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER0_OFFSET (0x0054)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER1_OFFSET (0x0054)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER2_OFFSET (0x0054)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER3_OFFSET (0x0054)
+#define S32K3XX_EMAC_MAC_VLAN_HASH_TABLE_OFFSET (0x0058)
+#define S32K3XX_EMAC_MAC_VLAN_INCL_OFFSET (0x0060)
+#define S32K3XX_EMAC_MAC_INNER_VLAN_INCL_OFFSET (0x0064)
+#define S32K3XX_EMAC_MAC_Q0_TX_FLOW_CTRL_OFFSET (0x0070)
+#define S32K3XX_EMAC_MAC_RX_FLOW_CTRL_OFFSET (0x0090)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL4_OFFSET (0x0094)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL0_OFFSET (0x00a0)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL1_OFFSET (0x00a4)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL2_OFFSET (0x00a8)
+#define S32K3XX_EMAC_MAC_INTERRUPT_STATUS_OFFSET (0x00b0)
+#define S32K3XX_EMAC_MAC_INTERRUPT_ENABLE_OFFSET (0x00b4)
+#define S32K3XX_EMAC_MAC_RX_TX_STATUS_OFFSET (0x00b8)
+#define S32K3XX_EMAC_MAC_VERSION_OFFSET (0x0110)
+#define S32K3XX_EMAC_MAC_DEBUG_OFFSET (0x0114)
+#define S32K3XX_EMAC_MAC_HW_FEATURE0_OFFSET (0x011c)
+#define S32K3XX_EMAC_MAC_HW_FEATURE1_OFFSET (0x0120)
+#define S32K3XX_EMAC_MAC_HW_FEATURE2_OFFSET (0x0124)
+#define S32K3XX_EMAC_MAC_HW_FEATURE3_OFFSET (0x0128)
+#define S32K3XX_EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_OFFSET (0x0140)
+#define S32K3XX_EMAC_MAC_FSM_CONTROL_OFFSET (0x0148)
+#define S32K3XX_EMAC_MAC_FSM_ACT_TIMER_OFFSET (0x014c)
+#define S32K3XX_EMAC_SCS_REG1_OFFSET (0x0150)
+#define S32K3XX_EMAC_MAC_MDIO_ADDRESS_OFFSET (0x0200)
+#define S32K3XX_EMAC_MAC_MDIO_DATA_OFFSET (0x0204)
+#define S32K3XX_EMAC_MAC_CSR_SW_CTRL_OFFSET (0x0230)
+#define S32K3XX_EMAC_MAC_FPE_CTRL_STS_OFFSET (0x0234)
+#define S32K3XX_EMAC_MAC_PRESN_TIME_NS_OFFSET (0x0240)
+#define S32K3XX_EMAC_MAC_PRESN_TIME_UPDT_OFFSET (0x0244)
+#define S32K3XX_EMAC_MAC_ADDRESS0_HIGH_OFFSET (0x0300)
+#define S32K3XX_EMAC_MAC_ADDRESS0_LOW_OFFSET (0x0304)
+#define S32K3XX_EMAC_MAC_ADDRESS1_HIGH_OFFSET (0x0308)
+#define S32K3XX_EMAC_MAC_ADDRESS1_LOW_OFFSET (0x030c)
+#define S32K3XX_EMAC_MAC_ADDRESS2_HIGH_OFFSET (0x0310)
+#define S32K3XX_EMAC_MAC_ADDRESS2_LOW_OFFSET (0x0314)
+#define S32K3XX_EMAC_MMC_CONTROL_OFFSET (0x0700)
+#define S32K3XX_EMAC_MMC_RX_INTERRUPT_OFFSET (0x0704)
+#define S32K3XX_EMAC_MMC_TX_INTERRUPT_OFFSET (0x0708)
+#define S32K3XX_EMAC_MMC_RX_INTERRUPT_MASK_OFFSET (0x070c)
+#define S32K3XX_EMAC_MMC_TX_INTERRUPT_MASK_OFFSET (0x0710)
+#define S32K3XX_EMAC_TX_OCTET_COUNT_GOOD_BAD_OFFSET (0x0714)
+#define S32K3XX_EMAC_TX_PACKET_COUNT_GOOD_BAD_OFFSET (0x0718)
+#define S32K3XX_EMAC_TX_BROADCAST_PACKETS_GOOD_OFFSET (0x071c)
+#define S32K3XX_EMAC_TX_MULTICAST_PACKETS_GOOD_OFFSET (0x0720)
+#define S32K3XX_EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_OFFSET (0x0724)
+#define S32K3XX_EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_OFFSET (0x0728)
+#define S32K3XX_EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_OFFSET (0x072c)
+#define S32K3XX_EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_OFFSET (0x0730)
+#define S32K3XX_EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_OFFSET (0x0734)
+#define S32K3XX_EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_OFFSET (0x0738)
+#define S32K3XX_EMAC_TX_UNICAST_PACKETS_GOOD_BAD_OFFSET (0x073c)
+#define S32K3XX_EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_OFFSET (0x0740)
+#define S32K3XX_EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_OFFSET (0x0744)
+#define S32K3XX_EMAC_TX_UNDERFLOW_ERROR_PACKETS_OFFSET (0x0748)
+#define S32K3XX_EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_OFFSET (0x074c)
+#define S32K3XX_EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_OFFSET (0x0750)
+#define S32K3XX_EMAC_TX_DEFERRED_PACKETS_OFFSET (0x0754)
+#define S32K3XX_EMAC_TX_LATE_COLLISION_PACKETS_OFFSET (0x0758)
+#define S32K3XX_EMAC_TX_EXCESSIVE_COLLISION_PACKETS_OFFSET (0x075c)
+#define S32K3XX_EMAC_TX_CARRIER_ERROR_PACKETS_OFFSET (0x0760)
+#define S32K3XX_EMAC_TX_OCTET_COUNT_GOOD_OFFSET (0x0764)
+#define S32K3XX_EMAC_TX_PACKET_COUNT_GOOD_OFFSET (0x0768)
+#define S32K3XX_EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_OFFSET (0x076c)
+#define S32K3XX_EMAC_TX_PAUSE_PACKETS_OFFSET (0x0770)
+#define S32K3XX_EMAC_TX_VLAN_PACKETS_GOOD_OFFSET (0x0774)
+#define S32K3XX_EMAC_TX_OSIZE_PACKETS_GOOD_OFFSET (0x0778)
+#define S32K3XX_EMAC_RX_PACKETS_COUNT_GOOD_BAD_OFFSET (0x0780)
+#define S32K3XX_EMAC_RX_OCTET_COUNT_GOOD_BAD_OFFSET (0x0784)
+#define S32K3XX_EMAC_RX_OCTET_COUNT_GOOD_OFFSET (0x0788)
+#define S32K3XX_EMAC_RX_BROADCAST_PACKETS_GOOD_OFFSET (0x078c)
+#define S32K3XX_EMAC_RX_MULTICAST_PACKETS_GOOD_OFFSET (0x0790)
+#define S32K3XX_EMAC_RX_CRC_ERROR_PACKETS_OFFSET (0x0794)
+#define S32K3XX_EMAC_RX_ALIGNMENT_ERROR_PACKETS_OFFSET (0x0798)
+#define S32K3XX_EMAC_RX_RUNT_ERROR_PACKETS_OFFSET (0x079c)
+#define S32K3XX_EMAC_RX_JABBER_ERROR_PACKETS_OFFSET (0x07a0)
+#define S32K3XX_EMAC_RX_UNDERSIZE_PACKETS_GOOD_OFFSET (0x07a4)
+#define S32K3XX_EMAC_RX_OVERSIZE_PACKETS_GOOD_OFFSET (0x07a8)
+#define S32K3XX_EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_OFFSET (0x07ac)
+#define S32K3XX_EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_OFFSET (0x07b0)
+#define S32K3XX_EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_OFFSET (0x07b4)
+#define S32K3XX_EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_OFFSET (0x07b8)
+#define S32K3XX_EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_OFFSET (0x07bc)
+#define S32K3XX_EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_OFFSET (0x07c0)
+#define S32K3XX_EMAC_RX_UNICAST_PACKETS_GOOD_OFFSET (0x07c4)
+#define S32K3XX_EMAC_RX_LENGTH_ERROR_PACKETS_OFFSET (0x07c8)
+#define S32K3XX_EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_OFFSET (0x07cc)
+#define S32K3XX_EMAC_RX_PAUSE_PACKETS_OFFSET (0x07d0)
+#define S32K3XX_EMAC_RX_FIFO_OVERFLOW_PACKETS_OFFSET (0x07d4)
+#define S32K3XX_EMAC_RX_VLAN_PACKETS_GOOD_BAD_OFFSET (0x07d8)
+#define S32K3XX_EMAC_RX_WATCHDOG_ERROR_PACKETS_OFFSET (0x07dc)
+#define S32K3XX_EMAC_RX_RECEIVE_ERROR_PACKETS_OFFSET (0x07e0)
+#define S32K3XX_EMAC_RX_CONTROL_PACKETS_GOOD_OFFSET (0x07e4)
+#define S32K3XX_EMAC_MMC_FPE_TX_INTERRUPT_OFFSET (0x08a0)
+#define S32K3XX_EMAC_MMC_FPE_TX_INTERRUPT_MASK_OFFSET (0x08a4)
+#define S32K3XX_EMAC_MMC_TX_FPE_FRAGMENT_CNTR_OFFSET (0x08a8)
+#define S32K3XX_EMAC_MMC_TX_HOLD_REQ_CNTR_OFFSET (0x08ac)
+#define S32K3XX_EMAC_MMC_FPE_RX_INTERRUPT_OFFSET (0x08c0)
+#define S32K3XX_EMAC_MMC_FPE_RX_INTERRUPT_MASK_OFFSET (0x08c4)
+#define S32K3XX_EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_OFFSET (0x08c8)
+#define S32K3XX_EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_OFFSET (0x08cc)
+#define S32K3XX_EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_OFFSET (0x08d0)
+#define S32K3XX_EMAC_MMC_RX_FPE_FRAGMENT_CNTR_OFFSET (0x08d4)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL0_OFFSET (0x0900)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS0_OFFSET (0x0904)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG0_OFFSET (0x0910)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG0_OFFSET (0x0914)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG0_OFFSET (0x0918)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG0_OFFSET (0x091c)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL1_OFFSET (0x0930)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS1_OFFSET (0x0934)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG1_OFFSET (0x0940)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG1_OFFSET (0x0944)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG1_OFFSET (0x0948)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG1_OFFSET (0x094c)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL2_OFFSET (0x0960)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS2_OFFSET (0x0964)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG2_OFFSET (0x0970)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG2_OFFSET (0x0974)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG2_OFFSET (0x0978)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG2_OFFSET (0x097c)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL3_OFFSET (0x0990)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS3_OFFSET (0x0994)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG3_OFFSET (0x09a0)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG3_OFFSET (0x09a4)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG3_OFFSET (0x09a8)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG3_OFFSET (0x09ac)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_CONTROL_OFFSET (0x0b00)
+#define S32K3XX_EMAC_MAC_SUB_SECOND_INCREMENT_OFFSET (0x0b04)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_SECONDS_OFFSET (0x0b08)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_NANOSECONDS_OFFSET (0x0b0c)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_OFFSET (0x0b10)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_OFFSET (0x0b14)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_ADDEND_OFFSET (0x0b18)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_OFFSET (0x0b1c)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_STATUS_OFFSET (0x0b20)
+#define S32K3XX_EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_OFFSET (0x0b30)
+#define S32K3XX_EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_OFFSET (0x0b34)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OFFSET (0x0b50)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OFFSET (0x0b54)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_OFFSET (0x0b58)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_OFFSET (0x0b5c)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_OFFSET (0x0b60)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_OFFSET (0x0b64)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_OFFSET (0x0b68)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_OFFSET (0x0b6c)
+#define S32K3XX_EMAC_MAC_PPS_CONTROL_OFFSET (0x0b70)
+#define S32K3XX_EMAC_MAC_PPS0_TARGET_TIME_SECONDS_OFFSET (0x0b80)
+#define S32K3XX_EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_OFFSET (0x0b84)
+#define S32K3XX_EMAC_MAC_PPS0_INTERVAL_OFFSET (0x0b88)
+#define S32K3XX_EMAC_MAC_PPS0_WIDTH_OFFSET (0x0b8c)
+#define S32K3XX_EMAC_MAC_PPS1_TARGET_TIME_SECONDS_OFFSET (0x0b90)
+#define S32K3XX_EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_OFFSET (0x0b94)
+#define S32K3XX_EMAC_MAC_PPS1_INTERVAL_OFFSET (0x0b98)
+#define S32K3XX_EMAC_MAC_PPS1_WIDTH_OFFSET (0x0b9c)
+#define S32K3XX_EMAC_MAC_PPS2_TARGET_TIME_SECONDS_OFFSET (0x0ba0)
+#define S32K3XX_EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_OFFSET (0x0ba4)
+#define S32K3XX_EMAC_MAC_PPS2_INTERVAL_OFFSET (0x0ba8)
+#define S32K3XX_EMAC_MAC_PPS2_WIDTH_OFFSET (0x0bac)
+#define S32K3XX_EMAC_MAC_PPS3_TARGET_TIME_SECONDS_OFFSET (0x0bb0)
+#define S32K3XX_EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_OFFSET (0x0bb4)
+#define S32K3XX_EMAC_MAC_PPS3_INTERVAL_OFFSET (0x0bb8)
+#define S32K3XX_EMAC_MAC_PPS3_WIDTH_OFFSET (0x0bbc)
+#define S32K3XX_EMAC_MTL_OPERATION_MODE_OFFSET (0x0c00)
+#define S32K3XX_EMAC_MTL_DBG_CTL_OFFSET (0x0c08)
+#define S32K3XX_EMAC_MTL_DBG_STS_OFFSET (0x0c0c)
+#define S32K3XX_EMAC_MTL_FIFO_DEBUG_DATA_OFFSET (0x0c10)
+#define S32K3XX_EMAC_MTL_INTERRUPT_STATUS_OFFSET (0x0c20)
+#define S32K3XX_EMAC_MTL_RXQ_DMA_MAP0_OFFSET (0x0c30)
+#define S32K3XX_EMAC_MTL_TBS_CTRL_OFFSET (0x0c40)
+#define S32K3XX_EMAC_MTL_EST_CONTROL_OFFSET (0x0c50)
+#define S32K3XX_EMAC_MTL_EST_STATUS_OFFSET (0x0c58)
+#define S32K3XX_EMAC_MTL_EST_SCH_ERROR_OFFSET (0x0c60)
+#define S32K3XX_EMAC_MTL_EST_FRM_SIZE_ERROR_OFFSET (0x0c64)
+#define S32K3XX_EMAC_MTL_EST_FRM_SIZE_CAPTURE_OFFSET (0x0c68)
+#define S32K3XX_EMAC_MTL_EST_INTR_ENABLE_OFFSET (0x0c70)
+#define S32K3XX_EMAC_MTL_EST_GCL_CONTROL_OFFSET (0x0c80)
+#define S32K3XX_EMAC_MTL_EST_GCL_DATA_OFFSET (0x0c84)
+#define S32K3XX_EMAC_MTL_FPE_CTRL_STS_OFFSET (0x0c90)
+#define S32K3XX_EMAC_MTL_FPE_ADVANCE_OFFSET (0x0c94)
+#define S32K3XX_EMAC_MTL_RXP_CONTROL_STATUS_OFFSET (0x0ca0)
+#define S32K3XX_EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_OFFSET (0x0ca4)
+#define S32K3XX_EMAC_MTL_RXP_DROP_CNT_OFFSET (0x0ca8)
+#define S32K3XX_EMAC_MTL_RXP_ERROR_CNT_OFFSET (0x0cac)
+#define S32K3XX_EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_OFFSET (0x0cb0)
+#define S32K3XX_EMAC_MTL_RXP_INDIRECT_ACC_DATA_OFFSET (0x0cb4)
+#define S32K3XX_EMAC_MTL_ECC_CONTROL_OFFSET (0x0cc0)
+#define S32K3XX_EMAC_MTL_SAFETY_INTERRUPT_STATUS_OFFSET (0x0cc4)
+#define S32K3XX_EMAC_MTL_ECC_INTERRUPT_ENABLE_OFFSET (0x0cc8)
+#define S32K3XX_EMAC_MTL_ECC_INTERRUPT_STATUS_OFFSET (0x0ccc)
+#define S32K3XX_EMAC_MTL_ECC_ERR_STS_RCTL_OFFSET (0x0cd0)
+#define S32K3XX_EMAC_MTL_ECC_ERR_ADDR_STATUS_OFFSET (0x0cd4)
+#define S32K3XX_EMAC_MTL_ECC_ERR_CNTR_STATUS_OFFSET (0x0cd8)
+#define S32K3XX_EMAC_MTL_DPP_CONTROL_OFFSET (0x0ce0)
+#define S32K3XX_EMAC_MTL_TXQ0_OPERATION_MODE_OFFSET (0x0d00)
+#define S32K3XX_EMAC_MTL_TXQ0_UNDERFLOW_OFFSET (0x0d04)
+#define S32K3XX_EMAC_MTL_TXQ0_DEBUG_OFFSET (0x0d08)
+#define S32K3XX_EMAC_MTL_TXQ0_ETS_STATUS_OFFSET (0x0d14)
+#define S32K3XX_EMAC_MTL_TXQ0_QUANTUM_WEIGHT_OFFSET (0x0d18)
+#define S32K3XX_EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_OFFSET (0x0d2c)
+#define S32K3XX_EMAC_MTL_RXQ0_OPERATION_MODE_OFFSET (0x0d30)
+#define S32K3XX_EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OFFSET (0x0d34)
+#define S32K3XX_EMAC_MTL_RXQ0_DEBUG_OFFSET (0x0d38)
+#define S32K3XX_EMAC_MTL_RXQ0_CONTROL_OFFSET (0x0d3c)
+#define S32K3XX_EMAC_MTL_TXQ1_OPERATION_MODE_OFFSET (0x0d40)
+#define S32K3XX_EMAC_MTL_TXQ1_UNDERFLOW_OFFSET (0x0d44)
+#define S32K3XX_EMAC_MTL_TXQ1_DEBUG_OFFSET (0x0d48)
+#define S32K3XX_EMAC_MTL_TXQ1_ETS_CONTROL_OFFSET (0x0d50)
+#define S32K3XX_EMAC_MTL_TXQ1_ETS_STATUS_OFFSET (0x0d54)
+#define S32K3XX_EMAC_MTL_TXQ1_QUANTUM_WEIGHT_OFFSET (0x0d58)
+#define S32K3XX_EMAC_MTL_TXQ1_SENDSLOPECREDIT_OFFSET (0x0d5c)
+#define S32K3XX_EMAC_MTL_TXQ1_HICREDIT_OFFSET (0x0d60)
+#define S32K3XX_EMAC_MTL_TXQ1_LOCREDIT_OFFSET (0x0d64)
+#define S32K3XX_EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_OFFSET (0x0d6c)
+#define S32K3XX_EMAC_MTL_RXQ1_OPERATION_MODE_OFFSET (0x0d70)
+#define S32K3XX_EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OFFSET (0x0d74)
+#define S32K3XX_EMAC_MTL_RXQ1_DEBUG_OFFSET (0x0d78)
+#define S32K3XX_EMAC_MTL_RXQ1_CONTROL_OFFSET (0x0d7c)
+#define S32K3XX_EMAC_DMA_MODE_OFFSET (0x1000)
+#define S32K3XX_EMAC_DMA_SYSBUS_MODE_OFFSET (0x1004)
+#define S32K3XX_EMAC_DMA_INTERRUPT_STATUS_OFFSET (0x1008)
+#define S32K3XX_EMAC_DMA_DEBUG_STATUS0_OFFSET (0x100c)
+#define S32K3XX_EMAC_DMA_TBS_CTRL_OFFSET (0x1050)
+#define S32K3XX_EMAC_DMA_SAFETY_INTERRUPT_STATUS_OFFSET (0x1080)
+#define S32K3XX_EMAC_DMA_CH0_CONTROL_OFFSET (0x1100)
+#define S32K3XX_EMAC_DMA_CH0_TX_CONTROL_OFFSET (0x1104)
+#define S32K3XX_EMAC_DMA_CH0_RX_CONTROL_OFFSET (0x1108)
+#define S32K3XX_EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_OFFSET (0x1114)
+#define S32K3XX_EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_OFFSET (0x111c)
+#define S32K3XX_EMAC_DMA_CH0_TXDESC_TAIL_POINTER_OFFSET (0x1120)
+#define S32K3XX_EMAC_DMA_CH0_RXDESC_TAIL_POINTER_OFFSET (0x1128)
+#define S32K3XX_EMAC_DMA_CH0_TXDESC_RING_LENGTH_OFFSET (0x112c)
+#define S32K3XX_EMAC_DMA_CH0_RXDESC_RING_LENGTH_OFFSET (0x1130)
+#define S32K3XX_EMAC_DMA_CH0_INTERRUPT_ENABLE_OFFSET (0x1134)
+#define S32K3XX_EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_OFFSET (0x1138)
+#define S32K3XX_EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_OFFSET (0x113c)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_TXDESC_OFFSET (0x1144)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_RXDESC_OFFSET (0x114c)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_OFFSET (0x1154)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_OFFSET (0x115c)
+#define S32K3XX_EMAC_DMA_CH0_STATUS_OFFSET (0x1160)
+#define S32K3XX_EMAC_DMA_CH0_MISS_FRAME_CNT_OFFSET (0x1164)
+#define S32K3XX_EMAC_DMA_CH0_RXP_ACCEPT_CNT_OFFSET (0x1168)
+#define S32K3XX_EMAC_DMA_CH0_RX_ERI_CNT_OFFSET (0x116c)
+#define S32K3XX_EMAC_DMA_CH1_CONTROL_OFFSET (0x1180)
+#define S32K3XX_EMAC_DMA_CH1_TX_CONTROL_OFFSET (0x1184)
+#define S32K3XX_EMAC_DMA_CH1_RX_CONTROL_OFFSET (0x1188)
+#define S32K3XX_EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_OFFSET (0x1194)
+#define S32K3XX_EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_OFFSET (0x119c)
+#define S32K3XX_EMAC_DMA_CH1_TXDESC_TAIL_POINTER_OFFSET (0x11a0)
+#define S32K3XX_EMAC_DMA_CH1_RXDESC_TAIL_POINTER_OFFSET (0x11a8)
+#define S32K3XX_EMAC_DMA_CH1_TXDESC_RING_LENGTH_OFFSET (0x11ac)
+#define S32K3XX_EMAC_DMA_CH1_RXDESC_RING_LENGTH_OFFSET (0x11b0)
+#define S32K3XX_EMAC_DMA_CH1_INTERRUPT_ENABLE_OFFSET (0x11b4)
+#define S32K3XX_EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_OFFSET (0x11b8)
+#define S32K3XX_EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_OFFSET (0x11bc)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_TXDESC_OFFSET (0x11c4)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_RXDESC_OFFSET (0x11cc)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_OFFSET (0x11d4)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_OFFSET (0x11dc)
+#define S32K3XX_EMAC_DMA_CH1_STATUS_OFFSET (0x11e0)
+#define S32K3XX_EMAC_DMA_CH1_MISS_FRAME_CNT_OFFSET (0x11e4)
+#define S32K3XX_EMAC_DMA_CH1_RXP_ACCEPT_CNT_OFFSET (0x11e8)
+#define S32K3XX_EMAC_DMA_CH1_RX_ERI_CNT_OFFSET (0x11ec)
+
+/* EMAC Register Addresses **************************************************/
+
+#define S32K3XX_EMAC_MAC_CONFIGURATION (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_CONFIGURATION_OFFSET)
+#define S32K3XX_EMAC_MAC_EXT_CONFIGURATION (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_EXT_CONFIGURATION_OFFSET)
+#define S32K3XX_EMAC_MAC_PACKET_FILTER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PACKET_FILTER_OFFSET)
+#define S32K3XX_EMAC_MAC_WATCHDOG_TIMEOUT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_WATCHDOG_TIMEOUT_OFFSET)
+#define S32K3XX_EMAC_MAC_HASH_TABLE_REG0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_HASH_TABLE_REG0_OFFSET)
+#define S32K3XX_EMAC_MAC_HASH_TABLE_REG1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_HASH_TABLE_REG1_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_TAG (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_TAG_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_CTRL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_TAG_CTRL_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_DATA (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_TAG_DATA_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_TAG_FILTER0_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_TAG_FILTER1_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_TAG_FILTER2_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_TAG_FILTER3_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_HASH_TABLE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_HASH_TABLE_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_INCL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_INCL_OFFSET)
+#define S32K3XX_EMAC_MAC_INNER_VLAN_INCL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_INNER_VLAN_INCL_OFFSET)
+#define S32K3XX_EMAC_MAC_Q0_TX_FLOW_CTRL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_Q0_TX_FLOW_CTRL_OFFSET)
+#define S32K3XX_EMAC_MAC_RX_FLOW_CTRL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_RX_FLOW_CTRL_OFFSET)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL4 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_RXQ_CTRL4_OFFSET)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_RXQ_CTRL0_OFFSET)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_RXQ_CTRL1_OFFSET)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_RXQ_CTRL2_OFFSET)
+#define S32K3XX_EMAC_MAC_INTERRUPT_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_INTERRUPT_STATUS_OFFSET)
+#define S32K3XX_EMAC_MAC_INTERRUPT_ENABLE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_INTERRUPT_ENABLE_OFFSET)
+#define S32K3XX_EMAC_MAC_RX_TX_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_RX_TX_STATUS_OFFSET)
+#define S32K3XX_EMAC_MAC_VERSION (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VERSION_OFFSET)
+#define S32K3XX_EMAC_MAC_DEBUG (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_DEBUG_OFFSET)
+#define S32K3XX_EMAC_MAC_HW_FEATURE0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_HW_FEATURE0_OFFSET)
+#define S32K3XX_EMAC_MAC_HW_FEATURE1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_HW_FEATURE1_OFFSET)
+#define S32K3XX_EMAC_MAC_HW_FEATURE2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_HW_FEATURE2_OFFSET)
+#define S32K3XX_EMAC_MAC_HW_FEATURE3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_HW_FEATURE3_OFFSET)
+#define S32K3XX_EMAC_MAC_DPP_FSM_INTERRUPT_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_OFFSET)
+#define S32K3XX_EMAC_MAC_FSM_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_FSM_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MAC_FSM_ACT_TIMER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_FSM_ACT_TIMER_OFFSET)
+#define S32K3XX_EMAC_SCS_REG1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_SCS_REG1_OFFSET)
+#define S32K3XX_EMAC_MAC_MDIO_ADDRESS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_MDIO_ADDRESS_OFFSET)
+#define S32K3XX_EMAC_MAC_MDIO_DATA (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_MDIO_DATA_OFFSET)
+#define S32K3XX_EMAC_MAC_CSR_SW_CTRL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_CSR_SW_CTRL_OFFSET)
+#define S32K3XX_EMAC_MAC_FPE_CTRL_STS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_FPE_CTRL_STS_OFFSET)
+#define S32K3XX_EMAC_MAC_PRESN_TIME_NS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PRESN_TIME_NS_OFFSET)
+#define S32K3XX_EMAC_MAC_PRESN_TIME_UPDT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PRESN_TIME_UPDT_OFFSET)
+#define S32K3XX_EMAC_MAC_ADDRESS0_HIGH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_ADDRESS0_HIGH_OFFSET)
+#define S32K3XX_EMAC_MAC_ADDRESS0_LOW (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_ADDRESS0_LOW_OFFSET)
+#define S32K3XX_EMAC_MAC_ADDRESS1_HIGH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_ADDRESS1_HIGH_OFFSET)
+#define S32K3XX_EMAC_MAC_ADDRESS1_LOW (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_ADDRESS1_LOW_OFFSET)
+#define S32K3XX_EMAC_MAC_ADDRESS2_HIGH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_ADDRESS2_HIGH_OFFSET)
+#define S32K3XX_EMAC_MAC_ADDRESS2_LOW (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_ADDRESS2_LOW_OFFSET)
+#define S32K3XX_EMAC_MMC_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MMC_RX_INTERRUPT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_RX_INTERRUPT_OFFSET)
+#define S32K3XX_EMAC_MMC_TX_INTERRUPT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_TX_INTERRUPT_OFFSET)
+#define S32K3XX_EMAC_MMC_RX_INTERRUPT_MASK (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_RX_INTERRUPT_MASK_OFFSET)
+#define S32K3XX_EMAC_MMC_TX_INTERRUPT_MASK (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_TX_INTERRUPT_MASK_OFFSET)
+#define S32K3XX_EMAC_TX_OCTET_COUNT_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_OCTET_COUNT_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_PACKET_COUNT_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_PACKET_COUNT_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_BROADCAST_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_BROADCAST_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_TX_MULTICAST_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_MULTICAST_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_TX_64OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_UNICAST_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_UNICAST_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_MULTICAST_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_BROADCAST_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_UNDERFLOW_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_UNDERFLOW_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_DEFERRED_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_DEFERRED_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_LATE_COLLISION_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_LATE_COLLISION_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_EXCESSIVE_COLLISION_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_EXCESSIVE_COLLISION_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_CARRIER_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_CARRIER_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_OCTET_COUNT_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_OCTET_COUNT_GOOD_OFFSET)
+#define S32K3XX_EMAC_TX_PACKET_COUNT_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_PACKET_COUNT_GOOD_OFFSET)
+#define S32K3XX_EMAC_TX_EXCESSIVE_DEFERRAL_ERROR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_OFFSET)
+#define S32K3XX_EMAC_TX_PAUSE_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_PAUSE_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_VLAN_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_VLAN_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_TX_OSIZE_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_OSIZE_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_RX_PACKETS_COUNT_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_PACKETS_COUNT_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_OCTET_COUNT_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_OCTET_COUNT_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_OCTET_COUNT_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_OCTET_COUNT_GOOD_OFFSET)
+#define S32K3XX_EMAC_RX_BROADCAST_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_BROADCAST_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_RX_MULTICAST_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_MULTICAST_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_RX_CRC_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_CRC_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_ALIGNMENT_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_ALIGNMENT_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_RUNT_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_RUNT_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_JABBER_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_JABBER_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_UNDERSIZE_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_UNDERSIZE_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_RX_OVERSIZE_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_OVERSIZE_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_RX_64OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_UNICAST_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_UNICAST_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_RX_LENGTH_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_LENGTH_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_PAUSE_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_PAUSE_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_FIFO_OVERFLOW_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_FIFO_OVERFLOW_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_VLAN_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_VLAN_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_WATCHDOG_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_WATCHDOG_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_RECEIVE_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_RECEIVE_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_CONTROL_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_CONTROL_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_MMC_FPE_TX_INTERRUPT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_FPE_TX_INTERRUPT_OFFSET)
+#define S32K3XX_EMAC_MMC_FPE_TX_INTERRUPT_MASK (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_FPE_TX_INTERRUPT_MASK_OFFSET)
+#define S32K3XX_EMAC_MMC_TX_FPE_FRAGMENT_CNTR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_TX_FPE_FRAGMENT_CNTR_OFFSET)
+#define S32K3XX_EMAC_MMC_TX_HOLD_REQ_CNTR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_TX_HOLD_REQ_CNTR_OFFSET)
+#define S32K3XX_EMAC_MMC_FPE_RX_INTERRUPT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_FPE_RX_INTERRUPT_OFFSET)
+#define S32K3XX_EMAC_MMC_FPE_RX_INTERRUPT_MASK (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_FPE_RX_INTERRUPT_MASK_OFFSET)
+#define S32K3XX_EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_OFFSET)
+#define S32K3XX_EMAC_MMC_RX_PACKET_SMD_ERR_CNTR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_OFFSET)
+#define S32K3XX_EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_OFFSET)
+#define S32K3XX_EMAC_MMC_RX_FPE_FRAGMENT_CNTR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_RX_FPE_FRAGMENT_CNTR_OFFSET)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_L3_L4_CONTROL0_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER4_ADDRESS0_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG0_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG0_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG0_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG0_OFFSET)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_L3_L4_CONTROL1_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER4_ADDRESS1_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG1_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG1_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG1_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG1_OFFSET)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_L3_L4_CONTROL2_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER4_ADDRESS2_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG2_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG2_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG2_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG2_OFFSET)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_L3_L4_CONTROL3_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER4_ADDRESS3_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG3_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG3_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG3_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG3_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MAC_SUB_SECOND_INCREMENT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_SUB_SECOND_INCREMENT_OFFSET)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_SECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_SYSTEM_TIME_SECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_NANOSECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_SYSTEM_TIME_NANOSECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_OFFSET)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_ADDEND (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_ADDEND_OFFSET)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_STATUS_OFFSET)
+#define S32K3XX_EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_LATENCY (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_LATENCY (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS0_TARGET_TIME_SECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS0_TARGET_TIME_SECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS0_INTERVAL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS0_INTERVAL_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS0_WIDTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS0_WIDTH_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS1_TARGET_TIME_SECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS1_TARGET_TIME_SECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS1_INTERVAL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS1_INTERVAL_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS1_WIDTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS1_WIDTH_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS2_TARGET_TIME_SECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS2_TARGET_TIME_SECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS2_INTERVAL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS2_INTERVAL_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS2_WIDTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS2_WIDTH_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS3_TARGET_TIME_SECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS3_TARGET_TIME_SECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS3_INTERVAL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS3_INTERVAL_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS3_WIDTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS3_WIDTH_OFFSET)
+#define S32K3XX_EMAC_MTL_OPERATION_MODE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_OPERATION_MODE_OFFSET)
+#define S32K3XX_EMAC_MTL_DBG_CTL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_DBG_CTL_OFFSET)
+#define S32K3XX_EMAC_MTL_DBG_STS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_DBG_STS_OFFSET)
+#define S32K3XX_EMAC_MTL_FIFO_DEBUG_DATA (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_FIFO_DEBUG_DATA_OFFSET)
+#define S32K3XX_EMAC_MTL_INTERRUPT_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_INTERRUPT_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ_DMA_MAP0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ_DMA_MAP0_OFFSET)
+#define S32K3XX_EMAC_MTL_TBS_CTRL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TBS_CTRL_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_SCH_ERROR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_SCH_ERROR_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_FRM_SIZE_ERROR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_FRM_SIZE_ERROR_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_FRM_SIZE_CAPTURE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_FRM_SIZE_CAPTURE_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_INTR_ENABLE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_INTR_ENABLE_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_GCL_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_GCL_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_GCL_DATA (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_GCL_DATA_OFFSET)
+#define S32K3XX_EMAC_MTL_FPE_CTRL_STS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_FPE_CTRL_STS_OFFSET)
+#define S32K3XX_EMAC_MTL_FPE_ADVANCE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_FPE_ADVANCE_OFFSET)
+#define S32K3XX_EMAC_MTL_RXP_CONTROL_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXP_CONTROL_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_RXP_DROP_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXP_DROP_CNT_OFFSET)
+#define S32K3XX_EMAC_MTL_RXP_ERROR_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXP_ERROR_CNT_OFFSET)
+#define S32K3XX_EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_RXP_INDIRECT_ACC_DATA (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXP_INDIRECT_ACC_DATA_OFFSET)
+#define S32K3XX_EMAC_MTL_ECC_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_ECC_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MTL_SAFETY_INTERRUPT_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_SAFETY_INTERRUPT_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_ECC_INTERRUPT_ENABLE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_ECC_INTERRUPT_ENABLE_OFFSET)
+#define S32K3XX_EMAC_MTL_ECC_INTERRUPT_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_ECC_INTERRUPT_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_ECC_ERR_STS_RCTL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_ECC_ERR_STS_RCTL_OFFSET)
+#define S32K3XX_EMAC_MTL_ECC_ERR_ADDR_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_ECC_ERR_ADDR_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_ECC_ERR_CNTR_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_ECC_ERR_CNTR_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_DPP_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_DPP_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ0_OPERATION_MODE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ0_OPERATION_MODE_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ0_UNDERFLOW (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ0_UNDERFLOW_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ0_DEBUG (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ0_DEBUG_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ0_ETS_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ0_ETS_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ0_QUANTUM_WEIGHT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ0_QUANTUM_WEIGHT_OFFSET)
+#define S32K3XX_EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ0_OPERATION_MODE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ0_OPERATION_MODE_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ0_DEBUG (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ0_DEBUG_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ0_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ0_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_OPERATION_MODE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_OPERATION_MODE_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_UNDERFLOW (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_UNDERFLOW_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_DEBUG (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_DEBUG_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_ETS_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_ETS_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_ETS_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_ETS_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_QUANTUM_WEIGHT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_QUANTUM_WEIGHT_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_SENDSLOPECREDIT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_SENDSLOPECREDIT_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_HICREDIT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_HICREDIT_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_LOCREDIT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_LOCREDIT_OFFSET)
+#define S32K3XX_EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ1_OPERATION_MODE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ1_OPERATION_MODE_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ1_DEBUG (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ1_DEBUG_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ1_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ1_CONTROL_OFFSET)
+#define S32K3XX_EMAC_DMA_MODE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_MODE_OFFSET)
+#define S32K3XX_EMAC_DMA_SYSBUS_MODE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_SYSBUS_MODE_OFFSET)
+#define S32K3XX_EMAC_DMA_INTERRUPT_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_INTERRUPT_STATUS_OFFSET)
+#define S32K3XX_EMAC_DMA_DEBUG_STATUS0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_DEBUG_STATUS0_OFFSET)
+#define S32K3XX_EMAC_DMA_TBS_CTRL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_TBS_CTRL_OFFSET)
+#define S32K3XX_EMAC_DMA_SAFETY_INTERRUPT_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_SAFETY_INTERRUPT_STATUS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_CONTROL_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_TX_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_TX_CONTROL_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_RX_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_RX_CONTROL_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_TXDESC_LIST_ADDRESS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_RXDESC_LIST_ADDRESS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_TXDESC_TAIL_POINTER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_TXDESC_TAIL_POINTER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_RXDESC_TAIL_POINTER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_RXDESC_TAIL_POINTER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_TXDESC_RING_LENGTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_TXDESC_RING_LENGTH_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_RXDESC_RING_LENGTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_RXDESC_RING_LENGTH_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_INTERRUPT_ENABLE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_INTERRUPT_ENABLE_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_TXDESC (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_CURRENT_APP_TXDESC_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_RXDESC (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_CURRENT_APP_RXDESC_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_TXBUFFER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_RXBUFFER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_STATUS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_MISS_FRAME_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_MISS_FRAME_CNT_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_RXP_ACCEPT_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_RXP_ACCEPT_CNT_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_RX_ERI_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_RX_ERI_CNT_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_CONTROL_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_TX_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_TX_CONTROL_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_RX_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_RX_CONTROL_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_TXDESC_LIST_ADDRESS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_RXDESC_LIST_ADDRESS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_TXDESC_TAIL_POINTER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_TXDESC_TAIL_POINTER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_RXDESC_TAIL_POINTER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_RXDESC_TAIL_POINTER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_TXDESC_RING_LENGTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_TXDESC_RING_LENGTH_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_RXDESC_RING_LENGTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_RXDESC_RING_LENGTH_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_INTERRUPT_ENABLE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_INTERRUPT_ENABLE_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_TXDESC (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_CURRENT_APP_TXDESC_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_RXDESC (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_CURRENT_APP_RXDESC_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_TXBUFFER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_RXBUFFER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_STATUS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_MISS_FRAME_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_MISS_FRAME_CNT_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_RXP_ACCEPT_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_RXP_ACCEPT_CNT_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_RX_ERI_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_RX_ERI_CNT_OFFSET)
+
+/* MAC Configuration (MAC_CONFIGURATION) */
+#define EMAC_MAC_CONFIGURATION_RE (1 << 0) /* Bit 0: Receiver Enable */
+#define EMAC_MAC_CONFIGURATION_TE (1 << 1) /* Bit 1: Transmitter Enable */
+#define EMAC_MAC_CONFIGURATION_PRELEN_SHIFT (2) /* Bits 2-4: Preamble Length for Transmit Packets */
+#define EMAC_MAC_CONFIGURATION_PRELEN_MASK (0x3 << EMAC_MAC_CONFIGURATION_PRELEN_SHIFT)
+#define EMAC_MAC_CONFIGURATION_PRELEN(n) ((n << EMAC_MAC_CONFIGURATION_PRELEN_SHIFT) & EMAC_MAC_CONFIGURATION_PRELEN_MASK)
+#define EMAC_MAC_CONFIGURATION_DC (1 << 4) /* Bit 4: Deferral Check */
+#define EMAC_MAC_CONFIGURATION_BL_SHIFT (5) /* Bits 5-7: Back-Off Limit */
+#define EMAC_MAC_CONFIGURATION_BL_MASK (0x3 << EMAC_MAC_CONFIGURATION_BL_SHIFT)
+#define EMAC_MAC_CONFIGURATION_BL(n) ((n << EMAC_MAC_CONFIGURATION_BL_SHIFT) & EMAC_MAC_CONFIGURATION_BL_MASK)
+#define EMAC_MAC_CONFIGURATION_DR (1 << 8) /* Bit 8: Disable Retry */
+#define EMAC_MAC_CONFIGURATION_DCRS (1 << 9) /* Bit 9: Disable Carrier Sense During Transmission */
+#define EMAC_MAC_CONFIGURATION_DO (1 << 10) /* Bit 10: Disable Receive Own */
+#define EMAC_MAC_CONFIGURATION_ECRSFD (1 << 11) /* Bit 11: Enable Carrier Sense In Full-Duplex Mode */
+#define EMAC_MAC_CONFIGURATION_LM (1 << 12) /* Bit 12: Loopback Mode */
+#define EMAC_MAC_CONFIGURATION_DM (1 << 13) /* Bit 13: Duplex Mode */
+#define EMAC_MAC_CONFIGURATION_FES (1 << 14) /* Bit 14: Speed */
+#define EMAC_MAC_CONFIGURATION_PS (1 << 15) /* Bit 15: Port Select */
+#define EMAC_MAC_CONFIGURATION_JE (1 << 16) /* Bit 16: Jumbo Packet Enable */
+#define EMAC_MAC_CONFIGURATION_JD (1 << 17) /* Bit 17: Jabber Disable */
+#define EMAC_MAC_CONFIGURATION_WD (1 << 19) /* Bit 19: Watchdog Disable */
+#define EMAC_MAC_CONFIGURATION_ACS (1 << 20) /* Bit 20: Automatic Pad Or CRC Stripping */
+#define EMAC_MAC_CONFIGURATION_CST (1 << 21) /* Bit 21: CRC Stripping For Type Packets */
+#define EMAC_MAC_CONFIGURATION_S2KP (1 << 22) /* Bit 22: IEEE 802.3 Support For 2K Packets */
+#define EMAC_MAC_CONFIGURATION_GPSLCE (1 << 23) /* Bit 23: Giant Packet Size Limit Control Enable */
+#define EMAC_MAC_CONFIGURATION_IPG_SHIFT (24) /* Bits 24-27: Inter-Packet Gap */
+#define EMAC_MAC_CONFIGURATION_IPG_MASK (0x7 << EMAC_MAC_CONFIGURATION_IPG_SHIFT)
+#define EMAC_MAC_CONFIGURATION_IPG(n) ((n << EMAC_MAC_CONFIGURATION_IPG_SHIFT) & EMAC_MAC_CONFIGURATION_IPG_MASK)
+#define EMAC_MAC_CONFIGURATION_IPC (1 << 27) /* Bit 27: Checksum Offload */
+#define EMAC_MAC_CONFIGURATION_SARC_SHIFT (28) /* Bits 28-31: Source Address Insertion Or Replacement Control */
+#define EMAC_MAC_CONFIGURATION_SARC_MASK (0x7 << EMAC_MAC_CONFIGURATION_SARC_SHIFT)
+#define EMAC_MAC_CONFIGURATION_SARC(n) ((n << EMAC_MAC_CONFIGURATION_SARC_SHIFT) & EMAC_MAC_CONFIGURATION_SARC_MASK)
+
+/* MAC Extended Configuration (MAC_EXT_CONFIGURATION) */
+#define EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0) /* Bits 0-14: Giant Packet Size Limit */
+#define EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFF << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT)
+#define EMAC_MAC_EXT_CONFIGURATION_GPSL(n) ((n << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK)
+#define EMAC_MAC_EXT_CONFIGURATION_DCRCC (1 << 16) /* Bit 16: Disable CRC Checking For Received Packets */
+#define EMAC_MAC_EXT_CONFIGURATION_SPEN (1 << 17) /* Bit 17: Slow Protocol Detection Enable */
+#define EMAC_MAC_EXT_CONFIGURATION_USP (1 << 18) /* Bit 18: Unicast Slow Protocol Packet Detect */
+#define EMAC_MAC_EXT_CONFIGURATION_PDC (1 << 19) /* Bit 19: Packet Duplication Control */
+#define EMAC_MAC_EXT_CONFIGURATION_EIPGEN (1 << 24) /* Bit 24: Extended Inter-Packet Gap Enable */
+#define EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25) /* Bits 25-30: Extended Inter-Packet Gap */
+#define EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK (0x1F << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT)
+#define EMAC_MAC_EXT_CONFIGURATION_EIPG(n) ((n << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK)
+
+/* MAC Packet Filter (MAC_PACKET_FILTER) */
+#define EMAC_MAC_PACKET_FILTER_PR (1 << 0) /* Bit 0: Promiscuous Mode */
+#define EMAC_MAC_PACKET_FILTER_HUC (1 << 1) /* Bit 1: Hash Unicast */
+#define EMAC_MAC_PACKET_FILTER_HMC (1 << 2) /* Bit 2: Hash Multicast */
+#define EMAC_MAC_PACKET_FILTER_DAIF (1 << 3) /* Bit 3: DA Inverse Filtering */
+#define EMAC_MAC_PACKET_FILTER_PM (1 << 4) /* Bit 4: Pass All Multicast */
+#define EMAC_MAC_PACKET_FILTER_DBF (1 << 5) /* Bit 5: Disable Broadcast Packets */
+#define EMAC_MAC_PACKET_FILTER_PCF_SHIFT (6) /* Bits 6-8: Pass Control Packets */
+#define EMAC_MAC_PACKET_FILTER_PCF_MASK (0x3 << EMAC_MAC_PACKET_FILTER_PCF_SHIFT)
+#define EMAC_MAC_PACKET_FILTER_PCF(n) ((n << EMAC_MAC_PACKET_FILTER_PCF_SHIFT) & EMAC_MAC_PACKET_FILTER_PCF_MASK)
+#define EMAC_MAC_PACKET_FILTER_SAIF (1 << 8) /* Bit 8: SA Inverse Filtering */
+#define EMAC_MAC_PACKET_FILTER_SAF (1 << 9) /* Bit 9: Source Address Filter Enable */
+#define EMAC_MAC_PACKET_FILTER_HPF (1 << 10) /* Bit 10: Hash Or Perfect Filter */
+#define EMAC_MAC_PACKET_FILTER_VTFE (1 << 16) /* Bit 16: VLAN Tag Filter Enable */
+#define EMAC_MAC_PACKET_FILTER_IPFE (1 << 20) /* Bit 20: Layer 3 and Layer 4 Filter Enable */
+#define EMAC_MAC_PACKET_FILTER_DNTU (1 << 21) /* Bit 21: Drop Non-TCP/UDP Over IP Packets */
+#define EMAC_MAC_PACKET_FILTER_RA (1 << 31) /* Bit 31: Receive All */
+
+/* MAC Watchdog Timeout (MAC_WATCHDOG_TIMEOUT) */
+#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0) /* Bits 0-4: Watchdog Timeout */
+#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xF << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)
+#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO(n) ((n << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT) & EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK)
+#define EMAC_MAC_WATCHDOG_TIMEOUT_PWE (1 << 8) /* Bit 8: Programmable Watchdog Enable */
+
+/* MAC Hash Table First 32 Bits (MAC_HASH_TABLE_REG0) */
+#define EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0) /* Bits 0-32: MAC Hash Table First 32 Bits */
+#define EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFF << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT)
+#define EMAC_MAC_HASH_TABLE_REG0_HT31T0(n) ((n << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT) & EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK)
+
+/* MAC Hash Table Second 32 Bits (MAC_HASH_TABLE_REG1) */
+#define EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0) /* Bits 0-32: MAC Hash Table Second 32 Bits */
+#define EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFF << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT)
+#define EMAC_MAC_HASH_TABLE_REG1_HT63T32(n) ((n << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT) & EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK)
+
+/* MAC VLAN Tag (MAC_VLAN_TAG) */
+#define EMAC_MAC_VLAN_TAG_VL_SHIFT (0) /* Bits 0-16: VLAN Tag Identifier for Receive Packets */
+#define EMAC_MAC_VLAN_TAG_VL_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_VL_SHIFT)
+#define EMAC_MAC_VLAN_TAG_VL(n) ((n << EMAC_MAC_VLAN_TAG_VL_SHIFT) & EMAC_MAC_VLAN_TAG_VL_MASK)
+#define EMAC_MAC_VLAN_TAG_ETV (1 << 16) /* Bit 16: Enable Tag For VLAN */
+#define EMAC_MAC_VLAN_TAG_VTIM (1 << 17) /* Bit 17: VLAN Tag Inverse Match Enable */
+#define EMAC_MAC_VLAN_TAG_ESVL (1 << 18) /* Bit 18: Enable S-VLAN */
+#define EMAC_MAC_VLAN_TAG_ERSVLM (1 << 19) /* Bit 19: Enable Receive S-VLAN Match */
+#define EMAC_MAC_VLAN_TAG_DOVLTC (1 << 20) /* Bit 20: Disable VLAN Type Check */
+#define EMAC_MAC_VLAN_TAG_EVLS_SHIFT (21) /* Bits 21-23: Enable VLAN Tag Stripping */
+#define EMAC_MAC_VLAN_TAG_EVLS_MASK (0x3 << EMAC_MAC_VLAN_TAG_EVLS_SHIFT)
+#define EMAC_MAC_VLAN_TAG_EVLS(n) ((n << EMAC_MAC_VLAN_TAG_EVLS_SHIFT) & EMAC_MAC_VLAN_TAG_EVLS_MASK)
Review Comment:
```suggestion
#define EMAC_MAC_VLAN_TAG_EVLS(n) (((n) << EMAC_MAC_VLAN_TAG_EVLS_SHIFT) & EMAC_MAC_VLAN_TAG_EVLS_MASK)
```
here and other places
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h:
##########
@@ -0,0 +1,1433 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define S32K3XX_EDMA_NCHANNELS 32
+
+/* eDMA Register Offsets ****************************************************/
+
+#define S32K3XX_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */
+#define S32K3XX_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */
+#define S32K3XX_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */
+#define S32K3XX_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */
+
+#define S32K3XX_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */
+
+/* eDMA Register Addresses **************************************************/
+
+#define S32K3XX_EDMA_CSR (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CSR_OFFSET)
+#define S32K3XX_EDMA_ES (S32K3XX_EDMA_BASE + S32K3XX_EDMA_ES_OFFSET)
+#define S32K3XX_EDMA_INT (S32K3XX_EDMA_BASE + S32K3XX_EDMA_INT_OFFSET)
+#define S32K3XX_EDMA_HRS (S32K3XX_EDMA_BASE + S32K3XX_EDMA_HRS_OFFSET)
+#define S32K3XX_EDMA_CH_GRPRI(n) (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CH_GRPRI_OFFSET(n))
+
+/* eDMA Transfer Control Descriptor (TCD) Register Offsets ******************/
+
+#define S32K3XX_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH0_CSR_OFFSET (0x000000) /* Channel 0 Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH0_ES_OFFSET (0x000004) /* Channel 0 Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH0_INT_OFFSET (0x000008) /* Channel 0 Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH0_SBR_OFFSET (0x00000c) /* Channel 0 System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH0_PRI_OFFSET (0x000010) /* Channel 0 Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD0_SADDR_OFFSET (0x000020) /* TCD0 Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD0_SOFF_OFFSET (0x000024) /* TCD0 Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD0_ATTR_OFFSET (0x000026) /* TCD0 Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD0_NBYTES_OFFSET (0x000028) /* TCD0 Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET (0x00002c) /* TCD0 Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD0_DADDR_OFFSET (0x000030) /* TCD0 Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD0_DOFF_OFFSET (0x000034) /* TCD0 Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD0_CITER_OFFSET (0x000036) /* TCD0 Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET (0x000038) /* TCD0 Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD0_CSR_OFFSET (0x00003c) /* TCD0 Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD0_BITER_OFFSET (0x00003e) /* TCD0 Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH1_CSR_OFFSET (0x004000) /* Channel 1 Control and Status Register (CH1_CSR) */
+#define S32K3XX_EDMA_CH1_ES_OFFSET (0x004004) /* Channel 1 Error Status Register (CH1_ES) */
+#define S32K3XX_EDMA_CH1_INT_OFFSET (0x004008) /* Channel 1 Interrupt Status Register (CH1_INT) */
+#define S32K3XX_EDMA_CH1_SBR_OFFSET (0x00400c) /* Channel 1 System Bus Register (CH1_SBR) */
+#define S32K3XX_EDMA_CH1_PRI_OFFSET (0x004010) /* Channel 1 Priority Register (CH1_PRI) */
+#define S32K3XX_EDMA_TCD1_SADDR_OFFSET (0x004020) /* TCD1 Source Address Register (TCD1_SADDR) */
+#define S32K3XX_EDMA_TCD1_SOFF_OFFSET (0x004024) /* TCD1 Signed Source Address Offset Register (TCD1_SOFF) */
+#define S32K3XX_EDMA_TCD1_ATTR_OFFSET (0x004026) /* TCD1 Transfer Attributes (TCD1_ATTR) */
+#define S32K3XX_EDMA_TCD1_NBYTES_OFFSET (0x004028) /* TCD1 Transfer Size (TCD1_NBYTES) */
+#define S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET (0x00402c) /* TCD1 Last Source Address Adjustment / Store DADDR Address Register (TCD1_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD1_DADDR_OFFSET (0x004030) /* TCD1 Destination Address Register (TCD1_DADDR) */
+#define S32K3XX_EDMA_TCD1_DOFF_OFFSET (0x004034) /* TCD1 Signed Destination Address Offset Register (TCD1_DOFF) */
+#define S32K3XX_EDMA_TCD1_CITER_OFFSET (0x004036) /* TCD1 Current Major Loop Count Register (TCD1_CITER) */
+#define S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET (0x004038) /* TCD1 Last Destination Address Adjustment / Scatter Gather Address Register (TCD1_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD1_CSR_OFFSET (0x00403c) /* TCD1 Control and Status Register (TCD1_CSR) */
+#define S32K3XX_EDMA_TCD1_BITER_OFFSET (0x00403e) /* TCD1 Beginning Major Loop Count Register (TCD1_BITER) */
+
+#define S32K3XX_EDMA_CH2_CSR_OFFSET (0x008000) /* Channel 2 Control and Status Register (CH2_CSR) */
+#define S32K3XX_EDMA_CH2_ES_OFFSET (0x008004) /* Channel 2 Error Status Register (CH2_ES) */
+#define S32K3XX_EDMA_CH2_INT_OFFSET (0x008008) /* Channel 2 Interrupt Status Register (CH2_INT) */
+#define S32K3XX_EDMA_CH2_SBR_OFFSET (0x00800c) /* Channel 2 System Bus Register (CH2_SBR) */
+#define S32K3XX_EDMA_CH2_PRI_OFFSET (0x008010) /* Channel 2 Priority Register (CH2_PRI) */
+#define S32K3XX_EDMA_TCD2_SADDR_OFFSET (0x008020) /* TCD2 Source Address Register (TCD2_SADDR) */
+#define S32K3XX_EDMA_TCD2_SOFF_OFFSET (0x008024) /* TCD2 Signed Source Address Offset Register (TCD2_SOFF) */
+#define S32K3XX_EDMA_TCD2_ATTR_OFFSET (0x008026) /* TCD2 Transfer Attributes (TCD2_ATTR) */
+#define S32K3XX_EDMA_TCD2_NBYTES_OFFSET (0x008028) /* TCD2 Transfer Size (TCD2_NBYTES) */
+#define S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET (0x00802c) /* TCD2 Last Source Address Adjustment / Store DADDR Address Register (TCD2_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD2_DADDR_OFFSET (0x008030) /* TCD2 Destination Address Register (TCD2_DADDR) */
+#define S32K3XX_EDMA_TCD2_DOFF_OFFSET (0x008034) /* TCD2 Signed Destination Address Offset Register (TCD2_DOFF) */
+#define S32K3XX_EDMA_TCD2_CITER_OFFSET (0x008036) /* TCD2 Current Major Loop Count Register (TCD2_CITER) */
+#define S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET (0x008038) /* TCD2 Last Destination Address Adjustment / Scatter Gather Address Register (TCD2_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD2_CSR_OFFSET (0x00803c) /* TCD2 Control and Status Register (TCD2_CSR) */
+#define S32K3XX_EDMA_TCD2_BITER_OFFSET (0x00803e) /* TCD2 Beginning Major Loop Count Register (TCD2_BITER) */
+
+#define S32K3XX_EDMA_CH3_CSR_OFFSET (0x00c000) /* Channel 3 Control and Status Register (CH3_CSR) */
+#define S32K3XX_EDMA_CH3_ES_OFFSET (0x00c004) /* Channel 3 Error Status Register (CH3_ES) */
+#define S32K3XX_EDMA_CH3_INT_OFFSET (0x00c008) /* Channel 3 Interrupt Status Register (CH3_INT) */
+#define S32K3XX_EDMA_CH3_SBR_OFFSET (0x00c00c) /* Channel 3 System Bus Register (CH3_SBR) */
+#define S32K3XX_EDMA_CH3_PRI_OFFSET (0x00c010) /* Channel 3 Priority Register (CH3_PRI) */
+#define S32K3XX_EDMA_TCD3_SADDR_OFFSET (0x00c020) /* TCD3 Source Address Register (TCD3_SADDR) */
+#define S32K3XX_EDMA_TCD3_SOFF_OFFSET (0x00c024) /* TCD3 Signed Source Address Offset Register (TCD3_SOFF) */
+#define S32K3XX_EDMA_TCD3_ATTR_OFFSET (0x00c026) /* TCD3 Transfer Attributes (TCD3_ATTR) */
+#define S32K3XX_EDMA_TCD3_NBYTES_OFFSET (0x00c028) /* TCD3 Transfer Size (TCD3_NBYTES) */
+#define S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET (0x00c02c) /* TCD3 Last Source Address Adjustment / Store DADDR Address Register (TCD3_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD3_DADDR_OFFSET (0x00c030) /* TCD3 Destination Address Register (TCD3_DADDR) */
+#define S32K3XX_EDMA_TCD3_DOFF_OFFSET (0x00c034) /* TCD3 Signed Destination Address Offset Register (TCD3_DOFF) */
+#define S32K3XX_EDMA_TCD3_CITER_OFFSET (0x00c036) /* TCD3 Current Major Loop Count Register (TCD3_CITER) */
+#define S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET (0x00c038) /* TCD3 Last Destination Address Adjustment / Scatter Gather Address Register (TCD3_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD3_CSR_OFFSET (0x00c03c) /* TCD3 Control and Status Register (TCD3_CSR) */
+#define S32K3XX_EDMA_TCD3_BITER_OFFSET (0x00c03e) /* TCD3 Beginning Major Loop Count Register (TCD3_BITER) */
+
+#define S32K3XX_EDMA_CH4_CSR_OFFSET (0x010000) /* Channel 4 Control and Status Register (CH4_CSR) */
+#define S32K3XX_EDMA_CH4_ES_OFFSET (0x010004) /* Channel 4 Error Status Register (CH4_ES) */
+#define S32K3XX_EDMA_CH4_INT_OFFSET (0x010008) /* Channel 4 Interrupt Status Register (CH4_INT) */
+#define S32K3XX_EDMA_CH4_SBR_OFFSET (0x01000c) /* Channel 4 System Bus Register (CH4_SBR) */
+#define S32K3XX_EDMA_CH4_PRI_OFFSET (0x010010) /* Channel 4 Priority Register (CH4_PRI) */
+#define S32K3XX_EDMA_TCD4_SADDR_OFFSET (0x010020) /* TCD4 Source Address Register (TCD4_SADDR) */
+#define S32K3XX_EDMA_TCD4_SOFF_OFFSET (0x010024) /* TCD4 Signed Source Address Offset Register (TCD4_SOFF) */
+#define S32K3XX_EDMA_TCD4_ATTR_OFFSET (0x010026) /* TCD4 Transfer Attributes (TCD4_ATTR) */
+#define S32K3XX_EDMA_TCD4_NBYTES_OFFSET (0x010028) /* TCD4 Transfer Size (TCD4_NBYTES) */
+#define S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET (0x01002c) /* TCD4 Last Source Address Adjustment / Store DADDR Address Register (TCD4_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD4_DADDR_OFFSET (0x010030) /* TCD4 Destination Address Register (TCD4_DADDR) */
+#define S32K3XX_EDMA_TCD4_DOFF_OFFSET (0x010034) /* TCD4 Signed Destination Address Offset Register (TCD4_DOFF) */
+#define S32K3XX_EDMA_TCD4_CITER_OFFSET (0x010036) /* TCD4 Current Major Loop Count Register (TCD4_CITER) */
+#define S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET (0x010038) /* TCD4 Last Destination Address Adjustment / Scatter Gather Address Register (TCD4_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD4_CSR_OFFSET (0x01003c) /* TCD4 Control and Status Register (TCD4_CSR) */
+#define S32K3XX_EDMA_TCD4_BITER_OFFSET (0x01003e) /* TCD4 Beginning Major Loop Count Register (TCD4_BITER) */
+
+#define S32K3XX_EDMA_CH5_CSR_OFFSET (0x014000) /* Channel 5 Control and Status Register (CH5_CSR) */
+#define S32K3XX_EDMA_CH5_ES_OFFSET (0x014004) /* Channel 5 Error Status Register (CH5_ES) */
+#define S32K3XX_EDMA_CH5_INT_OFFSET (0x014008) /* Channel 5 Interrupt Status Register (CH5_INT) */
+#define S32K3XX_EDMA_CH5_SBR_OFFSET (0x01400c) /* Channel 5 System Bus Register (CH5_SBR) */
+#define S32K3XX_EDMA_CH5_PRI_OFFSET (0x014010) /* Channel 5 Priority Register (CH5_PRI) */
+#define S32K3XX_EDMA_TCD5_SADDR_OFFSET (0x014020) /* TCD5 Source Address Register (TCD5_SADDR) */
+#define S32K3XX_EDMA_TCD5_SOFF_OFFSET (0x014024) /* TCD5 Signed Source Address Offset Register (TCD5_SOFF) */
+#define S32K3XX_EDMA_TCD5_ATTR_OFFSET (0x014026) /* TCD5 Transfer Attributes (TCD5_ATTR) */
+#define S32K3XX_EDMA_TCD5_NBYTES_OFFSET (0x014028) /* TCD5 Transfer Size (TCD5_NBYTES) */
+#define S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET (0x01402c) /* TCD5 Last Source Address Adjustment / Store DADDR Address Register (TCD5_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD5_DADDR_OFFSET (0x014030) /* TCD5 Destination Address Register (TCD5_DADDR) */
+#define S32K3XX_EDMA_TCD5_DOFF_OFFSET (0x014034) /* TCD5 Signed Destination Address Offset Register (TCD5_DOFF) */
+#define S32K3XX_EDMA_TCD5_CITER_OFFSET (0x014036) /* TCD5 Current Major Loop Count Register (TCD5_CITER) */
+#define S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET (0x014038) /* TCD5 Last Destination Address Adjustment / Scatter Gather Address Register (TCD5_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD5_CSR_OFFSET (0x01403c) /* TCD5 Control and Status Register (TCD5_CSR) */
+#define S32K3XX_EDMA_TCD5_BITER_OFFSET (0x01403e) /* TCD5 Beginning Major Loop Count Register (TCD5_BITER) */
+
+#define S32K3XX_EDMA_CH6_CSR_OFFSET (0x018000) /* Channel 6 Control and Status Register (CH6_CSR) */
+#define S32K3XX_EDMA_CH6_ES_OFFSET (0x018004) /* Channel 6 Error Status Register (CH6_ES) */
+#define S32K3XX_EDMA_CH6_INT_OFFSET (0x018008) /* Channel 6 Interrupt Status Register (CH6_INT) */
+#define S32K3XX_EDMA_CH6_SBR_OFFSET (0x01800c) /* Channel 6 System Bus Register (CH6_SBR) */
+#define S32K3XX_EDMA_CH6_PRI_OFFSET (0x018010) /* Channel 6 Priority Register (CH6_PRI) */
+#define S32K3XX_EDMA_TCD6_SADDR_OFFSET (0x018020) /* TCD6 Source Address Register (TCD6_SADDR) */
+#define S32K3XX_EDMA_TCD6_SOFF_OFFSET (0x018024) /* TCD6 Signed Source Address Offset Register (TCD6_SOFF) */
+#define S32K3XX_EDMA_TCD6_ATTR_OFFSET (0x018026) /* TCD6 Transfer Attributes (TCD6_ATTR) */
+#define S32K3XX_EDMA_TCD6_NBYTES_OFFSET (0x018028) /* TCD6 Transfer Size (TCD6_NBYTES) */
+#define S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET (0x01802c) /* TCD6 Last Source Address Adjustment / Store DADDR Address Register (TCD6_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD6_DADDR_OFFSET (0x018030) /* TCD6 Destination Address Register (TCD6_DADDR) */
+#define S32K3XX_EDMA_TCD6_DOFF_OFFSET (0x018034) /* TCD6 Signed Destination Address Offset Register (TCD6_DOFF) */
+#define S32K3XX_EDMA_TCD6_CITER_OFFSET (0x018036) /* TCD6 Current Major Loop Count Register (TCD6_CITER) */
+#define S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET (0x018038) /* TCD6 Last Destination Address Adjustment / Scatter Gather Address Register (TCD6_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD6_CSR_OFFSET (0x01803c) /* TCD6 Control and Status Register (TCD6_CSR) */
+#define S32K3XX_EDMA_TCD6_BITER_OFFSET (0x01803e) /* TCD6 Beginning Major Loop Count Register (TCD6_BITER) */
+
+#define S32K3XX_EDMA_CH7_CSR_OFFSET (0x01c000) /* Channel 7 Control and Status Register (CH7_CSR) */
+#define S32K3XX_EDMA_CH7_ES_OFFSET (0x01c004) /* Channel 7 Error Status Register (CH7_ES) */
+#define S32K3XX_EDMA_CH7_INT_OFFSET (0x01c008) /* Channel 7 Interrupt Status Register (CH7_INT) */
+#define S32K3XX_EDMA_CH7_SBR_OFFSET (0x01c00c) /* Channel 7 System Bus Register (CH7_SBR) */
+#define S32K3XX_EDMA_CH7_PRI_OFFSET (0x01c010) /* Channel 7 Priority Register (CH7_PRI) */
+#define S32K3XX_EDMA_TCD7_SADDR_OFFSET (0x01c020) /* TCD7 Source Address Register (TCD7_SADDR) */
+#define S32K3XX_EDMA_TCD7_SOFF_OFFSET (0x01c024) /* TCD7 Signed Source Address Offset Register (TCD7_SOFF) */
+#define S32K3XX_EDMA_TCD7_ATTR_OFFSET (0x01c026) /* TCD7 Transfer Attributes (TCD7_ATTR) */
+#define S32K3XX_EDMA_TCD7_NBYTES_OFFSET (0x01c028) /* TCD7 Transfer Size (TCD7_NBYTES) */
+#define S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET (0x01c02c) /* TCD7 Last Source Address Adjustment / Store DADDR Address Register (TCD7_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD7_DADDR_OFFSET (0x01c030) /* TCD7 Destination Address Register (TCD7_DADDR) */
+#define S32K3XX_EDMA_TCD7_DOFF_OFFSET (0x01c034) /* TCD7 Signed Destination Address Offset Register (TCD7_DOFF) */
+#define S32K3XX_EDMA_TCD7_CITER_OFFSET (0x01c036) /* TCD7 Current Major Loop Count Register (TCD7_CITER) */
+#define S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET (0x01c038) /* TCD7 Last Destination Address Adjustment / Scatter Gather Address Register (TCD7_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD7_CSR_OFFSET (0x01c03c) /* TCD7 Control and Status Register (TCD7_CSR) */
+#define S32K3XX_EDMA_TCD7_BITER_OFFSET (0x01c03e) /* TCD7 Beginning Major Loop Count Register (TCD7_BITER) */
+
+#define S32K3XX_EDMA_CH8_CSR_OFFSET (0x020000) /* Channel 8 Control and Status Register (CH8_CSR) */
+#define S32K3XX_EDMA_CH8_ES_OFFSET (0x020004) /* Channel 8 Error Status Register (CH8_ES) */
+#define S32K3XX_EDMA_CH8_INT_OFFSET (0x020008) /* Channel 8 Interrupt Status Register (CH8_INT) */
+#define S32K3XX_EDMA_CH8_SBR_OFFSET (0x02000c) /* Channel 8 System Bus Register (CH8_SBR) */
+#define S32K3XX_EDMA_CH8_PRI_OFFSET (0x020010) /* Channel 8 Priority Register (CH8_PRI) */
+#define S32K3XX_EDMA_TCD8_SADDR_OFFSET (0x020020) /* TCD8 Source Address Register (TCD8_SADDR) */
+#define S32K3XX_EDMA_TCD8_SOFF_OFFSET (0x020024) /* TCD8 Signed Source Address Offset Register (TCD8_SOFF) */
+#define S32K3XX_EDMA_TCD8_ATTR_OFFSET (0x020026) /* TCD8 Transfer Attributes (TCD8_ATTR) */
+#define S32K3XX_EDMA_TCD8_NBYTES_OFFSET (0x020028) /* TCD8 Transfer Size (TCD8_NBYTES) */
+#define S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET (0x02002c) /* TCD8 Last Source Address Adjustment / Store DADDR Address Register (TCD8_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD8_DADDR_OFFSET (0x020030) /* TCD8 Destination Address Register (TCD8_DADDR) */
+#define S32K3XX_EDMA_TCD8_DOFF_OFFSET (0x020034) /* TCD8 Signed Destination Address Offset Register (TCD8_DOFF) */
+#define S32K3XX_EDMA_TCD8_CITER_OFFSET (0x020036) /* TCD8 Current Major Loop Count Register (TCD8_CITER) */
+#define S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET (0x020038) /* TCD8 Last Destination Address Adjustment / Scatter Gather Address Register (TCD8_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD8_CSR_OFFSET (0x02003c) /* TCD8 Control and Status Register (TCD8_CSR) */
+#define S32K3XX_EDMA_TCD8_BITER_OFFSET (0x02003e) /* TCD8 Beginning Major Loop Count Register (TCD8_BITER) */
+
+#define S32K3XX_EDMA_CH9_CSR_OFFSET (0x024000) /* Channel 9 Control and Status Register (CH9_CSR) */
+#define S32K3XX_EDMA_CH9_ES_OFFSET (0x024004) /* Channel 9 Error Status Register (CH9_ES) */
+#define S32K3XX_EDMA_CH9_INT_OFFSET (0x024008) /* Channel 9 Interrupt Status Register (CH9_INT) */
+#define S32K3XX_EDMA_CH9_SBR_OFFSET (0x02400c) /* Channel 9 System Bus Register (CH9_SBR) */
+#define S32K3XX_EDMA_CH9_PRI_OFFSET (0x024010) /* Channel 9 Priority Register (CH9_PRI) */
+#define S32K3XX_EDMA_TCD9_SADDR_OFFSET (0x024020) /* TCD9 Source Address Register (TCD9_SADDR) */
+#define S32K3XX_EDMA_TCD9_SOFF_OFFSET (0x024024) /* TCD9 Signed Source Address Offset Register (TCD9_SOFF) */
+#define S32K3XX_EDMA_TCD9_ATTR_OFFSET (0x024026) /* TCD9 Transfer Attributes (TCD9_ATTR) */
+#define S32K3XX_EDMA_TCD9_NBYTES_OFFSET (0x024028) /* TCD9 Transfer Size (TCD9_NBYTES) */
+#define S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET (0x02402c) /* TCD9 Last Source Address Adjustment / Store DADDR Address Register (TCD9_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD9_DADDR_OFFSET (0x024030) /* TCD9 Destination Address Register (TCD9_DADDR) */
+#define S32K3XX_EDMA_TCD9_DOFF_OFFSET (0x024034) /* TCD9 Signed Destination Address Offset Register (TCD9_DOFF) */
+#define S32K3XX_EDMA_TCD9_CITER_OFFSET (0x024036) /* TCD9 Current Major Loop Count Register (TCD9_CITER) */
+#define S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET (0x024038) /* TCD9 Last Destination Address Adjustment / Scatter Gather Address Register (TCD9_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD9_CSR_OFFSET (0x02403c) /* TCD9 Control and Status Register (TCD9_CSR) */
+#define S32K3XX_EDMA_TCD9_BITER_OFFSET (0x02403e) /* TCD9 Beginning Major Loop Count Register (TCD9_BITER) */
+
+#define S32K3XX_EDMA_CH10_CSR_OFFSET (0x028000) /* Channel 10 Control and Status Register (CH10_CSR) */
+#define S32K3XX_EDMA_CH10_ES_OFFSET (0x028004) /* Channel 10 Error Status Register (CH10_ES) */
+#define S32K3XX_EDMA_CH10_INT_OFFSET (0x028008) /* Channel 10 Interrupt Status Register (CH10_INT) */
+#define S32K3XX_EDMA_CH10_SBR_OFFSET (0x02800c) /* Channel 10 System Bus Register (CH10_SBR) */
+#define S32K3XX_EDMA_CH10_PRI_OFFSET (0x028010) /* Channel 10 Priority Register (CH10_PRI) */
+#define S32K3XX_EDMA_TCD10_SADDR_OFFSET (0x028020) /* TCD10 Source Address Register (TCD10_SADDR) */
+#define S32K3XX_EDMA_TCD10_SOFF_OFFSET (0x028024) /* TCD10 Signed Source Address Offset Register (TCD10_SOFF) */
+#define S32K3XX_EDMA_TCD10_ATTR_OFFSET (0x028026) /* TCD10 Transfer Attributes (TCD10_ATTR) */
+#define S32K3XX_EDMA_TCD10_NBYTES_OFFSET (0x028028) /* TCD10 Transfer Size (TCD10_NBYTES) */
+#define S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET (0x02802c) /* TCD10 Last Source Address Adjustment / Store DADDR Address Register (TCD10_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD10_DADDR_OFFSET (0x028030) /* TCD10 Destination Address Register (TCD10_DADDR) */
+#define S32K3XX_EDMA_TCD10_DOFF_OFFSET (0x028034) /* TCD10 Signed Destination Address Offset Register (TCD10_DOFF) */
+#define S32K3XX_EDMA_TCD10_CITER_OFFSET (0x028036) /* TCD10 Current Major Loop Count Register (TCD10_CITER) */
+#define S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET (0x028038) /* TCD10 Last Destination Address Adjustment / Scatter Gather Address Register (TCD10_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD10_CSR_OFFSET (0x02803c) /* TCD10 Control and Status Register (TCD10_CSR) */
+#define S32K3XX_EDMA_TCD10_BITER_OFFSET (0x02803e) /* TCD10 Beginning Major Loop Count Register (TCD10_BITER) */
+#define S32K3XX_EDMA_CH11_CSR_OFFSET (0x02c000) /* Channel 11 Control and Status Register (CH11_CSR) */
+#define S32K3XX_EDMA_CH11_ES_OFFSET (0x02c004) /* Channel 11 Error Status Register (CH11_ES) */
+#define S32K3XX_EDMA_CH11_INT_OFFSET (0x02c008) /* Channel 11 Interrupt Status Register (CH11_INT) */
+#define S32K3XX_EDMA_CH11_SBR_OFFSET (0x02c00c) /* Channel 11 System Bus Register (CH11_SBR) */
+#define S32K3XX_EDMA_CH11_PRI_OFFSET (0x02c010) /* Channel 11 Priority Register (CH11_PRI) */
+#define S32K3XX_EDMA_TCD11_SADDR_OFFSET (0x02c020) /* TCD11 Source Address Register (TCD11_SADDR) */
+#define S32K3XX_EDMA_TCD11_SOFF_OFFSET (0x02c024) /* TCD11 Signed Source Address Offset Register (TCD11_SOFF) */
+#define S32K3XX_EDMA_TCD11_ATTR_OFFSET (0x02c026) /* TCD11 Transfer Attributes (TCD11_ATTR) */
+#define S32K3XX_EDMA_TCD11_NBYTES_OFFSET (0x02c028) /* TCD11 Transfer Size (TCD11_NBYTES) */
+#define S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET (0x02c02c) /* TCD11 Last Source Address Adjustment / Store DADDR Address Register (TCD11_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD11_DADDR_OFFSET (0x02c030) /* TCD11 Destination Address Register (TCD11_DADDR) */
+#define S32K3XX_EDMA_TCD11_DOFF_OFFSET (0x02c034) /* TCD11 Signed Destination Address Offset Register (TCD11_DOFF) */
+#define S32K3XX_EDMA_TCD11_CITER_OFFSET (0x02c036) /* TCD11 Current Major Loop Count Register (TCD11_CITER) */
+#define S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET (0x02c038) /* TCD11 Last Destination Address Adjustment / Scatter Gather Address Register (TCD11_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD11_CSR_OFFSET (0x02c03c) /* TCD11 Control and Status Register (TCD11_CSR) */
+#define S32K3XX_EDMA_TCD11_BITER_OFFSET (0x02c03e) /* TCD11 Beginning Major Loop Count Register (TCD11_BITER) */
+
+#define S32K3XX_EDMA_CH12_CSR_OFFSET (0x200000) /* Channel 12 Control and Status Register (CH12_CSR) */
+#define S32K3XX_EDMA_CH12_ES_OFFSET (0x200004) /* Channel 12 Error Status Register (CH12_ES) */
+#define S32K3XX_EDMA_CH12_INT_OFFSET (0x200008) /* Channel 12 Interrupt Status Register (CH12_INT) */
+#define S32K3XX_EDMA_CH12_SBR_OFFSET (0x20000c) /* Channel 12 System Bus Register (CH12_SBR) */
+#define S32K3XX_EDMA_CH12_PRI_OFFSET (0x200010) /* Channel 12 Priority Register (CH12_PRI) */
+#define S32K3XX_EDMA_TCD12_SADDR_OFFSET (0x200020) /* TCD12 Source Address Register (TCD12_SADDR) */
+#define S32K3XX_EDMA_TCD12_SOFF_OFFSET (0x200024) /* TCD12 Signed Source Address Offset Register (TCD12_SOFF) */
+#define S32K3XX_EDMA_TCD12_ATTR_OFFSET (0x200026) /* TCD12 Transfer Attributes (TCD12_ATTR) */
+#define S32K3XX_EDMA_TCD12_NBYTES_OFFSET (0x200028) /* TCD12 Transfer Size (TCD12_NBYTES) */
+#define S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET (0x20002c) /* TCD12 Last Source Address Adjustment / Store DADDR Address Register (TCD12_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD12_DADDR_OFFSET (0x200030) /* TCD12 Destination Address Register (TCD12_DADDR) */
+#define S32K3XX_EDMA_TCD12_DOFF_OFFSET (0x200034) /* TCD12 Signed Destination Address Offset Register (TCD12_DOFF) */
+#define S32K3XX_EDMA_TCD12_CITER_OFFSET (0x200036) /* TCD12 Current Major Loop Count Register (TCD12_CITER) */
+#define S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET (0x200038) /* TCD12 Last Destination Address Adjustment / Scatter Gather Address Register (TCD12_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD12_CSR_OFFSET (0x20003c) /* TCD12 Control and Status Register (TCD12_CSR) */
+#define S32K3XX_EDMA_TCD12_BITER_OFFSET (0x20003e) /* TCD12 Beginning Major Loop Count Register (TCD12_BITER) */
+
+#define S32K3XX_EDMA_CH13_CSR_OFFSET (0x204000) /* Channel 13 Control and Status Register (CH13_CSR) */
+#define S32K3XX_EDMA_CH13_ES_OFFSET (0x204004) /* Channel 13 Error Status Register (CH13_ES) */
+#define S32K3XX_EDMA_CH13_INT_OFFSET (0x204008) /* Channel 13 Interrupt Status Register (CH13_INT) */
+#define S32K3XX_EDMA_CH13_SBR_OFFSET (0x20400c) /* Channel 13 System Bus Register (CH13_SBR) */
+#define S32K3XX_EDMA_CH13_PRI_OFFSET (0x204010) /* Channel 13 Priority Register (CH13_PRI) */
+#define S32K3XX_EDMA_TCD13_SADDR_OFFSET (0x204020) /* TCD13 Source Address Register (TCD13_SADDR) */
+#define S32K3XX_EDMA_TCD13_SOFF_OFFSET (0x204024) /* TCD13 Signed Source Address Offset Register (TCD13_SOFF) */
+#define S32K3XX_EDMA_TCD13_ATTR_OFFSET (0x204026) /* TCD13 Transfer Attributes (TCD13_ATTR) */
+#define S32K3XX_EDMA_TCD13_NBYTES_OFFSET (0x204028) /* TCD13 Transfer Size (TCD13_NBYTES) */
+#define S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET (0x20402c) /* TCD13 Last Source Address Adjustment / Store DADDR Address Register (TCD13_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD13_DADDR_OFFSET (0x204030) /* TCD13 Destination Address Register (TCD13_DADDR) */
+#define S32K3XX_EDMA_TCD13_DOFF_OFFSET (0x204034) /* TCD13 Signed Destination Address Offset Register (TCD13_DOFF) */
+#define S32K3XX_EDMA_TCD13_CITER_OFFSET (0x204036) /* TCD13 Current Major Loop Count Register (TCD13_CITER) */
+#define S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET (0x204038) /* TCD13 Last Destination Address Adjustment / Scatter Gather Address Register (TCD13_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD13_CSR_OFFSET (0x20403c) /* TCD13 Control and Status Register (TCD13_CSR) */
+#define S32K3XX_EDMA_TCD13_BITER_OFFSET (0x20403e) /* TCD13 Beginning Major Loop Count Register (TCD13_BITER) */
+
+#define S32K3XX_EDMA_CH14_CSR_OFFSET (0x208000) /* Channel 14 Control and Status Register (CH14_CSR) */
+#define S32K3XX_EDMA_CH14_ES_OFFSET (0x208004) /* Channel 14 Error Status Register (CH14_ES) */
+#define S32K3XX_EDMA_CH14_INT_OFFSET (0x208008) /* Channel 14 Interrupt Status Register (CH14_INT) */
+#define S32K3XX_EDMA_CH14_SBR_OFFSET (0x20800c) /* Channel 14 System Bus Register (CH14_SBR) */
+#define S32K3XX_EDMA_CH14_PRI_OFFSET (0x208010) /* Channel 14 Priority Register (CH14_PRI) */
+#define S32K3XX_EDMA_TCD14_SADDR_OFFSET (0x208020) /* TCD14 Source Address Register (TCD14_SADDR) */
+#define S32K3XX_EDMA_TCD14_SOFF_OFFSET (0x208024) /* TCD14 Signed Source Address Offset Register (TCD14_SOFF) */
+#define S32K3XX_EDMA_TCD14_ATTR_OFFSET (0x208026) /* TCD14 Transfer Attributes (TCD14_ATTR) */
+#define S32K3XX_EDMA_TCD14_NBYTES_OFFSET (0x208028) /* TCD14 Transfer Size (TCD14_NBYTES) */
+#define S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET (0x20802c) /* TCD14 Last Source Address Adjustment / Store DADDR Address Register (TCD14_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD14_DADDR_OFFSET (0x208030) /* TCD14 Destination Address Register (TCD14_DADDR) */
+#define S32K3XX_EDMA_TCD14_DOFF_OFFSET (0x208034) /* TCD14 Signed Destination Address Offset Register (TCD14_DOFF) */
+#define S32K3XX_EDMA_TCD14_CITER_OFFSET (0x208036) /* TCD14 Current Major Loop Count Register (TCD14_CITER) */
+#define S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET (0x208038) /* TCD14 Last Destination Address Adjustment / Scatter Gather Address Register (TCD14_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD14_CSR_OFFSET (0x20803c) /* TCD14 Control and Status Register (TCD14_CSR) */
+#define S32K3XX_EDMA_TCD14_BITER_OFFSET (0x20803e) /* TCD14 Beginning Major Loop Count Register (TCD14_BITER) */
+
+#define S32K3XX_EDMA_CH15_CSR_OFFSET (0x20c000) /* Channel 15 Control and Status Register (CH15_CSR) */
+#define S32K3XX_EDMA_CH15_ES_OFFSET (0x20c004) /* Channel 15 Error Status Register (CH15_ES) */
+#define S32K3XX_EDMA_CH15_INT_OFFSET (0x20c008) /* Channel 15 Interrupt Status Register (CH15_INT) */
+#define S32K3XX_EDMA_CH15_SBR_OFFSET (0x20c00c) /* Channel 15 System Bus Register (CH15_SBR) */
+#define S32K3XX_EDMA_CH15_PRI_OFFSET (0x20c010) /* Channel 15 Priority Register (CH15_PRI) */
+#define S32K3XX_EDMA_TCD15_SADDR_OFFSET (0x20c020) /* TCD15 Source Address Register (TCD15_SADDR) */
+#define S32K3XX_EDMA_TCD15_SOFF_OFFSET (0x20c024) /* TCD15 Signed Source Address Offset Register (TCD15_SOFF) */
+#define S32K3XX_EDMA_TCD15_ATTR_OFFSET (0x20c026) /* TCD15 Transfer Attributes (TCD15_ATTR) */
+#define S32K3XX_EDMA_TCD15_NBYTES_OFFSET (0x20c028) /* TCD15 Transfer Size (TCD15_NBYTES) */
+#define S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET (0x20c02c) /* TCD15 Last Source Address Adjustment / Store DADDR Address Register (TCD15_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD15_DADDR_OFFSET (0x20c030) /* TCD15 Destination Address Register (TCD15_DADDR) */
+#define S32K3XX_EDMA_TCD15_DOFF_OFFSET (0x20c034) /* TCD15 Signed Destination Address Offset Register (TCD15_DOFF) */
+#define S32K3XX_EDMA_TCD15_CITER_OFFSET (0x20c036) /* TCD15 Current Major Loop Count Register (TCD15_CITER) */
+#define S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET (0x20c038) /* TCD15 Last Destination Address Adjustment / Scatter Gather Address Register (TCD15_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD15_CSR_OFFSET (0x20c03c) /* TCD15 Control and Status Register (TCD15_CSR) */
+#define S32K3XX_EDMA_TCD15_BITER_OFFSET (0x20c03e) /* TCD15 Beginning Major Loop Count Register (TCD15_BITER) */
+
+#define S32K3XX_EDMA_CH16_CSR_OFFSET (0x210000) /* Channel 16 Control and Status Register (CH16_CSR) */
+#define S32K3XX_EDMA_CH16_ES_OFFSET (0x210004) /* Channel 16 Error Status Register (CH16_ES) */
+#define S32K3XX_EDMA_CH16_INT_OFFSET (0x210008) /* Channel 16 Interrupt Status Register (CH16_INT) */
+#define S32K3XX_EDMA_CH16_SBR_OFFSET (0x21000c) /* Channel 16 System Bus Register (CH16_SBR) */
+#define S32K3XX_EDMA_CH16_PRI_OFFSET (0x210010) /* Channel 16 Priority Register (CH16_PRI) */
+#define S32K3XX_EDMA_TCD16_SADDR_OFFSET (0x210020) /* TCD16 Source Address Register (TCD16_SADDR) */
+#define S32K3XX_EDMA_TCD16_SOFF_OFFSET (0x210024) /* TCD16 Signed Source Address Offset Register (TCD16_SOFF) */
+#define S32K3XX_EDMA_TCD16_ATTR_OFFSET (0x210026) /* TCD16 Transfer Attributes (TCD16_ATTR) */
+#define S32K3XX_EDMA_TCD16_NBYTES_OFFSET (0x210028) /* TCD16 Transfer Size (TCD16_NBYTES) */
+#define S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET (0x21002c) /* TCD16 Last Source Address Adjustment / Store DADDR Address Register (TCD16_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD16_DADDR_OFFSET (0x210030) /* TCD16 Destination Address Register (TCD16_DADDR) */
+#define S32K3XX_EDMA_TCD16_DOFF_OFFSET (0x210034) /* TCD16 Signed Destination Address Offset Register (TCD16_DOFF) */
+#define S32K3XX_EDMA_TCD16_CITER_OFFSET (0x210036) /* TCD16 Current Major Loop Count Register (TCD16_CITER) */
+#define S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET (0x210038) /* TCD16 Last Destination Address Adjustment / Scatter Gather Address Register (TCD16_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD16_CSR_OFFSET (0x21003c) /* TCD16 Control and Status Register (TCD16_CSR) */
+#define S32K3XX_EDMA_TCD16_BITER_OFFSET (0x21003e) /* TCD16 Beginning Major Loop Count Register (TCD16_BITER) */
+
+#define S32K3XX_EDMA_CH17_CSR_OFFSET (0x214000) /* Channel 17 Control and Status Register (CH17_CSR) */
+#define S32K3XX_EDMA_CH17_ES_OFFSET (0x214004) /* Channel 17 Error Status Register (CH17_ES) */
+#define S32K3XX_EDMA_CH17_INT_OFFSET (0x214008) /* Channel 17 Interrupt Status Register (CH17_INT) */
+#define S32K3XX_EDMA_CH17_SBR_OFFSET (0x21400c) /* Channel 17 System Bus Register (CH17_SBR) */
+#define S32K3XX_EDMA_CH17_PRI_OFFSET (0x214010) /* Channel 17 Priority Register (CH17_PRI) */
+#define S32K3XX_EDMA_TCD17_SADDR_OFFSET (0x214020) /* TCD17 Source Address Register (TCD17_SADDR) */
+#define S32K3XX_EDMA_TCD17_SOFF_OFFSET (0x214024) /* TCD17 Signed Source Address Offset Register (TCD17_SOFF) */
+#define S32K3XX_EDMA_TCD17_ATTR_OFFSET (0x214026) /* TCD17 Transfer Attributes (TCD17_ATTR) */
+#define S32K3XX_EDMA_TCD17_NBYTES_OFFSET (0x214028) /* TCD17 Transfer Size (TCD17_NBYTES) */
+#define S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET (0x21402c) /* TCD17 Last Source Address Adjustment / Store DADDR Address Register (TCD17_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD17_DADDR_OFFSET (0x214030) /* TCD17 Destination Address Register (TCD17_DADDR) */
+#define S32K3XX_EDMA_TCD17_DOFF_OFFSET (0x214034) /* TCD17 Signed Destination Address Offset Register (TCD17_DOFF) */
+#define S32K3XX_EDMA_TCD17_CITER_OFFSET (0x214036) /* TCD17 Current Major Loop Count Register (TCD17_CITER) */
+#define S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET (0x214038) /* TCD17 Last Destination Address Adjustment / Scatter Gather Address Register (TCD17_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD17_CSR_OFFSET (0x21403c) /* TCD17 Control and Status Register (TCD17_CSR) */
+#define S32K3XX_EDMA_TCD17_BITER_OFFSET (0x21403e) /* TCD17 Beginning Major Loop Count Register (TCD17_BITER) */
+
+#define S32K3XX_EDMA_CH18_CSR_OFFSET (0x218000) /* Channel 18 Control and Status Register (CH18_CSR) */
+#define S32K3XX_EDMA_CH18_ES_OFFSET (0x218004) /* Channel 18 Error Status Register (CH18_ES) */
+#define S32K3XX_EDMA_CH18_INT_OFFSET (0x218008) /* Channel 18 Interrupt Status Register (CH18_INT) */
+#define S32K3XX_EDMA_CH18_SBR_OFFSET (0x21800c) /* Channel 18 System Bus Register (CH18_SBR) */
+#define S32K3XX_EDMA_CH18_PRI_OFFSET (0x218010) /* Channel 18 Priority Register (CH18_PRI) */
+#define S32K3XX_EDMA_TCD18_SADDR_OFFSET (0x218020) /* TCD18 Source Address Register (TCD18_SADDR) */
+#define S32K3XX_EDMA_TCD18_SOFF_OFFSET (0x218024) /* TCD18 Signed Source Address Offset Register (TCD18_SOFF) */
+#define S32K3XX_EDMA_TCD18_ATTR_OFFSET (0x218026) /* TCD18 Transfer Attributes (TCD18_ATTR) */
+#define S32K3XX_EDMA_TCD18_NBYTES_OFFSET (0x218028) /* TCD18 Transfer Size (TCD18_NBYTES) */
+#define S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET (0x21802c) /* TCD18 Last Source Address Adjustment / Store DADDR Address Register (TCD18_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD18_DADDR_OFFSET (0x218030) /* TCD18 Destination Address Register (TCD18_DADDR) */
+#define S32K3XX_EDMA_TCD18_DOFF_OFFSET (0x218034) /* TCD18 Signed Destination Address Offset Register (TCD18_DOFF) */
+#define S32K3XX_EDMA_TCD18_CITER_OFFSET (0x218036) /* TCD18 Current Major Loop Count Register (TCD18_CITER) */
+#define S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET (0x218038) /* TCD18 Last Destination Address Adjustment / Scatter Gather Address Register (TCD18_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD18_CSR_OFFSET (0x21803c) /* TCD18 Control and Status Register (TCD18_CSR) */
+#define S32K3XX_EDMA_TCD18_BITER_OFFSET (0x21803e) /* TCD18 Beginning Major Loop Count Register (TCD18_BITER) */
+
+#define S32K3XX_EDMA_CH19_CSR_OFFSET (0x21c000) /* Channel 19 Control and Status Register (CH19_CSR) */
+#define S32K3XX_EDMA_CH19_ES_OFFSET (0x21c004) /* Channel 19 Error Status Register (CH19_ES) */
+#define S32K3XX_EDMA_CH19_INT_OFFSET (0x21c008) /* Channel 19 Interrupt Status Register (CH19_INT) */
+#define S32K3XX_EDMA_CH19_SBR_OFFSET (0x21c00c) /* Channel 19 System Bus Register (CH19_SBR) */
+#define S32K3XX_EDMA_CH19_PRI_OFFSET (0x21c010) /* Channel 19 Priority Register (CH19_PRI) */
+#define S32K3XX_EDMA_TCD19_SADDR_OFFSET (0x21c020) /* TCD19 Source Address Register (TCD19_SADDR) */
+#define S32K3XX_EDMA_TCD19_SOFF_OFFSET (0x21c024) /* TCD19 Signed Source Address Offset Register (TCD19_SOFF) */
+#define S32K3XX_EDMA_TCD19_ATTR_OFFSET (0x21c026) /* TCD19 Transfer Attributes (TCD19_ATTR) */
+#define S32K3XX_EDMA_TCD19_NBYTES_OFFSET (0x21c028) /* TCD19 Transfer Size (TCD19_NBYTES) */
+#define S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET (0x21c02c) /* TCD19 Last Source Address Adjustment / Store DADDR Address Register (TCD19_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD19_DADDR_OFFSET (0x21c030) /* TCD19 Destination Address Register (TCD19_DADDR) */
+#define S32K3XX_EDMA_TCD19_DOFF_OFFSET (0x21c034) /* TCD19 Signed Destination Address Offset Register (TCD19_DOFF) */
+#define S32K3XX_EDMA_TCD19_CITER_OFFSET (0x21c036) /* TCD19 Current Major Loop Count Register (TCD19_CITER) */
+#define S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET (0x21c038) /* TCD19 Last Destination Address Adjustment / Scatter Gather Address Register (TCD19_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD19_CSR_OFFSET (0x21c03c) /* TCD19 Control and Status Register (TCD19_CSR) */
+#define S32K3XX_EDMA_TCD19_BITER_OFFSET (0x21c03e) /* TCD19 Beginning Major Loop Count Register (TCD19_BITER) */
+
+#define S32K3XX_EDMA_CH20_CSR_OFFSET (0x220000) /* Channel 20 Control and Status Register (CH20_CSR) */
+#define S32K3XX_EDMA_CH20_ES_OFFSET (0x220004) /* Channel 20 Error Status Register (CH20_ES) */
+#define S32K3XX_EDMA_CH20_INT_OFFSET (0x220008) /* Channel 20 Interrupt Status Register (CH20_INT) */
+#define S32K3XX_EDMA_CH20_SBR_OFFSET (0x22000c) /* Channel 20 System Bus Register (CH20_SBR) */
+#define S32K3XX_EDMA_CH20_PRI_OFFSET (0x220010) /* Channel 20 Priority Register (CH20_PRI) */
+#define S32K3XX_EDMA_TCD20_SADDR_OFFSET (0x220020) /* TCD20 Source Address Register (TCD20_SADDR) */
+#define S32K3XX_EDMA_TCD20_SOFF_OFFSET (0x220024) /* TCD20 Signed Source Address Offset Register (TCD20_SOFF) */
+#define S32K3XX_EDMA_TCD20_ATTR_OFFSET (0x220026) /* TCD20 Transfer Attributes (TCD20_ATTR) */
+#define S32K3XX_EDMA_TCD20_NBYTES_OFFSET (0x220028) /* TCD20 Transfer Size (TCD20_NBYTES) */
+#define S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET (0x22002c) /* TCD20 Last Source Address Adjustment / Store DADDR Address Register (TCD20_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD20_DADDR_OFFSET (0x220030) /* TCD20 Destination Address Register (TCD20_DADDR) */
+#define S32K3XX_EDMA_TCD20_DOFF_OFFSET (0x220034) /* TCD20 Signed Destination Address Offset Register (TCD20_DOFF) */
+#define S32K3XX_EDMA_TCD20_CITER_OFFSET (0x220036) /* TCD20 Current Major Loop Count Register (TCD20_CITER) */
+#define S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET (0x220038) /* TCD20 Last Destination Address Adjustment / Scatter Gather Address Register (TCD20_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD20_CSR_OFFSET (0x22003c) /* TCD20 Control and Status Register (TCD20_CSR) */
+#define S32K3XX_EDMA_TCD20_BITER_OFFSET (0x22003e) /* TCD20 Beginning Major Loop Count Register (TCD20_BITER) */
+
+#define S32K3XX_EDMA_CH21_CSR_OFFSET (0x224000) /* Channel 21 Control and Status Register (CH21_CSR) */
+#define S32K3XX_EDMA_CH21_ES_OFFSET (0x224004) /* Channel 21 Error Status Register (CH21_ES) */
+#define S32K3XX_EDMA_CH21_INT_OFFSET (0x224008) /* Channel 21 Interrupt Status Register (CH21_INT) */
+#define S32K3XX_EDMA_CH21_SBR_OFFSET (0x22400c) /* Channel 21 System Bus Register (CH21_SBR) */
+#define S32K3XX_EDMA_CH21_PRI_OFFSET (0x224010) /* Channel 21 Priority Register (CH21_PRI) */
+#define S32K3XX_EDMA_TCD21_SADDR_OFFSET (0x224020) /* TCD21 Source Address Register (TCD21_SADDR) */
+#define S32K3XX_EDMA_TCD21_SOFF_OFFSET (0x224024) /* TCD21 Signed Source Address Offset Register (TCD21_SOFF) */
+#define S32K3XX_EDMA_TCD21_ATTR_OFFSET (0x224026) /* TCD21 Transfer Attributes (TCD21_ATTR) */
+#define S32K3XX_EDMA_TCD21_NBYTES_OFFSET (0x224028) /* TCD21 Transfer Size (TCD21_NBYTES) */
+#define S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET (0x22402c) /* TCD21 Last Source Address Adjustment / Store DADDR Address Register (TCD21_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD21_DADDR_OFFSET (0x224030) /* TCD21 Destination Address Register (TCD21_DADDR) */
+#define S32K3XX_EDMA_TCD21_DOFF_OFFSET (0x224034) /* TCD21 Signed Destination Address Offset Register (TCD21_DOFF) */
+#define S32K3XX_EDMA_TCD21_CITER_OFFSET (0x224036) /* TCD21 Current Major Loop Count Register (TCD21_CITER) */
+#define S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET (0x224038) /* TCD21 Last Destination Address Adjustment / Scatter Gather Address Register (TCD21_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD21_CSR_OFFSET (0x22403c) /* TCD21 Control and Status Register (TCD21_CSR) */
+#define S32K3XX_EDMA_TCD21_BITER_OFFSET (0x22403e) /* TCD21 Beginning Major Loop Count Register (TCD21_BITER) */
+
+#define S32K3XX_EDMA_CH22_CSR_OFFSET (0x228000) /* Channel 22 Control and Status Register (CH22_CSR) */
+#define S32K3XX_EDMA_CH22_ES_OFFSET (0x228004) /* Channel 22 Error Status Register (CH22_ES) */
+#define S32K3XX_EDMA_CH22_INT_OFFSET (0x228008) /* Channel 22 Interrupt Status Register (CH22_INT) */
+#define S32K3XX_EDMA_CH22_SBR_OFFSET (0x22800c) /* Channel 22 System Bus Register (CH22_SBR) */
+#define S32K3XX_EDMA_CH22_PRI_OFFSET (0x228010) /* Channel 22 Priority Register (CH22_PRI) */
+#define S32K3XX_EDMA_TCD22_SADDR_OFFSET (0x228020) /* TCD22 Source Address Register (TCD22_SADDR) */
+#define S32K3XX_EDMA_TCD22_SOFF_OFFSET (0x228024) /* TCD22 Signed Source Address Offset Register (TCD22_SOFF) */
+#define S32K3XX_EDMA_TCD22_ATTR_OFFSET (0x228026) /* TCD22 Transfer Attributes (TCD22_ATTR) */
+#define S32K3XX_EDMA_TCD22_NBYTES_OFFSET (0x228028) /* TCD22 Transfer Size (TCD22_NBYTES) */
+#define S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET (0x22802c) /* TCD22 Last Source Address Adjustment / Store DADDR Address Register (TCD22_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD22_DADDR_OFFSET (0x228030) /* TCD22 Destination Address Register (TCD22_DADDR) */
+#define S32K3XX_EDMA_TCD22_DOFF_OFFSET (0x228034) /* TCD22 Signed Destination Address Offset Register (TCD22_DOFF) */
+#define S32K3XX_EDMA_TCD22_CITER_OFFSET (0x228036) /* TCD22 Current Major Loop Count Register (TCD22_CITER) */
+#define S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET (0x228038) /* TCD22 Last Destination Address Adjustment / Scatter Gather Address Register (TCD22_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD22_CSR_OFFSET (0x22803c) /* TCD22 Control and Status Register (TCD22_CSR) */
+#define S32K3XX_EDMA_TCD22_BITER_OFFSET (0x22803e) /* TCD22 Beginning Major Loop Count Register (TCD22_BITER) */
+
+#define S32K3XX_EDMA_CH23_CSR_OFFSET (0x22c000) /* Channel 23 Control and Status Register (CH23_CSR) */
+#define S32K3XX_EDMA_CH23_ES_OFFSET (0x22c004) /* Channel 23 Error Status Register (CH23_ES) */
+#define S32K3XX_EDMA_CH23_INT_OFFSET (0x22c008) /* Channel 23 Interrupt Status Register (CH23_INT) */
+#define S32K3XX_EDMA_CH23_SBR_OFFSET (0x22c00c) /* Channel 23 System Bus Register (CH23_SBR) */
+#define S32K3XX_EDMA_CH23_PRI_OFFSET (0x22c010) /* Channel 23 Priority Register (CH23_PRI) */
+#define S32K3XX_EDMA_TCD23_SADDR_OFFSET (0x22c020) /* TCD23 Source Address Register (TCD23_SADDR) */
+#define S32K3XX_EDMA_TCD23_SOFF_OFFSET (0x22c024) /* TCD23 Signed Source Address Offset Register (TCD23_SOFF) */
+#define S32K3XX_EDMA_TCD23_ATTR_OFFSET (0x22c026) /* TCD23 Transfer Attributes (TCD23_ATTR) */
+#define S32K3XX_EDMA_TCD23_NBYTES_OFFSET (0x22c028) /* TCD23 Transfer Size (TCD23_NBYTES) */
+#define S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET (0x22c02c) /* TCD23 Last Source Address Adjustment / Store DADDR Address Register (TCD23_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD23_DADDR_OFFSET (0x22c030) /* TCD23 Destination Address Register (TCD23_DADDR) */
+#define S32K3XX_EDMA_TCD23_DOFF_OFFSET (0x22c034) /* TCD23 Signed Destination Address Offset Register (TCD23_DOFF) */
+#define S32K3XX_EDMA_TCD23_CITER_OFFSET (0x22c036) /* TCD23 Current Major Loop Count Register (TCD23_CITER) */
+#define S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET (0x22c038) /* TCD23 Last Destination Address Adjustment / Scatter Gather Address Register (TCD23_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD23_CSR_OFFSET (0x22c03c) /* TCD23 Control and Status Register (TCD23_CSR) */
+#define S32K3XX_EDMA_TCD23_BITER_OFFSET (0x22c03e) /* TCD23 Beginning Major Loop Count Register (TCD23_BITER) */
+
+#define S32K3XX_EDMA_CH24_CSR_OFFSET (0x230000) /* Channel 24 Control and Status Register (CH24_CSR) */
+#define S32K3XX_EDMA_CH24_ES_OFFSET (0x230004) /* Channel 24 Error Status Register (CH24_ES) */
+#define S32K3XX_EDMA_CH24_INT_OFFSET (0x230008) /* Channel 24 Interrupt Status Register (CH24_INT) */
+#define S32K3XX_EDMA_CH24_SBR_OFFSET (0x23000c) /* Channel 24 System Bus Register (CH24_SBR) */
+#define S32K3XX_EDMA_CH24_PRI_OFFSET (0x230010) /* Channel 24 Priority Register (CH24_PRI) */
+#define S32K3XX_EDMA_TCD24_SADDR_OFFSET (0x230020) /* TCD24 Source Address Register (TCD24_SADDR) */
+#define S32K3XX_EDMA_TCD24_SOFF_OFFSET (0x230024) /* TCD24 Signed Source Address Offset Register (TCD24_SOFF) */
+#define S32K3XX_EDMA_TCD24_ATTR_OFFSET (0x230026) /* TCD24 Transfer Attributes (TCD24_ATTR) */
+#define S32K3XX_EDMA_TCD24_NBYTES_OFFSET (0x230028) /* TCD24 Transfer Size (TCD24_NBYTES) */
+#define S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET (0x23002c) /* TCD24 Last Source Address Adjustment / Store DADDR Address Register (TCD24_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD24_DADDR_OFFSET (0x230030) /* TCD24 Destination Address Register (TCD24_DADDR) */
+#define S32K3XX_EDMA_TCD24_DOFF_OFFSET (0x230034) /* TCD24 Signed Destination Address Offset Register (TCD24_DOFF) */
+#define S32K3XX_EDMA_TCD24_CITER_OFFSET (0x230036) /* TCD24 Current Major Loop Count Register (TCD24_CITER) */
+#define S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET (0x230038) /* TCD24 Last Destination Address Adjustment / Scatter Gather Address Register (TCD24_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD24_CSR_OFFSET (0x23003c) /* TCD24 Control and Status Register (TCD24_CSR) */
+#define S32K3XX_EDMA_TCD24_BITER_OFFSET (0x23003e) /* TCD24 Beginning Major Loop Count Register (TCD24_BITER) */
+
+#define S32K3XX_EDMA_CH25_CSR_OFFSET (0x234000) /* Channel 25 Control and Status Register (CH25_CSR) */
+#define S32K3XX_EDMA_CH25_ES_OFFSET (0x234004) /* Channel 25 Error Status Register (CH25_ES) */
+#define S32K3XX_EDMA_CH25_INT_OFFSET (0x234008) /* Channel 25 Interrupt Status Register (CH25_INT) */
+#define S32K3XX_EDMA_CH25_SBR_OFFSET (0x23400c) /* Channel 25 System Bus Register (CH25_SBR) */
+#define S32K3XX_EDMA_CH25_PRI_OFFSET (0x234010) /* Channel 25 Priority Register (CH25_PRI) */
+#define S32K3XX_EDMA_TCD25_SADDR_OFFSET (0x234020) /* TCD25 Source Address Register (TCD25_SADDR) */
+#define S32K3XX_EDMA_TCD25_SOFF_OFFSET (0x234024) /* TCD25 Signed Source Address Offset Register (TCD25_SOFF) */
+#define S32K3XX_EDMA_TCD25_ATTR_OFFSET (0x234026) /* TCD25 Transfer Attributes (TCD25_ATTR) */
+#define S32K3XX_EDMA_TCD25_NBYTES_OFFSET (0x234028) /* TCD25 Transfer Size (TCD25_NBYTES) */
+#define S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET (0x23402c) /* TCD25 Last Source Address Adjustment / Store DADDR Address Register (TCD25_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD25_DADDR_OFFSET (0x234030) /* TCD25 Destination Address Register (TCD25_DADDR) */
+#define S32K3XX_EDMA_TCD25_DOFF_OFFSET (0x234034) /* TCD25 Signed Destination Address Offset Register (TCD25_DOFF) */
+#define S32K3XX_EDMA_TCD25_CITER_OFFSET (0x234036) /* TCD25 Current Major Loop Count Register (TCD25_CITER) */
+#define S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET (0x234038) /* TCD25 Last Destination Address Adjustment / Scatter Gather Address Register (TCD25_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD25_CSR_OFFSET (0x23403c) /* TCD25 Control and Status Register (TCD25_CSR) */
+#define S32K3XX_EDMA_TCD25_BITER_OFFSET (0x23403e) /* TCD25 Beginning Major Loop Count Register (TCD25_BITER) */
+
+#define S32K3XX_EDMA_CH26_CSR_OFFSET (0x238000) /* Channel 26 Control and Status Register (CH26_CSR) */
+#define S32K3XX_EDMA_CH26_ES_OFFSET (0x238004) /* Channel 26 Error Status Register (CH26_ES) */
+#define S32K3XX_EDMA_CH26_INT_OFFSET (0x238008) /* Channel 26 Interrupt Status Register (CH26_INT) */
+#define S32K3XX_EDMA_CH26_SBR_OFFSET (0x23800c) /* Channel 26 System Bus Register (CH26_SBR) */
+#define S32K3XX_EDMA_CH26_PRI_OFFSET (0x238010) /* Channel 26 Priority Register (CH26_PRI) */
+#define S32K3XX_EDMA_TCD26_SADDR_OFFSET (0x238020) /* TCD26 Source Address Register (TCD26_SADDR) */
+#define S32K3XX_EDMA_TCD26_SOFF_OFFSET (0x238024) /* TCD26 Signed Source Address Offset Register (TCD26_SOFF) */
+#define S32K3XX_EDMA_TCD26_ATTR_OFFSET (0x238026) /* TCD26 Transfer Attributes (TCD26_ATTR) */
+#define S32K3XX_EDMA_TCD26_NBYTES_OFFSET (0x238028) /* TCD26 Transfer Size (TCD26_NBYTES) */
+#define S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET (0x23802c) /* TCD26 Last Source Address Adjustment / Store DADDR Address Register (TCD26_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD26_DADDR_OFFSET (0x238030) /* TCD26 Destination Address Register (TCD26_DADDR) */
+#define S32K3XX_EDMA_TCD26_DOFF_OFFSET (0x238034) /* TCD26 Signed Destination Address Offset Register (TCD26_DOFF) */
+#define S32K3XX_EDMA_TCD26_CITER_OFFSET (0x238036) /* TCD26 Current Major Loop Count Register (TCD26_CITER) */
+#define S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET (0x238038) /* TCD26 Last Destination Address Adjustment / Scatter Gather Address Register (TCD26_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD26_CSR_OFFSET (0x23803c) /* TCD26 Control and Status Register (TCD26_CSR) */
+#define S32K3XX_EDMA_TCD26_BITER_OFFSET (0x23803e) /* TCD26 Beginning Major Loop Count Register (TCD26_BITER) */
+
+#define S32K3XX_EDMA_CH27_CSR_OFFSET (0x23c000) /* Channel 27 Control and Status Register (CH27_CSR) */
+#define S32K3XX_EDMA_CH27_ES_OFFSET (0x23c004) /* Channel 27 Error Status Register (CH27_ES) */
+#define S32K3XX_EDMA_CH27_INT_OFFSET (0x23c008) /* Channel 27 Interrupt Status Register (CH27_INT) */
+#define S32K3XX_EDMA_CH27_SBR_OFFSET (0x23c00c) /* Channel 27 System Bus Register (CH27_SBR) */
+#define S32K3XX_EDMA_CH27_PRI_OFFSET (0x23c010) /* Channel 27 Priority Register (CH27_PRI) */
+#define S32K3XX_EDMA_TCD27_SADDR_OFFSET (0x23c020) /* TCD27 Source Address Register (TCD27_SADDR) */
+#define S32K3XX_EDMA_TCD27_SOFF_OFFSET (0x23c024) /* TCD27 Signed Source Address Offset Register (TCD27_SOFF) */
+#define S32K3XX_EDMA_TCD27_ATTR_OFFSET (0x23c026) /* TCD27 Transfer Attributes (TCD27_ATTR) */
+#define S32K3XX_EDMA_TCD27_NBYTES_OFFSET (0x23c028) /* TCD27 Transfer Size (TCD27_NBYTES) */
+#define S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET (0x23c02c) /* TCD27 Last Source Address Adjustment / Store DADDR Address Register (TCD27_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD27_DADDR_OFFSET (0x23c030) /* TCD27 Destination Address Register (TCD27_DADDR) */
+#define S32K3XX_EDMA_TCD27_DOFF_OFFSET (0x23c034) /* TCD27 Signed Destination Address Offset Register (TCD27_DOFF) */
+#define S32K3XX_EDMA_TCD27_CITER_OFFSET (0x23c036) /* TCD27 Current Major Loop Count Register (TCD27_CITER) */
+#define S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET (0x23c038) /* TCD27 Last Destination Address Adjustment / Scatter Gather Address Register (TCD27_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD27_CSR_OFFSET (0x23c03c) /* TCD27 Control and Status Register (TCD27_CSR) */
+#define S32K3XX_EDMA_TCD27_BITER_OFFSET (0x23c03e) /* TCD27 Beginning Major Loop Count Register (TCD27_BITER) */
+
+#define S32K3XX_EDMA_CH28_CSR_OFFSET (0x240000) /* Channel 28 Control and Status Register (CH28_CSR) */
+#define S32K3XX_EDMA_CH28_ES_OFFSET (0x240004) /* Channel 28 Error Status Register (CH28_ES) */
+#define S32K3XX_EDMA_CH28_INT_OFFSET (0x240008) /* Channel 28 Interrupt Status Register (CH28_INT) */
+#define S32K3XX_EDMA_CH28_SBR_OFFSET (0x24000c) /* Channel 28 System Bus Register (CH28_SBR) */
+#define S32K3XX_EDMA_CH28_PRI_OFFSET (0x240010) /* Channel 28 Priority Register (CH28_PRI) */
+#define S32K3XX_EDMA_TCD28_SADDR_OFFSET (0x240020) /* TCD28 Source Address Register (TCD28_SADDR) */
+#define S32K3XX_EDMA_TCD28_SOFF_OFFSET (0x240024) /* TCD28 Signed Source Address Offset Register (TCD28_SOFF) */
+#define S32K3XX_EDMA_TCD28_ATTR_OFFSET (0x240026) /* TCD28 Transfer Attributes (TCD28_ATTR) */
+#define S32K3XX_EDMA_TCD28_NBYTES_OFFSET (0x240028) /* TCD28 Transfer Size (TCD28_NBYTES) */
+#define S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET (0x24002c) /* TCD28 Last Source Address Adjustment / Store DADDR Address Register (TCD28_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD28_DADDR_OFFSET (0x240030) /* TCD28 Destination Address Register (TCD28_DADDR) */
+#define S32K3XX_EDMA_TCD28_DOFF_OFFSET (0x240034) /* TCD28 Signed Destination Address Offset Register (TCD28_DOFF) */
+#define S32K3XX_EDMA_TCD28_CITER_OFFSET (0x240036) /* TCD28 Current Major Loop Count Register (TCD28_CITER) */
+#define S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET (0x240038) /* TCD28 Last Destination Address Adjustment / Scatter Gather Address Register (TCD28_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD28_CSR_OFFSET (0x24003c) /* TCD28 Control and Status Register (TCD28_CSR) */
+#define S32K3XX_EDMA_TCD28_BITER_OFFSET (0x24003e) /* TCD28 Beginning Major Loop Count Register (TCD28_BITER) */
+
+#define S32K3XX_EDMA_CH29_CSR_OFFSET (0x244000) /* Channel 29 Control and Status Register (CH29_CSR) */
+#define S32K3XX_EDMA_CH29_ES_OFFSET (0x244004) /* Channel 29 Error Status Register (CH29_ES) */
+#define S32K3XX_EDMA_CH29_INT_OFFSET (0x244008) /* Channel 29 Interrupt Status Register (CH29_INT) */
+#define S32K3XX_EDMA_CH29_SBR_OFFSET (0x24400c) /* Channel 29 System Bus Register (CH29_SBR) */
+#define S32K3XX_EDMA_CH29_PRI_OFFSET (0x244010) /* Channel 29 Priority Register (CH29_PRI) */
+#define S32K3XX_EDMA_TCD29_SADDR_OFFSET (0x244020) /* TCD29 Source Address Register (TCD29_SADDR) */
+#define S32K3XX_EDMA_TCD29_SOFF_OFFSET (0x244024) /* TCD29 Signed Source Address Offset Register (TCD29_SOFF) */
+#define S32K3XX_EDMA_TCD29_ATTR_OFFSET (0x244026) /* TCD29 Transfer Attributes (TCD29_ATTR) */
+#define S32K3XX_EDMA_TCD29_NBYTES_OFFSET (0x244028) /* TCD29 Transfer Size (TCD29_NBYTES) */
+#define S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET (0x24402c) /* TCD29 Last Source Address Adjustment / Store DADDR Address Register (TCD29_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD29_DADDR_OFFSET (0x244030) /* TCD29 Destination Address Register (TCD29_DADDR) */
+#define S32K3XX_EDMA_TCD29_DOFF_OFFSET (0x244034) /* TCD29 Signed Destination Address Offset Register (TCD29_DOFF) */
+#define S32K3XX_EDMA_TCD29_CITER_OFFSET (0x244036) /* TCD29 Current Major Loop Count Register (TCD29_CITER) */
+#define S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET (0x244038) /* TCD29 Last Destination Address Adjustment / Scatter Gather Address Register (TCD29_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD29_CSR_OFFSET (0x24403c) /* TCD29 Control and Status Register (TCD29_CSR) */
+#define S32K3XX_EDMA_TCD29_BITER_OFFSET (0x24403e) /* TCD29 Beginning Major Loop Count Register (TCD29_BITER) */
+
+#define S32K3XX_EDMA_CH30_CSR_OFFSET (0x248000) /* Channel 30 Control and Status Register (CH30_CSR) */
+#define S32K3XX_EDMA_CH30_ES_OFFSET (0x248004) /* Channel 30 Error Status Register (CH30_ES) */
+#define S32K3XX_EDMA_CH30_INT_OFFSET (0x248008) /* Channel 30 Interrupt Status Register (CH30_INT) */
+#define S32K3XX_EDMA_CH30_SBR_OFFSET (0x24800c) /* Channel 30 System Bus Register (CH30_SBR) */
+#define S32K3XX_EDMA_CH30_PRI_OFFSET (0x248010) /* Channel 30 Priority Register (CH30_PRI) */
+#define S32K3XX_EDMA_TCD30_SADDR_OFFSET (0x248020) /* TCD30 Source Address Register (TCD30_SADDR) */
+#define S32K3XX_EDMA_TCD30_SOFF_OFFSET (0x248024) /* TCD30 Signed Source Address Offset Register (TCD30_SOFF) */
+#define S32K3XX_EDMA_TCD30_ATTR_OFFSET (0x248026) /* TCD30 Transfer Attributes (TCD30_ATTR) */
+#define S32K3XX_EDMA_TCD30_NBYTES_OFFSET (0x248028) /* TCD30 Transfer Size (TCD30_NBYTES) */
+#define S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET (0x24802c) /* TCD30 Last Source Address Adjustment / Store DADDR Address Register (TCD30_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD30_DADDR_OFFSET (0x248030) /* TCD30 Destination Address Register (TCD30_DADDR) */
+#define S32K3XX_EDMA_TCD30_DOFF_OFFSET (0x248034) /* TCD30 Signed Destination Address Offset Register (TCD30_DOFF) */
+#define S32K3XX_EDMA_TCD30_CITER_OFFSET (0x248036) /* TCD30 Current Major Loop Count Register (TCD30_CITER) */
+#define S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET (0x248038) /* TCD30 Last Destination Address Adjustment / Scatter Gather Address Register (TCD30_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD30_CSR_OFFSET (0x24803c) /* TCD30 Control and Status Register (TCD30_CSR) */
+#define S32K3XX_EDMA_TCD30_BITER_OFFSET (0x24803e) /* TCD30 Beginning Major Loop Count Register (TCD30_BITER) */
+
+#define S32K3XX_EDMA_CH31_CSR_OFFSET (0x24c000) /* Channel 31 Control and Status Register (CH31_CSR) */
+#define S32K3XX_EDMA_CH31_ES_OFFSET (0x24c004) /* Channel 31 Error Status Register (CH31_ES) */
+#define S32K3XX_EDMA_CH31_INT_OFFSET (0x24c008) /* Channel 31 Interrupt Status Register (CH31_INT) */
+#define S32K3XX_EDMA_CH31_SBR_OFFSET (0x24c00c) /* Channel 31 System Bus Register (CH31_SBR) */
+#define S32K3XX_EDMA_CH31_PRI_OFFSET (0x24c010) /* Channel 31 Priority Register (CH31_PRI) */
+#define S32K3XX_EDMA_TCD31_SADDR_OFFSET (0x24c020) /* TCD31 Source Address Register (TCD31_SADDR) */
+#define S32K3XX_EDMA_TCD31_SOFF_OFFSET (0x24c024) /* TCD31 Signed Source Address Offset Register (TCD31_SOFF) */
+#define S32K3XX_EDMA_TCD31_ATTR_OFFSET (0x24c026) /* TCD31 Transfer Attributes (TCD31_ATTR) */
+#define S32K3XX_EDMA_TCD31_NBYTES_OFFSET (0x24c028) /* TCD31 Transfer Size (TCD31_NBYTES) */
+#define S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET (0x24c02c) /* TCD31 Last Source Address Adjustment / Store DADDR Address Register (TCD31_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD31_DADDR_OFFSET (0x24c030) /* TCD31 Destination Address Register (TCD31_DADDR) */
+#define S32K3XX_EDMA_TCD31_DOFF_OFFSET (0x24c034) /* TCD31 Signed Destination Address Offset Register (TCD31_DOFF) */
+#define S32K3XX_EDMA_TCD31_CITER_OFFSET (0x24c036) /* TCD31 Current Major Loop Count Register (TCD31_CITER) */
+#define S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET (0x24c038) /* TCD31 Last Destination Address Adjustment / Scatter Gather Address Register (TCD31_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD31_CSR_OFFSET (0x24c03c) /* TCD31 Control and Status Register (TCD31_CSR) */
+#define S32K3XX_EDMA_TCD31_BITER_OFFSET (0x24c03e) /* TCD31 Beginning Major Loop Count Register (TCD31_BITER) */
+
+/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/
+
+#define S32K3XX_EDMA_CH0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_CSR_OFFSET)
+#define S32K3XX_EDMA_CH0_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_ES_OFFSET)
+#define S32K3XX_EDMA_CH0_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_INT_OFFSET)
+#define S32K3XX_EDMA_CH0_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_SBR_OFFSET)
+#define S32K3XX_EDMA_CH0_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD0_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD0_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD0_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD0_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD0_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD0_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_CSR_OFFSET)
+#define S32K3XX_EDMA_CH1_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_ES_OFFSET)
+#define S32K3XX_EDMA_CH1_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_INT_OFFSET)
+#define S32K3XX_EDMA_CH1_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_SBR_OFFSET)
+#define S32K3XX_EDMA_CH1_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD1_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD1_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD1_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD1_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD1_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD1_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_CSR_OFFSET)
+#define S32K3XX_EDMA_CH2_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_ES_OFFSET)
+#define S32K3XX_EDMA_CH2_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_INT_OFFSET)
+#define S32K3XX_EDMA_CH2_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_SBR_OFFSET)
+#define S32K3XX_EDMA_CH2_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD2_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD2_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD2_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD2_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD2_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD2_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_CSR_OFFSET)
+#define S32K3XX_EDMA_CH3_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_ES_OFFSET)
+#define S32K3XX_EDMA_CH3_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_INT_OFFSET)
+#define S32K3XX_EDMA_CH3_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_SBR_OFFSET)
+#define S32K3XX_EDMA_CH3_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD3_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD3_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD3_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD3_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD3_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD3_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_CSR_OFFSET)
+#define S32K3XX_EDMA_CH4_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_ES_OFFSET)
+#define S32K3XX_EDMA_CH4_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_INT_OFFSET)
+#define S32K3XX_EDMA_CH4_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_SBR_OFFSET)
+#define S32K3XX_EDMA_CH4_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD4_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD4_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD4_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD4_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD4_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD4_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_CSR_OFFSET)
+#define S32K3XX_EDMA_CH5_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_ES_OFFSET)
+#define S32K3XX_EDMA_CH5_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_INT_OFFSET)
+#define S32K3XX_EDMA_CH5_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_SBR_OFFSET)
+#define S32K3XX_EDMA_CH5_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD5_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD5_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD5_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD5_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD5_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD5_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_CSR_OFFSET)
+#define S32K3XX_EDMA_CH6_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_ES_OFFSET)
+#define S32K3XX_EDMA_CH6_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_INT_OFFSET)
+#define S32K3XX_EDMA_CH6_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_SBR_OFFSET)
+#define S32K3XX_EDMA_CH6_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD6_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD6_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD6_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD6_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD6_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD6_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_CSR_OFFSET)
+#define S32K3XX_EDMA_CH7_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_ES_OFFSET)
+#define S32K3XX_EDMA_CH7_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_INT_OFFSET)
+#define S32K3XX_EDMA_CH7_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_SBR_OFFSET)
+#define S32K3XX_EDMA_CH7_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD7_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD7_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD7_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD7_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD7_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD7_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_CSR_OFFSET)
+#define S32K3XX_EDMA_CH8_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_ES_OFFSET)
+#define S32K3XX_EDMA_CH8_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_INT_OFFSET)
+#define S32K3XX_EDMA_CH8_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_SBR_OFFSET)
+#define S32K3XX_EDMA_CH8_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD8_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD8_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD8_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD8_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD8_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD8_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_CSR_OFFSET)
+#define S32K3XX_EDMA_CH9_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_ES_OFFSET)
+#define S32K3XX_EDMA_CH9_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_INT_OFFSET)
+#define S32K3XX_EDMA_CH9_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_SBR_OFFSET)
+#define S32K3XX_EDMA_CH9_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD9_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD9_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD9_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD9_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD9_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD9_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_CSR_OFFSET)
+#define S32K3XX_EDMA_CH10_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_ES_OFFSET)
+#define S32K3XX_EDMA_CH10_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_INT_OFFSET)
+#define S32K3XX_EDMA_CH10_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_SBR_OFFSET)
+#define S32K3XX_EDMA_CH10_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD10_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD10_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD10_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD10_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD10_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD10_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_CSR_OFFSET)
+#define S32K3XX_EDMA_CH11_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_ES_OFFSET)
+#define S32K3XX_EDMA_CH11_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_INT_OFFSET)
+#define S32K3XX_EDMA_CH11_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_SBR_OFFSET)
+#define S32K3XX_EDMA_CH11_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD11_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD11_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD11_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD11_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD11_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD11_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_CSR_OFFSET)
+#define S32K3XX_EDMA_CH12_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_ES_OFFSET)
+#define S32K3XX_EDMA_CH12_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_INT_OFFSET)
+#define S32K3XX_EDMA_CH12_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_SBR_OFFSET)
+#define S32K3XX_EDMA_CH12_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD12_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD12_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD12_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD12_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD12_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD12_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_CSR_OFFSET)
+#define S32K3XX_EDMA_CH13_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_ES_OFFSET)
+#define S32K3XX_EDMA_CH13_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_INT_OFFSET)
+#define S32K3XX_EDMA_CH13_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_SBR_OFFSET)
+#define S32K3XX_EDMA_CH13_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD13_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD13_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD13_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD13_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD13_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD13_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_CSR_OFFSET)
+#define S32K3XX_EDMA_CH14_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_ES_OFFSET)
+#define S32K3XX_EDMA_CH14_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_INT_OFFSET)
+#define S32K3XX_EDMA_CH14_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_SBR_OFFSET)
+#define S32K3XX_EDMA_CH14_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD14_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD14_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD14_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD14_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD14_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD14_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_CSR_OFFSET)
+#define S32K3XX_EDMA_CH15_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_ES_OFFSET)
+#define S32K3XX_EDMA_CH15_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_INT_OFFSET)
+#define S32K3XX_EDMA_CH15_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_SBR_OFFSET)
+#define S32K3XX_EDMA_CH15_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD15_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD15_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD15_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD15_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD15_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD15_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_CSR_OFFSET)
+#define S32K3XX_EDMA_CH16_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_ES_OFFSET)
+#define S32K3XX_EDMA_CH16_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_INT_OFFSET)
+#define S32K3XX_EDMA_CH16_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_SBR_OFFSET)
+#define S32K3XX_EDMA_CH16_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD16_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD16_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD16_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD16_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD16_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD16_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_CSR_OFFSET)
+#define S32K3XX_EDMA_CH17_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_ES_OFFSET)
+#define S32K3XX_EDMA_CH17_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_INT_OFFSET)
+#define S32K3XX_EDMA_CH17_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_SBR_OFFSET)
+#define S32K3XX_EDMA_CH17_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD17_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD17_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD17_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD17_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD17_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD17_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_CSR_OFFSET)
+#define S32K3XX_EDMA_CH18_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_ES_OFFSET)
+#define S32K3XX_EDMA_CH18_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_INT_OFFSET)
+#define S32K3XX_EDMA_CH18_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_SBR_OFFSET)
+#define S32K3XX_EDMA_CH18_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD18_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD18_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD18_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD18_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD18_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD18_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_CSR_OFFSET)
+#define S32K3XX_EDMA_CH19_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_ES_OFFSET)
+#define S32K3XX_EDMA_CH19_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_INT_OFFSET)
+#define S32K3XX_EDMA_CH19_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_SBR_OFFSET)
+#define S32K3XX_EDMA_CH19_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD19_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD19_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD19_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD19_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD19_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD19_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_CSR_OFFSET)
+#define S32K3XX_EDMA_CH20_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_ES_OFFSET)
+#define S32K3XX_EDMA_CH20_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_INT_OFFSET)
+#define S32K3XX_EDMA_CH20_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_SBR_OFFSET)
+#define S32K3XX_EDMA_CH20_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD20_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD20_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD20_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD20_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD20_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD20_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_CSR_OFFSET)
+#define S32K3XX_EDMA_CH21_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_ES_OFFSET)
+#define S32K3XX_EDMA_CH21_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_INT_OFFSET)
+#define S32K3XX_EDMA_CH21_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_SBR_OFFSET)
+#define S32K3XX_EDMA_CH21_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD21_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD21_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD21_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD21_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD21_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD21_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_CSR_OFFSET)
+#define S32K3XX_EDMA_CH22_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_ES_OFFSET)
+#define S32K3XX_EDMA_CH22_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_INT_OFFSET)
+#define S32K3XX_EDMA_CH22_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_SBR_OFFSET)
+#define S32K3XX_EDMA_CH22_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD22_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD22_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD22_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD22_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD22_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD22_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_CSR_OFFSET)
+#define S32K3XX_EDMA_CH23_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_ES_OFFSET)
+#define S32K3XX_EDMA_CH23_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_INT_OFFSET)
+#define S32K3XX_EDMA_CH23_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_SBR_OFFSET)
+#define S32K3XX_EDMA_CH23_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD23_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD23_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD23_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD23_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD23_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD23_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_CSR_OFFSET)
+#define S32K3XX_EDMA_CH24_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_ES_OFFSET)
+#define S32K3XX_EDMA_CH24_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_INT_OFFSET)
+#define S32K3XX_EDMA_CH24_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_SBR_OFFSET)
+#define S32K3XX_EDMA_CH24_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD24_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD24_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD24_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD24_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD24_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD24_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_CSR_OFFSET)
+#define S32K3XX_EDMA_CH25_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_ES_OFFSET)
+#define S32K3XX_EDMA_CH25_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_INT_OFFSET)
+#define S32K3XX_EDMA_CH25_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_SBR_OFFSET)
+#define S32K3XX_EDMA_CH25_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD25_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD25_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD25_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD25_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD25_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD25_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_CSR_OFFSET)
+#define S32K3XX_EDMA_CH26_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_ES_OFFSET)
+#define S32K3XX_EDMA_CH26_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_INT_OFFSET)
+#define S32K3XX_EDMA_CH26_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_SBR_OFFSET)
+#define S32K3XX_EDMA_CH26_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD26_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD26_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD26_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD26_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD26_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD26_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_CSR_OFFSET)
+#define S32K3XX_EDMA_CH27_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_ES_OFFSET)
+#define S32K3XX_EDMA_CH27_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_INT_OFFSET)
+#define S32K3XX_EDMA_CH27_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_SBR_OFFSET)
+#define S32K3XX_EDMA_CH27_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD27_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD27_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD27_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD27_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD27_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD27_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_CSR_OFFSET)
+#define S32K3XX_EDMA_CH28_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_ES_OFFSET)
+#define S32K3XX_EDMA_CH28_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_INT_OFFSET)
+#define S32K3XX_EDMA_CH28_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_SBR_OFFSET)
+#define S32K3XX_EDMA_CH28_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD28_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD28_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD28_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD28_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD28_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD28_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_CSR_OFFSET)
+#define S32K3XX_EDMA_CH29_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_ES_OFFSET)
+#define S32K3XX_EDMA_CH29_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_INT_OFFSET)
+#define S32K3XX_EDMA_CH29_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_SBR_OFFSET)
+#define S32K3XX_EDMA_CH29_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD29_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD29_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD29_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD29_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD29_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD29_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_CSR_OFFSET)
+#define S32K3XX_EDMA_CH30_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_ES_OFFSET)
+#define S32K3XX_EDMA_CH30_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_INT_OFFSET)
+#define S32K3XX_EDMA_CH30_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_SBR_OFFSET)
+#define S32K3XX_EDMA_CH30_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD30_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD30_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD30_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD30_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD30_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD30_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_CSR_OFFSET)
+#define S32K3XX_EDMA_CH31_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_ES_OFFSET)
+#define S32K3XX_EDMA_CH31_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_INT_OFFSET)
+#define S32K3XX_EDMA_CH31_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_SBR_OFFSET)
+#define S32K3XX_EDMA_CH31_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD31_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD31_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD31_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD31_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD31_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD31_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_BITER_OFFSET)
+
+uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
+{
+ S32K3XX_EDMA_CH0_CSR,
+ S32K3XX_EDMA_CH1_CSR,
+ S32K3XX_EDMA_CH2_CSR,
+ S32K3XX_EDMA_CH3_CSR,
+ S32K3XX_EDMA_CH4_CSR,
+ S32K3XX_EDMA_CH5_CSR,
+ S32K3XX_EDMA_CH6_CSR,
+ S32K3XX_EDMA_CH7_CSR,
+ S32K3XX_EDMA_CH8_CSR,
+ S32K3XX_EDMA_CH9_CSR,
+ S32K3XX_EDMA_CH10_CSR,
+ S32K3XX_EDMA_CH11_CSR,
+ S32K3XX_EDMA_CH12_CSR,
+ S32K3XX_EDMA_CH13_CSR,
+ S32K3XX_EDMA_CH14_CSR,
+ S32K3XX_EDMA_CH15_CSR,
+ S32K3XX_EDMA_CH16_CSR,
+ S32K3XX_EDMA_CH17_CSR,
+ S32K3XX_EDMA_CH18_CSR,
+ S32K3XX_EDMA_CH19_CSR,
+ S32K3XX_EDMA_CH20_CSR,
+ S32K3XX_EDMA_CH21_CSR,
+ S32K3XX_EDMA_CH22_CSR,
+ S32K3XX_EDMA_CH23_CSR,
+ S32K3XX_EDMA_CH24_CSR,
+ S32K3XX_EDMA_CH25_CSR,
+ S32K3XX_EDMA_CH26_CSR,
+ S32K3XX_EDMA_CH27_CSR,
+ S32K3XX_EDMA_CH28_CSR,
+ S32K3XX_EDMA_CH29_CSR,
+ S32K3XX_EDMA_CH30_CSR,
+ S32K3XX_EDMA_CH31_CSR
+};
+
+/* eDMA Register Bitfield Definitions ***************************************/
+
+/* Management Page Control Register (CSR) */
+
+ /* Bit 0: Reserved */
+#define EDMA_CSR_EDBG (1 << 1) /* Bit 1: Enable Debug (EDBG) */
+#define EDMA_CSR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration (ERCA) */
+ /* Bit 3: Reserved */
+#define EDMA_CSR_HAE (1 << 4) /* Bit 4: Halt After Error (HAE) */
+#define EDMA_CSR_HALT (1 << 5) /* Bit 5: Halt DMA Operations (HALT) */
+#define EDMA_CSR_GCLC (1 << 6) /* Bit 6: Global Channel Linking Control (GCLC) */
+#define EDMA_CSR_GMRC (1 << 7) /* Bit 7: Global Master ID Replication Control (GMRC) */
+#define EDMA_CSR_ECX (1 << 8) /* Bit 8: Cancel Transfer With Error (ECX) */
+#define EDMA_CSR_CX (1 << 9) /* Bit 9: Cancel Transfer (CX) */
+ /* Bits 10-23: Reserved */
+#define EDMA_CSR_ACTIVE_ID_SHIFT (24) /* Bits 24-28: Active Channel ID (ACTIVE_ID) */
+#define EDMA_CSR_ACTIVE_ID_MASK (0x1f << EDMA_CSR_ACTIVE_ID_SHIFT)
+ /* Bits 29-30: Reserved */
+#define EDMA_CSR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status (ACTIVE) */
+
+/* Management Page Error Status Register (ES) */
+
+#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
+#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
+#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
+#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
+#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
+#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
+#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
+#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
+#define EDMA_ES_ECX (1 << 8) /* Bit 8: Transfer Canceled (ECX) */
+#define EDMA_ES_UCE (1 << 9) /* Bit 9: Uncorrectable TCD Error During Channel Execution (UCE) */
+ /* Bits 10-23: Reserved */
+#define EDMA_ES_ERRCHN_SHIFT (8) /* Bits 24-28: Error Channel Number or Canceled Channel Number (ERRCHN) */
+#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT)
+ /* Bits 29-30: Reserved */
+#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status fields (VALID) */
+
+/* Management Page Interrupt Request Status Register (INT) */
+
+#define EDMA_INT(n) (1 << (n)) /* Bit n: Interrupt Request Status (INT) */
+
+/* Management Page Hardware Request Status Register (HRS) */
+
+#define EDMA_HRS(n) (1 << (n)) /* Bit n: Hardware Request Status (HRS) */
+
+/* Channel n Arbitration Group Register (CHn_GRPRI) */
+
+#define EDMA_CH_GRPRI_SHIFT (0) /* Bits 0-4: Arbitration Group For Channel n (GRPRI) */
+#define EDMA_CH_GRPRI_MASK (0x1f << EDMA_CH_GRPRI_SHIFT)
+ /* Bits 5-31: Reserved */
+
+/* eDMA Transfer Control Descriptor (TCD) Bitfield Definitions **************/
+
+/* Channel n Control and Status Register (CHn_CSR) */
+
+#define EDMA_CH_CSR_ERQ (1 << 0) /* Bit 0: Enable DMA Request (ERQ) */
+#define EDMA_CH_CSR_EARQ (1 << 1) /* Bit 1: Enable Asynchronous DMA Request in Stop Mode for Channel (EARQ) */
+#define EDMA_CH_CSR_EEI (1 << 2) /* Bit 2: Enable Error Interrupt (EEI) */
+#define EDMA_CH_CSR_EBW (1 << 3) /* Bit 3: Enable Buffered Writes (EBW) */
+ /* Bit 4-29: Reserved */
+#define EDMA_CH_CSR_DONE (1 << 30) /* Bit 30: Channel Done (DONE) */
+#define EDMA_CH_CSR_ACTIVE (1 << 31) /* Bit 31: CHannel Active (ACTIVE) */
+
+/* Channel n Error Status Register (CHn_ES) */
+
+#define EDMA_CH_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
+#define EDMA_CH_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
+#define EDMA_CH_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
+#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
+#define EDMA_CH_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
+#define EDMA_CH_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
+#define EDMA_CH_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
+#define EDMA_CH_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
+ /* Bit 8-30: Reserved */
+#define EDMA_CH_ES_ERR (1 << 31) /* Bit 31: Error in this channel (ERR) */
+
+/* Channel n Interrupt Status Register (CHn_INT) */
+
+#define EDMA_CH_INT (1 << 0) /* Bit 0: Interrupt Request (INT) */
+ /* Bits 1-31: Reserved */
+
+/* Channel n System Bus Register (CHn_SBR) */
+
+#define EDMA_CH_SBR_MID_SHIFT (0) /* Bits 0-3: Master ID (MID) */
+#define EDMA_CH_SBR_MID_MASK (0x0f << EDMA_CH_SBR_MID_SHIFT)
+ /* Bits 4-14: Reserved */
+#define EDMA_CH_SBR_PAL (1 << 15) /* Bit 15: Privileged Access Level (PAL) */
+#define EDMA_CH_SBR_EMI (1 << 16) /* Bit 16: Enable Master ID Replication (EMI) */
+#define EDMA_CH_SBR_ATTR_SHIFT (17) /* Bits 17-19: Attribute Output (ATTR) */
+#define EDMA_CH_SBR_ATTR_MASK (0x07 << EDMA_CH_SBR_ATTR_SHIFT)
+ /* Bits 20-31: Reserved */
+
+/* Channel n Priority Register (CHn_PRI) */
+
+#define EDMA_CH_PRI_APL_SHIFT (0) /* Bits 0-2: Arbitration Priority Level (APL) */
+#define EDMA_CH_PRI_APL_MASK (0x07 << EDMA_CH_PRI_APL_SHIFT)
+ /* Bits 3-29: Reserved */
+#define EDMA_CH_PRI_DPA (1 << 30) /* Bit 30: Disable Preempt Ability (DPA) */
+#define EDMA_CH_PRI_ECP (1 << 31) /* Bit 31: Enable Channel Preemption (ECP) */
+
+/* TCDn Source Address Register (TCDn_SADDR) */
+
+#define EDMA_TCD_SADDR_SHIFT (0) /* Bits 0-31: Source Address (SADDR) */
+#define EDMA_TCD_SADDR_MASK (0xffffffff << EDMA_TCD_SADDR_SHIFT)
+
+/* TCDn Signed Source Address Offset Register (TCDn_SOFF) */
+
+#define EDMA_TCD_SOFF_SHIFT (0) /* Bits 0-31: Source Address Signed Offset (SOFF) */
+#define EDMA_TCD_SOFF_MASK (0xffffffff << EDMA_TCD_SOFF_SHIFT)
+
+/* TCDn Transfer Attributes (TCDn_ATTR) */
+
+#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */
+#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT)
+#define EDMA_TCD_ATTR_DSIZE(n) ((n << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK)
+#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */
+#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT)
+#define EDMA_TCD_ATTR_DMOD(n) ((n << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK)
+#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */
+#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT)
+#define EDMA_TCD_ATTR_SSIZE(n) ((n << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK)
+# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
+# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
+# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
+# define EDMA_TCD_ATTR_SSIZE_64BIT (0x03 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */
+# define EDMA_TCD_ATTR_SSIZE_16BYTE (0x04 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */
+# define EDMA_TCD_ATTR_SSIZE_32BYTE (0x05 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte */
+# define EDMA_TCD_ATTR_SSIZE_64BYTE (0x06 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-byte */
+
+#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */
+#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT)
+#define EDMA_TCD_ATTR_SMOD(n) ((n << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK)
+
+/* TCDn Transfer Size (TCDn_NBYTES) */
+
+#define EDMA_TCD_NBYTES_SHIFT (0) /* Bits 0-29: Number of Bytes to Transfer per Service Request (NBYTES) */
+#define EDMA_TCD_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_SHIFT)
+#define EDMA_TCD_NBYTES_MASK_MLOFF (0x03ff << EDMA_TCD_NBYTES_SHIFT)
+#define EDMA_TCD_NBYTES_MLOFF_SHIFT (10) /* Bits 10-29: Minor Loop Offset (MLOFF) */
+#define EDMA_TCD_NBYTES_MLOFF_MASK (0x0fffff << EDMA_TCD_NBYTES_MLOFF_SHIFT)
+#define EDMA_TCD_NBYTES_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset Enable (DMLOE) */
+#define EDMA_TCD_NBYTES_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable (SMLOE) */
+
+/* TCDn Last Source Address Adjustment / Store DADDR Address Register
+ * (TCDn_SLAST_SDA)
+ */
+
+#define EDMA_TCD_SLAST_SDA_SHIFT (0) /* Bits 0-31: Last Source Address Adjustment / Store DADDR Address (SLAST_SDA) */
+#define EDMA_TCD_SLAST_SDA_MASK (0xffffffff << EDMA_TCD_SLAST_SDA_SHIFT)
+
+/* TCDn Destination Address Register (TCDn_DADDR) */
+
+#define EDMA_TCD_DADDR_SHIFT (0) /* Bits 0-31: Destination Address (DADDR) */
+#define EDMA_TCD_DADDR_MASK (0xffffffff << EDMA_TCD_DADDR_SHIFT)
+
+/* TCDn Signed Destination Address Offset Register (TCDn_DOFF) */
+
+#define EDMA_TCD_DOFF_SHIFT (0) /* Bits 0-15: Destination Address Signed Offset (DOFF) */
+#define EDMA_TCD_DOFF_MASK (0xffff << EDMA_TCD_DOFF_SHIFT)
+
+/* TCDn Current Major Loop Count Register (TCDn_CITER) */
+
+#define EDMA_TCD_CITER_SHIFT (0) /* Bits 0-14: Current Major Iteration Count (CITER) */
+#define EDMA_TCD_CITER_MASK (0x7fff << EDMA_TCD_CITER_SHIFT)
+#define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT)
+#define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */
+#define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT)
+#define EDMA_TCD_CITER_LINKCH(n) ((n << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT)
Review Comment:
```suggestion
#define EDMA_TCD_CITER_LINKCH(n) (((n) << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT)
```
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h:
##########
@@ -0,0 +1,1433 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define S32K3XX_EDMA_NCHANNELS 32
+
+/* eDMA Register Offsets ****************************************************/
+
+#define S32K3XX_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */
+#define S32K3XX_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */
+#define S32K3XX_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */
+#define S32K3XX_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */
+
+#define S32K3XX_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */
+
+/* eDMA Register Addresses **************************************************/
+
+#define S32K3XX_EDMA_CSR (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CSR_OFFSET)
+#define S32K3XX_EDMA_ES (S32K3XX_EDMA_BASE + S32K3XX_EDMA_ES_OFFSET)
+#define S32K3XX_EDMA_INT (S32K3XX_EDMA_BASE + S32K3XX_EDMA_INT_OFFSET)
+#define S32K3XX_EDMA_HRS (S32K3XX_EDMA_BASE + S32K3XX_EDMA_HRS_OFFSET)
+#define S32K3XX_EDMA_CH_GRPRI(n) (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CH_GRPRI_OFFSET(n))
+
+/* eDMA Transfer Control Descriptor (TCD) Register Offsets ******************/
+
+#define S32K3XX_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH0_CSR_OFFSET (0x000000) /* Channel 0 Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH0_ES_OFFSET (0x000004) /* Channel 0 Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH0_INT_OFFSET (0x000008) /* Channel 0 Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH0_SBR_OFFSET (0x00000c) /* Channel 0 System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH0_PRI_OFFSET (0x000010) /* Channel 0 Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD0_SADDR_OFFSET (0x000020) /* TCD0 Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD0_SOFF_OFFSET (0x000024) /* TCD0 Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD0_ATTR_OFFSET (0x000026) /* TCD0 Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD0_NBYTES_OFFSET (0x000028) /* TCD0 Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET (0x00002c) /* TCD0 Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD0_DADDR_OFFSET (0x000030) /* TCD0 Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD0_DOFF_OFFSET (0x000034) /* TCD0 Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD0_CITER_OFFSET (0x000036) /* TCD0 Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET (0x000038) /* TCD0 Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD0_CSR_OFFSET (0x00003c) /* TCD0 Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD0_BITER_OFFSET (0x00003e) /* TCD0 Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH1_CSR_OFFSET (0x004000) /* Channel 1 Control and Status Register (CH1_CSR) */
+#define S32K3XX_EDMA_CH1_ES_OFFSET (0x004004) /* Channel 1 Error Status Register (CH1_ES) */
+#define S32K3XX_EDMA_CH1_INT_OFFSET (0x004008) /* Channel 1 Interrupt Status Register (CH1_INT) */
+#define S32K3XX_EDMA_CH1_SBR_OFFSET (0x00400c) /* Channel 1 System Bus Register (CH1_SBR) */
+#define S32K3XX_EDMA_CH1_PRI_OFFSET (0x004010) /* Channel 1 Priority Register (CH1_PRI) */
+#define S32K3XX_EDMA_TCD1_SADDR_OFFSET (0x004020) /* TCD1 Source Address Register (TCD1_SADDR) */
+#define S32K3XX_EDMA_TCD1_SOFF_OFFSET (0x004024) /* TCD1 Signed Source Address Offset Register (TCD1_SOFF) */
+#define S32K3XX_EDMA_TCD1_ATTR_OFFSET (0x004026) /* TCD1 Transfer Attributes (TCD1_ATTR) */
+#define S32K3XX_EDMA_TCD1_NBYTES_OFFSET (0x004028) /* TCD1 Transfer Size (TCD1_NBYTES) */
+#define S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET (0x00402c) /* TCD1 Last Source Address Adjustment / Store DADDR Address Register (TCD1_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD1_DADDR_OFFSET (0x004030) /* TCD1 Destination Address Register (TCD1_DADDR) */
+#define S32K3XX_EDMA_TCD1_DOFF_OFFSET (0x004034) /* TCD1 Signed Destination Address Offset Register (TCD1_DOFF) */
+#define S32K3XX_EDMA_TCD1_CITER_OFFSET (0x004036) /* TCD1 Current Major Loop Count Register (TCD1_CITER) */
+#define S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET (0x004038) /* TCD1 Last Destination Address Adjustment / Scatter Gather Address Register (TCD1_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD1_CSR_OFFSET (0x00403c) /* TCD1 Control and Status Register (TCD1_CSR) */
+#define S32K3XX_EDMA_TCD1_BITER_OFFSET (0x00403e) /* TCD1 Beginning Major Loop Count Register (TCD1_BITER) */
+
+#define S32K3XX_EDMA_CH2_CSR_OFFSET (0x008000) /* Channel 2 Control and Status Register (CH2_CSR) */
+#define S32K3XX_EDMA_CH2_ES_OFFSET (0x008004) /* Channel 2 Error Status Register (CH2_ES) */
+#define S32K3XX_EDMA_CH2_INT_OFFSET (0x008008) /* Channel 2 Interrupt Status Register (CH2_INT) */
+#define S32K3XX_EDMA_CH2_SBR_OFFSET (0x00800c) /* Channel 2 System Bus Register (CH2_SBR) */
+#define S32K3XX_EDMA_CH2_PRI_OFFSET (0x008010) /* Channel 2 Priority Register (CH2_PRI) */
+#define S32K3XX_EDMA_TCD2_SADDR_OFFSET (0x008020) /* TCD2 Source Address Register (TCD2_SADDR) */
+#define S32K3XX_EDMA_TCD2_SOFF_OFFSET (0x008024) /* TCD2 Signed Source Address Offset Register (TCD2_SOFF) */
+#define S32K3XX_EDMA_TCD2_ATTR_OFFSET (0x008026) /* TCD2 Transfer Attributes (TCD2_ATTR) */
+#define S32K3XX_EDMA_TCD2_NBYTES_OFFSET (0x008028) /* TCD2 Transfer Size (TCD2_NBYTES) */
+#define S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET (0x00802c) /* TCD2 Last Source Address Adjustment / Store DADDR Address Register (TCD2_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD2_DADDR_OFFSET (0x008030) /* TCD2 Destination Address Register (TCD2_DADDR) */
+#define S32K3XX_EDMA_TCD2_DOFF_OFFSET (0x008034) /* TCD2 Signed Destination Address Offset Register (TCD2_DOFF) */
+#define S32K3XX_EDMA_TCD2_CITER_OFFSET (0x008036) /* TCD2 Current Major Loop Count Register (TCD2_CITER) */
+#define S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET (0x008038) /* TCD2 Last Destination Address Adjustment / Scatter Gather Address Register (TCD2_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD2_CSR_OFFSET (0x00803c) /* TCD2 Control and Status Register (TCD2_CSR) */
+#define S32K3XX_EDMA_TCD2_BITER_OFFSET (0x00803e) /* TCD2 Beginning Major Loop Count Register (TCD2_BITER) */
+
+#define S32K3XX_EDMA_CH3_CSR_OFFSET (0x00c000) /* Channel 3 Control and Status Register (CH3_CSR) */
+#define S32K3XX_EDMA_CH3_ES_OFFSET (0x00c004) /* Channel 3 Error Status Register (CH3_ES) */
+#define S32K3XX_EDMA_CH3_INT_OFFSET (0x00c008) /* Channel 3 Interrupt Status Register (CH3_INT) */
+#define S32K3XX_EDMA_CH3_SBR_OFFSET (0x00c00c) /* Channel 3 System Bus Register (CH3_SBR) */
+#define S32K3XX_EDMA_CH3_PRI_OFFSET (0x00c010) /* Channel 3 Priority Register (CH3_PRI) */
+#define S32K3XX_EDMA_TCD3_SADDR_OFFSET (0x00c020) /* TCD3 Source Address Register (TCD3_SADDR) */
+#define S32K3XX_EDMA_TCD3_SOFF_OFFSET (0x00c024) /* TCD3 Signed Source Address Offset Register (TCD3_SOFF) */
+#define S32K3XX_EDMA_TCD3_ATTR_OFFSET (0x00c026) /* TCD3 Transfer Attributes (TCD3_ATTR) */
+#define S32K3XX_EDMA_TCD3_NBYTES_OFFSET (0x00c028) /* TCD3 Transfer Size (TCD3_NBYTES) */
+#define S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET (0x00c02c) /* TCD3 Last Source Address Adjustment / Store DADDR Address Register (TCD3_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD3_DADDR_OFFSET (0x00c030) /* TCD3 Destination Address Register (TCD3_DADDR) */
+#define S32K3XX_EDMA_TCD3_DOFF_OFFSET (0x00c034) /* TCD3 Signed Destination Address Offset Register (TCD3_DOFF) */
+#define S32K3XX_EDMA_TCD3_CITER_OFFSET (0x00c036) /* TCD3 Current Major Loop Count Register (TCD3_CITER) */
+#define S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET (0x00c038) /* TCD3 Last Destination Address Adjustment / Scatter Gather Address Register (TCD3_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD3_CSR_OFFSET (0x00c03c) /* TCD3 Control and Status Register (TCD3_CSR) */
+#define S32K3XX_EDMA_TCD3_BITER_OFFSET (0x00c03e) /* TCD3 Beginning Major Loop Count Register (TCD3_BITER) */
+
+#define S32K3XX_EDMA_CH4_CSR_OFFSET (0x010000) /* Channel 4 Control and Status Register (CH4_CSR) */
+#define S32K3XX_EDMA_CH4_ES_OFFSET (0x010004) /* Channel 4 Error Status Register (CH4_ES) */
+#define S32K3XX_EDMA_CH4_INT_OFFSET (0x010008) /* Channel 4 Interrupt Status Register (CH4_INT) */
+#define S32K3XX_EDMA_CH4_SBR_OFFSET (0x01000c) /* Channel 4 System Bus Register (CH4_SBR) */
+#define S32K3XX_EDMA_CH4_PRI_OFFSET (0x010010) /* Channel 4 Priority Register (CH4_PRI) */
+#define S32K3XX_EDMA_TCD4_SADDR_OFFSET (0x010020) /* TCD4 Source Address Register (TCD4_SADDR) */
+#define S32K3XX_EDMA_TCD4_SOFF_OFFSET (0x010024) /* TCD4 Signed Source Address Offset Register (TCD4_SOFF) */
+#define S32K3XX_EDMA_TCD4_ATTR_OFFSET (0x010026) /* TCD4 Transfer Attributes (TCD4_ATTR) */
+#define S32K3XX_EDMA_TCD4_NBYTES_OFFSET (0x010028) /* TCD4 Transfer Size (TCD4_NBYTES) */
+#define S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET (0x01002c) /* TCD4 Last Source Address Adjustment / Store DADDR Address Register (TCD4_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD4_DADDR_OFFSET (0x010030) /* TCD4 Destination Address Register (TCD4_DADDR) */
+#define S32K3XX_EDMA_TCD4_DOFF_OFFSET (0x010034) /* TCD4 Signed Destination Address Offset Register (TCD4_DOFF) */
+#define S32K3XX_EDMA_TCD4_CITER_OFFSET (0x010036) /* TCD4 Current Major Loop Count Register (TCD4_CITER) */
+#define S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET (0x010038) /* TCD4 Last Destination Address Adjustment / Scatter Gather Address Register (TCD4_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD4_CSR_OFFSET (0x01003c) /* TCD4 Control and Status Register (TCD4_CSR) */
+#define S32K3XX_EDMA_TCD4_BITER_OFFSET (0x01003e) /* TCD4 Beginning Major Loop Count Register (TCD4_BITER) */
+
+#define S32K3XX_EDMA_CH5_CSR_OFFSET (0x014000) /* Channel 5 Control and Status Register (CH5_CSR) */
+#define S32K3XX_EDMA_CH5_ES_OFFSET (0x014004) /* Channel 5 Error Status Register (CH5_ES) */
+#define S32K3XX_EDMA_CH5_INT_OFFSET (0x014008) /* Channel 5 Interrupt Status Register (CH5_INT) */
+#define S32K3XX_EDMA_CH5_SBR_OFFSET (0x01400c) /* Channel 5 System Bus Register (CH5_SBR) */
+#define S32K3XX_EDMA_CH5_PRI_OFFSET (0x014010) /* Channel 5 Priority Register (CH5_PRI) */
+#define S32K3XX_EDMA_TCD5_SADDR_OFFSET (0x014020) /* TCD5 Source Address Register (TCD5_SADDR) */
+#define S32K3XX_EDMA_TCD5_SOFF_OFFSET (0x014024) /* TCD5 Signed Source Address Offset Register (TCD5_SOFF) */
+#define S32K3XX_EDMA_TCD5_ATTR_OFFSET (0x014026) /* TCD5 Transfer Attributes (TCD5_ATTR) */
+#define S32K3XX_EDMA_TCD5_NBYTES_OFFSET (0x014028) /* TCD5 Transfer Size (TCD5_NBYTES) */
+#define S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET (0x01402c) /* TCD5 Last Source Address Adjustment / Store DADDR Address Register (TCD5_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD5_DADDR_OFFSET (0x014030) /* TCD5 Destination Address Register (TCD5_DADDR) */
+#define S32K3XX_EDMA_TCD5_DOFF_OFFSET (0x014034) /* TCD5 Signed Destination Address Offset Register (TCD5_DOFF) */
+#define S32K3XX_EDMA_TCD5_CITER_OFFSET (0x014036) /* TCD5 Current Major Loop Count Register (TCD5_CITER) */
+#define S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET (0x014038) /* TCD5 Last Destination Address Adjustment / Scatter Gather Address Register (TCD5_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD5_CSR_OFFSET (0x01403c) /* TCD5 Control and Status Register (TCD5_CSR) */
+#define S32K3XX_EDMA_TCD5_BITER_OFFSET (0x01403e) /* TCD5 Beginning Major Loop Count Register (TCD5_BITER) */
+
+#define S32K3XX_EDMA_CH6_CSR_OFFSET (0x018000) /* Channel 6 Control and Status Register (CH6_CSR) */
+#define S32K3XX_EDMA_CH6_ES_OFFSET (0x018004) /* Channel 6 Error Status Register (CH6_ES) */
+#define S32K3XX_EDMA_CH6_INT_OFFSET (0x018008) /* Channel 6 Interrupt Status Register (CH6_INT) */
+#define S32K3XX_EDMA_CH6_SBR_OFFSET (0x01800c) /* Channel 6 System Bus Register (CH6_SBR) */
+#define S32K3XX_EDMA_CH6_PRI_OFFSET (0x018010) /* Channel 6 Priority Register (CH6_PRI) */
+#define S32K3XX_EDMA_TCD6_SADDR_OFFSET (0x018020) /* TCD6 Source Address Register (TCD6_SADDR) */
+#define S32K3XX_EDMA_TCD6_SOFF_OFFSET (0x018024) /* TCD6 Signed Source Address Offset Register (TCD6_SOFF) */
+#define S32K3XX_EDMA_TCD6_ATTR_OFFSET (0x018026) /* TCD6 Transfer Attributes (TCD6_ATTR) */
+#define S32K3XX_EDMA_TCD6_NBYTES_OFFSET (0x018028) /* TCD6 Transfer Size (TCD6_NBYTES) */
+#define S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET (0x01802c) /* TCD6 Last Source Address Adjustment / Store DADDR Address Register (TCD6_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD6_DADDR_OFFSET (0x018030) /* TCD6 Destination Address Register (TCD6_DADDR) */
+#define S32K3XX_EDMA_TCD6_DOFF_OFFSET (0x018034) /* TCD6 Signed Destination Address Offset Register (TCD6_DOFF) */
+#define S32K3XX_EDMA_TCD6_CITER_OFFSET (0x018036) /* TCD6 Current Major Loop Count Register (TCD6_CITER) */
+#define S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET (0x018038) /* TCD6 Last Destination Address Adjustment / Scatter Gather Address Register (TCD6_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD6_CSR_OFFSET (0x01803c) /* TCD6 Control and Status Register (TCD6_CSR) */
+#define S32K3XX_EDMA_TCD6_BITER_OFFSET (0x01803e) /* TCD6 Beginning Major Loop Count Register (TCD6_BITER) */
+
+#define S32K3XX_EDMA_CH7_CSR_OFFSET (0x01c000) /* Channel 7 Control and Status Register (CH7_CSR) */
+#define S32K3XX_EDMA_CH7_ES_OFFSET (0x01c004) /* Channel 7 Error Status Register (CH7_ES) */
+#define S32K3XX_EDMA_CH7_INT_OFFSET (0x01c008) /* Channel 7 Interrupt Status Register (CH7_INT) */
+#define S32K3XX_EDMA_CH7_SBR_OFFSET (0x01c00c) /* Channel 7 System Bus Register (CH7_SBR) */
+#define S32K3XX_EDMA_CH7_PRI_OFFSET (0x01c010) /* Channel 7 Priority Register (CH7_PRI) */
+#define S32K3XX_EDMA_TCD7_SADDR_OFFSET (0x01c020) /* TCD7 Source Address Register (TCD7_SADDR) */
+#define S32K3XX_EDMA_TCD7_SOFF_OFFSET (0x01c024) /* TCD7 Signed Source Address Offset Register (TCD7_SOFF) */
+#define S32K3XX_EDMA_TCD7_ATTR_OFFSET (0x01c026) /* TCD7 Transfer Attributes (TCD7_ATTR) */
+#define S32K3XX_EDMA_TCD7_NBYTES_OFFSET (0x01c028) /* TCD7 Transfer Size (TCD7_NBYTES) */
+#define S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET (0x01c02c) /* TCD7 Last Source Address Adjustment / Store DADDR Address Register (TCD7_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD7_DADDR_OFFSET (0x01c030) /* TCD7 Destination Address Register (TCD7_DADDR) */
+#define S32K3XX_EDMA_TCD7_DOFF_OFFSET (0x01c034) /* TCD7 Signed Destination Address Offset Register (TCD7_DOFF) */
+#define S32K3XX_EDMA_TCD7_CITER_OFFSET (0x01c036) /* TCD7 Current Major Loop Count Register (TCD7_CITER) */
+#define S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET (0x01c038) /* TCD7 Last Destination Address Adjustment / Scatter Gather Address Register (TCD7_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD7_CSR_OFFSET (0x01c03c) /* TCD7 Control and Status Register (TCD7_CSR) */
+#define S32K3XX_EDMA_TCD7_BITER_OFFSET (0x01c03e) /* TCD7 Beginning Major Loop Count Register (TCD7_BITER) */
+
+#define S32K3XX_EDMA_CH8_CSR_OFFSET (0x020000) /* Channel 8 Control and Status Register (CH8_CSR) */
+#define S32K3XX_EDMA_CH8_ES_OFFSET (0x020004) /* Channel 8 Error Status Register (CH8_ES) */
+#define S32K3XX_EDMA_CH8_INT_OFFSET (0x020008) /* Channel 8 Interrupt Status Register (CH8_INT) */
+#define S32K3XX_EDMA_CH8_SBR_OFFSET (0x02000c) /* Channel 8 System Bus Register (CH8_SBR) */
+#define S32K3XX_EDMA_CH8_PRI_OFFSET (0x020010) /* Channel 8 Priority Register (CH8_PRI) */
+#define S32K3XX_EDMA_TCD8_SADDR_OFFSET (0x020020) /* TCD8 Source Address Register (TCD8_SADDR) */
+#define S32K3XX_EDMA_TCD8_SOFF_OFFSET (0x020024) /* TCD8 Signed Source Address Offset Register (TCD8_SOFF) */
+#define S32K3XX_EDMA_TCD8_ATTR_OFFSET (0x020026) /* TCD8 Transfer Attributes (TCD8_ATTR) */
+#define S32K3XX_EDMA_TCD8_NBYTES_OFFSET (0x020028) /* TCD8 Transfer Size (TCD8_NBYTES) */
+#define S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET (0x02002c) /* TCD8 Last Source Address Adjustment / Store DADDR Address Register (TCD8_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD8_DADDR_OFFSET (0x020030) /* TCD8 Destination Address Register (TCD8_DADDR) */
+#define S32K3XX_EDMA_TCD8_DOFF_OFFSET (0x020034) /* TCD8 Signed Destination Address Offset Register (TCD8_DOFF) */
+#define S32K3XX_EDMA_TCD8_CITER_OFFSET (0x020036) /* TCD8 Current Major Loop Count Register (TCD8_CITER) */
+#define S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET (0x020038) /* TCD8 Last Destination Address Adjustment / Scatter Gather Address Register (TCD8_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD8_CSR_OFFSET (0x02003c) /* TCD8 Control and Status Register (TCD8_CSR) */
+#define S32K3XX_EDMA_TCD8_BITER_OFFSET (0x02003e) /* TCD8 Beginning Major Loop Count Register (TCD8_BITER) */
+
+#define S32K3XX_EDMA_CH9_CSR_OFFSET (0x024000) /* Channel 9 Control and Status Register (CH9_CSR) */
+#define S32K3XX_EDMA_CH9_ES_OFFSET (0x024004) /* Channel 9 Error Status Register (CH9_ES) */
+#define S32K3XX_EDMA_CH9_INT_OFFSET (0x024008) /* Channel 9 Interrupt Status Register (CH9_INT) */
+#define S32K3XX_EDMA_CH9_SBR_OFFSET (0x02400c) /* Channel 9 System Bus Register (CH9_SBR) */
+#define S32K3XX_EDMA_CH9_PRI_OFFSET (0x024010) /* Channel 9 Priority Register (CH9_PRI) */
+#define S32K3XX_EDMA_TCD9_SADDR_OFFSET (0x024020) /* TCD9 Source Address Register (TCD9_SADDR) */
+#define S32K3XX_EDMA_TCD9_SOFF_OFFSET (0x024024) /* TCD9 Signed Source Address Offset Register (TCD9_SOFF) */
+#define S32K3XX_EDMA_TCD9_ATTR_OFFSET (0x024026) /* TCD9 Transfer Attributes (TCD9_ATTR) */
+#define S32K3XX_EDMA_TCD9_NBYTES_OFFSET (0x024028) /* TCD9 Transfer Size (TCD9_NBYTES) */
+#define S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET (0x02402c) /* TCD9 Last Source Address Adjustment / Store DADDR Address Register (TCD9_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD9_DADDR_OFFSET (0x024030) /* TCD9 Destination Address Register (TCD9_DADDR) */
+#define S32K3XX_EDMA_TCD9_DOFF_OFFSET (0x024034) /* TCD9 Signed Destination Address Offset Register (TCD9_DOFF) */
+#define S32K3XX_EDMA_TCD9_CITER_OFFSET (0x024036) /* TCD9 Current Major Loop Count Register (TCD9_CITER) */
+#define S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET (0x024038) /* TCD9 Last Destination Address Adjustment / Scatter Gather Address Register (TCD9_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD9_CSR_OFFSET (0x02403c) /* TCD9 Control and Status Register (TCD9_CSR) */
+#define S32K3XX_EDMA_TCD9_BITER_OFFSET (0x02403e) /* TCD9 Beginning Major Loop Count Register (TCD9_BITER) */
+
+#define S32K3XX_EDMA_CH10_CSR_OFFSET (0x028000) /* Channel 10 Control and Status Register (CH10_CSR) */
+#define S32K3XX_EDMA_CH10_ES_OFFSET (0x028004) /* Channel 10 Error Status Register (CH10_ES) */
+#define S32K3XX_EDMA_CH10_INT_OFFSET (0x028008) /* Channel 10 Interrupt Status Register (CH10_INT) */
+#define S32K3XX_EDMA_CH10_SBR_OFFSET (0x02800c) /* Channel 10 System Bus Register (CH10_SBR) */
+#define S32K3XX_EDMA_CH10_PRI_OFFSET (0x028010) /* Channel 10 Priority Register (CH10_PRI) */
+#define S32K3XX_EDMA_TCD10_SADDR_OFFSET (0x028020) /* TCD10 Source Address Register (TCD10_SADDR) */
+#define S32K3XX_EDMA_TCD10_SOFF_OFFSET (0x028024) /* TCD10 Signed Source Address Offset Register (TCD10_SOFF) */
+#define S32K3XX_EDMA_TCD10_ATTR_OFFSET (0x028026) /* TCD10 Transfer Attributes (TCD10_ATTR) */
+#define S32K3XX_EDMA_TCD10_NBYTES_OFFSET (0x028028) /* TCD10 Transfer Size (TCD10_NBYTES) */
+#define S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET (0x02802c) /* TCD10 Last Source Address Adjustment / Store DADDR Address Register (TCD10_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD10_DADDR_OFFSET (0x028030) /* TCD10 Destination Address Register (TCD10_DADDR) */
+#define S32K3XX_EDMA_TCD10_DOFF_OFFSET (0x028034) /* TCD10 Signed Destination Address Offset Register (TCD10_DOFF) */
+#define S32K3XX_EDMA_TCD10_CITER_OFFSET (0x028036) /* TCD10 Current Major Loop Count Register (TCD10_CITER) */
+#define S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET (0x028038) /* TCD10 Last Destination Address Adjustment / Scatter Gather Address Register (TCD10_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD10_CSR_OFFSET (0x02803c) /* TCD10 Control and Status Register (TCD10_CSR) */
+#define S32K3XX_EDMA_TCD10_BITER_OFFSET (0x02803e) /* TCD10 Beginning Major Loop Count Register (TCD10_BITER) */
+#define S32K3XX_EDMA_CH11_CSR_OFFSET (0x02c000) /* Channel 11 Control and Status Register (CH11_CSR) */
+#define S32K3XX_EDMA_CH11_ES_OFFSET (0x02c004) /* Channel 11 Error Status Register (CH11_ES) */
+#define S32K3XX_EDMA_CH11_INT_OFFSET (0x02c008) /* Channel 11 Interrupt Status Register (CH11_INT) */
+#define S32K3XX_EDMA_CH11_SBR_OFFSET (0x02c00c) /* Channel 11 System Bus Register (CH11_SBR) */
+#define S32K3XX_EDMA_CH11_PRI_OFFSET (0x02c010) /* Channel 11 Priority Register (CH11_PRI) */
+#define S32K3XX_EDMA_TCD11_SADDR_OFFSET (0x02c020) /* TCD11 Source Address Register (TCD11_SADDR) */
+#define S32K3XX_EDMA_TCD11_SOFF_OFFSET (0x02c024) /* TCD11 Signed Source Address Offset Register (TCD11_SOFF) */
+#define S32K3XX_EDMA_TCD11_ATTR_OFFSET (0x02c026) /* TCD11 Transfer Attributes (TCD11_ATTR) */
+#define S32K3XX_EDMA_TCD11_NBYTES_OFFSET (0x02c028) /* TCD11 Transfer Size (TCD11_NBYTES) */
+#define S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET (0x02c02c) /* TCD11 Last Source Address Adjustment / Store DADDR Address Register (TCD11_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD11_DADDR_OFFSET (0x02c030) /* TCD11 Destination Address Register (TCD11_DADDR) */
+#define S32K3XX_EDMA_TCD11_DOFF_OFFSET (0x02c034) /* TCD11 Signed Destination Address Offset Register (TCD11_DOFF) */
+#define S32K3XX_EDMA_TCD11_CITER_OFFSET (0x02c036) /* TCD11 Current Major Loop Count Register (TCD11_CITER) */
+#define S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET (0x02c038) /* TCD11 Last Destination Address Adjustment / Scatter Gather Address Register (TCD11_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD11_CSR_OFFSET (0x02c03c) /* TCD11 Control and Status Register (TCD11_CSR) */
+#define S32K3XX_EDMA_TCD11_BITER_OFFSET (0x02c03e) /* TCD11 Beginning Major Loop Count Register (TCD11_BITER) */
+
+#define S32K3XX_EDMA_CH12_CSR_OFFSET (0x200000) /* Channel 12 Control and Status Register (CH12_CSR) */
+#define S32K3XX_EDMA_CH12_ES_OFFSET (0x200004) /* Channel 12 Error Status Register (CH12_ES) */
+#define S32K3XX_EDMA_CH12_INT_OFFSET (0x200008) /* Channel 12 Interrupt Status Register (CH12_INT) */
+#define S32K3XX_EDMA_CH12_SBR_OFFSET (0x20000c) /* Channel 12 System Bus Register (CH12_SBR) */
+#define S32K3XX_EDMA_CH12_PRI_OFFSET (0x200010) /* Channel 12 Priority Register (CH12_PRI) */
+#define S32K3XX_EDMA_TCD12_SADDR_OFFSET (0x200020) /* TCD12 Source Address Register (TCD12_SADDR) */
+#define S32K3XX_EDMA_TCD12_SOFF_OFFSET (0x200024) /* TCD12 Signed Source Address Offset Register (TCD12_SOFF) */
+#define S32K3XX_EDMA_TCD12_ATTR_OFFSET (0x200026) /* TCD12 Transfer Attributes (TCD12_ATTR) */
+#define S32K3XX_EDMA_TCD12_NBYTES_OFFSET (0x200028) /* TCD12 Transfer Size (TCD12_NBYTES) */
+#define S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET (0x20002c) /* TCD12 Last Source Address Adjustment / Store DADDR Address Register (TCD12_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD12_DADDR_OFFSET (0x200030) /* TCD12 Destination Address Register (TCD12_DADDR) */
+#define S32K3XX_EDMA_TCD12_DOFF_OFFSET (0x200034) /* TCD12 Signed Destination Address Offset Register (TCD12_DOFF) */
+#define S32K3XX_EDMA_TCD12_CITER_OFFSET (0x200036) /* TCD12 Current Major Loop Count Register (TCD12_CITER) */
+#define S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET (0x200038) /* TCD12 Last Destination Address Adjustment / Scatter Gather Address Register (TCD12_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD12_CSR_OFFSET (0x20003c) /* TCD12 Control and Status Register (TCD12_CSR) */
+#define S32K3XX_EDMA_TCD12_BITER_OFFSET (0x20003e) /* TCD12 Beginning Major Loop Count Register (TCD12_BITER) */
+
+#define S32K3XX_EDMA_CH13_CSR_OFFSET (0x204000) /* Channel 13 Control and Status Register (CH13_CSR) */
+#define S32K3XX_EDMA_CH13_ES_OFFSET (0x204004) /* Channel 13 Error Status Register (CH13_ES) */
+#define S32K3XX_EDMA_CH13_INT_OFFSET (0x204008) /* Channel 13 Interrupt Status Register (CH13_INT) */
+#define S32K3XX_EDMA_CH13_SBR_OFFSET (0x20400c) /* Channel 13 System Bus Register (CH13_SBR) */
+#define S32K3XX_EDMA_CH13_PRI_OFFSET (0x204010) /* Channel 13 Priority Register (CH13_PRI) */
+#define S32K3XX_EDMA_TCD13_SADDR_OFFSET (0x204020) /* TCD13 Source Address Register (TCD13_SADDR) */
+#define S32K3XX_EDMA_TCD13_SOFF_OFFSET (0x204024) /* TCD13 Signed Source Address Offset Register (TCD13_SOFF) */
+#define S32K3XX_EDMA_TCD13_ATTR_OFFSET (0x204026) /* TCD13 Transfer Attributes (TCD13_ATTR) */
+#define S32K3XX_EDMA_TCD13_NBYTES_OFFSET (0x204028) /* TCD13 Transfer Size (TCD13_NBYTES) */
+#define S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET (0x20402c) /* TCD13 Last Source Address Adjustment / Store DADDR Address Register (TCD13_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD13_DADDR_OFFSET (0x204030) /* TCD13 Destination Address Register (TCD13_DADDR) */
+#define S32K3XX_EDMA_TCD13_DOFF_OFFSET (0x204034) /* TCD13 Signed Destination Address Offset Register (TCD13_DOFF) */
+#define S32K3XX_EDMA_TCD13_CITER_OFFSET (0x204036) /* TCD13 Current Major Loop Count Register (TCD13_CITER) */
+#define S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET (0x204038) /* TCD13 Last Destination Address Adjustment / Scatter Gather Address Register (TCD13_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD13_CSR_OFFSET (0x20403c) /* TCD13 Control and Status Register (TCD13_CSR) */
+#define S32K3XX_EDMA_TCD13_BITER_OFFSET (0x20403e) /* TCD13 Beginning Major Loop Count Register (TCD13_BITER) */
+
+#define S32K3XX_EDMA_CH14_CSR_OFFSET (0x208000) /* Channel 14 Control and Status Register (CH14_CSR) */
+#define S32K3XX_EDMA_CH14_ES_OFFSET (0x208004) /* Channel 14 Error Status Register (CH14_ES) */
+#define S32K3XX_EDMA_CH14_INT_OFFSET (0x208008) /* Channel 14 Interrupt Status Register (CH14_INT) */
+#define S32K3XX_EDMA_CH14_SBR_OFFSET (0x20800c) /* Channel 14 System Bus Register (CH14_SBR) */
+#define S32K3XX_EDMA_CH14_PRI_OFFSET (0x208010) /* Channel 14 Priority Register (CH14_PRI) */
+#define S32K3XX_EDMA_TCD14_SADDR_OFFSET (0x208020) /* TCD14 Source Address Register (TCD14_SADDR) */
+#define S32K3XX_EDMA_TCD14_SOFF_OFFSET (0x208024) /* TCD14 Signed Source Address Offset Register (TCD14_SOFF) */
+#define S32K3XX_EDMA_TCD14_ATTR_OFFSET (0x208026) /* TCD14 Transfer Attributes (TCD14_ATTR) */
+#define S32K3XX_EDMA_TCD14_NBYTES_OFFSET (0x208028) /* TCD14 Transfer Size (TCD14_NBYTES) */
+#define S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET (0x20802c) /* TCD14 Last Source Address Adjustment / Store DADDR Address Register (TCD14_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD14_DADDR_OFFSET (0x208030) /* TCD14 Destination Address Register (TCD14_DADDR) */
+#define S32K3XX_EDMA_TCD14_DOFF_OFFSET (0x208034) /* TCD14 Signed Destination Address Offset Register (TCD14_DOFF) */
+#define S32K3XX_EDMA_TCD14_CITER_OFFSET (0x208036) /* TCD14 Current Major Loop Count Register (TCD14_CITER) */
+#define S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET (0x208038) /* TCD14 Last Destination Address Adjustment / Scatter Gather Address Register (TCD14_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD14_CSR_OFFSET (0x20803c) /* TCD14 Control and Status Register (TCD14_CSR) */
+#define S32K3XX_EDMA_TCD14_BITER_OFFSET (0x20803e) /* TCD14 Beginning Major Loop Count Register (TCD14_BITER) */
+
+#define S32K3XX_EDMA_CH15_CSR_OFFSET (0x20c000) /* Channel 15 Control and Status Register (CH15_CSR) */
+#define S32K3XX_EDMA_CH15_ES_OFFSET (0x20c004) /* Channel 15 Error Status Register (CH15_ES) */
+#define S32K3XX_EDMA_CH15_INT_OFFSET (0x20c008) /* Channel 15 Interrupt Status Register (CH15_INT) */
+#define S32K3XX_EDMA_CH15_SBR_OFFSET (0x20c00c) /* Channel 15 System Bus Register (CH15_SBR) */
+#define S32K3XX_EDMA_CH15_PRI_OFFSET (0x20c010) /* Channel 15 Priority Register (CH15_PRI) */
+#define S32K3XX_EDMA_TCD15_SADDR_OFFSET (0x20c020) /* TCD15 Source Address Register (TCD15_SADDR) */
+#define S32K3XX_EDMA_TCD15_SOFF_OFFSET (0x20c024) /* TCD15 Signed Source Address Offset Register (TCD15_SOFF) */
+#define S32K3XX_EDMA_TCD15_ATTR_OFFSET (0x20c026) /* TCD15 Transfer Attributes (TCD15_ATTR) */
+#define S32K3XX_EDMA_TCD15_NBYTES_OFFSET (0x20c028) /* TCD15 Transfer Size (TCD15_NBYTES) */
+#define S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET (0x20c02c) /* TCD15 Last Source Address Adjustment / Store DADDR Address Register (TCD15_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD15_DADDR_OFFSET (0x20c030) /* TCD15 Destination Address Register (TCD15_DADDR) */
+#define S32K3XX_EDMA_TCD15_DOFF_OFFSET (0x20c034) /* TCD15 Signed Destination Address Offset Register (TCD15_DOFF) */
+#define S32K3XX_EDMA_TCD15_CITER_OFFSET (0x20c036) /* TCD15 Current Major Loop Count Register (TCD15_CITER) */
+#define S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET (0x20c038) /* TCD15 Last Destination Address Adjustment / Scatter Gather Address Register (TCD15_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD15_CSR_OFFSET (0x20c03c) /* TCD15 Control and Status Register (TCD15_CSR) */
+#define S32K3XX_EDMA_TCD15_BITER_OFFSET (0x20c03e) /* TCD15 Beginning Major Loop Count Register (TCD15_BITER) */
+
+#define S32K3XX_EDMA_CH16_CSR_OFFSET (0x210000) /* Channel 16 Control and Status Register (CH16_CSR) */
+#define S32K3XX_EDMA_CH16_ES_OFFSET (0x210004) /* Channel 16 Error Status Register (CH16_ES) */
+#define S32K3XX_EDMA_CH16_INT_OFFSET (0x210008) /* Channel 16 Interrupt Status Register (CH16_INT) */
+#define S32K3XX_EDMA_CH16_SBR_OFFSET (0x21000c) /* Channel 16 System Bus Register (CH16_SBR) */
+#define S32K3XX_EDMA_CH16_PRI_OFFSET (0x210010) /* Channel 16 Priority Register (CH16_PRI) */
+#define S32K3XX_EDMA_TCD16_SADDR_OFFSET (0x210020) /* TCD16 Source Address Register (TCD16_SADDR) */
+#define S32K3XX_EDMA_TCD16_SOFF_OFFSET (0x210024) /* TCD16 Signed Source Address Offset Register (TCD16_SOFF) */
+#define S32K3XX_EDMA_TCD16_ATTR_OFFSET (0x210026) /* TCD16 Transfer Attributes (TCD16_ATTR) */
+#define S32K3XX_EDMA_TCD16_NBYTES_OFFSET (0x210028) /* TCD16 Transfer Size (TCD16_NBYTES) */
+#define S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET (0x21002c) /* TCD16 Last Source Address Adjustment / Store DADDR Address Register (TCD16_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD16_DADDR_OFFSET (0x210030) /* TCD16 Destination Address Register (TCD16_DADDR) */
+#define S32K3XX_EDMA_TCD16_DOFF_OFFSET (0x210034) /* TCD16 Signed Destination Address Offset Register (TCD16_DOFF) */
+#define S32K3XX_EDMA_TCD16_CITER_OFFSET (0x210036) /* TCD16 Current Major Loop Count Register (TCD16_CITER) */
+#define S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET (0x210038) /* TCD16 Last Destination Address Adjustment / Scatter Gather Address Register (TCD16_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD16_CSR_OFFSET (0x21003c) /* TCD16 Control and Status Register (TCD16_CSR) */
+#define S32K3XX_EDMA_TCD16_BITER_OFFSET (0x21003e) /* TCD16 Beginning Major Loop Count Register (TCD16_BITER) */
+
+#define S32K3XX_EDMA_CH17_CSR_OFFSET (0x214000) /* Channel 17 Control and Status Register (CH17_CSR) */
+#define S32K3XX_EDMA_CH17_ES_OFFSET (0x214004) /* Channel 17 Error Status Register (CH17_ES) */
+#define S32K3XX_EDMA_CH17_INT_OFFSET (0x214008) /* Channel 17 Interrupt Status Register (CH17_INT) */
+#define S32K3XX_EDMA_CH17_SBR_OFFSET (0x21400c) /* Channel 17 System Bus Register (CH17_SBR) */
+#define S32K3XX_EDMA_CH17_PRI_OFFSET (0x214010) /* Channel 17 Priority Register (CH17_PRI) */
+#define S32K3XX_EDMA_TCD17_SADDR_OFFSET (0x214020) /* TCD17 Source Address Register (TCD17_SADDR) */
+#define S32K3XX_EDMA_TCD17_SOFF_OFFSET (0x214024) /* TCD17 Signed Source Address Offset Register (TCD17_SOFF) */
+#define S32K3XX_EDMA_TCD17_ATTR_OFFSET (0x214026) /* TCD17 Transfer Attributes (TCD17_ATTR) */
+#define S32K3XX_EDMA_TCD17_NBYTES_OFFSET (0x214028) /* TCD17 Transfer Size (TCD17_NBYTES) */
+#define S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET (0x21402c) /* TCD17 Last Source Address Adjustment / Store DADDR Address Register (TCD17_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD17_DADDR_OFFSET (0x214030) /* TCD17 Destination Address Register (TCD17_DADDR) */
+#define S32K3XX_EDMA_TCD17_DOFF_OFFSET (0x214034) /* TCD17 Signed Destination Address Offset Register (TCD17_DOFF) */
+#define S32K3XX_EDMA_TCD17_CITER_OFFSET (0x214036) /* TCD17 Current Major Loop Count Register (TCD17_CITER) */
+#define S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET (0x214038) /* TCD17 Last Destination Address Adjustment / Scatter Gather Address Register (TCD17_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD17_CSR_OFFSET (0x21403c) /* TCD17 Control and Status Register (TCD17_CSR) */
+#define S32K3XX_EDMA_TCD17_BITER_OFFSET (0x21403e) /* TCD17 Beginning Major Loop Count Register (TCD17_BITER) */
+
+#define S32K3XX_EDMA_CH18_CSR_OFFSET (0x218000) /* Channel 18 Control and Status Register (CH18_CSR) */
+#define S32K3XX_EDMA_CH18_ES_OFFSET (0x218004) /* Channel 18 Error Status Register (CH18_ES) */
+#define S32K3XX_EDMA_CH18_INT_OFFSET (0x218008) /* Channel 18 Interrupt Status Register (CH18_INT) */
+#define S32K3XX_EDMA_CH18_SBR_OFFSET (0x21800c) /* Channel 18 System Bus Register (CH18_SBR) */
+#define S32K3XX_EDMA_CH18_PRI_OFFSET (0x218010) /* Channel 18 Priority Register (CH18_PRI) */
+#define S32K3XX_EDMA_TCD18_SADDR_OFFSET (0x218020) /* TCD18 Source Address Register (TCD18_SADDR) */
+#define S32K3XX_EDMA_TCD18_SOFF_OFFSET (0x218024) /* TCD18 Signed Source Address Offset Register (TCD18_SOFF) */
+#define S32K3XX_EDMA_TCD18_ATTR_OFFSET (0x218026) /* TCD18 Transfer Attributes (TCD18_ATTR) */
+#define S32K3XX_EDMA_TCD18_NBYTES_OFFSET (0x218028) /* TCD18 Transfer Size (TCD18_NBYTES) */
+#define S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET (0x21802c) /* TCD18 Last Source Address Adjustment / Store DADDR Address Register (TCD18_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD18_DADDR_OFFSET (0x218030) /* TCD18 Destination Address Register (TCD18_DADDR) */
+#define S32K3XX_EDMA_TCD18_DOFF_OFFSET (0x218034) /* TCD18 Signed Destination Address Offset Register (TCD18_DOFF) */
+#define S32K3XX_EDMA_TCD18_CITER_OFFSET (0x218036) /* TCD18 Current Major Loop Count Register (TCD18_CITER) */
+#define S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET (0x218038) /* TCD18 Last Destination Address Adjustment / Scatter Gather Address Register (TCD18_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD18_CSR_OFFSET (0x21803c) /* TCD18 Control and Status Register (TCD18_CSR) */
+#define S32K3XX_EDMA_TCD18_BITER_OFFSET (0x21803e) /* TCD18 Beginning Major Loop Count Register (TCD18_BITER) */
+
+#define S32K3XX_EDMA_CH19_CSR_OFFSET (0x21c000) /* Channel 19 Control and Status Register (CH19_CSR) */
+#define S32K3XX_EDMA_CH19_ES_OFFSET (0x21c004) /* Channel 19 Error Status Register (CH19_ES) */
+#define S32K3XX_EDMA_CH19_INT_OFFSET (0x21c008) /* Channel 19 Interrupt Status Register (CH19_INT) */
+#define S32K3XX_EDMA_CH19_SBR_OFFSET (0x21c00c) /* Channel 19 System Bus Register (CH19_SBR) */
+#define S32K3XX_EDMA_CH19_PRI_OFFSET (0x21c010) /* Channel 19 Priority Register (CH19_PRI) */
+#define S32K3XX_EDMA_TCD19_SADDR_OFFSET (0x21c020) /* TCD19 Source Address Register (TCD19_SADDR) */
+#define S32K3XX_EDMA_TCD19_SOFF_OFFSET (0x21c024) /* TCD19 Signed Source Address Offset Register (TCD19_SOFF) */
+#define S32K3XX_EDMA_TCD19_ATTR_OFFSET (0x21c026) /* TCD19 Transfer Attributes (TCD19_ATTR) */
+#define S32K3XX_EDMA_TCD19_NBYTES_OFFSET (0x21c028) /* TCD19 Transfer Size (TCD19_NBYTES) */
+#define S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET (0x21c02c) /* TCD19 Last Source Address Adjustment / Store DADDR Address Register (TCD19_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD19_DADDR_OFFSET (0x21c030) /* TCD19 Destination Address Register (TCD19_DADDR) */
+#define S32K3XX_EDMA_TCD19_DOFF_OFFSET (0x21c034) /* TCD19 Signed Destination Address Offset Register (TCD19_DOFF) */
+#define S32K3XX_EDMA_TCD19_CITER_OFFSET (0x21c036) /* TCD19 Current Major Loop Count Register (TCD19_CITER) */
+#define S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET (0x21c038) /* TCD19 Last Destination Address Adjustment / Scatter Gather Address Register (TCD19_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD19_CSR_OFFSET (0x21c03c) /* TCD19 Control and Status Register (TCD19_CSR) */
+#define S32K3XX_EDMA_TCD19_BITER_OFFSET (0x21c03e) /* TCD19 Beginning Major Loop Count Register (TCD19_BITER) */
+
+#define S32K3XX_EDMA_CH20_CSR_OFFSET (0x220000) /* Channel 20 Control and Status Register (CH20_CSR) */
+#define S32K3XX_EDMA_CH20_ES_OFFSET (0x220004) /* Channel 20 Error Status Register (CH20_ES) */
+#define S32K3XX_EDMA_CH20_INT_OFFSET (0x220008) /* Channel 20 Interrupt Status Register (CH20_INT) */
+#define S32K3XX_EDMA_CH20_SBR_OFFSET (0x22000c) /* Channel 20 System Bus Register (CH20_SBR) */
+#define S32K3XX_EDMA_CH20_PRI_OFFSET (0x220010) /* Channel 20 Priority Register (CH20_PRI) */
+#define S32K3XX_EDMA_TCD20_SADDR_OFFSET (0x220020) /* TCD20 Source Address Register (TCD20_SADDR) */
+#define S32K3XX_EDMA_TCD20_SOFF_OFFSET (0x220024) /* TCD20 Signed Source Address Offset Register (TCD20_SOFF) */
+#define S32K3XX_EDMA_TCD20_ATTR_OFFSET (0x220026) /* TCD20 Transfer Attributes (TCD20_ATTR) */
+#define S32K3XX_EDMA_TCD20_NBYTES_OFFSET (0x220028) /* TCD20 Transfer Size (TCD20_NBYTES) */
+#define S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET (0x22002c) /* TCD20 Last Source Address Adjustment / Store DADDR Address Register (TCD20_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD20_DADDR_OFFSET (0x220030) /* TCD20 Destination Address Register (TCD20_DADDR) */
+#define S32K3XX_EDMA_TCD20_DOFF_OFFSET (0x220034) /* TCD20 Signed Destination Address Offset Register (TCD20_DOFF) */
+#define S32K3XX_EDMA_TCD20_CITER_OFFSET (0x220036) /* TCD20 Current Major Loop Count Register (TCD20_CITER) */
+#define S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET (0x220038) /* TCD20 Last Destination Address Adjustment / Scatter Gather Address Register (TCD20_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD20_CSR_OFFSET (0x22003c) /* TCD20 Control and Status Register (TCD20_CSR) */
+#define S32K3XX_EDMA_TCD20_BITER_OFFSET (0x22003e) /* TCD20 Beginning Major Loop Count Register (TCD20_BITER) */
+
+#define S32K3XX_EDMA_CH21_CSR_OFFSET (0x224000) /* Channel 21 Control and Status Register (CH21_CSR) */
+#define S32K3XX_EDMA_CH21_ES_OFFSET (0x224004) /* Channel 21 Error Status Register (CH21_ES) */
+#define S32K3XX_EDMA_CH21_INT_OFFSET (0x224008) /* Channel 21 Interrupt Status Register (CH21_INT) */
+#define S32K3XX_EDMA_CH21_SBR_OFFSET (0x22400c) /* Channel 21 System Bus Register (CH21_SBR) */
+#define S32K3XX_EDMA_CH21_PRI_OFFSET (0x224010) /* Channel 21 Priority Register (CH21_PRI) */
+#define S32K3XX_EDMA_TCD21_SADDR_OFFSET (0x224020) /* TCD21 Source Address Register (TCD21_SADDR) */
+#define S32K3XX_EDMA_TCD21_SOFF_OFFSET (0x224024) /* TCD21 Signed Source Address Offset Register (TCD21_SOFF) */
+#define S32K3XX_EDMA_TCD21_ATTR_OFFSET (0x224026) /* TCD21 Transfer Attributes (TCD21_ATTR) */
+#define S32K3XX_EDMA_TCD21_NBYTES_OFFSET (0x224028) /* TCD21 Transfer Size (TCD21_NBYTES) */
+#define S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET (0x22402c) /* TCD21 Last Source Address Adjustment / Store DADDR Address Register (TCD21_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD21_DADDR_OFFSET (0x224030) /* TCD21 Destination Address Register (TCD21_DADDR) */
+#define S32K3XX_EDMA_TCD21_DOFF_OFFSET (0x224034) /* TCD21 Signed Destination Address Offset Register (TCD21_DOFF) */
+#define S32K3XX_EDMA_TCD21_CITER_OFFSET (0x224036) /* TCD21 Current Major Loop Count Register (TCD21_CITER) */
+#define S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET (0x224038) /* TCD21 Last Destination Address Adjustment / Scatter Gather Address Register (TCD21_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD21_CSR_OFFSET (0x22403c) /* TCD21 Control and Status Register (TCD21_CSR) */
+#define S32K3XX_EDMA_TCD21_BITER_OFFSET (0x22403e) /* TCD21 Beginning Major Loop Count Register (TCD21_BITER) */
+
+#define S32K3XX_EDMA_CH22_CSR_OFFSET (0x228000) /* Channel 22 Control and Status Register (CH22_CSR) */
+#define S32K3XX_EDMA_CH22_ES_OFFSET (0x228004) /* Channel 22 Error Status Register (CH22_ES) */
+#define S32K3XX_EDMA_CH22_INT_OFFSET (0x228008) /* Channel 22 Interrupt Status Register (CH22_INT) */
+#define S32K3XX_EDMA_CH22_SBR_OFFSET (0x22800c) /* Channel 22 System Bus Register (CH22_SBR) */
+#define S32K3XX_EDMA_CH22_PRI_OFFSET (0x228010) /* Channel 22 Priority Register (CH22_PRI) */
+#define S32K3XX_EDMA_TCD22_SADDR_OFFSET (0x228020) /* TCD22 Source Address Register (TCD22_SADDR) */
+#define S32K3XX_EDMA_TCD22_SOFF_OFFSET (0x228024) /* TCD22 Signed Source Address Offset Register (TCD22_SOFF) */
+#define S32K3XX_EDMA_TCD22_ATTR_OFFSET (0x228026) /* TCD22 Transfer Attributes (TCD22_ATTR) */
+#define S32K3XX_EDMA_TCD22_NBYTES_OFFSET (0x228028) /* TCD22 Transfer Size (TCD22_NBYTES) */
+#define S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET (0x22802c) /* TCD22 Last Source Address Adjustment / Store DADDR Address Register (TCD22_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD22_DADDR_OFFSET (0x228030) /* TCD22 Destination Address Register (TCD22_DADDR) */
+#define S32K3XX_EDMA_TCD22_DOFF_OFFSET (0x228034) /* TCD22 Signed Destination Address Offset Register (TCD22_DOFF) */
+#define S32K3XX_EDMA_TCD22_CITER_OFFSET (0x228036) /* TCD22 Current Major Loop Count Register (TCD22_CITER) */
+#define S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET (0x228038) /* TCD22 Last Destination Address Adjustment / Scatter Gather Address Register (TCD22_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD22_CSR_OFFSET (0x22803c) /* TCD22 Control and Status Register (TCD22_CSR) */
+#define S32K3XX_EDMA_TCD22_BITER_OFFSET (0x22803e) /* TCD22 Beginning Major Loop Count Register (TCD22_BITER) */
+
+#define S32K3XX_EDMA_CH23_CSR_OFFSET (0x22c000) /* Channel 23 Control and Status Register (CH23_CSR) */
+#define S32K3XX_EDMA_CH23_ES_OFFSET (0x22c004) /* Channel 23 Error Status Register (CH23_ES) */
+#define S32K3XX_EDMA_CH23_INT_OFFSET (0x22c008) /* Channel 23 Interrupt Status Register (CH23_INT) */
+#define S32K3XX_EDMA_CH23_SBR_OFFSET (0x22c00c) /* Channel 23 System Bus Register (CH23_SBR) */
+#define S32K3XX_EDMA_CH23_PRI_OFFSET (0x22c010) /* Channel 23 Priority Register (CH23_PRI) */
+#define S32K3XX_EDMA_TCD23_SADDR_OFFSET (0x22c020) /* TCD23 Source Address Register (TCD23_SADDR) */
+#define S32K3XX_EDMA_TCD23_SOFF_OFFSET (0x22c024) /* TCD23 Signed Source Address Offset Register (TCD23_SOFF) */
+#define S32K3XX_EDMA_TCD23_ATTR_OFFSET (0x22c026) /* TCD23 Transfer Attributes (TCD23_ATTR) */
+#define S32K3XX_EDMA_TCD23_NBYTES_OFFSET (0x22c028) /* TCD23 Transfer Size (TCD23_NBYTES) */
+#define S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET (0x22c02c) /* TCD23 Last Source Address Adjustment / Store DADDR Address Register (TCD23_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD23_DADDR_OFFSET (0x22c030) /* TCD23 Destination Address Register (TCD23_DADDR) */
+#define S32K3XX_EDMA_TCD23_DOFF_OFFSET (0x22c034) /* TCD23 Signed Destination Address Offset Register (TCD23_DOFF) */
+#define S32K3XX_EDMA_TCD23_CITER_OFFSET (0x22c036) /* TCD23 Current Major Loop Count Register (TCD23_CITER) */
+#define S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET (0x22c038) /* TCD23 Last Destination Address Adjustment / Scatter Gather Address Register (TCD23_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD23_CSR_OFFSET (0x22c03c) /* TCD23 Control and Status Register (TCD23_CSR) */
+#define S32K3XX_EDMA_TCD23_BITER_OFFSET (0x22c03e) /* TCD23 Beginning Major Loop Count Register (TCD23_BITER) */
+
+#define S32K3XX_EDMA_CH24_CSR_OFFSET (0x230000) /* Channel 24 Control and Status Register (CH24_CSR) */
+#define S32K3XX_EDMA_CH24_ES_OFFSET (0x230004) /* Channel 24 Error Status Register (CH24_ES) */
+#define S32K3XX_EDMA_CH24_INT_OFFSET (0x230008) /* Channel 24 Interrupt Status Register (CH24_INT) */
+#define S32K3XX_EDMA_CH24_SBR_OFFSET (0x23000c) /* Channel 24 System Bus Register (CH24_SBR) */
+#define S32K3XX_EDMA_CH24_PRI_OFFSET (0x230010) /* Channel 24 Priority Register (CH24_PRI) */
+#define S32K3XX_EDMA_TCD24_SADDR_OFFSET (0x230020) /* TCD24 Source Address Register (TCD24_SADDR) */
+#define S32K3XX_EDMA_TCD24_SOFF_OFFSET (0x230024) /* TCD24 Signed Source Address Offset Register (TCD24_SOFF) */
+#define S32K3XX_EDMA_TCD24_ATTR_OFFSET (0x230026) /* TCD24 Transfer Attributes (TCD24_ATTR) */
+#define S32K3XX_EDMA_TCD24_NBYTES_OFFSET (0x230028) /* TCD24 Transfer Size (TCD24_NBYTES) */
+#define S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET (0x23002c) /* TCD24 Last Source Address Adjustment / Store DADDR Address Register (TCD24_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD24_DADDR_OFFSET (0x230030) /* TCD24 Destination Address Register (TCD24_DADDR) */
+#define S32K3XX_EDMA_TCD24_DOFF_OFFSET (0x230034) /* TCD24 Signed Destination Address Offset Register (TCD24_DOFF) */
+#define S32K3XX_EDMA_TCD24_CITER_OFFSET (0x230036) /* TCD24 Current Major Loop Count Register (TCD24_CITER) */
+#define S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET (0x230038) /* TCD24 Last Destination Address Adjustment / Scatter Gather Address Register (TCD24_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD24_CSR_OFFSET (0x23003c) /* TCD24 Control and Status Register (TCD24_CSR) */
+#define S32K3XX_EDMA_TCD24_BITER_OFFSET (0x23003e) /* TCD24 Beginning Major Loop Count Register (TCD24_BITER) */
+
+#define S32K3XX_EDMA_CH25_CSR_OFFSET (0x234000) /* Channel 25 Control and Status Register (CH25_CSR) */
+#define S32K3XX_EDMA_CH25_ES_OFFSET (0x234004) /* Channel 25 Error Status Register (CH25_ES) */
+#define S32K3XX_EDMA_CH25_INT_OFFSET (0x234008) /* Channel 25 Interrupt Status Register (CH25_INT) */
+#define S32K3XX_EDMA_CH25_SBR_OFFSET (0x23400c) /* Channel 25 System Bus Register (CH25_SBR) */
+#define S32K3XX_EDMA_CH25_PRI_OFFSET (0x234010) /* Channel 25 Priority Register (CH25_PRI) */
+#define S32K3XX_EDMA_TCD25_SADDR_OFFSET (0x234020) /* TCD25 Source Address Register (TCD25_SADDR) */
+#define S32K3XX_EDMA_TCD25_SOFF_OFFSET (0x234024) /* TCD25 Signed Source Address Offset Register (TCD25_SOFF) */
+#define S32K3XX_EDMA_TCD25_ATTR_OFFSET (0x234026) /* TCD25 Transfer Attributes (TCD25_ATTR) */
+#define S32K3XX_EDMA_TCD25_NBYTES_OFFSET (0x234028) /* TCD25 Transfer Size (TCD25_NBYTES) */
+#define S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET (0x23402c) /* TCD25 Last Source Address Adjustment / Store DADDR Address Register (TCD25_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD25_DADDR_OFFSET (0x234030) /* TCD25 Destination Address Register (TCD25_DADDR) */
+#define S32K3XX_EDMA_TCD25_DOFF_OFFSET (0x234034) /* TCD25 Signed Destination Address Offset Register (TCD25_DOFF) */
+#define S32K3XX_EDMA_TCD25_CITER_OFFSET (0x234036) /* TCD25 Current Major Loop Count Register (TCD25_CITER) */
+#define S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET (0x234038) /* TCD25 Last Destination Address Adjustment / Scatter Gather Address Register (TCD25_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD25_CSR_OFFSET (0x23403c) /* TCD25 Control and Status Register (TCD25_CSR) */
+#define S32K3XX_EDMA_TCD25_BITER_OFFSET (0x23403e) /* TCD25 Beginning Major Loop Count Register (TCD25_BITER) */
+
+#define S32K3XX_EDMA_CH26_CSR_OFFSET (0x238000) /* Channel 26 Control and Status Register (CH26_CSR) */
+#define S32K3XX_EDMA_CH26_ES_OFFSET (0x238004) /* Channel 26 Error Status Register (CH26_ES) */
+#define S32K3XX_EDMA_CH26_INT_OFFSET (0x238008) /* Channel 26 Interrupt Status Register (CH26_INT) */
+#define S32K3XX_EDMA_CH26_SBR_OFFSET (0x23800c) /* Channel 26 System Bus Register (CH26_SBR) */
+#define S32K3XX_EDMA_CH26_PRI_OFFSET (0x238010) /* Channel 26 Priority Register (CH26_PRI) */
+#define S32K3XX_EDMA_TCD26_SADDR_OFFSET (0x238020) /* TCD26 Source Address Register (TCD26_SADDR) */
+#define S32K3XX_EDMA_TCD26_SOFF_OFFSET (0x238024) /* TCD26 Signed Source Address Offset Register (TCD26_SOFF) */
+#define S32K3XX_EDMA_TCD26_ATTR_OFFSET (0x238026) /* TCD26 Transfer Attributes (TCD26_ATTR) */
+#define S32K3XX_EDMA_TCD26_NBYTES_OFFSET (0x238028) /* TCD26 Transfer Size (TCD26_NBYTES) */
+#define S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET (0x23802c) /* TCD26 Last Source Address Adjustment / Store DADDR Address Register (TCD26_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD26_DADDR_OFFSET (0x238030) /* TCD26 Destination Address Register (TCD26_DADDR) */
+#define S32K3XX_EDMA_TCD26_DOFF_OFFSET (0x238034) /* TCD26 Signed Destination Address Offset Register (TCD26_DOFF) */
+#define S32K3XX_EDMA_TCD26_CITER_OFFSET (0x238036) /* TCD26 Current Major Loop Count Register (TCD26_CITER) */
+#define S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET (0x238038) /* TCD26 Last Destination Address Adjustment / Scatter Gather Address Register (TCD26_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD26_CSR_OFFSET (0x23803c) /* TCD26 Control and Status Register (TCD26_CSR) */
+#define S32K3XX_EDMA_TCD26_BITER_OFFSET (0x23803e) /* TCD26 Beginning Major Loop Count Register (TCD26_BITER) */
+
+#define S32K3XX_EDMA_CH27_CSR_OFFSET (0x23c000) /* Channel 27 Control and Status Register (CH27_CSR) */
+#define S32K3XX_EDMA_CH27_ES_OFFSET (0x23c004) /* Channel 27 Error Status Register (CH27_ES) */
+#define S32K3XX_EDMA_CH27_INT_OFFSET (0x23c008) /* Channel 27 Interrupt Status Register (CH27_INT) */
+#define S32K3XX_EDMA_CH27_SBR_OFFSET (0x23c00c) /* Channel 27 System Bus Register (CH27_SBR) */
+#define S32K3XX_EDMA_CH27_PRI_OFFSET (0x23c010) /* Channel 27 Priority Register (CH27_PRI) */
+#define S32K3XX_EDMA_TCD27_SADDR_OFFSET (0x23c020) /* TCD27 Source Address Register (TCD27_SADDR) */
+#define S32K3XX_EDMA_TCD27_SOFF_OFFSET (0x23c024) /* TCD27 Signed Source Address Offset Register (TCD27_SOFF) */
+#define S32K3XX_EDMA_TCD27_ATTR_OFFSET (0x23c026) /* TCD27 Transfer Attributes (TCD27_ATTR) */
+#define S32K3XX_EDMA_TCD27_NBYTES_OFFSET (0x23c028) /* TCD27 Transfer Size (TCD27_NBYTES) */
+#define S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET (0x23c02c) /* TCD27 Last Source Address Adjustment / Store DADDR Address Register (TCD27_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD27_DADDR_OFFSET (0x23c030) /* TCD27 Destination Address Register (TCD27_DADDR) */
+#define S32K3XX_EDMA_TCD27_DOFF_OFFSET (0x23c034) /* TCD27 Signed Destination Address Offset Register (TCD27_DOFF) */
+#define S32K3XX_EDMA_TCD27_CITER_OFFSET (0x23c036) /* TCD27 Current Major Loop Count Register (TCD27_CITER) */
+#define S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET (0x23c038) /* TCD27 Last Destination Address Adjustment / Scatter Gather Address Register (TCD27_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD27_CSR_OFFSET (0x23c03c) /* TCD27 Control and Status Register (TCD27_CSR) */
+#define S32K3XX_EDMA_TCD27_BITER_OFFSET (0x23c03e) /* TCD27 Beginning Major Loop Count Register (TCD27_BITER) */
+
+#define S32K3XX_EDMA_CH28_CSR_OFFSET (0x240000) /* Channel 28 Control and Status Register (CH28_CSR) */
+#define S32K3XX_EDMA_CH28_ES_OFFSET (0x240004) /* Channel 28 Error Status Register (CH28_ES) */
+#define S32K3XX_EDMA_CH28_INT_OFFSET (0x240008) /* Channel 28 Interrupt Status Register (CH28_INT) */
+#define S32K3XX_EDMA_CH28_SBR_OFFSET (0x24000c) /* Channel 28 System Bus Register (CH28_SBR) */
+#define S32K3XX_EDMA_CH28_PRI_OFFSET (0x240010) /* Channel 28 Priority Register (CH28_PRI) */
+#define S32K3XX_EDMA_TCD28_SADDR_OFFSET (0x240020) /* TCD28 Source Address Register (TCD28_SADDR) */
+#define S32K3XX_EDMA_TCD28_SOFF_OFFSET (0x240024) /* TCD28 Signed Source Address Offset Register (TCD28_SOFF) */
+#define S32K3XX_EDMA_TCD28_ATTR_OFFSET (0x240026) /* TCD28 Transfer Attributes (TCD28_ATTR) */
+#define S32K3XX_EDMA_TCD28_NBYTES_OFFSET (0x240028) /* TCD28 Transfer Size (TCD28_NBYTES) */
+#define S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET (0x24002c) /* TCD28 Last Source Address Adjustment / Store DADDR Address Register (TCD28_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD28_DADDR_OFFSET (0x240030) /* TCD28 Destination Address Register (TCD28_DADDR) */
+#define S32K3XX_EDMA_TCD28_DOFF_OFFSET (0x240034) /* TCD28 Signed Destination Address Offset Register (TCD28_DOFF) */
+#define S32K3XX_EDMA_TCD28_CITER_OFFSET (0x240036) /* TCD28 Current Major Loop Count Register (TCD28_CITER) */
+#define S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET (0x240038) /* TCD28 Last Destination Address Adjustment / Scatter Gather Address Register (TCD28_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD28_CSR_OFFSET (0x24003c) /* TCD28 Control and Status Register (TCD28_CSR) */
+#define S32K3XX_EDMA_TCD28_BITER_OFFSET (0x24003e) /* TCD28 Beginning Major Loop Count Register (TCD28_BITER) */
+
+#define S32K3XX_EDMA_CH29_CSR_OFFSET (0x244000) /* Channel 29 Control and Status Register (CH29_CSR) */
+#define S32K3XX_EDMA_CH29_ES_OFFSET (0x244004) /* Channel 29 Error Status Register (CH29_ES) */
+#define S32K3XX_EDMA_CH29_INT_OFFSET (0x244008) /* Channel 29 Interrupt Status Register (CH29_INT) */
+#define S32K3XX_EDMA_CH29_SBR_OFFSET (0x24400c) /* Channel 29 System Bus Register (CH29_SBR) */
+#define S32K3XX_EDMA_CH29_PRI_OFFSET (0x244010) /* Channel 29 Priority Register (CH29_PRI) */
+#define S32K3XX_EDMA_TCD29_SADDR_OFFSET (0x244020) /* TCD29 Source Address Register (TCD29_SADDR) */
+#define S32K3XX_EDMA_TCD29_SOFF_OFFSET (0x244024) /* TCD29 Signed Source Address Offset Register (TCD29_SOFF) */
+#define S32K3XX_EDMA_TCD29_ATTR_OFFSET (0x244026) /* TCD29 Transfer Attributes (TCD29_ATTR) */
+#define S32K3XX_EDMA_TCD29_NBYTES_OFFSET (0x244028) /* TCD29 Transfer Size (TCD29_NBYTES) */
+#define S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET (0x24402c) /* TCD29 Last Source Address Adjustment / Store DADDR Address Register (TCD29_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD29_DADDR_OFFSET (0x244030) /* TCD29 Destination Address Register (TCD29_DADDR) */
+#define S32K3XX_EDMA_TCD29_DOFF_OFFSET (0x244034) /* TCD29 Signed Destination Address Offset Register (TCD29_DOFF) */
+#define S32K3XX_EDMA_TCD29_CITER_OFFSET (0x244036) /* TCD29 Current Major Loop Count Register (TCD29_CITER) */
+#define S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET (0x244038) /* TCD29 Last Destination Address Adjustment / Scatter Gather Address Register (TCD29_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD29_CSR_OFFSET (0x24403c) /* TCD29 Control and Status Register (TCD29_CSR) */
+#define S32K3XX_EDMA_TCD29_BITER_OFFSET (0x24403e) /* TCD29 Beginning Major Loop Count Register (TCD29_BITER) */
+
+#define S32K3XX_EDMA_CH30_CSR_OFFSET (0x248000) /* Channel 30 Control and Status Register (CH30_CSR) */
+#define S32K3XX_EDMA_CH30_ES_OFFSET (0x248004) /* Channel 30 Error Status Register (CH30_ES) */
+#define S32K3XX_EDMA_CH30_INT_OFFSET (0x248008) /* Channel 30 Interrupt Status Register (CH30_INT) */
+#define S32K3XX_EDMA_CH30_SBR_OFFSET (0x24800c) /* Channel 30 System Bus Register (CH30_SBR) */
+#define S32K3XX_EDMA_CH30_PRI_OFFSET (0x248010) /* Channel 30 Priority Register (CH30_PRI) */
+#define S32K3XX_EDMA_TCD30_SADDR_OFFSET (0x248020) /* TCD30 Source Address Register (TCD30_SADDR) */
+#define S32K3XX_EDMA_TCD30_SOFF_OFFSET (0x248024) /* TCD30 Signed Source Address Offset Register (TCD30_SOFF) */
+#define S32K3XX_EDMA_TCD30_ATTR_OFFSET (0x248026) /* TCD30 Transfer Attributes (TCD30_ATTR) */
+#define S32K3XX_EDMA_TCD30_NBYTES_OFFSET (0x248028) /* TCD30 Transfer Size (TCD30_NBYTES) */
+#define S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET (0x24802c) /* TCD30 Last Source Address Adjustment / Store DADDR Address Register (TCD30_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD30_DADDR_OFFSET (0x248030) /* TCD30 Destination Address Register (TCD30_DADDR) */
+#define S32K3XX_EDMA_TCD30_DOFF_OFFSET (0x248034) /* TCD30 Signed Destination Address Offset Register (TCD30_DOFF) */
+#define S32K3XX_EDMA_TCD30_CITER_OFFSET (0x248036) /* TCD30 Current Major Loop Count Register (TCD30_CITER) */
+#define S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET (0x248038) /* TCD30 Last Destination Address Adjustment / Scatter Gather Address Register (TCD30_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD30_CSR_OFFSET (0x24803c) /* TCD30 Control and Status Register (TCD30_CSR) */
+#define S32K3XX_EDMA_TCD30_BITER_OFFSET (0x24803e) /* TCD30 Beginning Major Loop Count Register (TCD30_BITER) */
+
+#define S32K3XX_EDMA_CH31_CSR_OFFSET (0x24c000) /* Channel 31 Control and Status Register (CH31_CSR) */
+#define S32K3XX_EDMA_CH31_ES_OFFSET (0x24c004) /* Channel 31 Error Status Register (CH31_ES) */
+#define S32K3XX_EDMA_CH31_INT_OFFSET (0x24c008) /* Channel 31 Interrupt Status Register (CH31_INT) */
+#define S32K3XX_EDMA_CH31_SBR_OFFSET (0x24c00c) /* Channel 31 System Bus Register (CH31_SBR) */
+#define S32K3XX_EDMA_CH31_PRI_OFFSET (0x24c010) /* Channel 31 Priority Register (CH31_PRI) */
+#define S32K3XX_EDMA_TCD31_SADDR_OFFSET (0x24c020) /* TCD31 Source Address Register (TCD31_SADDR) */
+#define S32K3XX_EDMA_TCD31_SOFF_OFFSET (0x24c024) /* TCD31 Signed Source Address Offset Register (TCD31_SOFF) */
+#define S32K3XX_EDMA_TCD31_ATTR_OFFSET (0x24c026) /* TCD31 Transfer Attributes (TCD31_ATTR) */
+#define S32K3XX_EDMA_TCD31_NBYTES_OFFSET (0x24c028) /* TCD31 Transfer Size (TCD31_NBYTES) */
+#define S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET (0x24c02c) /* TCD31 Last Source Address Adjustment / Store DADDR Address Register (TCD31_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD31_DADDR_OFFSET (0x24c030) /* TCD31 Destination Address Register (TCD31_DADDR) */
+#define S32K3XX_EDMA_TCD31_DOFF_OFFSET (0x24c034) /* TCD31 Signed Destination Address Offset Register (TCD31_DOFF) */
+#define S32K3XX_EDMA_TCD31_CITER_OFFSET (0x24c036) /* TCD31 Current Major Loop Count Register (TCD31_CITER) */
+#define S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET (0x24c038) /* TCD31 Last Destination Address Adjustment / Scatter Gather Address Register (TCD31_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD31_CSR_OFFSET (0x24c03c) /* TCD31 Control and Status Register (TCD31_CSR) */
+#define S32K3XX_EDMA_TCD31_BITER_OFFSET (0x24c03e) /* TCD31 Beginning Major Loop Count Register (TCD31_BITER) */
+
+/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/
+
+#define S32K3XX_EDMA_CH0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_CSR_OFFSET)
+#define S32K3XX_EDMA_CH0_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_ES_OFFSET)
+#define S32K3XX_EDMA_CH0_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_INT_OFFSET)
+#define S32K3XX_EDMA_CH0_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_SBR_OFFSET)
+#define S32K3XX_EDMA_CH0_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD0_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD0_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD0_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD0_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD0_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD0_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_CSR_OFFSET)
+#define S32K3XX_EDMA_CH1_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_ES_OFFSET)
+#define S32K3XX_EDMA_CH1_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_INT_OFFSET)
+#define S32K3XX_EDMA_CH1_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_SBR_OFFSET)
+#define S32K3XX_EDMA_CH1_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD1_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD1_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD1_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD1_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD1_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD1_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_CSR_OFFSET)
+#define S32K3XX_EDMA_CH2_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_ES_OFFSET)
+#define S32K3XX_EDMA_CH2_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_INT_OFFSET)
+#define S32K3XX_EDMA_CH2_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_SBR_OFFSET)
+#define S32K3XX_EDMA_CH2_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD2_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD2_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD2_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD2_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD2_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD2_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_CSR_OFFSET)
+#define S32K3XX_EDMA_CH3_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_ES_OFFSET)
+#define S32K3XX_EDMA_CH3_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_INT_OFFSET)
+#define S32K3XX_EDMA_CH3_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_SBR_OFFSET)
+#define S32K3XX_EDMA_CH3_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD3_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD3_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD3_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD3_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD3_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD3_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_CSR_OFFSET)
+#define S32K3XX_EDMA_CH4_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_ES_OFFSET)
+#define S32K3XX_EDMA_CH4_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_INT_OFFSET)
+#define S32K3XX_EDMA_CH4_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_SBR_OFFSET)
+#define S32K3XX_EDMA_CH4_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD4_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD4_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD4_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD4_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD4_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD4_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_CSR_OFFSET)
+#define S32K3XX_EDMA_CH5_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_ES_OFFSET)
+#define S32K3XX_EDMA_CH5_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_INT_OFFSET)
+#define S32K3XX_EDMA_CH5_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_SBR_OFFSET)
+#define S32K3XX_EDMA_CH5_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD5_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD5_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD5_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD5_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD5_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD5_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_CSR_OFFSET)
+#define S32K3XX_EDMA_CH6_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_ES_OFFSET)
+#define S32K3XX_EDMA_CH6_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_INT_OFFSET)
+#define S32K3XX_EDMA_CH6_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_SBR_OFFSET)
+#define S32K3XX_EDMA_CH6_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD6_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD6_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD6_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD6_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD6_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD6_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_CSR_OFFSET)
+#define S32K3XX_EDMA_CH7_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_ES_OFFSET)
+#define S32K3XX_EDMA_CH7_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_INT_OFFSET)
+#define S32K3XX_EDMA_CH7_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_SBR_OFFSET)
+#define S32K3XX_EDMA_CH7_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD7_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD7_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD7_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD7_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD7_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD7_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_CSR_OFFSET)
+#define S32K3XX_EDMA_CH8_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_ES_OFFSET)
+#define S32K3XX_EDMA_CH8_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_INT_OFFSET)
+#define S32K3XX_EDMA_CH8_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_SBR_OFFSET)
+#define S32K3XX_EDMA_CH8_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD8_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD8_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD8_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD8_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD8_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD8_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_CSR_OFFSET)
+#define S32K3XX_EDMA_CH9_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_ES_OFFSET)
+#define S32K3XX_EDMA_CH9_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_INT_OFFSET)
+#define S32K3XX_EDMA_CH9_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_SBR_OFFSET)
+#define S32K3XX_EDMA_CH9_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD9_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD9_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD9_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD9_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD9_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD9_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_CSR_OFFSET)
+#define S32K3XX_EDMA_CH10_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_ES_OFFSET)
+#define S32K3XX_EDMA_CH10_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_INT_OFFSET)
+#define S32K3XX_EDMA_CH10_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_SBR_OFFSET)
+#define S32K3XX_EDMA_CH10_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD10_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD10_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD10_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD10_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD10_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD10_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_CSR_OFFSET)
+#define S32K3XX_EDMA_CH11_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_ES_OFFSET)
+#define S32K3XX_EDMA_CH11_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_INT_OFFSET)
+#define S32K3XX_EDMA_CH11_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_SBR_OFFSET)
+#define S32K3XX_EDMA_CH11_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD11_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD11_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD11_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD11_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD11_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD11_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_CSR_OFFSET)
+#define S32K3XX_EDMA_CH12_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_ES_OFFSET)
+#define S32K3XX_EDMA_CH12_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_INT_OFFSET)
+#define S32K3XX_EDMA_CH12_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_SBR_OFFSET)
+#define S32K3XX_EDMA_CH12_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD12_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD12_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD12_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD12_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD12_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD12_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_CSR_OFFSET)
+#define S32K3XX_EDMA_CH13_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_ES_OFFSET)
+#define S32K3XX_EDMA_CH13_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_INT_OFFSET)
+#define S32K3XX_EDMA_CH13_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_SBR_OFFSET)
+#define S32K3XX_EDMA_CH13_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD13_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD13_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD13_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD13_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD13_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD13_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_CSR_OFFSET)
+#define S32K3XX_EDMA_CH14_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_ES_OFFSET)
+#define S32K3XX_EDMA_CH14_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_INT_OFFSET)
+#define S32K3XX_EDMA_CH14_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_SBR_OFFSET)
+#define S32K3XX_EDMA_CH14_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD14_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD14_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD14_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD14_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD14_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD14_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_CSR_OFFSET)
+#define S32K3XX_EDMA_CH15_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_ES_OFFSET)
+#define S32K3XX_EDMA_CH15_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_INT_OFFSET)
+#define S32K3XX_EDMA_CH15_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_SBR_OFFSET)
+#define S32K3XX_EDMA_CH15_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD15_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD15_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD15_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD15_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD15_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD15_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_CSR_OFFSET)
+#define S32K3XX_EDMA_CH16_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_ES_OFFSET)
+#define S32K3XX_EDMA_CH16_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_INT_OFFSET)
+#define S32K3XX_EDMA_CH16_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_SBR_OFFSET)
+#define S32K3XX_EDMA_CH16_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD16_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD16_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD16_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD16_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD16_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD16_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_CSR_OFFSET)
+#define S32K3XX_EDMA_CH17_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_ES_OFFSET)
+#define S32K3XX_EDMA_CH17_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_INT_OFFSET)
+#define S32K3XX_EDMA_CH17_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_SBR_OFFSET)
+#define S32K3XX_EDMA_CH17_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD17_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD17_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD17_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD17_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD17_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD17_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_CSR_OFFSET)
+#define S32K3XX_EDMA_CH18_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_ES_OFFSET)
+#define S32K3XX_EDMA_CH18_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_INT_OFFSET)
+#define S32K3XX_EDMA_CH18_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_SBR_OFFSET)
+#define S32K3XX_EDMA_CH18_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD18_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD18_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD18_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD18_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD18_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD18_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_CSR_OFFSET)
+#define S32K3XX_EDMA_CH19_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_ES_OFFSET)
+#define S32K3XX_EDMA_CH19_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_INT_OFFSET)
+#define S32K3XX_EDMA_CH19_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_SBR_OFFSET)
+#define S32K3XX_EDMA_CH19_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD19_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD19_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD19_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD19_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD19_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD19_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_CSR_OFFSET)
+#define S32K3XX_EDMA_CH20_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_ES_OFFSET)
+#define S32K3XX_EDMA_CH20_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_INT_OFFSET)
+#define S32K3XX_EDMA_CH20_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_SBR_OFFSET)
+#define S32K3XX_EDMA_CH20_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD20_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD20_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD20_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD20_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD20_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD20_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_CSR_OFFSET)
+#define S32K3XX_EDMA_CH21_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_ES_OFFSET)
+#define S32K3XX_EDMA_CH21_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_INT_OFFSET)
+#define S32K3XX_EDMA_CH21_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_SBR_OFFSET)
+#define S32K3XX_EDMA_CH21_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD21_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD21_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD21_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD21_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD21_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD21_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_CSR_OFFSET)
+#define S32K3XX_EDMA_CH22_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_ES_OFFSET)
+#define S32K3XX_EDMA_CH22_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_INT_OFFSET)
+#define S32K3XX_EDMA_CH22_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_SBR_OFFSET)
+#define S32K3XX_EDMA_CH22_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD22_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD22_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD22_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD22_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD22_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD22_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_CSR_OFFSET)
+#define S32K3XX_EDMA_CH23_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_ES_OFFSET)
+#define S32K3XX_EDMA_CH23_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_INT_OFFSET)
+#define S32K3XX_EDMA_CH23_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_SBR_OFFSET)
+#define S32K3XX_EDMA_CH23_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD23_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD23_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD23_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD23_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD23_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD23_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_CSR_OFFSET)
+#define S32K3XX_EDMA_CH24_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_ES_OFFSET)
+#define S32K3XX_EDMA_CH24_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_INT_OFFSET)
+#define S32K3XX_EDMA_CH24_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_SBR_OFFSET)
+#define S32K3XX_EDMA_CH24_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD24_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD24_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD24_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD24_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD24_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD24_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_CSR_OFFSET)
+#define S32K3XX_EDMA_CH25_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_ES_OFFSET)
+#define S32K3XX_EDMA_CH25_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_INT_OFFSET)
+#define S32K3XX_EDMA_CH25_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_SBR_OFFSET)
+#define S32K3XX_EDMA_CH25_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD25_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD25_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD25_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD25_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD25_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD25_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_CSR_OFFSET)
+#define S32K3XX_EDMA_CH26_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_ES_OFFSET)
+#define S32K3XX_EDMA_CH26_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_INT_OFFSET)
+#define S32K3XX_EDMA_CH26_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_SBR_OFFSET)
+#define S32K3XX_EDMA_CH26_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD26_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD26_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD26_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD26_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD26_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD26_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_CSR_OFFSET)
+#define S32K3XX_EDMA_CH27_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_ES_OFFSET)
+#define S32K3XX_EDMA_CH27_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_INT_OFFSET)
+#define S32K3XX_EDMA_CH27_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_SBR_OFFSET)
+#define S32K3XX_EDMA_CH27_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD27_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD27_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD27_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD27_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD27_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD27_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_CSR_OFFSET)
+#define S32K3XX_EDMA_CH28_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_ES_OFFSET)
+#define S32K3XX_EDMA_CH28_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_INT_OFFSET)
+#define S32K3XX_EDMA_CH28_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_SBR_OFFSET)
+#define S32K3XX_EDMA_CH28_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD28_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD28_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD28_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD28_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD28_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD28_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_CSR_OFFSET)
+#define S32K3XX_EDMA_CH29_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_ES_OFFSET)
+#define S32K3XX_EDMA_CH29_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_INT_OFFSET)
+#define S32K3XX_EDMA_CH29_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_SBR_OFFSET)
+#define S32K3XX_EDMA_CH29_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD29_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD29_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD29_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD29_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD29_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD29_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_CSR_OFFSET)
+#define S32K3XX_EDMA_CH30_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_ES_OFFSET)
+#define S32K3XX_EDMA_CH30_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_INT_OFFSET)
+#define S32K3XX_EDMA_CH30_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_SBR_OFFSET)
+#define S32K3XX_EDMA_CH30_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD30_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD30_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD30_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD30_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD30_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD30_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_CSR_OFFSET)
+#define S32K3XX_EDMA_CH31_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_ES_OFFSET)
+#define S32K3XX_EDMA_CH31_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_INT_OFFSET)
+#define S32K3XX_EDMA_CH31_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_SBR_OFFSET)
+#define S32K3XX_EDMA_CH31_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD31_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD31_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD31_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD31_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD31_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD31_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_BITER_OFFSET)
+
+uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
+{
+ S32K3XX_EDMA_CH0_CSR,
+ S32K3XX_EDMA_CH1_CSR,
+ S32K3XX_EDMA_CH2_CSR,
+ S32K3XX_EDMA_CH3_CSR,
+ S32K3XX_EDMA_CH4_CSR,
+ S32K3XX_EDMA_CH5_CSR,
+ S32K3XX_EDMA_CH6_CSR,
+ S32K3XX_EDMA_CH7_CSR,
+ S32K3XX_EDMA_CH8_CSR,
+ S32K3XX_EDMA_CH9_CSR,
+ S32K3XX_EDMA_CH10_CSR,
+ S32K3XX_EDMA_CH11_CSR,
+ S32K3XX_EDMA_CH12_CSR,
+ S32K3XX_EDMA_CH13_CSR,
+ S32K3XX_EDMA_CH14_CSR,
+ S32K3XX_EDMA_CH15_CSR,
+ S32K3XX_EDMA_CH16_CSR,
+ S32K3XX_EDMA_CH17_CSR,
+ S32K3XX_EDMA_CH18_CSR,
+ S32K3XX_EDMA_CH19_CSR,
+ S32K3XX_EDMA_CH20_CSR,
+ S32K3XX_EDMA_CH21_CSR,
+ S32K3XX_EDMA_CH22_CSR,
+ S32K3XX_EDMA_CH23_CSR,
+ S32K3XX_EDMA_CH24_CSR,
+ S32K3XX_EDMA_CH25_CSR,
+ S32K3XX_EDMA_CH26_CSR,
+ S32K3XX_EDMA_CH27_CSR,
+ S32K3XX_EDMA_CH28_CSR,
+ S32K3XX_EDMA_CH29_CSR,
+ S32K3XX_EDMA_CH30_CSR,
+ S32K3XX_EDMA_CH31_CSR
+};
+
+/* eDMA Register Bitfield Definitions ***************************************/
+
+/* Management Page Control Register (CSR) */
+
+ /* Bit 0: Reserved */
+#define EDMA_CSR_EDBG (1 << 1) /* Bit 1: Enable Debug (EDBG) */
+#define EDMA_CSR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration (ERCA) */
+ /* Bit 3: Reserved */
+#define EDMA_CSR_HAE (1 << 4) /* Bit 4: Halt After Error (HAE) */
+#define EDMA_CSR_HALT (1 << 5) /* Bit 5: Halt DMA Operations (HALT) */
+#define EDMA_CSR_GCLC (1 << 6) /* Bit 6: Global Channel Linking Control (GCLC) */
+#define EDMA_CSR_GMRC (1 << 7) /* Bit 7: Global Master ID Replication Control (GMRC) */
+#define EDMA_CSR_ECX (1 << 8) /* Bit 8: Cancel Transfer With Error (ECX) */
+#define EDMA_CSR_CX (1 << 9) /* Bit 9: Cancel Transfer (CX) */
+ /* Bits 10-23: Reserved */
+#define EDMA_CSR_ACTIVE_ID_SHIFT (24) /* Bits 24-28: Active Channel ID (ACTIVE_ID) */
+#define EDMA_CSR_ACTIVE_ID_MASK (0x1f << EDMA_CSR_ACTIVE_ID_SHIFT)
+ /* Bits 29-30: Reserved */
+#define EDMA_CSR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status (ACTIVE) */
+
+/* Management Page Error Status Register (ES) */
+
+#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
+#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
+#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
+#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
+#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
+#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
+#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
+#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
+#define EDMA_ES_ECX (1 << 8) /* Bit 8: Transfer Canceled (ECX) */
+#define EDMA_ES_UCE (1 << 9) /* Bit 9: Uncorrectable TCD Error During Channel Execution (UCE) */
+ /* Bits 10-23: Reserved */
+#define EDMA_ES_ERRCHN_SHIFT (8) /* Bits 24-28: Error Channel Number or Canceled Channel Number (ERRCHN) */
+#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT)
+ /* Bits 29-30: Reserved */
+#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status fields (VALID) */
+
+/* Management Page Interrupt Request Status Register (INT) */
+
+#define EDMA_INT(n) (1 << (n)) /* Bit n: Interrupt Request Status (INT) */
+
+/* Management Page Hardware Request Status Register (HRS) */
+
+#define EDMA_HRS(n) (1 << (n)) /* Bit n: Hardware Request Status (HRS) */
+
+/* Channel n Arbitration Group Register (CHn_GRPRI) */
+
+#define EDMA_CH_GRPRI_SHIFT (0) /* Bits 0-4: Arbitration Group For Channel n (GRPRI) */
+#define EDMA_CH_GRPRI_MASK (0x1f << EDMA_CH_GRPRI_SHIFT)
+ /* Bits 5-31: Reserved */
+
+/* eDMA Transfer Control Descriptor (TCD) Bitfield Definitions **************/
+
+/* Channel n Control and Status Register (CHn_CSR) */
+
+#define EDMA_CH_CSR_ERQ (1 << 0) /* Bit 0: Enable DMA Request (ERQ) */
+#define EDMA_CH_CSR_EARQ (1 << 1) /* Bit 1: Enable Asynchronous DMA Request in Stop Mode for Channel (EARQ) */
+#define EDMA_CH_CSR_EEI (1 << 2) /* Bit 2: Enable Error Interrupt (EEI) */
+#define EDMA_CH_CSR_EBW (1 << 3) /* Bit 3: Enable Buffered Writes (EBW) */
+ /* Bit 4-29: Reserved */
+#define EDMA_CH_CSR_DONE (1 << 30) /* Bit 30: Channel Done (DONE) */
+#define EDMA_CH_CSR_ACTIVE (1 << 31) /* Bit 31: CHannel Active (ACTIVE) */
+
+/* Channel n Error Status Register (CHn_ES) */
+
+#define EDMA_CH_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
+#define EDMA_CH_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
+#define EDMA_CH_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
+#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
+#define EDMA_CH_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
+#define EDMA_CH_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
+#define EDMA_CH_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
+#define EDMA_CH_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
+ /* Bit 8-30: Reserved */
+#define EDMA_CH_ES_ERR (1 << 31) /* Bit 31: Error in this channel (ERR) */
+
+/* Channel n Interrupt Status Register (CHn_INT) */
+
+#define EDMA_CH_INT (1 << 0) /* Bit 0: Interrupt Request (INT) */
+ /* Bits 1-31: Reserved */
+
+/* Channel n System Bus Register (CHn_SBR) */
+
+#define EDMA_CH_SBR_MID_SHIFT (0) /* Bits 0-3: Master ID (MID) */
+#define EDMA_CH_SBR_MID_MASK (0x0f << EDMA_CH_SBR_MID_SHIFT)
+ /* Bits 4-14: Reserved */
+#define EDMA_CH_SBR_PAL (1 << 15) /* Bit 15: Privileged Access Level (PAL) */
+#define EDMA_CH_SBR_EMI (1 << 16) /* Bit 16: Enable Master ID Replication (EMI) */
+#define EDMA_CH_SBR_ATTR_SHIFT (17) /* Bits 17-19: Attribute Output (ATTR) */
+#define EDMA_CH_SBR_ATTR_MASK (0x07 << EDMA_CH_SBR_ATTR_SHIFT)
+ /* Bits 20-31: Reserved */
+
+/* Channel n Priority Register (CHn_PRI) */
+
+#define EDMA_CH_PRI_APL_SHIFT (0) /* Bits 0-2: Arbitration Priority Level (APL) */
+#define EDMA_CH_PRI_APL_MASK (0x07 << EDMA_CH_PRI_APL_SHIFT)
+ /* Bits 3-29: Reserved */
+#define EDMA_CH_PRI_DPA (1 << 30) /* Bit 30: Disable Preempt Ability (DPA) */
+#define EDMA_CH_PRI_ECP (1 << 31) /* Bit 31: Enable Channel Preemption (ECP) */
+
+/* TCDn Source Address Register (TCDn_SADDR) */
+
+#define EDMA_TCD_SADDR_SHIFT (0) /* Bits 0-31: Source Address (SADDR) */
+#define EDMA_TCD_SADDR_MASK (0xffffffff << EDMA_TCD_SADDR_SHIFT)
+
+/* TCDn Signed Source Address Offset Register (TCDn_SOFF) */
+
+#define EDMA_TCD_SOFF_SHIFT (0) /* Bits 0-31: Source Address Signed Offset (SOFF) */
+#define EDMA_TCD_SOFF_MASK (0xffffffff << EDMA_TCD_SOFF_SHIFT)
+
+/* TCDn Transfer Attributes (TCDn_ATTR) */
+
+#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */
+#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT)
+#define EDMA_TCD_ATTR_DSIZE(n) ((n << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK)
+#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */
+#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT)
+#define EDMA_TCD_ATTR_DMOD(n) ((n << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK)
+#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */
+#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT)
+#define EDMA_TCD_ATTR_SSIZE(n) ((n << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK)
+# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
+# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
+# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
+# define EDMA_TCD_ATTR_SSIZE_64BIT (0x03 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */
+# define EDMA_TCD_ATTR_SSIZE_16BYTE (0x04 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */
+# define EDMA_TCD_ATTR_SSIZE_32BYTE (0x05 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte */
+# define EDMA_TCD_ATTR_SSIZE_64BYTE (0x06 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-byte */
+
+#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */
+#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT)
+#define EDMA_TCD_ATTR_SMOD(n) ((n << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK)
+
+/* TCDn Transfer Size (TCDn_NBYTES) */
+
+#define EDMA_TCD_NBYTES_SHIFT (0) /* Bits 0-29: Number of Bytes to Transfer per Service Request (NBYTES) */
+#define EDMA_TCD_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_SHIFT)
+#define EDMA_TCD_NBYTES_MASK_MLOFF (0x03ff << EDMA_TCD_NBYTES_SHIFT)
+#define EDMA_TCD_NBYTES_MLOFF_SHIFT (10) /* Bits 10-29: Minor Loop Offset (MLOFF) */
+#define EDMA_TCD_NBYTES_MLOFF_MASK (0x0fffff << EDMA_TCD_NBYTES_MLOFF_SHIFT)
+#define EDMA_TCD_NBYTES_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset Enable (DMLOE) */
+#define EDMA_TCD_NBYTES_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable (SMLOE) */
+
+/* TCDn Last Source Address Adjustment / Store DADDR Address Register
+ * (TCDn_SLAST_SDA)
+ */
+
+#define EDMA_TCD_SLAST_SDA_SHIFT (0) /* Bits 0-31: Last Source Address Adjustment / Store DADDR Address (SLAST_SDA) */
+#define EDMA_TCD_SLAST_SDA_MASK (0xffffffff << EDMA_TCD_SLAST_SDA_SHIFT)
+
+/* TCDn Destination Address Register (TCDn_DADDR) */
+
+#define EDMA_TCD_DADDR_SHIFT (0) /* Bits 0-31: Destination Address (DADDR) */
+#define EDMA_TCD_DADDR_MASK (0xffffffff << EDMA_TCD_DADDR_SHIFT)
+
+/* TCDn Signed Destination Address Offset Register (TCDn_DOFF) */
+
+#define EDMA_TCD_DOFF_SHIFT (0) /* Bits 0-15: Destination Address Signed Offset (DOFF) */
+#define EDMA_TCD_DOFF_MASK (0xffff << EDMA_TCD_DOFF_SHIFT)
+
+/* TCDn Current Major Loop Count Register (TCDn_CITER) */
+
+#define EDMA_TCD_CITER_SHIFT (0) /* Bits 0-14: Current Major Iteration Count (CITER) */
+#define EDMA_TCD_CITER_MASK (0x7fff << EDMA_TCD_CITER_SHIFT)
+#define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT)
+#define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */
+#define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT)
+#define EDMA_TCD_CITER_LINKCH(n) ((n << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT)
+#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
+
+/* TCDn Last Destination Address Adjustment / Scatter Gather Address Register
+ * (TCDn_DLAST_SGA)
+ */
+
+#define EDMA_TCD_DLAST_SGA_SHIFT (0) /* Bits 0-31: Last Destination Address Adjustment / Scatter Gather Address (DLAST_SGA) */
+#define EDMA_TCD_DLAST_SGA_MASK (0xffffffff << EDMA_TCD_DLAST_SGA_SHIFT)
+
+/* TCDn Control and Status Register (TCDn_CSR) */
+
+#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start (START) */
+#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable Interrupt if Major count complete (INTMAJOR) */
+#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable Interrupt if Major Count Half-complete (INTHALF) */
+#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request (DREQ) */
+#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing (ESG) */
+#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable Link When Major Loop Complete (MAJORELINK) */
+#define EDMA_TCD_CSR_EEOP (1 << 6) /* Bit 6: Enable End-Of-Packet Processing (EEOP) */
+#define EDMA_TCD_CSR_ESDA (1 << 7) /* Bit 7: Enable Store Destination Address (ESDA) */
+#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number (MAJORLINKCH) */
+#define EDMA_TCD_CSR_MAJORLINKCH_MASK (0x1f << EDMA_TCD_CSR_MAJORLINKCH_SHIFT)
+#define EDMA_TCD_CSR_MAJORLINKCH(n) ((n << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK)
+ /* Bit 13: Reserved */
+#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control (BWC) */
+#define EDMA_TCD_CSR_BWC_MASK (0x03 << EDMA_TCD_CSR_BWC_SHIFT)
+# define EDMA_TCD_CSR_BWC_NOSTALL (0x00 << EDMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */
+# define EDMA_TCD_CSR_BWC_HPE (0x01 << EDMA_TCD_CSR_BWC_SHIFT) /* Enable eDMA master high-priority elevation (HPE) mode */
+# define EDMA_TCD_CSR_BWC_4CYCLES (0x02 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 4 cycles after each R/W */
+# define EDMA_TCD_CSR_BWC_8CYCLES (0x03 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8 cycles after each R/W */
+
+/* TCDn Beginning Major Loop Count Register (TCDn_BITER) */
+
+#define EDMA_TCD_BITER_SHIFT (0) /* Bits 0-14: Starting Major Iteration Count (BITER) */
+#define EDMA_TCD_BITER_MASK (0x7fff << EDMA_TCD_BITER_SHIFT)
+#define EDMA_TCD_BITER_MASK_ELINK (0x01ff << EDMA_TCD_BITER_SHIFT)
+#define EDMA_TCD_BITER_LINKCH_SHIFT (9) /* Bits 9-13: Link Channel Number (LINKCH) */
+#define EDMA_TCD_BITER_LINKCH_MASK (0x1f << EDMA_TCD_BITER_LINKCH_SHIFT)
+#define EDMA_TCD_BITER_LINKCH(n) ((n << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK)
Review Comment:
```suggestion
#define EDMA_TCD_BITER_LINKCH(n) (((n) << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK)
```
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h:
##########
@@ -0,0 +1,1433 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define S32K3XX_EDMA_NCHANNELS 32
+
+/* eDMA Register Offsets ****************************************************/
+
+#define S32K3XX_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */
+#define S32K3XX_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */
+#define S32K3XX_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */
+#define S32K3XX_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */
+
+#define S32K3XX_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */
+
+/* eDMA Register Addresses **************************************************/
+
+#define S32K3XX_EDMA_CSR (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CSR_OFFSET)
+#define S32K3XX_EDMA_ES (S32K3XX_EDMA_BASE + S32K3XX_EDMA_ES_OFFSET)
+#define S32K3XX_EDMA_INT (S32K3XX_EDMA_BASE + S32K3XX_EDMA_INT_OFFSET)
+#define S32K3XX_EDMA_HRS (S32K3XX_EDMA_BASE + S32K3XX_EDMA_HRS_OFFSET)
+#define S32K3XX_EDMA_CH_GRPRI(n) (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CH_GRPRI_OFFSET(n))
+
+/* eDMA Transfer Control Descriptor (TCD) Register Offsets ******************/
+
+#define S32K3XX_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH0_CSR_OFFSET (0x000000) /* Channel 0 Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH0_ES_OFFSET (0x000004) /* Channel 0 Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH0_INT_OFFSET (0x000008) /* Channel 0 Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH0_SBR_OFFSET (0x00000c) /* Channel 0 System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH0_PRI_OFFSET (0x000010) /* Channel 0 Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD0_SADDR_OFFSET (0x000020) /* TCD0 Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD0_SOFF_OFFSET (0x000024) /* TCD0 Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD0_ATTR_OFFSET (0x000026) /* TCD0 Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD0_NBYTES_OFFSET (0x000028) /* TCD0 Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET (0x00002c) /* TCD0 Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD0_DADDR_OFFSET (0x000030) /* TCD0 Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD0_DOFF_OFFSET (0x000034) /* TCD0 Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD0_CITER_OFFSET (0x000036) /* TCD0 Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET (0x000038) /* TCD0 Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD0_CSR_OFFSET (0x00003c) /* TCD0 Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD0_BITER_OFFSET (0x00003e) /* TCD0 Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH1_CSR_OFFSET (0x004000) /* Channel 1 Control and Status Register (CH1_CSR) */
+#define S32K3XX_EDMA_CH1_ES_OFFSET (0x004004) /* Channel 1 Error Status Register (CH1_ES) */
+#define S32K3XX_EDMA_CH1_INT_OFFSET (0x004008) /* Channel 1 Interrupt Status Register (CH1_INT) */
+#define S32K3XX_EDMA_CH1_SBR_OFFSET (0x00400c) /* Channel 1 System Bus Register (CH1_SBR) */
+#define S32K3XX_EDMA_CH1_PRI_OFFSET (0x004010) /* Channel 1 Priority Register (CH1_PRI) */
+#define S32K3XX_EDMA_TCD1_SADDR_OFFSET (0x004020) /* TCD1 Source Address Register (TCD1_SADDR) */
+#define S32K3XX_EDMA_TCD1_SOFF_OFFSET (0x004024) /* TCD1 Signed Source Address Offset Register (TCD1_SOFF) */
+#define S32K3XX_EDMA_TCD1_ATTR_OFFSET (0x004026) /* TCD1 Transfer Attributes (TCD1_ATTR) */
+#define S32K3XX_EDMA_TCD1_NBYTES_OFFSET (0x004028) /* TCD1 Transfer Size (TCD1_NBYTES) */
+#define S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET (0x00402c) /* TCD1 Last Source Address Adjustment / Store DADDR Address Register (TCD1_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD1_DADDR_OFFSET (0x004030) /* TCD1 Destination Address Register (TCD1_DADDR) */
+#define S32K3XX_EDMA_TCD1_DOFF_OFFSET (0x004034) /* TCD1 Signed Destination Address Offset Register (TCD1_DOFF) */
+#define S32K3XX_EDMA_TCD1_CITER_OFFSET (0x004036) /* TCD1 Current Major Loop Count Register (TCD1_CITER) */
+#define S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET (0x004038) /* TCD1 Last Destination Address Adjustment / Scatter Gather Address Register (TCD1_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD1_CSR_OFFSET (0x00403c) /* TCD1 Control and Status Register (TCD1_CSR) */
+#define S32K3XX_EDMA_TCD1_BITER_OFFSET (0x00403e) /* TCD1 Beginning Major Loop Count Register (TCD1_BITER) */
+
+#define S32K3XX_EDMA_CH2_CSR_OFFSET (0x008000) /* Channel 2 Control and Status Register (CH2_CSR) */
+#define S32K3XX_EDMA_CH2_ES_OFFSET (0x008004) /* Channel 2 Error Status Register (CH2_ES) */
+#define S32K3XX_EDMA_CH2_INT_OFFSET (0x008008) /* Channel 2 Interrupt Status Register (CH2_INT) */
+#define S32K3XX_EDMA_CH2_SBR_OFFSET (0x00800c) /* Channel 2 System Bus Register (CH2_SBR) */
+#define S32K3XX_EDMA_CH2_PRI_OFFSET (0x008010) /* Channel 2 Priority Register (CH2_PRI) */
+#define S32K3XX_EDMA_TCD2_SADDR_OFFSET (0x008020) /* TCD2 Source Address Register (TCD2_SADDR) */
+#define S32K3XX_EDMA_TCD2_SOFF_OFFSET (0x008024) /* TCD2 Signed Source Address Offset Register (TCD2_SOFF) */
+#define S32K3XX_EDMA_TCD2_ATTR_OFFSET (0x008026) /* TCD2 Transfer Attributes (TCD2_ATTR) */
+#define S32K3XX_EDMA_TCD2_NBYTES_OFFSET (0x008028) /* TCD2 Transfer Size (TCD2_NBYTES) */
+#define S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET (0x00802c) /* TCD2 Last Source Address Adjustment / Store DADDR Address Register (TCD2_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD2_DADDR_OFFSET (0x008030) /* TCD2 Destination Address Register (TCD2_DADDR) */
+#define S32K3XX_EDMA_TCD2_DOFF_OFFSET (0x008034) /* TCD2 Signed Destination Address Offset Register (TCD2_DOFF) */
+#define S32K3XX_EDMA_TCD2_CITER_OFFSET (0x008036) /* TCD2 Current Major Loop Count Register (TCD2_CITER) */
+#define S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET (0x008038) /* TCD2 Last Destination Address Adjustment / Scatter Gather Address Register (TCD2_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD2_CSR_OFFSET (0x00803c) /* TCD2 Control and Status Register (TCD2_CSR) */
+#define S32K3XX_EDMA_TCD2_BITER_OFFSET (0x00803e) /* TCD2 Beginning Major Loop Count Register (TCD2_BITER) */
+
+#define S32K3XX_EDMA_CH3_CSR_OFFSET (0x00c000) /* Channel 3 Control and Status Register (CH3_CSR) */
+#define S32K3XX_EDMA_CH3_ES_OFFSET (0x00c004) /* Channel 3 Error Status Register (CH3_ES) */
+#define S32K3XX_EDMA_CH3_INT_OFFSET (0x00c008) /* Channel 3 Interrupt Status Register (CH3_INT) */
+#define S32K3XX_EDMA_CH3_SBR_OFFSET (0x00c00c) /* Channel 3 System Bus Register (CH3_SBR) */
+#define S32K3XX_EDMA_CH3_PRI_OFFSET (0x00c010) /* Channel 3 Priority Register (CH3_PRI) */
+#define S32K3XX_EDMA_TCD3_SADDR_OFFSET (0x00c020) /* TCD3 Source Address Register (TCD3_SADDR) */
+#define S32K3XX_EDMA_TCD3_SOFF_OFFSET (0x00c024) /* TCD3 Signed Source Address Offset Register (TCD3_SOFF) */
+#define S32K3XX_EDMA_TCD3_ATTR_OFFSET (0x00c026) /* TCD3 Transfer Attributes (TCD3_ATTR) */
+#define S32K3XX_EDMA_TCD3_NBYTES_OFFSET (0x00c028) /* TCD3 Transfer Size (TCD3_NBYTES) */
+#define S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET (0x00c02c) /* TCD3 Last Source Address Adjustment / Store DADDR Address Register (TCD3_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD3_DADDR_OFFSET (0x00c030) /* TCD3 Destination Address Register (TCD3_DADDR) */
+#define S32K3XX_EDMA_TCD3_DOFF_OFFSET (0x00c034) /* TCD3 Signed Destination Address Offset Register (TCD3_DOFF) */
+#define S32K3XX_EDMA_TCD3_CITER_OFFSET (0x00c036) /* TCD3 Current Major Loop Count Register (TCD3_CITER) */
+#define S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET (0x00c038) /* TCD3 Last Destination Address Adjustment / Scatter Gather Address Register (TCD3_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD3_CSR_OFFSET (0x00c03c) /* TCD3 Control and Status Register (TCD3_CSR) */
+#define S32K3XX_EDMA_TCD3_BITER_OFFSET (0x00c03e) /* TCD3 Beginning Major Loop Count Register (TCD3_BITER) */
+
+#define S32K3XX_EDMA_CH4_CSR_OFFSET (0x010000) /* Channel 4 Control and Status Register (CH4_CSR) */
+#define S32K3XX_EDMA_CH4_ES_OFFSET (0x010004) /* Channel 4 Error Status Register (CH4_ES) */
+#define S32K3XX_EDMA_CH4_INT_OFFSET (0x010008) /* Channel 4 Interrupt Status Register (CH4_INT) */
+#define S32K3XX_EDMA_CH4_SBR_OFFSET (0x01000c) /* Channel 4 System Bus Register (CH4_SBR) */
+#define S32K3XX_EDMA_CH4_PRI_OFFSET (0x010010) /* Channel 4 Priority Register (CH4_PRI) */
+#define S32K3XX_EDMA_TCD4_SADDR_OFFSET (0x010020) /* TCD4 Source Address Register (TCD4_SADDR) */
+#define S32K3XX_EDMA_TCD4_SOFF_OFFSET (0x010024) /* TCD4 Signed Source Address Offset Register (TCD4_SOFF) */
+#define S32K3XX_EDMA_TCD4_ATTR_OFFSET (0x010026) /* TCD4 Transfer Attributes (TCD4_ATTR) */
+#define S32K3XX_EDMA_TCD4_NBYTES_OFFSET (0x010028) /* TCD4 Transfer Size (TCD4_NBYTES) */
+#define S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET (0x01002c) /* TCD4 Last Source Address Adjustment / Store DADDR Address Register (TCD4_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD4_DADDR_OFFSET (0x010030) /* TCD4 Destination Address Register (TCD4_DADDR) */
+#define S32K3XX_EDMA_TCD4_DOFF_OFFSET (0x010034) /* TCD4 Signed Destination Address Offset Register (TCD4_DOFF) */
+#define S32K3XX_EDMA_TCD4_CITER_OFFSET (0x010036) /* TCD4 Current Major Loop Count Register (TCD4_CITER) */
+#define S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET (0x010038) /* TCD4 Last Destination Address Adjustment / Scatter Gather Address Register (TCD4_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD4_CSR_OFFSET (0x01003c) /* TCD4 Control and Status Register (TCD4_CSR) */
+#define S32K3XX_EDMA_TCD4_BITER_OFFSET (0x01003e) /* TCD4 Beginning Major Loop Count Register (TCD4_BITER) */
+
+#define S32K3XX_EDMA_CH5_CSR_OFFSET (0x014000) /* Channel 5 Control and Status Register (CH5_CSR) */
+#define S32K3XX_EDMA_CH5_ES_OFFSET (0x014004) /* Channel 5 Error Status Register (CH5_ES) */
+#define S32K3XX_EDMA_CH5_INT_OFFSET (0x014008) /* Channel 5 Interrupt Status Register (CH5_INT) */
+#define S32K3XX_EDMA_CH5_SBR_OFFSET (0x01400c) /* Channel 5 System Bus Register (CH5_SBR) */
+#define S32K3XX_EDMA_CH5_PRI_OFFSET (0x014010) /* Channel 5 Priority Register (CH5_PRI) */
+#define S32K3XX_EDMA_TCD5_SADDR_OFFSET (0x014020) /* TCD5 Source Address Register (TCD5_SADDR) */
+#define S32K3XX_EDMA_TCD5_SOFF_OFFSET (0x014024) /* TCD5 Signed Source Address Offset Register (TCD5_SOFF) */
+#define S32K3XX_EDMA_TCD5_ATTR_OFFSET (0x014026) /* TCD5 Transfer Attributes (TCD5_ATTR) */
+#define S32K3XX_EDMA_TCD5_NBYTES_OFFSET (0x014028) /* TCD5 Transfer Size (TCD5_NBYTES) */
+#define S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET (0x01402c) /* TCD5 Last Source Address Adjustment / Store DADDR Address Register (TCD5_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD5_DADDR_OFFSET (0x014030) /* TCD5 Destination Address Register (TCD5_DADDR) */
+#define S32K3XX_EDMA_TCD5_DOFF_OFFSET (0x014034) /* TCD5 Signed Destination Address Offset Register (TCD5_DOFF) */
+#define S32K3XX_EDMA_TCD5_CITER_OFFSET (0x014036) /* TCD5 Current Major Loop Count Register (TCD5_CITER) */
+#define S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET (0x014038) /* TCD5 Last Destination Address Adjustment / Scatter Gather Address Register (TCD5_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD5_CSR_OFFSET (0x01403c) /* TCD5 Control and Status Register (TCD5_CSR) */
+#define S32K3XX_EDMA_TCD5_BITER_OFFSET (0x01403e) /* TCD5 Beginning Major Loop Count Register (TCD5_BITER) */
+
+#define S32K3XX_EDMA_CH6_CSR_OFFSET (0x018000) /* Channel 6 Control and Status Register (CH6_CSR) */
+#define S32K3XX_EDMA_CH6_ES_OFFSET (0x018004) /* Channel 6 Error Status Register (CH6_ES) */
+#define S32K3XX_EDMA_CH6_INT_OFFSET (0x018008) /* Channel 6 Interrupt Status Register (CH6_INT) */
+#define S32K3XX_EDMA_CH6_SBR_OFFSET (0x01800c) /* Channel 6 System Bus Register (CH6_SBR) */
+#define S32K3XX_EDMA_CH6_PRI_OFFSET (0x018010) /* Channel 6 Priority Register (CH6_PRI) */
+#define S32K3XX_EDMA_TCD6_SADDR_OFFSET (0x018020) /* TCD6 Source Address Register (TCD6_SADDR) */
+#define S32K3XX_EDMA_TCD6_SOFF_OFFSET (0x018024) /* TCD6 Signed Source Address Offset Register (TCD6_SOFF) */
+#define S32K3XX_EDMA_TCD6_ATTR_OFFSET (0x018026) /* TCD6 Transfer Attributes (TCD6_ATTR) */
+#define S32K3XX_EDMA_TCD6_NBYTES_OFFSET (0x018028) /* TCD6 Transfer Size (TCD6_NBYTES) */
+#define S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET (0x01802c) /* TCD6 Last Source Address Adjustment / Store DADDR Address Register (TCD6_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD6_DADDR_OFFSET (0x018030) /* TCD6 Destination Address Register (TCD6_DADDR) */
+#define S32K3XX_EDMA_TCD6_DOFF_OFFSET (0x018034) /* TCD6 Signed Destination Address Offset Register (TCD6_DOFF) */
+#define S32K3XX_EDMA_TCD6_CITER_OFFSET (0x018036) /* TCD6 Current Major Loop Count Register (TCD6_CITER) */
+#define S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET (0x018038) /* TCD6 Last Destination Address Adjustment / Scatter Gather Address Register (TCD6_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD6_CSR_OFFSET (0x01803c) /* TCD6 Control and Status Register (TCD6_CSR) */
+#define S32K3XX_EDMA_TCD6_BITER_OFFSET (0x01803e) /* TCD6 Beginning Major Loop Count Register (TCD6_BITER) */
+
+#define S32K3XX_EDMA_CH7_CSR_OFFSET (0x01c000) /* Channel 7 Control and Status Register (CH7_CSR) */
+#define S32K3XX_EDMA_CH7_ES_OFFSET (0x01c004) /* Channel 7 Error Status Register (CH7_ES) */
+#define S32K3XX_EDMA_CH7_INT_OFFSET (0x01c008) /* Channel 7 Interrupt Status Register (CH7_INT) */
+#define S32K3XX_EDMA_CH7_SBR_OFFSET (0x01c00c) /* Channel 7 System Bus Register (CH7_SBR) */
+#define S32K3XX_EDMA_CH7_PRI_OFFSET (0x01c010) /* Channel 7 Priority Register (CH7_PRI) */
+#define S32K3XX_EDMA_TCD7_SADDR_OFFSET (0x01c020) /* TCD7 Source Address Register (TCD7_SADDR) */
+#define S32K3XX_EDMA_TCD7_SOFF_OFFSET (0x01c024) /* TCD7 Signed Source Address Offset Register (TCD7_SOFF) */
+#define S32K3XX_EDMA_TCD7_ATTR_OFFSET (0x01c026) /* TCD7 Transfer Attributes (TCD7_ATTR) */
+#define S32K3XX_EDMA_TCD7_NBYTES_OFFSET (0x01c028) /* TCD7 Transfer Size (TCD7_NBYTES) */
+#define S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET (0x01c02c) /* TCD7 Last Source Address Adjustment / Store DADDR Address Register (TCD7_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD7_DADDR_OFFSET (0x01c030) /* TCD7 Destination Address Register (TCD7_DADDR) */
+#define S32K3XX_EDMA_TCD7_DOFF_OFFSET (0x01c034) /* TCD7 Signed Destination Address Offset Register (TCD7_DOFF) */
+#define S32K3XX_EDMA_TCD7_CITER_OFFSET (0x01c036) /* TCD7 Current Major Loop Count Register (TCD7_CITER) */
+#define S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET (0x01c038) /* TCD7 Last Destination Address Adjustment / Scatter Gather Address Register (TCD7_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD7_CSR_OFFSET (0x01c03c) /* TCD7 Control and Status Register (TCD7_CSR) */
+#define S32K3XX_EDMA_TCD7_BITER_OFFSET (0x01c03e) /* TCD7 Beginning Major Loop Count Register (TCD7_BITER) */
+
+#define S32K3XX_EDMA_CH8_CSR_OFFSET (0x020000) /* Channel 8 Control and Status Register (CH8_CSR) */
+#define S32K3XX_EDMA_CH8_ES_OFFSET (0x020004) /* Channel 8 Error Status Register (CH8_ES) */
+#define S32K3XX_EDMA_CH8_INT_OFFSET (0x020008) /* Channel 8 Interrupt Status Register (CH8_INT) */
+#define S32K3XX_EDMA_CH8_SBR_OFFSET (0x02000c) /* Channel 8 System Bus Register (CH8_SBR) */
+#define S32K3XX_EDMA_CH8_PRI_OFFSET (0x020010) /* Channel 8 Priority Register (CH8_PRI) */
+#define S32K3XX_EDMA_TCD8_SADDR_OFFSET (0x020020) /* TCD8 Source Address Register (TCD8_SADDR) */
+#define S32K3XX_EDMA_TCD8_SOFF_OFFSET (0x020024) /* TCD8 Signed Source Address Offset Register (TCD8_SOFF) */
+#define S32K3XX_EDMA_TCD8_ATTR_OFFSET (0x020026) /* TCD8 Transfer Attributes (TCD8_ATTR) */
+#define S32K3XX_EDMA_TCD8_NBYTES_OFFSET (0x020028) /* TCD8 Transfer Size (TCD8_NBYTES) */
+#define S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET (0x02002c) /* TCD8 Last Source Address Adjustment / Store DADDR Address Register (TCD8_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD8_DADDR_OFFSET (0x020030) /* TCD8 Destination Address Register (TCD8_DADDR) */
+#define S32K3XX_EDMA_TCD8_DOFF_OFFSET (0x020034) /* TCD8 Signed Destination Address Offset Register (TCD8_DOFF) */
+#define S32K3XX_EDMA_TCD8_CITER_OFFSET (0x020036) /* TCD8 Current Major Loop Count Register (TCD8_CITER) */
+#define S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET (0x020038) /* TCD8 Last Destination Address Adjustment / Scatter Gather Address Register (TCD8_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD8_CSR_OFFSET (0x02003c) /* TCD8 Control and Status Register (TCD8_CSR) */
+#define S32K3XX_EDMA_TCD8_BITER_OFFSET (0x02003e) /* TCD8 Beginning Major Loop Count Register (TCD8_BITER) */
+
+#define S32K3XX_EDMA_CH9_CSR_OFFSET (0x024000) /* Channel 9 Control and Status Register (CH9_CSR) */
+#define S32K3XX_EDMA_CH9_ES_OFFSET (0x024004) /* Channel 9 Error Status Register (CH9_ES) */
+#define S32K3XX_EDMA_CH9_INT_OFFSET (0x024008) /* Channel 9 Interrupt Status Register (CH9_INT) */
+#define S32K3XX_EDMA_CH9_SBR_OFFSET (0x02400c) /* Channel 9 System Bus Register (CH9_SBR) */
+#define S32K3XX_EDMA_CH9_PRI_OFFSET (0x024010) /* Channel 9 Priority Register (CH9_PRI) */
+#define S32K3XX_EDMA_TCD9_SADDR_OFFSET (0x024020) /* TCD9 Source Address Register (TCD9_SADDR) */
+#define S32K3XX_EDMA_TCD9_SOFF_OFFSET (0x024024) /* TCD9 Signed Source Address Offset Register (TCD9_SOFF) */
+#define S32K3XX_EDMA_TCD9_ATTR_OFFSET (0x024026) /* TCD9 Transfer Attributes (TCD9_ATTR) */
+#define S32K3XX_EDMA_TCD9_NBYTES_OFFSET (0x024028) /* TCD9 Transfer Size (TCD9_NBYTES) */
+#define S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET (0x02402c) /* TCD9 Last Source Address Adjustment / Store DADDR Address Register (TCD9_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD9_DADDR_OFFSET (0x024030) /* TCD9 Destination Address Register (TCD9_DADDR) */
+#define S32K3XX_EDMA_TCD9_DOFF_OFFSET (0x024034) /* TCD9 Signed Destination Address Offset Register (TCD9_DOFF) */
+#define S32K3XX_EDMA_TCD9_CITER_OFFSET (0x024036) /* TCD9 Current Major Loop Count Register (TCD9_CITER) */
+#define S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET (0x024038) /* TCD9 Last Destination Address Adjustment / Scatter Gather Address Register (TCD9_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD9_CSR_OFFSET (0x02403c) /* TCD9 Control and Status Register (TCD9_CSR) */
+#define S32K3XX_EDMA_TCD9_BITER_OFFSET (0x02403e) /* TCD9 Beginning Major Loop Count Register (TCD9_BITER) */
+
+#define S32K3XX_EDMA_CH10_CSR_OFFSET (0x028000) /* Channel 10 Control and Status Register (CH10_CSR) */
+#define S32K3XX_EDMA_CH10_ES_OFFSET (0x028004) /* Channel 10 Error Status Register (CH10_ES) */
+#define S32K3XX_EDMA_CH10_INT_OFFSET (0x028008) /* Channel 10 Interrupt Status Register (CH10_INT) */
+#define S32K3XX_EDMA_CH10_SBR_OFFSET (0x02800c) /* Channel 10 System Bus Register (CH10_SBR) */
+#define S32K3XX_EDMA_CH10_PRI_OFFSET (0x028010) /* Channel 10 Priority Register (CH10_PRI) */
+#define S32K3XX_EDMA_TCD10_SADDR_OFFSET (0x028020) /* TCD10 Source Address Register (TCD10_SADDR) */
+#define S32K3XX_EDMA_TCD10_SOFF_OFFSET (0x028024) /* TCD10 Signed Source Address Offset Register (TCD10_SOFF) */
+#define S32K3XX_EDMA_TCD10_ATTR_OFFSET (0x028026) /* TCD10 Transfer Attributes (TCD10_ATTR) */
+#define S32K3XX_EDMA_TCD10_NBYTES_OFFSET (0x028028) /* TCD10 Transfer Size (TCD10_NBYTES) */
+#define S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET (0x02802c) /* TCD10 Last Source Address Adjustment / Store DADDR Address Register (TCD10_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD10_DADDR_OFFSET (0x028030) /* TCD10 Destination Address Register (TCD10_DADDR) */
+#define S32K3XX_EDMA_TCD10_DOFF_OFFSET (0x028034) /* TCD10 Signed Destination Address Offset Register (TCD10_DOFF) */
+#define S32K3XX_EDMA_TCD10_CITER_OFFSET (0x028036) /* TCD10 Current Major Loop Count Register (TCD10_CITER) */
+#define S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET (0x028038) /* TCD10 Last Destination Address Adjustment / Scatter Gather Address Register (TCD10_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD10_CSR_OFFSET (0x02803c) /* TCD10 Control and Status Register (TCD10_CSR) */
+#define S32K3XX_EDMA_TCD10_BITER_OFFSET (0x02803e) /* TCD10 Beginning Major Loop Count Register (TCD10_BITER) */
+#define S32K3XX_EDMA_CH11_CSR_OFFSET (0x02c000) /* Channel 11 Control and Status Register (CH11_CSR) */
+#define S32K3XX_EDMA_CH11_ES_OFFSET (0x02c004) /* Channel 11 Error Status Register (CH11_ES) */
+#define S32K3XX_EDMA_CH11_INT_OFFSET (0x02c008) /* Channel 11 Interrupt Status Register (CH11_INT) */
+#define S32K3XX_EDMA_CH11_SBR_OFFSET (0x02c00c) /* Channel 11 System Bus Register (CH11_SBR) */
+#define S32K3XX_EDMA_CH11_PRI_OFFSET (0x02c010) /* Channel 11 Priority Register (CH11_PRI) */
+#define S32K3XX_EDMA_TCD11_SADDR_OFFSET (0x02c020) /* TCD11 Source Address Register (TCD11_SADDR) */
+#define S32K3XX_EDMA_TCD11_SOFF_OFFSET (0x02c024) /* TCD11 Signed Source Address Offset Register (TCD11_SOFF) */
+#define S32K3XX_EDMA_TCD11_ATTR_OFFSET (0x02c026) /* TCD11 Transfer Attributes (TCD11_ATTR) */
+#define S32K3XX_EDMA_TCD11_NBYTES_OFFSET (0x02c028) /* TCD11 Transfer Size (TCD11_NBYTES) */
+#define S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET (0x02c02c) /* TCD11 Last Source Address Adjustment / Store DADDR Address Register (TCD11_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD11_DADDR_OFFSET (0x02c030) /* TCD11 Destination Address Register (TCD11_DADDR) */
+#define S32K3XX_EDMA_TCD11_DOFF_OFFSET (0x02c034) /* TCD11 Signed Destination Address Offset Register (TCD11_DOFF) */
+#define S32K3XX_EDMA_TCD11_CITER_OFFSET (0x02c036) /* TCD11 Current Major Loop Count Register (TCD11_CITER) */
+#define S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET (0x02c038) /* TCD11 Last Destination Address Adjustment / Scatter Gather Address Register (TCD11_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD11_CSR_OFFSET (0x02c03c) /* TCD11 Control and Status Register (TCD11_CSR) */
+#define S32K3XX_EDMA_TCD11_BITER_OFFSET (0x02c03e) /* TCD11 Beginning Major Loop Count Register (TCD11_BITER) */
+
+#define S32K3XX_EDMA_CH12_CSR_OFFSET (0x200000) /* Channel 12 Control and Status Register (CH12_CSR) */
+#define S32K3XX_EDMA_CH12_ES_OFFSET (0x200004) /* Channel 12 Error Status Register (CH12_ES) */
+#define S32K3XX_EDMA_CH12_INT_OFFSET (0x200008) /* Channel 12 Interrupt Status Register (CH12_INT) */
+#define S32K3XX_EDMA_CH12_SBR_OFFSET (0x20000c) /* Channel 12 System Bus Register (CH12_SBR) */
+#define S32K3XX_EDMA_CH12_PRI_OFFSET (0x200010) /* Channel 12 Priority Register (CH12_PRI) */
+#define S32K3XX_EDMA_TCD12_SADDR_OFFSET (0x200020) /* TCD12 Source Address Register (TCD12_SADDR) */
+#define S32K3XX_EDMA_TCD12_SOFF_OFFSET (0x200024) /* TCD12 Signed Source Address Offset Register (TCD12_SOFF) */
+#define S32K3XX_EDMA_TCD12_ATTR_OFFSET (0x200026) /* TCD12 Transfer Attributes (TCD12_ATTR) */
+#define S32K3XX_EDMA_TCD12_NBYTES_OFFSET (0x200028) /* TCD12 Transfer Size (TCD12_NBYTES) */
+#define S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET (0x20002c) /* TCD12 Last Source Address Adjustment / Store DADDR Address Register (TCD12_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD12_DADDR_OFFSET (0x200030) /* TCD12 Destination Address Register (TCD12_DADDR) */
+#define S32K3XX_EDMA_TCD12_DOFF_OFFSET (0x200034) /* TCD12 Signed Destination Address Offset Register (TCD12_DOFF) */
+#define S32K3XX_EDMA_TCD12_CITER_OFFSET (0x200036) /* TCD12 Current Major Loop Count Register (TCD12_CITER) */
+#define S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET (0x200038) /* TCD12 Last Destination Address Adjustment / Scatter Gather Address Register (TCD12_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD12_CSR_OFFSET (0x20003c) /* TCD12 Control and Status Register (TCD12_CSR) */
+#define S32K3XX_EDMA_TCD12_BITER_OFFSET (0x20003e) /* TCD12 Beginning Major Loop Count Register (TCD12_BITER) */
+
+#define S32K3XX_EDMA_CH13_CSR_OFFSET (0x204000) /* Channel 13 Control and Status Register (CH13_CSR) */
+#define S32K3XX_EDMA_CH13_ES_OFFSET (0x204004) /* Channel 13 Error Status Register (CH13_ES) */
+#define S32K3XX_EDMA_CH13_INT_OFFSET (0x204008) /* Channel 13 Interrupt Status Register (CH13_INT) */
+#define S32K3XX_EDMA_CH13_SBR_OFFSET (0x20400c) /* Channel 13 System Bus Register (CH13_SBR) */
+#define S32K3XX_EDMA_CH13_PRI_OFFSET (0x204010) /* Channel 13 Priority Register (CH13_PRI) */
+#define S32K3XX_EDMA_TCD13_SADDR_OFFSET (0x204020) /* TCD13 Source Address Register (TCD13_SADDR) */
+#define S32K3XX_EDMA_TCD13_SOFF_OFFSET (0x204024) /* TCD13 Signed Source Address Offset Register (TCD13_SOFF) */
+#define S32K3XX_EDMA_TCD13_ATTR_OFFSET (0x204026) /* TCD13 Transfer Attributes (TCD13_ATTR) */
+#define S32K3XX_EDMA_TCD13_NBYTES_OFFSET (0x204028) /* TCD13 Transfer Size (TCD13_NBYTES) */
+#define S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET (0x20402c) /* TCD13 Last Source Address Adjustment / Store DADDR Address Register (TCD13_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD13_DADDR_OFFSET (0x204030) /* TCD13 Destination Address Register (TCD13_DADDR) */
+#define S32K3XX_EDMA_TCD13_DOFF_OFFSET (0x204034) /* TCD13 Signed Destination Address Offset Register (TCD13_DOFF) */
+#define S32K3XX_EDMA_TCD13_CITER_OFFSET (0x204036) /* TCD13 Current Major Loop Count Register (TCD13_CITER) */
+#define S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET (0x204038) /* TCD13 Last Destination Address Adjustment / Scatter Gather Address Register (TCD13_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD13_CSR_OFFSET (0x20403c) /* TCD13 Control and Status Register (TCD13_CSR) */
+#define S32K3XX_EDMA_TCD13_BITER_OFFSET (0x20403e) /* TCD13 Beginning Major Loop Count Register (TCD13_BITER) */
+
+#define S32K3XX_EDMA_CH14_CSR_OFFSET (0x208000) /* Channel 14 Control and Status Register (CH14_CSR) */
+#define S32K3XX_EDMA_CH14_ES_OFFSET (0x208004) /* Channel 14 Error Status Register (CH14_ES) */
+#define S32K3XX_EDMA_CH14_INT_OFFSET (0x208008) /* Channel 14 Interrupt Status Register (CH14_INT) */
+#define S32K3XX_EDMA_CH14_SBR_OFFSET (0x20800c) /* Channel 14 System Bus Register (CH14_SBR) */
+#define S32K3XX_EDMA_CH14_PRI_OFFSET (0x208010) /* Channel 14 Priority Register (CH14_PRI) */
+#define S32K3XX_EDMA_TCD14_SADDR_OFFSET (0x208020) /* TCD14 Source Address Register (TCD14_SADDR) */
+#define S32K3XX_EDMA_TCD14_SOFF_OFFSET (0x208024) /* TCD14 Signed Source Address Offset Register (TCD14_SOFF) */
+#define S32K3XX_EDMA_TCD14_ATTR_OFFSET (0x208026) /* TCD14 Transfer Attributes (TCD14_ATTR) */
+#define S32K3XX_EDMA_TCD14_NBYTES_OFFSET (0x208028) /* TCD14 Transfer Size (TCD14_NBYTES) */
+#define S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET (0x20802c) /* TCD14 Last Source Address Adjustment / Store DADDR Address Register (TCD14_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD14_DADDR_OFFSET (0x208030) /* TCD14 Destination Address Register (TCD14_DADDR) */
+#define S32K3XX_EDMA_TCD14_DOFF_OFFSET (0x208034) /* TCD14 Signed Destination Address Offset Register (TCD14_DOFF) */
+#define S32K3XX_EDMA_TCD14_CITER_OFFSET (0x208036) /* TCD14 Current Major Loop Count Register (TCD14_CITER) */
+#define S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET (0x208038) /* TCD14 Last Destination Address Adjustment / Scatter Gather Address Register (TCD14_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD14_CSR_OFFSET (0x20803c) /* TCD14 Control and Status Register (TCD14_CSR) */
+#define S32K3XX_EDMA_TCD14_BITER_OFFSET (0x20803e) /* TCD14 Beginning Major Loop Count Register (TCD14_BITER) */
+
+#define S32K3XX_EDMA_CH15_CSR_OFFSET (0x20c000) /* Channel 15 Control and Status Register (CH15_CSR) */
+#define S32K3XX_EDMA_CH15_ES_OFFSET (0x20c004) /* Channel 15 Error Status Register (CH15_ES) */
+#define S32K3XX_EDMA_CH15_INT_OFFSET (0x20c008) /* Channel 15 Interrupt Status Register (CH15_INT) */
+#define S32K3XX_EDMA_CH15_SBR_OFFSET (0x20c00c) /* Channel 15 System Bus Register (CH15_SBR) */
+#define S32K3XX_EDMA_CH15_PRI_OFFSET (0x20c010) /* Channel 15 Priority Register (CH15_PRI) */
+#define S32K3XX_EDMA_TCD15_SADDR_OFFSET (0x20c020) /* TCD15 Source Address Register (TCD15_SADDR) */
+#define S32K3XX_EDMA_TCD15_SOFF_OFFSET (0x20c024) /* TCD15 Signed Source Address Offset Register (TCD15_SOFF) */
+#define S32K3XX_EDMA_TCD15_ATTR_OFFSET (0x20c026) /* TCD15 Transfer Attributes (TCD15_ATTR) */
+#define S32K3XX_EDMA_TCD15_NBYTES_OFFSET (0x20c028) /* TCD15 Transfer Size (TCD15_NBYTES) */
+#define S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET (0x20c02c) /* TCD15 Last Source Address Adjustment / Store DADDR Address Register (TCD15_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD15_DADDR_OFFSET (0x20c030) /* TCD15 Destination Address Register (TCD15_DADDR) */
+#define S32K3XX_EDMA_TCD15_DOFF_OFFSET (0x20c034) /* TCD15 Signed Destination Address Offset Register (TCD15_DOFF) */
+#define S32K3XX_EDMA_TCD15_CITER_OFFSET (0x20c036) /* TCD15 Current Major Loop Count Register (TCD15_CITER) */
+#define S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET (0x20c038) /* TCD15 Last Destination Address Adjustment / Scatter Gather Address Register (TCD15_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD15_CSR_OFFSET (0x20c03c) /* TCD15 Control and Status Register (TCD15_CSR) */
+#define S32K3XX_EDMA_TCD15_BITER_OFFSET (0x20c03e) /* TCD15 Beginning Major Loop Count Register (TCD15_BITER) */
+
+#define S32K3XX_EDMA_CH16_CSR_OFFSET (0x210000) /* Channel 16 Control and Status Register (CH16_CSR) */
+#define S32K3XX_EDMA_CH16_ES_OFFSET (0x210004) /* Channel 16 Error Status Register (CH16_ES) */
+#define S32K3XX_EDMA_CH16_INT_OFFSET (0x210008) /* Channel 16 Interrupt Status Register (CH16_INT) */
+#define S32K3XX_EDMA_CH16_SBR_OFFSET (0x21000c) /* Channel 16 System Bus Register (CH16_SBR) */
+#define S32K3XX_EDMA_CH16_PRI_OFFSET (0x210010) /* Channel 16 Priority Register (CH16_PRI) */
+#define S32K3XX_EDMA_TCD16_SADDR_OFFSET (0x210020) /* TCD16 Source Address Register (TCD16_SADDR) */
+#define S32K3XX_EDMA_TCD16_SOFF_OFFSET (0x210024) /* TCD16 Signed Source Address Offset Register (TCD16_SOFF) */
+#define S32K3XX_EDMA_TCD16_ATTR_OFFSET (0x210026) /* TCD16 Transfer Attributes (TCD16_ATTR) */
+#define S32K3XX_EDMA_TCD16_NBYTES_OFFSET (0x210028) /* TCD16 Transfer Size (TCD16_NBYTES) */
+#define S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET (0x21002c) /* TCD16 Last Source Address Adjustment / Store DADDR Address Register (TCD16_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD16_DADDR_OFFSET (0x210030) /* TCD16 Destination Address Register (TCD16_DADDR) */
+#define S32K3XX_EDMA_TCD16_DOFF_OFFSET (0x210034) /* TCD16 Signed Destination Address Offset Register (TCD16_DOFF) */
+#define S32K3XX_EDMA_TCD16_CITER_OFFSET (0x210036) /* TCD16 Current Major Loop Count Register (TCD16_CITER) */
+#define S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET (0x210038) /* TCD16 Last Destination Address Adjustment / Scatter Gather Address Register (TCD16_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD16_CSR_OFFSET (0x21003c) /* TCD16 Control and Status Register (TCD16_CSR) */
+#define S32K3XX_EDMA_TCD16_BITER_OFFSET (0x21003e) /* TCD16 Beginning Major Loop Count Register (TCD16_BITER) */
+
+#define S32K3XX_EDMA_CH17_CSR_OFFSET (0x214000) /* Channel 17 Control and Status Register (CH17_CSR) */
+#define S32K3XX_EDMA_CH17_ES_OFFSET (0x214004) /* Channel 17 Error Status Register (CH17_ES) */
+#define S32K3XX_EDMA_CH17_INT_OFFSET (0x214008) /* Channel 17 Interrupt Status Register (CH17_INT) */
+#define S32K3XX_EDMA_CH17_SBR_OFFSET (0x21400c) /* Channel 17 System Bus Register (CH17_SBR) */
+#define S32K3XX_EDMA_CH17_PRI_OFFSET (0x214010) /* Channel 17 Priority Register (CH17_PRI) */
+#define S32K3XX_EDMA_TCD17_SADDR_OFFSET (0x214020) /* TCD17 Source Address Register (TCD17_SADDR) */
+#define S32K3XX_EDMA_TCD17_SOFF_OFFSET (0x214024) /* TCD17 Signed Source Address Offset Register (TCD17_SOFF) */
+#define S32K3XX_EDMA_TCD17_ATTR_OFFSET (0x214026) /* TCD17 Transfer Attributes (TCD17_ATTR) */
+#define S32K3XX_EDMA_TCD17_NBYTES_OFFSET (0x214028) /* TCD17 Transfer Size (TCD17_NBYTES) */
+#define S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET (0x21402c) /* TCD17 Last Source Address Adjustment / Store DADDR Address Register (TCD17_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD17_DADDR_OFFSET (0x214030) /* TCD17 Destination Address Register (TCD17_DADDR) */
+#define S32K3XX_EDMA_TCD17_DOFF_OFFSET (0x214034) /* TCD17 Signed Destination Address Offset Register (TCD17_DOFF) */
+#define S32K3XX_EDMA_TCD17_CITER_OFFSET (0x214036) /* TCD17 Current Major Loop Count Register (TCD17_CITER) */
+#define S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET (0x214038) /* TCD17 Last Destination Address Adjustment / Scatter Gather Address Register (TCD17_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD17_CSR_OFFSET (0x21403c) /* TCD17 Control and Status Register (TCD17_CSR) */
+#define S32K3XX_EDMA_TCD17_BITER_OFFSET (0x21403e) /* TCD17 Beginning Major Loop Count Register (TCD17_BITER) */
+
+#define S32K3XX_EDMA_CH18_CSR_OFFSET (0x218000) /* Channel 18 Control and Status Register (CH18_CSR) */
+#define S32K3XX_EDMA_CH18_ES_OFFSET (0x218004) /* Channel 18 Error Status Register (CH18_ES) */
+#define S32K3XX_EDMA_CH18_INT_OFFSET (0x218008) /* Channel 18 Interrupt Status Register (CH18_INT) */
+#define S32K3XX_EDMA_CH18_SBR_OFFSET (0x21800c) /* Channel 18 System Bus Register (CH18_SBR) */
+#define S32K3XX_EDMA_CH18_PRI_OFFSET (0x218010) /* Channel 18 Priority Register (CH18_PRI) */
+#define S32K3XX_EDMA_TCD18_SADDR_OFFSET (0x218020) /* TCD18 Source Address Register (TCD18_SADDR) */
+#define S32K3XX_EDMA_TCD18_SOFF_OFFSET (0x218024) /* TCD18 Signed Source Address Offset Register (TCD18_SOFF) */
+#define S32K3XX_EDMA_TCD18_ATTR_OFFSET (0x218026) /* TCD18 Transfer Attributes (TCD18_ATTR) */
+#define S32K3XX_EDMA_TCD18_NBYTES_OFFSET (0x218028) /* TCD18 Transfer Size (TCD18_NBYTES) */
+#define S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET (0x21802c) /* TCD18 Last Source Address Adjustment / Store DADDR Address Register (TCD18_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD18_DADDR_OFFSET (0x218030) /* TCD18 Destination Address Register (TCD18_DADDR) */
+#define S32K3XX_EDMA_TCD18_DOFF_OFFSET (0x218034) /* TCD18 Signed Destination Address Offset Register (TCD18_DOFF) */
+#define S32K3XX_EDMA_TCD18_CITER_OFFSET (0x218036) /* TCD18 Current Major Loop Count Register (TCD18_CITER) */
+#define S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET (0x218038) /* TCD18 Last Destination Address Adjustment / Scatter Gather Address Register (TCD18_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD18_CSR_OFFSET (0x21803c) /* TCD18 Control and Status Register (TCD18_CSR) */
+#define S32K3XX_EDMA_TCD18_BITER_OFFSET (0x21803e) /* TCD18 Beginning Major Loop Count Register (TCD18_BITER) */
+
+#define S32K3XX_EDMA_CH19_CSR_OFFSET (0x21c000) /* Channel 19 Control and Status Register (CH19_CSR) */
+#define S32K3XX_EDMA_CH19_ES_OFFSET (0x21c004) /* Channel 19 Error Status Register (CH19_ES) */
+#define S32K3XX_EDMA_CH19_INT_OFFSET (0x21c008) /* Channel 19 Interrupt Status Register (CH19_INT) */
+#define S32K3XX_EDMA_CH19_SBR_OFFSET (0x21c00c) /* Channel 19 System Bus Register (CH19_SBR) */
+#define S32K3XX_EDMA_CH19_PRI_OFFSET (0x21c010) /* Channel 19 Priority Register (CH19_PRI) */
+#define S32K3XX_EDMA_TCD19_SADDR_OFFSET (0x21c020) /* TCD19 Source Address Register (TCD19_SADDR) */
+#define S32K3XX_EDMA_TCD19_SOFF_OFFSET (0x21c024) /* TCD19 Signed Source Address Offset Register (TCD19_SOFF) */
+#define S32K3XX_EDMA_TCD19_ATTR_OFFSET (0x21c026) /* TCD19 Transfer Attributes (TCD19_ATTR) */
+#define S32K3XX_EDMA_TCD19_NBYTES_OFFSET (0x21c028) /* TCD19 Transfer Size (TCD19_NBYTES) */
+#define S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET (0x21c02c) /* TCD19 Last Source Address Adjustment / Store DADDR Address Register (TCD19_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD19_DADDR_OFFSET (0x21c030) /* TCD19 Destination Address Register (TCD19_DADDR) */
+#define S32K3XX_EDMA_TCD19_DOFF_OFFSET (0x21c034) /* TCD19 Signed Destination Address Offset Register (TCD19_DOFF) */
+#define S32K3XX_EDMA_TCD19_CITER_OFFSET (0x21c036) /* TCD19 Current Major Loop Count Register (TCD19_CITER) */
+#define S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET (0x21c038) /* TCD19 Last Destination Address Adjustment / Scatter Gather Address Register (TCD19_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD19_CSR_OFFSET (0x21c03c) /* TCD19 Control and Status Register (TCD19_CSR) */
+#define S32K3XX_EDMA_TCD19_BITER_OFFSET (0x21c03e) /* TCD19 Beginning Major Loop Count Register (TCD19_BITER) */
+
+#define S32K3XX_EDMA_CH20_CSR_OFFSET (0x220000) /* Channel 20 Control and Status Register (CH20_CSR) */
+#define S32K3XX_EDMA_CH20_ES_OFFSET (0x220004) /* Channel 20 Error Status Register (CH20_ES) */
+#define S32K3XX_EDMA_CH20_INT_OFFSET (0x220008) /* Channel 20 Interrupt Status Register (CH20_INT) */
+#define S32K3XX_EDMA_CH20_SBR_OFFSET (0x22000c) /* Channel 20 System Bus Register (CH20_SBR) */
+#define S32K3XX_EDMA_CH20_PRI_OFFSET (0x220010) /* Channel 20 Priority Register (CH20_PRI) */
+#define S32K3XX_EDMA_TCD20_SADDR_OFFSET (0x220020) /* TCD20 Source Address Register (TCD20_SADDR) */
+#define S32K3XX_EDMA_TCD20_SOFF_OFFSET (0x220024) /* TCD20 Signed Source Address Offset Register (TCD20_SOFF) */
+#define S32K3XX_EDMA_TCD20_ATTR_OFFSET (0x220026) /* TCD20 Transfer Attributes (TCD20_ATTR) */
+#define S32K3XX_EDMA_TCD20_NBYTES_OFFSET (0x220028) /* TCD20 Transfer Size (TCD20_NBYTES) */
+#define S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET (0x22002c) /* TCD20 Last Source Address Adjustment / Store DADDR Address Register (TCD20_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD20_DADDR_OFFSET (0x220030) /* TCD20 Destination Address Register (TCD20_DADDR) */
+#define S32K3XX_EDMA_TCD20_DOFF_OFFSET (0x220034) /* TCD20 Signed Destination Address Offset Register (TCD20_DOFF) */
+#define S32K3XX_EDMA_TCD20_CITER_OFFSET (0x220036) /* TCD20 Current Major Loop Count Register (TCD20_CITER) */
+#define S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET (0x220038) /* TCD20 Last Destination Address Adjustment / Scatter Gather Address Register (TCD20_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD20_CSR_OFFSET (0x22003c) /* TCD20 Control and Status Register (TCD20_CSR) */
+#define S32K3XX_EDMA_TCD20_BITER_OFFSET (0x22003e) /* TCD20 Beginning Major Loop Count Register (TCD20_BITER) */
+
+#define S32K3XX_EDMA_CH21_CSR_OFFSET (0x224000) /* Channel 21 Control and Status Register (CH21_CSR) */
+#define S32K3XX_EDMA_CH21_ES_OFFSET (0x224004) /* Channel 21 Error Status Register (CH21_ES) */
+#define S32K3XX_EDMA_CH21_INT_OFFSET (0x224008) /* Channel 21 Interrupt Status Register (CH21_INT) */
+#define S32K3XX_EDMA_CH21_SBR_OFFSET (0x22400c) /* Channel 21 System Bus Register (CH21_SBR) */
+#define S32K3XX_EDMA_CH21_PRI_OFFSET (0x224010) /* Channel 21 Priority Register (CH21_PRI) */
+#define S32K3XX_EDMA_TCD21_SADDR_OFFSET (0x224020) /* TCD21 Source Address Register (TCD21_SADDR) */
+#define S32K3XX_EDMA_TCD21_SOFF_OFFSET (0x224024) /* TCD21 Signed Source Address Offset Register (TCD21_SOFF) */
+#define S32K3XX_EDMA_TCD21_ATTR_OFFSET (0x224026) /* TCD21 Transfer Attributes (TCD21_ATTR) */
+#define S32K3XX_EDMA_TCD21_NBYTES_OFFSET (0x224028) /* TCD21 Transfer Size (TCD21_NBYTES) */
+#define S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET (0x22402c) /* TCD21 Last Source Address Adjustment / Store DADDR Address Register (TCD21_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD21_DADDR_OFFSET (0x224030) /* TCD21 Destination Address Register (TCD21_DADDR) */
+#define S32K3XX_EDMA_TCD21_DOFF_OFFSET (0x224034) /* TCD21 Signed Destination Address Offset Register (TCD21_DOFF) */
+#define S32K3XX_EDMA_TCD21_CITER_OFFSET (0x224036) /* TCD21 Current Major Loop Count Register (TCD21_CITER) */
+#define S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET (0x224038) /* TCD21 Last Destination Address Adjustment / Scatter Gather Address Register (TCD21_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD21_CSR_OFFSET (0x22403c) /* TCD21 Control and Status Register (TCD21_CSR) */
+#define S32K3XX_EDMA_TCD21_BITER_OFFSET (0x22403e) /* TCD21 Beginning Major Loop Count Register (TCD21_BITER) */
+
+#define S32K3XX_EDMA_CH22_CSR_OFFSET (0x228000) /* Channel 22 Control and Status Register (CH22_CSR) */
+#define S32K3XX_EDMA_CH22_ES_OFFSET (0x228004) /* Channel 22 Error Status Register (CH22_ES) */
+#define S32K3XX_EDMA_CH22_INT_OFFSET (0x228008) /* Channel 22 Interrupt Status Register (CH22_INT) */
+#define S32K3XX_EDMA_CH22_SBR_OFFSET (0x22800c) /* Channel 22 System Bus Register (CH22_SBR) */
+#define S32K3XX_EDMA_CH22_PRI_OFFSET (0x228010) /* Channel 22 Priority Register (CH22_PRI) */
+#define S32K3XX_EDMA_TCD22_SADDR_OFFSET (0x228020) /* TCD22 Source Address Register (TCD22_SADDR) */
+#define S32K3XX_EDMA_TCD22_SOFF_OFFSET (0x228024) /* TCD22 Signed Source Address Offset Register (TCD22_SOFF) */
+#define S32K3XX_EDMA_TCD22_ATTR_OFFSET (0x228026) /* TCD22 Transfer Attributes (TCD22_ATTR) */
+#define S32K3XX_EDMA_TCD22_NBYTES_OFFSET (0x228028) /* TCD22 Transfer Size (TCD22_NBYTES) */
+#define S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET (0x22802c) /* TCD22 Last Source Address Adjustment / Store DADDR Address Register (TCD22_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD22_DADDR_OFFSET (0x228030) /* TCD22 Destination Address Register (TCD22_DADDR) */
+#define S32K3XX_EDMA_TCD22_DOFF_OFFSET (0x228034) /* TCD22 Signed Destination Address Offset Register (TCD22_DOFF) */
+#define S32K3XX_EDMA_TCD22_CITER_OFFSET (0x228036) /* TCD22 Current Major Loop Count Register (TCD22_CITER) */
+#define S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET (0x228038) /* TCD22 Last Destination Address Adjustment / Scatter Gather Address Register (TCD22_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD22_CSR_OFFSET (0x22803c) /* TCD22 Control and Status Register (TCD22_CSR) */
+#define S32K3XX_EDMA_TCD22_BITER_OFFSET (0x22803e) /* TCD22 Beginning Major Loop Count Register (TCD22_BITER) */
+
+#define S32K3XX_EDMA_CH23_CSR_OFFSET (0x22c000) /* Channel 23 Control and Status Register (CH23_CSR) */
+#define S32K3XX_EDMA_CH23_ES_OFFSET (0x22c004) /* Channel 23 Error Status Register (CH23_ES) */
+#define S32K3XX_EDMA_CH23_INT_OFFSET (0x22c008) /* Channel 23 Interrupt Status Register (CH23_INT) */
+#define S32K3XX_EDMA_CH23_SBR_OFFSET (0x22c00c) /* Channel 23 System Bus Register (CH23_SBR) */
+#define S32K3XX_EDMA_CH23_PRI_OFFSET (0x22c010) /* Channel 23 Priority Register (CH23_PRI) */
+#define S32K3XX_EDMA_TCD23_SADDR_OFFSET (0x22c020) /* TCD23 Source Address Register (TCD23_SADDR) */
+#define S32K3XX_EDMA_TCD23_SOFF_OFFSET (0x22c024) /* TCD23 Signed Source Address Offset Register (TCD23_SOFF) */
+#define S32K3XX_EDMA_TCD23_ATTR_OFFSET (0x22c026) /* TCD23 Transfer Attributes (TCD23_ATTR) */
+#define S32K3XX_EDMA_TCD23_NBYTES_OFFSET (0x22c028) /* TCD23 Transfer Size (TCD23_NBYTES) */
+#define S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET (0x22c02c) /* TCD23 Last Source Address Adjustment / Store DADDR Address Register (TCD23_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD23_DADDR_OFFSET (0x22c030) /* TCD23 Destination Address Register (TCD23_DADDR) */
+#define S32K3XX_EDMA_TCD23_DOFF_OFFSET (0x22c034) /* TCD23 Signed Destination Address Offset Register (TCD23_DOFF) */
+#define S32K3XX_EDMA_TCD23_CITER_OFFSET (0x22c036) /* TCD23 Current Major Loop Count Register (TCD23_CITER) */
+#define S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET (0x22c038) /* TCD23 Last Destination Address Adjustment / Scatter Gather Address Register (TCD23_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD23_CSR_OFFSET (0x22c03c) /* TCD23 Control and Status Register (TCD23_CSR) */
+#define S32K3XX_EDMA_TCD23_BITER_OFFSET (0x22c03e) /* TCD23 Beginning Major Loop Count Register (TCD23_BITER) */
+
+#define S32K3XX_EDMA_CH24_CSR_OFFSET (0x230000) /* Channel 24 Control and Status Register (CH24_CSR) */
+#define S32K3XX_EDMA_CH24_ES_OFFSET (0x230004) /* Channel 24 Error Status Register (CH24_ES) */
+#define S32K3XX_EDMA_CH24_INT_OFFSET (0x230008) /* Channel 24 Interrupt Status Register (CH24_INT) */
+#define S32K3XX_EDMA_CH24_SBR_OFFSET (0x23000c) /* Channel 24 System Bus Register (CH24_SBR) */
+#define S32K3XX_EDMA_CH24_PRI_OFFSET (0x230010) /* Channel 24 Priority Register (CH24_PRI) */
+#define S32K3XX_EDMA_TCD24_SADDR_OFFSET (0x230020) /* TCD24 Source Address Register (TCD24_SADDR) */
+#define S32K3XX_EDMA_TCD24_SOFF_OFFSET (0x230024) /* TCD24 Signed Source Address Offset Register (TCD24_SOFF) */
+#define S32K3XX_EDMA_TCD24_ATTR_OFFSET (0x230026) /* TCD24 Transfer Attributes (TCD24_ATTR) */
+#define S32K3XX_EDMA_TCD24_NBYTES_OFFSET (0x230028) /* TCD24 Transfer Size (TCD24_NBYTES) */
+#define S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET (0x23002c) /* TCD24 Last Source Address Adjustment / Store DADDR Address Register (TCD24_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD24_DADDR_OFFSET (0x230030) /* TCD24 Destination Address Register (TCD24_DADDR) */
+#define S32K3XX_EDMA_TCD24_DOFF_OFFSET (0x230034) /* TCD24 Signed Destination Address Offset Register (TCD24_DOFF) */
+#define S32K3XX_EDMA_TCD24_CITER_OFFSET (0x230036) /* TCD24 Current Major Loop Count Register (TCD24_CITER) */
+#define S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET (0x230038) /* TCD24 Last Destination Address Adjustment / Scatter Gather Address Register (TCD24_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD24_CSR_OFFSET (0x23003c) /* TCD24 Control and Status Register (TCD24_CSR) */
+#define S32K3XX_EDMA_TCD24_BITER_OFFSET (0x23003e) /* TCD24 Beginning Major Loop Count Register (TCD24_BITER) */
+
+#define S32K3XX_EDMA_CH25_CSR_OFFSET (0x234000) /* Channel 25 Control and Status Register (CH25_CSR) */
+#define S32K3XX_EDMA_CH25_ES_OFFSET (0x234004) /* Channel 25 Error Status Register (CH25_ES) */
+#define S32K3XX_EDMA_CH25_INT_OFFSET (0x234008) /* Channel 25 Interrupt Status Register (CH25_INT) */
+#define S32K3XX_EDMA_CH25_SBR_OFFSET (0x23400c) /* Channel 25 System Bus Register (CH25_SBR) */
+#define S32K3XX_EDMA_CH25_PRI_OFFSET (0x234010) /* Channel 25 Priority Register (CH25_PRI) */
+#define S32K3XX_EDMA_TCD25_SADDR_OFFSET (0x234020) /* TCD25 Source Address Register (TCD25_SADDR) */
+#define S32K3XX_EDMA_TCD25_SOFF_OFFSET (0x234024) /* TCD25 Signed Source Address Offset Register (TCD25_SOFF) */
+#define S32K3XX_EDMA_TCD25_ATTR_OFFSET (0x234026) /* TCD25 Transfer Attributes (TCD25_ATTR) */
+#define S32K3XX_EDMA_TCD25_NBYTES_OFFSET (0x234028) /* TCD25 Transfer Size (TCD25_NBYTES) */
+#define S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET (0x23402c) /* TCD25 Last Source Address Adjustment / Store DADDR Address Register (TCD25_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD25_DADDR_OFFSET (0x234030) /* TCD25 Destination Address Register (TCD25_DADDR) */
+#define S32K3XX_EDMA_TCD25_DOFF_OFFSET (0x234034) /* TCD25 Signed Destination Address Offset Register (TCD25_DOFF) */
+#define S32K3XX_EDMA_TCD25_CITER_OFFSET (0x234036) /* TCD25 Current Major Loop Count Register (TCD25_CITER) */
+#define S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET (0x234038) /* TCD25 Last Destination Address Adjustment / Scatter Gather Address Register (TCD25_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD25_CSR_OFFSET (0x23403c) /* TCD25 Control and Status Register (TCD25_CSR) */
+#define S32K3XX_EDMA_TCD25_BITER_OFFSET (0x23403e) /* TCD25 Beginning Major Loop Count Register (TCD25_BITER) */
+
+#define S32K3XX_EDMA_CH26_CSR_OFFSET (0x238000) /* Channel 26 Control and Status Register (CH26_CSR) */
+#define S32K3XX_EDMA_CH26_ES_OFFSET (0x238004) /* Channel 26 Error Status Register (CH26_ES) */
+#define S32K3XX_EDMA_CH26_INT_OFFSET (0x238008) /* Channel 26 Interrupt Status Register (CH26_INT) */
+#define S32K3XX_EDMA_CH26_SBR_OFFSET (0x23800c) /* Channel 26 System Bus Register (CH26_SBR) */
+#define S32K3XX_EDMA_CH26_PRI_OFFSET (0x238010) /* Channel 26 Priority Register (CH26_PRI) */
+#define S32K3XX_EDMA_TCD26_SADDR_OFFSET (0x238020) /* TCD26 Source Address Register (TCD26_SADDR) */
+#define S32K3XX_EDMA_TCD26_SOFF_OFFSET (0x238024) /* TCD26 Signed Source Address Offset Register (TCD26_SOFF) */
+#define S32K3XX_EDMA_TCD26_ATTR_OFFSET (0x238026) /* TCD26 Transfer Attributes (TCD26_ATTR) */
+#define S32K3XX_EDMA_TCD26_NBYTES_OFFSET (0x238028) /* TCD26 Transfer Size (TCD26_NBYTES) */
+#define S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET (0x23802c) /* TCD26 Last Source Address Adjustment / Store DADDR Address Register (TCD26_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD26_DADDR_OFFSET (0x238030) /* TCD26 Destination Address Register (TCD26_DADDR) */
+#define S32K3XX_EDMA_TCD26_DOFF_OFFSET (0x238034) /* TCD26 Signed Destination Address Offset Register (TCD26_DOFF) */
+#define S32K3XX_EDMA_TCD26_CITER_OFFSET (0x238036) /* TCD26 Current Major Loop Count Register (TCD26_CITER) */
+#define S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET (0x238038) /* TCD26 Last Destination Address Adjustment / Scatter Gather Address Register (TCD26_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD26_CSR_OFFSET (0x23803c) /* TCD26 Control and Status Register (TCD26_CSR) */
+#define S32K3XX_EDMA_TCD26_BITER_OFFSET (0x23803e) /* TCD26 Beginning Major Loop Count Register (TCD26_BITER) */
+
+#define S32K3XX_EDMA_CH27_CSR_OFFSET (0x23c000) /* Channel 27 Control and Status Register (CH27_CSR) */
+#define S32K3XX_EDMA_CH27_ES_OFFSET (0x23c004) /* Channel 27 Error Status Register (CH27_ES) */
+#define S32K3XX_EDMA_CH27_INT_OFFSET (0x23c008) /* Channel 27 Interrupt Status Register (CH27_INT) */
+#define S32K3XX_EDMA_CH27_SBR_OFFSET (0x23c00c) /* Channel 27 System Bus Register (CH27_SBR) */
+#define S32K3XX_EDMA_CH27_PRI_OFFSET (0x23c010) /* Channel 27 Priority Register (CH27_PRI) */
+#define S32K3XX_EDMA_TCD27_SADDR_OFFSET (0x23c020) /* TCD27 Source Address Register (TCD27_SADDR) */
+#define S32K3XX_EDMA_TCD27_SOFF_OFFSET (0x23c024) /* TCD27 Signed Source Address Offset Register (TCD27_SOFF) */
+#define S32K3XX_EDMA_TCD27_ATTR_OFFSET (0x23c026) /* TCD27 Transfer Attributes (TCD27_ATTR) */
+#define S32K3XX_EDMA_TCD27_NBYTES_OFFSET (0x23c028) /* TCD27 Transfer Size (TCD27_NBYTES) */
+#define S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET (0x23c02c) /* TCD27 Last Source Address Adjustment / Store DADDR Address Register (TCD27_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD27_DADDR_OFFSET (0x23c030) /* TCD27 Destination Address Register (TCD27_DADDR) */
+#define S32K3XX_EDMA_TCD27_DOFF_OFFSET (0x23c034) /* TCD27 Signed Destination Address Offset Register (TCD27_DOFF) */
+#define S32K3XX_EDMA_TCD27_CITER_OFFSET (0x23c036) /* TCD27 Current Major Loop Count Register (TCD27_CITER) */
+#define S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET (0x23c038) /* TCD27 Last Destination Address Adjustment / Scatter Gather Address Register (TCD27_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD27_CSR_OFFSET (0x23c03c) /* TCD27 Control and Status Register (TCD27_CSR) */
+#define S32K3XX_EDMA_TCD27_BITER_OFFSET (0x23c03e) /* TCD27 Beginning Major Loop Count Register (TCD27_BITER) */
+
+#define S32K3XX_EDMA_CH28_CSR_OFFSET (0x240000) /* Channel 28 Control and Status Register (CH28_CSR) */
+#define S32K3XX_EDMA_CH28_ES_OFFSET (0x240004) /* Channel 28 Error Status Register (CH28_ES) */
+#define S32K3XX_EDMA_CH28_INT_OFFSET (0x240008) /* Channel 28 Interrupt Status Register (CH28_INT) */
+#define S32K3XX_EDMA_CH28_SBR_OFFSET (0x24000c) /* Channel 28 System Bus Register (CH28_SBR) */
+#define S32K3XX_EDMA_CH28_PRI_OFFSET (0x240010) /* Channel 28 Priority Register (CH28_PRI) */
+#define S32K3XX_EDMA_TCD28_SADDR_OFFSET (0x240020) /* TCD28 Source Address Register (TCD28_SADDR) */
+#define S32K3XX_EDMA_TCD28_SOFF_OFFSET (0x240024) /* TCD28 Signed Source Address Offset Register (TCD28_SOFF) */
+#define S32K3XX_EDMA_TCD28_ATTR_OFFSET (0x240026) /* TCD28 Transfer Attributes (TCD28_ATTR) */
+#define S32K3XX_EDMA_TCD28_NBYTES_OFFSET (0x240028) /* TCD28 Transfer Size (TCD28_NBYTES) */
+#define S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET (0x24002c) /* TCD28 Last Source Address Adjustment / Store DADDR Address Register (TCD28_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD28_DADDR_OFFSET (0x240030) /* TCD28 Destination Address Register (TCD28_DADDR) */
+#define S32K3XX_EDMA_TCD28_DOFF_OFFSET (0x240034) /* TCD28 Signed Destination Address Offset Register (TCD28_DOFF) */
+#define S32K3XX_EDMA_TCD28_CITER_OFFSET (0x240036) /* TCD28 Current Major Loop Count Register (TCD28_CITER) */
+#define S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET (0x240038) /* TCD28 Last Destination Address Adjustment / Scatter Gather Address Register (TCD28_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD28_CSR_OFFSET (0x24003c) /* TCD28 Control and Status Register (TCD28_CSR) */
+#define S32K3XX_EDMA_TCD28_BITER_OFFSET (0x24003e) /* TCD28 Beginning Major Loop Count Register (TCD28_BITER) */
+
+#define S32K3XX_EDMA_CH29_CSR_OFFSET (0x244000) /* Channel 29 Control and Status Register (CH29_CSR) */
+#define S32K3XX_EDMA_CH29_ES_OFFSET (0x244004) /* Channel 29 Error Status Register (CH29_ES) */
+#define S32K3XX_EDMA_CH29_INT_OFFSET (0x244008) /* Channel 29 Interrupt Status Register (CH29_INT) */
+#define S32K3XX_EDMA_CH29_SBR_OFFSET (0x24400c) /* Channel 29 System Bus Register (CH29_SBR) */
+#define S32K3XX_EDMA_CH29_PRI_OFFSET (0x244010) /* Channel 29 Priority Register (CH29_PRI) */
+#define S32K3XX_EDMA_TCD29_SADDR_OFFSET (0x244020) /* TCD29 Source Address Register (TCD29_SADDR) */
+#define S32K3XX_EDMA_TCD29_SOFF_OFFSET (0x244024) /* TCD29 Signed Source Address Offset Register (TCD29_SOFF) */
+#define S32K3XX_EDMA_TCD29_ATTR_OFFSET (0x244026) /* TCD29 Transfer Attributes (TCD29_ATTR) */
+#define S32K3XX_EDMA_TCD29_NBYTES_OFFSET (0x244028) /* TCD29 Transfer Size (TCD29_NBYTES) */
+#define S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET (0x24402c) /* TCD29 Last Source Address Adjustment / Store DADDR Address Register (TCD29_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD29_DADDR_OFFSET (0x244030) /* TCD29 Destination Address Register (TCD29_DADDR) */
+#define S32K3XX_EDMA_TCD29_DOFF_OFFSET (0x244034) /* TCD29 Signed Destination Address Offset Register (TCD29_DOFF) */
+#define S32K3XX_EDMA_TCD29_CITER_OFFSET (0x244036) /* TCD29 Current Major Loop Count Register (TCD29_CITER) */
+#define S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET (0x244038) /* TCD29 Last Destination Address Adjustment / Scatter Gather Address Register (TCD29_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD29_CSR_OFFSET (0x24403c) /* TCD29 Control and Status Register (TCD29_CSR) */
+#define S32K3XX_EDMA_TCD29_BITER_OFFSET (0x24403e) /* TCD29 Beginning Major Loop Count Register (TCD29_BITER) */
+
+#define S32K3XX_EDMA_CH30_CSR_OFFSET (0x248000) /* Channel 30 Control and Status Register (CH30_CSR) */
+#define S32K3XX_EDMA_CH30_ES_OFFSET (0x248004) /* Channel 30 Error Status Register (CH30_ES) */
+#define S32K3XX_EDMA_CH30_INT_OFFSET (0x248008) /* Channel 30 Interrupt Status Register (CH30_INT) */
+#define S32K3XX_EDMA_CH30_SBR_OFFSET (0x24800c) /* Channel 30 System Bus Register (CH30_SBR) */
+#define S32K3XX_EDMA_CH30_PRI_OFFSET (0x248010) /* Channel 30 Priority Register (CH30_PRI) */
+#define S32K3XX_EDMA_TCD30_SADDR_OFFSET (0x248020) /* TCD30 Source Address Register (TCD30_SADDR) */
+#define S32K3XX_EDMA_TCD30_SOFF_OFFSET (0x248024) /* TCD30 Signed Source Address Offset Register (TCD30_SOFF) */
+#define S32K3XX_EDMA_TCD30_ATTR_OFFSET (0x248026) /* TCD30 Transfer Attributes (TCD30_ATTR) */
+#define S32K3XX_EDMA_TCD30_NBYTES_OFFSET (0x248028) /* TCD30 Transfer Size (TCD30_NBYTES) */
+#define S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET (0x24802c) /* TCD30 Last Source Address Adjustment / Store DADDR Address Register (TCD30_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD30_DADDR_OFFSET (0x248030) /* TCD30 Destination Address Register (TCD30_DADDR) */
+#define S32K3XX_EDMA_TCD30_DOFF_OFFSET (0x248034) /* TCD30 Signed Destination Address Offset Register (TCD30_DOFF) */
+#define S32K3XX_EDMA_TCD30_CITER_OFFSET (0x248036) /* TCD30 Current Major Loop Count Register (TCD30_CITER) */
+#define S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET (0x248038) /* TCD30 Last Destination Address Adjustment / Scatter Gather Address Register (TCD30_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD30_CSR_OFFSET (0x24803c) /* TCD30 Control and Status Register (TCD30_CSR) */
+#define S32K3XX_EDMA_TCD30_BITER_OFFSET (0x24803e) /* TCD30 Beginning Major Loop Count Register (TCD30_BITER) */
+
+#define S32K3XX_EDMA_CH31_CSR_OFFSET (0x24c000) /* Channel 31 Control and Status Register (CH31_CSR) */
+#define S32K3XX_EDMA_CH31_ES_OFFSET (0x24c004) /* Channel 31 Error Status Register (CH31_ES) */
+#define S32K3XX_EDMA_CH31_INT_OFFSET (0x24c008) /* Channel 31 Interrupt Status Register (CH31_INT) */
+#define S32K3XX_EDMA_CH31_SBR_OFFSET (0x24c00c) /* Channel 31 System Bus Register (CH31_SBR) */
+#define S32K3XX_EDMA_CH31_PRI_OFFSET (0x24c010) /* Channel 31 Priority Register (CH31_PRI) */
+#define S32K3XX_EDMA_TCD31_SADDR_OFFSET (0x24c020) /* TCD31 Source Address Register (TCD31_SADDR) */
+#define S32K3XX_EDMA_TCD31_SOFF_OFFSET (0x24c024) /* TCD31 Signed Source Address Offset Register (TCD31_SOFF) */
+#define S32K3XX_EDMA_TCD31_ATTR_OFFSET (0x24c026) /* TCD31 Transfer Attributes (TCD31_ATTR) */
+#define S32K3XX_EDMA_TCD31_NBYTES_OFFSET (0x24c028) /* TCD31 Transfer Size (TCD31_NBYTES) */
+#define S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET (0x24c02c) /* TCD31 Last Source Address Adjustment / Store DADDR Address Register (TCD31_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD31_DADDR_OFFSET (0x24c030) /* TCD31 Destination Address Register (TCD31_DADDR) */
+#define S32K3XX_EDMA_TCD31_DOFF_OFFSET (0x24c034) /* TCD31 Signed Destination Address Offset Register (TCD31_DOFF) */
+#define S32K3XX_EDMA_TCD31_CITER_OFFSET (0x24c036) /* TCD31 Current Major Loop Count Register (TCD31_CITER) */
+#define S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET (0x24c038) /* TCD31 Last Destination Address Adjustment / Scatter Gather Address Register (TCD31_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD31_CSR_OFFSET (0x24c03c) /* TCD31 Control and Status Register (TCD31_CSR) */
+#define S32K3XX_EDMA_TCD31_BITER_OFFSET (0x24c03e) /* TCD31 Beginning Major Loop Count Register (TCD31_BITER) */
+
+/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/
+
+#define S32K3XX_EDMA_CH0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_CSR_OFFSET)
+#define S32K3XX_EDMA_CH0_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_ES_OFFSET)
+#define S32K3XX_EDMA_CH0_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_INT_OFFSET)
+#define S32K3XX_EDMA_CH0_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_SBR_OFFSET)
+#define S32K3XX_EDMA_CH0_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD0_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD0_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD0_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD0_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD0_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD0_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_CSR_OFFSET)
+#define S32K3XX_EDMA_CH1_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_ES_OFFSET)
+#define S32K3XX_EDMA_CH1_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_INT_OFFSET)
+#define S32K3XX_EDMA_CH1_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_SBR_OFFSET)
+#define S32K3XX_EDMA_CH1_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD1_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD1_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD1_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD1_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD1_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD1_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_CSR_OFFSET)
+#define S32K3XX_EDMA_CH2_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_ES_OFFSET)
+#define S32K3XX_EDMA_CH2_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_INT_OFFSET)
+#define S32K3XX_EDMA_CH2_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_SBR_OFFSET)
+#define S32K3XX_EDMA_CH2_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD2_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD2_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD2_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD2_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD2_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD2_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_CSR_OFFSET)
+#define S32K3XX_EDMA_CH3_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_ES_OFFSET)
+#define S32K3XX_EDMA_CH3_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_INT_OFFSET)
+#define S32K3XX_EDMA_CH3_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_SBR_OFFSET)
+#define S32K3XX_EDMA_CH3_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD3_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD3_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD3_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD3_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD3_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD3_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_CSR_OFFSET)
+#define S32K3XX_EDMA_CH4_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_ES_OFFSET)
+#define S32K3XX_EDMA_CH4_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_INT_OFFSET)
+#define S32K3XX_EDMA_CH4_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_SBR_OFFSET)
+#define S32K3XX_EDMA_CH4_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD4_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD4_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD4_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD4_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD4_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD4_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_CSR_OFFSET)
+#define S32K3XX_EDMA_CH5_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_ES_OFFSET)
+#define S32K3XX_EDMA_CH5_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_INT_OFFSET)
+#define S32K3XX_EDMA_CH5_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_SBR_OFFSET)
+#define S32K3XX_EDMA_CH5_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD5_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD5_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD5_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD5_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD5_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD5_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_CSR_OFFSET)
+#define S32K3XX_EDMA_CH6_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_ES_OFFSET)
+#define S32K3XX_EDMA_CH6_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_INT_OFFSET)
+#define S32K3XX_EDMA_CH6_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_SBR_OFFSET)
+#define S32K3XX_EDMA_CH6_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD6_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD6_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD6_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD6_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD6_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD6_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_CSR_OFFSET)
+#define S32K3XX_EDMA_CH7_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_ES_OFFSET)
+#define S32K3XX_EDMA_CH7_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_INT_OFFSET)
+#define S32K3XX_EDMA_CH7_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_SBR_OFFSET)
+#define S32K3XX_EDMA_CH7_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD7_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD7_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD7_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD7_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD7_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD7_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_CSR_OFFSET)
+#define S32K3XX_EDMA_CH8_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_ES_OFFSET)
+#define S32K3XX_EDMA_CH8_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_INT_OFFSET)
+#define S32K3XX_EDMA_CH8_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_SBR_OFFSET)
+#define S32K3XX_EDMA_CH8_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD8_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD8_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD8_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD8_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD8_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD8_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_CSR_OFFSET)
+#define S32K3XX_EDMA_CH9_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_ES_OFFSET)
+#define S32K3XX_EDMA_CH9_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_INT_OFFSET)
+#define S32K3XX_EDMA_CH9_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_SBR_OFFSET)
+#define S32K3XX_EDMA_CH9_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD9_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD9_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD9_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD9_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD9_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD9_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_CSR_OFFSET)
+#define S32K3XX_EDMA_CH10_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_ES_OFFSET)
+#define S32K3XX_EDMA_CH10_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_INT_OFFSET)
+#define S32K3XX_EDMA_CH10_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_SBR_OFFSET)
+#define S32K3XX_EDMA_CH10_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD10_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD10_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD10_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD10_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD10_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD10_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_CSR_OFFSET)
+#define S32K3XX_EDMA_CH11_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_ES_OFFSET)
+#define S32K3XX_EDMA_CH11_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_INT_OFFSET)
+#define S32K3XX_EDMA_CH11_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_SBR_OFFSET)
+#define S32K3XX_EDMA_CH11_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD11_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD11_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD11_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD11_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD11_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD11_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_CSR_OFFSET)
+#define S32K3XX_EDMA_CH12_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_ES_OFFSET)
+#define S32K3XX_EDMA_CH12_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_INT_OFFSET)
+#define S32K3XX_EDMA_CH12_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_SBR_OFFSET)
+#define S32K3XX_EDMA_CH12_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD12_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD12_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD12_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD12_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD12_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD12_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_CSR_OFFSET)
+#define S32K3XX_EDMA_CH13_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_ES_OFFSET)
+#define S32K3XX_EDMA_CH13_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_INT_OFFSET)
+#define S32K3XX_EDMA_CH13_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_SBR_OFFSET)
+#define S32K3XX_EDMA_CH13_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD13_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD13_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD13_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD13_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD13_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD13_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_CSR_OFFSET)
+#define S32K3XX_EDMA_CH14_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_ES_OFFSET)
+#define S32K3XX_EDMA_CH14_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_INT_OFFSET)
+#define S32K3XX_EDMA_CH14_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_SBR_OFFSET)
+#define S32K3XX_EDMA_CH14_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD14_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD14_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD14_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD14_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD14_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD14_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_CSR_OFFSET)
+#define S32K3XX_EDMA_CH15_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_ES_OFFSET)
+#define S32K3XX_EDMA_CH15_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_INT_OFFSET)
+#define S32K3XX_EDMA_CH15_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_SBR_OFFSET)
+#define S32K3XX_EDMA_CH15_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD15_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD15_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD15_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD15_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD15_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD15_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_CSR_OFFSET)
+#define S32K3XX_EDMA_CH16_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_ES_OFFSET)
+#define S32K3XX_EDMA_CH16_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_INT_OFFSET)
+#define S32K3XX_EDMA_CH16_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_SBR_OFFSET)
+#define S32K3XX_EDMA_CH16_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD16_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD16_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD16_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD16_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD16_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD16_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_CSR_OFFSET)
+#define S32K3XX_EDMA_CH17_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_ES_OFFSET)
+#define S32K3XX_EDMA_CH17_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_INT_OFFSET)
+#define S32K3XX_EDMA_CH17_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_SBR_OFFSET)
+#define S32K3XX_EDMA_CH17_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD17_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD17_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD17_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD17_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD17_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD17_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_CSR_OFFSET)
+#define S32K3XX_EDMA_CH18_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_ES_OFFSET)
+#define S32K3XX_EDMA_CH18_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_INT_OFFSET)
+#define S32K3XX_EDMA_CH18_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_SBR_OFFSET)
+#define S32K3XX_EDMA_CH18_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD18_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD18_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD18_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD18_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD18_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD18_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_CSR_OFFSET)
+#define S32K3XX_EDMA_CH19_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_ES_OFFSET)
+#define S32K3XX_EDMA_CH19_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_INT_OFFSET)
+#define S32K3XX_EDMA_CH19_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_SBR_OFFSET)
+#define S32K3XX_EDMA_CH19_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD19_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD19_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD19_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD19_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD19_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD19_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_CSR_OFFSET)
+#define S32K3XX_EDMA_CH20_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_ES_OFFSET)
+#define S32K3XX_EDMA_CH20_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_INT_OFFSET)
+#define S32K3XX_EDMA_CH20_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_SBR_OFFSET)
+#define S32K3XX_EDMA_CH20_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD20_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD20_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD20_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD20_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD20_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD20_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_CSR_OFFSET)
+#define S32K3XX_EDMA_CH21_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_ES_OFFSET)
+#define S32K3XX_EDMA_CH21_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_INT_OFFSET)
+#define S32K3XX_EDMA_CH21_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_SBR_OFFSET)
+#define S32K3XX_EDMA_CH21_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD21_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD21_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD21_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD21_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD21_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD21_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_CSR_OFFSET)
+#define S32K3XX_EDMA_CH22_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_ES_OFFSET)
+#define S32K3XX_EDMA_CH22_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_INT_OFFSET)
+#define S32K3XX_EDMA_CH22_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_SBR_OFFSET)
+#define S32K3XX_EDMA_CH22_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD22_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD22_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD22_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD22_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD22_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD22_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_CSR_OFFSET)
+#define S32K3XX_EDMA_CH23_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_ES_OFFSET)
+#define S32K3XX_EDMA_CH23_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_INT_OFFSET)
+#define S32K3XX_EDMA_CH23_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_SBR_OFFSET)
+#define S32K3XX_EDMA_CH23_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD23_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD23_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD23_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD23_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD23_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD23_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_CSR_OFFSET)
+#define S32K3XX_EDMA_CH24_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_ES_OFFSET)
+#define S32K3XX_EDMA_CH24_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_INT_OFFSET)
+#define S32K3XX_EDMA_CH24_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_SBR_OFFSET)
+#define S32K3XX_EDMA_CH24_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD24_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD24_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD24_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD24_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD24_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD24_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_CSR_OFFSET)
+#define S32K3XX_EDMA_CH25_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_ES_OFFSET)
+#define S32K3XX_EDMA_CH25_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_INT_OFFSET)
+#define S32K3XX_EDMA_CH25_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_SBR_OFFSET)
+#define S32K3XX_EDMA_CH25_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD25_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD25_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD25_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD25_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD25_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD25_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_CSR_OFFSET)
+#define S32K3XX_EDMA_CH26_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_ES_OFFSET)
+#define S32K3XX_EDMA_CH26_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_INT_OFFSET)
+#define S32K3XX_EDMA_CH26_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_SBR_OFFSET)
+#define S32K3XX_EDMA_CH26_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD26_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD26_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD26_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD26_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD26_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD26_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_CSR_OFFSET)
+#define S32K3XX_EDMA_CH27_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_ES_OFFSET)
+#define S32K3XX_EDMA_CH27_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_INT_OFFSET)
+#define S32K3XX_EDMA_CH27_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_SBR_OFFSET)
+#define S32K3XX_EDMA_CH27_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD27_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD27_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD27_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD27_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD27_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD27_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_CSR_OFFSET)
+#define S32K3XX_EDMA_CH28_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_ES_OFFSET)
+#define S32K3XX_EDMA_CH28_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_INT_OFFSET)
+#define S32K3XX_EDMA_CH28_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_SBR_OFFSET)
+#define S32K3XX_EDMA_CH28_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD28_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD28_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD28_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD28_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD28_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD28_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_CSR_OFFSET)
+#define S32K3XX_EDMA_CH29_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_ES_OFFSET)
+#define S32K3XX_EDMA_CH29_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_INT_OFFSET)
+#define S32K3XX_EDMA_CH29_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_SBR_OFFSET)
+#define S32K3XX_EDMA_CH29_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD29_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD29_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD29_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD29_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD29_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD29_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_CSR_OFFSET)
+#define S32K3XX_EDMA_CH30_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_ES_OFFSET)
+#define S32K3XX_EDMA_CH30_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_INT_OFFSET)
+#define S32K3XX_EDMA_CH30_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_SBR_OFFSET)
+#define S32K3XX_EDMA_CH30_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD30_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD30_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD30_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD30_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD30_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD30_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_CSR_OFFSET)
+#define S32K3XX_EDMA_CH31_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_ES_OFFSET)
+#define S32K3XX_EDMA_CH31_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_INT_OFFSET)
+#define S32K3XX_EDMA_CH31_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_SBR_OFFSET)
+#define S32K3XX_EDMA_CH31_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD31_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD31_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD31_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD31_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD31_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD31_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_BITER_OFFSET)
+
+uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
+{
+ S32K3XX_EDMA_CH0_CSR,
+ S32K3XX_EDMA_CH1_CSR,
+ S32K3XX_EDMA_CH2_CSR,
+ S32K3XX_EDMA_CH3_CSR,
+ S32K3XX_EDMA_CH4_CSR,
+ S32K3XX_EDMA_CH5_CSR,
+ S32K3XX_EDMA_CH6_CSR,
+ S32K3XX_EDMA_CH7_CSR,
+ S32K3XX_EDMA_CH8_CSR,
+ S32K3XX_EDMA_CH9_CSR,
+ S32K3XX_EDMA_CH10_CSR,
+ S32K3XX_EDMA_CH11_CSR,
+ S32K3XX_EDMA_CH12_CSR,
+ S32K3XX_EDMA_CH13_CSR,
+ S32K3XX_EDMA_CH14_CSR,
+ S32K3XX_EDMA_CH15_CSR,
+ S32K3XX_EDMA_CH16_CSR,
+ S32K3XX_EDMA_CH17_CSR,
+ S32K3XX_EDMA_CH18_CSR,
+ S32K3XX_EDMA_CH19_CSR,
+ S32K3XX_EDMA_CH20_CSR,
+ S32K3XX_EDMA_CH21_CSR,
+ S32K3XX_EDMA_CH22_CSR,
+ S32K3XX_EDMA_CH23_CSR,
+ S32K3XX_EDMA_CH24_CSR,
+ S32K3XX_EDMA_CH25_CSR,
+ S32K3XX_EDMA_CH26_CSR,
+ S32K3XX_EDMA_CH27_CSR,
+ S32K3XX_EDMA_CH28_CSR,
+ S32K3XX_EDMA_CH29_CSR,
+ S32K3XX_EDMA_CH30_CSR,
+ S32K3XX_EDMA_CH31_CSR
+};
+
+/* eDMA Register Bitfield Definitions ***************************************/
+
+/* Management Page Control Register (CSR) */
+
+ /* Bit 0: Reserved */
+#define EDMA_CSR_EDBG (1 << 1) /* Bit 1: Enable Debug (EDBG) */
+#define EDMA_CSR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration (ERCA) */
+ /* Bit 3: Reserved */
+#define EDMA_CSR_HAE (1 << 4) /* Bit 4: Halt After Error (HAE) */
+#define EDMA_CSR_HALT (1 << 5) /* Bit 5: Halt DMA Operations (HALT) */
+#define EDMA_CSR_GCLC (1 << 6) /* Bit 6: Global Channel Linking Control (GCLC) */
+#define EDMA_CSR_GMRC (1 << 7) /* Bit 7: Global Master ID Replication Control (GMRC) */
+#define EDMA_CSR_ECX (1 << 8) /* Bit 8: Cancel Transfer With Error (ECX) */
+#define EDMA_CSR_CX (1 << 9) /* Bit 9: Cancel Transfer (CX) */
+ /* Bits 10-23: Reserved */
+#define EDMA_CSR_ACTIVE_ID_SHIFT (24) /* Bits 24-28: Active Channel ID (ACTIVE_ID) */
+#define EDMA_CSR_ACTIVE_ID_MASK (0x1f << EDMA_CSR_ACTIVE_ID_SHIFT)
+ /* Bits 29-30: Reserved */
+#define EDMA_CSR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status (ACTIVE) */
+
+/* Management Page Error Status Register (ES) */
+
+#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
+#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
+#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
+#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
+#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
+#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
+#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
+#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
+#define EDMA_ES_ECX (1 << 8) /* Bit 8: Transfer Canceled (ECX) */
+#define EDMA_ES_UCE (1 << 9) /* Bit 9: Uncorrectable TCD Error During Channel Execution (UCE) */
+ /* Bits 10-23: Reserved */
+#define EDMA_ES_ERRCHN_SHIFT (8) /* Bits 24-28: Error Channel Number or Canceled Channel Number (ERRCHN) */
+#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT)
+ /* Bits 29-30: Reserved */
+#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status fields (VALID) */
+
+/* Management Page Interrupt Request Status Register (INT) */
+
+#define EDMA_INT(n) (1 << (n)) /* Bit n: Interrupt Request Status (INT) */
+
+/* Management Page Hardware Request Status Register (HRS) */
+
+#define EDMA_HRS(n) (1 << (n)) /* Bit n: Hardware Request Status (HRS) */
+
+/* Channel n Arbitration Group Register (CHn_GRPRI) */
+
+#define EDMA_CH_GRPRI_SHIFT (0) /* Bits 0-4: Arbitration Group For Channel n (GRPRI) */
+#define EDMA_CH_GRPRI_MASK (0x1f << EDMA_CH_GRPRI_SHIFT)
+ /* Bits 5-31: Reserved */
+
+/* eDMA Transfer Control Descriptor (TCD) Bitfield Definitions **************/
+
+/* Channel n Control and Status Register (CHn_CSR) */
+
+#define EDMA_CH_CSR_ERQ (1 << 0) /* Bit 0: Enable DMA Request (ERQ) */
+#define EDMA_CH_CSR_EARQ (1 << 1) /* Bit 1: Enable Asynchronous DMA Request in Stop Mode for Channel (EARQ) */
+#define EDMA_CH_CSR_EEI (1 << 2) /* Bit 2: Enable Error Interrupt (EEI) */
+#define EDMA_CH_CSR_EBW (1 << 3) /* Bit 3: Enable Buffered Writes (EBW) */
+ /* Bit 4-29: Reserved */
+#define EDMA_CH_CSR_DONE (1 << 30) /* Bit 30: Channel Done (DONE) */
+#define EDMA_CH_CSR_ACTIVE (1 << 31) /* Bit 31: CHannel Active (ACTIVE) */
+
+/* Channel n Error Status Register (CHn_ES) */
+
+#define EDMA_CH_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
+#define EDMA_CH_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
+#define EDMA_CH_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
+#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
+#define EDMA_CH_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
+#define EDMA_CH_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
+#define EDMA_CH_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
+#define EDMA_CH_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
+ /* Bit 8-30: Reserved */
+#define EDMA_CH_ES_ERR (1 << 31) /* Bit 31: Error in this channel (ERR) */
+
+/* Channel n Interrupt Status Register (CHn_INT) */
+
+#define EDMA_CH_INT (1 << 0) /* Bit 0: Interrupt Request (INT) */
+ /* Bits 1-31: Reserved */
+
+/* Channel n System Bus Register (CHn_SBR) */
+
+#define EDMA_CH_SBR_MID_SHIFT (0) /* Bits 0-3: Master ID (MID) */
+#define EDMA_CH_SBR_MID_MASK (0x0f << EDMA_CH_SBR_MID_SHIFT)
+ /* Bits 4-14: Reserved */
+#define EDMA_CH_SBR_PAL (1 << 15) /* Bit 15: Privileged Access Level (PAL) */
+#define EDMA_CH_SBR_EMI (1 << 16) /* Bit 16: Enable Master ID Replication (EMI) */
+#define EDMA_CH_SBR_ATTR_SHIFT (17) /* Bits 17-19: Attribute Output (ATTR) */
+#define EDMA_CH_SBR_ATTR_MASK (0x07 << EDMA_CH_SBR_ATTR_SHIFT)
+ /* Bits 20-31: Reserved */
+
+/* Channel n Priority Register (CHn_PRI) */
+
+#define EDMA_CH_PRI_APL_SHIFT (0) /* Bits 0-2: Arbitration Priority Level (APL) */
+#define EDMA_CH_PRI_APL_MASK (0x07 << EDMA_CH_PRI_APL_SHIFT)
+ /* Bits 3-29: Reserved */
+#define EDMA_CH_PRI_DPA (1 << 30) /* Bit 30: Disable Preempt Ability (DPA) */
+#define EDMA_CH_PRI_ECP (1 << 31) /* Bit 31: Enable Channel Preemption (ECP) */
+
+/* TCDn Source Address Register (TCDn_SADDR) */
+
+#define EDMA_TCD_SADDR_SHIFT (0) /* Bits 0-31: Source Address (SADDR) */
+#define EDMA_TCD_SADDR_MASK (0xffffffff << EDMA_TCD_SADDR_SHIFT)
+
+/* TCDn Signed Source Address Offset Register (TCDn_SOFF) */
+
+#define EDMA_TCD_SOFF_SHIFT (0) /* Bits 0-31: Source Address Signed Offset (SOFF) */
+#define EDMA_TCD_SOFF_MASK (0xffffffff << EDMA_TCD_SOFF_SHIFT)
+
+/* TCDn Transfer Attributes (TCDn_ATTR) */
+
+#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */
+#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT)
+#define EDMA_TCD_ATTR_DSIZE(n) ((n << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK)
+#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */
+#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT)
+#define EDMA_TCD_ATTR_DMOD(n) ((n << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK)
+#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */
+#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT)
+#define EDMA_TCD_ATTR_SSIZE(n) ((n << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK)
+# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
+# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
+# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
+# define EDMA_TCD_ATTR_SSIZE_64BIT (0x03 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */
+# define EDMA_TCD_ATTR_SSIZE_16BYTE (0x04 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */
+# define EDMA_TCD_ATTR_SSIZE_32BYTE (0x05 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte */
+# define EDMA_TCD_ATTR_SSIZE_64BYTE (0x06 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-byte */
+
+#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */
+#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT)
+#define EDMA_TCD_ATTR_SMOD(n) ((n << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK)
+
+/* TCDn Transfer Size (TCDn_NBYTES) */
+
+#define EDMA_TCD_NBYTES_SHIFT (0) /* Bits 0-29: Number of Bytes to Transfer per Service Request (NBYTES) */
+#define EDMA_TCD_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_SHIFT)
+#define EDMA_TCD_NBYTES_MASK_MLOFF (0x03ff << EDMA_TCD_NBYTES_SHIFT)
+#define EDMA_TCD_NBYTES_MLOFF_SHIFT (10) /* Bits 10-29: Minor Loop Offset (MLOFF) */
+#define EDMA_TCD_NBYTES_MLOFF_MASK (0x0fffff << EDMA_TCD_NBYTES_MLOFF_SHIFT)
+#define EDMA_TCD_NBYTES_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset Enable (DMLOE) */
+#define EDMA_TCD_NBYTES_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable (SMLOE) */
+
+/* TCDn Last Source Address Adjustment / Store DADDR Address Register
+ * (TCDn_SLAST_SDA)
+ */
+
+#define EDMA_TCD_SLAST_SDA_SHIFT (0) /* Bits 0-31: Last Source Address Adjustment / Store DADDR Address (SLAST_SDA) */
+#define EDMA_TCD_SLAST_SDA_MASK (0xffffffff << EDMA_TCD_SLAST_SDA_SHIFT)
+
+/* TCDn Destination Address Register (TCDn_DADDR) */
+
+#define EDMA_TCD_DADDR_SHIFT (0) /* Bits 0-31: Destination Address (DADDR) */
+#define EDMA_TCD_DADDR_MASK (0xffffffff << EDMA_TCD_DADDR_SHIFT)
+
+/* TCDn Signed Destination Address Offset Register (TCDn_DOFF) */
+
+#define EDMA_TCD_DOFF_SHIFT (0) /* Bits 0-15: Destination Address Signed Offset (DOFF) */
+#define EDMA_TCD_DOFF_MASK (0xffff << EDMA_TCD_DOFF_SHIFT)
+
+/* TCDn Current Major Loop Count Register (TCDn_CITER) */
+
+#define EDMA_TCD_CITER_SHIFT (0) /* Bits 0-14: Current Major Iteration Count (CITER) */
+#define EDMA_TCD_CITER_MASK (0x7fff << EDMA_TCD_CITER_SHIFT)
+#define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT)
+#define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */
+#define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT)
+#define EDMA_TCD_CITER_LINKCH(n) ((n << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT)
+#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
+
+/* TCDn Last Destination Address Adjustment / Scatter Gather Address Register
+ * (TCDn_DLAST_SGA)
+ */
+
+#define EDMA_TCD_DLAST_SGA_SHIFT (0) /* Bits 0-31: Last Destination Address Adjustment / Scatter Gather Address (DLAST_SGA) */
+#define EDMA_TCD_DLAST_SGA_MASK (0xffffffff << EDMA_TCD_DLAST_SGA_SHIFT)
+
+/* TCDn Control and Status Register (TCDn_CSR) */
+
+#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start (START) */
+#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable Interrupt if Major count complete (INTMAJOR) */
+#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable Interrupt if Major Count Half-complete (INTHALF) */
+#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request (DREQ) */
+#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing (ESG) */
+#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable Link When Major Loop Complete (MAJORELINK) */
+#define EDMA_TCD_CSR_EEOP (1 << 6) /* Bit 6: Enable End-Of-Packet Processing (EEOP) */
+#define EDMA_TCD_CSR_ESDA (1 << 7) /* Bit 7: Enable Store Destination Address (ESDA) */
+#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number (MAJORLINKCH) */
+#define EDMA_TCD_CSR_MAJORLINKCH_MASK (0x1f << EDMA_TCD_CSR_MAJORLINKCH_SHIFT)
+#define EDMA_TCD_CSR_MAJORLINKCH(n) ((n << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK)
Review Comment:
```suggestion
#define EDMA_TCD_CSR_MAJORLINKCH(n) (((n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK)
```
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] PetervdPerk-NXP commented on a diff in pull request #6687: Add support for NXP S32K3XX MCU family and boards
Posted by GitBox <gi...@apache.org>.
PetervdPerk-NXP commented on code in PR #6687:
URL: https://github.com/apache/incubator-nuttx/pull/6687#discussion_r927751053
##########
boards/arm/s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c:
##########
@@ -0,0 +1,157 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+
+#include "s32k3xx_clockconfig.h"
+#include "s32k3xx_start.h"
+
+#include "s32k344evb.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Each S32K3XX board must provide the following initialized structure.
+ * This is needed to establish the initial board clocking.
+ */
+
+const struct clock_configuration_s g_initial_clkconfig =
+{
+ .cgm =
+ {
+ .sirc =
+ {
+ .range = CGM_FIRC_RANGE_32K, /* Slow IRC is trimmed to 32 kHz */
+ },
+ .firc =
+ {
+ .range = CGM_FIRC_RANGE_HIGH, /* RANGE */
+ .div = CGM_CLOCK_DIV_BY_1, /* FIRCDIV1 */
+ },
+ .scs =
+ {
+ .scs_source = CGM_SCS_SOURCE_PLL_PHI0,
+ .core_clk =
+ {
+ .div = CGM_MUX_DIV_BY_1,
+ .trigger = false,
+ },
+ .aips_plat_clk =
+ {
+ .div = CGM_MUX_DIV_BY_2,
+ .trigger = false,
Review Comment:
Rather make it explicit for visibility.
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] PetervdPerk-NXP commented on a diff in pull request #6687: Add support for NXP S32K3XX MCU family and boards
Posted by GitBox <gi...@apache.org>.
PetervdPerk-NXP commented on code in PR #6687:
URL: https://github.com/apache/incubator-nuttx/pull/6687#discussion_r928762513
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h:
##########
@@ -0,0 +1,504 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* QSPI Register Offsets ****************************************************/
+
+#define S32K3XX_QSPI_MCR_OFFSET (0x0000) /* Module Configuration Register (MCR) */
+#define S32K3XX_QSPI_IPCR_OFFSET (0x0008) /* IP Configuration Register (IPCR) */
+#define S32K3XX_QSPI_FLSHCR_OFFSET (0x000c) /* Flash Memory Configuration Register (FLSHCR) */
+#define S32K3XX_QSPI_BUF0CR_OFFSET (0x0010) /* Buffer 0 Configuration Register (BUF0CR) */
+#define S32K3XX_QSPI_BUF1CR_OFFSET (0x0014) /* Buffer 1 Configuration Register (BUF1CR) */
+#define S32K3XX_QSPI_BUF2CR_OFFSET (0x0018) /* Buffer 2 Configuration Register (BUF2CR) */
+#define S32K3XX_QSPI_BUF3CR_OFFSET (0x001c) /* Buffer 3 Configuration Register (BUF3CR) */
+#define S32K3XX_QSPI_BFGENCR_OFFSET (0x0020) /* Buffer Generic Configuration Register (BFGENCR) */
+#define S32K3XX_QSPI_SOCCR_OFFSET (0x0024) /* SOC Configuration Register (SOCCR) */
+#define S32K3XX_QSPI_BUF0IND_OFFSET (0x0030) /* Buffer 0 Top Index Register (BUF0IND) */
+#define S32K3XX_QSPI_BUF1IND_OFFSET (0x0034) /* Buffer 1 Top Index Register (BUF1IND) */
+#define S32K3XX_QSPI_BUF2IND_OFFSET (0x0038) /* Buffer 2 Top Index Register (BUF2IND) */
+#define S32K3XX_QSPI_DLLCRA_OFFSET (0x0060) /* DLL Flash Memory A Configuration Register (DLLCRA) */
+#define S32K3XX_QSPI_SFAR_OFFSET (0x0100) /* Serial Flash Memory Address Register (SFAR) */
+#define S32K3XX_QSPI_SMPR_OFFSET (0x0108) /* Sampling Register (SMPR) */
+#define S32K3XX_QSPI_RBSR_OFFSET (0x010c) /* RX Buffer Status Register (RBSR) */
+#define S32K3XX_QSPI_RBCT_OFFSET (0x0110) /* RX Buffer Control Register (RBCT) */
+#define S32K3XX_QSPI_DLSR_FA_OFFSET (0x0134) /* Data Learning Status Flash Memory A Register (DLSR_FA) */
+#define S32K3XX_QSPI_TBSR_OFFSET (0x0150) /* TX Buffer Status Register (TBSR) */
+#define S32K3XX_QSPI_TBDR_OFFSET (0x0154) /* TX Buffer Data Register (TBDR) */
+#define S32K3XX_QSPI_TBCT_OFFSET (0x0158) /* TX Buffer Control Register (TBCT) */
+#define S32K3XX_QSPI_SR_OFFSET (0x015c) /* Status Register (SR) */
+#define S32K3XX_QSPI_FR_OFFSET (0x0160) /* Flag Register (FR) */
+#define S32K3XX_QSPI_RSER_OFFSET (0x0164) /* Interrupt and DMA Request Select and Enable Register (RSER) */
+#define S32K3XX_QSPI_SPTRCLR_OFFSET (0x016c) /* Sequence Pointer Clear Register (SPTRCLR) */
+#define S32K3XX_QSPI_SFA1AD_OFFSET (0x0180) /* Serial Flash Memory A1 Top Address Register (SFA1AD) */
+#define S32K3XX_QSPI_SFA2AD_OFFSET (0x0184) /* Serial Flash Memory A2 Top Address Register (SFA2AD) */
+#define S32K3XX_QSPI_SFB1AD_OFFSET (0x0188) /* Serial Flash Memory B1 Top Address Register (SFB1AD) */
+#define S32K3XX_QSPI_SFB2AD_OFFSET (0x018c) /* Serial Flash Memory B2 Top Address Register (SFB2AD) */
+
+#define S32K3XX_QSPI_RBDR_OFFSET(n) (0x0200 + ((n) << 2)) /* RX Buffer Data Register (RBDRn, n=0,...,63) */
+
+#define S32K3XX_QSPI_LUTKEY_OFFSET (0x0300) /* LUT Key Register (LUTKEY) */
+#define S32K3XX_QSPI_LCKCR_OFFSET (0x0304) /* LUT Lock Configuration Register (LKCR) */
+#define S32K3XX_QSPI_LUT0_OFFSET (0x0310) /* LUT Register 0 (LUT0) */
+#define S32K3XX_QSPI_LUT1_OFFSET (0x0314) /* LUT Register 1 (LUT1) */
+#define S32K3XX_QSPI_LUT2_OFFSET (0x0318) /* LUT Register 2 (LUT2) */
+#define S32K3XX_QSPI_LUT3_OFFSET (0x031c) /* LUT Register 3 (LUT3) */
+#define S32K3XX_QSPI_LUT4_OFFSET (0x0320) /* LUT Register 4 (LUT4) */
+#define S32K3XX_QSPI_LUT5_OFFSET (0x0324) /* LUT Register 5 (LUT5) */
+#define S32K3XX_QSPI_LUT6_OFFSET (0x0328) /* LUT Register 6 (LUT6) */
+#define S32K3XX_QSPI_LUT7_OFFSET (0x032c) /* LUT Register 7 (LUT7) */
+#define S32K3XX_QSPI_LUT8_OFFSET (0x0330) /* LUT Register 8 (LUT8) */
+#define S32K3XX_QSPI_LUT9_OFFSET (0x0334) /* LUT Register 9 (LUT9) */
+#define S32K3XX_QSPI_LUT10_OFFSET (0x0338) /* LUT Register 10 (LUT10) */
+#define S32K3XX_QSPI_LUT11_OFFSET (0x033c) /* LUT Register 11 (LUT11) */
+#define S32K3XX_QSPI_LUT12_OFFSET (0x0340) /* LUT Register 12 (LUT12) */
+#define S32K3XX_QSPI_LUT13_OFFSET (0x0344) /* LUT Register 13 (LUT13) */
+#define S32K3XX_QSPI_LUT14_OFFSET (0x0348) /* LUT Register 14 (LUT14) */
+#define S32K3XX_QSPI_LUT15_OFFSET (0x034c) /* LUT Register 15 (LUT15) */
+#define S32K3XX_QSPI_LUT16_OFFSET (0x0350) /* LUT Register 16 (LUT16) */
+#define S32K3XX_QSPI_LUT17_OFFSET (0x0354) /* LUT Register 17 (LUT17) */
+#define S32K3XX_QSPI_LUT18_OFFSET (0x0358) /* LUT Register 18 (LUT18) */
+#define S32K3XX_QSPI_LUT19_OFFSET (0x035c) /* LUT Register 19 (LUT19) */
+
+/* QSPI Register Addresses **************************************************/
+
+#define S32K3XX_QSPI_MCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_MCR_OFFSET)
+#define S32K3XX_QSPI_IPCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_IPCR_OFFSET)
+#define S32K3XX_QSPI_FLSHCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FLSHCR_OFFSET)
+#define S32K3XX_QSPI_BUF0CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0CR_OFFSET)
+#define S32K3XX_QSPI_BUF1CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1CR_OFFSET)
+#define S32K3XX_QSPI_BUF2CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2CR_OFFSET)
+#define S32K3XX_QSPI_BUF3CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF3CR_OFFSET)
+#define S32K3XX_QSPI_BFGENCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BFGENCR_OFFSET)
+#define S32K3XX_QSPI_SOCCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SOCCR_OFFSET)
+#define S32K3XX_QSPI_BUF0IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0IND_OFFSET)
+#define S32K3XX_QSPI_BUF1IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1IND_OFFSET)
+#define S32K3XX_QSPI_BUF2IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2IND_OFFSET)
+#define S32K3XX_QSPI_DLLCRA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLLCRA_OFFSET)
+#define S32K3XX_QSPI_SFAR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFAR_OFFSET)
+#define S32K3XX_QSPI_SMPR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SMPR_OFFSET)
+#define S32K3XX_QSPI_RBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBSR_OFFSET)
+#define S32K3XX_QSPI_RBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBCT_OFFSET)
+#define S32K3XX_QSPI_DLSR_FA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLSR_FA_OFFSET)
+#define S32K3XX_QSPI_TBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBSR_OFFSET)
+#define S32K3XX_QSPI_TBDR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBDR_OFFSET)
+#define S32K3XX_QSPI_TBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBCT_OFFSET)
+#define S32K3XX_QSPI_SR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SR_OFFSET)
+#define S32K3XX_QSPI_FR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FR_OFFSET)
+#define S32K3XX_QSPI_RSER (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RSER_OFFSET)
+#define S32K3XX_QSPI_SPTRCLR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SPTRCLR_OFFSET)
+#define S32K3XX_QSPI_SFA1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA1AD_OFFSET)
+#define S32K3XX_QSPI_SFA2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA2AD_OFFSET)
+#define S32K3XX_QSPI_SFB1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB1AD_OFFSET)
+#define S32K3XX_QSPI_SFB2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB2AD_OFFSET)
+#define S32K3XX_QSPI_RBDR(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBDR_OFFSET(n))
+#define S32K3XX_QSPI_LUTKEY (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUTKEY_OFFSET)
+#define S32K3XX_QSPI_LCKCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LCKCR_OFFSET)
+#define S32K3XX_QSPI_LUT0 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET)
+#define S32K3XX_QSPI_LUT1 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT1_OFFSET)
+#define S32K3XX_QSPI_LUT2 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT2_OFFSET)
+#define S32K3XX_QSPI_LUT3 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT3_OFFSET)
+#define S32K3XX_QSPI_LUT4 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT4_OFFSET)
+#define S32K3XX_QSPI_LUT5 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT5_OFFSET)
+#define S32K3XX_QSPI_LUT6 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT6_OFFSET)
+#define S32K3XX_QSPI_LUT7 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT7_OFFSET)
+#define S32K3XX_QSPI_LUT8 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT8_OFFSET)
+#define S32K3XX_QSPI_LUT9 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT9_OFFSET)
+#define S32K3XX_QSPI_LUT10 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT10_OFFSET)
+#define S32K3XX_QSPI_LUT11 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT11_OFFSET)
+#define S32K3XX_QSPI_LUT12 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT12_OFFSET)
+#define S32K3XX_QSPI_LUT13 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT13_OFFSET)
+#define S32K3XX_QSPI_LUT14 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT14_OFFSET)
+#define S32K3XX_QSPI_LUT15 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT15_OFFSET)
+#define S32K3XX_QSPI_LUT16 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT16_OFFSET)
+#define S32K3XX_QSPI_LUT17 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT17_OFFSET)
+#define S32K3XX_QSPI_LUT18 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT18_OFFSET)
+#define S32K3XX_QSPI_LUT19 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT19_OFFSET)
+
+#define S32K3XX_QSPI_LUT(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET + (n*4))
+#define S32K3XX_QSPI_LUT_COUNT 20
+
+/* QSPI Register Bitfield Definitions ***************************************/
+
+/* Module Configuration Register (MCR) */
+
+#define QSPI_MCR_SWRSTSD (1 << 0) /* Bit 0: Software reset for serial flash memory domain (SWRSTSD) */
+#define QSPI_MCR_SWRSTHD (1 << 1) /* Bit 1: Software reset fo AHB domain (SWRSTHD) */
+ /* Bits 2-9: Reserved */
+#define QSPI_MCR_CLR_RXF (1 << 10) /* Bit 10: Clear RX FIFO (CLR_RXF) */
+#define QSPI_MCR_CLR_TXF (1 << 11) /* Bit 11: Clear TX FIFO/buffer (CLR_TXF) */
+ /* Bits 12-13: Reserved */
+#define QSPI_MCR_MDIS (1 << 14) /* Bit 14: Module disable (MDIS) */
+ /* Bits 15-23: Reserved */
+#define QSPI_MCR_DQS_FA_SEL_SHIFT (24) /* Bits 24-25: DQS clock for sampling read data at flash memory A (DQS_FA_SEL) */
+#define QSPI_MCR_DQS_FA_SEL_MASK (0x03 << QSPI_MCR_DQS_FA_SEL_SHIFT)
+#define QSPI_MCR_DQS_FA_SEL_INTERNAL_DQS ((0x00 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+#define QSPI_MCR_DQS_FA_SEL_LOOPBACK ((0x01 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+#define QSPI_MCR_DQS_FA_SEL_LOOPBACK_DQS ((0x02 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+ /* Bits 26-31: Reserved */
+
+/* IP Configuration Register (IPCR) */
+
+#define QSPICR_IDATSZ_SHIFT (0) /* Bits 0-15: IP data transfer size (IDATSZ) */
+#define QSPICR_IDATSZ_MASK (0xffff << QSPICR_IDATSZ_SHIFT)
+#define QSPICR_IDATSZ(n) ((n << QSPICR_IDATSZ_SHIFT) & QSPICR_IDATSZ_MASK)
+ /* Bits 16-23: Reserved */
+#define QSPICR_SEQID_SHIFT (24) /* Bits 24-27: Points to a sequence in the LUT (SEQID) */
+#define QSPICR_SEQID_MASK (0x0f << QSPICR_SEQID_SHIFT)
+#define QSPICR_SEQID(n) ((n << QSPICR_SEQID_SHIFT) & QSPICR_SEQID_MASK)
+ /* Bits 28-31: Reserved */
+
+/* Flash Memory Configuration Register (FLSHCR) */
+
+#define QSPI_FLSHCR_TCSS_SHIFT (0) /* Bits 0-3: Serial flash memory CS setup time (TCSS) */
+#define QSPI_FLSHCR_TCSS_MASK (0x0f << QSPI_FLSHCR_TCSS_SHIFT)
+#define QSPI_FLSHCR_TCSS(n) (n & QSPI_FLSHCR_TCSS_MASK)
+#define QSPI_FLSHCR_TCSH_SHIFT (8) /* Bits 8-11: Serial flash memory CS hold time (TCSH) */
+#define QSPI_FLSHCR_TCSH_MASK (0x0f << QSPI_FLSHCR_TCSH_SHIFT)
+#define QSPI_FLSHCR_TCSH(n) ((n << QSPI_FLSHCR_TCSH_SHIFT) & QSPI_FLSHCR_TCSH_MASK)
+ /* Bits 12-31: Reserved */
+
+/* Buffer n Configuration Register (BUFnCR) */
+
+#define QSPI_BUFCR_MSTRID_SHIFT (0) /* Bits 0-3: Master ID (MSTRID) */
+#define QSPI_BUFCR_MSTRID_MASK (0x0f << QSPI_BUFCR_MSTRID_SHIFT)
+#define QSPI_BUFCR_MSTRID(n) ((n << QSPI_BUFCR_MSTRID_SHIFT) & QSPI_BUFCR_MSTRID_MASK)
+ /* Bits 4-7: Reserved */
+#define QSPI_BUFCR_ADATSZ_SHIFT (8) /* Bits 8-13: AHB data transfer size (ADATSZ) */
+#define QSPI_BUFCR_ADATSZ_MASK (0x3f << QSPI_BUFCR_ADATSZ_SHIFT)
+#define QSPI_BUFCR_ADATSZ(n) ((n << QSPI_BUFCR_ADATSZ_SHIFT) & QSPI_BUFCR_ADATSZ_MASK)
+ /* Bits 14-31: Reserved */
+#define QSPI_BUF3CR_ALLMST (1 << 31) /* Bit 31: All master enable (ALLMST) */
+
+/* Buffer Generic Configuration Register (BFGENCR) */
+
+ /* Bits 0-11: Reserved */
+#define QSPI_BFGENCR_SEQID_SHIFT (12) /* Bits 12-15: Points to a sequence in the LUT (SEQID) */
+#define QSPI_BFGENCR_SEQID_MASK (0x0f << QSPI_BFGENCR_SEQID_SHIFT)
+ /* Bits 16-31: Reserved */
+
+/* SOC Configuration Register (SOCCR) */
+
+#define QSPI_SOCCR_SOCCFG_SHIFT (0) /* Bits 0-31: SOC configuration (SOCCFG) */
+#define QSPI_SOCCR_SOCCFG_MASK (0xffffffff << QSPI_SOCCR_SOCCFG_SHIFT)
+#define QSPI_SOCCR_OBE_PULL_TMG_RLX (1 << 0) /* Bit 0: obe_pull_timing_relax_b*/
+#define QSPI_SOCCR_IBE (1 << 1) /* Bit 1: IBE */
+#define QSPI_SOCCR_OBE (1 << 2) /* Bit 2: OBE */
+#define QSPI_SOCCR_DSE (1 << 3) /* Bit 3: DSE */
+#define QSPI_SOCCR_PUE (1 << 4) /* Bit 4: PUE */
+#define QSPI_SOCCR_PUS (1 << 5) /* Bit 5: PUS */
+#define QSPI_SOCCR_SRE (1 << 6) /* Bit 6: SRE */
+
+/* Buffer n Top Index Register (BUFnIND) */
+
+ /* Bits 0-2: Reserved */
+#define QSPI_BUFIND_TPINDX_SHIFT (3) /* Bits 3-8: Top index of buffer n (TPINDXn) */
+#define QSPI_BUFIND_TPINDX_MASK (0x3f << QSPI_BUFIND_TPINDX_SHIFT)
+ /* Bits 9-31: Reserved */
+
+/* DLL Flash Memory A Configuration Register (DLLCRA) */
+
+#define QSPI_DLLCRA_SLV_UPD (1 << 0) /* Bit 0: Slave update (SLV_UPD) */
+#define QSPI_DLLCRA_SLV_DLL_BYPASS (1 << 1) /* Bit 1: Slave DLL bypass (SLV_DLL_BYPASS) */
+#define QSPI_DLLCRA_SLV_EN (1 << 2) /* Bit 2: Slave enable (SLV_EN) */
+ /* Bits 3-7: Reserved */
+
+#define QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT (8) /* Bits 8-11: Delay elements in each delay tap (SLV_DLY_COARSE) */
+#define QSPI_DLLCRA_SLV_DLY_COARSE_MASK (0x0f << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT)
+#define QSPI_DLLCRA_SLV_DLY_COARSE(n) ((n << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT) & QSPI_DLLCRA_SLV_DLY_COARSE_MASK)
Review Comment:
I've got them all now I think, thanks for being sharp.
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] PetervdPerk-NXP commented on a diff in pull request #6687: Add support for NXP S32K3XX MCU family and boards
Posted by GitBox <gi...@apache.org>.
PetervdPerk-NXP commented on code in PR #6687:
URL: https://github.com/apache/incubator-nuttx/pull/6687#discussion_r927750373
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h:
##########
@@ -0,0 +1,1433 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define S32K3XX_EDMA_NCHANNELS 32
+
+/* eDMA Register Offsets ****************************************************/
+
+#define S32K3XX_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */
+#define S32K3XX_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */
+#define S32K3XX_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */
+#define S32K3XX_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */
+
+#define S32K3XX_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */
+
+/* eDMA Register Addresses **************************************************/
+
+#define S32K3XX_EDMA_CSR (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CSR_OFFSET)
+#define S32K3XX_EDMA_ES (S32K3XX_EDMA_BASE + S32K3XX_EDMA_ES_OFFSET)
+#define S32K3XX_EDMA_INT (S32K3XX_EDMA_BASE + S32K3XX_EDMA_INT_OFFSET)
+#define S32K3XX_EDMA_HRS (S32K3XX_EDMA_BASE + S32K3XX_EDMA_HRS_OFFSET)
+#define S32K3XX_EDMA_CH_GRPRI(n) (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CH_GRPRI_OFFSET(n))
+
+/* eDMA Transfer Control Descriptor (TCD) Register Offsets ******************/
+
+#define S32K3XX_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH0_CSR_OFFSET (0x000000) /* Channel 0 Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH0_ES_OFFSET (0x000004) /* Channel 0 Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH0_INT_OFFSET (0x000008) /* Channel 0 Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH0_SBR_OFFSET (0x00000c) /* Channel 0 System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH0_PRI_OFFSET (0x000010) /* Channel 0 Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD0_SADDR_OFFSET (0x000020) /* TCD0 Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD0_SOFF_OFFSET (0x000024) /* TCD0 Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD0_ATTR_OFFSET (0x000026) /* TCD0 Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD0_NBYTES_OFFSET (0x000028) /* TCD0 Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET (0x00002c) /* TCD0 Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD0_DADDR_OFFSET (0x000030) /* TCD0 Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD0_DOFF_OFFSET (0x000034) /* TCD0 Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD0_CITER_OFFSET (0x000036) /* TCD0 Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET (0x000038) /* TCD0 Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD0_CSR_OFFSET (0x00003c) /* TCD0 Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD0_BITER_OFFSET (0x00003e) /* TCD0 Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH1_CSR_OFFSET (0x004000) /* Channel 1 Control and Status Register (CH1_CSR) */
+#define S32K3XX_EDMA_CH1_ES_OFFSET (0x004004) /* Channel 1 Error Status Register (CH1_ES) */
+#define S32K3XX_EDMA_CH1_INT_OFFSET (0x004008) /* Channel 1 Interrupt Status Register (CH1_INT) */
+#define S32K3XX_EDMA_CH1_SBR_OFFSET (0x00400c) /* Channel 1 System Bus Register (CH1_SBR) */
+#define S32K3XX_EDMA_CH1_PRI_OFFSET (0x004010) /* Channel 1 Priority Register (CH1_PRI) */
+#define S32K3XX_EDMA_TCD1_SADDR_OFFSET (0x004020) /* TCD1 Source Address Register (TCD1_SADDR) */
+#define S32K3XX_EDMA_TCD1_SOFF_OFFSET (0x004024) /* TCD1 Signed Source Address Offset Register (TCD1_SOFF) */
+#define S32K3XX_EDMA_TCD1_ATTR_OFFSET (0x004026) /* TCD1 Transfer Attributes (TCD1_ATTR) */
+#define S32K3XX_EDMA_TCD1_NBYTES_OFFSET (0x004028) /* TCD1 Transfer Size (TCD1_NBYTES) */
+#define S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET (0x00402c) /* TCD1 Last Source Address Adjustment / Store DADDR Address Register (TCD1_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD1_DADDR_OFFSET (0x004030) /* TCD1 Destination Address Register (TCD1_DADDR) */
+#define S32K3XX_EDMA_TCD1_DOFF_OFFSET (0x004034) /* TCD1 Signed Destination Address Offset Register (TCD1_DOFF) */
+#define S32K3XX_EDMA_TCD1_CITER_OFFSET (0x004036) /* TCD1 Current Major Loop Count Register (TCD1_CITER) */
+#define S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET (0x004038) /* TCD1 Last Destination Address Adjustment / Scatter Gather Address Register (TCD1_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD1_CSR_OFFSET (0x00403c) /* TCD1 Control and Status Register (TCD1_CSR) */
+#define S32K3XX_EDMA_TCD1_BITER_OFFSET (0x00403e) /* TCD1 Beginning Major Loop Count Register (TCD1_BITER) */
+
+#define S32K3XX_EDMA_CH2_CSR_OFFSET (0x008000) /* Channel 2 Control and Status Register (CH2_CSR) */
+#define S32K3XX_EDMA_CH2_ES_OFFSET (0x008004) /* Channel 2 Error Status Register (CH2_ES) */
+#define S32K3XX_EDMA_CH2_INT_OFFSET (0x008008) /* Channel 2 Interrupt Status Register (CH2_INT) */
+#define S32K3XX_EDMA_CH2_SBR_OFFSET (0x00800c) /* Channel 2 System Bus Register (CH2_SBR) */
+#define S32K3XX_EDMA_CH2_PRI_OFFSET (0x008010) /* Channel 2 Priority Register (CH2_PRI) */
+#define S32K3XX_EDMA_TCD2_SADDR_OFFSET (0x008020) /* TCD2 Source Address Register (TCD2_SADDR) */
+#define S32K3XX_EDMA_TCD2_SOFF_OFFSET (0x008024) /* TCD2 Signed Source Address Offset Register (TCD2_SOFF) */
+#define S32K3XX_EDMA_TCD2_ATTR_OFFSET (0x008026) /* TCD2 Transfer Attributes (TCD2_ATTR) */
+#define S32K3XX_EDMA_TCD2_NBYTES_OFFSET (0x008028) /* TCD2 Transfer Size (TCD2_NBYTES) */
+#define S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET (0x00802c) /* TCD2 Last Source Address Adjustment / Store DADDR Address Register (TCD2_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD2_DADDR_OFFSET (0x008030) /* TCD2 Destination Address Register (TCD2_DADDR) */
+#define S32K3XX_EDMA_TCD2_DOFF_OFFSET (0x008034) /* TCD2 Signed Destination Address Offset Register (TCD2_DOFF) */
+#define S32K3XX_EDMA_TCD2_CITER_OFFSET (0x008036) /* TCD2 Current Major Loop Count Register (TCD2_CITER) */
+#define S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET (0x008038) /* TCD2 Last Destination Address Adjustment / Scatter Gather Address Register (TCD2_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD2_CSR_OFFSET (0x00803c) /* TCD2 Control and Status Register (TCD2_CSR) */
+#define S32K3XX_EDMA_TCD2_BITER_OFFSET (0x00803e) /* TCD2 Beginning Major Loop Count Register (TCD2_BITER) */
+
+#define S32K3XX_EDMA_CH3_CSR_OFFSET (0x00c000) /* Channel 3 Control and Status Register (CH3_CSR) */
+#define S32K3XX_EDMA_CH3_ES_OFFSET (0x00c004) /* Channel 3 Error Status Register (CH3_ES) */
+#define S32K3XX_EDMA_CH3_INT_OFFSET (0x00c008) /* Channel 3 Interrupt Status Register (CH3_INT) */
+#define S32K3XX_EDMA_CH3_SBR_OFFSET (0x00c00c) /* Channel 3 System Bus Register (CH3_SBR) */
+#define S32K3XX_EDMA_CH3_PRI_OFFSET (0x00c010) /* Channel 3 Priority Register (CH3_PRI) */
+#define S32K3XX_EDMA_TCD3_SADDR_OFFSET (0x00c020) /* TCD3 Source Address Register (TCD3_SADDR) */
+#define S32K3XX_EDMA_TCD3_SOFF_OFFSET (0x00c024) /* TCD3 Signed Source Address Offset Register (TCD3_SOFF) */
+#define S32K3XX_EDMA_TCD3_ATTR_OFFSET (0x00c026) /* TCD3 Transfer Attributes (TCD3_ATTR) */
+#define S32K3XX_EDMA_TCD3_NBYTES_OFFSET (0x00c028) /* TCD3 Transfer Size (TCD3_NBYTES) */
+#define S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET (0x00c02c) /* TCD3 Last Source Address Adjustment / Store DADDR Address Register (TCD3_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD3_DADDR_OFFSET (0x00c030) /* TCD3 Destination Address Register (TCD3_DADDR) */
+#define S32K3XX_EDMA_TCD3_DOFF_OFFSET (0x00c034) /* TCD3 Signed Destination Address Offset Register (TCD3_DOFF) */
+#define S32K3XX_EDMA_TCD3_CITER_OFFSET (0x00c036) /* TCD3 Current Major Loop Count Register (TCD3_CITER) */
+#define S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET (0x00c038) /* TCD3 Last Destination Address Adjustment / Scatter Gather Address Register (TCD3_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD3_CSR_OFFSET (0x00c03c) /* TCD3 Control and Status Register (TCD3_CSR) */
+#define S32K3XX_EDMA_TCD3_BITER_OFFSET (0x00c03e) /* TCD3 Beginning Major Loop Count Register (TCD3_BITER) */
+
+#define S32K3XX_EDMA_CH4_CSR_OFFSET (0x010000) /* Channel 4 Control and Status Register (CH4_CSR) */
+#define S32K3XX_EDMA_CH4_ES_OFFSET (0x010004) /* Channel 4 Error Status Register (CH4_ES) */
+#define S32K3XX_EDMA_CH4_INT_OFFSET (0x010008) /* Channel 4 Interrupt Status Register (CH4_INT) */
+#define S32K3XX_EDMA_CH4_SBR_OFFSET (0x01000c) /* Channel 4 System Bus Register (CH4_SBR) */
+#define S32K3XX_EDMA_CH4_PRI_OFFSET (0x010010) /* Channel 4 Priority Register (CH4_PRI) */
+#define S32K3XX_EDMA_TCD4_SADDR_OFFSET (0x010020) /* TCD4 Source Address Register (TCD4_SADDR) */
+#define S32K3XX_EDMA_TCD4_SOFF_OFFSET (0x010024) /* TCD4 Signed Source Address Offset Register (TCD4_SOFF) */
+#define S32K3XX_EDMA_TCD4_ATTR_OFFSET (0x010026) /* TCD4 Transfer Attributes (TCD4_ATTR) */
+#define S32K3XX_EDMA_TCD4_NBYTES_OFFSET (0x010028) /* TCD4 Transfer Size (TCD4_NBYTES) */
+#define S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET (0x01002c) /* TCD4 Last Source Address Adjustment / Store DADDR Address Register (TCD4_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD4_DADDR_OFFSET (0x010030) /* TCD4 Destination Address Register (TCD4_DADDR) */
+#define S32K3XX_EDMA_TCD4_DOFF_OFFSET (0x010034) /* TCD4 Signed Destination Address Offset Register (TCD4_DOFF) */
+#define S32K3XX_EDMA_TCD4_CITER_OFFSET (0x010036) /* TCD4 Current Major Loop Count Register (TCD4_CITER) */
+#define S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET (0x010038) /* TCD4 Last Destination Address Adjustment / Scatter Gather Address Register (TCD4_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD4_CSR_OFFSET (0x01003c) /* TCD4 Control and Status Register (TCD4_CSR) */
+#define S32K3XX_EDMA_TCD4_BITER_OFFSET (0x01003e) /* TCD4 Beginning Major Loop Count Register (TCD4_BITER) */
+
+#define S32K3XX_EDMA_CH5_CSR_OFFSET (0x014000) /* Channel 5 Control and Status Register (CH5_CSR) */
+#define S32K3XX_EDMA_CH5_ES_OFFSET (0x014004) /* Channel 5 Error Status Register (CH5_ES) */
+#define S32K3XX_EDMA_CH5_INT_OFFSET (0x014008) /* Channel 5 Interrupt Status Register (CH5_INT) */
+#define S32K3XX_EDMA_CH5_SBR_OFFSET (0x01400c) /* Channel 5 System Bus Register (CH5_SBR) */
+#define S32K3XX_EDMA_CH5_PRI_OFFSET (0x014010) /* Channel 5 Priority Register (CH5_PRI) */
+#define S32K3XX_EDMA_TCD5_SADDR_OFFSET (0x014020) /* TCD5 Source Address Register (TCD5_SADDR) */
+#define S32K3XX_EDMA_TCD5_SOFF_OFFSET (0x014024) /* TCD5 Signed Source Address Offset Register (TCD5_SOFF) */
+#define S32K3XX_EDMA_TCD5_ATTR_OFFSET (0x014026) /* TCD5 Transfer Attributes (TCD5_ATTR) */
+#define S32K3XX_EDMA_TCD5_NBYTES_OFFSET (0x014028) /* TCD5 Transfer Size (TCD5_NBYTES) */
+#define S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET (0x01402c) /* TCD5 Last Source Address Adjustment / Store DADDR Address Register (TCD5_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD5_DADDR_OFFSET (0x014030) /* TCD5 Destination Address Register (TCD5_DADDR) */
+#define S32K3XX_EDMA_TCD5_DOFF_OFFSET (0x014034) /* TCD5 Signed Destination Address Offset Register (TCD5_DOFF) */
+#define S32K3XX_EDMA_TCD5_CITER_OFFSET (0x014036) /* TCD5 Current Major Loop Count Register (TCD5_CITER) */
+#define S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET (0x014038) /* TCD5 Last Destination Address Adjustment / Scatter Gather Address Register (TCD5_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD5_CSR_OFFSET (0x01403c) /* TCD5 Control and Status Register (TCD5_CSR) */
+#define S32K3XX_EDMA_TCD5_BITER_OFFSET (0x01403e) /* TCD5 Beginning Major Loop Count Register (TCD5_BITER) */
+
+#define S32K3XX_EDMA_CH6_CSR_OFFSET (0x018000) /* Channel 6 Control and Status Register (CH6_CSR) */
+#define S32K3XX_EDMA_CH6_ES_OFFSET (0x018004) /* Channel 6 Error Status Register (CH6_ES) */
+#define S32K3XX_EDMA_CH6_INT_OFFSET (0x018008) /* Channel 6 Interrupt Status Register (CH6_INT) */
+#define S32K3XX_EDMA_CH6_SBR_OFFSET (0x01800c) /* Channel 6 System Bus Register (CH6_SBR) */
+#define S32K3XX_EDMA_CH6_PRI_OFFSET (0x018010) /* Channel 6 Priority Register (CH6_PRI) */
+#define S32K3XX_EDMA_TCD6_SADDR_OFFSET (0x018020) /* TCD6 Source Address Register (TCD6_SADDR) */
+#define S32K3XX_EDMA_TCD6_SOFF_OFFSET (0x018024) /* TCD6 Signed Source Address Offset Register (TCD6_SOFF) */
+#define S32K3XX_EDMA_TCD6_ATTR_OFFSET (0x018026) /* TCD6 Transfer Attributes (TCD6_ATTR) */
+#define S32K3XX_EDMA_TCD6_NBYTES_OFFSET (0x018028) /* TCD6 Transfer Size (TCD6_NBYTES) */
+#define S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET (0x01802c) /* TCD6 Last Source Address Adjustment / Store DADDR Address Register (TCD6_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD6_DADDR_OFFSET (0x018030) /* TCD6 Destination Address Register (TCD6_DADDR) */
+#define S32K3XX_EDMA_TCD6_DOFF_OFFSET (0x018034) /* TCD6 Signed Destination Address Offset Register (TCD6_DOFF) */
+#define S32K3XX_EDMA_TCD6_CITER_OFFSET (0x018036) /* TCD6 Current Major Loop Count Register (TCD6_CITER) */
+#define S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET (0x018038) /* TCD6 Last Destination Address Adjustment / Scatter Gather Address Register (TCD6_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD6_CSR_OFFSET (0x01803c) /* TCD6 Control and Status Register (TCD6_CSR) */
+#define S32K3XX_EDMA_TCD6_BITER_OFFSET (0x01803e) /* TCD6 Beginning Major Loop Count Register (TCD6_BITER) */
+
+#define S32K3XX_EDMA_CH7_CSR_OFFSET (0x01c000) /* Channel 7 Control and Status Register (CH7_CSR) */
+#define S32K3XX_EDMA_CH7_ES_OFFSET (0x01c004) /* Channel 7 Error Status Register (CH7_ES) */
+#define S32K3XX_EDMA_CH7_INT_OFFSET (0x01c008) /* Channel 7 Interrupt Status Register (CH7_INT) */
+#define S32K3XX_EDMA_CH7_SBR_OFFSET (0x01c00c) /* Channel 7 System Bus Register (CH7_SBR) */
+#define S32K3XX_EDMA_CH7_PRI_OFFSET (0x01c010) /* Channel 7 Priority Register (CH7_PRI) */
+#define S32K3XX_EDMA_TCD7_SADDR_OFFSET (0x01c020) /* TCD7 Source Address Register (TCD7_SADDR) */
+#define S32K3XX_EDMA_TCD7_SOFF_OFFSET (0x01c024) /* TCD7 Signed Source Address Offset Register (TCD7_SOFF) */
+#define S32K3XX_EDMA_TCD7_ATTR_OFFSET (0x01c026) /* TCD7 Transfer Attributes (TCD7_ATTR) */
+#define S32K3XX_EDMA_TCD7_NBYTES_OFFSET (0x01c028) /* TCD7 Transfer Size (TCD7_NBYTES) */
+#define S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET (0x01c02c) /* TCD7 Last Source Address Adjustment / Store DADDR Address Register (TCD7_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD7_DADDR_OFFSET (0x01c030) /* TCD7 Destination Address Register (TCD7_DADDR) */
+#define S32K3XX_EDMA_TCD7_DOFF_OFFSET (0x01c034) /* TCD7 Signed Destination Address Offset Register (TCD7_DOFF) */
+#define S32K3XX_EDMA_TCD7_CITER_OFFSET (0x01c036) /* TCD7 Current Major Loop Count Register (TCD7_CITER) */
+#define S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET (0x01c038) /* TCD7 Last Destination Address Adjustment / Scatter Gather Address Register (TCD7_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD7_CSR_OFFSET (0x01c03c) /* TCD7 Control and Status Register (TCD7_CSR) */
+#define S32K3XX_EDMA_TCD7_BITER_OFFSET (0x01c03e) /* TCD7 Beginning Major Loop Count Register (TCD7_BITER) */
+
+#define S32K3XX_EDMA_CH8_CSR_OFFSET (0x020000) /* Channel 8 Control and Status Register (CH8_CSR) */
+#define S32K3XX_EDMA_CH8_ES_OFFSET (0x020004) /* Channel 8 Error Status Register (CH8_ES) */
+#define S32K3XX_EDMA_CH8_INT_OFFSET (0x020008) /* Channel 8 Interrupt Status Register (CH8_INT) */
+#define S32K3XX_EDMA_CH8_SBR_OFFSET (0x02000c) /* Channel 8 System Bus Register (CH8_SBR) */
+#define S32K3XX_EDMA_CH8_PRI_OFFSET (0x020010) /* Channel 8 Priority Register (CH8_PRI) */
+#define S32K3XX_EDMA_TCD8_SADDR_OFFSET (0x020020) /* TCD8 Source Address Register (TCD8_SADDR) */
+#define S32K3XX_EDMA_TCD8_SOFF_OFFSET (0x020024) /* TCD8 Signed Source Address Offset Register (TCD8_SOFF) */
+#define S32K3XX_EDMA_TCD8_ATTR_OFFSET (0x020026) /* TCD8 Transfer Attributes (TCD8_ATTR) */
+#define S32K3XX_EDMA_TCD8_NBYTES_OFFSET (0x020028) /* TCD8 Transfer Size (TCD8_NBYTES) */
+#define S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET (0x02002c) /* TCD8 Last Source Address Adjustment / Store DADDR Address Register (TCD8_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD8_DADDR_OFFSET (0x020030) /* TCD8 Destination Address Register (TCD8_DADDR) */
+#define S32K3XX_EDMA_TCD8_DOFF_OFFSET (0x020034) /* TCD8 Signed Destination Address Offset Register (TCD8_DOFF) */
+#define S32K3XX_EDMA_TCD8_CITER_OFFSET (0x020036) /* TCD8 Current Major Loop Count Register (TCD8_CITER) */
+#define S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET (0x020038) /* TCD8 Last Destination Address Adjustment / Scatter Gather Address Register (TCD8_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD8_CSR_OFFSET (0x02003c) /* TCD8 Control and Status Register (TCD8_CSR) */
+#define S32K3XX_EDMA_TCD8_BITER_OFFSET (0x02003e) /* TCD8 Beginning Major Loop Count Register (TCD8_BITER) */
+
+#define S32K3XX_EDMA_CH9_CSR_OFFSET (0x024000) /* Channel 9 Control and Status Register (CH9_CSR) */
+#define S32K3XX_EDMA_CH9_ES_OFFSET (0x024004) /* Channel 9 Error Status Register (CH9_ES) */
+#define S32K3XX_EDMA_CH9_INT_OFFSET (0x024008) /* Channel 9 Interrupt Status Register (CH9_INT) */
+#define S32K3XX_EDMA_CH9_SBR_OFFSET (0x02400c) /* Channel 9 System Bus Register (CH9_SBR) */
+#define S32K3XX_EDMA_CH9_PRI_OFFSET (0x024010) /* Channel 9 Priority Register (CH9_PRI) */
+#define S32K3XX_EDMA_TCD9_SADDR_OFFSET (0x024020) /* TCD9 Source Address Register (TCD9_SADDR) */
+#define S32K3XX_EDMA_TCD9_SOFF_OFFSET (0x024024) /* TCD9 Signed Source Address Offset Register (TCD9_SOFF) */
+#define S32K3XX_EDMA_TCD9_ATTR_OFFSET (0x024026) /* TCD9 Transfer Attributes (TCD9_ATTR) */
+#define S32K3XX_EDMA_TCD9_NBYTES_OFFSET (0x024028) /* TCD9 Transfer Size (TCD9_NBYTES) */
+#define S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET (0x02402c) /* TCD9 Last Source Address Adjustment / Store DADDR Address Register (TCD9_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD9_DADDR_OFFSET (0x024030) /* TCD9 Destination Address Register (TCD9_DADDR) */
+#define S32K3XX_EDMA_TCD9_DOFF_OFFSET (0x024034) /* TCD9 Signed Destination Address Offset Register (TCD9_DOFF) */
+#define S32K3XX_EDMA_TCD9_CITER_OFFSET (0x024036) /* TCD9 Current Major Loop Count Register (TCD9_CITER) */
+#define S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET (0x024038) /* TCD9 Last Destination Address Adjustment / Scatter Gather Address Register (TCD9_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD9_CSR_OFFSET (0x02403c) /* TCD9 Control and Status Register (TCD9_CSR) */
+#define S32K3XX_EDMA_TCD9_BITER_OFFSET (0x02403e) /* TCD9 Beginning Major Loop Count Register (TCD9_BITER) */
+
+#define S32K3XX_EDMA_CH10_CSR_OFFSET (0x028000) /* Channel 10 Control and Status Register (CH10_CSR) */
+#define S32K3XX_EDMA_CH10_ES_OFFSET (0x028004) /* Channel 10 Error Status Register (CH10_ES) */
+#define S32K3XX_EDMA_CH10_INT_OFFSET (0x028008) /* Channel 10 Interrupt Status Register (CH10_INT) */
+#define S32K3XX_EDMA_CH10_SBR_OFFSET (0x02800c) /* Channel 10 System Bus Register (CH10_SBR) */
+#define S32K3XX_EDMA_CH10_PRI_OFFSET (0x028010) /* Channel 10 Priority Register (CH10_PRI) */
+#define S32K3XX_EDMA_TCD10_SADDR_OFFSET (0x028020) /* TCD10 Source Address Register (TCD10_SADDR) */
+#define S32K3XX_EDMA_TCD10_SOFF_OFFSET (0x028024) /* TCD10 Signed Source Address Offset Register (TCD10_SOFF) */
+#define S32K3XX_EDMA_TCD10_ATTR_OFFSET (0x028026) /* TCD10 Transfer Attributes (TCD10_ATTR) */
+#define S32K3XX_EDMA_TCD10_NBYTES_OFFSET (0x028028) /* TCD10 Transfer Size (TCD10_NBYTES) */
+#define S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET (0x02802c) /* TCD10 Last Source Address Adjustment / Store DADDR Address Register (TCD10_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD10_DADDR_OFFSET (0x028030) /* TCD10 Destination Address Register (TCD10_DADDR) */
+#define S32K3XX_EDMA_TCD10_DOFF_OFFSET (0x028034) /* TCD10 Signed Destination Address Offset Register (TCD10_DOFF) */
+#define S32K3XX_EDMA_TCD10_CITER_OFFSET (0x028036) /* TCD10 Current Major Loop Count Register (TCD10_CITER) */
+#define S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET (0x028038) /* TCD10 Last Destination Address Adjustment / Scatter Gather Address Register (TCD10_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD10_CSR_OFFSET (0x02803c) /* TCD10 Control and Status Register (TCD10_CSR) */
+#define S32K3XX_EDMA_TCD10_BITER_OFFSET (0x02803e) /* TCD10 Beginning Major Loop Count Register (TCD10_BITER) */
+#define S32K3XX_EDMA_CH11_CSR_OFFSET (0x02c000) /* Channel 11 Control and Status Register (CH11_CSR) */
+#define S32K3XX_EDMA_CH11_ES_OFFSET (0x02c004) /* Channel 11 Error Status Register (CH11_ES) */
+#define S32K3XX_EDMA_CH11_INT_OFFSET (0x02c008) /* Channel 11 Interrupt Status Register (CH11_INT) */
+#define S32K3XX_EDMA_CH11_SBR_OFFSET (0x02c00c) /* Channel 11 System Bus Register (CH11_SBR) */
+#define S32K3XX_EDMA_CH11_PRI_OFFSET (0x02c010) /* Channel 11 Priority Register (CH11_PRI) */
+#define S32K3XX_EDMA_TCD11_SADDR_OFFSET (0x02c020) /* TCD11 Source Address Register (TCD11_SADDR) */
+#define S32K3XX_EDMA_TCD11_SOFF_OFFSET (0x02c024) /* TCD11 Signed Source Address Offset Register (TCD11_SOFF) */
+#define S32K3XX_EDMA_TCD11_ATTR_OFFSET (0x02c026) /* TCD11 Transfer Attributes (TCD11_ATTR) */
+#define S32K3XX_EDMA_TCD11_NBYTES_OFFSET (0x02c028) /* TCD11 Transfer Size (TCD11_NBYTES) */
+#define S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET (0x02c02c) /* TCD11 Last Source Address Adjustment / Store DADDR Address Register (TCD11_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD11_DADDR_OFFSET (0x02c030) /* TCD11 Destination Address Register (TCD11_DADDR) */
+#define S32K3XX_EDMA_TCD11_DOFF_OFFSET (0x02c034) /* TCD11 Signed Destination Address Offset Register (TCD11_DOFF) */
+#define S32K3XX_EDMA_TCD11_CITER_OFFSET (0x02c036) /* TCD11 Current Major Loop Count Register (TCD11_CITER) */
+#define S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET (0x02c038) /* TCD11 Last Destination Address Adjustment / Scatter Gather Address Register (TCD11_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD11_CSR_OFFSET (0x02c03c) /* TCD11 Control and Status Register (TCD11_CSR) */
+#define S32K3XX_EDMA_TCD11_BITER_OFFSET (0x02c03e) /* TCD11 Beginning Major Loop Count Register (TCD11_BITER) */
+
+#define S32K3XX_EDMA_CH12_CSR_OFFSET (0x200000) /* Channel 12 Control and Status Register (CH12_CSR) */
+#define S32K3XX_EDMA_CH12_ES_OFFSET (0x200004) /* Channel 12 Error Status Register (CH12_ES) */
+#define S32K3XX_EDMA_CH12_INT_OFFSET (0x200008) /* Channel 12 Interrupt Status Register (CH12_INT) */
+#define S32K3XX_EDMA_CH12_SBR_OFFSET (0x20000c) /* Channel 12 System Bus Register (CH12_SBR) */
+#define S32K3XX_EDMA_CH12_PRI_OFFSET (0x200010) /* Channel 12 Priority Register (CH12_PRI) */
+#define S32K3XX_EDMA_TCD12_SADDR_OFFSET (0x200020) /* TCD12 Source Address Register (TCD12_SADDR) */
+#define S32K3XX_EDMA_TCD12_SOFF_OFFSET (0x200024) /* TCD12 Signed Source Address Offset Register (TCD12_SOFF) */
+#define S32K3XX_EDMA_TCD12_ATTR_OFFSET (0x200026) /* TCD12 Transfer Attributes (TCD12_ATTR) */
+#define S32K3XX_EDMA_TCD12_NBYTES_OFFSET (0x200028) /* TCD12 Transfer Size (TCD12_NBYTES) */
+#define S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET (0x20002c) /* TCD12 Last Source Address Adjustment / Store DADDR Address Register (TCD12_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD12_DADDR_OFFSET (0x200030) /* TCD12 Destination Address Register (TCD12_DADDR) */
+#define S32K3XX_EDMA_TCD12_DOFF_OFFSET (0x200034) /* TCD12 Signed Destination Address Offset Register (TCD12_DOFF) */
+#define S32K3XX_EDMA_TCD12_CITER_OFFSET (0x200036) /* TCD12 Current Major Loop Count Register (TCD12_CITER) */
+#define S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET (0x200038) /* TCD12 Last Destination Address Adjustment / Scatter Gather Address Register (TCD12_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD12_CSR_OFFSET (0x20003c) /* TCD12 Control and Status Register (TCD12_CSR) */
+#define S32K3XX_EDMA_TCD12_BITER_OFFSET (0x20003e) /* TCD12 Beginning Major Loop Count Register (TCD12_BITER) */
+
+#define S32K3XX_EDMA_CH13_CSR_OFFSET (0x204000) /* Channel 13 Control and Status Register (CH13_CSR) */
+#define S32K3XX_EDMA_CH13_ES_OFFSET (0x204004) /* Channel 13 Error Status Register (CH13_ES) */
+#define S32K3XX_EDMA_CH13_INT_OFFSET (0x204008) /* Channel 13 Interrupt Status Register (CH13_INT) */
+#define S32K3XX_EDMA_CH13_SBR_OFFSET (0x20400c) /* Channel 13 System Bus Register (CH13_SBR) */
+#define S32K3XX_EDMA_CH13_PRI_OFFSET (0x204010) /* Channel 13 Priority Register (CH13_PRI) */
+#define S32K3XX_EDMA_TCD13_SADDR_OFFSET (0x204020) /* TCD13 Source Address Register (TCD13_SADDR) */
+#define S32K3XX_EDMA_TCD13_SOFF_OFFSET (0x204024) /* TCD13 Signed Source Address Offset Register (TCD13_SOFF) */
+#define S32K3XX_EDMA_TCD13_ATTR_OFFSET (0x204026) /* TCD13 Transfer Attributes (TCD13_ATTR) */
+#define S32K3XX_EDMA_TCD13_NBYTES_OFFSET (0x204028) /* TCD13 Transfer Size (TCD13_NBYTES) */
+#define S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET (0x20402c) /* TCD13 Last Source Address Adjustment / Store DADDR Address Register (TCD13_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD13_DADDR_OFFSET (0x204030) /* TCD13 Destination Address Register (TCD13_DADDR) */
+#define S32K3XX_EDMA_TCD13_DOFF_OFFSET (0x204034) /* TCD13 Signed Destination Address Offset Register (TCD13_DOFF) */
+#define S32K3XX_EDMA_TCD13_CITER_OFFSET (0x204036) /* TCD13 Current Major Loop Count Register (TCD13_CITER) */
+#define S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET (0x204038) /* TCD13 Last Destination Address Adjustment / Scatter Gather Address Register (TCD13_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD13_CSR_OFFSET (0x20403c) /* TCD13 Control and Status Register (TCD13_CSR) */
+#define S32K3XX_EDMA_TCD13_BITER_OFFSET (0x20403e) /* TCD13 Beginning Major Loop Count Register (TCD13_BITER) */
+
+#define S32K3XX_EDMA_CH14_CSR_OFFSET (0x208000) /* Channel 14 Control and Status Register (CH14_CSR) */
+#define S32K3XX_EDMA_CH14_ES_OFFSET (0x208004) /* Channel 14 Error Status Register (CH14_ES) */
+#define S32K3XX_EDMA_CH14_INT_OFFSET (0x208008) /* Channel 14 Interrupt Status Register (CH14_INT) */
+#define S32K3XX_EDMA_CH14_SBR_OFFSET (0x20800c) /* Channel 14 System Bus Register (CH14_SBR) */
+#define S32K3XX_EDMA_CH14_PRI_OFFSET (0x208010) /* Channel 14 Priority Register (CH14_PRI) */
+#define S32K3XX_EDMA_TCD14_SADDR_OFFSET (0x208020) /* TCD14 Source Address Register (TCD14_SADDR) */
+#define S32K3XX_EDMA_TCD14_SOFF_OFFSET (0x208024) /* TCD14 Signed Source Address Offset Register (TCD14_SOFF) */
+#define S32K3XX_EDMA_TCD14_ATTR_OFFSET (0x208026) /* TCD14 Transfer Attributes (TCD14_ATTR) */
+#define S32K3XX_EDMA_TCD14_NBYTES_OFFSET (0x208028) /* TCD14 Transfer Size (TCD14_NBYTES) */
+#define S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET (0x20802c) /* TCD14 Last Source Address Adjustment / Store DADDR Address Register (TCD14_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD14_DADDR_OFFSET (0x208030) /* TCD14 Destination Address Register (TCD14_DADDR) */
+#define S32K3XX_EDMA_TCD14_DOFF_OFFSET (0x208034) /* TCD14 Signed Destination Address Offset Register (TCD14_DOFF) */
+#define S32K3XX_EDMA_TCD14_CITER_OFFSET (0x208036) /* TCD14 Current Major Loop Count Register (TCD14_CITER) */
+#define S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET (0x208038) /* TCD14 Last Destination Address Adjustment / Scatter Gather Address Register (TCD14_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD14_CSR_OFFSET (0x20803c) /* TCD14 Control and Status Register (TCD14_CSR) */
+#define S32K3XX_EDMA_TCD14_BITER_OFFSET (0x20803e) /* TCD14 Beginning Major Loop Count Register (TCD14_BITER) */
+
+#define S32K3XX_EDMA_CH15_CSR_OFFSET (0x20c000) /* Channel 15 Control and Status Register (CH15_CSR) */
+#define S32K3XX_EDMA_CH15_ES_OFFSET (0x20c004) /* Channel 15 Error Status Register (CH15_ES) */
+#define S32K3XX_EDMA_CH15_INT_OFFSET (0x20c008) /* Channel 15 Interrupt Status Register (CH15_INT) */
+#define S32K3XX_EDMA_CH15_SBR_OFFSET (0x20c00c) /* Channel 15 System Bus Register (CH15_SBR) */
+#define S32K3XX_EDMA_CH15_PRI_OFFSET (0x20c010) /* Channel 15 Priority Register (CH15_PRI) */
+#define S32K3XX_EDMA_TCD15_SADDR_OFFSET (0x20c020) /* TCD15 Source Address Register (TCD15_SADDR) */
+#define S32K3XX_EDMA_TCD15_SOFF_OFFSET (0x20c024) /* TCD15 Signed Source Address Offset Register (TCD15_SOFF) */
+#define S32K3XX_EDMA_TCD15_ATTR_OFFSET (0x20c026) /* TCD15 Transfer Attributes (TCD15_ATTR) */
+#define S32K3XX_EDMA_TCD15_NBYTES_OFFSET (0x20c028) /* TCD15 Transfer Size (TCD15_NBYTES) */
+#define S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET (0x20c02c) /* TCD15 Last Source Address Adjustment / Store DADDR Address Register (TCD15_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD15_DADDR_OFFSET (0x20c030) /* TCD15 Destination Address Register (TCD15_DADDR) */
+#define S32K3XX_EDMA_TCD15_DOFF_OFFSET (0x20c034) /* TCD15 Signed Destination Address Offset Register (TCD15_DOFF) */
+#define S32K3XX_EDMA_TCD15_CITER_OFFSET (0x20c036) /* TCD15 Current Major Loop Count Register (TCD15_CITER) */
+#define S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET (0x20c038) /* TCD15 Last Destination Address Adjustment / Scatter Gather Address Register (TCD15_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD15_CSR_OFFSET (0x20c03c) /* TCD15 Control and Status Register (TCD15_CSR) */
+#define S32K3XX_EDMA_TCD15_BITER_OFFSET (0x20c03e) /* TCD15 Beginning Major Loop Count Register (TCD15_BITER) */
+
+#define S32K3XX_EDMA_CH16_CSR_OFFSET (0x210000) /* Channel 16 Control and Status Register (CH16_CSR) */
+#define S32K3XX_EDMA_CH16_ES_OFFSET (0x210004) /* Channel 16 Error Status Register (CH16_ES) */
+#define S32K3XX_EDMA_CH16_INT_OFFSET (0x210008) /* Channel 16 Interrupt Status Register (CH16_INT) */
+#define S32K3XX_EDMA_CH16_SBR_OFFSET (0x21000c) /* Channel 16 System Bus Register (CH16_SBR) */
+#define S32K3XX_EDMA_CH16_PRI_OFFSET (0x210010) /* Channel 16 Priority Register (CH16_PRI) */
+#define S32K3XX_EDMA_TCD16_SADDR_OFFSET (0x210020) /* TCD16 Source Address Register (TCD16_SADDR) */
+#define S32K3XX_EDMA_TCD16_SOFF_OFFSET (0x210024) /* TCD16 Signed Source Address Offset Register (TCD16_SOFF) */
+#define S32K3XX_EDMA_TCD16_ATTR_OFFSET (0x210026) /* TCD16 Transfer Attributes (TCD16_ATTR) */
+#define S32K3XX_EDMA_TCD16_NBYTES_OFFSET (0x210028) /* TCD16 Transfer Size (TCD16_NBYTES) */
+#define S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET (0x21002c) /* TCD16 Last Source Address Adjustment / Store DADDR Address Register (TCD16_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD16_DADDR_OFFSET (0x210030) /* TCD16 Destination Address Register (TCD16_DADDR) */
+#define S32K3XX_EDMA_TCD16_DOFF_OFFSET (0x210034) /* TCD16 Signed Destination Address Offset Register (TCD16_DOFF) */
+#define S32K3XX_EDMA_TCD16_CITER_OFFSET (0x210036) /* TCD16 Current Major Loop Count Register (TCD16_CITER) */
+#define S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET (0x210038) /* TCD16 Last Destination Address Adjustment / Scatter Gather Address Register (TCD16_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD16_CSR_OFFSET (0x21003c) /* TCD16 Control and Status Register (TCD16_CSR) */
+#define S32K3XX_EDMA_TCD16_BITER_OFFSET (0x21003e) /* TCD16 Beginning Major Loop Count Register (TCD16_BITER) */
+
+#define S32K3XX_EDMA_CH17_CSR_OFFSET (0x214000) /* Channel 17 Control and Status Register (CH17_CSR) */
+#define S32K3XX_EDMA_CH17_ES_OFFSET (0x214004) /* Channel 17 Error Status Register (CH17_ES) */
+#define S32K3XX_EDMA_CH17_INT_OFFSET (0x214008) /* Channel 17 Interrupt Status Register (CH17_INT) */
+#define S32K3XX_EDMA_CH17_SBR_OFFSET (0x21400c) /* Channel 17 System Bus Register (CH17_SBR) */
+#define S32K3XX_EDMA_CH17_PRI_OFFSET (0x214010) /* Channel 17 Priority Register (CH17_PRI) */
+#define S32K3XX_EDMA_TCD17_SADDR_OFFSET (0x214020) /* TCD17 Source Address Register (TCD17_SADDR) */
+#define S32K3XX_EDMA_TCD17_SOFF_OFFSET (0x214024) /* TCD17 Signed Source Address Offset Register (TCD17_SOFF) */
+#define S32K3XX_EDMA_TCD17_ATTR_OFFSET (0x214026) /* TCD17 Transfer Attributes (TCD17_ATTR) */
+#define S32K3XX_EDMA_TCD17_NBYTES_OFFSET (0x214028) /* TCD17 Transfer Size (TCD17_NBYTES) */
+#define S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET (0x21402c) /* TCD17 Last Source Address Adjustment / Store DADDR Address Register (TCD17_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD17_DADDR_OFFSET (0x214030) /* TCD17 Destination Address Register (TCD17_DADDR) */
+#define S32K3XX_EDMA_TCD17_DOFF_OFFSET (0x214034) /* TCD17 Signed Destination Address Offset Register (TCD17_DOFF) */
+#define S32K3XX_EDMA_TCD17_CITER_OFFSET (0x214036) /* TCD17 Current Major Loop Count Register (TCD17_CITER) */
+#define S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET (0x214038) /* TCD17 Last Destination Address Adjustment / Scatter Gather Address Register (TCD17_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD17_CSR_OFFSET (0x21403c) /* TCD17 Control and Status Register (TCD17_CSR) */
+#define S32K3XX_EDMA_TCD17_BITER_OFFSET (0x21403e) /* TCD17 Beginning Major Loop Count Register (TCD17_BITER) */
+
+#define S32K3XX_EDMA_CH18_CSR_OFFSET (0x218000) /* Channel 18 Control and Status Register (CH18_CSR) */
+#define S32K3XX_EDMA_CH18_ES_OFFSET (0x218004) /* Channel 18 Error Status Register (CH18_ES) */
+#define S32K3XX_EDMA_CH18_INT_OFFSET (0x218008) /* Channel 18 Interrupt Status Register (CH18_INT) */
+#define S32K3XX_EDMA_CH18_SBR_OFFSET (0x21800c) /* Channel 18 System Bus Register (CH18_SBR) */
+#define S32K3XX_EDMA_CH18_PRI_OFFSET (0x218010) /* Channel 18 Priority Register (CH18_PRI) */
+#define S32K3XX_EDMA_TCD18_SADDR_OFFSET (0x218020) /* TCD18 Source Address Register (TCD18_SADDR) */
+#define S32K3XX_EDMA_TCD18_SOFF_OFFSET (0x218024) /* TCD18 Signed Source Address Offset Register (TCD18_SOFF) */
+#define S32K3XX_EDMA_TCD18_ATTR_OFFSET (0x218026) /* TCD18 Transfer Attributes (TCD18_ATTR) */
+#define S32K3XX_EDMA_TCD18_NBYTES_OFFSET (0x218028) /* TCD18 Transfer Size (TCD18_NBYTES) */
+#define S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET (0x21802c) /* TCD18 Last Source Address Adjustment / Store DADDR Address Register (TCD18_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD18_DADDR_OFFSET (0x218030) /* TCD18 Destination Address Register (TCD18_DADDR) */
+#define S32K3XX_EDMA_TCD18_DOFF_OFFSET (0x218034) /* TCD18 Signed Destination Address Offset Register (TCD18_DOFF) */
+#define S32K3XX_EDMA_TCD18_CITER_OFFSET (0x218036) /* TCD18 Current Major Loop Count Register (TCD18_CITER) */
+#define S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET (0x218038) /* TCD18 Last Destination Address Adjustment / Scatter Gather Address Register (TCD18_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD18_CSR_OFFSET (0x21803c) /* TCD18 Control and Status Register (TCD18_CSR) */
+#define S32K3XX_EDMA_TCD18_BITER_OFFSET (0x21803e) /* TCD18 Beginning Major Loop Count Register (TCD18_BITER) */
+
+#define S32K3XX_EDMA_CH19_CSR_OFFSET (0x21c000) /* Channel 19 Control and Status Register (CH19_CSR) */
+#define S32K3XX_EDMA_CH19_ES_OFFSET (0x21c004) /* Channel 19 Error Status Register (CH19_ES) */
+#define S32K3XX_EDMA_CH19_INT_OFFSET (0x21c008) /* Channel 19 Interrupt Status Register (CH19_INT) */
+#define S32K3XX_EDMA_CH19_SBR_OFFSET (0x21c00c) /* Channel 19 System Bus Register (CH19_SBR) */
+#define S32K3XX_EDMA_CH19_PRI_OFFSET (0x21c010) /* Channel 19 Priority Register (CH19_PRI) */
+#define S32K3XX_EDMA_TCD19_SADDR_OFFSET (0x21c020) /* TCD19 Source Address Register (TCD19_SADDR) */
+#define S32K3XX_EDMA_TCD19_SOFF_OFFSET (0x21c024) /* TCD19 Signed Source Address Offset Register (TCD19_SOFF) */
+#define S32K3XX_EDMA_TCD19_ATTR_OFFSET (0x21c026) /* TCD19 Transfer Attributes (TCD19_ATTR) */
+#define S32K3XX_EDMA_TCD19_NBYTES_OFFSET (0x21c028) /* TCD19 Transfer Size (TCD19_NBYTES) */
+#define S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET (0x21c02c) /* TCD19 Last Source Address Adjustment / Store DADDR Address Register (TCD19_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD19_DADDR_OFFSET (0x21c030) /* TCD19 Destination Address Register (TCD19_DADDR) */
+#define S32K3XX_EDMA_TCD19_DOFF_OFFSET (0x21c034) /* TCD19 Signed Destination Address Offset Register (TCD19_DOFF) */
+#define S32K3XX_EDMA_TCD19_CITER_OFFSET (0x21c036) /* TCD19 Current Major Loop Count Register (TCD19_CITER) */
+#define S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET (0x21c038) /* TCD19 Last Destination Address Adjustment / Scatter Gather Address Register (TCD19_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD19_CSR_OFFSET (0x21c03c) /* TCD19 Control and Status Register (TCD19_CSR) */
+#define S32K3XX_EDMA_TCD19_BITER_OFFSET (0x21c03e) /* TCD19 Beginning Major Loop Count Register (TCD19_BITER) */
+
+#define S32K3XX_EDMA_CH20_CSR_OFFSET (0x220000) /* Channel 20 Control and Status Register (CH20_CSR) */
+#define S32K3XX_EDMA_CH20_ES_OFFSET (0x220004) /* Channel 20 Error Status Register (CH20_ES) */
+#define S32K3XX_EDMA_CH20_INT_OFFSET (0x220008) /* Channel 20 Interrupt Status Register (CH20_INT) */
+#define S32K3XX_EDMA_CH20_SBR_OFFSET (0x22000c) /* Channel 20 System Bus Register (CH20_SBR) */
+#define S32K3XX_EDMA_CH20_PRI_OFFSET (0x220010) /* Channel 20 Priority Register (CH20_PRI) */
+#define S32K3XX_EDMA_TCD20_SADDR_OFFSET (0x220020) /* TCD20 Source Address Register (TCD20_SADDR) */
+#define S32K3XX_EDMA_TCD20_SOFF_OFFSET (0x220024) /* TCD20 Signed Source Address Offset Register (TCD20_SOFF) */
+#define S32K3XX_EDMA_TCD20_ATTR_OFFSET (0x220026) /* TCD20 Transfer Attributes (TCD20_ATTR) */
+#define S32K3XX_EDMA_TCD20_NBYTES_OFFSET (0x220028) /* TCD20 Transfer Size (TCD20_NBYTES) */
+#define S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET (0x22002c) /* TCD20 Last Source Address Adjustment / Store DADDR Address Register (TCD20_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD20_DADDR_OFFSET (0x220030) /* TCD20 Destination Address Register (TCD20_DADDR) */
+#define S32K3XX_EDMA_TCD20_DOFF_OFFSET (0x220034) /* TCD20 Signed Destination Address Offset Register (TCD20_DOFF) */
+#define S32K3XX_EDMA_TCD20_CITER_OFFSET (0x220036) /* TCD20 Current Major Loop Count Register (TCD20_CITER) */
+#define S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET (0x220038) /* TCD20 Last Destination Address Adjustment / Scatter Gather Address Register (TCD20_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD20_CSR_OFFSET (0x22003c) /* TCD20 Control and Status Register (TCD20_CSR) */
+#define S32K3XX_EDMA_TCD20_BITER_OFFSET (0x22003e) /* TCD20 Beginning Major Loop Count Register (TCD20_BITER) */
+
+#define S32K3XX_EDMA_CH21_CSR_OFFSET (0x224000) /* Channel 21 Control and Status Register (CH21_CSR) */
+#define S32K3XX_EDMA_CH21_ES_OFFSET (0x224004) /* Channel 21 Error Status Register (CH21_ES) */
+#define S32K3XX_EDMA_CH21_INT_OFFSET (0x224008) /* Channel 21 Interrupt Status Register (CH21_INT) */
+#define S32K3XX_EDMA_CH21_SBR_OFFSET (0x22400c) /* Channel 21 System Bus Register (CH21_SBR) */
+#define S32K3XX_EDMA_CH21_PRI_OFFSET (0x224010) /* Channel 21 Priority Register (CH21_PRI) */
+#define S32K3XX_EDMA_TCD21_SADDR_OFFSET (0x224020) /* TCD21 Source Address Register (TCD21_SADDR) */
+#define S32K3XX_EDMA_TCD21_SOFF_OFFSET (0x224024) /* TCD21 Signed Source Address Offset Register (TCD21_SOFF) */
+#define S32K3XX_EDMA_TCD21_ATTR_OFFSET (0x224026) /* TCD21 Transfer Attributes (TCD21_ATTR) */
+#define S32K3XX_EDMA_TCD21_NBYTES_OFFSET (0x224028) /* TCD21 Transfer Size (TCD21_NBYTES) */
+#define S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET (0x22402c) /* TCD21 Last Source Address Adjustment / Store DADDR Address Register (TCD21_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD21_DADDR_OFFSET (0x224030) /* TCD21 Destination Address Register (TCD21_DADDR) */
+#define S32K3XX_EDMA_TCD21_DOFF_OFFSET (0x224034) /* TCD21 Signed Destination Address Offset Register (TCD21_DOFF) */
+#define S32K3XX_EDMA_TCD21_CITER_OFFSET (0x224036) /* TCD21 Current Major Loop Count Register (TCD21_CITER) */
+#define S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET (0x224038) /* TCD21 Last Destination Address Adjustment / Scatter Gather Address Register (TCD21_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD21_CSR_OFFSET (0x22403c) /* TCD21 Control and Status Register (TCD21_CSR) */
+#define S32K3XX_EDMA_TCD21_BITER_OFFSET (0x22403e) /* TCD21 Beginning Major Loop Count Register (TCD21_BITER) */
+
+#define S32K3XX_EDMA_CH22_CSR_OFFSET (0x228000) /* Channel 22 Control and Status Register (CH22_CSR) */
+#define S32K3XX_EDMA_CH22_ES_OFFSET (0x228004) /* Channel 22 Error Status Register (CH22_ES) */
+#define S32K3XX_EDMA_CH22_INT_OFFSET (0x228008) /* Channel 22 Interrupt Status Register (CH22_INT) */
+#define S32K3XX_EDMA_CH22_SBR_OFFSET (0x22800c) /* Channel 22 System Bus Register (CH22_SBR) */
+#define S32K3XX_EDMA_CH22_PRI_OFFSET (0x228010) /* Channel 22 Priority Register (CH22_PRI) */
+#define S32K3XX_EDMA_TCD22_SADDR_OFFSET (0x228020) /* TCD22 Source Address Register (TCD22_SADDR) */
+#define S32K3XX_EDMA_TCD22_SOFF_OFFSET (0x228024) /* TCD22 Signed Source Address Offset Register (TCD22_SOFF) */
+#define S32K3XX_EDMA_TCD22_ATTR_OFFSET (0x228026) /* TCD22 Transfer Attributes (TCD22_ATTR) */
+#define S32K3XX_EDMA_TCD22_NBYTES_OFFSET (0x228028) /* TCD22 Transfer Size (TCD22_NBYTES) */
+#define S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET (0x22802c) /* TCD22 Last Source Address Adjustment / Store DADDR Address Register (TCD22_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD22_DADDR_OFFSET (0x228030) /* TCD22 Destination Address Register (TCD22_DADDR) */
+#define S32K3XX_EDMA_TCD22_DOFF_OFFSET (0x228034) /* TCD22 Signed Destination Address Offset Register (TCD22_DOFF) */
+#define S32K3XX_EDMA_TCD22_CITER_OFFSET (0x228036) /* TCD22 Current Major Loop Count Register (TCD22_CITER) */
+#define S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET (0x228038) /* TCD22 Last Destination Address Adjustment / Scatter Gather Address Register (TCD22_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD22_CSR_OFFSET (0x22803c) /* TCD22 Control and Status Register (TCD22_CSR) */
+#define S32K3XX_EDMA_TCD22_BITER_OFFSET (0x22803e) /* TCD22 Beginning Major Loop Count Register (TCD22_BITER) */
+
+#define S32K3XX_EDMA_CH23_CSR_OFFSET (0x22c000) /* Channel 23 Control and Status Register (CH23_CSR) */
+#define S32K3XX_EDMA_CH23_ES_OFFSET (0x22c004) /* Channel 23 Error Status Register (CH23_ES) */
+#define S32K3XX_EDMA_CH23_INT_OFFSET (0x22c008) /* Channel 23 Interrupt Status Register (CH23_INT) */
+#define S32K3XX_EDMA_CH23_SBR_OFFSET (0x22c00c) /* Channel 23 System Bus Register (CH23_SBR) */
+#define S32K3XX_EDMA_CH23_PRI_OFFSET (0x22c010) /* Channel 23 Priority Register (CH23_PRI) */
+#define S32K3XX_EDMA_TCD23_SADDR_OFFSET (0x22c020) /* TCD23 Source Address Register (TCD23_SADDR) */
+#define S32K3XX_EDMA_TCD23_SOFF_OFFSET (0x22c024) /* TCD23 Signed Source Address Offset Register (TCD23_SOFF) */
+#define S32K3XX_EDMA_TCD23_ATTR_OFFSET (0x22c026) /* TCD23 Transfer Attributes (TCD23_ATTR) */
+#define S32K3XX_EDMA_TCD23_NBYTES_OFFSET (0x22c028) /* TCD23 Transfer Size (TCD23_NBYTES) */
+#define S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET (0x22c02c) /* TCD23 Last Source Address Adjustment / Store DADDR Address Register (TCD23_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD23_DADDR_OFFSET (0x22c030) /* TCD23 Destination Address Register (TCD23_DADDR) */
+#define S32K3XX_EDMA_TCD23_DOFF_OFFSET (0x22c034) /* TCD23 Signed Destination Address Offset Register (TCD23_DOFF) */
+#define S32K3XX_EDMA_TCD23_CITER_OFFSET (0x22c036) /* TCD23 Current Major Loop Count Register (TCD23_CITER) */
+#define S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET (0x22c038) /* TCD23 Last Destination Address Adjustment / Scatter Gather Address Register (TCD23_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD23_CSR_OFFSET (0x22c03c) /* TCD23 Control and Status Register (TCD23_CSR) */
+#define S32K3XX_EDMA_TCD23_BITER_OFFSET (0x22c03e) /* TCD23 Beginning Major Loop Count Register (TCD23_BITER) */
+
+#define S32K3XX_EDMA_CH24_CSR_OFFSET (0x230000) /* Channel 24 Control and Status Register (CH24_CSR) */
+#define S32K3XX_EDMA_CH24_ES_OFFSET (0x230004) /* Channel 24 Error Status Register (CH24_ES) */
+#define S32K3XX_EDMA_CH24_INT_OFFSET (0x230008) /* Channel 24 Interrupt Status Register (CH24_INT) */
+#define S32K3XX_EDMA_CH24_SBR_OFFSET (0x23000c) /* Channel 24 System Bus Register (CH24_SBR) */
+#define S32K3XX_EDMA_CH24_PRI_OFFSET (0x230010) /* Channel 24 Priority Register (CH24_PRI) */
+#define S32K3XX_EDMA_TCD24_SADDR_OFFSET (0x230020) /* TCD24 Source Address Register (TCD24_SADDR) */
+#define S32K3XX_EDMA_TCD24_SOFF_OFFSET (0x230024) /* TCD24 Signed Source Address Offset Register (TCD24_SOFF) */
+#define S32K3XX_EDMA_TCD24_ATTR_OFFSET (0x230026) /* TCD24 Transfer Attributes (TCD24_ATTR) */
+#define S32K3XX_EDMA_TCD24_NBYTES_OFFSET (0x230028) /* TCD24 Transfer Size (TCD24_NBYTES) */
+#define S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET (0x23002c) /* TCD24 Last Source Address Adjustment / Store DADDR Address Register (TCD24_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD24_DADDR_OFFSET (0x230030) /* TCD24 Destination Address Register (TCD24_DADDR) */
+#define S32K3XX_EDMA_TCD24_DOFF_OFFSET (0x230034) /* TCD24 Signed Destination Address Offset Register (TCD24_DOFF) */
+#define S32K3XX_EDMA_TCD24_CITER_OFFSET (0x230036) /* TCD24 Current Major Loop Count Register (TCD24_CITER) */
+#define S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET (0x230038) /* TCD24 Last Destination Address Adjustment / Scatter Gather Address Register (TCD24_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD24_CSR_OFFSET (0x23003c) /* TCD24 Control and Status Register (TCD24_CSR) */
+#define S32K3XX_EDMA_TCD24_BITER_OFFSET (0x23003e) /* TCD24 Beginning Major Loop Count Register (TCD24_BITER) */
+
+#define S32K3XX_EDMA_CH25_CSR_OFFSET (0x234000) /* Channel 25 Control and Status Register (CH25_CSR) */
+#define S32K3XX_EDMA_CH25_ES_OFFSET (0x234004) /* Channel 25 Error Status Register (CH25_ES) */
+#define S32K3XX_EDMA_CH25_INT_OFFSET (0x234008) /* Channel 25 Interrupt Status Register (CH25_INT) */
+#define S32K3XX_EDMA_CH25_SBR_OFFSET (0x23400c) /* Channel 25 System Bus Register (CH25_SBR) */
+#define S32K3XX_EDMA_CH25_PRI_OFFSET (0x234010) /* Channel 25 Priority Register (CH25_PRI) */
+#define S32K3XX_EDMA_TCD25_SADDR_OFFSET (0x234020) /* TCD25 Source Address Register (TCD25_SADDR) */
+#define S32K3XX_EDMA_TCD25_SOFF_OFFSET (0x234024) /* TCD25 Signed Source Address Offset Register (TCD25_SOFF) */
+#define S32K3XX_EDMA_TCD25_ATTR_OFFSET (0x234026) /* TCD25 Transfer Attributes (TCD25_ATTR) */
+#define S32K3XX_EDMA_TCD25_NBYTES_OFFSET (0x234028) /* TCD25 Transfer Size (TCD25_NBYTES) */
+#define S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET (0x23402c) /* TCD25 Last Source Address Adjustment / Store DADDR Address Register (TCD25_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD25_DADDR_OFFSET (0x234030) /* TCD25 Destination Address Register (TCD25_DADDR) */
+#define S32K3XX_EDMA_TCD25_DOFF_OFFSET (0x234034) /* TCD25 Signed Destination Address Offset Register (TCD25_DOFF) */
+#define S32K3XX_EDMA_TCD25_CITER_OFFSET (0x234036) /* TCD25 Current Major Loop Count Register (TCD25_CITER) */
+#define S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET (0x234038) /* TCD25 Last Destination Address Adjustment / Scatter Gather Address Register (TCD25_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD25_CSR_OFFSET (0x23403c) /* TCD25 Control and Status Register (TCD25_CSR) */
+#define S32K3XX_EDMA_TCD25_BITER_OFFSET (0x23403e) /* TCD25 Beginning Major Loop Count Register (TCD25_BITER) */
+
+#define S32K3XX_EDMA_CH26_CSR_OFFSET (0x238000) /* Channel 26 Control and Status Register (CH26_CSR) */
+#define S32K3XX_EDMA_CH26_ES_OFFSET (0x238004) /* Channel 26 Error Status Register (CH26_ES) */
+#define S32K3XX_EDMA_CH26_INT_OFFSET (0x238008) /* Channel 26 Interrupt Status Register (CH26_INT) */
+#define S32K3XX_EDMA_CH26_SBR_OFFSET (0x23800c) /* Channel 26 System Bus Register (CH26_SBR) */
+#define S32K3XX_EDMA_CH26_PRI_OFFSET (0x238010) /* Channel 26 Priority Register (CH26_PRI) */
+#define S32K3XX_EDMA_TCD26_SADDR_OFFSET (0x238020) /* TCD26 Source Address Register (TCD26_SADDR) */
+#define S32K3XX_EDMA_TCD26_SOFF_OFFSET (0x238024) /* TCD26 Signed Source Address Offset Register (TCD26_SOFF) */
+#define S32K3XX_EDMA_TCD26_ATTR_OFFSET (0x238026) /* TCD26 Transfer Attributes (TCD26_ATTR) */
+#define S32K3XX_EDMA_TCD26_NBYTES_OFFSET (0x238028) /* TCD26 Transfer Size (TCD26_NBYTES) */
+#define S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET (0x23802c) /* TCD26 Last Source Address Adjustment / Store DADDR Address Register (TCD26_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD26_DADDR_OFFSET (0x238030) /* TCD26 Destination Address Register (TCD26_DADDR) */
+#define S32K3XX_EDMA_TCD26_DOFF_OFFSET (0x238034) /* TCD26 Signed Destination Address Offset Register (TCD26_DOFF) */
+#define S32K3XX_EDMA_TCD26_CITER_OFFSET (0x238036) /* TCD26 Current Major Loop Count Register (TCD26_CITER) */
+#define S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET (0x238038) /* TCD26 Last Destination Address Adjustment / Scatter Gather Address Register (TCD26_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD26_CSR_OFFSET (0x23803c) /* TCD26 Control and Status Register (TCD26_CSR) */
+#define S32K3XX_EDMA_TCD26_BITER_OFFSET (0x23803e) /* TCD26 Beginning Major Loop Count Register (TCD26_BITER) */
+
+#define S32K3XX_EDMA_CH27_CSR_OFFSET (0x23c000) /* Channel 27 Control and Status Register (CH27_CSR) */
+#define S32K3XX_EDMA_CH27_ES_OFFSET (0x23c004) /* Channel 27 Error Status Register (CH27_ES) */
+#define S32K3XX_EDMA_CH27_INT_OFFSET (0x23c008) /* Channel 27 Interrupt Status Register (CH27_INT) */
+#define S32K3XX_EDMA_CH27_SBR_OFFSET (0x23c00c) /* Channel 27 System Bus Register (CH27_SBR) */
+#define S32K3XX_EDMA_CH27_PRI_OFFSET (0x23c010) /* Channel 27 Priority Register (CH27_PRI) */
+#define S32K3XX_EDMA_TCD27_SADDR_OFFSET (0x23c020) /* TCD27 Source Address Register (TCD27_SADDR) */
+#define S32K3XX_EDMA_TCD27_SOFF_OFFSET (0x23c024) /* TCD27 Signed Source Address Offset Register (TCD27_SOFF) */
+#define S32K3XX_EDMA_TCD27_ATTR_OFFSET (0x23c026) /* TCD27 Transfer Attributes (TCD27_ATTR) */
+#define S32K3XX_EDMA_TCD27_NBYTES_OFFSET (0x23c028) /* TCD27 Transfer Size (TCD27_NBYTES) */
+#define S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET (0x23c02c) /* TCD27 Last Source Address Adjustment / Store DADDR Address Register (TCD27_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD27_DADDR_OFFSET (0x23c030) /* TCD27 Destination Address Register (TCD27_DADDR) */
+#define S32K3XX_EDMA_TCD27_DOFF_OFFSET (0x23c034) /* TCD27 Signed Destination Address Offset Register (TCD27_DOFF) */
+#define S32K3XX_EDMA_TCD27_CITER_OFFSET (0x23c036) /* TCD27 Current Major Loop Count Register (TCD27_CITER) */
+#define S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET (0x23c038) /* TCD27 Last Destination Address Adjustment / Scatter Gather Address Register (TCD27_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD27_CSR_OFFSET (0x23c03c) /* TCD27 Control and Status Register (TCD27_CSR) */
+#define S32K3XX_EDMA_TCD27_BITER_OFFSET (0x23c03e) /* TCD27 Beginning Major Loop Count Register (TCD27_BITER) */
+
+#define S32K3XX_EDMA_CH28_CSR_OFFSET (0x240000) /* Channel 28 Control and Status Register (CH28_CSR) */
+#define S32K3XX_EDMA_CH28_ES_OFFSET (0x240004) /* Channel 28 Error Status Register (CH28_ES) */
+#define S32K3XX_EDMA_CH28_INT_OFFSET (0x240008) /* Channel 28 Interrupt Status Register (CH28_INT) */
+#define S32K3XX_EDMA_CH28_SBR_OFFSET (0x24000c) /* Channel 28 System Bus Register (CH28_SBR) */
+#define S32K3XX_EDMA_CH28_PRI_OFFSET (0x240010) /* Channel 28 Priority Register (CH28_PRI) */
+#define S32K3XX_EDMA_TCD28_SADDR_OFFSET (0x240020) /* TCD28 Source Address Register (TCD28_SADDR) */
+#define S32K3XX_EDMA_TCD28_SOFF_OFFSET (0x240024) /* TCD28 Signed Source Address Offset Register (TCD28_SOFF) */
+#define S32K3XX_EDMA_TCD28_ATTR_OFFSET (0x240026) /* TCD28 Transfer Attributes (TCD28_ATTR) */
+#define S32K3XX_EDMA_TCD28_NBYTES_OFFSET (0x240028) /* TCD28 Transfer Size (TCD28_NBYTES) */
+#define S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET (0x24002c) /* TCD28 Last Source Address Adjustment / Store DADDR Address Register (TCD28_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD28_DADDR_OFFSET (0x240030) /* TCD28 Destination Address Register (TCD28_DADDR) */
+#define S32K3XX_EDMA_TCD28_DOFF_OFFSET (0x240034) /* TCD28 Signed Destination Address Offset Register (TCD28_DOFF) */
+#define S32K3XX_EDMA_TCD28_CITER_OFFSET (0x240036) /* TCD28 Current Major Loop Count Register (TCD28_CITER) */
+#define S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET (0x240038) /* TCD28 Last Destination Address Adjustment / Scatter Gather Address Register (TCD28_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD28_CSR_OFFSET (0x24003c) /* TCD28 Control and Status Register (TCD28_CSR) */
+#define S32K3XX_EDMA_TCD28_BITER_OFFSET (0x24003e) /* TCD28 Beginning Major Loop Count Register (TCD28_BITER) */
+
+#define S32K3XX_EDMA_CH29_CSR_OFFSET (0x244000) /* Channel 29 Control and Status Register (CH29_CSR) */
+#define S32K3XX_EDMA_CH29_ES_OFFSET (0x244004) /* Channel 29 Error Status Register (CH29_ES) */
+#define S32K3XX_EDMA_CH29_INT_OFFSET (0x244008) /* Channel 29 Interrupt Status Register (CH29_INT) */
+#define S32K3XX_EDMA_CH29_SBR_OFFSET (0x24400c) /* Channel 29 System Bus Register (CH29_SBR) */
+#define S32K3XX_EDMA_CH29_PRI_OFFSET (0x244010) /* Channel 29 Priority Register (CH29_PRI) */
+#define S32K3XX_EDMA_TCD29_SADDR_OFFSET (0x244020) /* TCD29 Source Address Register (TCD29_SADDR) */
+#define S32K3XX_EDMA_TCD29_SOFF_OFFSET (0x244024) /* TCD29 Signed Source Address Offset Register (TCD29_SOFF) */
+#define S32K3XX_EDMA_TCD29_ATTR_OFFSET (0x244026) /* TCD29 Transfer Attributes (TCD29_ATTR) */
+#define S32K3XX_EDMA_TCD29_NBYTES_OFFSET (0x244028) /* TCD29 Transfer Size (TCD29_NBYTES) */
+#define S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET (0x24402c) /* TCD29 Last Source Address Adjustment / Store DADDR Address Register (TCD29_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD29_DADDR_OFFSET (0x244030) /* TCD29 Destination Address Register (TCD29_DADDR) */
+#define S32K3XX_EDMA_TCD29_DOFF_OFFSET (0x244034) /* TCD29 Signed Destination Address Offset Register (TCD29_DOFF) */
+#define S32K3XX_EDMA_TCD29_CITER_OFFSET (0x244036) /* TCD29 Current Major Loop Count Register (TCD29_CITER) */
+#define S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET (0x244038) /* TCD29 Last Destination Address Adjustment / Scatter Gather Address Register (TCD29_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD29_CSR_OFFSET (0x24403c) /* TCD29 Control and Status Register (TCD29_CSR) */
+#define S32K3XX_EDMA_TCD29_BITER_OFFSET (0x24403e) /* TCD29 Beginning Major Loop Count Register (TCD29_BITER) */
+
+#define S32K3XX_EDMA_CH30_CSR_OFFSET (0x248000) /* Channel 30 Control and Status Register (CH30_CSR) */
+#define S32K3XX_EDMA_CH30_ES_OFFSET (0x248004) /* Channel 30 Error Status Register (CH30_ES) */
+#define S32K3XX_EDMA_CH30_INT_OFFSET (0x248008) /* Channel 30 Interrupt Status Register (CH30_INT) */
+#define S32K3XX_EDMA_CH30_SBR_OFFSET (0x24800c) /* Channel 30 System Bus Register (CH30_SBR) */
+#define S32K3XX_EDMA_CH30_PRI_OFFSET (0x248010) /* Channel 30 Priority Register (CH30_PRI) */
+#define S32K3XX_EDMA_TCD30_SADDR_OFFSET (0x248020) /* TCD30 Source Address Register (TCD30_SADDR) */
+#define S32K3XX_EDMA_TCD30_SOFF_OFFSET (0x248024) /* TCD30 Signed Source Address Offset Register (TCD30_SOFF) */
+#define S32K3XX_EDMA_TCD30_ATTR_OFFSET (0x248026) /* TCD30 Transfer Attributes (TCD30_ATTR) */
+#define S32K3XX_EDMA_TCD30_NBYTES_OFFSET (0x248028) /* TCD30 Transfer Size (TCD30_NBYTES) */
+#define S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET (0x24802c) /* TCD30 Last Source Address Adjustment / Store DADDR Address Register (TCD30_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD30_DADDR_OFFSET (0x248030) /* TCD30 Destination Address Register (TCD30_DADDR) */
+#define S32K3XX_EDMA_TCD30_DOFF_OFFSET (0x248034) /* TCD30 Signed Destination Address Offset Register (TCD30_DOFF) */
+#define S32K3XX_EDMA_TCD30_CITER_OFFSET (0x248036) /* TCD30 Current Major Loop Count Register (TCD30_CITER) */
+#define S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET (0x248038) /* TCD30 Last Destination Address Adjustment / Scatter Gather Address Register (TCD30_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD30_CSR_OFFSET (0x24803c) /* TCD30 Control and Status Register (TCD30_CSR) */
+#define S32K3XX_EDMA_TCD30_BITER_OFFSET (0x24803e) /* TCD30 Beginning Major Loop Count Register (TCD30_BITER) */
+
+#define S32K3XX_EDMA_CH31_CSR_OFFSET (0x24c000) /* Channel 31 Control and Status Register (CH31_CSR) */
+#define S32K3XX_EDMA_CH31_ES_OFFSET (0x24c004) /* Channel 31 Error Status Register (CH31_ES) */
+#define S32K3XX_EDMA_CH31_INT_OFFSET (0x24c008) /* Channel 31 Interrupt Status Register (CH31_INT) */
+#define S32K3XX_EDMA_CH31_SBR_OFFSET (0x24c00c) /* Channel 31 System Bus Register (CH31_SBR) */
+#define S32K3XX_EDMA_CH31_PRI_OFFSET (0x24c010) /* Channel 31 Priority Register (CH31_PRI) */
+#define S32K3XX_EDMA_TCD31_SADDR_OFFSET (0x24c020) /* TCD31 Source Address Register (TCD31_SADDR) */
+#define S32K3XX_EDMA_TCD31_SOFF_OFFSET (0x24c024) /* TCD31 Signed Source Address Offset Register (TCD31_SOFF) */
+#define S32K3XX_EDMA_TCD31_ATTR_OFFSET (0x24c026) /* TCD31 Transfer Attributes (TCD31_ATTR) */
+#define S32K3XX_EDMA_TCD31_NBYTES_OFFSET (0x24c028) /* TCD31 Transfer Size (TCD31_NBYTES) */
+#define S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET (0x24c02c) /* TCD31 Last Source Address Adjustment / Store DADDR Address Register (TCD31_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD31_DADDR_OFFSET (0x24c030) /* TCD31 Destination Address Register (TCD31_DADDR) */
+#define S32K3XX_EDMA_TCD31_DOFF_OFFSET (0x24c034) /* TCD31 Signed Destination Address Offset Register (TCD31_DOFF) */
+#define S32K3XX_EDMA_TCD31_CITER_OFFSET (0x24c036) /* TCD31 Current Major Loop Count Register (TCD31_CITER) */
+#define S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET (0x24c038) /* TCD31 Last Destination Address Adjustment / Scatter Gather Address Register (TCD31_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD31_CSR_OFFSET (0x24c03c) /* TCD31 Control and Status Register (TCD31_CSR) */
+#define S32K3XX_EDMA_TCD31_BITER_OFFSET (0x24c03e) /* TCD31 Beginning Major Loop Count Register (TCD31_BITER) */
+
+/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/
+
+#define S32K3XX_EDMA_CH0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_CSR_OFFSET)
+#define S32K3XX_EDMA_CH0_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_ES_OFFSET)
+#define S32K3XX_EDMA_CH0_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_INT_OFFSET)
+#define S32K3XX_EDMA_CH0_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_SBR_OFFSET)
+#define S32K3XX_EDMA_CH0_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD0_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD0_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD0_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD0_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD0_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD0_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_CSR_OFFSET)
+#define S32K3XX_EDMA_CH1_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_ES_OFFSET)
+#define S32K3XX_EDMA_CH1_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_INT_OFFSET)
+#define S32K3XX_EDMA_CH1_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_SBR_OFFSET)
+#define S32K3XX_EDMA_CH1_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD1_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD1_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD1_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD1_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD1_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD1_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_CSR_OFFSET)
+#define S32K3XX_EDMA_CH2_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_ES_OFFSET)
+#define S32K3XX_EDMA_CH2_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_INT_OFFSET)
+#define S32K3XX_EDMA_CH2_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_SBR_OFFSET)
+#define S32K3XX_EDMA_CH2_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD2_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD2_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD2_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD2_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD2_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD2_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_CSR_OFFSET)
+#define S32K3XX_EDMA_CH3_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_ES_OFFSET)
+#define S32K3XX_EDMA_CH3_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_INT_OFFSET)
+#define S32K3XX_EDMA_CH3_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_SBR_OFFSET)
+#define S32K3XX_EDMA_CH3_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD3_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD3_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD3_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD3_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD3_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD3_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_CSR_OFFSET)
+#define S32K3XX_EDMA_CH4_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_ES_OFFSET)
+#define S32K3XX_EDMA_CH4_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_INT_OFFSET)
+#define S32K3XX_EDMA_CH4_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_SBR_OFFSET)
+#define S32K3XX_EDMA_CH4_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD4_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD4_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD4_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD4_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD4_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD4_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_CSR_OFFSET)
+#define S32K3XX_EDMA_CH5_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_ES_OFFSET)
+#define S32K3XX_EDMA_CH5_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_INT_OFFSET)
+#define S32K3XX_EDMA_CH5_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_SBR_OFFSET)
+#define S32K3XX_EDMA_CH5_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD5_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD5_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD5_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD5_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD5_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD5_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_CSR_OFFSET)
+#define S32K3XX_EDMA_CH6_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_ES_OFFSET)
+#define S32K3XX_EDMA_CH6_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_INT_OFFSET)
+#define S32K3XX_EDMA_CH6_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_SBR_OFFSET)
+#define S32K3XX_EDMA_CH6_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD6_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD6_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD6_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD6_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD6_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD6_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_CSR_OFFSET)
+#define S32K3XX_EDMA_CH7_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_ES_OFFSET)
+#define S32K3XX_EDMA_CH7_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_INT_OFFSET)
+#define S32K3XX_EDMA_CH7_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_SBR_OFFSET)
+#define S32K3XX_EDMA_CH7_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD7_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD7_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD7_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD7_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD7_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD7_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_CSR_OFFSET)
+#define S32K3XX_EDMA_CH8_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_ES_OFFSET)
+#define S32K3XX_EDMA_CH8_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_INT_OFFSET)
+#define S32K3XX_EDMA_CH8_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_SBR_OFFSET)
+#define S32K3XX_EDMA_CH8_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD8_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD8_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD8_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD8_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD8_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD8_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_CSR_OFFSET)
+#define S32K3XX_EDMA_CH9_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_ES_OFFSET)
+#define S32K3XX_EDMA_CH9_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_INT_OFFSET)
+#define S32K3XX_EDMA_CH9_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_SBR_OFFSET)
+#define S32K3XX_EDMA_CH9_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD9_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD9_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD9_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD9_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD9_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD9_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_CSR_OFFSET)
+#define S32K3XX_EDMA_CH10_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_ES_OFFSET)
+#define S32K3XX_EDMA_CH10_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_INT_OFFSET)
+#define S32K3XX_EDMA_CH10_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_SBR_OFFSET)
+#define S32K3XX_EDMA_CH10_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD10_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD10_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD10_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD10_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD10_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD10_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_CSR_OFFSET)
+#define S32K3XX_EDMA_CH11_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_ES_OFFSET)
+#define S32K3XX_EDMA_CH11_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_INT_OFFSET)
+#define S32K3XX_EDMA_CH11_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_SBR_OFFSET)
+#define S32K3XX_EDMA_CH11_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD11_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD11_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD11_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD11_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD11_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD11_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_CSR_OFFSET)
+#define S32K3XX_EDMA_CH12_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_ES_OFFSET)
+#define S32K3XX_EDMA_CH12_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_INT_OFFSET)
+#define S32K3XX_EDMA_CH12_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_SBR_OFFSET)
+#define S32K3XX_EDMA_CH12_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD12_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD12_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD12_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD12_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD12_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD12_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_CSR_OFFSET)
+#define S32K3XX_EDMA_CH13_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_ES_OFFSET)
+#define S32K3XX_EDMA_CH13_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_INT_OFFSET)
+#define S32K3XX_EDMA_CH13_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_SBR_OFFSET)
+#define S32K3XX_EDMA_CH13_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD13_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD13_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD13_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD13_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD13_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD13_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_CSR_OFFSET)
+#define S32K3XX_EDMA_CH14_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_ES_OFFSET)
+#define S32K3XX_EDMA_CH14_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_INT_OFFSET)
+#define S32K3XX_EDMA_CH14_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_SBR_OFFSET)
+#define S32K3XX_EDMA_CH14_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD14_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD14_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD14_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD14_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD14_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD14_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_CSR_OFFSET)
+#define S32K3XX_EDMA_CH15_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_ES_OFFSET)
+#define S32K3XX_EDMA_CH15_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_INT_OFFSET)
+#define S32K3XX_EDMA_CH15_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_SBR_OFFSET)
+#define S32K3XX_EDMA_CH15_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD15_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD15_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD15_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD15_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD15_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD15_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_CSR_OFFSET)
+#define S32K3XX_EDMA_CH16_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_ES_OFFSET)
+#define S32K3XX_EDMA_CH16_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_INT_OFFSET)
+#define S32K3XX_EDMA_CH16_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_SBR_OFFSET)
+#define S32K3XX_EDMA_CH16_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD16_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD16_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD16_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD16_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD16_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD16_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_CSR_OFFSET)
+#define S32K3XX_EDMA_CH17_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_ES_OFFSET)
+#define S32K3XX_EDMA_CH17_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_INT_OFFSET)
+#define S32K3XX_EDMA_CH17_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_SBR_OFFSET)
+#define S32K3XX_EDMA_CH17_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD17_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD17_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD17_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD17_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD17_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD17_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_CSR_OFFSET)
+#define S32K3XX_EDMA_CH18_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_ES_OFFSET)
+#define S32K3XX_EDMA_CH18_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_INT_OFFSET)
+#define S32K3XX_EDMA_CH18_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_SBR_OFFSET)
+#define S32K3XX_EDMA_CH18_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD18_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD18_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD18_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD18_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD18_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD18_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_CSR_OFFSET)
+#define S32K3XX_EDMA_CH19_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_ES_OFFSET)
+#define S32K3XX_EDMA_CH19_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_INT_OFFSET)
+#define S32K3XX_EDMA_CH19_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_SBR_OFFSET)
+#define S32K3XX_EDMA_CH19_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD19_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD19_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD19_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD19_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD19_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD19_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_CSR_OFFSET)
+#define S32K3XX_EDMA_CH20_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_ES_OFFSET)
+#define S32K3XX_EDMA_CH20_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_INT_OFFSET)
+#define S32K3XX_EDMA_CH20_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_SBR_OFFSET)
+#define S32K3XX_EDMA_CH20_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD20_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD20_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD20_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD20_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD20_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD20_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_CSR_OFFSET)
+#define S32K3XX_EDMA_CH21_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_ES_OFFSET)
+#define S32K3XX_EDMA_CH21_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_INT_OFFSET)
+#define S32K3XX_EDMA_CH21_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_SBR_OFFSET)
+#define S32K3XX_EDMA_CH21_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD21_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD21_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD21_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD21_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD21_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD21_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_CSR_OFFSET)
+#define S32K3XX_EDMA_CH22_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_ES_OFFSET)
+#define S32K3XX_EDMA_CH22_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_INT_OFFSET)
+#define S32K3XX_EDMA_CH22_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_SBR_OFFSET)
+#define S32K3XX_EDMA_CH22_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD22_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD22_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD22_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD22_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD22_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD22_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_CSR_OFFSET)
+#define S32K3XX_EDMA_CH23_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_ES_OFFSET)
+#define S32K3XX_EDMA_CH23_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_INT_OFFSET)
+#define S32K3XX_EDMA_CH23_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_SBR_OFFSET)
+#define S32K3XX_EDMA_CH23_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD23_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD23_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD23_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD23_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD23_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD23_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_CSR_OFFSET)
+#define S32K3XX_EDMA_CH24_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_ES_OFFSET)
+#define S32K3XX_EDMA_CH24_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_INT_OFFSET)
+#define S32K3XX_EDMA_CH24_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_SBR_OFFSET)
+#define S32K3XX_EDMA_CH24_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD24_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD24_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD24_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD24_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD24_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD24_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_CSR_OFFSET)
+#define S32K3XX_EDMA_CH25_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_ES_OFFSET)
+#define S32K3XX_EDMA_CH25_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_INT_OFFSET)
+#define S32K3XX_EDMA_CH25_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_SBR_OFFSET)
+#define S32K3XX_EDMA_CH25_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD25_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD25_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD25_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD25_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD25_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD25_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_CSR_OFFSET)
+#define S32K3XX_EDMA_CH26_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_ES_OFFSET)
+#define S32K3XX_EDMA_CH26_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_INT_OFFSET)
+#define S32K3XX_EDMA_CH26_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_SBR_OFFSET)
+#define S32K3XX_EDMA_CH26_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD26_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD26_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD26_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD26_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD26_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD26_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_CSR_OFFSET)
+#define S32K3XX_EDMA_CH27_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_ES_OFFSET)
+#define S32K3XX_EDMA_CH27_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_INT_OFFSET)
+#define S32K3XX_EDMA_CH27_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_SBR_OFFSET)
+#define S32K3XX_EDMA_CH27_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD27_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD27_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD27_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD27_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD27_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD27_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_CSR_OFFSET)
+#define S32K3XX_EDMA_CH28_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_ES_OFFSET)
+#define S32K3XX_EDMA_CH28_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_INT_OFFSET)
+#define S32K3XX_EDMA_CH28_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_SBR_OFFSET)
+#define S32K3XX_EDMA_CH28_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD28_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD28_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD28_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD28_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD28_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD28_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_CSR_OFFSET)
+#define S32K3XX_EDMA_CH29_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_ES_OFFSET)
+#define S32K3XX_EDMA_CH29_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_INT_OFFSET)
+#define S32K3XX_EDMA_CH29_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_SBR_OFFSET)
+#define S32K3XX_EDMA_CH29_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD29_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD29_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD29_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD29_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD29_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD29_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_CSR_OFFSET)
+#define S32K3XX_EDMA_CH30_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_ES_OFFSET)
+#define S32K3XX_EDMA_CH30_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_INT_OFFSET)
+#define S32K3XX_EDMA_CH30_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_SBR_OFFSET)
+#define S32K3XX_EDMA_CH30_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD30_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD30_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD30_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD30_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD30_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD30_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_CSR_OFFSET)
+#define S32K3XX_EDMA_CH31_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_ES_OFFSET)
+#define S32K3XX_EDMA_CH31_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_INT_OFFSET)
+#define S32K3XX_EDMA_CH31_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_SBR_OFFSET)
+#define S32K3XX_EDMA_CH31_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD31_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD31_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD31_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD31_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD31_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD31_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_BITER_OFFSET)
+
+uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
+{
+ S32K3XX_EDMA_CH0_CSR,
+ S32K3XX_EDMA_CH1_CSR,
+ S32K3XX_EDMA_CH2_CSR,
+ S32K3XX_EDMA_CH3_CSR,
+ S32K3XX_EDMA_CH4_CSR,
+ S32K3XX_EDMA_CH5_CSR,
+ S32K3XX_EDMA_CH6_CSR,
+ S32K3XX_EDMA_CH7_CSR,
+ S32K3XX_EDMA_CH8_CSR,
+ S32K3XX_EDMA_CH9_CSR,
+ S32K3XX_EDMA_CH10_CSR,
+ S32K3XX_EDMA_CH11_CSR,
+ S32K3XX_EDMA_CH12_CSR,
+ S32K3XX_EDMA_CH13_CSR,
+ S32K3XX_EDMA_CH14_CSR,
+ S32K3XX_EDMA_CH15_CSR,
+ S32K3XX_EDMA_CH16_CSR,
+ S32K3XX_EDMA_CH17_CSR,
+ S32K3XX_EDMA_CH18_CSR,
+ S32K3XX_EDMA_CH19_CSR,
+ S32K3XX_EDMA_CH20_CSR,
+ S32K3XX_EDMA_CH21_CSR,
+ S32K3XX_EDMA_CH22_CSR,
+ S32K3XX_EDMA_CH23_CSR,
+ S32K3XX_EDMA_CH24_CSR,
+ S32K3XX_EDMA_CH25_CSR,
+ S32K3XX_EDMA_CH26_CSR,
+ S32K3XX_EDMA_CH27_CSR,
+ S32K3XX_EDMA_CH28_CSR,
+ S32K3XX_EDMA_CH29_CSR,
+ S32K3XX_EDMA_CH30_CSR,
+ S32K3XX_EDMA_CH31_CSR
+};
+
+/* eDMA Register Bitfield Definitions ***************************************/
+
+/* Management Page Control Register (CSR) */
+
+ /* Bit 0: Reserved */
+#define EDMA_CSR_EDBG (1 << 1) /* Bit 1: Enable Debug (EDBG) */
+#define EDMA_CSR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration (ERCA) */
+ /* Bit 3: Reserved */
+#define EDMA_CSR_HAE (1 << 4) /* Bit 4: Halt After Error (HAE) */
+#define EDMA_CSR_HALT (1 << 5) /* Bit 5: Halt DMA Operations (HALT) */
+#define EDMA_CSR_GCLC (1 << 6) /* Bit 6: Global Channel Linking Control (GCLC) */
+#define EDMA_CSR_GMRC (1 << 7) /* Bit 7: Global Master ID Replication Control (GMRC) */
+#define EDMA_CSR_ECX (1 << 8) /* Bit 8: Cancel Transfer With Error (ECX) */
+#define EDMA_CSR_CX (1 << 9) /* Bit 9: Cancel Transfer (CX) */
+ /* Bits 10-23: Reserved */
+#define EDMA_CSR_ACTIVE_ID_SHIFT (24) /* Bits 24-28: Active Channel ID (ACTIVE_ID) */
+#define EDMA_CSR_ACTIVE_ID_MASK (0x1f << EDMA_CSR_ACTIVE_ID_SHIFT)
+ /* Bits 29-30: Reserved */
+#define EDMA_CSR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status (ACTIVE) */
+
+/* Management Page Error Status Register (ES) */
+
+#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
+#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
+#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
+#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
+#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
+#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
+#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
+#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
+#define EDMA_ES_ECX (1 << 8) /* Bit 8: Transfer Canceled (ECX) */
+#define EDMA_ES_UCE (1 << 9) /* Bit 9: Uncorrectable TCD Error During Channel Execution (UCE) */
+ /* Bits 10-23: Reserved */
+#define EDMA_ES_ERRCHN_SHIFT (8) /* Bits 24-28: Error Channel Number or Canceled Channel Number (ERRCHN) */
+#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT)
+ /* Bits 29-30: Reserved */
+#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status fields (VALID) */
+
+/* Management Page Interrupt Request Status Register (INT) */
+
+#define EDMA_INT(n) (1 << (n)) /* Bit n: Interrupt Request Status (INT) */
+
+/* Management Page Hardware Request Status Register (HRS) */
+
+#define EDMA_HRS(n) (1 << (n)) /* Bit n: Hardware Request Status (HRS) */
+
+/* Channel n Arbitration Group Register (CHn_GRPRI) */
+
+#define EDMA_CH_GRPRI_SHIFT (0) /* Bits 0-4: Arbitration Group For Channel n (GRPRI) */
+#define EDMA_CH_GRPRI_MASK (0x1f << EDMA_CH_GRPRI_SHIFT)
+ /* Bits 5-31: Reserved */
+
+/* eDMA Transfer Control Descriptor (TCD) Bitfield Definitions **************/
+
+/* Channel n Control and Status Register (CHn_CSR) */
+
+#define EDMA_CH_CSR_ERQ (1 << 0) /* Bit 0: Enable DMA Request (ERQ) */
+#define EDMA_CH_CSR_EARQ (1 << 1) /* Bit 1: Enable Asynchronous DMA Request in Stop Mode for Channel (EARQ) */
+#define EDMA_CH_CSR_EEI (1 << 2) /* Bit 2: Enable Error Interrupt (EEI) */
+#define EDMA_CH_CSR_EBW (1 << 3) /* Bit 3: Enable Buffered Writes (EBW) */
+ /* Bit 4-29: Reserved */
+#define EDMA_CH_CSR_DONE (1 << 30) /* Bit 30: Channel Done (DONE) */
+#define EDMA_CH_CSR_ACTIVE (1 << 31) /* Bit 31: CHannel Active (ACTIVE) */
+
+/* Channel n Error Status Register (CHn_ES) */
+
+#define EDMA_CH_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
+#define EDMA_CH_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
+#define EDMA_CH_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
+#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
+#define EDMA_CH_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
+#define EDMA_CH_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
+#define EDMA_CH_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
+#define EDMA_CH_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
+ /* Bit 8-30: Reserved */
+#define EDMA_CH_ES_ERR (1 << 31) /* Bit 31: Error in this channel (ERR) */
+
+/* Channel n Interrupt Status Register (CHn_INT) */
+
+#define EDMA_CH_INT (1 << 0) /* Bit 0: Interrupt Request (INT) */
+ /* Bits 1-31: Reserved */
+
+/* Channel n System Bus Register (CHn_SBR) */
+
+#define EDMA_CH_SBR_MID_SHIFT (0) /* Bits 0-3: Master ID (MID) */
+#define EDMA_CH_SBR_MID_MASK (0x0f << EDMA_CH_SBR_MID_SHIFT)
+ /* Bits 4-14: Reserved */
+#define EDMA_CH_SBR_PAL (1 << 15) /* Bit 15: Privileged Access Level (PAL) */
+#define EDMA_CH_SBR_EMI (1 << 16) /* Bit 16: Enable Master ID Replication (EMI) */
+#define EDMA_CH_SBR_ATTR_SHIFT (17) /* Bits 17-19: Attribute Output (ATTR) */
+#define EDMA_CH_SBR_ATTR_MASK (0x07 << EDMA_CH_SBR_ATTR_SHIFT)
+ /* Bits 20-31: Reserved */
+
+/* Channel n Priority Register (CHn_PRI) */
+
+#define EDMA_CH_PRI_APL_SHIFT (0) /* Bits 0-2: Arbitration Priority Level (APL) */
+#define EDMA_CH_PRI_APL_MASK (0x07 << EDMA_CH_PRI_APL_SHIFT)
+ /* Bits 3-29: Reserved */
+#define EDMA_CH_PRI_DPA (1 << 30) /* Bit 30: Disable Preempt Ability (DPA) */
+#define EDMA_CH_PRI_ECP (1 << 31) /* Bit 31: Enable Channel Preemption (ECP) */
+
+/* TCDn Source Address Register (TCDn_SADDR) */
+
+#define EDMA_TCD_SADDR_SHIFT (0) /* Bits 0-31: Source Address (SADDR) */
+#define EDMA_TCD_SADDR_MASK (0xffffffff << EDMA_TCD_SADDR_SHIFT)
+
+/* TCDn Signed Source Address Offset Register (TCDn_SOFF) */
+
+#define EDMA_TCD_SOFF_SHIFT (0) /* Bits 0-31: Source Address Signed Offset (SOFF) */
+#define EDMA_TCD_SOFF_MASK (0xffffffff << EDMA_TCD_SOFF_SHIFT)
+
+/* TCDn Transfer Attributes (TCDn_ATTR) */
+
+#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */
+#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT)
+#define EDMA_TCD_ATTR_DSIZE(n) ((n << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK)
+#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */
+#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT)
+#define EDMA_TCD_ATTR_DMOD(n) ((n << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK)
+#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */
+#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT)
+#define EDMA_TCD_ATTR_SSIZE(n) ((n << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK)
+# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
+# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
+# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
+# define EDMA_TCD_ATTR_SSIZE_64BIT (0x03 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */
+# define EDMA_TCD_ATTR_SSIZE_16BYTE (0x04 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */
+# define EDMA_TCD_ATTR_SSIZE_32BYTE (0x05 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte */
+# define EDMA_TCD_ATTR_SSIZE_64BYTE (0x06 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-byte */
+
+#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */
+#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT)
+#define EDMA_TCD_ATTR_SMOD(n) ((n << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK)
+
+/* TCDn Transfer Size (TCDn_NBYTES) */
+
+#define EDMA_TCD_NBYTES_SHIFT (0) /* Bits 0-29: Number of Bytes to Transfer per Service Request (NBYTES) */
+#define EDMA_TCD_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_SHIFT)
+#define EDMA_TCD_NBYTES_MASK_MLOFF (0x03ff << EDMA_TCD_NBYTES_SHIFT)
+#define EDMA_TCD_NBYTES_MLOFF_SHIFT (10) /* Bits 10-29: Minor Loop Offset (MLOFF) */
+#define EDMA_TCD_NBYTES_MLOFF_MASK (0x0fffff << EDMA_TCD_NBYTES_MLOFF_SHIFT)
+#define EDMA_TCD_NBYTES_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset Enable (DMLOE) */
+#define EDMA_TCD_NBYTES_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable (SMLOE) */
+
+/* TCDn Last Source Address Adjustment / Store DADDR Address Register
+ * (TCDn_SLAST_SDA)
+ */
+
+#define EDMA_TCD_SLAST_SDA_SHIFT (0) /* Bits 0-31: Last Source Address Adjustment / Store DADDR Address (SLAST_SDA) */
+#define EDMA_TCD_SLAST_SDA_MASK (0xffffffff << EDMA_TCD_SLAST_SDA_SHIFT)
+
+/* TCDn Destination Address Register (TCDn_DADDR) */
+
+#define EDMA_TCD_DADDR_SHIFT (0) /* Bits 0-31: Destination Address (DADDR) */
+#define EDMA_TCD_DADDR_MASK (0xffffffff << EDMA_TCD_DADDR_SHIFT)
+
+/* TCDn Signed Destination Address Offset Register (TCDn_DOFF) */
+
+#define EDMA_TCD_DOFF_SHIFT (0) /* Bits 0-15: Destination Address Signed Offset (DOFF) */
+#define EDMA_TCD_DOFF_MASK (0xffff << EDMA_TCD_DOFF_SHIFT)
+
+/* TCDn Current Major Loop Count Register (TCDn_CITER) */
+
+#define EDMA_TCD_CITER_SHIFT (0) /* Bits 0-14: Current Major Iteration Count (CITER) */
+#define EDMA_TCD_CITER_MASK (0x7fff << EDMA_TCD_CITER_SHIFT)
+#define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT)
+#define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */
+#define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT)
+#define EDMA_TCD_CITER_LINKCH(n) ((n << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT)
+#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
+
+/* TCDn Last Destination Address Adjustment / Scatter Gather Address Register
+ * (TCDn_DLAST_SGA)
+ */
+
+#define EDMA_TCD_DLAST_SGA_SHIFT (0) /* Bits 0-31: Last Destination Address Adjustment / Scatter Gather Address (DLAST_SGA) */
+#define EDMA_TCD_DLAST_SGA_MASK (0xffffffff << EDMA_TCD_DLAST_SGA_SHIFT)
+
+/* TCDn Control and Status Register (TCDn_CSR) */
+
+#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start (START) */
+#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable Interrupt if Major count complete (INTMAJOR) */
+#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable Interrupt if Major Count Half-complete (INTHALF) */
+#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request (DREQ) */
+#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing (ESG) */
+#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable Link When Major Loop Complete (MAJORELINK) */
+#define EDMA_TCD_CSR_EEOP (1 << 6) /* Bit 6: Enable End-Of-Packet Processing (EEOP) */
+#define EDMA_TCD_CSR_ESDA (1 << 7) /* Bit 7: Enable Store Destination Address (ESDA) */
+#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number (MAJORLINKCH) */
+#define EDMA_TCD_CSR_MAJORLINKCH_MASK (0x1f << EDMA_TCD_CSR_MAJORLINKCH_SHIFT)
+#define EDMA_TCD_CSR_MAJORLINKCH(n) ((n << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK)
Review Comment:
Thanks that's indeed safer to do so
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] PetervdPerk-NXP commented on a diff in pull request #6687: Add support for NXP S32K3XX MCU family and boards
Posted by GitBox <gi...@apache.org>.
PetervdPerk-NXP commented on code in PR #6687:
URL: https://github.com/apache/incubator-nuttx/pull/6687#discussion_r928534276
##########
arch/arm/src/s32k3xx/s32k3xx_edma.c:
##########
@@ -1623,4 +1659,4 @@ void s32k3xx_dmadump(const struct s32k3xx_dmaregs_s *regs, const char *msg)
dmainfo(" DMAMUX: %08x\n", (unsigned int)regs->dmamux);
}
#endif /* CONFIG_DEBUG_DMA */
-#endif /* CONFIG_S32K3XX_EDMA */
+#endif /* CONFIG_S32K3XX_EDMA */
Review Comment:
Oops something went wrong there.
There were some double \n\n which I wanted to remove but apparently I've removed them all.
I've pushed the correct version now.
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6687: Add support for NXP S32K3XX MCU family and boards
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6687:
URL: https://github.com/apache/incubator-nuttx/pull/6687#discussion_r928698863
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h:
##########
@@ -0,0 +1,504 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* QSPI Register Offsets ****************************************************/
+
+#define S32K3XX_QSPI_MCR_OFFSET (0x0000) /* Module Configuration Register (MCR) */
+#define S32K3XX_QSPI_IPCR_OFFSET (0x0008) /* IP Configuration Register (IPCR) */
+#define S32K3XX_QSPI_FLSHCR_OFFSET (0x000c) /* Flash Memory Configuration Register (FLSHCR) */
+#define S32K3XX_QSPI_BUF0CR_OFFSET (0x0010) /* Buffer 0 Configuration Register (BUF0CR) */
+#define S32K3XX_QSPI_BUF1CR_OFFSET (0x0014) /* Buffer 1 Configuration Register (BUF1CR) */
+#define S32K3XX_QSPI_BUF2CR_OFFSET (0x0018) /* Buffer 2 Configuration Register (BUF2CR) */
+#define S32K3XX_QSPI_BUF3CR_OFFSET (0x001c) /* Buffer 3 Configuration Register (BUF3CR) */
+#define S32K3XX_QSPI_BFGENCR_OFFSET (0x0020) /* Buffer Generic Configuration Register (BFGENCR) */
+#define S32K3XX_QSPI_SOCCR_OFFSET (0x0024) /* SOC Configuration Register (SOCCR) */
+#define S32K3XX_QSPI_BUF0IND_OFFSET (0x0030) /* Buffer 0 Top Index Register (BUF0IND) */
+#define S32K3XX_QSPI_BUF1IND_OFFSET (0x0034) /* Buffer 1 Top Index Register (BUF1IND) */
+#define S32K3XX_QSPI_BUF2IND_OFFSET (0x0038) /* Buffer 2 Top Index Register (BUF2IND) */
+#define S32K3XX_QSPI_DLLCRA_OFFSET (0x0060) /* DLL Flash Memory A Configuration Register (DLLCRA) */
+#define S32K3XX_QSPI_SFAR_OFFSET (0x0100) /* Serial Flash Memory Address Register (SFAR) */
+#define S32K3XX_QSPI_SMPR_OFFSET (0x0108) /* Sampling Register (SMPR) */
+#define S32K3XX_QSPI_RBSR_OFFSET (0x010c) /* RX Buffer Status Register (RBSR) */
+#define S32K3XX_QSPI_RBCT_OFFSET (0x0110) /* RX Buffer Control Register (RBCT) */
+#define S32K3XX_QSPI_DLSR_FA_OFFSET (0x0134) /* Data Learning Status Flash Memory A Register (DLSR_FA) */
+#define S32K3XX_QSPI_TBSR_OFFSET (0x0150) /* TX Buffer Status Register (TBSR) */
+#define S32K3XX_QSPI_TBDR_OFFSET (0x0154) /* TX Buffer Data Register (TBDR) */
+#define S32K3XX_QSPI_TBCT_OFFSET (0x0158) /* TX Buffer Control Register (TBCT) */
+#define S32K3XX_QSPI_SR_OFFSET (0x015c) /* Status Register (SR) */
+#define S32K3XX_QSPI_FR_OFFSET (0x0160) /* Flag Register (FR) */
+#define S32K3XX_QSPI_RSER_OFFSET (0x0164) /* Interrupt and DMA Request Select and Enable Register (RSER) */
+#define S32K3XX_QSPI_SPTRCLR_OFFSET (0x016c) /* Sequence Pointer Clear Register (SPTRCLR) */
+#define S32K3XX_QSPI_SFA1AD_OFFSET (0x0180) /* Serial Flash Memory A1 Top Address Register (SFA1AD) */
+#define S32K3XX_QSPI_SFA2AD_OFFSET (0x0184) /* Serial Flash Memory A2 Top Address Register (SFA2AD) */
+#define S32K3XX_QSPI_SFB1AD_OFFSET (0x0188) /* Serial Flash Memory B1 Top Address Register (SFB1AD) */
+#define S32K3XX_QSPI_SFB2AD_OFFSET (0x018c) /* Serial Flash Memory B2 Top Address Register (SFB2AD) */
+
+#define S32K3XX_QSPI_RBDR_OFFSET(n) (0x0200 + ((n) << 2)) /* RX Buffer Data Register (RBDRn, n=0,...,63) */
+
+#define S32K3XX_QSPI_LUTKEY_OFFSET (0x0300) /* LUT Key Register (LUTKEY) */
+#define S32K3XX_QSPI_LCKCR_OFFSET (0x0304) /* LUT Lock Configuration Register (LKCR) */
+#define S32K3XX_QSPI_LUT0_OFFSET (0x0310) /* LUT Register 0 (LUT0) */
+#define S32K3XX_QSPI_LUT1_OFFSET (0x0314) /* LUT Register 1 (LUT1) */
+#define S32K3XX_QSPI_LUT2_OFFSET (0x0318) /* LUT Register 2 (LUT2) */
+#define S32K3XX_QSPI_LUT3_OFFSET (0x031c) /* LUT Register 3 (LUT3) */
+#define S32K3XX_QSPI_LUT4_OFFSET (0x0320) /* LUT Register 4 (LUT4) */
+#define S32K3XX_QSPI_LUT5_OFFSET (0x0324) /* LUT Register 5 (LUT5) */
+#define S32K3XX_QSPI_LUT6_OFFSET (0x0328) /* LUT Register 6 (LUT6) */
+#define S32K3XX_QSPI_LUT7_OFFSET (0x032c) /* LUT Register 7 (LUT7) */
+#define S32K3XX_QSPI_LUT8_OFFSET (0x0330) /* LUT Register 8 (LUT8) */
+#define S32K3XX_QSPI_LUT9_OFFSET (0x0334) /* LUT Register 9 (LUT9) */
+#define S32K3XX_QSPI_LUT10_OFFSET (0x0338) /* LUT Register 10 (LUT10) */
+#define S32K3XX_QSPI_LUT11_OFFSET (0x033c) /* LUT Register 11 (LUT11) */
+#define S32K3XX_QSPI_LUT12_OFFSET (0x0340) /* LUT Register 12 (LUT12) */
+#define S32K3XX_QSPI_LUT13_OFFSET (0x0344) /* LUT Register 13 (LUT13) */
+#define S32K3XX_QSPI_LUT14_OFFSET (0x0348) /* LUT Register 14 (LUT14) */
+#define S32K3XX_QSPI_LUT15_OFFSET (0x034c) /* LUT Register 15 (LUT15) */
+#define S32K3XX_QSPI_LUT16_OFFSET (0x0350) /* LUT Register 16 (LUT16) */
+#define S32K3XX_QSPI_LUT17_OFFSET (0x0354) /* LUT Register 17 (LUT17) */
+#define S32K3XX_QSPI_LUT18_OFFSET (0x0358) /* LUT Register 18 (LUT18) */
+#define S32K3XX_QSPI_LUT19_OFFSET (0x035c) /* LUT Register 19 (LUT19) */
+
+/* QSPI Register Addresses **************************************************/
+
+#define S32K3XX_QSPI_MCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_MCR_OFFSET)
+#define S32K3XX_QSPI_IPCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_IPCR_OFFSET)
+#define S32K3XX_QSPI_FLSHCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FLSHCR_OFFSET)
+#define S32K3XX_QSPI_BUF0CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0CR_OFFSET)
+#define S32K3XX_QSPI_BUF1CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1CR_OFFSET)
+#define S32K3XX_QSPI_BUF2CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2CR_OFFSET)
+#define S32K3XX_QSPI_BUF3CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF3CR_OFFSET)
+#define S32K3XX_QSPI_BFGENCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BFGENCR_OFFSET)
+#define S32K3XX_QSPI_SOCCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SOCCR_OFFSET)
+#define S32K3XX_QSPI_BUF0IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0IND_OFFSET)
+#define S32K3XX_QSPI_BUF1IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1IND_OFFSET)
+#define S32K3XX_QSPI_BUF2IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2IND_OFFSET)
+#define S32K3XX_QSPI_DLLCRA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLLCRA_OFFSET)
+#define S32K3XX_QSPI_SFAR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFAR_OFFSET)
+#define S32K3XX_QSPI_SMPR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SMPR_OFFSET)
+#define S32K3XX_QSPI_RBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBSR_OFFSET)
+#define S32K3XX_QSPI_RBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBCT_OFFSET)
+#define S32K3XX_QSPI_DLSR_FA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLSR_FA_OFFSET)
+#define S32K3XX_QSPI_TBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBSR_OFFSET)
+#define S32K3XX_QSPI_TBDR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBDR_OFFSET)
+#define S32K3XX_QSPI_TBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBCT_OFFSET)
+#define S32K3XX_QSPI_SR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SR_OFFSET)
+#define S32K3XX_QSPI_FR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FR_OFFSET)
+#define S32K3XX_QSPI_RSER (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RSER_OFFSET)
+#define S32K3XX_QSPI_SPTRCLR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SPTRCLR_OFFSET)
+#define S32K3XX_QSPI_SFA1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA1AD_OFFSET)
+#define S32K3XX_QSPI_SFA2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA2AD_OFFSET)
+#define S32K3XX_QSPI_SFB1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB1AD_OFFSET)
+#define S32K3XX_QSPI_SFB2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB2AD_OFFSET)
+#define S32K3XX_QSPI_RBDR(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBDR_OFFSET(n))
+#define S32K3XX_QSPI_LUTKEY (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUTKEY_OFFSET)
+#define S32K3XX_QSPI_LCKCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LCKCR_OFFSET)
+#define S32K3XX_QSPI_LUT0 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET)
+#define S32K3XX_QSPI_LUT1 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT1_OFFSET)
+#define S32K3XX_QSPI_LUT2 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT2_OFFSET)
+#define S32K3XX_QSPI_LUT3 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT3_OFFSET)
+#define S32K3XX_QSPI_LUT4 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT4_OFFSET)
+#define S32K3XX_QSPI_LUT5 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT5_OFFSET)
+#define S32K3XX_QSPI_LUT6 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT6_OFFSET)
+#define S32K3XX_QSPI_LUT7 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT7_OFFSET)
+#define S32K3XX_QSPI_LUT8 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT8_OFFSET)
+#define S32K3XX_QSPI_LUT9 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT9_OFFSET)
+#define S32K3XX_QSPI_LUT10 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT10_OFFSET)
+#define S32K3XX_QSPI_LUT11 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT11_OFFSET)
+#define S32K3XX_QSPI_LUT12 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT12_OFFSET)
+#define S32K3XX_QSPI_LUT13 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT13_OFFSET)
+#define S32K3XX_QSPI_LUT14 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT14_OFFSET)
+#define S32K3XX_QSPI_LUT15 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT15_OFFSET)
+#define S32K3XX_QSPI_LUT16 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT16_OFFSET)
+#define S32K3XX_QSPI_LUT17 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT17_OFFSET)
+#define S32K3XX_QSPI_LUT18 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT18_OFFSET)
+#define S32K3XX_QSPI_LUT19 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT19_OFFSET)
+
+#define S32K3XX_QSPI_LUT(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET + (n*4))
+#define S32K3XX_QSPI_LUT_COUNT 20
+
+/* QSPI Register Bitfield Definitions ***************************************/
+
+/* Module Configuration Register (MCR) */
+
+#define QSPI_MCR_SWRSTSD (1 << 0) /* Bit 0: Software reset for serial flash memory domain (SWRSTSD) */
+#define QSPI_MCR_SWRSTHD (1 << 1) /* Bit 1: Software reset fo AHB domain (SWRSTHD) */
+ /* Bits 2-9: Reserved */
+#define QSPI_MCR_CLR_RXF (1 << 10) /* Bit 10: Clear RX FIFO (CLR_RXF) */
+#define QSPI_MCR_CLR_TXF (1 << 11) /* Bit 11: Clear TX FIFO/buffer (CLR_TXF) */
+ /* Bits 12-13: Reserved */
+#define QSPI_MCR_MDIS (1 << 14) /* Bit 14: Module disable (MDIS) */
+ /* Bits 15-23: Reserved */
+#define QSPI_MCR_DQS_FA_SEL_SHIFT (24) /* Bits 24-25: DQS clock for sampling read data at flash memory A (DQS_FA_SEL) */
+#define QSPI_MCR_DQS_FA_SEL_MASK (0x03 << QSPI_MCR_DQS_FA_SEL_SHIFT)
+#define QSPI_MCR_DQS_FA_SEL_INTERNAL_DQS ((0x00 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+#define QSPI_MCR_DQS_FA_SEL_LOOPBACK ((0x01 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+#define QSPI_MCR_DQS_FA_SEL_LOOPBACK_DQS ((0x02 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+ /* Bits 26-31: Reserved */
+
+/* IP Configuration Register (IPCR) */
+
+#define QSPICR_IDATSZ_SHIFT (0) /* Bits 0-15: IP data transfer size (IDATSZ) */
+#define QSPICR_IDATSZ_MASK (0xffff << QSPICR_IDATSZ_SHIFT)
+#define QSPICR_IDATSZ(n) ((n << QSPICR_IDATSZ_SHIFT) & QSPICR_IDATSZ_MASK)
+ /* Bits 16-23: Reserved */
+#define QSPICR_SEQID_SHIFT (24) /* Bits 24-27: Points to a sequence in the LUT (SEQID) */
+#define QSPICR_SEQID_MASK (0x0f << QSPICR_SEQID_SHIFT)
+#define QSPICR_SEQID(n) ((n << QSPICR_SEQID_SHIFT) & QSPICR_SEQID_MASK)
+ /* Bits 28-31: Reserved */
+
+/* Flash Memory Configuration Register (FLSHCR) */
+
+#define QSPI_FLSHCR_TCSS_SHIFT (0) /* Bits 0-3: Serial flash memory CS setup time (TCSS) */
+#define QSPI_FLSHCR_TCSS_MASK (0x0f << QSPI_FLSHCR_TCSS_SHIFT)
+#define QSPI_FLSHCR_TCSS(n) (n & QSPI_FLSHCR_TCSS_MASK)
+#define QSPI_FLSHCR_TCSH_SHIFT (8) /* Bits 8-11: Serial flash memory CS hold time (TCSH) */
+#define QSPI_FLSHCR_TCSH_MASK (0x0f << QSPI_FLSHCR_TCSH_SHIFT)
+#define QSPI_FLSHCR_TCSH(n) ((n << QSPI_FLSHCR_TCSH_SHIFT) & QSPI_FLSHCR_TCSH_MASK)
+ /* Bits 12-31: Reserved */
+
+/* Buffer n Configuration Register (BUFnCR) */
+
+#define QSPI_BUFCR_MSTRID_SHIFT (0) /* Bits 0-3: Master ID (MSTRID) */
+#define QSPI_BUFCR_MSTRID_MASK (0x0f << QSPI_BUFCR_MSTRID_SHIFT)
+#define QSPI_BUFCR_MSTRID(n) ((n << QSPI_BUFCR_MSTRID_SHIFT) & QSPI_BUFCR_MSTRID_MASK)
+ /* Bits 4-7: Reserved */
+#define QSPI_BUFCR_ADATSZ_SHIFT (8) /* Bits 8-13: AHB data transfer size (ADATSZ) */
+#define QSPI_BUFCR_ADATSZ_MASK (0x3f << QSPI_BUFCR_ADATSZ_SHIFT)
+#define QSPI_BUFCR_ADATSZ(n) ((n << QSPI_BUFCR_ADATSZ_SHIFT) & QSPI_BUFCR_ADATSZ_MASK)
+ /* Bits 14-31: Reserved */
+#define QSPI_BUF3CR_ALLMST (1 << 31) /* Bit 31: All master enable (ALLMST) */
+
+/* Buffer Generic Configuration Register (BFGENCR) */
+
+ /* Bits 0-11: Reserved */
+#define QSPI_BFGENCR_SEQID_SHIFT (12) /* Bits 12-15: Points to a sequence in the LUT (SEQID) */
+#define QSPI_BFGENCR_SEQID_MASK (0x0f << QSPI_BFGENCR_SEQID_SHIFT)
+ /* Bits 16-31: Reserved */
+
+/* SOC Configuration Register (SOCCR) */
+
+#define QSPI_SOCCR_SOCCFG_SHIFT (0) /* Bits 0-31: SOC configuration (SOCCFG) */
+#define QSPI_SOCCR_SOCCFG_MASK (0xffffffff << QSPI_SOCCR_SOCCFG_SHIFT)
+#define QSPI_SOCCR_OBE_PULL_TMG_RLX (1 << 0) /* Bit 0: obe_pull_timing_relax_b*/
+#define QSPI_SOCCR_IBE (1 << 1) /* Bit 1: IBE */
+#define QSPI_SOCCR_OBE (1 << 2) /* Bit 2: OBE */
+#define QSPI_SOCCR_DSE (1 << 3) /* Bit 3: DSE */
+#define QSPI_SOCCR_PUE (1 << 4) /* Bit 4: PUE */
+#define QSPI_SOCCR_PUS (1 << 5) /* Bit 5: PUS */
+#define QSPI_SOCCR_SRE (1 << 6) /* Bit 6: SRE */
+
+/* Buffer n Top Index Register (BUFnIND) */
+
+ /* Bits 0-2: Reserved */
+#define QSPI_BUFIND_TPINDX_SHIFT (3) /* Bits 3-8: Top index of buffer n (TPINDXn) */
+#define QSPI_BUFIND_TPINDX_MASK (0x3f << QSPI_BUFIND_TPINDX_SHIFT)
+ /* Bits 9-31: Reserved */
+
+/* DLL Flash Memory A Configuration Register (DLLCRA) */
+
+#define QSPI_DLLCRA_SLV_UPD (1 << 0) /* Bit 0: Slave update (SLV_UPD) */
+#define QSPI_DLLCRA_SLV_DLL_BYPASS (1 << 1) /* Bit 1: Slave DLL bypass (SLV_DLL_BYPASS) */
+#define QSPI_DLLCRA_SLV_EN (1 << 2) /* Bit 2: Slave enable (SLV_EN) */
+ /* Bits 3-7: Reserved */
+
+#define QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT (8) /* Bits 8-11: Delay elements in each delay tap (SLV_DLY_COARSE) */
+#define QSPI_DLLCRA_SLV_DLY_COARSE_MASK (0x0f << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT)
+#define QSPI_DLLCRA_SLV_DLY_COARSE(n) ((n << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT) & QSPI_DLLCRA_SLV_DLY_COARSE_MASK)
Review Comment:
```suggestion
#define QSPI_DLLCRA_SLV_DLY_COARSE(n) (((n) << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT) & QSPI_DLLCRA_SLV_DLY_COARSE_MASK)
```
Could you please change here and similar places?
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] PetervdPerk-NXP commented on a diff in pull request #6687: Add support for NXP S32K3XX MCU family and boards
Posted by GitBox <gi...@apache.org>.
PetervdPerk-NXP commented on code in PR #6687:
URL: https://github.com/apache/incubator-nuttx/pull/6687#discussion_r927862888
##########
arch/arm/src/s32k3xx/s32k3xx_edma.c:
##########
@@ -0,0 +1,1626 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/s32k3xx_edma.c
+ *
+ * Copyright (C) 2019, 2021 Gregory Nutt. All rights reserved.
+ * Copyright 2022 NXP
+ * Authors: Gregory Nutt <gn...@nuttx.org>
+ * David Sidrane <da...@nscdg.com>
+ * Peter van der Perk <pe...@nxp.com>
+ *
+ * This file was leveraged from the NuttX S32K1 port. Portions of that eDMA
+ * logic derived from NXP sample code which has a compatible BSD 3-clause
+ * license:
+ *
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
Review Comment:
It's based on the original code here
https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/s32k1xx/s32k1xx_edma.c
With some backports from imxrt which @davids5 wrote.
I rather don't like to change the license of a file, but If @davids5 & @gregory-nutt can confirm they're okay with it I can change it.
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6687: Add support for NXP S32K3XX MCU family and boards
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6687:
URL: https://github.com/apache/incubator-nuttx/pull/6687#discussion_r927776292
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h:
##########
@@ -0,0 +1,499 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* MCU TO FS26 **************************************************************/
+
+#define FS26_M_FS (1 << 31) /* Bit 31: Main or Fail-safe register selection (M/FS) */
+#define FS26_REG_ADDR_SHIFT (25) /* Bits 25-31: Register Address + M/FS */
+#define FS26_REG_ADDR_MASK (0x7F << FS26_REG_ADDR_SHIFT)
+#define FS26_REG_ADDR(n) (((n) << FS26_REG_ADDR_SHIFT) & FS26_REG_ADDR_MASK)
+#define FS26_RW (1 << 24) /* Bit 24: Read/Write (reading Bit 24 = 0) */
+
+/* FS26 General device status ***********************************************/
+
+#define FS26_M_AVAL (1 << 31) /* Bit 31: Main State machine availability (M_AVAL) */
+#define FS26_FS_EN (1 << 30) /* Bit 30: Fail Safe State machine status (FS_EN) */
+#define FS26_FS_G (1 << 29) /* Bit 29: Interrupt notification from the Fail-Safe domain (FS_G) */
+#define FS26_COM_G (1 << 28) /* Bit 28: Interrupt notification from the M_COM_FLG register (COM_G) */
+#define FS26_WIO_G (1 << 27) /* Bit 27: Interrupt notification from the M_WIO_FLG register (WIO_G) */
+#define FS26_VSUP_G (1 << 26) /* Bit 26: Interrupt notification from the M_VSUP_FLG register (VSUP_G) */
+#define FS26_REG_G (1 << 25) /* Bit 25: Interrupt notification from the M_REG_FLG register (REG_G) */
+#define FS26_TSD_G (1 << 24) /* Bit 24: Interrupt notification from the M_TSD_FLG register (TSD_G) */
+
+/* FS26 Data encoding********************************************************/
+
+#define FS26_DATA_LSB_SHIFT (8) /* Bits 8-15: DATA_LSB */
+#define FS26_DATA_LSB_MASK (0xFF << FS26_DATA_LSB_SHIFT)
Review Comment:
```suggestion
#define FS26_DATA_LSB_MASK (0xff << FS26_DATA_LSB_SHIFT)
```
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h:
##########
@@ -0,0 +1,320 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EMIOS_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EMIOS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* eMIOS Register Offsets ***************************************************/
+
+#define S32K3XX_EMIOS_MCR_OFFSET (0x0000) /* Module Configuration Register (MCR) */
+#define S32K3XX_EMIOS_GFLAG_OFFSET (0x0004) /* Global Flag Register (GFLAG) */
+#define S32K3XX_EMIOS_OUDIS_OFFSET (0x0008) /* Output Update Disable Register (OUDIS) */
+#define S32K3XX_EMIOS_UCDIS_OFFSET (0x000c) /* Disable Channel Register (UCDIS) */
+
+#define S32K3XX_EMIOS_A_OFFSET(n) ((n) * 0x0020 + 0x0020) /* UC A n (An) */
+#define S32K3XX_EMIOS_B_OFFSET(n) ((n) * 0x0020 + 0x0024) /* UC B n (Bn) */
+#define S32K3XX_EMIOS_CNT_OFFSET(n) ((n) * 0x0020 + 0x0028) /* UC Counter n (CNTn) */
+#define S32K3XX_EMIOS_C_OFFSET(n) ((n) * 0x0020 + 0x002c) /* UC Control n (Cn) */
+#define S32K3XX_EMIOS_S_OFFSET(n) ((n) * 0x0020 + 0x0030) /* UC Status n (Sn) */
+#define S32K3XX_EMIOS_ALTA_OFFSET(n) ((n) * 0x0020 + 0x0034) /* Alternate Address n (ALTAn) */
+#define S32K3XX_EMIOS_C2_OFFSET(n) ((n) * 0x0020 + 0x0038) /* UC Control 2 n (C2_n) */
+
+/* eMIOS Register Addresses *************************************************/
+
+#define S32K3XX_EMIOS0_MCR (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_MCR_OFFSET)
+#define S32K3XX_EMIOS0_GFLAG (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_GFLAG_OFFSET)
+#define S32K3XX_EMIOS0_OUDIS (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_OUDIS_OFFSET)
+#define S32K3XX_EMIOS0_UCDIS (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_UCDIS_OFFSET)
+#define S32K3XX_EMIOS0_A(n) (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_A_OFFSET(n))
+#define S32K3XX_EMIOS0_B(n) (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_B_OFFSET(n))
+#define S32K3XX_EMIOS0_CNT(n) (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_CNT_OFFSET(n))
+#define S32K3XX_EMIOS0_C(n) (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_C_OFFSET(n))
+#define S32K3XX_EMIOS0_S(n) (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_S_OFFSET(n))
+#define S32K3XX_EMIOS0_ALTA(n) (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_ALTA_OFFSET(n))
+#define S32K3XX_EMIOS0_C2(n) (S32K3XX_EMIOS0_BASE + S32K3XX_EMIOS_C2_OFFSET(n))
+
+#define S32K3XX_EMIOS1_MCR (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_MCR_OFFSET)
+#define S32K3XX_EMIOS1_GFLAG (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_GFLAG_OFFSET)
+#define S32K3XX_EMIOS1_OUDIS (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_OUDIS_OFFSET)
+#define S32K3XX_EMIOS1_UCDIS (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_UCDIS_OFFSET)
+#define S32K3XX_EMIOS1_A(n) (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_A_OFFSET(n))
+#define S32K3XX_EMIOS1_B(n) (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_B_OFFSET(n))
+#define S32K3XX_EMIOS1_CNT(n) (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_CNT_OFFSET(n))
+#define S32K3XX_EMIOS1_C(n) (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_C_OFFSET(n))
+#define S32K3XX_EMIOS1_S(n) (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_S_OFFSET(n))
+#define S32K3XX_EMIOS1_ALTA(n) (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_ALTA_OFFSET(n))
+#define S32K3XX_EMIOS1_C2(n) (S32K3XX_EMIOS1_BASE + S32K3XX_EMIOS_C2_OFFSET(n))
+
+#define S32K3XX_EMIOS2_MCR (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_MCR_OFFSET)
+#define S32K3XX_EMIOS2_GFLAG (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_GFLAG_OFFSET)
+#define S32K3XX_EMIOS2_OUDIS (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_OUDIS_OFFSET)
+#define S32K3XX_EMIOS2_UCDIS (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_UCDIS_OFFSET)
+#define S32K3XX_EMIOS2_A(n) (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_A_OFFSET(n))
+#define S32K3XX_EMIOS2_B(n) (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_B_OFFSET(n))
+#define S32K3XX_EMIOS2_CNT(n) (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_CNT_OFFSET(n))
+#define S32K3XX_EMIOS2_C(n) (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_C_OFFSET(n))
+#define S32K3XX_EMIOS2_S(n) (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_S_OFFSET(n))
+#define S32K3XX_EMIOS2_ALTA(n) (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_ALTA_OFFSET(n))
+#define S32K3XX_EMIOS2_C2(n) (S32K3XX_EMIOS2_BASE + S32K3XX_EMIOS_C2_OFFSET(n))
+
+/* eMIOS Register Bitfield Definitions **************************************/
+
+/* Module Configuration Register (MCR) */
+
+ /* Bits 0-7: Reserved */
+#define EMIOS_MCR_GPRE_SHIFT (8) /* Bits 8-15: Global Prescaler (GPRE) */
+#define EMIOS_MCR_GPRE_MASK (0xff << EMIOS_MCR_GPRE_SHIFT)
+#define EMIOS_MCR_GPRE(n) (((n) << EMIOS_MCR_GPRE_SHIFT) & EMIOS_MCR_GPRE_MASK)
+ /* Bits 16-25: Reserved */
+#define EMIOS_MCR_GPREN (1 << 26) /* Bit 26: Global Prescaler Enable (GPREN) */
+ /* Bit 27: Reserved */
+#define EMIOS_MCR_GTBE (1 << 28) /* Bit 28: Global Timebase Enable (GTBE) */
+#define EMIOS_MCR_FRZ (1 << 29) /* Bit 29: Freeze (FRZ) */
+#define EMIOS_MCR_MDIS (1 << 30) /* Bit 30: Module Disable (MDIS) */
+ /* Bit 31: Reserved */
+
+/* Global Flag Register (GFLAG) */
+
+#define EMIOS_GFLAG_F0 (1 << 0) /* Bit 0: Mirror of UC 0 FLAG (F0) */
+#define EMIOS_GFLAG_F1 (1 << 1) /* Bit 1: Mirror of UC 1 FLAG (F1) */
+#define EMIOS_GFLAG_F2 (1 << 2) /* Bit 2: Mirror of UC 2 FLAG (F2) */
+#define EMIOS_GFLAG_F3 (1 << 3) /* Bit 3: Mirror of UC 3 FLAG (F3) */
+#define EMIOS_GFLAG_F4 (1 << 4) /* Bit 4: Mirror of UC 4 FLAG (F4) */
+#define EMIOS_GFLAG_F5 (1 << 5) /* Bit 5: Mirror of UC 5 FLAG (F5) */
+#define EMIOS_GFLAG_F6 (1 << 6) /* Bit 6: Mirror of UC 6 FLAG (F6) */
+#define EMIOS_GFLAG_F7 (1 << 7) /* Bit 7: Mirror of UC 7 FLAG (F7) */
+#define EMIOS_GFLAG_F8 (1 << 8) /* Bit 8: Mirror of UC 8 FLAG (F8) */
+#define EMIOS_GFLAG_F9 (1 << 9) /* Bit 9: Mirror of UC 9 FLAG (F9) */
+#define EMIOS_GFLAG_F10 (1 << 10) /* Bit 10: Mirror of UC 10 FLAG (F10) */
+#define EMIOS_GFLAG_F11 (1 << 11) /* Bit 11: Mirror of UC 11 FLAG (F11) */
+#define EMIOS_GFLAG_F12 (1 << 12) /* Bit 12: Mirror of UC 12 FLAG (F12) */
+#define EMIOS_GFLAG_F13 (1 << 13) /* Bit 13: Mirror of UC 13 FLAG (F13) */
+#define EMIOS_GFLAG_F14 (1 << 14) /* Bit 14: Mirror of UC 14 FLAG (F14) */
+#define EMIOS_GFLAG_F15 (1 << 15) /* Bit 15: Mirror of UC 15 FLAG (F15) */
+#define EMIOS_GFLAG_F16 (1 << 16) /* Bit 16: Mirror of UC 16 FLAG (F16) */
+#define EMIOS_GFLAG_F17 (1 << 17) /* Bit 17: Mirror of UC 17 FLAG (F17) */
+#define EMIOS_GFLAG_F18 (1 << 18) /* Bit 18: Mirror of UC 18 FLAG (F18) */
+#define EMIOS_GFLAG_F19 (1 << 19) /* Bit 19: Mirror of UC 19 FLAG (F19) */
+#define EMIOS_GFLAG_F20 (1 << 20) /* Bit 20: Mirror of UC 20 FLAG (F20) */
+#define EMIOS_GFLAG_F21 (1 << 21) /* Bit 21: Mirror of UC 21 FLAG (F21) */
+#define EMIOS_GFLAG_F22 (1 << 22) /* Bit 22: Mirror of UC 22 FLAG (F22) */
+#define EMIOS_GFLAG_F23 (1 << 23) /* Bit 23: Mirror of UC 23 FLAG (F23) */
+ /* Bits 24-31: Reserved */
+
+/* Output Update Disable Register (OUDIS) */
+
+#define EMIOS_OUDIS_OU0 (1 << 0) /* Bit 0: Channel 0 Output Update Disable (OU0) */
+#define EMIOS_OUDIS_OU1 (1 << 1) /* Bit 1: Channel 1 Output Update Disable (OU1) */
+#define EMIOS_OUDIS_OU2 (1 << 2) /* Bit 2: Channel 2 Output Update Disable (OU2) */
+#define EMIOS_OUDIS_OU3 (1 << 3) /* Bit 3: Channel 3 Output Update Disable (OU3) */
+#define EMIOS_OUDIS_OU4 (1 << 4) /* Bit 4: Channel 4 Output Update Disable (OU4) */
+#define EMIOS_OUDIS_OU5 (1 << 5) /* Bit 5: Channel 5 Output Update Disable (OU5) */
+#define EMIOS_OUDIS_OU6 (1 << 6) /* Bit 6: Channel 6 Output Update Disable (OU6) */
+#define EMIOS_OUDIS_OU7 (1 << 7) /* Bit 7: Channel 7 Output Update Disable (OU7) */
+#define EMIOS_OUDIS_OU8 (1 << 8) /* Bit 8: Channel 8 Output Update Disable (OU8) */
+#define EMIOS_OUDIS_OU9 (1 << 9) /* Bit 9: Channel 9 Output Update Disable (OU9) */
+#define EMIOS_OUDIS_OU10 (1 << 10) /* Bit 10: Channel 10 Output Update Disable (OU10) */
+#define EMIOS_OUDIS_OU11 (1 << 11) /* Bit 11: Channel 11 Output Update Disable (OU11) */
+#define EMIOS_OUDIS_OU12 (1 << 12) /* Bit 12: Channel 12 Output Update Disable (OU12) */
+#define EMIOS_OUDIS_OU13 (1 << 13) /* Bit 13: Channel 13 Output Update Disable (OU13) */
+#define EMIOS_OUDIS_OU14 (1 << 14) /* Bit 14: Channel 14 Output Update Disable (OU14) */
+#define EMIOS_OUDIS_OU15 (1 << 15) /* Bit 15: Channel 15 Output Update Disable (OU15) */
+#define EMIOS_OUDIS_OU16 (1 << 16) /* Bit 16: Channel 16 Output Update Disable (OU16) */
+#define EMIOS_OUDIS_OU17 (1 << 17) /* Bit 17: Channel 17 Output Update Disable (OU17) */
+#define EMIOS_OUDIS_OU18 (1 << 18) /* Bit 18: Channel 18 Output Update Disable (OU18) */
+#define EMIOS_OUDIS_OU19 (1 << 19) /* Bit 19: Channel 19 Output Update Disable (OU19) */
+#define EMIOS_OUDIS_OU20 (1 << 20) /* Bit 20: Channel 20 Output Update Disable (OU20) */
+#define EMIOS_OUDIS_OU21 (1 << 21) /* Bit 21: Channel 21 Output Update Disable (OU21) */
+#define EMIOS_OUDIS_OU22 (1 << 22) /* Bit 22: Channel 22 Output Update Disable (OU22) */
+#define EMIOS_OUDIS_OU23 (1 << 23) /* Bit 23: Channel 23 Output Update Disable (OU23) */
+#define EMIOS_OUDIS_OU(n) (1 << n) /* Bit n: Channel n Output Update Disable (OU23) */
+ /* Bits 24-31: Reserved */
+
+/* Disable Channel Register (UCDIS) */
+
+#define EMIOS_UCDIS_OU0 (1 << 0) /* Bit 0: Disable UC 0 (UCDIS0) */
+#define EMIOS_UCDIS_OU1 (1 << 1) /* Bit 1: Disable UC 1 (UCDIS1) */
+#define EMIOS_UCDIS_OU2 (1 << 2) /* Bit 2: Disable UC 2 (UCDIS2) */
+#define EMIOS_UCDIS_OU3 (1 << 3) /* Bit 3: Disable UC 3 (UCDIS3) */
+#define EMIOS_UCDIS_OU4 (1 << 4) /* Bit 4: Disable UC 4 (UCDIS4) */
+#define EMIOS_UCDIS_OU5 (1 << 5) /* Bit 5: Disable UC 5 (UCDIS5) */
+#define EMIOS_UCDIS_OU6 (1 << 6) /* Bit 6: Disable UC 6 (UCDIS6) */
+#define EMIOS_UCDIS_OU7 (1 << 7) /* Bit 7: Disable UC 7 (UCDIS7) */
+#define EMIOS_UCDIS_OU8 (1 << 8) /* Bit 8: Disable UC 8 (UCDIS8) */
+#define EMIOS_UCDIS_OU9 (1 << 9) /* Bit 9: Disable UC 9 (UCDIS9) */
+#define EMIOS_UCDIS_OU10 (1 << 10) /* Bit 10: Disable UC 10 (UCDIS10) */
+#define EMIOS_UCDIS_OU11 (1 << 11) /* Bit 11: Disable UC 11 (UCDIS11) */
+#define EMIOS_UCDIS_OU12 (1 << 12) /* Bit 12: Disable UC 12 (UCDIS12) */
+#define EMIOS_UCDIS_OU13 (1 << 13) /* Bit 13: Disable UC 13 (UCDIS13) */
+#define EMIOS_UCDIS_OU14 (1 << 14) /* Bit 14: Disable UC 14 (UCDIS14) */
+#define EMIOS_UCDIS_OU15 (1 << 15) /* Bit 15: Disable UC 15 (UCDIS15) */
+#define EMIOS_UCDIS_OU16 (1 << 16) /* Bit 16: Disable UC 16 (UCDIS16) */
+#define EMIOS_UCDIS_OU17 (1 << 17) /* Bit 17: Disable UC 17 (UCDIS17) */
+#define EMIOS_UCDIS_OU18 (1 << 18) /* Bit 18: Disable UC 18 (UCDIS18) */
+#define EMIOS_UCDIS_OU19 (1 << 19) /* Bit 19: Disable UC 19 (UCDIS19) */
+#define EMIOS_UCDIS_OU20 (1 << 20) /* Bit 20: Disable UC 20 (UCDIS20) */
+#define EMIOS_UCDIS_OU21 (1 << 21) /* Bit 21: Disable UC 21 (UCDIS21) */
+#define EMIOS_UCDIS_OU22 (1 << 22) /* Bit 22: Disable UC 22 (UCDIS22) */
+#define EMIOS_UCDIS_OU23 (1 << 23) /* Bit 23: Disable UC 23 (UCDIS23) */
+ /* Bits 24-31: Reserved */
+
+/* UC A n (An) */
+
+#define EMIOS_A_SHIFT (0) /* Bits 0-15: A */
+#define EMIOS_A_MASK (0xffff << EMIOS_A_SHIFT)
+#define EMIOS_A(n) ((n << EMIOS_A_SHIFT) & EMIOS_A_MASK)
+ /* Bits 16-31: Reserved */
+
+/* UC B n (Bn) */
+
+#define EMIOS_B_SHIFT (0) /* Bits 0-15: B */
+#define EMIOS_B_MASK (0xffff << EMIOS_B_SHIFT)
+#define EMIOS_B(n) ((n << EMIOS_B_SHIFT) & EMIOS_B_MASK)
+ /* Bits 16-31: Reserved */
+
+/* UC Counter n (CNTn) */
+
+#define EMIOS_CNT_C_SHIFT (0) /* Bits 0-15: Internal Counter Value (C) */
+#define EMIOS_CNT_C_MASK (0xffff << EMIOS_CNT_C_SHIFT)
+ /* Bits 16-31: Reserved */
+
+/* UC Control n (Cn) */
+
+#define EMIOS_C_MODE_SHIFT (0) /* Bits 0-6: Mode Selection (MODE) - NOTE: See S32K3XX Reference Manual for all options! */
+#define EMIOS_C_MODE_MASK (0x7f << EMIOS_C_MODE_SHIFT)
+# define EMIOS_C_MODE_GPIN (0x00 << EMIOS_C_MODE_SHIFT) /* 000_0000: General-Purpose Input mode */
+# define EMIOS_C_MODE_GPOUT (0x01 << EMIOS_C_MODE_SHIFT) /* 000_0001: General-Purpose Output mode */
+# define EMIOS_C_MODE_SAIC (0x02 << EMIOS_C_MODE_SHIFT) /* 000_0010: Single Action Input Capture mode */
+# define EMIOS_C_MODE_SAIC_EDGE (0x42 << EMIOS_C_MODE_SHIFT) /* 100_0010: Single Action Input Capture mode (with edge capturing) */
+# define EMIOS_C_MODE_SAOC (0x03 << EMIOS_C_MODE_SHIFT) /* 000_0011: Single Action Output Capture mode */
+# define EMIOS_C_MODE_IPWM (0x04 << EMIOS_C_MODE_SHIFT) /* 000_0100: Input Pulse Width Measurement mode */
+# define EMIOS_C_MODE_IPM (0x05 << EMIOS_C_MODE_SHIFT) /* 000_0101: Input Period Measurement mode */
+# define EMIOS_C_MODE_DAOC_BMATCH (0x06 << EMIOS_C_MODE_SHIFT) /* 000_0110: Double Action Output Compare mode (with FLAG = 1 on B match) */
+# define EMIOS_C_MODE_DAOC_ABMATCH (0x07 << EMIOS_C_MODE_SHIFT) /* 000_0111: Double Action Output Compare mode (with FLAG = 1 on A and B match) */
+# define EMIOS_C_MODE_PEC_CONT (0x0a << EMIOS_C_MODE_SHIFT) /* 000_1010: Pulse Edge Counting mode (continuous) */
+# define EMIOS_C_MODE_PEC_SINGLE (0x0b << EMIOS_C_MODE_SHIFT) /* 000_1011: Pulse Edge Counting mode (single-shot) */
+# define EMIOS_C_MODE_MC_UPCNT_CLRSTRT_INTCLK (0x10 << EMIOS_C_MODE_SHIFT) /* 001_0000: Modulus Counter mode (up counter with clear on match start, internal clock source) */
+# define EMIOS_C_MODE_MC_UPCNT_CLRSTRT_EXTCLK (0x11 << EMIOS_C_MODE_SHIFT) /* 001_0001: Modulus Counter mode (up counter with clear on match start, external clock source) */
+# define EMIOS_C_MODE_MC_UPCNT_CLREND_INTCLK (0x12 << EMIOS_C_MODE_SHIFT) /* 001_0010: Modulus Counter mode (up counter with clear on match end, internal clock source) */
+# define EMIOS_C_MODE_MC_UPCNT_CLREND_EXTCLK (0x13 << EMIOS_C_MODE_SHIFT) /* 001_0011: Modulus Counter mode (up counter with clear on match end, external clock source) */
+# define EMIOS_C_MODE_MC_UPDOWNCNT_CLRSTRT_INTCLK (0x14 << EMIOS_C_MODE_SHIFT) /* 001_0100: Modulus Counter mode (up/down counter with clear on match start, internal clock source) */
+# define EMIOS_C_MODE_MC_UPDOWNCNT_CLRSTRT_EXTCLK (0x15 << EMIOS_C_MODE_SHIFT) /* 001_0101: Modulus Counter mode (up/down counter with clear on match start, external clock source) */
+# define EMIOS_C_MODE_MC_UPDOWNCNT_CLREND_INTCLK (0x16 << EMIOS_C_MODE_SHIFT) /* 001_0110: Modulus Counter mode (up/down counter with clear on match end, internal clock source) */
+# define EMIOS_C_MODE_MC_UPDOWNCNT_CLREND_EXTCLK (0x17 << EMIOS_C_MODE_SHIFT) /* 001_0111: Modulus Counter mode (up/down counter with clear on match end, external clock source) */
+# define EMIOS_C_MODE_OPWMT (0x26 << EMIOS_C_MODE_SHIFT) /* 010_0110: Output PWM with Trigger mode */
+# define EMIOS_C_MODE_MCB_UPCNT_INTCLK (0x50 << EMIOS_C_MODE_SHIFT) /* 101_0000: Modulus Counter Buffered mode (up counter, internal clock source) */
+# define EMIOS_C_MODE_MCB_UPCNT_EXTCLK (0x51 << EMIOS_C_MODE_SHIFT) /* 101_0001: Modulus Counter Buffered mode (up counter, external clock source) */
+# define EMIOS_C_MODE_MCB_UPDOWNCNT_FSTRT_INTCLK (0x54 << EMIOS_C_MODE_SHIFT) /* 101_0100: Modulus Counter Buffered mode (up/down counter with flag set on match start, internal clock source) */
+# define EMIOS_C_MODE_MCB_UPDOWNCNT_FSTRT_EXTCLK (0x55 << EMIOS_C_MODE_SHIFT) /* 101_0101: Modulus Counter Buffered mode (up/down counter with flag set on match start, external clock source) */
+# define EMIOS_C_MODE_MCB_UPDOWNCNT_FBND_INTCLK (0x56 << EMIOS_C_MODE_SHIFT) /* 101_0110: Modulus Counter Buffered mode (up/down counter with flag set on period boundary, internal clock source) */
+# define EMIOS_C_MODE_MCB_UPDOWNCNT_FBND_EXTCLK (0x57 << EMIOS_C_MODE_SHIFT) /* 101_0111: Modulus Counter Buffered mode (up/down counter with flag set on period boundary, external clock source) */
+# define EMIOS_C_MODE_OPWFMB_BMATCH (0x58 << EMIOS_C_MODE_SHIFT) /* 101_1000: Output Pulse Width and Frequency Modulation Buffered mode (BS1 match) */
+# define EMIOS_C_MODE_OPWFMB_ABMATCH (0x5a << EMIOS_C_MODE_SHIFT) /* 101_1010: Output Pulse Width and Frequency Modulation Buffered mode (AS1 or BS1 match) */
+# define EMIOS_C_MODE_OPWMCB_TRAIL_FTRAIL (0x5c << EMIOS_C_MODE_SHIFT) /* 101_1100: Center Aligned Output PWM with Dead Time Insertion Buffered mode (with trailing edge dead time, input capture flag asserted on trailing edge) */
+# define EMIOS_C_MODE_OPWMCB_TRAIL_FBOTH (0x5e << EMIOS_C_MODE_SHIFT) /* 101_1110: Center Aligned Output PWM with Dead Time Insertion Buffered mode (with trailing edge dead time, input capture flag asserted on both edges) */
+# define EMIOS_C_MODE_OPWMCB_LEAD_FTRAIL (0x5d << EMIOS_C_MODE_SHIFT) /* 101_1101: Center Aligned Output PWM with Dead Time Insertion Buffered mode (with leading edge dead time, input capture flag asserted on trailing edge) */
+# define EMIOS_C_MODE_OPWMCB_LEAD_FBOTH (0x5f << EMIOS_C_MODE_SHIFT) /* 101_1111: Center Aligned Output PWM with Dead Time Insertion Buffered mode (with leading edge dead time, input capture flag asserted on both edges) */
+# define EMIOS_C_MODE_OPWMB_BMATCH (0x60 << EMIOS_C_MODE_SHIFT) /* 110_0000: Output PWM Buffered mode (BS1 match) */
+# define EMIOS_C_MODE_OPWMB_ABMATCH (0x62 << EMIOS_C_MODE_SHIFT) /* 110_0010: Output PWM Buffered mode (AS1 or BS1 match) */
+
+#define EMIOS_C_EDPOL (1 << 7) /* Bit 7: Edge Polarity (EDPOL) */
+#define EMIOS_C_EDSEL (1 << 8) /* Bit 8: Edge Selection (EDSEL) */
+#define EMIOS_C_BSL_SHIFT (9) /* Bits 9-10: Bus Select (BSL) */
+#define EMIOS_C_BSL_MASK (0x03 << EMIOS_C_BSL_SHIFT)
+# define EMIOS_C_BSL_BUSA (0x00 << EMIOS_C_BSL_SHIFT) /* Counter bus A for all channels */
+# define EMIOS_C_BSL_BUSBCD (0x01 << EMIOS_C_BSL_SHIFT) /* Counter bus B for channels 0-7, C for 8-15, D for 16-23, E for 24-31 */
+# define EMIOS_C_BSL_BUSF (0x02 << EMIOS_C_BSL_SHIFT) /* Counter bus F */
+# define EMIOS_C_BSL_INTCNT (0x03 << EMIOS_C_BSL_SHIFT) /* Internal counter for all channels */
+
+ /* Bit 11: Reserved */
+#define EMIOS_C_FORCMB (1 << 12) /* Bit 12: Force Match B (FORCMB) */
+#define EMIOS_C_FORCMA (1 << 13) /* Bit 13: Force Match A (FORCMA) */
+ /* Bits 14-16: Reserved */
+#define EMIOS_C_FEN (1 << 17) /* Bit 17: Flag Enable (FEN) */
+#define EMIOS_C_FCK (1 << 18) /* Bit 18: Filter Clock Select (FCK) */
+#define EMIOS_C_IF_SHIFT (19) /* Bits 19-22: Input Filter (IF) */
+#define EMIOS_C_IF_MASK (0x0f << EMIOS_C_IF_SHIFT)
+# define EMIOS_C_IF_BYPASS (0x00 << EMIOS_C_IF_SHIFT) /* Bypassed. Input signal is synchronized before arriving at the digital filter. */
+# define EMIOS_C_IF_2CYCLES (0x01 << EMIOS_C_IF_SHIFT) /* 2 Filter Clock Cycles */
+# define EMIOS_C_IF_4CYCLES (0x02 << EMIOS_C_IF_SHIFT) /* 4 Filter Clock Cycles */
+# define EMIOS_C_IF_8CYCLES (0x04 << EMIOS_C_IF_SHIFT) /* 8 Filter Clock Cycles */
+# define EMIOS_C_IF_16CYCLES (0x08 << EMIOS_C_IF_SHIFT) /* 16 Filter Clock Cycles */
+
+ /* Bit 23: Reserved */
+#define EMIOS_C_DMA (1 << 24) /* Bit 24: Direct Memory Access (DMA) */
+#define EMIOS_C_UCPREN (1 << 25) /* Bit 25: Prescaler Enable (UCPREN) */
+#define EMIOS_C_UCPRE_SHIFT (26) /* Bits 26-27: Prescaler (UCPRE) */
+#define EMIOS_C_UCPRE_MASK (0x03 << EMIOS_C_UCPRE_SHIFT)
+# define EMIOS_C_UCPRE_DIV1 (0x00 << EMIOS_C_UCPRE_SHIFT) /* Divide by 1 */
+# define EMIOS_C_UCPRE_DIV2 (0x01 << EMIOS_C_UCPRE_SHIFT) /* Divide by 2 */
+# define EMIOS_C_UCPRE_DIV3 (0x02 << EMIOS_C_UCPRE_SHIFT) /* Divide by 3 */
+# define EMIOS_C_UCPRE_DIV4 (0x03 << EMIOS_C_UCPRE_SHIFT) /* Divide by 4 */
+
+#define EMIOS_C_ODISSL_SHIFT (28) /* Bits 28-29: Output Disable Select (ODISSL) */
+#define EMIOS_C_ODISSL_MASK (0x03 << EMIOS_C_ODISSL_SHIFT)
+# define EMIOS_C_ODISSL_IN0 (0x00 << EMIOS_C_ODISSL_SHIFT) /* Output Disable Input 0 */
+# define EMIOS_C_ODISSL_IN1 (0x01 << EMIOS_C_ODISSL_SHIFT) /* Output Disable Input 1 */
+# define EMIOS_C_ODISSL_IN2 (0x02 << EMIOS_C_ODISSL_SHIFT) /* Output Disable Input 2 */
+# define EMIOS_C_ODISSL_IN3 (0x03 << EMIOS_C_ODISSL_SHIFT) /* Output Disable Input 3 */
+
+#define EMIOS_C_ODIS (1 << 30) /* Bit 30: Output Disable (ODIS) */
+#define EMIOS_C_FREN (1 << 31) /* Bit 31: Freeze Enable (FREN) */
+
+/* UC Status n (Sn) */
+
+#define EMIOS_S_FLAG (1 << 0) /* Bit 0: Flag indicating input capture or match event (FLAG) */
+#define EMIOS_S_UCOUT (1 << 1) /* Bit 1: UC Output Pin state (UCOUT) */
+#define EMIOS_S_UCIN (1 << 2) /* Bit 2: UC Input Pin state (UCIN) */
+ /* Bits 3-14: Reserved */
+#define EMIOS_S_OVFL (1 << 15) /* Bit 15: Overflow (OVFL) */
+ /* Bits 16-30: Reserved */
+#define EMIOS_S_OVR (1 << 31) /* Bit 31: Overrun (OVR) */
+
+/* Alternate Address n (ALTAn) */
+
+#define EMIOS_ALTA_SHIFT (0) /* Bits 0-15: Alternate Address */
+#define EMIOS_ALTA_MASK (0xffff << EMIOS_ALTA_SHIFT)
+ /* Bits 16-31: Reserved */
+
+/* UC Control 2 n (C2_n) */
+
+#define EMIOS_C2_UCRELDEL_INT_SHIFT (0) /* Bits 0-4: Reload Signal Output Delay Interval */
+#define EMIOS_C2_UCRELDEL_INT_MASK (0x1f << EMIOS_C2_UCRELDEL_INT_SHIFT)
+ /* Bits 5-13: Reserved */
+#define EMIOS_C2_UCPRECLK (1 << 14) /* Bit 14: Prescaler Clock Source (UCPRECLK) */
+ /* Bit 15: Reserved */
+#define EMIOS_C2_UCEXTPRE_SHIFT (16) /* Bits 16-19: Extended Prescaler (UCEXTPRE) */
+#define EMIOS_C2_UCEXTPRE_MASK (0x0f << EMIOS_C2_UCEXTPRE_SHIFT)
+#define EMIOS_C2_UCEXTPRE(n) ((n << EMIOS_C2_UCEXTPRE_SHIFT) & EMIOS_C2_UCEXTPRE_MASK)
Review Comment:
```suggestion
#define EMIOS_C2_UCEXTPRE(n) (((n) << EMIOS_C2_UCEXTPRE_SHIFT) & EMIOS_C2_UCEXTPRE_MASK)
```
here and other places in this file
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h:
##########
@@ -0,0 +1,1433 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define S32K3XX_EDMA_NCHANNELS 32
+
+/* eDMA Register Offsets ****************************************************/
+
+#define S32K3XX_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */
+#define S32K3XX_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */
+#define S32K3XX_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */
+#define S32K3XX_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */
+
+#define S32K3XX_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */
+
+/* eDMA Register Addresses **************************************************/
+
+#define S32K3XX_EDMA_CSR (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CSR_OFFSET)
+#define S32K3XX_EDMA_ES (S32K3XX_EDMA_BASE + S32K3XX_EDMA_ES_OFFSET)
+#define S32K3XX_EDMA_INT (S32K3XX_EDMA_BASE + S32K3XX_EDMA_INT_OFFSET)
+#define S32K3XX_EDMA_HRS (S32K3XX_EDMA_BASE + S32K3XX_EDMA_HRS_OFFSET)
+#define S32K3XX_EDMA_CH_GRPRI(n) (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CH_GRPRI_OFFSET(n))
+
+/* eDMA Transfer Control Descriptor (TCD) Register Offsets ******************/
+
+#define S32K3XX_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH0_CSR_OFFSET (0x000000) /* Channel 0 Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH0_ES_OFFSET (0x000004) /* Channel 0 Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH0_INT_OFFSET (0x000008) /* Channel 0 Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH0_SBR_OFFSET (0x00000c) /* Channel 0 System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH0_PRI_OFFSET (0x000010) /* Channel 0 Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD0_SADDR_OFFSET (0x000020) /* TCD0 Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD0_SOFF_OFFSET (0x000024) /* TCD0 Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD0_ATTR_OFFSET (0x000026) /* TCD0 Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD0_NBYTES_OFFSET (0x000028) /* TCD0 Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET (0x00002c) /* TCD0 Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD0_DADDR_OFFSET (0x000030) /* TCD0 Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD0_DOFF_OFFSET (0x000034) /* TCD0 Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD0_CITER_OFFSET (0x000036) /* TCD0 Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET (0x000038) /* TCD0 Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD0_CSR_OFFSET (0x00003c) /* TCD0 Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD0_BITER_OFFSET (0x00003e) /* TCD0 Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH1_CSR_OFFSET (0x004000) /* Channel 1 Control and Status Register (CH1_CSR) */
+#define S32K3XX_EDMA_CH1_ES_OFFSET (0x004004) /* Channel 1 Error Status Register (CH1_ES) */
+#define S32K3XX_EDMA_CH1_INT_OFFSET (0x004008) /* Channel 1 Interrupt Status Register (CH1_INT) */
+#define S32K3XX_EDMA_CH1_SBR_OFFSET (0x00400c) /* Channel 1 System Bus Register (CH1_SBR) */
+#define S32K3XX_EDMA_CH1_PRI_OFFSET (0x004010) /* Channel 1 Priority Register (CH1_PRI) */
+#define S32K3XX_EDMA_TCD1_SADDR_OFFSET (0x004020) /* TCD1 Source Address Register (TCD1_SADDR) */
+#define S32K3XX_EDMA_TCD1_SOFF_OFFSET (0x004024) /* TCD1 Signed Source Address Offset Register (TCD1_SOFF) */
+#define S32K3XX_EDMA_TCD1_ATTR_OFFSET (0x004026) /* TCD1 Transfer Attributes (TCD1_ATTR) */
+#define S32K3XX_EDMA_TCD1_NBYTES_OFFSET (0x004028) /* TCD1 Transfer Size (TCD1_NBYTES) */
+#define S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET (0x00402c) /* TCD1 Last Source Address Adjustment / Store DADDR Address Register (TCD1_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD1_DADDR_OFFSET (0x004030) /* TCD1 Destination Address Register (TCD1_DADDR) */
+#define S32K3XX_EDMA_TCD1_DOFF_OFFSET (0x004034) /* TCD1 Signed Destination Address Offset Register (TCD1_DOFF) */
+#define S32K3XX_EDMA_TCD1_CITER_OFFSET (0x004036) /* TCD1 Current Major Loop Count Register (TCD1_CITER) */
+#define S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET (0x004038) /* TCD1 Last Destination Address Adjustment / Scatter Gather Address Register (TCD1_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD1_CSR_OFFSET (0x00403c) /* TCD1 Control and Status Register (TCD1_CSR) */
+#define S32K3XX_EDMA_TCD1_BITER_OFFSET (0x00403e) /* TCD1 Beginning Major Loop Count Register (TCD1_BITER) */
+
+#define S32K3XX_EDMA_CH2_CSR_OFFSET (0x008000) /* Channel 2 Control and Status Register (CH2_CSR) */
+#define S32K3XX_EDMA_CH2_ES_OFFSET (0x008004) /* Channel 2 Error Status Register (CH2_ES) */
+#define S32K3XX_EDMA_CH2_INT_OFFSET (0x008008) /* Channel 2 Interrupt Status Register (CH2_INT) */
+#define S32K3XX_EDMA_CH2_SBR_OFFSET (0x00800c) /* Channel 2 System Bus Register (CH2_SBR) */
+#define S32K3XX_EDMA_CH2_PRI_OFFSET (0x008010) /* Channel 2 Priority Register (CH2_PRI) */
+#define S32K3XX_EDMA_TCD2_SADDR_OFFSET (0x008020) /* TCD2 Source Address Register (TCD2_SADDR) */
+#define S32K3XX_EDMA_TCD2_SOFF_OFFSET (0x008024) /* TCD2 Signed Source Address Offset Register (TCD2_SOFF) */
+#define S32K3XX_EDMA_TCD2_ATTR_OFFSET (0x008026) /* TCD2 Transfer Attributes (TCD2_ATTR) */
+#define S32K3XX_EDMA_TCD2_NBYTES_OFFSET (0x008028) /* TCD2 Transfer Size (TCD2_NBYTES) */
+#define S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET (0x00802c) /* TCD2 Last Source Address Adjustment / Store DADDR Address Register (TCD2_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD2_DADDR_OFFSET (0x008030) /* TCD2 Destination Address Register (TCD2_DADDR) */
+#define S32K3XX_EDMA_TCD2_DOFF_OFFSET (0x008034) /* TCD2 Signed Destination Address Offset Register (TCD2_DOFF) */
+#define S32K3XX_EDMA_TCD2_CITER_OFFSET (0x008036) /* TCD2 Current Major Loop Count Register (TCD2_CITER) */
+#define S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET (0x008038) /* TCD2 Last Destination Address Adjustment / Scatter Gather Address Register (TCD2_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD2_CSR_OFFSET (0x00803c) /* TCD2 Control and Status Register (TCD2_CSR) */
+#define S32K3XX_EDMA_TCD2_BITER_OFFSET (0x00803e) /* TCD2 Beginning Major Loop Count Register (TCD2_BITER) */
+
+#define S32K3XX_EDMA_CH3_CSR_OFFSET (0x00c000) /* Channel 3 Control and Status Register (CH3_CSR) */
+#define S32K3XX_EDMA_CH3_ES_OFFSET (0x00c004) /* Channel 3 Error Status Register (CH3_ES) */
+#define S32K3XX_EDMA_CH3_INT_OFFSET (0x00c008) /* Channel 3 Interrupt Status Register (CH3_INT) */
+#define S32K3XX_EDMA_CH3_SBR_OFFSET (0x00c00c) /* Channel 3 System Bus Register (CH3_SBR) */
+#define S32K3XX_EDMA_CH3_PRI_OFFSET (0x00c010) /* Channel 3 Priority Register (CH3_PRI) */
+#define S32K3XX_EDMA_TCD3_SADDR_OFFSET (0x00c020) /* TCD3 Source Address Register (TCD3_SADDR) */
+#define S32K3XX_EDMA_TCD3_SOFF_OFFSET (0x00c024) /* TCD3 Signed Source Address Offset Register (TCD3_SOFF) */
+#define S32K3XX_EDMA_TCD3_ATTR_OFFSET (0x00c026) /* TCD3 Transfer Attributes (TCD3_ATTR) */
+#define S32K3XX_EDMA_TCD3_NBYTES_OFFSET (0x00c028) /* TCD3 Transfer Size (TCD3_NBYTES) */
+#define S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET (0x00c02c) /* TCD3 Last Source Address Adjustment / Store DADDR Address Register (TCD3_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD3_DADDR_OFFSET (0x00c030) /* TCD3 Destination Address Register (TCD3_DADDR) */
+#define S32K3XX_EDMA_TCD3_DOFF_OFFSET (0x00c034) /* TCD3 Signed Destination Address Offset Register (TCD3_DOFF) */
+#define S32K3XX_EDMA_TCD3_CITER_OFFSET (0x00c036) /* TCD3 Current Major Loop Count Register (TCD3_CITER) */
+#define S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET (0x00c038) /* TCD3 Last Destination Address Adjustment / Scatter Gather Address Register (TCD3_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD3_CSR_OFFSET (0x00c03c) /* TCD3 Control and Status Register (TCD3_CSR) */
+#define S32K3XX_EDMA_TCD3_BITER_OFFSET (0x00c03e) /* TCD3 Beginning Major Loop Count Register (TCD3_BITER) */
+
+#define S32K3XX_EDMA_CH4_CSR_OFFSET (0x010000) /* Channel 4 Control and Status Register (CH4_CSR) */
+#define S32K3XX_EDMA_CH4_ES_OFFSET (0x010004) /* Channel 4 Error Status Register (CH4_ES) */
+#define S32K3XX_EDMA_CH4_INT_OFFSET (0x010008) /* Channel 4 Interrupt Status Register (CH4_INT) */
+#define S32K3XX_EDMA_CH4_SBR_OFFSET (0x01000c) /* Channel 4 System Bus Register (CH4_SBR) */
+#define S32K3XX_EDMA_CH4_PRI_OFFSET (0x010010) /* Channel 4 Priority Register (CH4_PRI) */
+#define S32K3XX_EDMA_TCD4_SADDR_OFFSET (0x010020) /* TCD4 Source Address Register (TCD4_SADDR) */
+#define S32K3XX_EDMA_TCD4_SOFF_OFFSET (0x010024) /* TCD4 Signed Source Address Offset Register (TCD4_SOFF) */
+#define S32K3XX_EDMA_TCD4_ATTR_OFFSET (0x010026) /* TCD4 Transfer Attributes (TCD4_ATTR) */
+#define S32K3XX_EDMA_TCD4_NBYTES_OFFSET (0x010028) /* TCD4 Transfer Size (TCD4_NBYTES) */
+#define S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET (0x01002c) /* TCD4 Last Source Address Adjustment / Store DADDR Address Register (TCD4_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD4_DADDR_OFFSET (0x010030) /* TCD4 Destination Address Register (TCD4_DADDR) */
+#define S32K3XX_EDMA_TCD4_DOFF_OFFSET (0x010034) /* TCD4 Signed Destination Address Offset Register (TCD4_DOFF) */
+#define S32K3XX_EDMA_TCD4_CITER_OFFSET (0x010036) /* TCD4 Current Major Loop Count Register (TCD4_CITER) */
+#define S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET (0x010038) /* TCD4 Last Destination Address Adjustment / Scatter Gather Address Register (TCD4_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD4_CSR_OFFSET (0x01003c) /* TCD4 Control and Status Register (TCD4_CSR) */
+#define S32K3XX_EDMA_TCD4_BITER_OFFSET (0x01003e) /* TCD4 Beginning Major Loop Count Register (TCD4_BITER) */
+
+#define S32K3XX_EDMA_CH5_CSR_OFFSET (0x014000) /* Channel 5 Control and Status Register (CH5_CSR) */
+#define S32K3XX_EDMA_CH5_ES_OFFSET (0x014004) /* Channel 5 Error Status Register (CH5_ES) */
+#define S32K3XX_EDMA_CH5_INT_OFFSET (0x014008) /* Channel 5 Interrupt Status Register (CH5_INT) */
+#define S32K3XX_EDMA_CH5_SBR_OFFSET (0x01400c) /* Channel 5 System Bus Register (CH5_SBR) */
+#define S32K3XX_EDMA_CH5_PRI_OFFSET (0x014010) /* Channel 5 Priority Register (CH5_PRI) */
+#define S32K3XX_EDMA_TCD5_SADDR_OFFSET (0x014020) /* TCD5 Source Address Register (TCD5_SADDR) */
+#define S32K3XX_EDMA_TCD5_SOFF_OFFSET (0x014024) /* TCD5 Signed Source Address Offset Register (TCD5_SOFF) */
+#define S32K3XX_EDMA_TCD5_ATTR_OFFSET (0x014026) /* TCD5 Transfer Attributes (TCD5_ATTR) */
+#define S32K3XX_EDMA_TCD5_NBYTES_OFFSET (0x014028) /* TCD5 Transfer Size (TCD5_NBYTES) */
+#define S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET (0x01402c) /* TCD5 Last Source Address Adjustment / Store DADDR Address Register (TCD5_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD5_DADDR_OFFSET (0x014030) /* TCD5 Destination Address Register (TCD5_DADDR) */
+#define S32K3XX_EDMA_TCD5_DOFF_OFFSET (0x014034) /* TCD5 Signed Destination Address Offset Register (TCD5_DOFF) */
+#define S32K3XX_EDMA_TCD5_CITER_OFFSET (0x014036) /* TCD5 Current Major Loop Count Register (TCD5_CITER) */
+#define S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET (0x014038) /* TCD5 Last Destination Address Adjustment / Scatter Gather Address Register (TCD5_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD5_CSR_OFFSET (0x01403c) /* TCD5 Control and Status Register (TCD5_CSR) */
+#define S32K3XX_EDMA_TCD5_BITER_OFFSET (0x01403e) /* TCD5 Beginning Major Loop Count Register (TCD5_BITER) */
+
+#define S32K3XX_EDMA_CH6_CSR_OFFSET (0x018000) /* Channel 6 Control and Status Register (CH6_CSR) */
+#define S32K3XX_EDMA_CH6_ES_OFFSET (0x018004) /* Channel 6 Error Status Register (CH6_ES) */
+#define S32K3XX_EDMA_CH6_INT_OFFSET (0x018008) /* Channel 6 Interrupt Status Register (CH6_INT) */
+#define S32K3XX_EDMA_CH6_SBR_OFFSET (0x01800c) /* Channel 6 System Bus Register (CH6_SBR) */
+#define S32K3XX_EDMA_CH6_PRI_OFFSET (0x018010) /* Channel 6 Priority Register (CH6_PRI) */
+#define S32K3XX_EDMA_TCD6_SADDR_OFFSET (0x018020) /* TCD6 Source Address Register (TCD6_SADDR) */
+#define S32K3XX_EDMA_TCD6_SOFF_OFFSET (0x018024) /* TCD6 Signed Source Address Offset Register (TCD6_SOFF) */
+#define S32K3XX_EDMA_TCD6_ATTR_OFFSET (0x018026) /* TCD6 Transfer Attributes (TCD6_ATTR) */
+#define S32K3XX_EDMA_TCD6_NBYTES_OFFSET (0x018028) /* TCD6 Transfer Size (TCD6_NBYTES) */
+#define S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET (0x01802c) /* TCD6 Last Source Address Adjustment / Store DADDR Address Register (TCD6_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD6_DADDR_OFFSET (0x018030) /* TCD6 Destination Address Register (TCD6_DADDR) */
+#define S32K3XX_EDMA_TCD6_DOFF_OFFSET (0x018034) /* TCD6 Signed Destination Address Offset Register (TCD6_DOFF) */
+#define S32K3XX_EDMA_TCD6_CITER_OFFSET (0x018036) /* TCD6 Current Major Loop Count Register (TCD6_CITER) */
+#define S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET (0x018038) /* TCD6 Last Destination Address Adjustment / Scatter Gather Address Register (TCD6_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD6_CSR_OFFSET (0x01803c) /* TCD6 Control and Status Register (TCD6_CSR) */
+#define S32K3XX_EDMA_TCD6_BITER_OFFSET (0x01803e) /* TCD6 Beginning Major Loop Count Register (TCD6_BITER) */
+
+#define S32K3XX_EDMA_CH7_CSR_OFFSET (0x01c000) /* Channel 7 Control and Status Register (CH7_CSR) */
+#define S32K3XX_EDMA_CH7_ES_OFFSET (0x01c004) /* Channel 7 Error Status Register (CH7_ES) */
+#define S32K3XX_EDMA_CH7_INT_OFFSET (0x01c008) /* Channel 7 Interrupt Status Register (CH7_INT) */
+#define S32K3XX_EDMA_CH7_SBR_OFFSET (0x01c00c) /* Channel 7 System Bus Register (CH7_SBR) */
+#define S32K3XX_EDMA_CH7_PRI_OFFSET (0x01c010) /* Channel 7 Priority Register (CH7_PRI) */
+#define S32K3XX_EDMA_TCD7_SADDR_OFFSET (0x01c020) /* TCD7 Source Address Register (TCD7_SADDR) */
+#define S32K3XX_EDMA_TCD7_SOFF_OFFSET (0x01c024) /* TCD7 Signed Source Address Offset Register (TCD7_SOFF) */
+#define S32K3XX_EDMA_TCD7_ATTR_OFFSET (0x01c026) /* TCD7 Transfer Attributes (TCD7_ATTR) */
+#define S32K3XX_EDMA_TCD7_NBYTES_OFFSET (0x01c028) /* TCD7 Transfer Size (TCD7_NBYTES) */
+#define S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET (0x01c02c) /* TCD7 Last Source Address Adjustment / Store DADDR Address Register (TCD7_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD7_DADDR_OFFSET (0x01c030) /* TCD7 Destination Address Register (TCD7_DADDR) */
+#define S32K3XX_EDMA_TCD7_DOFF_OFFSET (0x01c034) /* TCD7 Signed Destination Address Offset Register (TCD7_DOFF) */
+#define S32K3XX_EDMA_TCD7_CITER_OFFSET (0x01c036) /* TCD7 Current Major Loop Count Register (TCD7_CITER) */
+#define S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET (0x01c038) /* TCD7 Last Destination Address Adjustment / Scatter Gather Address Register (TCD7_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD7_CSR_OFFSET (0x01c03c) /* TCD7 Control and Status Register (TCD7_CSR) */
+#define S32K3XX_EDMA_TCD7_BITER_OFFSET (0x01c03e) /* TCD7 Beginning Major Loop Count Register (TCD7_BITER) */
+
+#define S32K3XX_EDMA_CH8_CSR_OFFSET (0x020000) /* Channel 8 Control and Status Register (CH8_CSR) */
+#define S32K3XX_EDMA_CH8_ES_OFFSET (0x020004) /* Channel 8 Error Status Register (CH8_ES) */
+#define S32K3XX_EDMA_CH8_INT_OFFSET (0x020008) /* Channel 8 Interrupt Status Register (CH8_INT) */
+#define S32K3XX_EDMA_CH8_SBR_OFFSET (0x02000c) /* Channel 8 System Bus Register (CH8_SBR) */
+#define S32K3XX_EDMA_CH8_PRI_OFFSET (0x020010) /* Channel 8 Priority Register (CH8_PRI) */
+#define S32K3XX_EDMA_TCD8_SADDR_OFFSET (0x020020) /* TCD8 Source Address Register (TCD8_SADDR) */
+#define S32K3XX_EDMA_TCD8_SOFF_OFFSET (0x020024) /* TCD8 Signed Source Address Offset Register (TCD8_SOFF) */
+#define S32K3XX_EDMA_TCD8_ATTR_OFFSET (0x020026) /* TCD8 Transfer Attributes (TCD8_ATTR) */
+#define S32K3XX_EDMA_TCD8_NBYTES_OFFSET (0x020028) /* TCD8 Transfer Size (TCD8_NBYTES) */
+#define S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET (0x02002c) /* TCD8 Last Source Address Adjustment / Store DADDR Address Register (TCD8_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD8_DADDR_OFFSET (0x020030) /* TCD8 Destination Address Register (TCD8_DADDR) */
+#define S32K3XX_EDMA_TCD8_DOFF_OFFSET (0x020034) /* TCD8 Signed Destination Address Offset Register (TCD8_DOFF) */
+#define S32K3XX_EDMA_TCD8_CITER_OFFSET (0x020036) /* TCD8 Current Major Loop Count Register (TCD8_CITER) */
+#define S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET (0x020038) /* TCD8 Last Destination Address Adjustment / Scatter Gather Address Register (TCD8_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD8_CSR_OFFSET (0x02003c) /* TCD8 Control and Status Register (TCD8_CSR) */
+#define S32K3XX_EDMA_TCD8_BITER_OFFSET (0x02003e) /* TCD8 Beginning Major Loop Count Register (TCD8_BITER) */
+
+#define S32K3XX_EDMA_CH9_CSR_OFFSET (0x024000) /* Channel 9 Control and Status Register (CH9_CSR) */
+#define S32K3XX_EDMA_CH9_ES_OFFSET (0x024004) /* Channel 9 Error Status Register (CH9_ES) */
+#define S32K3XX_EDMA_CH9_INT_OFFSET (0x024008) /* Channel 9 Interrupt Status Register (CH9_INT) */
+#define S32K3XX_EDMA_CH9_SBR_OFFSET (0x02400c) /* Channel 9 System Bus Register (CH9_SBR) */
+#define S32K3XX_EDMA_CH9_PRI_OFFSET (0x024010) /* Channel 9 Priority Register (CH9_PRI) */
+#define S32K3XX_EDMA_TCD9_SADDR_OFFSET (0x024020) /* TCD9 Source Address Register (TCD9_SADDR) */
+#define S32K3XX_EDMA_TCD9_SOFF_OFFSET (0x024024) /* TCD9 Signed Source Address Offset Register (TCD9_SOFF) */
+#define S32K3XX_EDMA_TCD9_ATTR_OFFSET (0x024026) /* TCD9 Transfer Attributes (TCD9_ATTR) */
+#define S32K3XX_EDMA_TCD9_NBYTES_OFFSET (0x024028) /* TCD9 Transfer Size (TCD9_NBYTES) */
+#define S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET (0x02402c) /* TCD9 Last Source Address Adjustment / Store DADDR Address Register (TCD9_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD9_DADDR_OFFSET (0x024030) /* TCD9 Destination Address Register (TCD9_DADDR) */
+#define S32K3XX_EDMA_TCD9_DOFF_OFFSET (0x024034) /* TCD9 Signed Destination Address Offset Register (TCD9_DOFF) */
+#define S32K3XX_EDMA_TCD9_CITER_OFFSET (0x024036) /* TCD9 Current Major Loop Count Register (TCD9_CITER) */
+#define S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET (0x024038) /* TCD9 Last Destination Address Adjustment / Scatter Gather Address Register (TCD9_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD9_CSR_OFFSET (0x02403c) /* TCD9 Control and Status Register (TCD9_CSR) */
+#define S32K3XX_EDMA_TCD9_BITER_OFFSET (0x02403e) /* TCD9 Beginning Major Loop Count Register (TCD9_BITER) */
+
+#define S32K3XX_EDMA_CH10_CSR_OFFSET (0x028000) /* Channel 10 Control and Status Register (CH10_CSR) */
+#define S32K3XX_EDMA_CH10_ES_OFFSET (0x028004) /* Channel 10 Error Status Register (CH10_ES) */
+#define S32K3XX_EDMA_CH10_INT_OFFSET (0x028008) /* Channel 10 Interrupt Status Register (CH10_INT) */
+#define S32K3XX_EDMA_CH10_SBR_OFFSET (0x02800c) /* Channel 10 System Bus Register (CH10_SBR) */
+#define S32K3XX_EDMA_CH10_PRI_OFFSET (0x028010) /* Channel 10 Priority Register (CH10_PRI) */
+#define S32K3XX_EDMA_TCD10_SADDR_OFFSET (0x028020) /* TCD10 Source Address Register (TCD10_SADDR) */
+#define S32K3XX_EDMA_TCD10_SOFF_OFFSET (0x028024) /* TCD10 Signed Source Address Offset Register (TCD10_SOFF) */
+#define S32K3XX_EDMA_TCD10_ATTR_OFFSET (0x028026) /* TCD10 Transfer Attributes (TCD10_ATTR) */
+#define S32K3XX_EDMA_TCD10_NBYTES_OFFSET (0x028028) /* TCD10 Transfer Size (TCD10_NBYTES) */
+#define S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET (0x02802c) /* TCD10 Last Source Address Adjustment / Store DADDR Address Register (TCD10_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD10_DADDR_OFFSET (0x028030) /* TCD10 Destination Address Register (TCD10_DADDR) */
+#define S32K3XX_EDMA_TCD10_DOFF_OFFSET (0x028034) /* TCD10 Signed Destination Address Offset Register (TCD10_DOFF) */
+#define S32K3XX_EDMA_TCD10_CITER_OFFSET (0x028036) /* TCD10 Current Major Loop Count Register (TCD10_CITER) */
+#define S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET (0x028038) /* TCD10 Last Destination Address Adjustment / Scatter Gather Address Register (TCD10_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD10_CSR_OFFSET (0x02803c) /* TCD10 Control and Status Register (TCD10_CSR) */
+#define S32K3XX_EDMA_TCD10_BITER_OFFSET (0x02803e) /* TCD10 Beginning Major Loop Count Register (TCD10_BITER) */
+#define S32K3XX_EDMA_CH11_CSR_OFFSET (0x02c000) /* Channel 11 Control and Status Register (CH11_CSR) */
+#define S32K3XX_EDMA_CH11_ES_OFFSET (0x02c004) /* Channel 11 Error Status Register (CH11_ES) */
+#define S32K3XX_EDMA_CH11_INT_OFFSET (0x02c008) /* Channel 11 Interrupt Status Register (CH11_INT) */
+#define S32K3XX_EDMA_CH11_SBR_OFFSET (0x02c00c) /* Channel 11 System Bus Register (CH11_SBR) */
+#define S32K3XX_EDMA_CH11_PRI_OFFSET (0x02c010) /* Channel 11 Priority Register (CH11_PRI) */
+#define S32K3XX_EDMA_TCD11_SADDR_OFFSET (0x02c020) /* TCD11 Source Address Register (TCD11_SADDR) */
+#define S32K3XX_EDMA_TCD11_SOFF_OFFSET (0x02c024) /* TCD11 Signed Source Address Offset Register (TCD11_SOFF) */
+#define S32K3XX_EDMA_TCD11_ATTR_OFFSET (0x02c026) /* TCD11 Transfer Attributes (TCD11_ATTR) */
+#define S32K3XX_EDMA_TCD11_NBYTES_OFFSET (0x02c028) /* TCD11 Transfer Size (TCD11_NBYTES) */
+#define S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET (0x02c02c) /* TCD11 Last Source Address Adjustment / Store DADDR Address Register (TCD11_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD11_DADDR_OFFSET (0x02c030) /* TCD11 Destination Address Register (TCD11_DADDR) */
+#define S32K3XX_EDMA_TCD11_DOFF_OFFSET (0x02c034) /* TCD11 Signed Destination Address Offset Register (TCD11_DOFF) */
+#define S32K3XX_EDMA_TCD11_CITER_OFFSET (0x02c036) /* TCD11 Current Major Loop Count Register (TCD11_CITER) */
+#define S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET (0x02c038) /* TCD11 Last Destination Address Adjustment / Scatter Gather Address Register (TCD11_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD11_CSR_OFFSET (0x02c03c) /* TCD11 Control and Status Register (TCD11_CSR) */
+#define S32K3XX_EDMA_TCD11_BITER_OFFSET (0x02c03e) /* TCD11 Beginning Major Loop Count Register (TCD11_BITER) */
+
+#define S32K3XX_EDMA_CH12_CSR_OFFSET (0x200000) /* Channel 12 Control and Status Register (CH12_CSR) */
+#define S32K3XX_EDMA_CH12_ES_OFFSET (0x200004) /* Channel 12 Error Status Register (CH12_ES) */
+#define S32K3XX_EDMA_CH12_INT_OFFSET (0x200008) /* Channel 12 Interrupt Status Register (CH12_INT) */
+#define S32K3XX_EDMA_CH12_SBR_OFFSET (0x20000c) /* Channel 12 System Bus Register (CH12_SBR) */
+#define S32K3XX_EDMA_CH12_PRI_OFFSET (0x200010) /* Channel 12 Priority Register (CH12_PRI) */
+#define S32K3XX_EDMA_TCD12_SADDR_OFFSET (0x200020) /* TCD12 Source Address Register (TCD12_SADDR) */
+#define S32K3XX_EDMA_TCD12_SOFF_OFFSET (0x200024) /* TCD12 Signed Source Address Offset Register (TCD12_SOFF) */
+#define S32K3XX_EDMA_TCD12_ATTR_OFFSET (0x200026) /* TCD12 Transfer Attributes (TCD12_ATTR) */
+#define S32K3XX_EDMA_TCD12_NBYTES_OFFSET (0x200028) /* TCD12 Transfer Size (TCD12_NBYTES) */
+#define S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET (0x20002c) /* TCD12 Last Source Address Adjustment / Store DADDR Address Register (TCD12_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD12_DADDR_OFFSET (0x200030) /* TCD12 Destination Address Register (TCD12_DADDR) */
+#define S32K3XX_EDMA_TCD12_DOFF_OFFSET (0x200034) /* TCD12 Signed Destination Address Offset Register (TCD12_DOFF) */
+#define S32K3XX_EDMA_TCD12_CITER_OFFSET (0x200036) /* TCD12 Current Major Loop Count Register (TCD12_CITER) */
+#define S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET (0x200038) /* TCD12 Last Destination Address Adjustment / Scatter Gather Address Register (TCD12_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD12_CSR_OFFSET (0x20003c) /* TCD12 Control and Status Register (TCD12_CSR) */
+#define S32K3XX_EDMA_TCD12_BITER_OFFSET (0x20003e) /* TCD12 Beginning Major Loop Count Register (TCD12_BITER) */
+
+#define S32K3XX_EDMA_CH13_CSR_OFFSET (0x204000) /* Channel 13 Control and Status Register (CH13_CSR) */
+#define S32K3XX_EDMA_CH13_ES_OFFSET (0x204004) /* Channel 13 Error Status Register (CH13_ES) */
+#define S32K3XX_EDMA_CH13_INT_OFFSET (0x204008) /* Channel 13 Interrupt Status Register (CH13_INT) */
+#define S32K3XX_EDMA_CH13_SBR_OFFSET (0x20400c) /* Channel 13 System Bus Register (CH13_SBR) */
+#define S32K3XX_EDMA_CH13_PRI_OFFSET (0x204010) /* Channel 13 Priority Register (CH13_PRI) */
+#define S32K3XX_EDMA_TCD13_SADDR_OFFSET (0x204020) /* TCD13 Source Address Register (TCD13_SADDR) */
+#define S32K3XX_EDMA_TCD13_SOFF_OFFSET (0x204024) /* TCD13 Signed Source Address Offset Register (TCD13_SOFF) */
+#define S32K3XX_EDMA_TCD13_ATTR_OFFSET (0x204026) /* TCD13 Transfer Attributes (TCD13_ATTR) */
+#define S32K3XX_EDMA_TCD13_NBYTES_OFFSET (0x204028) /* TCD13 Transfer Size (TCD13_NBYTES) */
+#define S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET (0x20402c) /* TCD13 Last Source Address Adjustment / Store DADDR Address Register (TCD13_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD13_DADDR_OFFSET (0x204030) /* TCD13 Destination Address Register (TCD13_DADDR) */
+#define S32K3XX_EDMA_TCD13_DOFF_OFFSET (0x204034) /* TCD13 Signed Destination Address Offset Register (TCD13_DOFF) */
+#define S32K3XX_EDMA_TCD13_CITER_OFFSET (0x204036) /* TCD13 Current Major Loop Count Register (TCD13_CITER) */
+#define S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET (0x204038) /* TCD13 Last Destination Address Adjustment / Scatter Gather Address Register (TCD13_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD13_CSR_OFFSET (0x20403c) /* TCD13 Control and Status Register (TCD13_CSR) */
+#define S32K3XX_EDMA_TCD13_BITER_OFFSET (0x20403e) /* TCD13 Beginning Major Loop Count Register (TCD13_BITER) */
+
+#define S32K3XX_EDMA_CH14_CSR_OFFSET (0x208000) /* Channel 14 Control and Status Register (CH14_CSR) */
+#define S32K3XX_EDMA_CH14_ES_OFFSET (0x208004) /* Channel 14 Error Status Register (CH14_ES) */
+#define S32K3XX_EDMA_CH14_INT_OFFSET (0x208008) /* Channel 14 Interrupt Status Register (CH14_INT) */
+#define S32K3XX_EDMA_CH14_SBR_OFFSET (0x20800c) /* Channel 14 System Bus Register (CH14_SBR) */
+#define S32K3XX_EDMA_CH14_PRI_OFFSET (0x208010) /* Channel 14 Priority Register (CH14_PRI) */
+#define S32K3XX_EDMA_TCD14_SADDR_OFFSET (0x208020) /* TCD14 Source Address Register (TCD14_SADDR) */
+#define S32K3XX_EDMA_TCD14_SOFF_OFFSET (0x208024) /* TCD14 Signed Source Address Offset Register (TCD14_SOFF) */
+#define S32K3XX_EDMA_TCD14_ATTR_OFFSET (0x208026) /* TCD14 Transfer Attributes (TCD14_ATTR) */
+#define S32K3XX_EDMA_TCD14_NBYTES_OFFSET (0x208028) /* TCD14 Transfer Size (TCD14_NBYTES) */
+#define S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET (0x20802c) /* TCD14 Last Source Address Adjustment / Store DADDR Address Register (TCD14_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD14_DADDR_OFFSET (0x208030) /* TCD14 Destination Address Register (TCD14_DADDR) */
+#define S32K3XX_EDMA_TCD14_DOFF_OFFSET (0x208034) /* TCD14 Signed Destination Address Offset Register (TCD14_DOFF) */
+#define S32K3XX_EDMA_TCD14_CITER_OFFSET (0x208036) /* TCD14 Current Major Loop Count Register (TCD14_CITER) */
+#define S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET (0x208038) /* TCD14 Last Destination Address Adjustment / Scatter Gather Address Register (TCD14_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD14_CSR_OFFSET (0x20803c) /* TCD14 Control and Status Register (TCD14_CSR) */
+#define S32K3XX_EDMA_TCD14_BITER_OFFSET (0x20803e) /* TCD14 Beginning Major Loop Count Register (TCD14_BITER) */
+
+#define S32K3XX_EDMA_CH15_CSR_OFFSET (0x20c000) /* Channel 15 Control and Status Register (CH15_CSR) */
+#define S32K3XX_EDMA_CH15_ES_OFFSET (0x20c004) /* Channel 15 Error Status Register (CH15_ES) */
+#define S32K3XX_EDMA_CH15_INT_OFFSET (0x20c008) /* Channel 15 Interrupt Status Register (CH15_INT) */
+#define S32K3XX_EDMA_CH15_SBR_OFFSET (0x20c00c) /* Channel 15 System Bus Register (CH15_SBR) */
+#define S32K3XX_EDMA_CH15_PRI_OFFSET (0x20c010) /* Channel 15 Priority Register (CH15_PRI) */
+#define S32K3XX_EDMA_TCD15_SADDR_OFFSET (0x20c020) /* TCD15 Source Address Register (TCD15_SADDR) */
+#define S32K3XX_EDMA_TCD15_SOFF_OFFSET (0x20c024) /* TCD15 Signed Source Address Offset Register (TCD15_SOFF) */
+#define S32K3XX_EDMA_TCD15_ATTR_OFFSET (0x20c026) /* TCD15 Transfer Attributes (TCD15_ATTR) */
+#define S32K3XX_EDMA_TCD15_NBYTES_OFFSET (0x20c028) /* TCD15 Transfer Size (TCD15_NBYTES) */
+#define S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET (0x20c02c) /* TCD15 Last Source Address Adjustment / Store DADDR Address Register (TCD15_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD15_DADDR_OFFSET (0x20c030) /* TCD15 Destination Address Register (TCD15_DADDR) */
+#define S32K3XX_EDMA_TCD15_DOFF_OFFSET (0x20c034) /* TCD15 Signed Destination Address Offset Register (TCD15_DOFF) */
+#define S32K3XX_EDMA_TCD15_CITER_OFFSET (0x20c036) /* TCD15 Current Major Loop Count Register (TCD15_CITER) */
+#define S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET (0x20c038) /* TCD15 Last Destination Address Adjustment / Scatter Gather Address Register (TCD15_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD15_CSR_OFFSET (0x20c03c) /* TCD15 Control and Status Register (TCD15_CSR) */
+#define S32K3XX_EDMA_TCD15_BITER_OFFSET (0x20c03e) /* TCD15 Beginning Major Loop Count Register (TCD15_BITER) */
+
+#define S32K3XX_EDMA_CH16_CSR_OFFSET (0x210000) /* Channel 16 Control and Status Register (CH16_CSR) */
+#define S32K3XX_EDMA_CH16_ES_OFFSET (0x210004) /* Channel 16 Error Status Register (CH16_ES) */
+#define S32K3XX_EDMA_CH16_INT_OFFSET (0x210008) /* Channel 16 Interrupt Status Register (CH16_INT) */
+#define S32K3XX_EDMA_CH16_SBR_OFFSET (0x21000c) /* Channel 16 System Bus Register (CH16_SBR) */
+#define S32K3XX_EDMA_CH16_PRI_OFFSET (0x210010) /* Channel 16 Priority Register (CH16_PRI) */
+#define S32K3XX_EDMA_TCD16_SADDR_OFFSET (0x210020) /* TCD16 Source Address Register (TCD16_SADDR) */
+#define S32K3XX_EDMA_TCD16_SOFF_OFFSET (0x210024) /* TCD16 Signed Source Address Offset Register (TCD16_SOFF) */
+#define S32K3XX_EDMA_TCD16_ATTR_OFFSET (0x210026) /* TCD16 Transfer Attributes (TCD16_ATTR) */
+#define S32K3XX_EDMA_TCD16_NBYTES_OFFSET (0x210028) /* TCD16 Transfer Size (TCD16_NBYTES) */
+#define S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET (0x21002c) /* TCD16 Last Source Address Adjustment / Store DADDR Address Register (TCD16_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD16_DADDR_OFFSET (0x210030) /* TCD16 Destination Address Register (TCD16_DADDR) */
+#define S32K3XX_EDMA_TCD16_DOFF_OFFSET (0x210034) /* TCD16 Signed Destination Address Offset Register (TCD16_DOFF) */
+#define S32K3XX_EDMA_TCD16_CITER_OFFSET (0x210036) /* TCD16 Current Major Loop Count Register (TCD16_CITER) */
+#define S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET (0x210038) /* TCD16 Last Destination Address Adjustment / Scatter Gather Address Register (TCD16_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD16_CSR_OFFSET (0x21003c) /* TCD16 Control and Status Register (TCD16_CSR) */
+#define S32K3XX_EDMA_TCD16_BITER_OFFSET (0x21003e) /* TCD16 Beginning Major Loop Count Register (TCD16_BITER) */
+
+#define S32K3XX_EDMA_CH17_CSR_OFFSET (0x214000) /* Channel 17 Control and Status Register (CH17_CSR) */
+#define S32K3XX_EDMA_CH17_ES_OFFSET (0x214004) /* Channel 17 Error Status Register (CH17_ES) */
+#define S32K3XX_EDMA_CH17_INT_OFFSET (0x214008) /* Channel 17 Interrupt Status Register (CH17_INT) */
+#define S32K3XX_EDMA_CH17_SBR_OFFSET (0x21400c) /* Channel 17 System Bus Register (CH17_SBR) */
+#define S32K3XX_EDMA_CH17_PRI_OFFSET (0x214010) /* Channel 17 Priority Register (CH17_PRI) */
+#define S32K3XX_EDMA_TCD17_SADDR_OFFSET (0x214020) /* TCD17 Source Address Register (TCD17_SADDR) */
+#define S32K3XX_EDMA_TCD17_SOFF_OFFSET (0x214024) /* TCD17 Signed Source Address Offset Register (TCD17_SOFF) */
+#define S32K3XX_EDMA_TCD17_ATTR_OFFSET (0x214026) /* TCD17 Transfer Attributes (TCD17_ATTR) */
+#define S32K3XX_EDMA_TCD17_NBYTES_OFFSET (0x214028) /* TCD17 Transfer Size (TCD17_NBYTES) */
+#define S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET (0x21402c) /* TCD17 Last Source Address Adjustment / Store DADDR Address Register (TCD17_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD17_DADDR_OFFSET (0x214030) /* TCD17 Destination Address Register (TCD17_DADDR) */
+#define S32K3XX_EDMA_TCD17_DOFF_OFFSET (0x214034) /* TCD17 Signed Destination Address Offset Register (TCD17_DOFF) */
+#define S32K3XX_EDMA_TCD17_CITER_OFFSET (0x214036) /* TCD17 Current Major Loop Count Register (TCD17_CITER) */
+#define S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET (0x214038) /* TCD17 Last Destination Address Adjustment / Scatter Gather Address Register (TCD17_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD17_CSR_OFFSET (0x21403c) /* TCD17 Control and Status Register (TCD17_CSR) */
+#define S32K3XX_EDMA_TCD17_BITER_OFFSET (0x21403e) /* TCD17 Beginning Major Loop Count Register (TCD17_BITER) */
+
+#define S32K3XX_EDMA_CH18_CSR_OFFSET (0x218000) /* Channel 18 Control and Status Register (CH18_CSR) */
+#define S32K3XX_EDMA_CH18_ES_OFFSET (0x218004) /* Channel 18 Error Status Register (CH18_ES) */
+#define S32K3XX_EDMA_CH18_INT_OFFSET (0x218008) /* Channel 18 Interrupt Status Register (CH18_INT) */
+#define S32K3XX_EDMA_CH18_SBR_OFFSET (0x21800c) /* Channel 18 System Bus Register (CH18_SBR) */
+#define S32K3XX_EDMA_CH18_PRI_OFFSET (0x218010) /* Channel 18 Priority Register (CH18_PRI) */
+#define S32K3XX_EDMA_TCD18_SADDR_OFFSET (0x218020) /* TCD18 Source Address Register (TCD18_SADDR) */
+#define S32K3XX_EDMA_TCD18_SOFF_OFFSET (0x218024) /* TCD18 Signed Source Address Offset Register (TCD18_SOFF) */
+#define S32K3XX_EDMA_TCD18_ATTR_OFFSET (0x218026) /* TCD18 Transfer Attributes (TCD18_ATTR) */
+#define S32K3XX_EDMA_TCD18_NBYTES_OFFSET (0x218028) /* TCD18 Transfer Size (TCD18_NBYTES) */
+#define S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET (0x21802c) /* TCD18 Last Source Address Adjustment / Store DADDR Address Register (TCD18_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD18_DADDR_OFFSET (0x218030) /* TCD18 Destination Address Register (TCD18_DADDR) */
+#define S32K3XX_EDMA_TCD18_DOFF_OFFSET (0x218034) /* TCD18 Signed Destination Address Offset Register (TCD18_DOFF) */
+#define S32K3XX_EDMA_TCD18_CITER_OFFSET (0x218036) /* TCD18 Current Major Loop Count Register (TCD18_CITER) */
+#define S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET (0x218038) /* TCD18 Last Destination Address Adjustment / Scatter Gather Address Register (TCD18_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD18_CSR_OFFSET (0x21803c) /* TCD18 Control and Status Register (TCD18_CSR) */
+#define S32K3XX_EDMA_TCD18_BITER_OFFSET (0x21803e) /* TCD18 Beginning Major Loop Count Register (TCD18_BITER) */
+
+#define S32K3XX_EDMA_CH19_CSR_OFFSET (0x21c000) /* Channel 19 Control and Status Register (CH19_CSR) */
+#define S32K3XX_EDMA_CH19_ES_OFFSET (0x21c004) /* Channel 19 Error Status Register (CH19_ES) */
+#define S32K3XX_EDMA_CH19_INT_OFFSET (0x21c008) /* Channel 19 Interrupt Status Register (CH19_INT) */
+#define S32K3XX_EDMA_CH19_SBR_OFFSET (0x21c00c) /* Channel 19 System Bus Register (CH19_SBR) */
+#define S32K3XX_EDMA_CH19_PRI_OFFSET (0x21c010) /* Channel 19 Priority Register (CH19_PRI) */
+#define S32K3XX_EDMA_TCD19_SADDR_OFFSET (0x21c020) /* TCD19 Source Address Register (TCD19_SADDR) */
+#define S32K3XX_EDMA_TCD19_SOFF_OFFSET (0x21c024) /* TCD19 Signed Source Address Offset Register (TCD19_SOFF) */
+#define S32K3XX_EDMA_TCD19_ATTR_OFFSET (0x21c026) /* TCD19 Transfer Attributes (TCD19_ATTR) */
+#define S32K3XX_EDMA_TCD19_NBYTES_OFFSET (0x21c028) /* TCD19 Transfer Size (TCD19_NBYTES) */
+#define S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET (0x21c02c) /* TCD19 Last Source Address Adjustment / Store DADDR Address Register (TCD19_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD19_DADDR_OFFSET (0x21c030) /* TCD19 Destination Address Register (TCD19_DADDR) */
+#define S32K3XX_EDMA_TCD19_DOFF_OFFSET (0x21c034) /* TCD19 Signed Destination Address Offset Register (TCD19_DOFF) */
+#define S32K3XX_EDMA_TCD19_CITER_OFFSET (0x21c036) /* TCD19 Current Major Loop Count Register (TCD19_CITER) */
+#define S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET (0x21c038) /* TCD19 Last Destination Address Adjustment / Scatter Gather Address Register (TCD19_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD19_CSR_OFFSET (0x21c03c) /* TCD19 Control and Status Register (TCD19_CSR) */
+#define S32K3XX_EDMA_TCD19_BITER_OFFSET (0x21c03e) /* TCD19 Beginning Major Loop Count Register (TCD19_BITER) */
+
+#define S32K3XX_EDMA_CH20_CSR_OFFSET (0x220000) /* Channel 20 Control and Status Register (CH20_CSR) */
+#define S32K3XX_EDMA_CH20_ES_OFFSET (0x220004) /* Channel 20 Error Status Register (CH20_ES) */
+#define S32K3XX_EDMA_CH20_INT_OFFSET (0x220008) /* Channel 20 Interrupt Status Register (CH20_INT) */
+#define S32K3XX_EDMA_CH20_SBR_OFFSET (0x22000c) /* Channel 20 System Bus Register (CH20_SBR) */
+#define S32K3XX_EDMA_CH20_PRI_OFFSET (0x220010) /* Channel 20 Priority Register (CH20_PRI) */
+#define S32K3XX_EDMA_TCD20_SADDR_OFFSET (0x220020) /* TCD20 Source Address Register (TCD20_SADDR) */
+#define S32K3XX_EDMA_TCD20_SOFF_OFFSET (0x220024) /* TCD20 Signed Source Address Offset Register (TCD20_SOFF) */
+#define S32K3XX_EDMA_TCD20_ATTR_OFFSET (0x220026) /* TCD20 Transfer Attributes (TCD20_ATTR) */
+#define S32K3XX_EDMA_TCD20_NBYTES_OFFSET (0x220028) /* TCD20 Transfer Size (TCD20_NBYTES) */
+#define S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET (0x22002c) /* TCD20 Last Source Address Adjustment / Store DADDR Address Register (TCD20_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD20_DADDR_OFFSET (0x220030) /* TCD20 Destination Address Register (TCD20_DADDR) */
+#define S32K3XX_EDMA_TCD20_DOFF_OFFSET (0x220034) /* TCD20 Signed Destination Address Offset Register (TCD20_DOFF) */
+#define S32K3XX_EDMA_TCD20_CITER_OFFSET (0x220036) /* TCD20 Current Major Loop Count Register (TCD20_CITER) */
+#define S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET (0x220038) /* TCD20 Last Destination Address Adjustment / Scatter Gather Address Register (TCD20_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD20_CSR_OFFSET (0x22003c) /* TCD20 Control and Status Register (TCD20_CSR) */
+#define S32K3XX_EDMA_TCD20_BITER_OFFSET (0x22003e) /* TCD20 Beginning Major Loop Count Register (TCD20_BITER) */
+
+#define S32K3XX_EDMA_CH21_CSR_OFFSET (0x224000) /* Channel 21 Control and Status Register (CH21_CSR) */
+#define S32K3XX_EDMA_CH21_ES_OFFSET (0x224004) /* Channel 21 Error Status Register (CH21_ES) */
+#define S32K3XX_EDMA_CH21_INT_OFFSET (0x224008) /* Channel 21 Interrupt Status Register (CH21_INT) */
+#define S32K3XX_EDMA_CH21_SBR_OFFSET (0x22400c) /* Channel 21 System Bus Register (CH21_SBR) */
+#define S32K3XX_EDMA_CH21_PRI_OFFSET (0x224010) /* Channel 21 Priority Register (CH21_PRI) */
+#define S32K3XX_EDMA_TCD21_SADDR_OFFSET (0x224020) /* TCD21 Source Address Register (TCD21_SADDR) */
+#define S32K3XX_EDMA_TCD21_SOFF_OFFSET (0x224024) /* TCD21 Signed Source Address Offset Register (TCD21_SOFF) */
+#define S32K3XX_EDMA_TCD21_ATTR_OFFSET (0x224026) /* TCD21 Transfer Attributes (TCD21_ATTR) */
+#define S32K3XX_EDMA_TCD21_NBYTES_OFFSET (0x224028) /* TCD21 Transfer Size (TCD21_NBYTES) */
+#define S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET (0x22402c) /* TCD21 Last Source Address Adjustment / Store DADDR Address Register (TCD21_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD21_DADDR_OFFSET (0x224030) /* TCD21 Destination Address Register (TCD21_DADDR) */
+#define S32K3XX_EDMA_TCD21_DOFF_OFFSET (0x224034) /* TCD21 Signed Destination Address Offset Register (TCD21_DOFF) */
+#define S32K3XX_EDMA_TCD21_CITER_OFFSET (0x224036) /* TCD21 Current Major Loop Count Register (TCD21_CITER) */
+#define S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET (0x224038) /* TCD21 Last Destination Address Adjustment / Scatter Gather Address Register (TCD21_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD21_CSR_OFFSET (0x22403c) /* TCD21 Control and Status Register (TCD21_CSR) */
+#define S32K3XX_EDMA_TCD21_BITER_OFFSET (0x22403e) /* TCD21 Beginning Major Loop Count Register (TCD21_BITER) */
+
+#define S32K3XX_EDMA_CH22_CSR_OFFSET (0x228000) /* Channel 22 Control and Status Register (CH22_CSR) */
+#define S32K3XX_EDMA_CH22_ES_OFFSET (0x228004) /* Channel 22 Error Status Register (CH22_ES) */
+#define S32K3XX_EDMA_CH22_INT_OFFSET (0x228008) /* Channel 22 Interrupt Status Register (CH22_INT) */
+#define S32K3XX_EDMA_CH22_SBR_OFFSET (0x22800c) /* Channel 22 System Bus Register (CH22_SBR) */
+#define S32K3XX_EDMA_CH22_PRI_OFFSET (0x228010) /* Channel 22 Priority Register (CH22_PRI) */
+#define S32K3XX_EDMA_TCD22_SADDR_OFFSET (0x228020) /* TCD22 Source Address Register (TCD22_SADDR) */
+#define S32K3XX_EDMA_TCD22_SOFF_OFFSET (0x228024) /* TCD22 Signed Source Address Offset Register (TCD22_SOFF) */
+#define S32K3XX_EDMA_TCD22_ATTR_OFFSET (0x228026) /* TCD22 Transfer Attributes (TCD22_ATTR) */
+#define S32K3XX_EDMA_TCD22_NBYTES_OFFSET (0x228028) /* TCD22 Transfer Size (TCD22_NBYTES) */
+#define S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET (0x22802c) /* TCD22 Last Source Address Adjustment / Store DADDR Address Register (TCD22_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD22_DADDR_OFFSET (0x228030) /* TCD22 Destination Address Register (TCD22_DADDR) */
+#define S32K3XX_EDMA_TCD22_DOFF_OFFSET (0x228034) /* TCD22 Signed Destination Address Offset Register (TCD22_DOFF) */
+#define S32K3XX_EDMA_TCD22_CITER_OFFSET (0x228036) /* TCD22 Current Major Loop Count Register (TCD22_CITER) */
+#define S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET (0x228038) /* TCD22 Last Destination Address Adjustment / Scatter Gather Address Register (TCD22_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD22_CSR_OFFSET (0x22803c) /* TCD22 Control and Status Register (TCD22_CSR) */
+#define S32K3XX_EDMA_TCD22_BITER_OFFSET (0x22803e) /* TCD22 Beginning Major Loop Count Register (TCD22_BITER) */
+
+#define S32K3XX_EDMA_CH23_CSR_OFFSET (0x22c000) /* Channel 23 Control and Status Register (CH23_CSR) */
+#define S32K3XX_EDMA_CH23_ES_OFFSET (0x22c004) /* Channel 23 Error Status Register (CH23_ES) */
+#define S32K3XX_EDMA_CH23_INT_OFFSET (0x22c008) /* Channel 23 Interrupt Status Register (CH23_INT) */
+#define S32K3XX_EDMA_CH23_SBR_OFFSET (0x22c00c) /* Channel 23 System Bus Register (CH23_SBR) */
+#define S32K3XX_EDMA_CH23_PRI_OFFSET (0x22c010) /* Channel 23 Priority Register (CH23_PRI) */
+#define S32K3XX_EDMA_TCD23_SADDR_OFFSET (0x22c020) /* TCD23 Source Address Register (TCD23_SADDR) */
+#define S32K3XX_EDMA_TCD23_SOFF_OFFSET (0x22c024) /* TCD23 Signed Source Address Offset Register (TCD23_SOFF) */
+#define S32K3XX_EDMA_TCD23_ATTR_OFFSET (0x22c026) /* TCD23 Transfer Attributes (TCD23_ATTR) */
+#define S32K3XX_EDMA_TCD23_NBYTES_OFFSET (0x22c028) /* TCD23 Transfer Size (TCD23_NBYTES) */
+#define S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET (0x22c02c) /* TCD23 Last Source Address Adjustment / Store DADDR Address Register (TCD23_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD23_DADDR_OFFSET (0x22c030) /* TCD23 Destination Address Register (TCD23_DADDR) */
+#define S32K3XX_EDMA_TCD23_DOFF_OFFSET (0x22c034) /* TCD23 Signed Destination Address Offset Register (TCD23_DOFF) */
+#define S32K3XX_EDMA_TCD23_CITER_OFFSET (0x22c036) /* TCD23 Current Major Loop Count Register (TCD23_CITER) */
+#define S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET (0x22c038) /* TCD23 Last Destination Address Adjustment / Scatter Gather Address Register (TCD23_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD23_CSR_OFFSET (0x22c03c) /* TCD23 Control and Status Register (TCD23_CSR) */
+#define S32K3XX_EDMA_TCD23_BITER_OFFSET (0x22c03e) /* TCD23 Beginning Major Loop Count Register (TCD23_BITER) */
+
+#define S32K3XX_EDMA_CH24_CSR_OFFSET (0x230000) /* Channel 24 Control and Status Register (CH24_CSR) */
+#define S32K3XX_EDMA_CH24_ES_OFFSET (0x230004) /* Channel 24 Error Status Register (CH24_ES) */
+#define S32K3XX_EDMA_CH24_INT_OFFSET (0x230008) /* Channel 24 Interrupt Status Register (CH24_INT) */
+#define S32K3XX_EDMA_CH24_SBR_OFFSET (0x23000c) /* Channel 24 System Bus Register (CH24_SBR) */
+#define S32K3XX_EDMA_CH24_PRI_OFFSET (0x230010) /* Channel 24 Priority Register (CH24_PRI) */
+#define S32K3XX_EDMA_TCD24_SADDR_OFFSET (0x230020) /* TCD24 Source Address Register (TCD24_SADDR) */
+#define S32K3XX_EDMA_TCD24_SOFF_OFFSET (0x230024) /* TCD24 Signed Source Address Offset Register (TCD24_SOFF) */
+#define S32K3XX_EDMA_TCD24_ATTR_OFFSET (0x230026) /* TCD24 Transfer Attributes (TCD24_ATTR) */
+#define S32K3XX_EDMA_TCD24_NBYTES_OFFSET (0x230028) /* TCD24 Transfer Size (TCD24_NBYTES) */
+#define S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET (0x23002c) /* TCD24 Last Source Address Adjustment / Store DADDR Address Register (TCD24_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD24_DADDR_OFFSET (0x230030) /* TCD24 Destination Address Register (TCD24_DADDR) */
+#define S32K3XX_EDMA_TCD24_DOFF_OFFSET (0x230034) /* TCD24 Signed Destination Address Offset Register (TCD24_DOFF) */
+#define S32K3XX_EDMA_TCD24_CITER_OFFSET (0x230036) /* TCD24 Current Major Loop Count Register (TCD24_CITER) */
+#define S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET (0x230038) /* TCD24 Last Destination Address Adjustment / Scatter Gather Address Register (TCD24_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD24_CSR_OFFSET (0x23003c) /* TCD24 Control and Status Register (TCD24_CSR) */
+#define S32K3XX_EDMA_TCD24_BITER_OFFSET (0x23003e) /* TCD24 Beginning Major Loop Count Register (TCD24_BITER) */
+
+#define S32K3XX_EDMA_CH25_CSR_OFFSET (0x234000) /* Channel 25 Control and Status Register (CH25_CSR) */
+#define S32K3XX_EDMA_CH25_ES_OFFSET (0x234004) /* Channel 25 Error Status Register (CH25_ES) */
+#define S32K3XX_EDMA_CH25_INT_OFFSET (0x234008) /* Channel 25 Interrupt Status Register (CH25_INT) */
+#define S32K3XX_EDMA_CH25_SBR_OFFSET (0x23400c) /* Channel 25 System Bus Register (CH25_SBR) */
+#define S32K3XX_EDMA_CH25_PRI_OFFSET (0x234010) /* Channel 25 Priority Register (CH25_PRI) */
+#define S32K3XX_EDMA_TCD25_SADDR_OFFSET (0x234020) /* TCD25 Source Address Register (TCD25_SADDR) */
+#define S32K3XX_EDMA_TCD25_SOFF_OFFSET (0x234024) /* TCD25 Signed Source Address Offset Register (TCD25_SOFF) */
+#define S32K3XX_EDMA_TCD25_ATTR_OFFSET (0x234026) /* TCD25 Transfer Attributes (TCD25_ATTR) */
+#define S32K3XX_EDMA_TCD25_NBYTES_OFFSET (0x234028) /* TCD25 Transfer Size (TCD25_NBYTES) */
+#define S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET (0x23402c) /* TCD25 Last Source Address Adjustment / Store DADDR Address Register (TCD25_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD25_DADDR_OFFSET (0x234030) /* TCD25 Destination Address Register (TCD25_DADDR) */
+#define S32K3XX_EDMA_TCD25_DOFF_OFFSET (0x234034) /* TCD25 Signed Destination Address Offset Register (TCD25_DOFF) */
+#define S32K3XX_EDMA_TCD25_CITER_OFFSET (0x234036) /* TCD25 Current Major Loop Count Register (TCD25_CITER) */
+#define S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET (0x234038) /* TCD25 Last Destination Address Adjustment / Scatter Gather Address Register (TCD25_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD25_CSR_OFFSET (0x23403c) /* TCD25 Control and Status Register (TCD25_CSR) */
+#define S32K3XX_EDMA_TCD25_BITER_OFFSET (0x23403e) /* TCD25 Beginning Major Loop Count Register (TCD25_BITER) */
+
+#define S32K3XX_EDMA_CH26_CSR_OFFSET (0x238000) /* Channel 26 Control and Status Register (CH26_CSR) */
+#define S32K3XX_EDMA_CH26_ES_OFFSET (0x238004) /* Channel 26 Error Status Register (CH26_ES) */
+#define S32K3XX_EDMA_CH26_INT_OFFSET (0x238008) /* Channel 26 Interrupt Status Register (CH26_INT) */
+#define S32K3XX_EDMA_CH26_SBR_OFFSET (0x23800c) /* Channel 26 System Bus Register (CH26_SBR) */
+#define S32K3XX_EDMA_CH26_PRI_OFFSET (0x238010) /* Channel 26 Priority Register (CH26_PRI) */
+#define S32K3XX_EDMA_TCD26_SADDR_OFFSET (0x238020) /* TCD26 Source Address Register (TCD26_SADDR) */
+#define S32K3XX_EDMA_TCD26_SOFF_OFFSET (0x238024) /* TCD26 Signed Source Address Offset Register (TCD26_SOFF) */
+#define S32K3XX_EDMA_TCD26_ATTR_OFFSET (0x238026) /* TCD26 Transfer Attributes (TCD26_ATTR) */
+#define S32K3XX_EDMA_TCD26_NBYTES_OFFSET (0x238028) /* TCD26 Transfer Size (TCD26_NBYTES) */
+#define S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET (0x23802c) /* TCD26 Last Source Address Adjustment / Store DADDR Address Register (TCD26_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD26_DADDR_OFFSET (0x238030) /* TCD26 Destination Address Register (TCD26_DADDR) */
+#define S32K3XX_EDMA_TCD26_DOFF_OFFSET (0x238034) /* TCD26 Signed Destination Address Offset Register (TCD26_DOFF) */
+#define S32K3XX_EDMA_TCD26_CITER_OFFSET (0x238036) /* TCD26 Current Major Loop Count Register (TCD26_CITER) */
+#define S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET (0x238038) /* TCD26 Last Destination Address Adjustment / Scatter Gather Address Register (TCD26_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD26_CSR_OFFSET (0x23803c) /* TCD26 Control and Status Register (TCD26_CSR) */
+#define S32K3XX_EDMA_TCD26_BITER_OFFSET (0x23803e) /* TCD26 Beginning Major Loop Count Register (TCD26_BITER) */
+
+#define S32K3XX_EDMA_CH27_CSR_OFFSET (0x23c000) /* Channel 27 Control and Status Register (CH27_CSR) */
+#define S32K3XX_EDMA_CH27_ES_OFFSET (0x23c004) /* Channel 27 Error Status Register (CH27_ES) */
+#define S32K3XX_EDMA_CH27_INT_OFFSET (0x23c008) /* Channel 27 Interrupt Status Register (CH27_INT) */
+#define S32K3XX_EDMA_CH27_SBR_OFFSET (0x23c00c) /* Channel 27 System Bus Register (CH27_SBR) */
+#define S32K3XX_EDMA_CH27_PRI_OFFSET (0x23c010) /* Channel 27 Priority Register (CH27_PRI) */
+#define S32K3XX_EDMA_TCD27_SADDR_OFFSET (0x23c020) /* TCD27 Source Address Register (TCD27_SADDR) */
+#define S32K3XX_EDMA_TCD27_SOFF_OFFSET (0x23c024) /* TCD27 Signed Source Address Offset Register (TCD27_SOFF) */
+#define S32K3XX_EDMA_TCD27_ATTR_OFFSET (0x23c026) /* TCD27 Transfer Attributes (TCD27_ATTR) */
+#define S32K3XX_EDMA_TCD27_NBYTES_OFFSET (0x23c028) /* TCD27 Transfer Size (TCD27_NBYTES) */
+#define S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET (0x23c02c) /* TCD27 Last Source Address Adjustment / Store DADDR Address Register (TCD27_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD27_DADDR_OFFSET (0x23c030) /* TCD27 Destination Address Register (TCD27_DADDR) */
+#define S32K3XX_EDMA_TCD27_DOFF_OFFSET (0x23c034) /* TCD27 Signed Destination Address Offset Register (TCD27_DOFF) */
+#define S32K3XX_EDMA_TCD27_CITER_OFFSET (0x23c036) /* TCD27 Current Major Loop Count Register (TCD27_CITER) */
+#define S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET (0x23c038) /* TCD27 Last Destination Address Adjustment / Scatter Gather Address Register (TCD27_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD27_CSR_OFFSET (0x23c03c) /* TCD27 Control and Status Register (TCD27_CSR) */
+#define S32K3XX_EDMA_TCD27_BITER_OFFSET (0x23c03e) /* TCD27 Beginning Major Loop Count Register (TCD27_BITER) */
+
+#define S32K3XX_EDMA_CH28_CSR_OFFSET (0x240000) /* Channel 28 Control and Status Register (CH28_CSR) */
+#define S32K3XX_EDMA_CH28_ES_OFFSET (0x240004) /* Channel 28 Error Status Register (CH28_ES) */
+#define S32K3XX_EDMA_CH28_INT_OFFSET (0x240008) /* Channel 28 Interrupt Status Register (CH28_INT) */
+#define S32K3XX_EDMA_CH28_SBR_OFFSET (0x24000c) /* Channel 28 System Bus Register (CH28_SBR) */
+#define S32K3XX_EDMA_CH28_PRI_OFFSET (0x240010) /* Channel 28 Priority Register (CH28_PRI) */
+#define S32K3XX_EDMA_TCD28_SADDR_OFFSET (0x240020) /* TCD28 Source Address Register (TCD28_SADDR) */
+#define S32K3XX_EDMA_TCD28_SOFF_OFFSET (0x240024) /* TCD28 Signed Source Address Offset Register (TCD28_SOFF) */
+#define S32K3XX_EDMA_TCD28_ATTR_OFFSET (0x240026) /* TCD28 Transfer Attributes (TCD28_ATTR) */
+#define S32K3XX_EDMA_TCD28_NBYTES_OFFSET (0x240028) /* TCD28 Transfer Size (TCD28_NBYTES) */
+#define S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET (0x24002c) /* TCD28 Last Source Address Adjustment / Store DADDR Address Register (TCD28_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD28_DADDR_OFFSET (0x240030) /* TCD28 Destination Address Register (TCD28_DADDR) */
+#define S32K3XX_EDMA_TCD28_DOFF_OFFSET (0x240034) /* TCD28 Signed Destination Address Offset Register (TCD28_DOFF) */
+#define S32K3XX_EDMA_TCD28_CITER_OFFSET (0x240036) /* TCD28 Current Major Loop Count Register (TCD28_CITER) */
+#define S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET (0x240038) /* TCD28 Last Destination Address Adjustment / Scatter Gather Address Register (TCD28_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD28_CSR_OFFSET (0x24003c) /* TCD28 Control and Status Register (TCD28_CSR) */
+#define S32K3XX_EDMA_TCD28_BITER_OFFSET (0x24003e) /* TCD28 Beginning Major Loop Count Register (TCD28_BITER) */
+
+#define S32K3XX_EDMA_CH29_CSR_OFFSET (0x244000) /* Channel 29 Control and Status Register (CH29_CSR) */
+#define S32K3XX_EDMA_CH29_ES_OFFSET (0x244004) /* Channel 29 Error Status Register (CH29_ES) */
+#define S32K3XX_EDMA_CH29_INT_OFFSET (0x244008) /* Channel 29 Interrupt Status Register (CH29_INT) */
+#define S32K3XX_EDMA_CH29_SBR_OFFSET (0x24400c) /* Channel 29 System Bus Register (CH29_SBR) */
+#define S32K3XX_EDMA_CH29_PRI_OFFSET (0x244010) /* Channel 29 Priority Register (CH29_PRI) */
+#define S32K3XX_EDMA_TCD29_SADDR_OFFSET (0x244020) /* TCD29 Source Address Register (TCD29_SADDR) */
+#define S32K3XX_EDMA_TCD29_SOFF_OFFSET (0x244024) /* TCD29 Signed Source Address Offset Register (TCD29_SOFF) */
+#define S32K3XX_EDMA_TCD29_ATTR_OFFSET (0x244026) /* TCD29 Transfer Attributes (TCD29_ATTR) */
+#define S32K3XX_EDMA_TCD29_NBYTES_OFFSET (0x244028) /* TCD29 Transfer Size (TCD29_NBYTES) */
+#define S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET (0x24402c) /* TCD29 Last Source Address Adjustment / Store DADDR Address Register (TCD29_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD29_DADDR_OFFSET (0x244030) /* TCD29 Destination Address Register (TCD29_DADDR) */
+#define S32K3XX_EDMA_TCD29_DOFF_OFFSET (0x244034) /* TCD29 Signed Destination Address Offset Register (TCD29_DOFF) */
+#define S32K3XX_EDMA_TCD29_CITER_OFFSET (0x244036) /* TCD29 Current Major Loop Count Register (TCD29_CITER) */
+#define S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET (0x244038) /* TCD29 Last Destination Address Adjustment / Scatter Gather Address Register (TCD29_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD29_CSR_OFFSET (0x24403c) /* TCD29 Control and Status Register (TCD29_CSR) */
+#define S32K3XX_EDMA_TCD29_BITER_OFFSET (0x24403e) /* TCD29 Beginning Major Loop Count Register (TCD29_BITER) */
+
+#define S32K3XX_EDMA_CH30_CSR_OFFSET (0x248000) /* Channel 30 Control and Status Register (CH30_CSR) */
+#define S32K3XX_EDMA_CH30_ES_OFFSET (0x248004) /* Channel 30 Error Status Register (CH30_ES) */
+#define S32K3XX_EDMA_CH30_INT_OFFSET (0x248008) /* Channel 30 Interrupt Status Register (CH30_INT) */
+#define S32K3XX_EDMA_CH30_SBR_OFFSET (0x24800c) /* Channel 30 System Bus Register (CH30_SBR) */
+#define S32K3XX_EDMA_CH30_PRI_OFFSET (0x248010) /* Channel 30 Priority Register (CH30_PRI) */
+#define S32K3XX_EDMA_TCD30_SADDR_OFFSET (0x248020) /* TCD30 Source Address Register (TCD30_SADDR) */
+#define S32K3XX_EDMA_TCD30_SOFF_OFFSET (0x248024) /* TCD30 Signed Source Address Offset Register (TCD30_SOFF) */
+#define S32K3XX_EDMA_TCD30_ATTR_OFFSET (0x248026) /* TCD30 Transfer Attributes (TCD30_ATTR) */
+#define S32K3XX_EDMA_TCD30_NBYTES_OFFSET (0x248028) /* TCD30 Transfer Size (TCD30_NBYTES) */
+#define S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET (0x24802c) /* TCD30 Last Source Address Adjustment / Store DADDR Address Register (TCD30_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD30_DADDR_OFFSET (0x248030) /* TCD30 Destination Address Register (TCD30_DADDR) */
+#define S32K3XX_EDMA_TCD30_DOFF_OFFSET (0x248034) /* TCD30 Signed Destination Address Offset Register (TCD30_DOFF) */
+#define S32K3XX_EDMA_TCD30_CITER_OFFSET (0x248036) /* TCD30 Current Major Loop Count Register (TCD30_CITER) */
+#define S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET (0x248038) /* TCD30 Last Destination Address Adjustment / Scatter Gather Address Register (TCD30_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD30_CSR_OFFSET (0x24803c) /* TCD30 Control and Status Register (TCD30_CSR) */
+#define S32K3XX_EDMA_TCD30_BITER_OFFSET (0x24803e) /* TCD30 Beginning Major Loop Count Register (TCD30_BITER) */
+
+#define S32K3XX_EDMA_CH31_CSR_OFFSET (0x24c000) /* Channel 31 Control and Status Register (CH31_CSR) */
+#define S32K3XX_EDMA_CH31_ES_OFFSET (0x24c004) /* Channel 31 Error Status Register (CH31_ES) */
+#define S32K3XX_EDMA_CH31_INT_OFFSET (0x24c008) /* Channel 31 Interrupt Status Register (CH31_INT) */
+#define S32K3XX_EDMA_CH31_SBR_OFFSET (0x24c00c) /* Channel 31 System Bus Register (CH31_SBR) */
+#define S32K3XX_EDMA_CH31_PRI_OFFSET (0x24c010) /* Channel 31 Priority Register (CH31_PRI) */
+#define S32K3XX_EDMA_TCD31_SADDR_OFFSET (0x24c020) /* TCD31 Source Address Register (TCD31_SADDR) */
+#define S32K3XX_EDMA_TCD31_SOFF_OFFSET (0x24c024) /* TCD31 Signed Source Address Offset Register (TCD31_SOFF) */
+#define S32K3XX_EDMA_TCD31_ATTR_OFFSET (0x24c026) /* TCD31 Transfer Attributes (TCD31_ATTR) */
+#define S32K3XX_EDMA_TCD31_NBYTES_OFFSET (0x24c028) /* TCD31 Transfer Size (TCD31_NBYTES) */
+#define S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET (0x24c02c) /* TCD31 Last Source Address Adjustment / Store DADDR Address Register (TCD31_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD31_DADDR_OFFSET (0x24c030) /* TCD31 Destination Address Register (TCD31_DADDR) */
+#define S32K3XX_EDMA_TCD31_DOFF_OFFSET (0x24c034) /* TCD31 Signed Destination Address Offset Register (TCD31_DOFF) */
+#define S32K3XX_EDMA_TCD31_CITER_OFFSET (0x24c036) /* TCD31 Current Major Loop Count Register (TCD31_CITER) */
+#define S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET (0x24c038) /* TCD31 Last Destination Address Adjustment / Scatter Gather Address Register (TCD31_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD31_CSR_OFFSET (0x24c03c) /* TCD31 Control and Status Register (TCD31_CSR) */
+#define S32K3XX_EDMA_TCD31_BITER_OFFSET (0x24c03e) /* TCD31 Beginning Major Loop Count Register (TCD31_BITER) */
+
+/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/
+
+#define S32K3XX_EDMA_CH0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_CSR_OFFSET)
+#define S32K3XX_EDMA_CH0_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_ES_OFFSET)
+#define S32K3XX_EDMA_CH0_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_INT_OFFSET)
+#define S32K3XX_EDMA_CH0_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_SBR_OFFSET)
+#define S32K3XX_EDMA_CH0_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD0_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD0_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD0_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD0_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD0_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD0_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_CSR_OFFSET)
+#define S32K3XX_EDMA_CH1_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_ES_OFFSET)
+#define S32K3XX_EDMA_CH1_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_INT_OFFSET)
+#define S32K3XX_EDMA_CH1_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_SBR_OFFSET)
+#define S32K3XX_EDMA_CH1_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD1_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD1_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD1_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD1_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD1_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD1_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_CSR_OFFSET)
+#define S32K3XX_EDMA_CH2_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_ES_OFFSET)
+#define S32K3XX_EDMA_CH2_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_INT_OFFSET)
+#define S32K3XX_EDMA_CH2_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_SBR_OFFSET)
+#define S32K3XX_EDMA_CH2_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD2_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD2_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD2_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD2_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD2_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD2_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_CSR_OFFSET)
+#define S32K3XX_EDMA_CH3_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_ES_OFFSET)
+#define S32K3XX_EDMA_CH3_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_INT_OFFSET)
+#define S32K3XX_EDMA_CH3_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_SBR_OFFSET)
+#define S32K3XX_EDMA_CH3_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD3_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD3_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD3_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD3_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD3_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD3_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_CSR_OFFSET)
+#define S32K3XX_EDMA_CH4_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_ES_OFFSET)
+#define S32K3XX_EDMA_CH4_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_INT_OFFSET)
+#define S32K3XX_EDMA_CH4_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_SBR_OFFSET)
+#define S32K3XX_EDMA_CH4_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD4_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD4_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD4_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD4_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD4_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD4_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_CSR_OFFSET)
+#define S32K3XX_EDMA_CH5_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_ES_OFFSET)
+#define S32K3XX_EDMA_CH5_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_INT_OFFSET)
+#define S32K3XX_EDMA_CH5_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_SBR_OFFSET)
+#define S32K3XX_EDMA_CH5_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD5_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD5_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD5_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD5_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD5_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD5_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_CSR_OFFSET)
+#define S32K3XX_EDMA_CH6_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_ES_OFFSET)
+#define S32K3XX_EDMA_CH6_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_INT_OFFSET)
+#define S32K3XX_EDMA_CH6_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_SBR_OFFSET)
+#define S32K3XX_EDMA_CH6_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD6_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD6_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD6_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD6_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD6_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD6_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_CSR_OFFSET)
+#define S32K3XX_EDMA_CH7_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_ES_OFFSET)
+#define S32K3XX_EDMA_CH7_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_INT_OFFSET)
+#define S32K3XX_EDMA_CH7_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_SBR_OFFSET)
+#define S32K3XX_EDMA_CH7_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD7_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD7_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD7_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD7_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD7_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD7_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_CSR_OFFSET)
+#define S32K3XX_EDMA_CH8_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_ES_OFFSET)
+#define S32K3XX_EDMA_CH8_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_INT_OFFSET)
+#define S32K3XX_EDMA_CH8_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_SBR_OFFSET)
+#define S32K3XX_EDMA_CH8_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD8_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD8_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD8_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD8_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD8_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD8_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_CSR_OFFSET)
+#define S32K3XX_EDMA_CH9_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_ES_OFFSET)
+#define S32K3XX_EDMA_CH9_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_INT_OFFSET)
+#define S32K3XX_EDMA_CH9_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_SBR_OFFSET)
+#define S32K3XX_EDMA_CH9_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD9_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD9_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD9_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD9_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD9_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD9_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_CSR_OFFSET)
+#define S32K3XX_EDMA_CH10_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_ES_OFFSET)
+#define S32K3XX_EDMA_CH10_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_INT_OFFSET)
+#define S32K3XX_EDMA_CH10_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_SBR_OFFSET)
+#define S32K3XX_EDMA_CH10_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD10_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD10_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD10_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD10_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD10_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD10_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_CSR_OFFSET)
+#define S32K3XX_EDMA_CH11_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_ES_OFFSET)
+#define S32K3XX_EDMA_CH11_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_INT_OFFSET)
+#define S32K3XX_EDMA_CH11_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_SBR_OFFSET)
+#define S32K3XX_EDMA_CH11_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD11_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD11_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD11_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD11_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD11_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD11_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_CSR_OFFSET)
+#define S32K3XX_EDMA_CH12_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_ES_OFFSET)
+#define S32K3XX_EDMA_CH12_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_INT_OFFSET)
+#define S32K3XX_EDMA_CH12_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_SBR_OFFSET)
+#define S32K3XX_EDMA_CH12_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD12_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD12_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD12_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD12_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD12_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD12_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_CSR_OFFSET)
+#define S32K3XX_EDMA_CH13_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_ES_OFFSET)
+#define S32K3XX_EDMA_CH13_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_INT_OFFSET)
+#define S32K3XX_EDMA_CH13_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_SBR_OFFSET)
+#define S32K3XX_EDMA_CH13_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD13_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD13_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD13_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD13_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD13_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD13_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_CSR_OFFSET)
+#define S32K3XX_EDMA_CH14_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_ES_OFFSET)
+#define S32K3XX_EDMA_CH14_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_INT_OFFSET)
+#define S32K3XX_EDMA_CH14_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_SBR_OFFSET)
+#define S32K3XX_EDMA_CH14_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD14_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD14_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD14_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD14_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD14_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD14_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_CSR_OFFSET)
+#define S32K3XX_EDMA_CH15_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_ES_OFFSET)
+#define S32K3XX_EDMA_CH15_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_INT_OFFSET)
+#define S32K3XX_EDMA_CH15_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_SBR_OFFSET)
+#define S32K3XX_EDMA_CH15_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD15_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD15_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD15_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD15_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD15_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD15_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_CSR_OFFSET)
+#define S32K3XX_EDMA_CH16_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_ES_OFFSET)
+#define S32K3XX_EDMA_CH16_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_INT_OFFSET)
+#define S32K3XX_EDMA_CH16_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_SBR_OFFSET)
+#define S32K3XX_EDMA_CH16_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD16_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD16_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD16_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD16_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD16_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD16_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_CSR_OFFSET)
+#define S32K3XX_EDMA_CH17_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_ES_OFFSET)
+#define S32K3XX_EDMA_CH17_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_INT_OFFSET)
+#define S32K3XX_EDMA_CH17_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_SBR_OFFSET)
+#define S32K3XX_EDMA_CH17_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD17_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD17_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD17_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD17_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD17_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD17_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_CSR_OFFSET)
+#define S32K3XX_EDMA_CH18_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_ES_OFFSET)
+#define S32K3XX_EDMA_CH18_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_INT_OFFSET)
+#define S32K3XX_EDMA_CH18_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_SBR_OFFSET)
+#define S32K3XX_EDMA_CH18_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD18_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD18_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD18_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD18_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD18_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD18_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_CSR_OFFSET)
+#define S32K3XX_EDMA_CH19_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_ES_OFFSET)
+#define S32K3XX_EDMA_CH19_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_INT_OFFSET)
+#define S32K3XX_EDMA_CH19_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_SBR_OFFSET)
+#define S32K3XX_EDMA_CH19_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD19_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD19_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD19_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD19_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD19_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD19_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_CSR_OFFSET)
+#define S32K3XX_EDMA_CH20_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_ES_OFFSET)
+#define S32K3XX_EDMA_CH20_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_INT_OFFSET)
+#define S32K3XX_EDMA_CH20_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_SBR_OFFSET)
+#define S32K3XX_EDMA_CH20_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD20_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD20_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD20_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD20_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD20_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD20_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_CSR_OFFSET)
+#define S32K3XX_EDMA_CH21_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_ES_OFFSET)
+#define S32K3XX_EDMA_CH21_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_INT_OFFSET)
+#define S32K3XX_EDMA_CH21_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_SBR_OFFSET)
+#define S32K3XX_EDMA_CH21_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD21_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD21_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD21_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD21_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD21_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD21_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_CSR_OFFSET)
+#define S32K3XX_EDMA_CH22_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_ES_OFFSET)
+#define S32K3XX_EDMA_CH22_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_INT_OFFSET)
+#define S32K3XX_EDMA_CH22_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_SBR_OFFSET)
+#define S32K3XX_EDMA_CH22_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD22_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD22_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD22_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD22_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD22_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD22_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_CSR_OFFSET)
+#define S32K3XX_EDMA_CH23_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_ES_OFFSET)
+#define S32K3XX_EDMA_CH23_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_INT_OFFSET)
+#define S32K3XX_EDMA_CH23_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_SBR_OFFSET)
+#define S32K3XX_EDMA_CH23_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD23_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD23_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD23_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD23_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD23_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD23_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_CSR_OFFSET)
+#define S32K3XX_EDMA_CH24_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_ES_OFFSET)
+#define S32K3XX_EDMA_CH24_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_INT_OFFSET)
+#define S32K3XX_EDMA_CH24_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_SBR_OFFSET)
+#define S32K3XX_EDMA_CH24_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD24_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD24_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD24_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD24_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD24_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD24_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_CSR_OFFSET)
+#define S32K3XX_EDMA_CH25_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_ES_OFFSET)
+#define S32K3XX_EDMA_CH25_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_INT_OFFSET)
+#define S32K3XX_EDMA_CH25_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_SBR_OFFSET)
+#define S32K3XX_EDMA_CH25_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD25_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD25_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD25_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD25_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD25_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD25_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_CSR_OFFSET)
+#define S32K3XX_EDMA_CH26_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_ES_OFFSET)
+#define S32K3XX_EDMA_CH26_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_INT_OFFSET)
+#define S32K3XX_EDMA_CH26_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_SBR_OFFSET)
+#define S32K3XX_EDMA_CH26_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD26_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD26_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD26_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD26_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD26_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD26_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_CSR_OFFSET)
+#define S32K3XX_EDMA_CH27_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_ES_OFFSET)
+#define S32K3XX_EDMA_CH27_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_INT_OFFSET)
+#define S32K3XX_EDMA_CH27_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_SBR_OFFSET)
+#define S32K3XX_EDMA_CH27_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD27_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD27_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD27_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD27_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD27_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD27_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_CSR_OFFSET)
+#define S32K3XX_EDMA_CH28_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_ES_OFFSET)
+#define S32K3XX_EDMA_CH28_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_INT_OFFSET)
+#define S32K3XX_EDMA_CH28_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_SBR_OFFSET)
+#define S32K3XX_EDMA_CH28_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD28_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD28_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD28_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD28_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD28_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD28_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_CSR_OFFSET)
+#define S32K3XX_EDMA_CH29_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_ES_OFFSET)
+#define S32K3XX_EDMA_CH29_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_INT_OFFSET)
+#define S32K3XX_EDMA_CH29_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_SBR_OFFSET)
+#define S32K3XX_EDMA_CH29_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD29_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD29_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD29_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD29_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD29_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD29_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_CSR_OFFSET)
+#define S32K3XX_EDMA_CH30_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_ES_OFFSET)
+#define S32K3XX_EDMA_CH30_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_INT_OFFSET)
+#define S32K3XX_EDMA_CH30_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_SBR_OFFSET)
+#define S32K3XX_EDMA_CH30_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD30_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD30_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD30_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD30_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD30_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD30_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_CSR_OFFSET)
+#define S32K3XX_EDMA_CH31_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_ES_OFFSET)
+#define S32K3XX_EDMA_CH31_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_INT_OFFSET)
+#define S32K3XX_EDMA_CH31_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_SBR_OFFSET)
+#define S32K3XX_EDMA_CH31_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD31_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD31_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD31_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD31_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD31_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD31_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_BITER_OFFSET)
+
+uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
+{
+ S32K3XX_EDMA_CH0_CSR,
Review Comment:
2 spaces indentation for this block
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h:
##########
@@ -0,0 +1,88 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FXOSC_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FXOSC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* FXOSC Register Offsets ***************************************************/
+
+#define S32K3XX_FXOSC_CTRL_OFFSET (0x00) /* FXOSC Control Register (CTRL) */
+#define S32K3XX_FXOSC_STAT_OFFSET (0x04) /* Oscillator Status Register (STAT) */
+
+/* FXOSC Register Addresses *************************************************/
+
+#define S32K3XX_FXOSC_CTRL (S32K3XX_FXOSC_BASE + S32K3XX_FXOSC_CTRL_OFFSET)
+#define S32K3XX_FXOSC_STAT (S32K3XX_FXOSC_BASE + S32K3XX_FXOSC_STAT_OFFSET)
+
+/* FXOSC Register Bitfield Definitions **************************************/
+
+/* FXOSC Control Register (CTRL) */
+
+#define FXOSC_CTRL_OSCON (1 << 0) /* Bit 0: Enables FXOSC (OSCON) */
+# define FXOSC_CTRL_OSCOFF (0 << 0) /* Disables FXOSC */
+ /* Bits 1-3: Reserved */
+#define FXOSC_CTRL_GM_SEL_SHIFT (4) /* Bits 4-7: Crystal overdrive protection, transconductance selection (GM_SEL) */
+#define FXOSC_CTRL_GM_SEL_MASK (0x0f << FXOSC_CTRL_GM_SEL_SHIFT)
+# define FXOSC_CTRL_GM_SEL_0X (0x00 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0x */
+# define FXOSC_CTRL_GM_SEL_0_1004X (0x01 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.1004x */
+# define FXOSC_CTRL_GM_SEL_0_2009X (0x02 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.2009x */
+# define FXOSC_CTRL_GM_SEL_0_3013X (0x03 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.3013x */
+# define FXOSC_CTRL_GM_SEL_0_2343X (0x04 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.2343x */
+# define FXOSC_CTRL_GM_SEL_0_3348X (0x05 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.3348x */
+# define FXOSC_CTRL_GM_SEL_0_4345X (0x06 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.4345x */
+# define FXOSC_CTRL_GM_SEL_0_5349X (0x07 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.5349x */
+# define FXOSC_CTRL_GM_SEL_0_4679X (0x08 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.4679x */
+# define FXOSC_CTRL_GM_SEL_0_5684X (0x09 << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.5684x */
+# define FXOSC_CTRL_GM_SEL_0_6681X (0x0a << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.6681x */
+# define FXOSC_CTRL_GM_SEL_0_7678X (0x0b << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.7678x */
+# define FXOSC_CTRL_GM_SEL_0_7016X (0x0c << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.7016x */
+# define FXOSC_CTRL_GM_SEL_0_8013X (0x0d << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.8013x */
+# define FXOSC_CTRL_GM_SEL_0_9003X (0x0e << FXOSC_CTRL_GM_SEL_SHIFT) /* 0.9003x */
+# define FXOSC_CTRL_GM_SEL_1X (0x0f << FXOSC_CTRL_GM_SEL_SHIFT) /* 1x */
+
+ /* Bits 8-15: Reserved */
+#define FXOSC_CTRL_EOCV_SHIFT (16) /* Bits 16-23: End of count value (EOCV) */
+#define FXOSC_CTRL_EOCV_MASK (0xff << FXOSC_CTRL_EOCV_SHIFT)
+#define FXOSC_CTRL_EOCV(n) ((n << FXOSC_CTRL_EOCV_SHIFT) & FXOSC_CTRL_EOCV_MASK)
Review Comment:
```suggestion
#define FXOSC_CTRL_EOCV(n) (((n) << FXOSC_CTRL_EOCV_SHIFT) & FXOSC_CTRL_EOCV_MASK)
```
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h:
##########
@@ -0,0 +1,499 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* MCU TO FS26 **************************************************************/
+
+#define FS26_M_FS (1 << 31) /* Bit 31: Main or Fail-safe register selection (M/FS) */
+#define FS26_REG_ADDR_SHIFT (25) /* Bits 25-31: Register Address + M/FS */
+#define FS26_REG_ADDR_MASK (0x7F << FS26_REG_ADDR_SHIFT)
+#define FS26_REG_ADDR(n) (((n) << FS26_REG_ADDR_SHIFT) & FS26_REG_ADDR_MASK)
+#define FS26_RW (1 << 24) /* Bit 24: Read/Write (reading Bit 24 = 0) */
+
+/* FS26 General device status ***********************************************/
+
+#define FS26_M_AVAL (1 << 31) /* Bit 31: Main State machine availability (M_AVAL) */
+#define FS26_FS_EN (1 << 30) /* Bit 30: Fail Safe State machine status (FS_EN) */
+#define FS26_FS_G (1 << 29) /* Bit 29: Interrupt notification from the Fail-Safe domain (FS_G) */
+#define FS26_COM_G (1 << 28) /* Bit 28: Interrupt notification from the M_COM_FLG register (COM_G) */
+#define FS26_WIO_G (1 << 27) /* Bit 27: Interrupt notification from the M_WIO_FLG register (WIO_G) */
+#define FS26_VSUP_G (1 << 26) /* Bit 26: Interrupt notification from the M_VSUP_FLG register (VSUP_G) */
+#define FS26_REG_G (1 << 25) /* Bit 25: Interrupt notification from the M_REG_FLG register (REG_G) */
+#define FS26_TSD_G (1 << 24) /* Bit 24: Interrupt notification from the M_TSD_FLG register (TSD_G) */
+
+/* FS26 Data encoding********************************************************/
+
+#define FS26_DATA_LSB_SHIFT (8) /* Bits 8-15: DATA_LSB */
+#define FS26_DATA_LSB_MASK (0xFF << FS26_DATA_LSB_SHIFT)
+#define FS26_DATA_LSB(n) (((n) << FS26_DATA_LSB_SHIFT) & FS26_DATA_LSB_MASK)
+#define FS26_DATA_MSB_SHIFT (16) /* Bits 16-23: DATA_MSB */
+#define FS26_DATA_MSB_MASK (0xFF << FS26_DATA_MSB_SHIFT)
+#define FS26_DATA_MSB(n) (((n) << FS26_DATA_MSB_SHIFT) & FS26_DATA_MSB_MASK)
+#define FS26_DATA_SHIFT (8) /* Bits 8-23: DATA_MSB */
+#define FS26_DATA_MASK (0xFFFF << FS26_DATA_SHIFT)
+#define FS26_SET_DATA(n) (((n) << FS26_DATA_SHIFT) & FS26_DATA_MASK)
+#define FS26_GET_DATA(n) (((n) & FS26_DATA_MASK) >> FS26_DATA_SHIFT)
+#define FS26_CRC_SHIFT (0) /* Bits 0-7: CRC */
+#define FS26_CRC_MASK (0xFF << FS26_CRC_SHIFT)
+#define FS26_CRC(n) (((n) << FS26_CRC_SHIFT) & FS26_CRC_MASK)
+
+/* FS26 SPI register map */
+
+#define FS26_M_DEVICE_ID (0x0) /* */
+#define FS26_M_PROGID (0x1) /* */
+#define FS26_M_STATUS (0x2) /* */
+#define FS26_M_TSD_FLG (0x3) /* */
+#define FS26_M_TSD_MSK (0x4) /* */
+#define FS26_M_REG_FLG (0x5) /* */
+#define FS26_M_REG_MSK (0x6) /* */
+#define FS26_M_VSUP_FLG (0x7) /* */
+#define FS26_M_VSUP_MSK (0x8) /* */
+#define FS26_M_WIO_FLG (0x9) /* */
+#define FS26_M_WIO_MSK (0xA) /* */
+#define FS26_M_COM_FLG (0xB) /* */
+#define FS26_M_COM_MSK (0xC) /* */
+#define FS26_M_SYS_CFG (0xD) /* */
+#define FS26_M_TSD_CFG (0xE) /* */
+#define FS26_M_REG_CFG (0xF) /* */
+#define FS26_M_WIO_CFG (0x10) /* */
+#define FS26_M_REG_CTRL1 (0x11) /* */
+#define FS26_M_REG_CTRL2 (0x12) /* */
+#define FS26_M_AMUX_CTRL (0x13) /* */
+#define FS26_M_LDT_CFG1 (0x14) /* */
+#define FS26_M_LDT_CFG2 (0x15) /* */
+#define FS26_M_LDT_CFG3 (0x16) /* */
+#define FS26_M_LDT_CTRL (0x17) /* */
+#define FS26_M_MEMORY0 (0x18) /* */
+#define FS26_M_MEMORY1 (0x19) /* */
+
+/* FS26 Fail safe register map */
+#define FS26_FS_GRL_FLAGS (0x40) /* */
+#define FS26_FS_I_OVUV_SAFE_REACTION1 (0x41) /* */
+#define FS26_FS_I_NOT_OVUV_SAFE_REACTION1 (0x42) /* */
+#define FS26_FS_I_OVUV_SAFE_REACTION2 (0x43) /* */
+#define FS26_FS_I_NOT_OVUV_SAFE_REACTION2 (0x44) /* */
+#define FS26_FS_I_WD_CFG (0x45) /* */
+#define FS26_FS_I_NOT_WD_CFG (0x46) /* */
+#define FS26_FS_I_SAFE_INPUTS (0x47) /* */
+#define FS26_FS_I_NOT_SAFE_INPUTS (0x48) /* */
+#define FS26_FS_I_FSSM (0x49) /* */
+#define FS26_FS_I_NOT_FSSM (0x4A) /* */
+#define FS26_FS_WDW_DURATION (0x4B) /* */
+#define FS26_FS_NOT_WDW_DURATION (0x4C) /* */
+#define FS26_FS_WD_ANSWER (0x4D) /* */
+#define FS26_FS_WD_TOKEN (0x4E) /* */
+#define FS26_FS_ABIST_ON_DEMAND (0x4F) /* */
+#define FS26_FS_OVUV_REG_STATUS (0x50) /* */
+#define FS26_FS_RELEASE_FS0B_FS1B (0x51) /* */
+#define FS26_FS_SAFE_IOS_1 (0x52) /* */
+#define FS26_FS_SAFE_IOS_2 (0x53) /* */
+#define FS26_FS_DIAG_SAFETY1 (0x54) /* */
+#define FS26_FS_DIAG_SAFETY2 (0x55) /* */
+#define FS26_FS_INTB_MASK (0x56) /* */
+#define FS26_FS_STATES (0x57) /* */
+#define FS26_FS_LP_REQ (0x58) /* */
+#define FS26_FS_LDT_LPSEL (0x59) /* */
+
+/* FS_I_OVUV_SAFE_REACTION1 register */
+
+#define VMON_PRE_OV_FS_REACTION_SHIFT (14) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_PRE */
+#define VMON_PRE_OV_FS_REACTION_MASK (0x3 << VMON_PRE_OV_FS_REACTION_SHIFT)
+# define VMON_PRE_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_PRE_OV_FS_REACTION_SHIFT)
+# define VMON_PRE_OV_FS_REACTION_FS0B (0x1 << VMON_PRE_OV_FS_REACTION_SHIFT)
+# define VMON_PRE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_OV_FS_REACTION_SHIFT)
+
+#define VMON_PRE_UV_FS_REACTION_SHIFT (12) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_PRE */
+#define VMON_PRE_UV_FS_REACTION_MASK (0x3 << VMON_PRE_UV_FS_REACTION_SHIFT)
+# define VMON_PRE_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_PRE_UV_FS_REACTION_SHIFT)
+# define VMON_PRE_UV_FS_REACTION_FS0B (0x1 << VMON_PRE_UV_FS_REACTION_SHIFT)
+# define VMON_PRE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_UV_FS_REACTION_SHIFT)
+
+#define VMON_CORE_OV_FS_REACTION_SHIFT (10) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_CORE */
+#define VMON_CORE_OV_FS_REACTION_MASK (0x3 << VMON_CORE_OV_FS_REACTION_SHIFT)
+# define VMON_CORE_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_CORE_OV_FS_REACTION_SHIFT)
+# define VMON_CORE_OV_FS_REACTION_FS0B (0x1 << VMON_CORE_OV_FS_REACTION_SHIFT)
+# define VMON_CORE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_OV_FS_REACTION_SHIFT)
+
+#define VMON_CORE_UV_FS_REACTION_SHIFT (8) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_CORE */
+#define VMON_CORE_UV_FS_REACTION_MASK (0x3 << VMON_CORE_UV_FS_REACTION_SHIFT)
+# define VMON_CORE_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_CORE_UV_FS_REACTION_SHIFT)
+# define VMON_CORE_UV_FS_REACTION_FS0B (0x1 << VMON_CORE_UV_FS_REACTION_SHIFT)
+# define VMON_CORE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_UV_FS_REACTION_SHIFT)
+
+#define VMON_LDO1_OV_FS_REACTION_SHIFT (6) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_LDO1 */
+#define VMON_LDO1_OV_FS_REACTION_MASK (0x3 << VMON_LDO1_OV_FS_REACTION_SHIFT)
+# define VMON_LDO1_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO1_OV_FS_REACTION_SHIFT)
+# define VMON_LDO1_OV_FS_REACTION_FS0B (0x1 << VMON_LDO1_OV_FS_REACTION_SHIFT)
+# define VMON_LDO1_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_OV_FS_REACTION_SHIFT)
+
+#define VMON_LDO1_UV_FS_REACTION_SHIFT (4) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_LDO1 */
+#define VMON_LDO1_UV_FS_REACTION_MASK (0x3 << VMON_LDO1_UV_FS_REACTION_SHIFT)
+# define VMON_LDO1_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO1_UV_FS_REACTION_SHIFT)
+# define VMON_LDO1_UV_FS_REACTION_FS0B (0x1 << VMON_LDO1_UV_FS_REACTION_SHIFT)
+# define VMON_LDO1_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_UV_FS_REACTION_SHIFT)
+
+#define VMON_LDO2_OV_FS_REACTION_SHIFT (2) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_LDO2 */
+#define VMON_LDO2_OV_FS_REACTION_MASK (0x3 << VMON_LDO2_OV_FS_REACTION_SHIFT)
+# define VMON_LDO2_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO2_OV_FS_REACTION_SHIFT)
+# define VMON_LDO2_OV_FS_REACTION_FS0B (0x1 << VMON_LDO2_OV_FS_REACTION_SHIFT)
+# define VMON_LDO2_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO2_OV_FS_REACTION_SHIFT)
+
+#define VMON_LDO2_UV_FS_REACTION_SHIFT (0) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_LDO2 */
+#define VMON_LDO2_UV_FS_REACTION_MASK (0x3 << VMON_LDO2_UV_FS_REACTION_SHIFT)
+# define VMON_LDO2_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO2_UV_FS_REACTION_SHIFT)
+# define VMON_LDO2_UV_FS_REACTION_FS0B (0x1 << VMON_LDO2_UV_FS_REACTION_SHIFT)
+# define VMON_LDO2_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO2_UV_FS_REACTION_SHIFT)
+
+/* FS_I_OVUV_SAFE_REACTION2 register */
+
+#define VMON_EXT_OV_FS_REACTION_SHIFT (14) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_EXT */
+#define VMON_EXT_OV_FS_REACTION_MASK (0x3 << VMON_EXT_OV_FS_REACTION_SHIFT)
+# define VMON_EXT_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_EXT_OV_FS_REACTION_SHIFT)
+# define VMON_EXT_OV_FS_REACTION_FS0B (0x1 << VMON_EXT_OV_FS_REACTION_SHIFT)
+# define VMON_EXT_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_EXT_OV_FS_REACTION_SHIFT)
+
+#define VMON_EXT_UV_FS_REACTION_SHIFT (12) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_EXT */
+#define VMON_EXT_UV_FS_REACTION_MASK (0x3 << VMON_EXT_UV_FS_REACTION_SHIFT)
+# define VMON_EXT_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_EXT_UV_FS_REACTION_SHIFT)
+# define VMON_EXT_UV_FS_REACTION_FS0B (0x1 << VMON_EXT_UV_FS_REACTION_SHIFT)
+# define VMON_EXT_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_EXT_UV_FS_REACTION_SHIFT)
+
+#define VMON_REF_OV_FS_REACTION_SHIFT (10) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_REF */
+#define VMON_REF_OV_FS_REACTION_MASK (0x3 << VMON_REF_OV_FS_REACTION_SHIFT)
+# define VMON_REF_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_REF_OV_FS_REACTION_SHIFT)
+# define VMON_REF_OV_FS_REACTION_FS0B (0x1 << VMON_REF_OV_FS_REACTION_SHIFT)
+# define VMON_REF_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_REF_OV_FS_REACTION_SHIFT)
+
+#define VMON_REF_UV_FS_REACTION_SHIFT (8) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_REF */
+#define VMON_REF_UV_FS_REACTION_MASK (0x3 << VMON_REF_UV_FS_REACTION_SHIFT)
+# define VMON_REF_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_REF_UV_FS_REACTION_SHIFT)
+# define VMON_REF_UV_FS_REACTION_FS0B (0x1 << VMON_REF_UV_FS_REACTION_SHIFT)
+# define VMON_REF_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_REF_UV_FS_REACTION_SHIFT)
+
+#define VMON_TRK2_OV_FS_REACTION_SHIFT (6) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_TRK2 */
+#define VMON_TRK2_OV_FS_REACTION_MASK (0x3 << VMON_TRK2_OV_FS_REACTION_SHIFT)
+# define VMON_TRK2_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK2_OV_FS_REACTION_SHIFT)
+# define VMON_TRK2_OV_FS_REACTION_FS0B (0x1 << VMON_TRK2_OV_FS_REACTION_SHIFT)
+# define VMON_TRK2_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK2_OV_FS_REACTION_SHIFT)
+
+#define VMON_TRK2_UV_FS_REACTION_SHIFT (4) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_TRK2 */
+#define VMON_TRK2_UV_FS_REACTION_MASK (0x3 << VMON_TRK2_UV_FS_REACTION_SHIFT)
+# define VMON_TRK2_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK2_UV_FS_REACTION_SHIFT)
+# define VMON_TRK2_UV_FS_REACTION_FS0B (0x1 << VMON_TRK2_UV_FS_REACTION_SHIFT)
+# define VMON_TRK2_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK2_UV_FS_REACTION_SHIFT)
+
+#define VMON_TRK1_OV_FS_REACTION_SHIFT (2) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_TRK1 */
+#define VMON_TRK1_OV_FS_REACTION_MASK (0x3 << VMON_TRK1_OV_FS_REACTION_SHIFT)
+# define VMON_TRK1_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK1_OV_FS_REACTION_SHIFT)
+# define VMON_TRK1_OV_FS_REACTION_FS0B (0x1 << VMON_TRK1_OV_FS_REACTION_SHIFT)
+# define VMON_TRK1_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK1_OV_FS_REACTION_SHIFT)
+
+#define VMON_TRK1_UV_FS_REACTION_SHIFT (0) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_TRK1 */
+#define VMON_TRK1_UV_FS_REACTION_MASK (0x3 << VMON_TRK1_UV_FS_REACTION_SHIFT)
+# define VMON_TRK1_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK1_UV_FS_REACTION_SHIFT)
+# define VMON_TRK1_UV_FS_REACTION_FS0B (0x1 << VMON_TRK1_UV_FS_REACTION_SHIFT)
+# define VMON_TRK1_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK1_UV_FS_REACTION_SHIFT)
+
+/* FS26_FS_I_WD_CFG register */
+
+#define WD_ERR_LIMIT_SHIFT (14) /* Watchdog error counter limit */
+#define WD_ERR_LIMIT_MASK (0x3 << WD_ERR_LIMIT_SHIFT)
+# define WD_ERR_LIMIT_8 (0x0 << WD_ERR_LIMIT_SHIFT)
+# define WD_ERR_LIMIT_6 (0x1 << WD_ERR_LIMIT_SHIFT)
+# define WD_ERR_LIMIT_4 (0x2 << WD_ERR_LIMIT_SHIFT)
+# define WD_ERR_LIMIT_2 (0x3 << WD_ERR_LIMIT_SHIFT)
+
+#define WD_RFR_LIMIT_SHIFT (11) /* Watchdog refresh counter limit */
+#define WD_RFR_LIMIT_MASK (0x3 << WD_RFR_LIMIT_SHIFT)
+# define WD_RFR_LIMIT_6 (0x0 << WD_RFR_LIMIT_SHIFT)
+# define WD_RFR_LIMIT_4 (0x1 << WD_RFR_LIMIT_SHIFT)
+# define WD_RFR_LIMIT_2 (0x2 << WD_RFR_LIMIT_SHIFT)
+# define WD_RFR_LIMIT_1 (0x3 << WD_RFR_LIMIT_SHIFT)
+
+#define WD_FS_REACTION_SHIFT (8) /* Reaction on RSTB or FAIL SAFE output in case of BAD Watchdog (data or timing) */
+#define WD_FS_REACTION_MASK (0x3 << WD_FS_REACTION_SHIFT)
+# define WD_FS_REACTION_NO_ACTION (0x0 << WD_FS_REACTION_SHIFT)
+# define WD_FS_REACTION_FS0B (0x1 << WD_FS_REACTION_SHIFT)
+# define WD_FS_REACTION_RSTB_FS0B (0x2 << WD_FS_REACTION_SHIFT)
+
+#define WD_RFR_CNT_SHIFT (8) /* Reflect the value of the Watchdog Refresh Counter */
+#define WD_RFR_CNT_MASK (0x7 << WD_RFR_CNT_SHIFT)
+#define WD_RFR_CNT(n) (n & (0x7 << WD_RFR_CNT_SHIFT))
+
+#define WD_ERR_CNT_SHIFT (0) /* Reflect the value of the Watchdog Error Counter */
+#define WD_ERR_CNT_MASK (0xF << WD_ERR_CNT_SHIFT)
+#define WD_ERR_CNT(n) ((n & (0x7 << WD_RFR_CNT_SHIFT)) > 11) ? (11) : ((n & (0x7 << WD_RFR_CNT_SHIFT)))
Review Comment:
```suggestion
#define WD_ERR_CNT(n) (((n) & (0x7 << WD_RFR_CNT_SHIFT)) > 11) ? 11 : (((n) & (0x7 << WD_RFR_CNT_SHIFT)))
```
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h:
##########
@@ -0,0 +1,505 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* QSPI Register Offsets ****************************************************/
+
+#define S32K3XX_QSPI_MCR_OFFSET (0x0000) /* Module Configuration Register (MCR) */
+#define S32K3XX_QSPI_IPCR_OFFSET (0x0008) /* IP Configuration Register (IPCR) */
+#define S32K3XX_QSPI_FLSHCR_OFFSET (0x000c) /* Flash Memory Configuration Register (FLSHCR) */
+#define S32K3XX_QSPI_BUF0CR_OFFSET (0x0010) /* Buffer 0 Configuration Register (BUF0CR) */
+#define S32K3XX_QSPI_BUF1CR_OFFSET (0x0014) /* Buffer 1 Configuration Register (BUF1CR) */
+#define S32K3XX_QSPI_BUF2CR_OFFSET (0x0018) /* Buffer 2 Configuration Register (BUF2CR) */
+#define S32K3XX_QSPI_BUF3CR_OFFSET (0x001c) /* Buffer 3 Configuration Register (BUF3CR) */
+#define S32K3XX_QSPI_BFGENCR_OFFSET (0x0020) /* Buffer Generic Configuration Register (BFGENCR) */
+#define S32K3XX_QSPI_SOCCR_OFFSET (0x0024) /* SOC Configuration Register (SOCCR) */
+#define S32K3XX_QSPI_BUF0IND_OFFSET (0x0030) /* Buffer 0 Top Index Register (BUF0IND) */
+#define S32K3XX_QSPI_BUF1IND_OFFSET (0x0034) /* Buffer 1 Top Index Register (BUF1IND) */
+#define S32K3XX_QSPI_BUF2IND_OFFSET (0x0038) /* Buffer 2 Top Index Register (BUF2IND) */
+#define S32K3XX_QSPI_DLLCRA_OFFSET (0x0060) /* DLL Flash Memory A Configuration Register (DLLCRA) */
+#define S32K3XX_QSPI_SFAR_OFFSET (0x0100) /* Serial Flash Memory Address Register (SFAR) */
+#define S32K3XX_QSPI_SMPR_OFFSET (0x0108) /* Sampling Register (SMPR) */
+#define S32K3XX_QSPI_RBSR_OFFSET (0x010c) /* RX Buffer Status Register (RBSR) */
+#define S32K3XX_QSPI_RBCT_OFFSET (0x0110) /* RX Buffer Control Register (RBCT) */
+#define S32K3XX_QSPI_DLSR_FA_OFFSET (0x0134) /* Data Learning Status Flash Memory A Register (DLSR_FA) */
+#define S32K3XX_QSPI_TBSR_OFFSET (0x0150) /* TX Buffer Status Register (TBSR) */
+#define S32K3XX_QSPI_TBDR_OFFSET (0x0154) /* TX Buffer Data Register (TBDR) */
+#define S32K3XX_QSPI_TBCT_OFFSET (0x0158) /* TX Buffer Control Register (TBCT) */
+#define S32K3XX_QSPI_SR_OFFSET (0x015c) /* Status Register (SR) */
+#define S32K3XX_QSPI_FR_OFFSET (0x0160) /* Flag Register (FR) */
+#define S32K3XX_QSPI_RSER_OFFSET (0x0164) /* Interrupt and DMA Request Select and Enable Register (RSER) */
+#define S32K3XX_QSPI_SPTRCLR_OFFSET (0x016c) /* Sequence Pointer Clear Register (SPTRCLR) */
+#define S32K3XX_QSPI_SFA1AD_OFFSET (0x0180) /* Serial Flash Memory A1 Top Address Register (SFA1AD) */
+#define S32K3XX_QSPI_SFA2AD_OFFSET (0x0184) /* Serial Flash Memory A2 Top Address Register (SFA2AD) */
+#define S32K3XX_QSPI_SFB1AD_OFFSET (0x0188) /* Serial Flash Memory B1 Top Address Register (SFB1AD) */
+#define S32K3XX_QSPI_SFB2AD_OFFSET (0x018c) /* Serial Flash Memory B2 Top Address Register (SFB2AD) */
+
+#define S32K3XX_QSPI_RBDR_OFFSET(n) (0x0200 + ((n) << 2)) /* RX Buffer Data Register (RBDRn, n=0,...,63) */
+
+#define S32K3XX_QSPI_LUTKEY_OFFSET (0x0300) /* LUT Key Register (LUTKEY) */
+#define S32K3XX_QSPI_LCKCR_OFFSET (0x0304) /* LUT Lock Configuration Register (LKCR) */
+#define S32K3XX_QSPI_LUT0_OFFSET (0x0310) /* LUT Register 0 (LUT0) */
+#define S32K3XX_QSPI_LUT1_OFFSET (0x0314) /* LUT Register 1 (LUT1) */
+#define S32K3XX_QSPI_LUT2_OFFSET (0x0318) /* LUT Register 2 (LUT2) */
+#define S32K3XX_QSPI_LUT3_OFFSET (0x031c) /* LUT Register 3 (LUT3) */
+#define S32K3XX_QSPI_LUT4_OFFSET (0x0320) /* LUT Register 4 (LUT4) */
+#define S32K3XX_QSPI_LUT5_OFFSET (0x0324) /* LUT Register 5 (LUT5) */
+#define S32K3XX_QSPI_LUT6_OFFSET (0x0328) /* LUT Register 6 (LUT6) */
+#define S32K3XX_QSPI_LUT7_OFFSET (0x032c) /* LUT Register 7 (LUT7) */
+#define S32K3XX_QSPI_LUT8_OFFSET (0x0330) /* LUT Register 8 (LUT8) */
+#define S32K3XX_QSPI_LUT9_OFFSET (0x0334) /* LUT Register 9 (LUT9) */
+#define S32K3XX_QSPI_LUT10_OFFSET (0x0338) /* LUT Register 10 (LUT10) */
+#define S32K3XX_QSPI_LUT11_OFFSET (0x033c) /* LUT Register 11 (LUT11) */
+#define S32K3XX_QSPI_LUT12_OFFSET (0x0340) /* LUT Register 12 (LUT12) */
+#define S32K3XX_QSPI_LUT13_OFFSET (0x0344) /* LUT Register 13 (LUT13) */
+#define S32K3XX_QSPI_LUT14_OFFSET (0x0348) /* LUT Register 14 (LUT14) */
+#define S32K3XX_QSPI_LUT15_OFFSET (0x034c) /* LUT Register 15 (LUT15) */
+#define S32K3XX_QSPI_LUT16_OFFSET (0x0350) /* LUT Register 16 (LUT16) */
+#define S32K3XX_QSPI_LUT17_OFFSET (0x0354) /* LUT Register 17 (LUT17) */
+#define S32K3XX_QSPI_LUT18_OFFSET (0x0358) /* LUT Register 18 (LUT18) */
+#define S32K3XX_QSPI_LUT19_OFFSET (0x035c) /* LUT Register 19 (LUT19) */
+
+/* QSPI Register Addresses **************************************************/
+
+#define S32K3XX_QSPI_MCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_MCR_OFFSET)
+#define S32K3XX_QSPI_IPCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_IPCR_OFFSET)
+#define S32K3XX_QSPI_FLSHCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FLSHCR_OFFSET)
+#define S32K3XX_QSPI_BUF0CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0CR_OFFSET)
+#define S32K3XX_QSPI_BUF1CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1CR_OFFSET)
+#define S32K3XX_QSPI_BUF2CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2CR_OFFSET)
+#define S32K3XX_QSPI_BUF3CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF3CR_OFFSET)
+#define S32K3XX_QSPI_BFGENCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BFGENCR_OFFSET)
+#define S32K3XX_QSPI_SOCCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SOCCR_OFFSET)
+#define S32K3XX_QSPI_BUF0IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0IND_OFFSET)
+#define S32K3XX_QSPI_BUF1IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1IND_OFFSET)
+#define S32K3XX_QSPI_BUF2IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2IND_OFFSET)
+#define S32K3XX_QSPI_DLLCRA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLLCRA_OFFSET)
+#define S32K3XX_QSPI_SFAR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFAR_OFFSET)
+#define S32K3XX_QSPI_SMPR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SMPR_OFFSET)
+#define S32K3XX_QSPI_RBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBSR_OFFSET)
+#define S32K3XX_QSPI_RBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBCT_OFFSET)
+#define S32K3XX_QSPI_DLSR_FA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLSR_FA_OFFSET)
+#define S32K3XX_QSPI_TBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBSR_OFFSET)
+#define S32K3XX_QSPI_TBDR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBDR_OFFSET)
+#define S32K3XX_QSPI_TBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBCT_OFFSET)
+#define S32K3XX_QSPI_SR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SR_OFFSET)
+#define S32K3XX_QSPI_FR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FR_OFFSET)
+#define S32K3XX_QSPI_RSER (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RSER_OFFSET)
+#define S32K3XX_QSPI_SPTRCLR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SPTRCLR_OFFSET)
+#define S32K3XX_QSPI_SFA1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA1AD_OFFSET)
+#define S32K3XX_QSPI_SFA2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA2AD_OFFSET)
+#define S32K3XX_QSPI_SFB1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB1AD_OFFSET)
+#define S32K3XX_QSPI_SFB2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB2AD_OFFSET)
+#define S32K3XX_QSPI_RBDR(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBDR_OFFSET(n))
+#define S32K3XX_QSPI_LUTKEY (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUTKEY_OFFSET)
+#define S32K3XX_QSPI_LCKCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LCKCR_OFFSET)
+#define S32K3XX_QSPI_LUT0 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET)
+#define S32K3XX_QSPI_LUT1 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT1_OFFSET)
+#define S32K3XX_QSPI_LUT2 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT2_OFFSET)
+#define S32K3XX_QSPI_LUT3 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT3_OFFSET)
+#define S32K3XX_QSPI_LUT4 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT4_OFFSET)
+#define S32K3XX_QSPI_LUT5 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT5_OFFSET)
+#define S32K3XX_QSPI_LUT6 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT6_OFFSET)
+#define S32K3XX_QSPI_LUT7 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT7_OFFSET)
+#define S32K3XX_QSPI_LUT8 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT8_OFFSET)
+#define S32K3XX_QSPI_LUT9 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT9_OFFSET)
+#define S32K3XX_QSPI_LUT10 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT10_OFFSET)
+#define S32K3XX_QSPI_LUT11 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT11_OFFSET)
+#define S32K3XX_QSPI_LUT12 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT12_OFFSET)
+#define S32K3XX_QSPI_LUT13 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT13_OFFSET)
+#define S32K3XX_QSPI_LUT14 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT14_OFFSET)
+#define S32K3XX_QSPI_LUT15 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT15_OFFSET)
+#define S32K3XX_QSPI_LUT16 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT16_OFFSET)
+#define S32K3XX_QSPI_LUT17 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT17_OFFSET)
+#define S32K3XX_QSPI_LUT18 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT18_OFFSET)
+#define S32K3XX_QSPI_LUT19 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT19_OFFSET)
+
+#define S32K3XX_QSPI_LUT(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET + (n*4))
+#define S32K3XX_QSPI_LUT_COUNT 20
+
+/* QSPI Register Bitfield Definitions ***************************************/
+
+/* Module Configuration Register (MCR) */
+
+#define QSPI_MCR_SWRSTSD (1 << 0) /* Bit 0: Software reset for serial flash memory domain (SWRSTSD) */
+#define QSPI_MCR_SWRSTHD (1 << 1) /* Bit 1: Software reset fo AHB domain (SWRSTHD) */
+ /* Bits 2-9: Reserved */
+#define QSPI_MCR_CLR_RXF (1 << 10) /* Bit 10: Clear RX FIFO (CLR_RXF) */
+#define QSPI_MCR_CLR_TXF (1 << 11) /* Bit 11: Clear TX FIFO/buffer (CLR_TXF) */
+ /* Bits 12-13: Reserved */
+#define QSPI_MCR_MDIS (1 << 14) /* Bit 14: Module disable (MDIS) */
+ /* Bits 15-23: Reserved */
+#define QSPI_MCR_DQS_FA_SEL_SHIFT (24) /* Bits 24-25: DQS clock for sampling read data at flash memory A (DQS_FA_SEL) */
+#define QSPI_MCR_DQS_FA_SEL_MASK (0x03 << QSPI_MCR_DQS_FA_SEL_SHIFT)
+#define QSPI_MCR_DQS_FA_SEL_INTERNAL_DQS ((0x00 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+#define QSPI_MCR_DQS_FA_SEL_LOOPBACK ((0x01 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+#define QSPI_MCR_DQS_FA_SEL_LOOPBACK_DQS ((0x02 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+ /* Bits 26-31: Reserved */
+
+/* IP Configuration Register (IPCR) */
+
+#define QSPICR_IDATSZ_SHIFT (0) /* Bits 0-15: IP data transfer size (IDATSZ) */
+#define QSPICR_IDATSZ_MASK (0xffff << QSPICR_IDATSZ_SHIFT)
+#define QSPICR_IDATSZ(n) ((n << QSPICR_IDATSZ_SHIFT) & QSPICR_IDATSZ_MASK)
+ /* Bits 16-23: Reserved */
+#define QSPICR_SEQID_SHIFT (24) /* Bits 24-27: Points to a sequence in the LUT (SEQID) */
+#define QSPICR_SEQID_MASK (0x0f << QSPICR_SEQID_SHIFT)
+#define QSPICR_SEQID(n) ((n << QSPICR_SEQID_SHIFT) & QSPICR_SEQID_MASK)
+ /* Bits 28-31: Reserved */
+
+/* Flash Memory Configuration Register (FLSHCR) */
+
+#define QSPI_FLSHCR_TCSS_SHIFT (0) /* Bits 0-3: Serial flash memory CS setup time (TCSS) */
+#define QSPI_FLSHCR_TCSS_MASK (0x0f << QSPI_FLSHCR_TCSS_SHIFT)
+#define QSPI_FLSHCR_TCSS(n) (n & QSPI_FLSHCR_TCSS_MASK)
+#define QSPI_FLSHCR_TCSH_SHIFT (8) /* Bits 8-11: Serial flash memory CS hold time (TCSH) */
+#define QSPI_FLSHCR_TCSH_MASK (0x0f << QSPI_FLSHCR_TCSH_SHIFT)
+#define QSPI_FLSHCR_TCSH(n) ((n << QSPI_FLSHCR_TCSH_SHIFT) & QSPI_FLSHCR_TCSH_MASK)
+ /* Bits 12-31: Reserved */
+
+/* Buffer n Configuration Register (BUFnCR) */
+
+#define QSPI_BUFCR_MSTRID_SHIFT (0) /* Bits 0-3: Master ID (MSTRID) */
+#define QSPI_BUFCR_MSTRID_MASK (0x0f << QSPI_BUFCR_MSTRID_SHIFT)
+#define QSPI_BUFCR_MSTRID(n) ((n << QSPI_BUFCR_MSTRID_SHIFT) & QSPI_BUFCR_MSTRID_MASK)
+ /* Bits 4-7: Reserved */
+#define QSPI_BUFCR_ADATSZ_SHIFT (8) /* Bits 8-13: AHB data transfer size (ADATSZ) */
+#define QSPI_BUFCR_ADATSZ_MASK (0x3f << QSPI_BUFCR_ADATSZ_SHIFT)
+#define QSPI_BUFCR_ADATSZ(n) ((n << QSPI_BUFCR_ADATSZ_SHIFT) & QSPI_BUFCR_ADATSZ_MASK)
+ /* Bits 14-31: Reserved */
+#define QSPI_BUF3CR_ALLMST (1 << 31) /* Bit 31: All master enable (ALLMST) */
+
+/* Buffer Generic Configuration Register (BFGENCR) */
+
+ /* Bits 0-11: Reserved */
+#define QSPI_BFGENCR_SEQID_SHIFT (12) /* Bits 12-15: Points to a sequence in the LUT (SEQID) */
+#define QSPI_BFGENCR_SEQID_MASK (0x0f << QSPI_BFGENCR_SEQID_SHIFT)
+ /* Bits 16-31: Reserved */
+
+/* SOC Configuration Register (SOCCR) */
+
+#define QSPI_SOCCR_SOCCFG_SHIFT (0) /* Bits 0-31: SOC configuration (SOCCFG) */
+#define QSPI_SOCCR_SOCCFG_MASK (0xffffffff << QSPI_SOCCR_SOCCFG_SHIFT)
+#define QSPI_SOCCR_OBE_PULL_TMG_RLX (1 << 0) /* Bit 0: obe_pull_timing_relax_b*/
+#define QSPI_SOCCR_IBE (1 << 1) /* Bit 1: IBE */
+#define QSPI_SOCCR_OBE (1 << 2) /* Bit 2: OBE */
+#define QSPI_SOCCR_DSE (1 << 3) /* Bit 3: DSE */
+#define QSPI_SOCCR_PUE (1 << 4) /* Bit 4: PUE */
+#define QSPI_SOCCR_PUS (1 << 5) /* Bit 5: PUS */
+#define QSPI_SOCCR_SRE (1 << 6) /* Bit 6: SRE */
+
+/* Buffer n Top Index Register (BUFnIND) */
+
+ /* Bits 0-2: Reserved */
+#define QSPI_BUFIND_TPINDX_SHIFT (3) /* Bits 3-8: Top index of buffer n (TPINDXn) */
+#define QSPI_BUFIND_TPINDX_MASK (0x3f << QSPI_BUFIND_TPINDX_SHIFT)
+ /* Bits 9-31: Reserved */
+
+/* DLL Flash Memory A Configuration Register (DLLCRA) */
+
+#define QSPI_DLLCRA_SLV_UPD (1 << 0) /* Bit 0: Slave update (SLV_UPD) */
+#define QSPI_DLLCRA_SLV_DLL_BYPASS (1 << 1) /* Bit 1: Slave DLL bypass (SLV_DLL_BYPASS) */
+#define QSPI_DLLCRA_SLV_EN (1 << 2) /* Bit 2: Slave enable (SLV_EN) */
+ /* Bits 3-7: Reserved */
+
+#define QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT (8) /* Bits 8-11: Delay elements in each delay tap (SLV_DLY_COARSE) */
+#define QSPI_DLLCRA_SLV_DLY_COARSE_MASK (0x0f << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT)
+#define QSPI_DLLCRA_SLV_DLY_COARSE(n) ((n << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT) & QSPI_DLLCRA_SLV_DLY_COARSE_MASK)
+#define QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT (12) /* Bits 12-14: T/16 offset delay elements in incoming DQS (SLV_DLY_OFFSET) */
+#define QSPI_DLLCRA_SLV_DLY_OFFSET_MASK (0x07 << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT)
+#define QSPI_DLLCRA_SLV_DLY(n) ((n << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT) & QSPI_DLLCRA_SLV_DLY_OFFSET_MASK)
+ /* Bit 15: Reserved */
+#define QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT (16) /* Bits 16-19: Fine offset delay elements in incoming DQS (SLV_FINE_OFFSET) */
+#define QSPI_DLLCRA_SLV_FINE_OFFSET_MASK (0x0f << QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT)
+ /* Bits 20-29: Reserved */
+#define QSPI_DLLCRA_FREQEN (1 << 30) /* Bit 30: Frequency enable (FREQEN) */
+ /* Bit 31: Reserved */
+
+/* Serial Flash Memory Address Register (SFAR) */
+
+#define QSPI_SFAR_SFADR_SHIFT (0) /* Bits 0-31: Serial flash memory address (SFADR) */
+#define QSPI_SFAR_SFADR_MASK (0xffffffff << QSPI_SFAR_SFADR_SHIFT)
+
+/* Sampling Register (SMPR) */
+
+ /* Bits 0-4: Reserved */
+#define QSPI_SMPR_FSPHS (1 << 5) /* Bit 5: Full speed phase selection for SDR instructions (FSPHS) */
+#define QSPI_SMPR_FSDLY (1 << 6) /* Bit 6: Full speed delay section for SDR instructions (FSDLY) */
+ /* Bits 7-23: Reserved */
+#define QSPI_SMPR_DLLFSMPFA_SHIFT (24) /* Bits 24-26: Selects the nth tap provided by slave delay chain for flash memory A (DLLFSMPFA) */
+#define QSPI_SMPR_DLLFSMPFA_MASK (0x07 << QSPI_SMPR_DLLFSMPFA_SHIFT)
+#define QSPI_SMPR_DLLFSMPFA(n) ((n << QSPI_SMPR_DLLFSMPFA_SHIFT) & QSPI_SMPR_DLLFSMPFA_MASK)
+ /* Bits 27-31: Reserved */
+
+/* RX Buffer Status Register (RBSR) */
+
+#define QSPI_RBSR_RDBFL_SHIFT (0) /* Bits 0-7: RX buffer fill level (RDBFL) */
+#define QSPI_RBSR_RDBFL_MASK (0xff << QSPI_RBSR_RDBFL_SHIFT)
+ /* Bits 8-15: Reserved */
+#define QSPI_RBSR_RDCTR_SHIFT (16) /* Bits 16-31: Read counter (RDCTR) */
+#define QSPI_RBSR_RDCTR_MASK (0xffff << QSPI_RBSR_RDCTR_SHIFT)
+
+/* RX Buffer Control Register (RBCT) */
+
+#define QSPI_RBCT_WMRK_SHIFT (0) /* Bits 0-6: RX buffer watermark (WMRK) */
+#define QSPI_RBCT_WMRK_MASK (0x7f << QSPI_RBCT_WMRK_SHIFT)
+#define QSPI_RBCT_WMRK(n) ((n << QSPI_RBCT_WMRK_SHIFT) & QSPI_RBCT_WMRK_MASK)
+ /* Bit 7: Reserved */
+#define QSPI_RBCT_RXBRD (1 << 8) /* Bit 8: RX buffer readout (RXBRD) */
+# define QSPI_RBCT_RXBRD_AHB (0 << 8) /* RX buffer content is read using the AHB bus registers */
+# define QSPI_RBCT_RXBRD_IP (1 << 8) /* RX buffer content is read using the IP bus registers */
+ /* Bits 9-31: Reserved */
+
+/* Data Learning Status Flash Memory A Register (DLSR_FA) */
+
+#define QSPI_DLSR_FA_NEG_EDGE_SHIFT (0) /* Bits 0-7: DLP negative edge match signature for flash memory A (NEG_EDGE) */
+#define QSPI_DLSR_FA_NEG_EDGE_MASK (0xff << QSPI_DLSR_FA_NEG_EDGE_SHIFT)
+#define QSPI_DLSR_FA_POS_EDGE_SHIFT (8) /* Bits 8-15: DLP positive edge match signature for flash memory A (POS_EDGE) */
+#define QSPI_DLSR_FA_POS_EDGE_MASK (0xff << QSPI_DLSR_FA_POS_EDGE_SHIFT)
+ /* Bits 16-30: Reserved */
+#define QSPI_DLSR_FA_DLPFFA (1 << 31) /* Bit 31: Data learning pattern fail (DLPFFA) */
+
+/* TX Buffer Status Register (TBSR) */
+
+#define QSPI_TBSR_TRBLF_SHIFT (0) /* Bits 0-5: TX buffer fill level (TRBFL) */
+#define QSPI_TBSR_TRBLF_MASK (0x3f << QSPI_TBSR_TRBLF_SHIFT)
+ /* Bits 6-15: Reserved */
+#define QSPI_TBSR_TRCTR_SHIFT (16) /* Bits 16-31: Transmit counter (TRCTR) */
+#define QSPI_TBSR_TRCTR_MASK (0xffff << QSPI_TBSR_TRCTR_SHIFT)
+
+/* TX Buffer Data Register (TBDR) */
+
+#define QSPI_TBDR_TXDATA_SHIFT (0) /* Bits 0-31: TX data (TXDATA) */
+#define QSPI_TBDR_TXDATA_MASK (0xffffffff << QSPI_TBDR_TXDATA_SHIFT)
+
+/* TX Buffer Control Register (TBCT) */
+
+#define QSPI_TBCT_WMRK_SHIFT (0) /* Bits 0-4: Watermark for TX buffer (WMRK) */
+#define QSPI_TBCT_WMRK_MASK (0x1f << QSPI_TBCT_WMRK_SHIFT)
+#define QSPI_TBCT_WMRK(n) ((n << QSPI_TBCT_WMRK_SHIFT) & QSPI_TBCT_WMRK_MASK)
+ /* Bits 5-31: Reserved */
+
+/* Status Register (SR) */
+
+#define QSPI_SR_BUSY (1 << 0) /* Bit 0: Module busy (BUSY) */
+#define QSPI_SR_IP_ACC (1 << 1) /* Bit 1: IP access (IP_ACC) */
+#define QSPI_SR_AHB_ACC (1 << 2) /* Bit 2: AHB read access (AHB_ACC) */
+ /* Bits 3-5: Reserved */
+#define QSPI_SR_AHBTRN (1 << 6) /* Bit 6: AHB access transaction pending (AHBTRN) */
+#define QSPI_SR_AHB0NE (1 << 7) /* Bit 7: AHB 0 buffer not empty (AHB0NE) */
+#define QSPI_SR_AHB1NE (1 << 8) /* Bit 8: AHB 1 buffer not empty (AHB1NE) */
+#define QSPI_SR_AHB2NE (1 << 9) /* Bit 9: AHB 2 buffer not empty (AHB2NE) */
+#define QSPI_SR_AHB3NE (1 << 10) /* Bit 10: AHB 3 buffer not empty (AHB3NE) */
+#define QSPI_SR_AHB0FUL (1 << 11) /* Bit 11: AHB 0 buffer full (AHB0FUL) */
+#define QSPI_SR_AHB1FUL (1 << 12) /* Bit 12: AHB 1 buffer full (AHB1FUL) */
+#define QSPI_SR_AHB2FUL (1 << 13) /* Bit 13: AHB 2 buffer full (AHB2FUL) */
+#define QSPI_SR_AHB3FUL (1 << 14) /* Bit 14: AHB 3 buffer full (AHB3FUL) */
+ /* Bit 15: Reserved */
+#define QSPI_SR_RXWE (1 << 16) /* Bit 16: RX buffer watermark exceeded (RXWE) */
+ /* Bits 17-18: Reserved */
+#define QSPI_SR_RXFULL (1 << 19) /* Bit 19: RX buffer full (RXFULL) */
+ /* Bits 20-22: Reserved */
+#define QSPI_SR_RXDMA (1 << 23) /* Bit 23: RX buffer DMA (RXDMA) */
+#define QSPI_SR_TXNE (1 << 24) /* Bit 24: TX buffer not empty (TXNE) */
+#define QSPI_SR_TXWA (1 << 25) /* Bit 25: TX buffer watermark available (TXWA) */
+#define QSPI_SR_TXDMA (1 << 26) /* Bit 26: TX buffer DMA (TXDMA) */
+#define QSPI_SR_TXFUL (1 << 27) /* Bit 27: TX buffer full (TXFULL) */
+ /* Bits 28-31: Reserved */
+
+/* Flag Register (FR) */
+
+#define QSPI_FR_TFF (1 << 0) /* Bit 0: IP command transaction finished flag (TFF) */
+ /* Bits 1-5: Reserved */
+#define QSPI_FR_IPIEF (1 << 6) /* Bit 6: IP command trigger could not be executed error flag (IPIEF) */
+#define QSPI_FR_IPAEF (1 << 7) /* Bit 7: IP command trigger during AHB access error flag (IPAEF) */
+ /* Bits 8-11: Reserved */
+#define QSPI_FR_ABOF (1 << 12) /* Bit 12: AHB buffer overflow flag (ABOF) */
+#define QSPI_FR_AIBSEF (1 << 13) /* Bit 13: AHB illegal burst size error flag (AIBSEF) */
+#define QSPI_FR_AITEF (1 << 14) /* Bit 14: AHB illegal transaction error flag (AITEF) */
+ /* Bit 15: Reserved */
+#define QSPI_FR_RBDF (1 << 16) /* Bit 16: RX buffer drain flag (RBDF) */
+#define QSPI_FR_RBOF (1 << 17) /* Bit 17: RX buffer overflow flag (RBOF) */
+ /* Bits 18-22: Reserved */
+#define QSPI_FR_ILLINE (1 << 23) /* Bit 23: Illegal instruction error flag (ILLINE) */
+ /* Bits 24-25: Reserved */
+#define QSPI_FR_TBUF (1 << 26) /* Bit 26: TX buffer underrun flag (TBUF) */
+#define QSPI_FR_TBFF (1 << 27) /* Bit 27: TX buffer fill flag (TBFF) */
+ /* Bits 28-31: Reserved */
+
+/* Interrupt and DMA Request Select and Enable Register (RSER) */
+
+#define QSPI_RSER_TFIE (1 << 0) /* Bit 0: Transaction finished interrupt enable flag (TFIE) */
+ /* Bits 1-5: Reserved */
+#define QSPI_RSER_IPIEIE (1 << 6) /* Bit 6: IP command trigger during IP access error interrupt enable flag (IPIEIE) */
+#define QSPI_RSER_IPAEIE (1 << 7) /* Bit 7: IP command trigger during AHB read access error interrupt enable flag (IPAEIE) */
+ /* Bits 8-11: Reserved */
+#define QSPI_RSER_ABOIE (1 << 12) /* Bit 12: AHB buffer overflow interrupt enable flag (ABOIE) */
+#define QSPI_RSER_AIBSIE (1 << 13) /* Bit 13: AHB illegal burst size interrupt enable flag (AIBSIE) */
+#define QSPI_RSER_AITIE (1 << 14) /* Bit 14: AHB illegal transaction interrupt enable flag (AITIE) */
+ /* Bit 15: Reserved */
+#define QSPI_RSER_RBDIE (1 << 16) /* Bit 16: RX buffer drain interrupt enable (RBDIE) */
+#define QSPI_RSER_RBOIE (1 << 17) /* Bit 17: RX buffer overflow interrupt enable (RBOIE) */
+ /* Bits 18-20: Reserved */
+#define QSPI_RSER_RBDDE (1 << 21) /* Bit 21: RX buffer drain DMA enable (RBDDE) */
+ /* Bit 22: Reserved */
+#define QSPI_RSER_ILLINIE (1 << 23) /* Bit 23: Illegal instruction error interrupt enable (ILLINIE) */
+ /* Bit 24: Reserved */
+#define QSPI_RSER_TBFDE (1 << 25) /* Bit 25: TX buffer fill DMA enable (TBFDE) */
+#define QSPI_RSER_TBUIE (1 << 26) /* Bit 26: TX buffer underrun interrupt enable flag (TBUIE) */
+#define QSPI_RSER_TBFIE (1 << 27) /* Bit 27: TX buffer fill interrupt enable flag (TBFIE) */
+ /* Bits 28-31: Reserved */
+
+/* Sequence Pointer Clear Register (SPTRCLR) */
+
+#define QSPI_SPTRCLR_BFPTRC (1 << 0) /* Bit 0: Buffer pointer clear (BFPTRC) */
+ /* Bits 1-7: Reserved */
+#define QSPI_SPTRCLR_IPPTRC (1 << 8) /* Bit 8: IP pointer clear (IPPTRC) */
+ /* Bits 9-31: Reserved */
+
+/* Serial Flash Memory An/Bn Top Address Register (SFAnAD/SFBnAD) */
+
+ /* Bits 0-9: Reserved */
+#define QSPI_SFAD_TPAD_SHIFT (10) /* Bits 10-31: Top address for serial flash memory An/Bn (TPADAn/TPADBn) */
+#define QSPI_SFAD_TPAD_MASK (0x3fffff << QSPI_SFAD_TPAD_SHIFT)
+#define QSPI_SFAD_TPAD(n) ((n << QSPI_SFAD_TPAD_SHIFT) & QSPI_SFAD_TPAD_MASK)
+
+/* RX Buffer Data Register (RBDRn, n=0,...,63) */
+
+#define QSPI_RBDR_RXDATA_SHIFT (0) /* Bits 0-31: RX data (RXDATA) */
+#define QSPI_RBDR_RXDATA_MASK (0xffffffff << QSPI_RBDR_RXDATA_SHIFT)
+
+/* LUT Key Register (LUTKEY) */
+
+#define QSPI_LUTKEY_KEY_SHIFT (0) /* Bits 0-31: Key to lock or unlock the LUT (KEY) */
+#define QSPI_LUTKEY_KEY_MASK (0xffffffff << QSPI_LUTKEY_KEY_SHIFT)
+#define QSPI_LUTKEY_KEY (0x5AF05AF0UL)
+
+/* LUT Lock Configuration Register (LKCR) */
+
+#define QSPI_LKCR_LOCK (1 << 0) /* Bit 0: Lock LUT (LOCK) */
+#define QSPI_LKCR_UNLOCK (1 << 1) /* Bit 1: Unlock LUT (UNLOCK) */
+ /* Bits 2-31: Reserved */
+
+/* LUT Register (LUTn) */
+
+#define QSPI_LUT_OPRND0_SHIFT (0) /* Bits 0-7: Operand for INSTR0 (OPRND0) */
+#define QSPI_LUT_OPRND0_MASK (0xff << QSPI_LUT_OPRND0_SHIFT)
+#define QSPI_LUT_OPRND0(n) ((n << QSPI_LUT_OPRND0_SHIFT) & QSPI_LUT_OPRND0_MASK)
+#define QSPI_LUT_PAD0_SHIFT (8) /* Bits 8-9: Pad information for INSTR0 (PAD0) */
+#define QSPI_LUT_PAD0_MASK (0x03 << QSPI_LUT_PAD0_SHIFT)
+# define QSPI_LUT_PAD0_1 (0x00 << QSPI_LUT_PAD0_SHIFT) /* 1 Pad */
+# define QSPI_LUT_PAD0_2 (0x01 << QSPI_LUT_PAD0_SHIFT) /* 2 Pad */
+# define QSPI_LUT_PAD0_4 (0x02 << QSPI_LUT_PAD0_SHIFT) /* 4 Pad */
+
+#define QSPI_LUT_INSTR0_SHIFT (10) /* Bits 10-15: Instruction 0 (INSTR0) */
+#define QSPI_LUT_INSTR0_MASK (0x3f << QSPI_LUT_INSTR0_SHIFT)
+#define QSPI_LUT_INSTR0(n) ((n << QSPI_LUT_INSTR0_SHIFT) & QSPI_LUT_INSTR0_MASK)
+
+#define QSPI_LUT_OPRND1_SHIFT (16) /* Bits 16-23: Operand for INSTR1 (OPRND1) */
+#define QSPI_LUT_OPRND1_MASK (0xff << QSPI_LUT_OPRND1_SHIFT)
+#define QSPI_LUT_OPRND1(n) ((n << QSPI_LUT_OPRND1_SHIFT) & QSPI_LUT_OPRND1_MASK)
+#define QSPI_LUT_PAD1_SHIFT (24) /* Bits 24-25: Pad information for INSTR1 (PAD1) */
+#define QSPI_LUT_PAD1_MASK (0x03 << QSPI_LUT_PAD1_SHIFT)
+# define QSPI_LUT_PAD1_1 (0x00 << QSPI_LUT_PAD1_SHIFT) /* 1 Pad */
+# define QSPI_LUT_PAD1_2 (0x01 << QSPI_LUT_PAD1_SHIFT) /* 2 Pad */
+# define QSPI_LUT_PAD1_4 (0x02 << QSPI_LUT_PAD1_SHIFT) /* 4 Pad */
+
+#define QSPI_LUT_INSTR1_SHIFT (26) /* Bits 26-31: Instruction 1 (INSTR1) */
+#define QSPI_LUT_INSTR1_MASK (0x3f << QSPI_LUT_INSTR1_SHIFT)
+#define QSPI_LUT_INSTR1(n) ((n << QSPI_LUT_INSTR1_SHIFT) & QSPI_LUT_INSTR1_MASK)
+
+/* External Memory Base Address */
+
+#define QSPI_AMBA_BASE 0x68000000
+
+/* flash connection to the QSPI module */
+
+typedef enum
+{
+ QSPI_SIDE_A1 = 0x00u, /* Serial flash connected on side A1 */
+ QSPI_SIDE_A2 = 0x01u, /* Serial flash connected on side A2 */
+ QSPI_SIDE_B1 = 0x02u, /* Serial flash connected on side B1 */
+ QSPI_SIDE_B2 = 0x03u, /* Serial flash connected on side B2 */
+} s32k3xx_qspi_connectiontype;
+
+/* flash operation type */
+
+typedef enum
+{
+ QSPI_OP_TYPE_CMD = 0x00u, /* Simple command */
+ QSPI_OP_TYPE_WRITE_REG = 0x01u, /* Write value in external flash register */
+ QSPI_OP_TYPE_RMW_REG = 0x02u, /* RMW command on external flash register */
+ QSPI_OP_TYPE_READ_REG = 0x03u, /* Read external flash register until expected value is read */
+ QSPI_OP_TYPE_QSPI_CFG = 0x04u, /* Re-configure QSPI controller */
+} s32k3xx_qspi_optype;
+
+/* Lut commands */
+
+typedef enum
+{
+ QSPI_LUT_INSTR_STOP = (0U << 10U), /* End of sequence */
+ QSPI_LUT_INSTR_CMD = (1U << 10U), /* Command */
+ QSPI_LUT_INSTR_ADDR = (2U << 10U), /* Address */
+ QSPI_LUT_INSTR_DUMMY = (3U << 10U), /* Dummy cycles */
+ QSPI_LUT_INSTR_MODE = (4U << 10U), /* 8-bit mode */
+ QSPI_LUT_INSTR_MODE2 = (5U << 10U), /* 2-bit mode */
+ QSPI_LUT_INSTR_MODE4 = (6U << 10U), /* 4-bit mode */
+ QSPI_LUT_INSTR_READ = (7U << 10U), /* Read data */
+ QSPI_LUT_INSTR_WRITE = (8U << 10U), /* Write data */
+ QSPI_LUT_INSTR_JMP_ON_CS = (9U << 10U), /* Jump on chip select deassert and stop */
+ QSPI_LUT_INSTR_ADDR_DDR = (10U << 10U), /* Address - DDR mode */
+ QSPI_LUT_INSTR_MODE_DDR = (11U << 10U), /* 8-bit mode - DDR mode */
+ QSPI_LUT_INSTR_MODE2_DDR = (12U << 10U), /* 2-bit mode - DDR mode */
+ QSPI_LUT_INSTR_MODE4_DDR = (13U << 10U), /* 4-bit mode - DDR mode */
+ QSPI_LUT_INSTR_READ_DDR = (14U << 10U), /* Read data - DDR mode */
+ QSPI_LUT_INSTR_WRITE_DDR = (15U << 10U), /* Write data - DDR mode */
+ QSPI_LUT_INSTR_DATA_LEARN = (16U << 10U), /* Data learning pattern */
+ QSPI_LUT_INSTR_CMD_DDR = (17U << 10U), /* Command - DDR mode */
+ QSPI_LUT_INSTR_CADDR = (18U << 10U), /* Column address */
+ QSPI_LUT_INSTR_CADDR_DDR = (19U << 10U), /* Column address - DDR mode */
+ QSPI_LUT_INSTR_JMP_TO_SEQ = (20U << 10U), /* Jump on chip select deassert and continue */
+} s32k3xx_qspi_lutcommandstype;
+
+/* Lut pad options */
+
+typedef enum
+{
+ QSPI_LUT_PADS_1 = (0U << 8U), /* 1 Pad */
Review Comment:
2 spaces
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h:
##########
@@ -0,0 +1,499 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* MCU TO FS26 **************************************************************/
+
+#define FS26_M_FS (1 << 31) /* Bit 31: Main or Fail-safe register selection (M/FS) */
+#define FS26_REG_ADDR_SHIFT (25) /* Bits 25-31: Register Address + M/FS */
+#define FS26_REG_ADDR_MASK (0x7F << FS26_REG_ADDR_SHIFT)
+#define FS26_REG_ADDR(n) (((n) << FS26_REG_ADDR_SHIFT) & FS26_REG_ADDR_MASK)
+#define FS26_RW (1 << 24) /* Bit 24: Read/Write (reading Bit 24 = 0) */
+
+/* FS26 General device status ***********************************************/
+
+#define FS26_M_AVAL (1 << 31) /* Bit 31: Main State machine availability (M_AVAL) */
+#define FS26_FS_EN (1 << 30) /* Bit 30: Fail Safe State machine status (FS_EN) */
+#define FS26_FS_G (1 << 29) /* Bit 29: Interrupt notification from the Fail-Safe domain (FS_G) */
+#define FS26_COM_G (1 << 28) /* Bit 28: Interrupt notification from the M_COM_FLG register (COM_G) */
+#define FS26_WIO_G (1 << 27) /* Bit 27: Interrupt notification from the M_WIO_FLG register (WIO_G) */
+#define FS26_VSUP_G (1 << 26) /* Bit 26: Interrupt notification from the M_VSUP_FLG register (VSUP_G) */
+#define FS26_REG_G (1 << 25) /* Bit 25: Interrupt notification from the M_REG_FLG register (REG_G) */
+#define FS26_TSD_G (1 << 24) /* Bit 24: Interrupt notification from the M_TSD_FLG register (TSD_G) */
+
+/* FS26 Data encoding********************************************************/
+
+#define FS26_DATA_LSB_SHIFT (8) /* Bits 8-15: DATA_LSB */
+#define FS26_DATA_LSB_MASK (0xFF << FS26_DATA_LSB_SHIFT)
+#define FS26_DATA_LSB(n) (((n) << FS26_DATA_LSB_SHIFT) & FS26_DATA_LSB_MASK)
+#define FS26_DATA_MSB_SHIFT (16) /* Bits 16-23: DATA_MSB */
+#define FS26_DATA_MSB_MASK (0xFF << FS26_DATA_MSB_SHIFT)
Review Comment:
```suggestion
#define FS26_DATA_MSB_MASK (0xff << FS26_DATA_MSB_SHIFT)
```
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h:
##########
@@ -0,0 +1,499 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* MCU TO FS26 **************************************************************/
+
+#define FS26_M_FS (1 << 31) /* Bit 31: Main or Fail-safe register selection (M/FS) */
+#define FS26_REG_ADDR_SHIFT (25) /* Bits 25-31: Register Address + M/FS */
+#define FS26_REG_ADDR_MASK (0x7F << FS26_REG_ADDR_SHIFT)
+#define FS26_REG_ADDR(n) (((n) << FS26_REG_ADDR_SHIFT) & FS26_REG_ADDR_MASK)
+#define FS26_RW (1 << 24) /* Bit 24: Read/Write (reading Bit 24 = 0) */
+
+/* FS26 General device status ***********************************************/
+
+#define FS26_M_AVAL (1 << 31) /* Bit 31: Main State machine availability (M_AVAL) */
+#define FS26_FS_EN (1 << 30) /* Bit 30: Fail Safe State machine status (FS_EN) */
+#define FS26_FS_G (1 << 29) /* Bit 29: Interrupt notification from the Fail-Safe domain (FS_G) */
+#define FS26_COM_G (1 << 28) /* Bit 28: Interrupt notification from the M_COM_FLG register (COM_G) */
+#define FS26_WIO_G (1 << 27) /* Bit 27: Interrupt notification from the M_WIO_FLG register (WIO_G) */
+#define FS26_VSUP_G (1 << 26) /* Bit 26: Interrupt notification from the M_VSUP_FLG register (VSUP_G) */
+#define FS26_REG_G (1 << 25) /* Bit 25: Interrupt notification from the M_REG_FLG register (REG_G) */
+#define FS26_TSD_G (1 << 24) /* Bit 24: Interrupt notification from the M_TSD_FLG register (TSD_G) */
+
+/* FS26 Data encoding********************************************************/
+
+#define FS26_DATA_LSB_SHIFT (8) /* Bits 8-15: DATA_LSB */
+#define FS26_DATA_LSB_MASK (0xFF << FS26_DATA_LSB_SHIFT)
+#define FS26_DATA_LSB(n) (((n) << FS26_DATA_LSB_SHIFT) & FS26_DATA_LSB_MASK)
+#define FS26_DATA_MSB_SHIFT (16) /* Bits 16-23: DATA_MSB */
+#define FS26_DATA_MSB_MASK (0xFF << FS26_DATA_MSB_SHIFT)
+#define FS26_DATA_MSB(n) (((n) << FS26_DATA_MSB_SHIFT) & FS26_DATA_MSB_MASK)
+#define FS26_DATA_SHIFT (8) /* Bits 8-23: DATA_MSB */
+#define FS26_DATA_MASK (0xFFFF << FS26_DATA_SHIFT)
Review Comment:
```suggestion
#define FS26_DATA_MASK (0xffff << FS26_DATA_SHIFT)
```
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h:
##########
@@ -0,0 +1,499 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* MCU TO FS26 **************************************************************/
+
+#define FS26_M_FS (1 << 31) /* Bit 31: Main or Fail-safe register selection (M/FS) */
+#define FS26_REG_ADDR_SHIFT (25) /* Bits 25-31: Register Address + M/FS */
+#define FS26_REG_ADDR_MASK (0x7F << FS26_REG_ADDR_SHIFT)
+#define FS26_REG_ADDR(n) (((n) << FS26_REG_ADDR_SHIFT) & FS26_REG_ADDR_MASK)
+#define FS26_RW (1 << 24) /* Bit 24: Read/Write (reading Bit 24 = 0) */
+
+/* FS26 General device status ***********************************************/
+
+#define FS26_M_AVAL (1 << 31) /* Bit 31: Main State machine availability (M_AVAL) */
+#define FS26_FS_EN (1 << 30) /* Bit 30: Fail Safe State machine status (FS_EN) */
+#define FS26_FS_G (1 << 29) /* Bit 29: Interrupt notification from the Fail-Safe domain (FS_G) */
+#define FS26_COM_G (1 << 28) /* Bit 28: Interrupt notification from the M_COM_FLG register (COM_G) */
+#define FS26_WIO_G (1 << 27) /* Bit 27: Interrupt notification from the M_WIO_FLG register (WIO_G) */
+#define FS26_VSUP_G (1 << 26) /* Bit 26: Interrupt notification from the M_VSUP_FLG register (VSUP_G) */
+#define FS26_REG_G (1 << 25) /* Bit 25: Interrupt notification from the M_REG_FLG register (REG_G) */
+#define FS26_TSD_G (1 << 24) /* Bit 24: Interrupt notification from the M_TSD_FLG register (TSD_G) */
+
+/* FS26 Data encoding********************************************************/
+
+#define FS26_DATA_LSB_SHIFT (8) /* Bits 8-15: DATA_LSB */
+#define FS26_DATA_LSB_MASK (0xFF << FS26_DATA_LSB_SHIFT)
+#define FS26_DATA_LSB(n) (((n) << FS26_DATA_LSB_SHIFT) & FS26_DATA_LSB_MASK)
+#define FS26_DATA_MSB_SHIFT (16) /* Bits 16-23: DATA_MSB */
+#define FS26_DATA_MSB_MASK (0xFF << FS26_DATA_MSB_SHIFT)
+#define FS26_DATA_MSB(n) (((n) << FS26_DATA_MSB_SHIFT) & FS26_DATA_MSB_MASK)
+#define FS26_DATA_SHIFT (8) /* Bits 8-23: DATA_MSB */
+#define FS26_DATA_MASK (0xFFFF << FS26_DATA_SHIFT)
+#define FS26_SET_DATA(n) (((n) << FS26_DATA_SHIFT) & FS26_DATA_MASK)
+#define FS26_GET_DATA(n) (((n) & FS26_DATA_MASK) >> FS26_DATA_SHIFT)
+#define FS26_CRC_SHIFT (0) /* Bits 0-7: CRC */
+#define FS26_CRC_MASK (0xFF << FS26_CRC_SHIFT)
Review Comment:
```suggestion
#define FS26_CRC_MASK (0xff << FS26_CRC_SHIFT)
```
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h:
##########
@@ -0,0 +1,499 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* MCU TO FS26 **************************************************************/
+
+#define FS26_M_FS (1 << 31) /* Bit 31: Main or Fail-safe register selection (M/FS) */
+#define FS26_REG_ADDR_SHIFT (25) /* Bits 25-31: Register Address + M/FS */
+#define FS26_REG_ADDR_MASK (0x7F << FS26_REG_ADDR_SHIFT)
+#define FS26_REG_ADDR(n) (((n) << FS26_REG_ADDR_SHIFT) & FS26_REG_ADDR_MASK)
+#define FS26_RW (1 << 24) /* Bit 24: Read/Write (reading Bit 24 = 0) */
+
+/* FS26 General device status ***********************************************/
+
+#define FS26_M_AVAL (1 << 31) /* Bit 31: Main State machine availability (M_AVAL) */
+#define FS26_FS_EN (1 << 30) /* Bit 30: Fail Safe State machine status (FS_EN) */
+#define FS26_FS_G (1 << 29) /* Bit 29: Interrupt notification from the Fail-Safe domain (FS_G) */
+#define FS26_COM_G (1 << 28) /* Bit 28: Interrupt notification from the M_COM_FLG register (COM_G) */
+#define FS26_WIO_G (1 << 27) /* Bit 27: Interrupt notification from the M_WIO_FLG register (WIO_G) */
+#define FS26_VSUP_G (1 << 26) /* Bit 26: Interrupt notification from the M_VSUP_FLG register (VSUP_G) */
+#define FS26_REG_G (1 << 25) /* Bit 25: Interrupt notification from the M_REG_FLG register (REG_G) */
+#define FS26_TSD_G (1 << 24) /* Bit 24: Interrupt notification from the M_TSD_FLG register (TSD_G) */
+
+/* FS26 Data encoding********************************************************/
+
+#define FS26_DATA_LSB_SHIFT (8) /* Bits 8-15: DATA_LSB */
+#define FS26_DATA_LSB_MASK (0xFF << FS26_DATA_LSB_SHIFT)
+#define FS26_DATA_LSB(n) (((n) << FS26_DATA_LSB_SHIFT) & FS26_DATA_LSB_MASK)
+#define FS26_DATA_MSB_SHIFT (16) /* Bits 16-23: DATA_MSB */
+#define FS26_DATA_MSB_MASK (0xFF << FS26_DATA_MSB_SHIFT)
+#define FS26_DATA_MSB(n) (((n) << FS26_DATA_MSB_SHIFT) & FS26_DATA_MSB_MASK)
+#define FS26_DATA_SHIFT (8) /* Bits 8-23: DATA_MSB */
+#define FS26_DATA_MASK (0xFFFF << FS26_DATA_SHIFT)
+#define FS26_SET_DATA(n) (((n) << FS26_DATA_SHIFT) & FS26_DATA_MASK)
+#define FS26_GET_DATA(n) (((n) & FS26_DATA_MASK) >> FS26_DATA_SHIFT)
+#define FS26_CRC_SHIFT (0) /* Bits 0-7: CRC */
+#define FS26_CRC_MASK (0xFF << FS26_CRC_SHIFT)
+#define FS26_CRC(n) (((n) << FS26_CRC_SHIFT) & FS26_CRC_MASK)
+
+/* FS26 SPI register map */
+
+#define FS26_M_DEVICE_ID (0x0) /* */
+#define FS26_M_PROGID (0x1) /* */
+#define FS26_M_STATUS (0x2) /* */
+#define FS26_M_TSD_FLG (0x3) /* */
+#define FS26_M_TSD_MSK (0x4) /* */
+#define FS26_M_REG_FLG (0x5) /* */
+#define FS26_M_REG_MSK (0x6) /* */
+#define FS26_M_VSUP_FLG (0x7) /* */
+#define FS26_M_VSUP_MSK (0x8) /* */
+#define FS26_M_WIO_FLG (0x9) /* */
+#define FS26_M_WIO_MSK (0xA) /* */
+#define FS26_M_COM_FLG (0xB) /* */
+#define FS26_M_COM_MSK (0xC) /* */
+#define FS26_M_SYS_CFG (0xD) /* */
+#define FS26_M_TSD_CFG (0xE) /* */
+#define FS26_M_REG_CFG (0xF) /* */
+#define FS26_M_WIO_CFG (0x10) /* */
+#define FS26_M_REG_CTRL1 (0x11) /* */
+#define FS26_M_REG_CTRL2 (0x12) /* */
+#define FS26_M_AMUX_CTRL (0x13) /* */
+#define FS26_M_LDT_CFG1 (0x14) /* */
+#define FS26_M_LDT_CFG2 (0x15) /* */
+#define FS26_M_LDT_CFG3 (0x16) /* */
+#define FS26_M_LDT_CTRL (0x17) /* */
+#define FS26_M_MEMORY0 (0x18) /* */
+#define FS26_M_MEMORY1 (0x19) /* */
+
+/* FS26 Fail safe register map */
+#define FS26_FS_GRL_FLAGS (0x40) /* */
+#define FS26_FS_I_OVUV_SAFE_REACTION1 (0x41) /* */
+#define FS26_FS_I_NOT_OVUV_SAFE_REACTION1 (0x42) /* */
+#define FS26_FS_I_OVUV_SAFE_REACTION2 (0x43) /* */
+#define FS26_FS_I_NOT_OVUV_SAFE_REACTION2 (0x44) /* */
+#define FS26_FS_I_WD_CFG (0x45) /* */
+#define FS26_FS_I_NOT_WD_CFG (0x46) /* */
+#define FS26_FS_I_SAFE_INPUTS (0x47) /* */
+#define FS26_FS_I_NOT_SAFE_INPUTS (0x48) /* */
+#define FS26_FS_I_FSSM (0x49) /* */
+#define FS26_FS_I_NOT_FSSM (0x4A) /* */
+#define FS26_FS_WDW_DURATION (0x4B) /* */
+#define FS26_FS_NOT_WDW_DURATION (0x4C) /* */
+#define FS26_FS_WD_ANSWER (0x4D) /* */
+#define FS26_FS_WD_TOKEN (0x4E) /* */
+#define FS26_FS_ABIST_ON_DEMAND (0x4F) /* */
+#define FS26_FS_OVUV_REG_STATUS (0x50) /* */
+#define FS26_FS_RELEASE_FS0B_FS1B (0x51) /* */
+#define FS26_FS_SAFE_IOS_1 (0x52) /* */
+#define FS26_FS_SAFE_IOS_2 (0x53) /* */
+#define FS26_FS_DIAG_SAFETY1 (0x54) /* */
+#define FS26_FS_DIAG_SAFETY2 (0x55) /* */
+#define FS26_FS_INTB_MASK (0x56) /* */
+#define FS26_FS_STATES (0x57) /* */
+#define FS26_FS_LP_REQ (0x58) /* */
+#define FS26_FS_LDT_LPSEL (0x59) /* */
+
+/* FS_I_OVUV_SAFE_REACTION1 register */
+
+#define VMON_PRE_OV_FS_REACTION_SHIFT (14) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_PRE */
+#define VMON_PRE_OV_FS_REACTION_MASK (0x3 << VMON_PRE_OV_FS_REACTION_SHIFT)
+# define VMON_PRE_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_PRE_OV_FS_REACTION_SHIFT)
+# define VMON_PRE_OV_FS_REACTION_FS0B (0x1 << VMON_PRE_OV_FS_REACTION_SHIFT)
+# define VMON_PRE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_OV_FS_REACTION_SHIFT)
+
+#define VMON_PRE_UV_FS_REACTION_SHIFT (12) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_PRE */
+#define VMON_PRE_UV_FS_REACTION_MASK (0x3 << VMON_PRE_UV_FS_REACTION_SHIFT)
+# define VMON_PRE_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_PRE_UV_FS_REACTION_SHIFT)
+# define VMON_PRE_UV_FS_REACTION_FS0B (0x1 << VMON_PRE_UV_FS_REACTION_SHIFT)
+# define VMON_PRE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_UV_FS_REACTION_SHIFT)
+
+#define VMON_CORE_OV_FS_REACTION_SHIFT (10) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_CORE */
+#define VMON_CORE_OV_FS_REACTION_MASK (0x3 << VMON_CORE_OV_FS_REACTION_SHIFT)
+# define VMON_CORE_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_CORE_OV_FS_REACTION_SHIFT)
+# define VMON_CORE_OV_FS_REACTION_FS0B (0x1 << VMON_CORE_OV_FS_REACTION_SHIFT)
+# define VMON_CORE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_OV_FS_REACTION_SHIFT)
+
+#define VMON_CORE_UV_FS_REACTION_SHIFT (8) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_CORE */
+#define VMON_CORE_UV_FS_REACTION_MASK (0x3 << VMON_CORE_UV_FS_REACTION_SHIFT)
+# define VMON_CORE_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_CORE_UV_FS_REACTION_SHIFT)
+# define VMON_CORE_UV_FS_REACTION_FS0B (0x1 << VMON_CORE_UV_FS_REACTION_SHIFT)
+# define VMON_CORE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_UV_FS_REACTION_SHIFT)
+
+#define VMON_LDO1_OV_FS_REACTION_SHIFT (6) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_LDO1 */
+#define VMON_LDO1_OV_FS_REACTION_MASK (0x3 << VMON_LDO1_OV_FS_REACTION_SHIFT)
+# define VMON_LDO1_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO1_OV_FS_REACTION_SHIFT)
+# define VMON_LDO1_OV_FS_REACTION_FS0B (0x1 << VMON_LDO1_OV_FS_REACTION_SHIFT)
+# define VMON_LDO1_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_OV_FS_REACTION_SHIFT)
+
+#define VMON_LDO1_UV_FS_REACTION_SHIFT (4) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_LDO1 */
+#define VMON_LDO1_UV_FS_REACTION_MASK (0x3 << VMON_LDO1_UV_FS_REACTION_SHIFT)
+# define VMON_LDO1_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO1_UV_FS_REACTION_SHIFT)
+# define VMON_LDO1_UV_FS_REACTION_FS0B (0x1 << VMON_LDO1_UV_FS_REACTION_SHIFT)
+# define VMON_LDO1_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_UV_FS_REACTION_SHIFT)
+
+#define VMON_LDO2_OV_FS_REACTION_SHIFT (2) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_LDO2 */
+#define VMON_LDO2_OV_FS_REACTION_MASK (0x3 << VMON_LDO2_OV_FS_REACTION_SHIFT)
+# define VMON_LDO2_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO2_OV_FS_REACTION_SHIFT)
+# define VMON_LDO2_OV_FS_REACTION_FS0B (0x1 << VMON_LDO2_OV_FS_REACTION_SHIFT)
+# define VMON_LDO2_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO2_OV_FS_REACTION_SHIFT)
+
+#define VMON_LDO2_UV_FS_REACTION_SHIFT (0) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_LDO2 */
+#define VMON_LDO2_UV_FS_REACTION_MASK (0x3 << VMON_LDO2_UV_FS_REACTION_SHIFT)
+# define VMON_LDO2_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO2_UV_FS_REACTION_SHIFT)
+# define VMON_LDO2_UV_FS_REACTION_FS0B (0x1 << VMON_LDO2_UV_FS_REACTION_SHIFT)
+# define VMON_LDO2_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO2_UV_FS_REACTION_SHIFT)
+
+/* FS_I_OVUV_SAFE_REACTION2 register */
+
+#define VMON_EXT_OV_FS_REACTION_SHIFT (14) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_EXT */
+#define VMON_EXT_OV_FS_REACTION_MASK (0x3 << VMON_EXT_OV_FS_REACTION_SHIFT)
+# define VMON_EXT_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_EXT_OV_FS_REACTION_SHIFT)
+# define VMON_EXT_OV_FS_REACTION_FS0B (0x1 << VMON_EXT_OV_FS_REACTION_SHIFT)
+# define VMON_EXT_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_EXT_OV_FS_REACTION_SHIFT)
+
+#define VMON_EXT_UV_FS_REACTION_SHIFT (12) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_EXT */
+#define VMON_EXT_UV_FS_REACTION_MASK (0x3 << VMON_EXT_UV_FS_REACTION_SHIFT)
+# define VMON_EXT_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_EXT_UV_FS_REACTION_SHIFT)
+# define VMON_EXT_UV_FS_REACTION_FS0B (0x1 << VMON_EXT_UV_FS_REACTION_SHIFT)
+# define VMON_EXT_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_EXT_UV_FS_REACTION_SHIFT)
+
+#define VMON_REF_OV_FS_REACTION_SHIFT (10) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_REF */
+#define VMON_REF_OV_FS_REACTION_MASK (0x3 << VMON_REF_OV_FS_REACTION_SHIFT)
+# define VMON_REF_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_REF_OV_FS_REACTION_SHIFT)
+# define VMON_REF_OV_FS_REACTION_FS0B (0x1 << VMON_REF_OV_FS_REACTION_SHIFT)
+# define VMON_REF_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_REF_OV_FS_REACTION_SHIFT)
+
+#define VMON_REF_UV_FS_REACTION_SHIFT (8) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_REF */
+#define VMON_REF_UV_FS_REACTION_MASK (0x3 << VMON_REF_UV_FS_REACTION_SHIFT)
+# define VMON_REF_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_REF_UV_FS_REACTION_SHIFT)
+# define VMON_REF_UV_FS_REACTION_FS0B (0x1 << VMON_REF_UV_FS_REACTION_SHIFT)
+# define VMON_REF_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_REF_UV_FS_REACTION_SHIFT)
+
+#define VMON_TRK2_OV_FS_REACTION_SHIFT (6) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_TRK2 */
+#define VMON_TRK2_OV_FS_REACTION_MASK (0x3 << VMON_TRK2_OV_FS_REACTION_SHIFT)
+# define VMON_TRK2_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK2_OV_FS_REACTION_SHIFT)
+# define VMON_TRK2_OV_FS_REACTION_FS0B (0x1 << VMON_TRK2_OV_FS_REACTION_SHIFT)
+# define VMON_TRK2_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK2_OV_FS_REACTION_SHIFT)
+
+#define VMON_TRK2_UV_FS_REACTION_SHIFT (4) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_TRK2 */
+#define VMON_TRK2_UV_FS_REACTION_MASK (0x3 << VMON_TRK2_UV_FS_REACTION_SHIFT)
+# define VMON_TRK2_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK2_UV_FS_REACTION_SHIFT)
+# define VMON_TRK2_UV_FS_REACTION_FS0B (0x1 << VMON_TRK2_UV_FS_REACTION_SHIFT)
+# define VMON_TRK2_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK2_UV_FS_REACTION_SHIFT)
+
+#define VMON_TRK1_OV_FS_REACTION_SHIFT (2) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_TRK1 */
+#define VMON_TRK1_OV_FS_REACTION_MASK (0x3 << VMON_TRK1_OV_FS_REACTION_SHIFT)
+# define VMON_TRK1_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK1_OV_FS_REACTION_SHIFT)
+# define VMON_TRK1_OV_FS_REACTION_FS0B (0x1 << VMON_TRK1_OV_FS_REACTION_SHIFT)
+# define VMON_TRK1_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK1_OV_FS_REACTION_SHIFT)
+
+#define VMON_TRK1_UV_FS_REACTION_SHIFT (0) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_TRK1 */
+#define VMON_TRK1_UV_FS_REACTION_MASK (0x3 << VMON_TRK1_UV_FS_REACTION_SHIFT)
+# define VMON_TRK1_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK1_UV_FS_REACTION_SHIFT)
+# define VMON_TRK1_UV_FS_REACTION_FS0B (0x1 << VMON_TRK1_UV_FS_REACTION_SHIFT)
+# define VMON_TRK1_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK1_UV_FS_REACTION_SHIFT)
+
+/* FS26_FS_I_WD_CFG register */
+
+#define WD_ERR_LIMIT_SHIFT (14) /* Watchdog error counter limit */
+#define WD_ERR_LIMIT_MASK (0x3 << WD_ERR_LIMIT_SHIFT)
+# define WD_ERR_LIMIT_8 (0x0 << WD_ERR_LIMIT_SHIFT)
+# define WD_ERR_LIMIT_6 (0x1 << WD_ERR_LIMIT_SHIFT)
+# define WD_ERR_LIMIT_4 (0x2 << WD_ERR_LIMIT_SHIFT)
+# define WD_ERR_LIMIT_2 (0x3 << WD_ERR_LIMIT_SHIFT)
+
+#define WD_RFR_LIMIT_SHIFT (11) /* Watchdog refresh counter limit */
+#define WD_RFR_LIMIT_MASK (0x3 << WD_RFR_LIMIT_SHIFT)
+# define WD_RFR_LIMIT_6 (0x0 << WD_RFR_LIMIT_SHIFT)
+# define WD_RFR_LIMIT_4 (0x1 << WD_RFR_LIMIT_SHIFT)
+# define WD_RFR_LIMIT_2 (0x2 << WD_RFR_LIMIT_SHIFT)
+# define WD_RFR_LIMIT_1 (0x3 << WD_RFR_LIMIT_SHIFT)
+
+#define WD_FS_REACTION_SHIFT (8) /* Reaction on RSTB or FAIL SAFE output in case of BAD Watchdog (data or timing) */
+#define WD_FS_REACTION_MASK (0x3 << WD_FS_REACTION_SHIFT)
+# define WD_FS_REACTION_NO_ACTION (0x0 << WD_FS_REACTION_SHIFT)
+# define WD_FS_REACTION_FS0B (0x1 << WD_FS_REACTION_SHIFT)
+# define WD_FS_REACTION_RSTB_FS0B (0x2 << WD_FS_REACTION_SHIFT)
+
+#define WD_RFR_CNT_SHIFT (8) /* Reflect the value of the Watchdog Refresh Counter */
+#define WD_RFR_CNT_MASK (0x7 << WD_RFR_CNT_SHIFT)
+#define WD_RFR_CNT(n) (n & (0x7 << WD_RFR_CNT_SHIFT))
Review Comment:
```suggestion
#define WD_RFR_CNT(n) ((n) & (0x7 << WD_RFR_CNT_SHIFT))
```
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h:
##########
@@ -0,0 +1,505 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* QSPI Register Offsets ****************************************************/
+
+#define S32K3XX_QSPI_MCR_OFFSET (0x0000) /* Module Configuration Register (MCR) */
+#define S32K3XX_QSPI_IPCR_OFFSET (0x0008) /* IP Configuration Register (IPCR) */
+#define S32K3XX_QSPI_FLSHCR_OFFSET (0x000c) /* Flash Memory Configuration Register (FLSHCR) */
+#define S32K3XX_QSPI_BUF0CR_OFFSET (0x0010) /* Buffer 0 Configuration Register (BUF0CR) */
+#define S32K3XX_QSPI_BUF1CR_OFFSET (0x0014) /* Buffer 1 Configuration Register (BUF1CR) */
+#define S32K3XX_QSPI_BUF2CR_OFFSET (0x0018) /* Buffer 2 Configuration Register (BUF2CR) */
+#define S32K3XX_QSPI_BUF3CR_OFFSET (0x001c) /* Buffer 3 Configuration Register (BUF3CR) */
+#define S32K3XX_QSPI_BFGENCR_OFFSET (0x0020) /* Buffer Generic Configuration Register (BFGENCR) */
+#define S32K3XX_QSPI_SOCCR_OFFSET (0x0024) /* SOC Configuration Register (SOCCR) */
+#define S32K3XX_QSPI_BUF0IND_OFFSET (0x0030) /* Buffer 0 Top Index Register (BUF0IND) */
+#define S32K3XX_QSPI_BUF1IND_OFFSET (0x0034) /* Buffer 1 Top Index Register (BUF1IND) */
+#define S32K3XX_QSPI_BUF2IND_OFFSET (0x0038) /* Buffer 2 Top Index Register (BUF2IND) */
+#define S32K3XX_QSPI_DLLCRA_OFFSET (0x0060) /* DLL Flash Memory A Configuration Register (DLLCRA) */
+#define S32K3XX_QSPI_SFAR_OFFSET (0x0100) /* Serial Flash Memory Address Register (SFAR) */
+#define S32K3XX_QSPI_SMPR_OFFSET (0x0108) /* Sampling Register (SMPR) */
+#define S32K3XX_QSPI_RBSR_OFFSET (0x010c) /* RX Buffer Status Register (RBSR) */
+#define S32K3XX_QSPI_RBCT_OFFSET (0x0110) /* RX Buffer Control Register (RBCT) */
+#define S32K3XX_QSPI_DLSR_FA_OFFSET (0x0134) /* Data Learning Status Flash Memory A Register (DLSR_FA) */
+#define S32K3XX_QSPI_TBSR_OFFSET (0x0150) /* TX Buffer Status Register (TBSR) */
+#define S32K3XX_QSPI_TBDR_OFFSET (0x0154) /* TX Buffer Data Register (TBDR) */
+#define S32K3XX_QSPI_TBCT_OFFSET (0x0158) /* TX Buffer Control Register (TBCT) */
+#define S32K3XX_QSPI_SR_OFFSET (0x015c) /* Status Register (SR) */
+#define S32K3XX_QSPI_FR_OFFSET (0x0160) /* Flag Register (FR) */
+#define S32K3XX_QSPI_RSER_OFFSET (0x0164) /* Interrupt and DMA Request Select and Enable Register (RSER) */
+#define S32K3XX_QSPI_SPTRCLR_OFFSET (0x016c) /* Sequence Pointer Clear Register (SPTRCLR) */
+#define S32K3XX_QSPI_SFA1AD_OFFSET (0x0180) /* Serial Flash Memory A1 Top Address Register (SFA1AD) */
+#define S32K3XX_QSPI_SFA2AD_OFFSET (0x0184) /* Serial Flash Memory A2 Top Address Register (SFA2AD) */
+#define S32K3XX_QSPI_SFB1AD_OFFSET (0x0188) /* Serial Flash Memory B1 Top Address Register (SFB1AD) */
+#define S32K3XX_QSPI_SFB2AD_OFFSET (0x018c) /* Serial Flash Memory B2 Top Address Register (SFB2AD) */
+
+#define S32K3XX_QSPI_RBDR_OFFSET(n) (0x0200 + ((n) << 2)) /* RX Buffer Data Register (RBDRn, n=0,...,63) */
+
+#define S32K3XX_QSPI_LUTKEY_OFFSET (0x0300) /* LUT Key Register (LUTKEY) */
+#define S32K3XX_QSPI_LCKCR_OFFSET (0x0304) /* LUT Lock Configuration Register (LKCR) */
+#define S32K3XX_QSPI_LUT0_OFFSET (0x0310) /* LUT Register 0 (LUT0) */
+#define S32K3XX_QSPI_LUT1_OFFSET (0x0314) /* LUT Register 1 (LUT1) */
+#define S32K3XX_QSPI_LUT2_OFFSET (0x0318) /* LUT Register 2 (LUT2) */
+#define S32K3XX_QSPI_LUT3_OFFSET (0x031c) /* LUT Register 3 (LUT3) */
+#define S32K3XX_QSPI_LUT4_OFFSET (0x0320) /* LUT Register 4 (LUT4) */
+#define S32K3XX_QSPI_LUT5_OFFSET (0x0324) /* LUT Register 5 (LUT5) */
+#define S32K3XX_QSPI_LUT6_OFFSET (0x0328) /* LUT Register 6 (LUT6) */
+#define S32K3XX_QSPI_LUT7_OFFSET (0x032c) /* LUT Register 7 (LUT7) */
+#define S32K3XX_QSPI_LUT8_OFFSET (0x0330) /* LUT Register 8 (LUT8) */
+#define S32K3XX_QSPI_LUT9_OFFSET (0x0334) /* LUT Register 9 (LUT9) */
+#define S32K3XX_QSPI_LUT10_OFFSET (0x0338) /* LUT Register 10 (LUT10) */
+#define S32K3XX_QSPI_LUT11_OFFSET (0x033c) /* LUT Register 11 (LUT11) */
+#define S32K3XX_QSPI_LUT12_OFFSET (0x0340) /* LUT Register 12 (LUT12) */
+#define S32K3XX_QSPI_LUT13_OFFSET (0x0344) /* LUT Register 13 (LUT13) */
+#define S32K3XX_QSPI_LUT14_OFFSET (0x0348) /* LUT Register 14 (LUT14) */
+#define S32K3XX_QSPI_LUT15_OFFSET (0x034c) /* LUT Register 15 (LUT15) */
+#define S32K3XX_QSPI_LUT16_OFFSET (0x0350) /* LUT Register 16 (LUT16) */
+#define S32K3XX_QSPI_LUT17_OFFSET (0x0354) /* LUT Register 17 (LUT17) */
+#define S32K3XX_QSPI_LUT18_OFFSET (0x0358) /* LUT Register 18 (LUT18) */
+#define S32K3XX_QSPI_LUT19_OFFSET (0x035c) /* LUT Register 19 (LUT19) */
+
+/* QSPI Register Addresses **************************************************/
+
+#define S32K3XX_QSPI_MCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_MCR_OFFSET)
+#define S32K3XX_QSPI_IPCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_IPCR_OFFSET)
+#define S32K3XX_QSPI_FLSHCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FLSHCR_OFFSET)
+#define S32K3XX_QSPI_BUF0CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0CR_OFFSET)
+#define S32K3XX_QSPI_BUF1CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1CR_OFFSET)
+#define S32K3XX_QSPI_BUF2CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2CR_OFFSET)
+#define S32K3XX_QSPI_BUF3CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF3CR_OFFSET)
+#define S32K3XX_QSPI_BFGENCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BFGENCR_OFFSET)
+#define S32K3XX_QSPI_SOCCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SOCCR_OFFSET)
+#define S32K3XX_QSPI_BUF0IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0IND_OFFSET)
+#define S32K3XX_QSPI_BUF1IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1IND_OFFSET)
+#define S32K3XX_QSPI_BUF2IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2IND_OFFSET)
+#define S32K3XX_QSPI_DLLCRA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLLCRA_OFFSET)
+#define S32K3XX_QSPI_SFAR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFAR_OFFSET)
+#define S32K3XX_QSPI_SMPR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SMPR_OFFSET)
+#define S32K3XX_QSPI_RBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBSR_OFFSET)
+#define S32K3XX_QSPI_RBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBCT_OFFSET)
+#define S32K3XX_QSPI_DLSR_FA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLSR_FA_OFFSET)
+#define S32K3XX_QSPI_TBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBSR_OFFSET)
+#define S32K3XX_QSPI_TBDR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBDR_OFFSET)
+#define S32K3XX_QSPI_TBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBCT_OFFSET)
+#define S32K3XX_QSPI_SR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SR_OFFSET)
+#define S32K3XX_QSPI_FR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FR_OFFSET)
+#define S32K3XX_QSPI_RSER (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RSER_OFFSET)
+#define S32K3XX_QSPI_SPTRCLR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SPTRCLR_OFFSET)
+#define S32K3XX_QSPI_SFA1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA1AD_OFFSET)
+#define S32K3XX_QSPI_SFA2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA2AD_OFFSET)
+#define S32K3XX_QSPI_SFB1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB1AD_OFFSET)
+#define S32K3XX_QSPI_SFB2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB2AD_OFFSET)
+#define S32K3XX_QSPI_RBDR(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBDR_OFFSET(n))
+#define S32K3XX_QSPI_LUTKEY (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUTKEY_OFFSET)
+#define S32K3XX_QSPI_LCKCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LCKCR_OFFSET)
+#define S32K3XX_QSPI_LUT0 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET)
+#define S32K3XX_QSPI_LUT1 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT1_OFFSET)
+#define S32K3XX_QSPI_LUT2 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT2_OFFSET)
+#define S32K3XX_QSPI_LUT3 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT3_OFFSET)
+#define S32K3XX_QSPI_LUT4 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT4_OFFSET)
+#define S32K3XX_QSPI_LUT5 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT5_OFFSET)
+#define S32K3XX_QSPI_LUT6 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT6_OFFSET)
+#define S32K3XX_QSPI_LUT7 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT7_OFFSET)
+#define S32K3XX_QSPI_LUT8 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT8_OFFSET)
+#define S32K3XX_QSPI_LUT9 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT9_OFFSET)
+#define S32K3XX_QSPI_LUT10 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT10_OFFSET)
+#define S32K3XX_QSPI_LUT11 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT11_OFFSET)
+#define S32K3XX_QSPI_LUT12 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT12_OFFSET)
+#define S32K3XX_QSPI_LUT13 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT13_OFFSET)
+#define S32K3XX_QSPI_LUT14 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT14_OFFSET)
+#define S32K3XX_QSPI_LUT15 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT15_OFFSET)
+#define S32K3XX_QSPI_LUT16 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT16_OFFSET)
+#define S32K3XX_QSPI_LUT17 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT17_OFFSET)
+#define S32K3XX_QSPI_LUT18 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT18_OFFSET)
+#define S32K3XX_QSPI_LUT19 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT19_OFFSET)
+
+#define S32K3XX_QSPI_LUT(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET + (n*4))
+#define S32K3XX_QSPI_LUT_COUNT 20
+
+/* QSPI Register Bitfield Definitions ***************************************/
+
+/* Module Configuration Register (MCR) */
+
+#define QSPI_MCR_SWRSTSD (1 << 0) /* Bit 0: Software reset for serial flash memory domain (SWRSTSD) */
+#define QSPI_MCR_SWRSTHD (1 << 1) /* Bit 1: Software reset fo AHB domain (SWRSTHD) */
+ /* Bits 2-9: Reserved */
+#define QSPI_MCR_CLR_RXF (1 << 10) /* Bit 10: Clear RX FIFO (CLR_RXF) */
+#define QSPI_MCR_CLR_TXF (1 << 11) /* Bit 11: Clear TX FIFO/buffer (CLR_TXF) */
+ /* Bits 12-13: Reserved */
+#define QSPI_MCR_MDIS (1 << 14) /* Bit 14: Module disable (MDIS) */
+ /* Bits 15-23: Reserved */
+#define QSPI_MCR_DQS_FA_SEL_SHIFT (24) /* Bits 24-25: DQS clock for sampling read data at flash memory A (DQS_FA_SEL) */
+#define QSPI_MCR_DQS_FA_SEL_MASK (0x03 << QSPI_MCR_DQS_FA_SEL_SHIFT)
+#define QSPI_MCR_DQS_FA_SEL_INTERNAL_DQS ((0x00 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+#define QSPI_MCR_DQS_FA_SEL_LOOPBACK ((0x01 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+#define QSPI_MCR_DQS_FA_SEL_LOOPBACK_DQS ((0x02 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+ /* Bits 26-31: Reserved */
+
+/* IP Configuration Register (IPCR) */
+
+#define QSPICR_IDATSZ_SHIFT (0) /* Bits 0-15: IP data transfer size (IDATSZ) */
+#define QSPICR_IDATSZ_MASK (0xffff << QSPICR_IDATSZ_SHIFT)
+#define QSPICR_IDATSZ(n) ((n << QSPICR_IDATSZ_SHIFT) & QSPICR_IDATSZ_MASK)
+ /* Bits 16-23: Reserved */
+#define QSPICR_SEQID_SHIFT (24) /* Bits 24-27: Points to a sequence in the LUT (SEQID) */
+#define QSPICR_SEQID_MASK (0x0f << QSPICR_SEQID_SHIFT)
+#define QSPICR_SEQID(n) ((n << QSPICR_SEQID_SHIFT) & QSPICR_SEQID_MASK)
+ /* Bits 28-31: Reserved */
+
+/* Flash Memory Configuration Register (FLSHCR) */
+
+#define QSPI_FLSHCR_TCSS_SHIFT (0) /* Bits 0-3: Serial flash memory CS setup time (TCSS) */
+#define QSPI_FLSHCR_TCSS_MASK (0x0f << QSPI_FLSHCR_TCSS_SHIFT)
+#define QSPI_FLSHCR_TCSS(n) (n & QSPI_FLSHCR_TCSS_MASK)
+#define QSPI_FLSHCR_TCSH_SHIFT (8) /* Bits 8-11: Serial flash memory CS hold time (TCSH) */
+#define QSPI_FLSHCR_TCSH_MASK (0x0f << QSPI_FLSHCR_TCSH_SHIFT)
+#define QSPI_FLSHCR_TCSH(n) ((n << QSPI_FLSHCR_TCSH_SHIFT) & QSPI_FLSHCR_TCSH_MASK)
+ /* Bits 12-31: Reserved */
+
+/* Buffer n Configuration Register (BUFnCR) */
+
+#define QSPI_BUFCR_MSTRID_SHIFT (0) /* Bits 0-3: Master ID (MSTRID) */
+#define QSPI_BUFCR_MSTRID_MASK (0x0f << QSPI_BUFCR_MSTRID_SHIFT)
+#define QSPI_BUFCR_MSTRID(n) ((n << QSPI_BUFCR_MSTRID_SHIFT) & QSPI_BUFCR_MSTRID_MASK)
+ /* Bits 4-7: Reserved */
+#define QSPI_BUFCR_ADATSZ_SHIFT (8) /* Bits 8-13: AHB data transfer size (ADATSZ) */
+#define QSPI_BUFCR_ADATSZ_MASK (0x3f << QSPI_BUFCR_ADATSZ_SHIFT)
+#define QSPI_BUFCR_ADATSZ(n) ((n << QSPI_BUFCR_ADATSZ_SHIFT) & QSPI_BUFCR_ADATSZ_MASK)
+ /* Bits 14-31: Reserved */
+#define QSPI_BUF3CR_ALLMST (1 << 31) /* Bit 31: All master enable (ALLMST) */
+
+/* Buffer Generic Configuration Register (BFGENCR) */
+
+ /* Bits 0-11: Reserved */
+#define QSPI_BFGENCR_SEQID_SHIFT (12) /* Bits 12-15: Points to a sequence in the LUT (SEQID) */
+#define QSPI_BFGENCR_SEQID_MASK (0x0f << QSPI_BFGENCR_SEQID_SHIFT)
+ /* Bits 16-31: Reserved */
+
+/* SOC Configuration Register (SOCCR) */
+
+#define QSPI_SOCCR_SOCCFG_SHIFT (0) /* Bits 0-31: SOC configuration (SOCCFG) */
+#define QSPI_SOCCR_SOCCFG_MASK (0xffffffff << QSPI_SOCCR_SOCCFG_SHIFT)
+#define QSPI_SOCCR_OBE_PULL_TMG_RLX (1 << 0) /* Bit 0: obe_pull_timing_relax_b*/
+#define QSPI_SOCCR_IBE (1 << 1) /* Bit 1: IBE */
+#define QSPI_SOCCR_OBE (1 << 2) /* Bit 2: OBE */
+#define QSPI_SOCCR_DSE (1 << 3) /* Bit 3: DSE */
+#define QSPI_SOCCR_PUE (1 << 4) /* Bit 4: PUE */
+#define QSPI_SOCCR_PUS (1 << 5) /* Bit 5: PUS */
+#define QSPI_SOCCR_SRE (1 << 6) /* Bit 6: SRE */
+
+/* Buffer n Top Index Register (BUFnIND) */
+
+ /* Bits 0-2: Reserved */
+#define QSPI_BUFIND_TPINDX_SHIFT (3) /* Bits 3-8: Top index of buffer n (TPINDXn) */
+#define QSPI_BUFIND_TPINDX_MASK (0x3f << QSPI_BUFIND_TPINDX_SHIFT)
+ /* Bits 9-31: Reserved */
+
+/* DLL Flash Memory A Configuration Register (DLLCRA) */
+
+#define QSPI_DLLCRA_SLV_UPD (1 << 0) /* Bit 0: Slave update (SLV_UPD) */
+#define QSPI_DLLCRA_SLV_DLL_BYPASS (1 << 1) /* Bit 1: Slave DLL bypass (SLV_DLL_BYPASS) */
+#define QSPI_DLLCRA_SLV_EN (1 << 2) /* Bit 2: Slave enable (SLV_EN) */
+ /* Bits 3-7: Reserved */
+
+#define QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT (8) /* Bits 8-11: Delay elements in each delay tap (SLV_DLY_COARSE) */
+#define QSPI_DLLCRA_SLV_DLY_COARSE_MASK (0x0f << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT)
+#define QSPI_DLLCRA_SLV_DLY_COARSE(n) ((n << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT) & QSPI_DLLCRA_SLV_DLY_COARSE_MASK)
+#define QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT (12) /* Bits 12-14: T/16 offset delay elements in incoming DQS (SLV_DLY_OFFSET) */
+#define QSPI_DLLCRA_SLV_DLY_OFFSET_MASK (0x07 << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT)
+#define QSPI_DLLCRA_SLV_DLY(n) ((n << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT) & QSPI_DLLCRA_SLV_DLY_OFFSET_MASK)
+ /* Bit 15: Reserved */
+#define QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT (16) /* Bits 16-19: Fine offset delay elements in incoming DQS (SLV_FINE_OFFSET) */
+#define QSPI_DLLCRA_SLV_FINE_OFFSET_MASK (0x0f << QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT)
+ /* Bits 20-29: Reserved */
+#define QSPI_DLLCRA_FREQEN (1 << 30) /* Bit 30: Frequency enable (FREQEN) */
+ /* Bit 31: Reserved */
+
+/* Serial Flash Memory Address Register (SFAR) */
+
+#define QSPI_SFAR_SFADR_SHIFT (0) /* Bits 0-31: Serial flash memory address (SFADR) */
+#define QSPI_SFAR_SFADR_MASK (0xffffffff << QSPI_SFAR_SFADR_SHIFT)
+
+/* Sampling Register (SMPR) */
+
+ /* Bits 0-4: Reserved */
+#define QSPI_SMPR_FSPHS (1 << 5) /* Bit 5: Full speed phase selection for SDR instructions (FSPHS) */
+#define QSPI_SMPR_FSDLY (1 << 6) /* Bit 6: Full speed delay section for SDR instructions (FSDLY) */
+ /* Bits 7-23: Reserved */
+#define QSPI_SMPR_DLLFSMPFA_SHIFT (24) /* Bits 24-26: Selects the nth tap provided by slave delay chain for flash memory A (DLLFSMPFA) */
+#define QSPI_SMPR_DLLFSMPFA_MASK (0x07 << QSPI_SMPR_DLLFSMPFA_SHIFT)
+#define QSPI_SMPR_DLLFSMPFA(n) ((n << QSPI_SMPR_DLLFSMPFA_SHIFT) & QSPI_SMPR_DLLFSMPFA_MASK)
+ /* Bits 27-31: Reserved */
+
+/* RX Buffer Status Register (RBSR) */
+
+#define QSPI_RBSR_RDBFL_SHIFT (0) /* Bits 0-7: RX buffer fill level (RDBFL) */
+#define QSPI_RBSR_RDBFL_MASK (0xff << QSPI_RBSR_RDBFL_SHIFT)
+ /* Bits 8-15: Reserved */
+#define QSPI_RBSR_RDCTR_SHIFT (16) /* Bits 16-31: Read counter (RDCTR) */
+#define QSPI_RBSR_RDCTR_MASK (0xffff << QSPI_RBSR_RDCTR_SHIFT)
+
+/* RX Buffer Control Register (RBCT) */
+
+#define QSPI_RBCT_WMRK_SHIFT (0) /* Bits 0-6: RX buffer watermark (WMRK) */
+#define QSPI_RBCT_WMRK_MASK (0x7f << QSPI_RBCT_WMRK_SHIFT)
+#define QSPI_RBCT_WMRK(n) ((n << QSPI_RBCT_WMRK_SHIFT) & QSPI_RBCT_WMRK_MASK)
+ /* Bit 7: Reserved */
+#define QSPI_RBCT_RXBRD (1 << 8) /* Bit 8: RX buffer readout (RXBRD) */
+# define QSPI_RBCT_RXBRD_AHB (0 << 8) /* RX buffer content is read using the AHB bus registers */
+# define QSPI_RBCT_RXBRD_IP (1 << 8) /* RX buffer content is read using the IP bus registers */
+ /* Bits 9-31: Reserved */
+
+/* Data Learning Status Flash Memory A Register (DLSR_FA) */
+
+#define QSPI_DLSR_FA_NEG_EDGE_SHIFT (0) /* Bits 0-7: DLP negative edge match signature for flash memory A (NEG_EDGE) */
+#define QSPI_DLSR_FA_NEG_EDGE_MASK (0xff << QSPI_DLSR_FA_NEG_EDGE_SHIFT)
+#define QSPI_DLSR_FA_POS_EDGE_SHIFT (8) /* Bits 8-15: DLP positive edge match signature for flash memory A (POS_EDGE) */
+#define QSPI_DLSR_FA_POS_EDGE_MASK (0xff << QSPI_DLSR_FA_POS_EDGE_SHIFT)
+ /* Bits 16-30: Reserved */
+#define QSPI_DLSR_FA_DLPFFA (1 << 31) /* Bit 31: Data learning pattern fail (DLPFFA) */
+
+/* TX Buffer Status Register (TBSR) */
+
+#define QSPI_TBSR_TRBLF_SHIFT (0) /* Bits 0-5: TX buffer fill level (TRBFL) */
+#define QSPI_TBSR_TRBLF_MASK (0x3f << QSPI_TBSR_TRBLF_SHIFT)
+ /* Bits 6-15: Reserved */
+#define QSPI_TBSR_TRCTR_SHIFT (16) /* Bits 16-31: Transmit counter (TRCTR) */
+#define QSPI_TBSR_TRCTR_MASK (0xffff << QSPI_TBSR_TRCTR_SHIFT)
+
+/* TX Buffer Data Register (TBDR) */
+
+#define QSPI_TBDR_TXDATA_SHIFT (0) /* Bits 0-31: TX data (TXDATA) */
+#define QSPI_TBDR_TXDATA_MASK (0xffffffff << QSPI_TBDR_TXDATA_SHIFT)
+
+/* TX Buffer Control Register (TBCT) */
+
+#define QSPI_TBCT_WMRK_SHIFT (0) /* Bits 0-4: Watermark for TX buffer (WMRK) */
+#define QSPI_TBCT_WMRK_MASK (0x1f << QSPI_TBCT_WMRK_SHIFT)
+#define QSPI_TBCT_WMRK(n) ((n << QSPI_TBCT_WMRK_SHIFT) & QSPI_TBCT_WMRK_MASK)
+ /* Bits 5-31: Reserved */
+
+/* Status Register (SR) */
+
+#define QSPI_SR_BUSY (1 << 0) /* Bit 0: Module busy (BUSY) */
+#define QSPI_SR_IP_ACC (1 << 1) /* Bit 1: IP access (IP_ACC) */
+#define QSPI_SR_AHB_ACC (1 << 2) /* Bit 2: AHB read access (AHB_ACC) */
+ /* Bits 3-5: Reserved */
+#define QSPI_SR_AHBTRN (1 << 6) /* Bit 6: AHB access transaction pending (AHBTRN) */
+#define QSPI_SR_AHB0NE (1 << 7) /* Bit 7: AHB 0 buffer not empty (AHB0NE) */
+#define QSPI_SR_AHB1NE (1 << 8) /* Bit 8: AHB 1 buffer not empty (AHB1NE) */
+#define QSPI_SR_AHB2NE (1 << 9) /* Bit 9: AHB 2 buffer not empty (AHB2NE) */
+#define QSPI_SR_AHB3NE (1 << 10) /* Bit 10: AHB 3 buffer not empty (AHB3NE) */
+#define QSPI_SR_AHB0FUL (1 << 11) /* Bit 11: AHB 0 buffer full (AHB0FUL) */
+#define QSPI_SR_AHB1FUL (1 << 12) /* Bit 12: AHB 1 buffer full (AHB1FUL) */
+#define QSPI_SR_AHB2FUL (1 << 13) /* Bit 13: AHB 2 buffer full (AHB2FUL) */
+#define QSPI_SR_AHB3FUL (1 << 14) /* Bit 14: AHB 3 buffer full (AHB3FUL) */
+ /* Bit 15: Reserved */
+#define QSPI_SR_RXWE (1 << 16) /* Bit 16: RX buffer watermark exceeded (RXWE) */
+ /* Bits 17-18: Reserved */
+#define QSPI_SR_RXFULL (1 << 19) /* Bit 19: RX buffer full (RXFULL) */
+ /* Bits 20-22: Reserved */
+#define QSPI_SR_RXDMA (1 << 23) /* Bit 23: RX buffer DMA (RXDMA) */
+#define QSPI_SR_TXNE (1 << 24) /* Bit 24: TX buffer not empty (TXNE) */
+#define QSPI_SR_TXWA (1 << 25) /* Bit 25: TX buffer watermark available (TXWA) */
+#define QSPI_SR_TXDMA (1 << 26) /* Bit 26: TX buffer DMA (TXDMA) */
+#define QSPI_SR_TXFUL (1 << 27) /* Bit 27: TX buffer full (TXFULL) */
+ /* Bits 28-31: Reserved */
+
+/* Flag Register (FR) */
+
+#define QSPI_FR_TFF (1 << 0) /* Bit 0: IP command transaction finished flag (TFF) */
+ /* Bits 1-5: Reserved */
+#define QSPI_FR_IPIEF (1 << 6) /* Bit 6: IP command trigger could not be executed error flag (IPIEF) */
+#define QSPI_FR_IPAEF (1 << 7) /* Bit 7: IP command trigger during AHB access error flag (IPAEF) */
+ /* Bits 8-11: Reserved */
+#define QSPI_FR_ABOF (1 << 12) /* Bit 12: AHB buffer overflow flag (ABOF) */
+#define QSPI_FR_AIBSEF (1 << 13) /* Bit 13: AHB illegal burst size error flag (AIBSEF) */
+#define QSPI_FR_AITEF (1 << 14) /* Bit 14: AHB illegal transaction error flag (AITEF) */
+ /* Bit 15: Reserved */
+#define QSPI_FR_RBDF (1 << 16) /* Bit 16: RX buffer drain flag (RBDF) */
+#define QSPI_FR_RBOF (1 << 17) /* Bit 17: RX buffer overflow flag (RBOF) */
+ /* Bits 18-22: Reserved */
+#define QSPI_FR_ILLINE (1 << 23) /* Bit 23: Illegal instruction error flag (ILLINE) */
+ /* Bits 24-25: Reserved */
+#define QSPI_FR_TBUF (1 << 26) /* Bit 26: TX buffer underrun flag (TBUF) */
+#define QSPI_FR_TBFF (1 << 27) /* Bit 27: TX buffer fill flag (TBFF) */
+ /* Bits 28-31: Reserved */
+
+/* Interrupt and DMA Request Select and Enable Register (RSER) */
+
+#define QSPI_RSER_TFIE (1 << 0) /* Bit 0: Transaction finished interrupt enable flag (TFIE) */
+ /* Bits 1-5: Reserved */
+#define QSPI_RSER_IPIEIE (1 << 6) /* Bit 6: IP command trigger during IP access error interrupt enable flag (IPIEIE) */
+#define QSPI_RSER_IPAEIE (1 << 7) /* Bit 7: IP command trigger during AHB read access error interrupt enable flag (IPAEIE) */
+ /* Bits 8-11: Reserved */
+#define QSPI_RSER_ABOIE (1 << 12) /* Bit 12: AHB buffer overflow interrupt enable flag (ABOIE) */
+#define QSPI_RSER_AIBSIE (1 << 13) /* Bit 13: AHB illegal burst size interrupt enable flag (AIBSIE) */
+#define QSPI_RSER_AITIE (1 << 14) /* Bit 14: AHB illegal transaction interrupt enable flag (AITIE) */
+ /* Bit 15: Reserved */
+#define QSPI_RSER_RBDIE (1 << 16) /* Bit 16: RX buffer drain interrupt enable (RBDIE) */
+#define QSPI_RSER_RBOIE (1 << 17) /* Bit 17: RX buffer overflow interrupt enable (RBOIE) */
+ /* Bits 18-20: Reserved */
+#define QSPI_RSER_RBDDE (1 << 21) /* Bit 21: RX buffer drain DMA enable (RBDDE) */
+ /* Bit 22: Reserved */
+#define QSPI_RSER_ILLINIE (1 << 23) /* Bit 23: Illegal instruction error interrupt enable (ILLINIE) */
+ /* Bit 24: Reserved */
+#define QSPI_RSER_TBFDE (1 << 25) /* Bit 25: TX buffer fill DMA enable (TBFDE) */
+#define QSPI_RSER_TBUIE (1 << 26) /* Bit 26: TX buffer underrun interrupt enable flag (TBUIE) */
+#define QSPI_RSER_TBFIE (1 << 27) /* Bit 27: TX buffer fill interrupt enable flag (TBFIE) */
+ /* Bits 28-31: Reserved */
+
+/* Sequence Pointer Clear Register (SPTRCLR) */
+
+#define QSPI_SPTRCLR_BFPTRC (1 << 0) /* Bit 0: Buffer pointer clear (BFPTRC) */
+ /* Bits 1-7: Reserved */
+#define QSPI_SPTRCLR_IPPTRC (1 << 8) /* Bit 8: IP pointer clear (IPPTRC) */
+ /* Bits 9-31: Reserved */
+
+/* Serial Flash Memory An/Bn Top Address Register (SFAnAD/SFBnAD) */
+
+ /* Bits 0-9: Reserved */
+#define QSPI_SFAD_TPAD_SHIFT (10) /* Bits 10-31: Top address for serial flash memory An/Bn (TPADAn/TPADBn) */
+#define QSPI_SFAD_TPAD_MASK (0x3fffff << QSPI_SFAD_TPAD_SHIFT)
+#define QSPI_SFAD_TPAD(n) ((n << QSPI_SFAD_TPAD_SHIFT) & QSPI_SFAD_TPAD_MASK)
+
+/* RX Buffer Data Register (RBDRn, n=0,...,63) */
+
+#define QSPI_RBDR_RXDATA_SHIFT (0) /* Bits 0-31: RX data (RXDATA) */
+#define QSPI_RBDR_RXDATA_MASK (0xffffffff << QSPI_RBDR_RXDATA_SHIFT)
+
+/* LUT Key Register (LUTKEY) */
+
+#define QSPI_LUTKEY_KEY_SHIFT (0) /* Bits 0-31: Key to lock or unlock the LUT (KEY) */
+#define QSPI_LUTKEY_KEY_MASK (0xffffffff << QSPI_LUTKEY_KEY_SHIFT)
+#define QSPI_LUTKEY_KEY (0x5AF05AF0UL)
+
+/* LUT Lock Configuration Register (LKCR) */
+
+#define QSPI_LKCR_LOCK (1 << 0) /* Bit 0: Lock LUT (LOCK) */
+#define QSPI_LKCR_UNLOCK (1 << 1) /* Bit 1: Unlock LUT (UNLOCK) */
+ /* Bits 2-31: Reserved */
+
+/* LUT Register (LUTn) */
+
+#define QSPI_LUT_OPRND0_SHIFT (0) /* Bits 0-7: Operand for INSTR0 (OPRND0) */
+#define QSPI_LUT_OPRND0_MASK (0xff << QSPI_LUT_OPRND0_SHIFT)
+#define QSPI_LUT_OPRND0(n) ((n << QSPI_LUT_OPRND0_SHIFT) & QSPI_LUT_OPRND0_MASK)
+#define QSPI_LUT_PAD0_SHIFT (8) /* Bits 8-9: Pad information for INSTR0 (PAD0) */
+#define QSPI_LUT_PAD0_MASK (0x03 << QSPI_LUT_PAD0_SHIFT)
+# define QSPI_LUT_PAD0_1 (0x00 << QSPI_LUT_PAD0_SHIFT) /* 1 Pad */
+# define QSPI_LUT_PAD0_2 (0x01 << QSPI_LUT_PAD0_SHIFT) /* 2 Pad */
+# define QSPI_LUT_PAD0_4 (0x02 << QSPI_LUT_PAD0_SHIFT) /* 4 Pad */
+
+#define QSPI_LUT_INSTR0_SHIFT (10) /* Bits 10-15: Instruction 0 (INSTR0) */
+#define QSPI_LUT_INSTR0_MASK (0x3f << QSPI_LUT_INSTR0_SHIFT)
+#define QSPI_LUT_INSTR0(n) ((n << QSPI_LUT_INSTR0_SHIFT) & QSPI_LUT_INSTR0_MASK)
+
+#define QSPI_LUT_OPRND1_SHIFT (16) /* Bits 16-23: Operand for INSTR1 (OPRND1) */
+#define QSPI_LUT_OPRND1_MASK (0xff << QSPI_LUT_OPRND1_SHIFT)
+#define QSPI_LUT_OPRND1(n) ((n << QSPI_LUT_OPRND1_SHIFT) & QSPI_LUT_OPRND1_MASK)
+#define QSPI_LUT_PAD1_SHIFT (24) /* Bits 24-25: Pad information for INSTR1 (PAD1) */
+#define QSPI_LUT_PAD1_MASK (0x03 << QSPI_LUT_PAD1_SHIFT)
+# define QSPI_LUT_PAD1_1 (0x00 << QSPI_LUT_PAD1_SHIFT) /* 1 Pad */
+# define QSPI_LUT_PAD1_2 (0x01 << QSPI_LUT_PAD1_SHIFT) /* 2 Pad */
+# define QSPI_LUT_PAD1_4 (0x02 << QSPI_LUT_PAD1_SHIFT) /* 4 Pad */
+
+#define QSPI_LUT_INSTR1_SHIFT (26) /* Bits 26-31: Instruction 1 (INSTR1) */
+#define QSPI_LUT_INSTR1_MASK (0x3f << QSPI_LUT_INSTR1_SHIFT)
+#define QSPI_LUT_INSTR1(n) ((n << QSPI_LUT_INSTR1_SHIFT) & QSPI_LUT_INSTR1_MASK)
+
+/* External Memory Base Address */
+
+#define QSPI_AMBA_BASE 0x68000000
+
+/* flash connection to the QSPI module */
+
+typedef enum
+{
+ QSPI_SIDE_A1 = 0x00u, /* Serial flash connected on side A1 */
+ QSPI_SIDE_A2 = 0x01u, /* Serial flash connected on side A2 */
+ QSPI_SIDE_B1 = 0x02u, /* Serial flash connected on side B1 */
+ QSPI_SIDE_B2 = 0x03u, /* Serial flash connected on side B2 */
+} s32k3xx_qspi_connectiontype;
+
+/* flash operation type */
+
+typedef enum
+{
+ QSPI_OP_TYPE_CMD = 0x00u, /* Simple command */
Review Comment:
2 spaces
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h:
##########
@@ -0,0 +1,499 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_FS26_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* MCU TO FS26 **************************************************************/
+
+#define FS26_M_FS (1 << 31) /* Bit 31: Main or Fail-safe register selection (M/FS) */
+#define FS26_REG_ADDR_SHIFT (25) /* Bits 25-31: Register Address + M/FS */
+#define FS26_REG_ADDR_MASK (0x7F << FS26_REG_ADDR_SHIFT)
+#define FS26_REG_ADDR(n) (((n) << FS26_REG_ADDR_SHIFT) & FS26_REG_ADDR_MASK)
+#define FS26_RW (1 << 24) /* Bit 24: Read/Write (reading Bit 24 = 0) */
+
+/* FS26 General device status ***********************************************/
+
+#define FS26_M_AVAL (1 << 31) /* Bit 31: Main State machine availability (M_AVAL) */
+#define FS26_FS_EN (1 << 30) /* Bit 30: Fail Safe State machine status (FS_EN) */
+#define FS26_FS_G (1 << 29) /* Bit 29: Interrupt notification from the Fail-Safe domain (FS_G) */
+#define FS26_COM_G (1 << 28) /* Bit 28: Interrupt notification from the M_COM_FLG register (COM_G) */
+#define FS26_WIO_G (1 << 27) /* Bit 27: Interrupt notification from the M_WIO_FLG register (WIO_G) */
+#define FS26_VSUP_G (1 << 26) /* Bit 26: Interrupt notification from the M_VSUP_FLG register (VSUP_G) */
+#define FS26_REG_G (1 << 25) /* Bit 25: Interrupt notification from the M_REG_FLG register (REG_G) */
+#define FS26_TSD_G (1 << 24) /* Bit 24: Interrupt notification from the M_TSD_FLG register (TSD_G) */
+
+/* FS26 Data encoding********************************************************/
+
+#define FS26_DATA_LSB_SHIFT (8) /* Bits 8-15: DATA_LSB */
+#define FS26_DATA_LSB_MASK (0xFF << FS26_DATA_LSB_SHIFT)
+#define FS26_DATA_LSB(n) (((n) << FS26_DATA_LSB_SHIFT) & FS26_DATA_LSB_MASK)
+#define FS26_DATA_MSB_SHIFT (16) /* Bits 16-23: DATA_MSB */
+#define FS26_DATA_MSB_MASK (0xFF << FS26_DATA_MSB_SHIFT)
+#define FS26_DATA_MSB(n) (((n) << FS26_DATA_MSB_SHIFT) & FS26_DATA_MSB_MASK)
+#define FS26_DATA_SHIFT (8) /* Bits 8-23: DATA_MSB */
+#define FS26_DATA_MASK (0xFFFF << FS26_DATA_SHIFT)
+#define FS26_SET_DATA(n) (((n) << FS26_DATA_SHIFT) & FS26_DATA_MASK)
+#define FS26_GET_DATA(n) (((n) & FS26_DATA_MASK) >> FS26_DATA_SHIFT)
+#define FS26_CRC_SHIFT (0) /* Bits 0-7: CRC */
+#define FS26_CRC_MASK (0xFF << FS26_CRC_SHIFT)
+#define FS26_CRC(n) (((n) << FS26_CRC_SHIFT) & FS26_CRC_MASK)
+
+/* FS26 SPI register map */
+
+#define FS26_M_DEVICE_ID (0x0) /* */
+#define FS26_M_PROGID (0x1) /* */
+#define FS26_M_STATUS (0x2) /* */
+#define FS26_M_TSD_FLG (0x3) /* */
+#define FS26_M_TSD_MSK (0x4) /* */
+#define FS26_M_REG_FLG (0x5) /* */
+#define FS26_M_REG_MSK (0x6) /* */
+#define FS26_M_VSUP_FLG (0x7) /* */
+#define FS26_M_VSUP_MSK (0x8) /* */
+#define FS26_M_WIO_FLG (0x9) /* */
+#define FS26_M_WIO_MSK (0xA) /* */
+#define FS26_M_COM_FLG (0xB) /* */
+#define FS26_M_COM_MSK (0xC) /* */
+#define FS26_M_SYS_CFG (0xD) /* */
+#define FS26_M_TSD_CFG (0xE) /* */
+#define FS26_M_REG_CFG (0xF) /* */
+#define FS26_M_WIO_CFG (0x10) /* */
+#define FS26_M_REG_CTRL1 (0x11) /* */
+#define FS26_M_REG_CTRL2 (0x12) /* */
+#define FS26_M_AMUX_CTRL (0x13) /* */
+#define FS26_M_LDT_CFG1 (0x14) /* */
+#define FS26_M_LDT_CFG2 (0x15) /* */
+#define FS26_M_LDT_CFG3 (0x16) /* */
+#define FS26_M_LDT_CTRL (0x17) /* */
+#define FS26_M_MEMORY0 (0x18) /* */
+#define FS26_M_MEMORY1 (0x19) /* */
+
+/* FS26 Fail safe register map */
+#define FS26_FS_GRL_FLAGS (0x40) /* */
+#define FS26_FS_I_OVUV_SAFE_REACTION1 (0x41) /* */
+#define FS26_FS_I_NOT_OVUV_SAFE_REACTION1 (0x42) /* */
+#define FS26_FS_I_OVUV_SAFE_REACTION2 (0x43) /* */
+#define FS26_FS_I_NOT_OVUV_SAFE_REACTION2 (0x44) /* */
+#define FS26_FS_I_WD_CFG (0x45) /* */
+#define FS26_FS_I_NOT_WD_CFG (0x46) /* */
+#define FS26_FS_I_SAFE_INPUTS (0x47) /* */
+#define FS26_FS_I_NOT_SAFE_INPUTS (0x48) /* */
+#define FS26_FS_I_FSSM (0x49) /* */
+#define FS26_FS_I_NOT_FSSM (0x4A) /* */
+#define FS26_FS_WDW_DURATION (0x4B) /* */
+#define FS26_FS_NOT_WDW_DURATION (0x4C) /* */
+#define FS26_FS_WD_ANSWER (0x4D) /* */
+#define FS26_FS_WD_TOKEN (0x4E) /* */
+#define FS26_FS_ABIST_ON_DEMAND (0x4F) /* */
+#define FS26_FS_OVUV_REG_STATUS (0x50) /* */
+#define FS26_FS_RELEASE_FS0B_FS1B (0x51) /* */
+#define FS26_FS_SAFE_IOS_1 (0x52) /* */
+#define FS26_FS_SAFE_IOS_2 (0x53) /* */
+#define FS26_FS_DIAG_SAFETY1 (0x54) /* */
+#define FS26_FS_DIAG_SAFETY2 (0x55) /* */
+#define FS26_FS_INTB_MASK (0x56) /* */
+#define FS26_FS_STATES (0x57) /* */
+#define FS26_FS_LP_REQ (0x58) /* */
+#define FS26_FS_LDT_LPSEL (0x59) /* */
+
+/* FS_I_OVUV_SAFE_REACTION1 register */
+
+#define VMON_PRE_OV_FS_REACTION_SHIFT (14) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_PRE */
+#define VMON_PRE_OV_FS_REACTION_MASK (0x3 << VMON_PRE_OV_FS_REACTION_SHIFT)
+# define VMON_PRE_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_PRE_OV_FS_REACTION_SHIFT)
+# define VMON_PRE_OV_FS_REACTION_FS0B (0x1 << VMON_PRE_OV_FS_REACTION_SHIFT)
+# define VMON_PRE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_OV_FS_REACTION_SHIFT)
+
+#define VMON_PRE_UV_FS_REACTION_SHIFT (12) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_PRE */
+#define VMON_PRE_UV_FS_REACTION_MASK (0x3 << VMON_PRE_UV_FS_REACTION_SHIFT)
+# define VMON_PRE_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_PRE_UV_FS_REACTION_SHIFT)
+# define VMON_PRE_UV_FS_REACTION_FS0B (0x1 << VMON_PRE_UV_FS_REACTION_SHIFT)
+# define VMON_PRE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_UV_FS_REACTION_SHIFT)
+
+#define VMON_CORE_OV_FS_REACTION_SHIFT (10) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_CORE */
+#define VMON_CORE_OV_FS_REACTION_MASK (0x3 << VMON_CORE_OV_FS_REACTION_SHIFT)
+# define VMON_CORE_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_CORE_OV_FS_REACTION_SHIFT)
+# define VMON_CORE_OV_FS_REACTION_FS0B (0x1 << VMON_CORE_OV_FS_REACTION_SHIFT)
+# define VMON_CORE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_OV_FS_REACTION_SHIFT)
+
+#define VMON_CORE_UV_FS_REACTION_SHIFT (8) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_CORE */
+#define VMON_CORE_UV_FS_REACTION_MASK (0x3 << VMON_CORE_UV_FS_REACTION_SHIFT)
+# define VMON_CORE_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_CORE_UV_FS_REACTION_SHIFT)
+# define VMON_CORE_UV_FS_REACTION_FS0B (0x1 << VMON_CORE_UV_FS_REACTION_SHIFT)
+# define VMON_CORE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_UV_FS_REACTION_SHIFT)
+
+#define VMON_LDO1_OV_FS_REACTION_SHIFT (6) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_LDO1 */
+#define VMON_LDO1_OV_FS_REACTION_MASK (0x3 << VMON_LDO1_OV_FS_REACTION_SHIFT)
+# define VMON_LDO1_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO1_OV_FS_REACTION_SHIFT)
+# define VMON_LDO1_OV_FS_REACTION_FS0B (0x1 << VMON_LDO1_OV_FS_REACTION_SHIFT)
+# define VMON_LDO1_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_OV_FS_REACTION_SHIFT)
+
+#define VMON_LDO1_UV_FS_REACTION_SHIFT (4) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_LDO1 */
+#define VMON_LDO1_UV_FS_REACTION_MASK (0x3 << VMON_LDO1_UV_FS_REACTION_SHIFT)
+# define VMON_LDO1_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO1_UV_FS_REACTION_SHIFT)
+# define VMON_LDO1_UV_FS_REACTION_FS0B (0x1 << VMON_LDO1_UV_FS_REACTION_SHIFT)
+# define VMON_LDO1_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_UV_FS_REACTION_SHIFT)
+
+#define VMON_LDO2_OV_FS_REACTION_SHIFT (2) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_LDO2 */
+#define VMON_LDO2_OV_FS_REACTION_MASK (0x3 << VMON_LDO2_OV_FS_REACTION_SHIFT)
+# define VMON_LDO2_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO2_OV_FS_REACTION_SHIFT)
+# define VMON_LDO2_OV_FS_REACTION_FS0B (0x1 << VMON_LDO2_OV_FS_REACTION_SHIFT)
+# define VMON_LDO2_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO2_OV_FS_REACTION_SHIFT)
+
+#define VMON_LDO2_UV_FS_REACTION_SHIFT (0) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_LDO2 */
+#define VMON_LDO2_UV_FS_REACTION_MASK (0x3 << VMON_LDO2_UV_FS_REACTION_SHIFT)
+# define VMON_LDO2_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_LDO2_UV_FS_REACTION_SHIFT)
+# define VMON_LDO2_UV_FS_REACTION_FS0B (0x1 << VMON_LDO2_UV_FS_REACTION_SHIFT)
+# define VMON_LDO2_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO2_UV_FS_REACTION_SHIFT)
+
+/* FS_I_OVUV_SAFE_REACTION2 register */
+
+#define VMON_EXT_OV_FS_REACTION_SHIFT (14) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_EXT */
+#define VMON_EXT_OV_FS_REACTION_MASK (0x3 << VMON_EXT_OV_FS_REACTION_SHIFT)
+# define VMON_EXT_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_EXT_OV_FS_REACTION_SHIFT)
+# define VMON_EXT_OV_FS_REACTION_FS0B (0x1 << VMON_EXT_OV_FS_REACTION_SHIFT)
+# define VMON_EXT_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_EXT_OV_FS_REACTION_SHIFT)
+
+#define VMON_EXT_UV_FS_REACTION_SHIFT (12) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_EXT */
+#define VMON_EXT_UV_FS_REACTION_MASK (0x3 << VMON_EXT_UV_FS_REACTION_SHIFT)
+# define VMON_EXT_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_EXT_UV_FS_REACTION_SHIFT)
+# define VMON_EXT_UV_FS_REACTION_FS0B (0x1 << VMON_EXT_UV_FS_REACTION_SHIFT)
+# define VMON_EXT_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_EXT_UV_FS_REACTION_SHIFT)
+
+#define VMON_REF_OV_FS_REACTION_SHIFT (10) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_REF */
+#define VMON_REF_OV_FS_REACTION_MASK (0x3 << VMON_REF_OV_FS_REACTION_SHIFT)
+# define VMON_REF_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_REF_OV_FS_REACTION_SHIFT)
+# define VMON_REF_OV_FS_REACTION_FS0B (0x1 << VMON_REF_OV_FS_REACTION_SHIFT)
+# define VMON_REF_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_REF_OV_FS_REACTION_SHIFT)
+
+#define VMON_REF_UV_FS_REACTION_SHIFT (8) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_REF */
+#define VMON_REF_UV_FS_REACTION_MASK (0x3 << VMON_REF_UV_FS_REACTION_SHIFT)
+# define VMON_REF_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_REF_UV_FS_REACTION_SHIFT)
+# define VMON_REF_UV_FS_REACTION_FS0B (0x1 << VMON_REF_UV_FS_REACTION_SHIFT)
+# define VMON_REF_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_REF_UV_FS_REACTION_SHIFT)
+
+#define VMON_TRK2_OV_FS_REACTION_SHIFT (6) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_TRK2 */
+#define VMON_TRK2_OV_FS_REACTION_MASK (0x3 << VMON_TRK2_OV_FS_REACTION_SHIFT)
+# define VMON_TRK2_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK2_OV_FS_REACTION_SHIFT)
+# define VMON_TRK2_OV_FS_REACTION_FS0B (0x1 << VMON_TRK2_OV_FS_REACTION_SHIFT)
+# define VMON_TRK2_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK2_OV_FS_REACTION_SHIFT)
+
+#define VMON_TRK2_UV_FS_REACTION_SHIFT (4) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_TRK2 */
+#define VMON_TRK2_UV_FS_REACTION_MASK (0x3 << VMON_TRK2_UV_FS_REACTION_SHIFT)
+# define VMON_TRK2_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK2_UV_FS_REACTION_SHIFT)
+# define VMON_TRK2_UV_FS_REACTION_FS0B (0x1 << VMON_TRK2_UV_FS_REACTION_SHIFT)
+# define VMON_TRK2_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK2_UV_FS_REACTION_SHIFT)
+
+#define VMON_TRK1_OV_FS_REACTION_SHIFT (2) /* Reaction on RSTB or FAIL SAFE outputs in case of OV detection on VMON_TRK1 */
+#define VMON_TRK1_OV_FS_REACTION_MASK (0x3 << VMON_TRK1_OV_FS_REACTION_SHIFT)
+# define VMON_TRK1_OV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK1_OV_FS_REACTION_SHIFT)
+# define VMON_TRK1_OV_FS_REACTION_FS0B (0x1 << VMON_TRK1_OV_FS_REACTION_SHIFT)
+# define VMON_TRK1_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK1_OV_FS_REACTION_SHIFT)
+
+#define VMON_TRK1_UV_FS_REACTION_SHIFT (0) /* Reaction on RSTB or FAIL SAFE outputs in case of UV detection on VMON_TRK1 */
+#define VMON_TRK1_UV_FS_REACTION_MASK (0x3 << VMON_TRK1_UV_FS_REACTION_SHIFT)
+# define VMON_TRK1_UV_FS_REACTION_NO_EFFECT (0x0 << VMON_TRK1_UV_FS_REACTION_SHIFT)
+# define VMON_TRK1_UV_FS_REACTION_FS0B (0x1 << VMON_TRK1_UV_FS_REACTION_SHIFT)
+# define VMON_TRK1_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_TRK1_UV_FS_REACTION_SHIFT)
+
+/* FS26_FS_I_WD_CFG register */
+
+#define WD_ERR_LIMIT_SHIFT (14) /* Watchdog error counter limit */
+#define WD_ERR_LIMIT_MASK (0x3 << WD_ERR_LIMIT_SHIFT)
+# define WD_ERR_LIMIT_8 (0x0 << WD_ERR_LIMIT_SHIFT)
+# define WD_ERR_LIMIT_6 (0x1 << WD_ERR_LIMIT_SHIFT)
+# define WD_ERR_LIMIT_4 (0x2 << WD_ERR_LIMIT_SHIFT)
+# define WD_ERR_LIMIT_2 (0x3 << WD_ERR_LIMIT_SHIFT)
+
+#define WD_RFR_LIMIT_SHIFT (11) /* Watchdog refresh counter limit */
+#define WD_RFR_LIMIT_MASK (0x3 << WD_RFR_LIMIT_SHIFT)
+# define WD_RFR_LIMIT_6 (0x0 << WD_RFR_LIMIT_SHIFT)
+# define WD_RFR_LIMIT_4 (0x1 << WD_RFR_LIMIT_SHIFT)
+# define WD_RFR_LIMIT_2 (0x2 << WD_RFR_LIMIT_SHIFT)
+# define WD_RFR_LIMIT_1 (0x3 << WD_RFR_LIMIT_SHIFT)
+
+#define WD_FS_REACTION_SHIFT (8) /* Reaction on RSTB or FAIL SAFE output in case of BAD Watchdog (data or timing) */
+#define WD_FS_REACTION_MASK (0x3 << WD_FS_REACTION_SHIFT)
+# define WD_FS_REACTION_NO_ACTION (0x0 << WD_FS_REACTION_SHIFT)
+# define WD_FS_REACTION_FS0B (0x1 << WD_FS_REACTION_SHIFT)
+# define WD_FS_REACTION_RSTB_FS0B (0x2 << WD_FS_REACTION_SHIFT)
+
+#define WD_RFR_CNT_SHIFT (8) /* Reflect the value of the Watchdog Refresh Counter */
+#define WD_RFR_CNT_MASK (0x7 << WD_RFR_CNT_SHIFT)
+#define WD_RFR_CNT(n) (n & (0x7 << WD_RFR_CNT_SHIFT))
+
+#define WD_ERR_CNT_SHIFT (0) /* Reflect the value of the Watchdog Error Counter */
+#define WD_ERR_CNT_MASK (0xF << WD_ERR_CNT_SHIFT)
Review Comment:
```suggestion
#define WD_ERR_CNT_MASK (0xf << WD_ERR_CNT_SHIFT)
```
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h:
##########
@@ -0,0 +1,505 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* QSPI Register Offsets ****************************************************/
+
+#define S32K3XX_QSPI_MCR_OFFSET (0x0000) /* Module Configuration Register (MCR) */
+#define S32K3XX_QSPI_IPCR_OFFSET (0x0008) /* IP Configuration Register (IPCR) */
+#define S32K3XX_QSPI_FLSHCR_OFFSET (0x000c) /* Flash Memory Configuration Register (FLSHCR) */
+#define S32K3XX_QSPI_BUF0CR_OFFSET (0x0010) /* Buffer 0 Configuration Register (BUF0CR) */
+#define S32K3XX_QSPI_BUF1CR_OFFSET (0x0014) /* Buffer 1 Configuration Register (BUF1CR) */
+#define S32K3XX_QSPI_BUF2CR_OFFSET (0x0018) /* Buffer 2 Configuration Register (BUF2CR) */
+#define S32K3XX_QSPI_BUF3CR_OFFSET (0x001c) /* Buffer 3 Configuration Register (BUF3CR) */
+#define S32K3XX_QSPI_BFGENCR_OFFSET (0x0020) /* Buffer Generic Configuration Register (BFGENCR) */
+#define S32K3XX_QSPI_SOCCR_OFFSET (0x0024) /* SOC Configuration Register (SOCCR) */
+#define S32K3XX_QSPI_BUF0IND_OFFSET (0x0030) /* Buffer 0 Top Index Register (BUF0IND) */
+#define S32K3XX_QSPI_BUF1IND_OFFSET (0x0034) /* Buffer 1 Top Index Register (BUF1IND) */
+#define S32K3XX_QSPI_BUF2IND_OFFSET (0x0038) /* Buffer 2 Top Index Register (BUF2IND) */
+#define S32K3XX_QSPI_DLLCRA_OFFSET (0x0060) /* DLL Flash Memory A Configuration Register (DLLCRA) */
+#define S32K3XX_QSPI_SFAR_OFFSET (0x0100) /* Serial Flash Memory Address Register (SFAR) */
+#define S32K3XX_QSPI_SMPR_OFFSET (0x0108) /* Sampling Register (SMPR) */
+#define S32K3XX_QSPI_RBSR_OFFSET (0x010c) /* RX Buffer Status Register (RBSR) */
+#define S32K3XX_QSPI_RBCT_OFFSET (0x0110) /* RX Buffer Control Register (RBCT) */
+#define S32K3XX_QSPI_DLSR_FA_OFFSET (0x0134) /* Data Learning Status Flash Memory A Register (DLSR_FA) */
+#define S32K3XX_QSPI_TBSR_OFFSET (0x0150) /* TX Buffer Status Register (TBSR) */
+#define S32K3XX_QSPI_TBDR_OFFSET (0x0154) /* TX Buffer Data Register (TBDR) */
+#define S32K3XX_QSPI_TBCT_OFFSET (0x0158) /* TX Buffer Control Register (TBCT) */
+#define S32K3XX_QSPI_SR_OFFSET (0x015c) /* Status Register (SR) */
+#define S32K3XX_QSPI_FR_OFFSET (0x0160) /* Flag Register (FR) */
+#define S32K3XX_QSPI_RSER_OFFSET (0x0164) /* Interrupt and DMA Request Select and Enable Register (RSER) */
+#define S32K3XX_QSPI_SPTRCLR_OFFSET (0x016c) /* Sequence Pointer Clear Register (SPTRCLR) */
+#define S32K3XX_QSPI_SFA1AD_OFFSET (0x0180) /* Serial Flash Memory A1 Top Address Register (SFA1AD) */
+#define S32K3XX_QSPI_SFA2AD_OFFSET (0x0184) /* Serial Flash Memory A2 Top Address Register (SFA2AD) */
+#define S32K3XX_QSPI_SFB1AD_OFFSET (0x0188) /* Serial Flash Memory B1 Top Address Register (SFB1AD) */
+#define S32K3XX_QSPI_SFB2AD_OFFSET (0x018c) /* Serial Flash Memory B2 Top Address Register (SFB2AD) */
+
+#define S32K3XX_QSPI_RBDR_OFFSET(n) (0x0200 + ((n) << 2)) /* RX Buffer Data Register (RBDRn, n=0,...,63) */
+
+#define S32K3XX_QSPI_LUTKEY_OFFSET (0x0300) /* LUT Key Register (LUTKEY) */
+#define S32K3XX_QSPI_LCKCR_OFFSET (0x0304) /* LUT Lock Configuration Register (LKCR) */
+#define S32K3XX_QSPI_LUT0_OFFSET (0x0310) /* LUT Register 0 (LUT0) */
+#define S32K3XX_QSPI_LUT1_OFFSET (0x0314) /* LUT Register 1 (LUT1) */
+#define S32K3XX_QSPI_LUT2_OFFSET (0x0318) /* LUT Register 2 (LUT2) */
+#define S32K3XX_QSPI_LUT3_OFFSET (0x031c) /* LUT Register 3 (LUT3) */
+#define S32K3XX_QSPI_LUT4_OFFSET (0x0320) /* LUT Register 4 (LUT4) */
+#define S32K3XX_QSPI_LUT5_OFFSET (0x0324) /* LUT Register 5 (LUT5) */
+#define S32K3XX_QSPI_LUT6_OFFSET (0x0328) /* LUT Register 6 (LUT6) */
+#define S32K3XX_QSPI_LUT7_OFFSET (0x032c) /* LUT Register 7 (LUT7) */
+#define S32K3XX_QSPI_LUT8_OFFSET (0x0330) /* LUT Register 8 (LUT8) */
+#define S32K3XX_QSPI_LUT9_OFFSET (0x0334) /* LUT Register 9 (LUT9) */
+#define S32K3XX_QSPI_LUT10_OFFSET (0x0338) /* LUT Register 10 (LUT10) */
+#define S32K3XX_QSPI_LUT11_OFFSET (0x033c) /* LUT Register 11 (LUT11) */
+#define S32K3XX_QSPI_LUT12_OFFSET (0x0340) /* LUT Register 12 (LUT12) */
+#define S32K3XX_QSPI_LUT13_OFFSET (0x0344) /* LUT Register 13 (LUT13) */
+#define S32K3XX_QSPI_LUT14_OFFSET (0x0348) /* LUT Register 14 (LUT14) */
+#define S32K3XX_QSPI_LUT15_OFFSET (0x034c) /* LUT Register 15 (LUT15) */
+#define S32K3XX_QSPI_LUT16_OFFSET (0x0350) /* LUT Register 16 (LUT16) */
+#define S32K3XX_QSPI_LUT17_OFFSET (0x0354) /* LUT Register 17 (LUT17) */
+#define S32K3XX_QSPI_LUT18_OFFSET (0x0358) /* LUT Register 18 (LUT18) */
+#define S32K3XX_QSPI_LUT19_OFFSET (0x035c) /* LUT Register 19 (LUT19) */
+
+/* QSPI Register Addresses **************************************************/
+
+#define S32K3XX_QSPI_MCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_MCR_OFFSET)
+#define S32K3XX_QSPI_IPCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_IPCR_OFFSET)
+#define S32K3XX_QSPI_FLSHCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FLSHCR_OFFSET)
+#define S32K3XX_QSPI_BUF0CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0CR_OFFSET)
+#define S32K3XX_QSPI_BUF1CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1CR_OFFSET)
+#define S32K3XX_QSPI_BUF2CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2CR_OFFSET)
+#define S32K3XX_QSPI_BUF3CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF3CR_OFFSET)
+#define S32K3XX_QSPI_BFGENCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BFGENCR_OFFSET)
+#define S32K3XX_QSPI_SOCCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SOCCR_OFFSET)
+#define S32K3XX_QSPI_BUF0IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0IND_OFFSET)
+#define S32K3XX_QSPI_BUF1IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1IND_OFFSET)
+#define S32K3XX_QSPI_BUF2IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2IND_OFFSET)
+#define S32K3XX_QSPI_DLLCRA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLLCRA_OFFSET)
+#define S32K3XX_QSPI_SFAR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFAR_OFFSET)
+#define S32K3XX_QSPI_SMPR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SMPR_OFFSET)
+#define S32K3XX_QSPI_RBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBSR_OFFSET)
+#define S32K3XX_QSPI_RBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBCT_OFFSET)
+#define S32K3XX_QSPI_DLSR_FA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLSR_FA_OFFSET)
+#define S32K3XX_QSPI_TBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBSR_OFFSET)
+#define S32K3XX_QSPI_TBDR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBDR_OFFSET)
+#define S32K3XX_QSPI_TBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBCT_OFFSET)
+#define S32K3XX_QSPI_SR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SR_OFFSET)
+#define S32K3XX_QSPI_FR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FR_OFFSET)
+#define S32K3XX_QSPI_RSER (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RSER_OFFSET)
+#define S32K3XX_QSPI_SPTRCLR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SPTRCLR_OFFSET)
+#define S32K3XX_QSPI_SFA1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA1AD_OFFSET)
+#define S32K3XX_QSPI_SFA2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA2AD_OFFSET)
+#define S32K3XX_QSPI_SFB1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB1AD_OFFSET)
+#define S32K3XX_QSPI_SFB2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB2AD_OFFSET)
+#define S32K3XX_QSPI_RBDR(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBDR_OFFSET(n))
+#define S32K3XX_QSPI_LUTKEY (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUTKEY_OFFSET)
+#define S32K3XX_QSPI_LCKCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LCKCR_OFFSET)
+#define S32K3XX_QSPI_LUT0 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET)
+#define S32K3XX_QSPI_LUT1 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT1_OFFSET)
+#define S32K3XX_QSPI_LUT2 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT2_OFFSET)
+#define S32K3XX_QSPI_LUT3 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT3_OFFSET)
+#define S32K3XX_QSPI_LUT4 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT4_OFFSET)
+#define S32K3XX_QSPI_LUT5 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT5_OFFSET)
+#define S32K3XX_QSPI_LUT6 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT6_OFFSET)
+#define S32K3XX_QSPI_LUT7 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT7_OFFSET)
+#define S32K3XX_QSPI_LUT8 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT8_OFFSET)
+#define S32K3XX_QSPI_LUT9 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT9_OFFSET)
+#define S32K3XX_QSPI_LUT10 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT10_OFFSET)
+#define S32K3XX_QSPI_LUT11 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT11_OFFSET)
+#define S32K3XX_QSPI_LUT12 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT12_OFFSET)
+#define S32K3XX_QSPI_LUT13 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT13_OFFSET)
+#define S32K3XX_QSPI_LUT14 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT14_OFFSET)
+#define S32K3XX_QSPI_LUT15 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT15_OFFSET)
+#define S32K3XX_QSPI_LUT16 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT16_OFFSET)
+#define S32K3XX_QSPI_LUT17 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT17_OFFSET)
+#define S32K3XX_QSPI_LUT18 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT18_OFFSET)
+#define S32K3XX_QSPI_LUT19 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT19_OFFSET)
+
+#define S32K3XX_QSPI_LUT(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET + (n*4))
+#define S32K3XX_QSPI_LUT_COUNT 20
+
+/* QSPI Register Bitfield Definitions ***************************************/
+
+/* Module Configuration Register (MCR) */
+
+#define QSPI_MCR_SWRSTSD (1 << 0) /* Bit 0: Software reset for serial flash memory domain (SWRSTSD) */
+#define QSPI_MCR_SWRSTHD (1 << 1) /* Bit 1: Software reset fo AHB domain (SWRSTHD) */
+ /* Bits 2-9: Reserved */
+#define QSPI_MCR_CLR_RXF (1 << 10) /* Bit 10: Clear RX FIFO (CLR_RXF) */
+#define QSPI_MCR_CLR_TXF (1 << 11) /* Bit 11: Clear TX FIFO/buffer (CLR_TXF) */
+ /* Bits 12-13: Reserved */
+#define QSPI_MCR_MDIS (1 << 14) /* Bit 14: Module disable (MDIS) */
+ /* Bits 15-23: Reserved */
+#define QSPI_MCR_DQS_FA_SEL_SHIFT (24) /* Bits 24-25: DQS clock for sampling read data at flash memory A (DQS_FA_SEL) */
+#define QSPI_MCR_DQS_FA_SEL_MASK (0x03 << QSPI_MCR_DQS_FA_SEL_SHIFT)
+#define QSPI_MCR_DQS_FA_SEL_INTERNAL_DQS ((0x00 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+#define QSPI_MCR_DQS_FA_SEL_LOOPBACK ((0x01 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+#define QSPI_MCR_DQS_FA_SEL_LOOPBACK_DQS ((0x02 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+ /* Bits 26-31: Reserved */
+
+/* IP Configuration Register (IPCR) */
+
+#define QSPICR_IDATSZ_SHIFT (0) /* Bits 0-15: IP data transfer size (IDATSZ) */
+#define QSPICR_IDATSZ_MASK (0xffff << QSPICR_IDATSZ_SHIFT)
+#define QSPICR_IDATSZ(n) ((n << QSPICR_IDATSZ_SHIFT) & QSPICR_IDATSZ_MASK)
+ /* Bits 16-23: Reserved */
+#define QSPICR_SEQID_SHIFT (24) /* Bits 24-27: Points to a sequence in the LUT (SEQID) */
+#define QSPICR_SEQID_MASK (0x0f << QSPICR_SEQID_SHIFT)
+#define QSPICR_SEQID(n) ((n << QSPICR_SEQID_SHIFT) & QSPICR_SEQID_MASK)
+ /* Bits 28-31: Reserved */
+
+/* Flash Memory Configuration Register (FLSHCR) */
+
+#define QSPI_FLSHCR_TCSS_SHIFT (0) /* Bits 0-3: Serial flash memory CS setup time (TCSS) */
+#define QSPI_FLSHCR_TCSS_MASK (0x0f << QSPI_FLSHCR_TCSS_SHIFT)
+#define QSPI_FLSHCR_TCSS(n) (n & QSPI_FLSHCR_TCSS_MASK)
+#define QSPI_FLSHCR_TCSH_SHIFT (8) /* Bits 8-11: Serial flash memory CS hold time (TCSH) */
+#define QSPI_FLSHCR_TCSH_MASK (0x0f << QSPI_FLSHCR_TCSH_SHIFT)
+#define QSPI_FLSHCR_TCSH(n) ((n << QSPI_FLSHCR_TCSH_SHIFT) & QSPI_FLSHCR_TCSH_MASK)
+ /* Bits 12-31: Reserved */
+
+/* Buffer n Configuration Register (BUFnCR) */
+
+#define QSPI_BUFCR_MSTRID_SHIFT (0) /* Bits 0-3: Master ID (MSTRID) */
+#define QSPI_BUFCR_MSTRID_MASK (0x0f << QSPI_BUFCR_MSTRID_SHIFT)
+#define QSPI_BUFCR_MSTRID(n) ((n << QSPI_BUFCR_MSTRID_SHIFT) & QSPI_BUFCR_MSTRID_MASK)
+ /* Bits 4-7: Reserved */
+#define QSPI_BUFCR_ADATSZ_SHIFT (8) /* Bits 8-13: AHB data transfer size (ADATSZ) */
+#define QSPI_BUFCR_ADATSZ_MASK (0x3f << QSPI_BUFCR_ADATSZ_SHIFT)
+#define QSPI_BUFCR_ADATSZ(n) ((n << QSPI_BUFCR_ADATSZ_SHIFT) & QSPI_BUFCR_ADATSZ_MASK)
+ /* Bits 14-31: Reserved */
+#define QSPI_BUF3CR_ALLMST (1 << 31) /* Bit 31: All master enable (ALLMST) */
+
+/* Buffer Generic Configuration Register (BFGENCR) */
+
+ /* Bits 0-11: Reserved */
+#define QSPI_BFGENCR_SEQID_SHIFT (12) /* Bits 12-15: Points to a sequence in the LUT (SEQID) */
+#define QSPI_BFGENCR_SEQID_MASK (0x0f << QSPI_BFGENCR_SEQID_SHIFT)
+ /* Bits 16-31: Reserved */
+
+/* SOC Configuration Register (SOCCR) */
+
+#define QSPI_SOCCR_SOCCFG_SHIFT (0) /* Bits 0-31: SOC configuration (SOCCFG) */
+#define QSPI_SOCCR_SOCCFG_MASK (0xffffffff << QSPI_SOCCR_SOCCFG_SHIFT)
+#define QSPI_SOCCR_OBE_PULL_TMG_RLX (1 << 0) /* Bit 0: obe_pull_timing_relax_b*/
+#define QSPI_SOCCR_IBE (1 << 1) /* Bit 1: IBE */
+#define QSPI_SOCCR_OBE (1 << 2) /* Bit 2: OBE */
+#define QSPI_SOCCR_DSE (1 << 3) /* Bit 3: DSE */
+#define QSPI_SOCCR_PUE (1 << 4) /* Bit 4: PUE */
+#define QSPI_SOCCR_PUS (1 << 5) /* Bit 5: PUS */
+#define QSPI_SOCCR_SRE (1 << 6) /* Bit 6: SRE */
+
+/* Buffer n Top Index Register (BUFnIND) */
+
+ /* Bits 0-2: Reserved */
+#define QSPI_BUFIND_TPINDX_SHIFT (3) /* Bits 3-8: Top index of buffer n (TPINDXn) */
+#define QSPI_BUFIND_TPINDX_MASK (0x3f << QSPI_BUFIND_TPINDX_SHIFT)
+ /* Bits 9-31: Reserved */
+
+/* DLL Flash Memory A Configuration Register (DLLCRA) */
+
+#define QSPI_DLLCRA_SLV_UPD (1 << 0) /* Bit 0: Slave update (SLV_UPD) */
+#define QSPI_DLLCRA_SLV_DLL_BYPASS (1 << 1) /* Bit 1: Slave DLL bypass (SLV_DLL_BYPASS) */
+#define QSPI_DLLCRA_SLV_EN (1 << 2) /* Bit 2: Slave enable (SLV_EN) */
+ /* Bits 3-7: Reserved */
+
+#define QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT (8) /* Bits 8-11: Delay elements in each delay tap (SLV_DLY_COARSE) */
+#define QSPI_DLLCRA_SLV_DLY_COARSE_MASK (0x0f << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT)
+#define QSPI_DLLCRA_SLV_DLY_COARSE(n) ((n << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT) & QSPI_DLLCRA_SLV_DLY_COARSE_MASK)
+#define QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT (12) /* Bits 12-14: T/16 offset delay elements in incoming DQS (SLV_DLY_OFFSET) */
+#define QSPI_DLLCRA_SLV_DLY_OFFSET_MASK (0x07 << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT)
+#define QSPI_DLLCRA_SLV_DLY(n) ((n << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT) & QSPI_DLLCRA_SLV_DLY_OFFSET_MASK)
+ /* Bit 15: Reserved */
+#define QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT (16) /* Bits 16-19: Fine offset delay elements in incoming DQS (SLV_FINE_OFFSET) */
+#define QSPI_DLLCRA_SLV_FINE_OFFSET_MASK (0x0f << QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT)
+ /* Bits 20-29: Reserved */
+#define QSPI_DLLCRA_FREQEN (1 << 30) /* Bit 30: Frequency enable (FREQEN) */
+ /* Bit 31: Reserved */
+
+/* Serial Flash Memory Address Register (SFAR) */
+
+#define QSPI_SFAR_SFADR_SHIFT (0) /* Bits 0-31: Serial flash memory address (SFADR) */
+#define QSPI_SFAR_SFADR_MASK (0xffffffff << QSPI_SFAR_SFADR_SHIFT)
+
+/* Sampling Register (SMPR) */
+
+ /* Bits 0-4: Reserved */
+#define QSPI_SMPR_FSPHS (1 << 5) /* Bit 5: Full speed phase selection for SDR instructions (FSPHS) */
+#define QSPI_SMPR_FSDLY (1 << 6) /* Bit 6: Full speed delay section for SDR instructions (FSDLY) */
+ /* Bits 7-23: Reserved */
+#define QSPI_SMPR_DLLFSMPFA_SHIFT (24) /* Bits 24-26: Selects the nth tap provided by slave delay chain for flash memory A (DLLFSMPFA) */
+#define QSPI_SMPR_DLLFSMPFA_MASK (0x07 << QSPI_SMPR_DLLFSMPFA_SHIFT)
+#define QSPI_SMPR_DLLFSMPFA(n) ((n << QSPI_SMPR_DLLFSMPFA_SHIFT) & QSPI_SMPR_DLLFSMPFA_MASK)
+ /* Bits 27-31: Reserved */
+
+/* RX Buffer Status Register (RBSR) */
+
+#define QSPI_RBSR_RDBFL_SHIFT (0) /* Bits 0-7: RX buffer fill level (RDBFL) */
+#define QSPI_RBSR_RDBFL_MASK (0xff << QSPI_RBSR_RDBFL_SHIFT)
+ /* Bits 8-15: Reserved */
+#define QSPI_RBSR_RDCTR_SHIFT (16) /* Bits 16-31: Read counter (RDCTR) */
+#define QSPI_RBSR_RDCTR_MASK (0xffff << QSPI_RBSR_RDCTR_SHIFT)
+
+/* RX Buffer Control Register (RBCT) */
+
+#define QSPI_RBCT_WMRK_SHIFT (0) /* Bits 0-6: RX buffer watermark (WMRK) */
+#define QSPI_RBCT_WMRK_MASK (0x7f << QSPI_RBCT_WMRK_SHIFT)
+#define QSPI_RBCT_WMRK(n) ((n << QSPI_RBCT_WMRK_SHIFT) & QSPI_RBCT_WMRK_MASK)
+ /* Bit 7: Reserved */
+#define QSPI_RBCT_RXBRD (1 << 8) /* Bit 8: RX buffer readout (RXBRD) */
+# define QSPI_RBCT_RXBRD_AHB (0 << 8) /* RX buffer content is read using the AHB bus registers */
+# define QSPI_RBCT_RXBRD_IP (1 << 8) /* RX buffer content is read using the IP bus registers */
+ /* Bits 9-31: Reserved */
+
+/* Data Learning Status Flash Memory A Register (DLSR_FA) */
+
+#define QSPI_DLSR_FA_NEG_EDGE_SHIFT (0) /* Bits 0-7: DLP negative edge match signature for flash memory A (NEG_EDGE) */
+#define QSPI_DLSR_FA_NEG_EDGE_MASK (0xff << QSPI_DLSR_FA_NEG_EDGE_SHIFT)
+#define QSPI_DLSR_FA_POS_EDGE_SHIFT (8) /* Bits 8-15: DLP positive edge match signature for flash memory A (POS_EDGE) */
+#define QSPI_DLSR_FA_POS_EDGE_MASK (0xff << QSPI_DLSR_FA_POS_EDGE_SHIFT)
+ /* Bits 16-30: Reserved */
+#define QSPI_DLSR_FA_DLPFFA (1 << 31) /* Bit 31: Data learning pattern fail (DLPFFA) */
+
+/* TX Buffer Status Register (TBSR) */
+
+#define QSPI_TBSR_TRBLF_SHIFT (0) /* Bits 0-5: TX buffer fill level (TRBFL) */
+#define QSPI_TBSR_TRBLF_MASK (0x3f << QSPI_TBSR_TRBLF_SHIFT)
+ /* Bits 6-15: Reserved */
+#define QSPI_TBSR_TRCTR_SHIFT (16) /* Bits 16-31: Transmit counter (TRCTR) */
+#define QSPI_TBSR_TRCTR_MASK (0xffff << QSPI_TBSR_TRCTR_SHIFT)
+
+/* TX Buffer Data Register (TBDR) */
+
+#define QSPI_TBDR_TXDATA_SHIFT (0) /* Bits 0-31: TX data (TXDATA) */
+#define QSPI_TBDR_TXDATA_MASK (0xffffffff << QSPI_TBDR_TXDATA_SHIFT)
+
+/* TX Buffer Control Register (TBCT) */
+
+#define QSPI_TBCT_WMRK_SHIFT (0) /* Bits 0-4: Watermark for TX buffer (WMRK) */
+#define QSPI_TBCT_WMRK_MASK (0x1f << QSPI_TBCT_WMRK_SHIFT)
+#define QSPI_TBCT_WMRK(n) ((n << QSPI_TBCT_WMRK_SHIFT) & QSPI_TBCT_WMRK_MASK)
+ /* Bits 5-31: Reserved */
+
+/* Status Register (SR) */
+
+#define QSPI_SR_BUSY (1 << 0) /* Bit 0: Module busy (BUSY) */
+#define QSPI_SR_IP_ACC (1 << 1) /* Bit 1: IP access (IP_ACC) */
+#define QSPI_SR_AHB_ACC (1 << 2) /* Bit 2: AHB read access (AHB_ACC) */
+ /* Bits 3-5: Reserved */
+#define QSPI_SR_AHBTRN (1 << 6) /* Bit 6: AHB access transaction pending (AHBTRN) */
+#define QSPI_SR_AHB0NE (1 << 7) /* Bit 7: AHB 0 buffer not empty (AHB0NE) */
+#define QSPI_SR_AHB1NE (1 << 8) /* Bit 8: AHB 1 buffer not empty (AHB1NE) */
+#define QSPI_SR_AHB2NE (1 << 9) /* Bit 9: AHB 2 buffer not empty (AHB2NE) */
+#define QSPI_SR_AHB3NE (1 << 10) /* Bit 10: AHB 3 buffer not empty (AHB3NE) */
+#define QSPI_SR_AHB0FUL (1 << 11) /* Bit 11: AHB 0 buffer full (AHB0FUL) */
+#define QSPI_SR_AHB1FUL (1 << 12) /* Bit 12: AHB 1 buffer full (AHB1FUL) */
+#define QSPI_SR_AHB2FUL (1 << 13) /* Bit 13: AHB 2 buffer full (AHB2FUL) */
+#define QSPI_SR_AHB3FUL (1 << 14) /* Bit 14: AHB 3 buffer full (AHB3FUL) */
+ /* Bit 15: Reserved */
+#define QSPI_SR_RXWE (1 << 16) /* Bit 16: RX buffer watermark exceeded (RXWE) */
+ /* Bits 17-18: Reserved */
+#define QSPI_SR_RXFULL (1 << 19) /* Bit 19: RX buffer full (RXFULL) */
+ /* Bits 20-22: Reserved */
+#define QSPI_SR_RXDMA (1 << 23) /* Bit 23: RX buffer DMA (RXDMA) */
+#define QSPI_SR_TXNE (1 << 24) /* Bit 24: TX buffer not empty (TXNE) */
+#define QSPI_SR_TXWA (1 << 25) /* Bit 25: TX buffer watermark available (TXWA) */
+#define QSPI_SR_TXDMA (1 << 26) /* Bit 26: TX buffer DMA (TXDMA) */
+#define QSPI_SR_TXFUL (1 << 27) /* Bit 27: TX buffer full (TXFULL) */
+ /* Bits 28-31: Reserved */
+
+/* Flag Register (FR) */
+
+#define QSPI_FR_TFF (1 << 0) /* Bit 0: IP command transaction finished flag (TFF) */
+ /* Bits 1-5: Reserved */
+#define QSPI_FR_IPIEF (1 << 6) /* Bit 6: IP command trigger could not be executed error flag (IPIEF) */
+#define QSPI_FR_IPAEF (1 << 7) /* Bit 7: IP command trigger during AHB access error flag (IPAEF) */
+ /* Bits 8-11: Reserved */
+#define QSPI_FR_ABOF (1 << 12) /* Bit 12: AHB buffer overflow flag (ABOF) */
+#define QSPI_FR_AIBSEF (1 << 13) /* Bit 13: AHB illegal burst size error flag (AIBSEF) */
+#define QSPI_FR_AITEF (1 << 14) /* Bit 14: AHB illegal transaction error flag (AITEF) */
+ /* Bit 15: Reserved */
+#define QSPI_FR_RBDF (1 << 16) /* Bit 16: RX buffer drain flag (RBDF) */
+#define QSPI_FR_RBOF (1 << 17) /* Bit 17: RX buffer overflow flag (RBOF) */
+ /* Bits 18-22: Reserved */
+#define QSPI_FR_ILLINE (1 << 23) /* Bit 23: Illegal instruction error flag (ILLINE) */
+ /* Bits 24-25: Reserved */
+#define QSPI_FR_TBUF (1 << 26) /* Bit 26: TX buffer underrun flag (TBUF) */
+#define QSPI_FR_TBFF (1 << 27) /* Bit 27: TX buffer fill flag (TBFF) */
+ /* Bits 28-31: Reserved */
+
+/* Interrupt and DMA Request Select and Enable Register (RSER) */
+
+#define QSPI_RSER_TFIE (1 << 0) /* Bit 0: Transaction finished interrupt enable flag (TFIE) */
+ /* Bits 1-5: Reserved */
+#define QSPI_RSER_IPIEIE (1 << 6) /* Bit 6: IP command trigger during IP access error interrupt enable flag (IPIEIE) */
+#define QSPI_RSER_IPAEIE (1 << 7) /* Bit 7: IP command trigger during AHB read access error interrupt enable flag (IPAEIE) */
+ /* Bits 8-11: Reserved */
+#define QSPI_RSER_ABOIE (1 << 12) /* Bit 12: AHB buffer overflow interrupt enable flag (ABOIE) */
+#define QSPI_RSER_AIBSIE (1 << 13) /* Bit 13: AHB illegal burst size interrupt enable flag (AIBSIE) */
+#define QSPI_RSER_AITIE (1 << 14) /* Bit 14: AHB illegal transaction interrupt enable flag (AITIE) */
+ /* Bit 15: Reserved */
+#define QSPI_RSER_RBDIE (1 << 16) /* Bit 16: RX buffer drain interrupt enable (RBDIE) */
+#define QSPI_RSER_RBOIE (1 << 17) /* Bit 17: RX buffer overflow interrupt enable (RBOIE) */
+ /* Bits 18-20: Reserved */
+#define QSPI_RSER_RBDDE (1 << 21) /* Bit 21: RX buffer drain DMA enable (RBDDE) */
+ /* Bit 22: Reserved */
+#define QSPI_RSER_ILLINIE (1 << 23) /* Bit 23: Illegal instruction error interrupt enable (ILLINIE) */
+ /* Bit 24: Reserved */
+#define QSPI_RSER_TBFDE (1 << 25) /* Bit 25: TX buffer fill DMA enable (TBFDE) */
+#define QSPI_RSER_TBUIE (1 << 26) /* Bit 26: TX buffer underrun interrupt enable flag (TBUIE) */
+#define QSPI_RSER_TBFIE (1 << 27) /* Bit 27: TX buffer fill interrupt enable flag (TBFIE) */
+ /* Bits 28-31: Reserved */
+
+/* Sequence Pointer Clear Register (SPTRCLR) */
+
+#define QSPI_SPTRCLR_BFPTRC (1 << 0) /* Bit 0: Buffer pointer clear (BFPTRC) */
+ /* Bits 1-7: Reserved */
+#define QSPI_SPTRCLR_IPPTRC (1 << 8) /* Bit 8: IP pointer clear (IPPTRC) */
+ /* Bits 9-31: Reserved */
+
+/* Serial Flash Memory An/Bn Top Address Register (SFAnAD/SFBnAD) */
+
+ /* Bits 0-9: Reserved */
+#define QSPI_SFAD_TPAD_SHIFT (10) /* Bits 10-31: Top address for serial flash memory An/Bn (TPADAn/TPADBn) */
+#define QSPI_SFAD_TPAD_MASK (0x3fffff << QSPI_SFAD_TPAD_SHIFT)
+#define QSPI_SFAD_TPAD(n) ((n << QSPI_SFAD_TPAD_SHIFT) & QSPI_SFAD_TPAD_MASK)
+
+/* RX Buffer Data Register (RBDRn, n=0,...,63) */
+
+#define QSPI_RBDR_RXDATA_SHIFT (0) /* Bits 0-31: RX data (RXDATA) */
+#define QSPI_RBDR_RXDATA_MASK (0xffffffff << QSPI_RBDR_RXDATA_SHIFT)
+
+/* LUT Key Register (LUTKEY) */
+
+#define QSPI_LUTKEY_KEY_SHIFT (0) /* Bits 0-31: Key to lock or unlock the LUT (KEY) */
+#define QSPI_LUTKEY_KEY_MASK (0xffffffff << QSPI_LUTKEY_KEY_SHIFT)
+#define QSPI_LUTKEY_KEY (0x5AF05AF0UL)
+
+/* LUT Lock Configuration Register (LKCR) */
+
+#define QSPI_LKCR_LOCK (1 << 0) /* Bit 0: Lock LUT (LOCK) */
+#define QSPI_LKCR_UNLOCK (1 << 1) /* Bit 1: Unlock LUT (UNLOCK) */
+ /* Bits 2-31: Reserved */
+
+/* LUT Register (LUTn) */
+
+#define QSPI_LUT_OPRND0_SHIFT (0) /* Bits 0-7: Operand for INSTR0 (OPRND0) */
+#define QSPI_LUT_OPRND0_MASK (0xff << QSPI_LUT_OPRND0_SHIFT)
+#define QSPI_LUT_OPRND0(n) ((n << QSPI_LUT_OPRND0_SHIFT) & QSPI_LUT_OPRND0_MASK)
+#define QSPI_LUT_PAD0_SHIFT (8) /* Bits 8-9: Pad information for INSTR0 (PAD0) */
+#define QSPI_LUT_PAD0_MASK (0x03 << QSPI_LUT_PAD0_SHIFT)
+# define QSPI_LUT_PAD0_1 (0x00 << QSPI_LUT_PAD0_SHIFT) /* 1 Pad */
+# define QSPI_LUT_PAD0_2 (0x01 << QSPI_LUT_PAD0_SHIFT) /* 2 Pad */
+# define QSPI_LUT_PAD0_4 (0x02 << QSPI_LUT_PAD0_SHIFT) /* 4 Pad */
+
+#define QSPI_LUT_INSTR0_SHIFT (10) /* Bits 10-15: Instruction 0 (INSTR0) */
+#define QSPI_LUT_INSTR0_MASK (0x3f << QSPI_LUT_INSTR0_SHIFT)
+#define QSPI_LUT_INSTR0(n) ((n << QSPI_LUT_INSTR0_SHIFT) & QSPI_LUT_INSTR0_MASK)
+
+#define QSPI_LUT_OPRND1_SHIFT (16) /* Bits 16-23: Operand for INSTR1 (OPRND1) */
+#define QSPI_LUT_OPRND1_MASK (0xff << QSPI_LUT_OPRND1_SHIFT)
+#define QSPI_LUT_OPRND1(n) ((n << QSPI_LUT_OPRND1_SHIFT) & QSPI_LUT_OPRND1_MASK)
+#define QSPI_LUT_PAD1_SHIFT (24) /* Bits 24-25: Pad information for INSTR1 (PAD1) */
+#define QSPI_LUT_PAD1_MASK (0x03 << QSPI_LUT_PAD1_SHIFT)
+# define QSPI_LUT_PAD1_1 (0x00 << QSPI_LUT_PAD1_SHIFT) /* 1 Pad */
+# define QSPI_LUT_PAD1_2 (0x01 << QSPI_LUT_PAD1_SHIFT) /* 2 Pad */
+# define QSPI_LUT_PAD1_4 (0x02 << QSPI_LUT_PAD1_SHIFT) /* 4 Pad */
+
+#define QSPI_LUT_INSTR1_SHIFT (26) /* Bits 26-31: Instruction 1 (INSTR1) */
+#define QSPI_LUT_INSTR1_MASK (0x3f << QSPI_LUT_INSTR1_SHIFT)
+#define QSPI_LUT_INSTR1(n) ((n << QSPI_LUT_INSTR1_SHIFT) & QSPI_LUT_INSTR1_MASK)
+
+/* External Memory Base Address */
+
+#define QSPI_AMBA_BASE 0x68000000
+
+/* flash connection to the QSPI module */
+
+typedef enum
+{
+ QSPI_SIDE_A1 = 0x00u, /* Serial flash connected on side A1 */
+ QSPI_SIDE_A2 = 0x01u, /* Serial flash connected on side A2 */
+ QSPI_SIDE_B1 = 0x02u, /* Serial flash connected on side B1 */
+ QSPI_SIDE_B2 = 0x03u, /* Serial flash connected on side B2 */
+} s32k3xx_qspi_connectiontype;
+
+/* flash operation type */
+
+typedef enum
+{
+ QSPI_OP_TYPE_CMD = 0x00u, /* Simple command */
+ QSPI_OP_TYPE_WRITE_REG = 0x01u, /* Write value in external flash register */
+ QSPI_OP_TYPE_RMW_REG = 0x02u, /* RMW command on external flash register */
+ QSPI_OP_TYPE_READ_REG = 0x03u, /* Read external flash register until expected value is read */
+ QSPI_OP_TYPE_QSPI_CFG = 0x04u, /* Re-configure QSPI controller */
+} s32k3xx_qspi_optype;
+
+/* Lut commands */
+
+typedef enum
+{
+ QSPI_LUT_INSTR_STOP = (0U << 10U), /* End of sequence */
Review Comment:
please use 2 spaces for indentation and either `u` or `U` across a single file, but not mix
##########
arch/arm/src/s32k3xx/s32k3xx_edma.c:
##########
@@ -0,0 +1,1626 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/s32k3xx_edma.c
+ *
+ * Copyright (C) 2019, 2021 Gregory Nutt. All rights reserved.
+ * Copyright 2022 NXP
+ * Authors: Gregory Nutt <gn...@nuttx.org>
+ * David Sidrane <da...@nscdg.com>
+ * Peter van der Perk <pe...@nxp.com>
+ *
+ * This file was leveraged from the NuttX S32K1 port. Portions of that eDMA
+ * logic derived from NXP sample code which has a compatible BSD 3-clause
+ * license:
+ *
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
Review Comment:
can we use Apache licence?
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h:
##########
@@ -0,0 +1,505 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* QSPI Register Offsets ****************************************************/
+
+#define S32K3XX_QSPI_MCR_OFFSET (0x0000) /* Module Configuration Register (MCR) */
+#define S32K3XX_QSPI_IPCR_OFFSET (0x0008) /* IP Configuration Register (IPCR) */
+#define S32K3XX_QSPI_FLSHCR_OFFSET (0x000c) /* Flash Memory Configuration Register (FLSHCR) */
+#define S32K3XX_QSPI_BUF0CR_OFFSET (0x0010) /* Buffer 0 Configuration Register (BUF0CR) */
+#define S32K3XX_QSPI_BUF1CR_OFFSET (0x0014) /* Buffer 1 Configuration Register (BUF1CR) */
+#define S32K3XX_QSPI_BUF2CR_OFFSET (0x0018) /* Buffer 2 Configuration Register (BUF2CR) */
+#define S32K3XX_QSPI_BUF3CR_OFFSET (0x001c) /* Buffer 3 Configuration Register (BUF3CR) */
+#define S32K3XX_QSPI_BFGENCR_OFFSET (0x0020) /* Buffer Generic Configuration Register (BFGENCR) */
+#define S32K3XX_QSPI_SOCCR_OFFSET (0x0024) /* SOC Configuration Register (SOCCR) */
+#define S32K3XX_QSPI_BUF0IND_OFFSET (0x0030) /* Buffer 0 Top Index Register (BUF0IND) */
+#define S32K3XX_QSPI_BUF1IND_OFFSET (0x0034) /* Buffer 1 Top Index Register (BUF1IND) */
+#define S32K3XX_QSPI_BUF2IND_OFFSET (0x0038) /* Buffer 2 Top Index Register (BUF2IND) */
+#define S32K3XX_QSPI_DLLCRA_OFFSET (0x0060) /* DLL Flash Memory A Configuration Register (DLLCRA) */
+#define S32K3XX_QSPI_SFAR_OFFSET (0x0100) /* Serial Flash Memory Address Register (SFAR) */
+#define S32K3XX_QSPI_SMPR_OFFSET (0x0108) /* Sampling Register (SMPR) */
+#define S32K3XX_QSPI_RBSR_OFFSET (0x010c) /* RX Buffer Status Register (RBSR) */
+#define S32K3XX_QSPI_RBCT_OFFSET (0x0110) /* RX Buffer Control Register (RBCT) */
+#define S32K3XX_QSPI_DLSR_FA_OFFSET (0x0134) /* Data Learning Status Flash Memory A Register (DLSR_FA) */
+#define S32K3XX_QSPI_TBSR_OFFSET (0x0150) /* TX Buffer Status Register (TBSR) */
+#define S32K3XX_QSPI_TBDR_OFFSET (0x0154) /* TX Buffer Data Register (TBDR) */
+#define S32K3XX_QSPI_TBCT_OFFSET (0x0158) /* TX Buffer Control Register (TBCT) */
+#define S32K3XX_QSPI_SR_OFFSET (0x015c) /* Status Register (SR) */
+#define S32K3XX_QSPI_FR_OFFSET (0x0160) /* Flag Register (FR) */
+#define S32K3XX_QSPI_RSER_OFFSET (0x0164) /* Interrupt and DMA Request Select and Enable Register (RSER) */
+#define S32K3XX_QSPI_SPTRCLR_OFFSET (0x016c) /* Sequence Pointer Clear Register (SPTRCLR) */
+#define S32K3XX_QSPI_SFA1AD_OFFSET (0x0180) /* Serial Flash Memory A1 Top Address Register (SFA1AD) */
+#define S32K3XX_QSPI_SFA2AD_OFFSET (0x0184) /* Serial Flash Memory A2 Top Address Register (SFA2AD) */
+#define S32K3XX_QSPI_SFB1AD_OFFSET (0x0188) /* Serial Flash Memory B1 Top Address Register (SFB1AD) */
+#define S32K3XX_QSPI_SFB2AD_OFFSET (0x018c) /* Serial Flash Memory B2 Top Address Register (SFB2AD) */
+
+#define S32K3XX_QSPI_RBDR_OFFSET(n) (0x0200 + ((n) << 2)) /* RX Buffer Data Register (RBDRn, n=0,...,63) */
+
+#define S32K3XX_QSPI_LUTKEY_OFFSET (0x0300) /* LUT Key Register (LUTKEY) */
+#define S32K3XX_QSPI_LCKCR_OFFSET (0x0304) /* LUT Lock Configuration Register (LKCR) */
+#define S32K3XX_QSPI_LUT0_OFFSET (0x0310) /* LUT Register 0 (LUT0) */
+#define S32K3XX_QSPI_LUT1_OFFSET (0x0314) /* LUT Register 1 (LUT1) */
+#define S32K3XX_QSPI_LUT2_OFFSET (0x0318) /* LUT Register 2 (LUT2) */
+#define S32K3XX_QSPI_LUT3_OFFSET (0x031c) /* LUT Register 3 (LUT3) */
+#define S32K3XX_QSPI_LUT4_OFFSET (0x0320) /* LUT Register 4 (LUT4) */
+#define S32K3XX_QSPI_LUT5_OFFSET (0x0324) /* LUT Register 5 (LUT5) */
+#define S32K3XX_QSPI_LUT6_OFFSET (0x0328) /* LUT Register 6 (LUT6) */
+#define S32K3XX_QSPI_LUT7_OFFSET (0x032c) /* LUT Register 7 (LUT7) */
+#define S32K3XX_QSPI_LUT8_OFFSET (0x0330) /* LUT Register 8 (LUT8) */
+#define S32K3XX_QSPI_LUT9_OFFSET (0x0334) /* LUT Register 9 (LUT9) */
+#define S32K3XX_QSPI_LUT10_OFFSET (0x0338) /* LUT Register 10 (LUT10) */
+#define S32K3XX_QSPI_LUT11_OFFSET (0x033c) /* LUT Register 11 (LUT11) */
+#define S32K3XX_QSPI_LUT12_OFFSET (0x0340) /* LUT Register 12 (LUT12) */
+#define S32K3XX_QSPI_LUT13_OFFSET (0x0344) /* LUT Register 13 (LUT13) */
+#define S32K3XX_QSPI_LUT14_OFFSET (0x0348) /* LUT Register 14 (LUT14) */
+#define S32K3XX_QSPI_LUT15_OFFSET (0x034c) /* LUT Register 15 (LUT15) */
+#define S32K3XX_QSPI_LUT16_OFFSET (0x0350) /* LUT Register 16 (LUT16) */
+#define S32K3XX_QSPI_LUT17_OFFSET (0x0354) /* LUT Register 17 (LUT17) */
+#define S32K3XX_QSPI_LUT18_OFFSET (0x0358) /* LUT Register 18 (LUT18) */
+#define S32K3XX_QSPI_LUT19_OFFSET (0x035c) /* LUT Register 19 (LUT19) */
+
+/* QSPI Register Addresses **************************************************/
+
+#define S32K3XX_QSPI_MCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_MCR_OFFSET)
+#define S32K3XX_QSPI_IPCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_IPCR_OFFSET)
+#define S32K3XX_QSPI_FLSHCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FLSHCR_OFFSET)
+#define S32K3XX_QSPI_BUF0CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0CR_OFFSET)
+#define S32K3XX_QSPI_BUF1CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1CR_OFFSET)
+#define S32K3XX_QSPI_BUF2CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2CR_OFFSET)
+#define S32K3XX_QSPI_BUF3CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF3CR_OFFSET)
+#define S32K3XX_QSPI_BFGENCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BFGENCR_OFFSET)
+#define S32K3XX_QSPI_SOCCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SOCCR_OFFSET)
+#define S32K3XX_QSPI_BUF0IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0IND_OFFSET)
+#define S32K3XX_QSPI_BUF1IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1IND_OFFSET)
+#define S32K3XX_QSPI_BUF2IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2IND_OFFSET)
+#define S32K3XX_QSPI_DLLCRA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLLCRA_OFFSET)
+#define S32K3XX_QSPI_SFAR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFAR_OFFSET)
+#define S32K3XX_QSPI_SMPR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SMPR_OFFSET)
+#define S32K3XX_QSPI_RBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBSR_OFFSET)
+#define S32K3XX_QSPI_RBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBCT_OFFSET)
+#define S32K3XX_QSPI_DLSR_FA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLSR_FA_OFFSET)
+#define S32K3XX_QSPI_TBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBSR_OFFSET)
+#define S32K3XX_QSPI_TBDR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBDR_OFFSET)
+#define S32K3XX_QSPI_TBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBCT_OFFSET)
+#define S32K3XX_QSPI_SR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SR_OFFSET)
+#define S32K3XX_QSPI_FR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FR_OFFSET)
+#define S32K3XX_QSPI_RSER (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RSER_OFFSET)
+#define S32K3XX_QSPI_SPTRCLR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SPTRCLR_OFFSET)
+#define S32K3XX_QSPI_SFA1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA1AD_OFFSET)
+#define S32K3XX_QSPI_SFA2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA2AD_OFFSET)
+#define S32K3XX_QSPI_SFB1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB1AD_OFFSET)
+#define S32K3XX_QSPI_SFB2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB2AD_OFFSET)
+#define S32K3XX_QSPI_RBDR(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBDR_OFFSET(n))
+#define S32K3XX_QSPI_LUTKEY (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUTKEY_OFFSET)
+#define S32K3XX_QSPI_LCKCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LCKCR_OFFSET)
+#define S32K3XX_QSPI_LUT0 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET)
+#define S32K3XX_QSPI_LUT1 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT1_OFFSET)
+#define S32K3XX_QSPI_LUT2 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT2_OFFSET)
+#define S32K3XX_QSPI_LUT3 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT3_OFFSET)
+#define S32K3XX_QSPI_LUT4 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT4_OFFSET)
+#define S32K3XX_QSPI_LUT5 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT5_OFFSET)
+#define S32K3XX_QSPI_LUT6 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT6_OFFSET)
+#define S32K3XX_QSPI_LUT7 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT7_OFFSET)
+#define S32K3XX_QSPI_LUT8 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT8_OFFSET)
+#define S32K3XX_QSPI_LUT9 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT9_OFFSET)
+#define S32K3XX_QSPI_LUT10 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT10_OFFSET)
+#define S32K3XX_QSPI_LUT11 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT11_OFFSET)
+#define S32K3XX_QSPI_LUT12 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT12_OFFSET)
+#define S32K3XX_QSPI_LUT13 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT13_OFFSET)
+#define S32K3XX_QSPI_LUT14 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT14_OFFSET)
+#define S32K3XX_QSPI_LUT15 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT15_OFFSET)
+#define S32K3XX_QSPI_LUT16 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT16_OFFSET)
+#define S32K3XX_QSPI_LUT17 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT17_OFFSET)
+#define S32K3XX_QSPI_LUT18 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT18_OFFSET)
+#define S32K3XX_QSPI_LUT19 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT19_OFFSET)
+
+#define S32K3XX_QSPI_LUT(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET + (n*4))
+#define S32K3XX_QSPI_LUT_COUNT 20
+
+/* QSPI Register Bitfield Definitions ***************************************/
+
+/* Module Configuration Register (MCR) */
+
+#define QSPI_MCR_SWRSTSD (1 << 0) /* Bit 0: Software reset for serial flash memory domain (SWRSTSD) */
+#define QSPI_MCR_SWRSTHD (1 << 1) /* Bit 1: Software reset fo AHB domain (SWRSTHD) */
+ /* Bits 2-9: Reserved */
+#define QSPI_MCR_CLR_RXF (1 << 10) /* Bit 10: Clear RX FIFO (CLR_RXF) */
+#define QSPI_MCR_CLR_TXF (1 << 11) /* Bit 11: Clear TX FIFO/buffer (CLR_TXF) */
+ /* Bits 12-13: Reserved */
+#define QSPI_MCR_MDIS (1 << 14) /* Bit 14: Module disable (MDIS) */
+ /* Bits 15-23: Reserved */
+#define QSPI_MCR_DQS_FA_SEL_SHIFT (24) /* Bits 24-25: DQS clock for sampling read data at flash memory A (DQS_FA_SEL) */
+#define QSPI_MCR_DQS_FA_SEL_MASK (0x03 << QSPI_MCR_DQS_FA_SEL_SHIFT)
+#define QSPI_MCR_DQS_FA_SEL_INTERNAL_DQS ((0x00 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+#define QSPI_MCR_DQS_FA_SEL_LOOPBACK ((0x01 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+#define QSPI_MCR_DQS_FA_SEL_LOOPBACK_DQS ((0x02 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+ /* Bits 26-31: Reserved */
+
+/* IP Configuration Register (IPCR) */
+
+#define QSPICR_IDATSZ_SHIFT (0) /* Bits 0-15: IP data transfer size (IDATSZ) */
+#define QSPICR_IDATSZ_MASK (0xffff << QSPICR_IDATSZ_SHIFT)
+#define QSPICR_IDATSZ(n) ((n << QSPICR_IDATSZ_SHIFT) & QSPICR_IDATSZ_MASK)
+ /* Bits 16-23: Reserved */
+#define QSPICR_SEQID_SHIFT (24) /* Bits 24-27: Points to a sequence in the LUT (SEQID) */
+#define QSPICR_SEQID_MASK (0x0f << QSPICR_SEQID_SHIFT)
+#define QSPICR_SEQID(n) ((n << QSPICR_SEQID_SHIFT) & QSPICR_SEQID_MASK)
+ /* Bits 28-31: Reserved */
+
+/* Flash Memory Configuration Register (FLSHCR) */
+
+#define QSPI_FLSHCR_TCSS_SHIFT (0) /* Bits 0-3: Serial flash memory CS setup time (TCSS) */
+#define QSPI_FLSHCR_TCSS_MASK (0x0f << QSPI_FLSHCR_TCSS_SHIFT)
+#define QSPI_FLSHCR_TCSS(n) (n & QSPI_FLSHCR_TCSS_MASK)
+#define QSPI_FLSHCR_TCSH_SHIFT (8) /* Bits 8-11: Serial flash memory CS hold time (TCSH) */
+#define QSPI_FLSHCR_TCSH_MASK (0x0f << QSPI_FLSHCR_TCSH_SHIFT)
+#define QSPI_FLSHCR_TCSH(n) ((n << QSPI_FLSHCR_TCSH_SHIFT) & QSPI_FLSHCR_TCSH_MASK)
+ /* Bits 12-31: Reserved */
+
+/* Buffer n Configuration Register (BUFnCR) */
+
+#define QSPI_BUFCR_MSTRID_SHIFT (0) /* Bits 0-3: Master ID (MSTRID) */
+#define QSPI_BUFCR_MSTRID_MASK (0x0f << QSPI_BUFCR_MSTRID_SHIFT)
+#define QSPI_BUFCR_MSTRID(n) ((n << QSPI_BUFCR_MSTRID_SHIFT) & QSPI_BUFCR_MSTRID_MASK)
+ /* Bits 4-7: Reserved */
+#define QSPI_BUFCR_ADATSZ_SHIFT (8) /* Bits 8-13: AHB data transfer size (ADATSZ) */
+#define QSPI_BUFCR_ADATSZ_MASK (0x3f << QSPI_BUFCR_ADATSZ_SHIFT)
+#define QSPI_BUFCR_ADATSZ(n) ((n << QSPI_BUFCR_ADATSZ_SHIFT) & QSPI_BUFCR_ADATSZ_MASK)
+ /* Bits 14-31: Reserved */
+#define QSPI_BUF3CR_ALLMST (1 << 31) /* Bit 31: All master enable (ALLMST) */
+
+/* Buffer Generic Configuration Register (BFGENCR) */
+
+ /* Bits 0-11: Reserved */
+#define QSPI_BFGENCR_SEQID_SHIFT (12) /* Bits 12-15: Points to a sequence in the LUT (SEQID) */
+#define QSPI_BFGENCR_SEQID_MASK (0x0f << QSPI_BFGENCR_SEQID_SHIFT)
+ /* Bits 16-31: Reserved */
+
+/* SOC Configuration Register (SOCCR) */
+
+#define QSPI_SOCCR_SOCCFG_SHIFT (0) /* Bits 0-31: SOC configuration (SOCCFG) */
+#define QSPI_SOCCR_SOCCFG_MASK (0xffffffff << QSPI_SOCCR_SOCCFG_SHIFT)
+#define QSPI_SOCCR_OBE_PULL_TMG_RLX (1 << 0) /* Bit 0: obe_pull_timing_relax_b*/
+#define QSPI_SOCCR_IBE (1 << 1) /* Bit 1: IBE */
+#define QSPI_SOCCR_OBE (1 << 2) /* Bit 2: OBE */
+#define QSPI_SOCCR_DSE (1 << 3) /* Bit 3: DSE */
+#define QSPI_SOCCR_PUE (1 << 4) /* Bit 4: PUE */
+#define QSPI_SOCCR_PUS (1 << 5) /* Bit 5: PUS */
+#define QSPI_SOCCR_SRE (1 << 6) /* Bit 6: SRE */
+
+/* Buffer n Top Index Register (BUFnIND) */
+
+ /* Bits 0-2: Reserved */
+#define QSPI_BUFIND_TPINDX_SHIFT (3) /* Bits 3-8: Top index of buffer n (TPINDXn) */
+#define QSPI_BUFIND_TPINDX_MASK (0x3f << QSPI_BUFIND_TPINDX_SHIFT)
+ /* Bits 9-31: Reserved */
+
+/* DLL Flash Memory A Configuration Register (DLLCRA) */
+
+#define QSPI_DLLCRA_SLV_UPD (1 << 0) /* Bit 0: Slave update (SLV_UPD) */
+#define QSPI_DLLCRA_SLV_DLL_BYPASS (1 << 1) /* Bit 1: Slave DLL bypass (SLV_DLL_BYPASS) */
+#define QSPI_DLLCRA_SLV_EN (1 << 2) /* Bit 2: Slave enable (SLV_EN) */
+ /* Bits 3-7: Reserved */
+
+#define QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT (8) /* Bits 8-11: Delay elements in each delay tap (SLV_DLY_COARSE) */
+#define QSPI_DLLCRA_SLV_DLY_COARSE_MASK (0x0f << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT)
+#define QSPI_DLLCRA_SLV_DLY_COARSE(n) ((n << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT) & QSPI_DLLCRA_SLV_DLY_COARSE_MASK)
+#define QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT (12) /* Bits 12-14: T/16 offset delay elements in incoming DQS (SLV_DLY_OFFSET) */
+#define QSPI_DLLCRA_SLV_DLY_OFFSET_MASK (0x07 << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT)
+#define QSPI_DLLCRA_SLV_DLY(n) ((n << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT) & QSPI_DLLCRA_SLV_DLY_OFFSET_MASK)
+ /* Bit 15: Reserved */
+#define QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT (16) /* Bits 16-19: Fine offset delay elements in incoming DQS (SLV_FINE_OFFSET) */
+#define QSPI_DLLCRA_SLV_FINE_OFFSET_MASK (0x0f << QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT)
+ /* Bits 20-29: Reserved */
+#define QSPI_DLLCRA_FREQEN (1 << 30) /* Bit 30: Frequency enable (FREQEN) */
+ /* Bit 31: Reserved */
+
+/* Serial Flash Memory Address Register (SFAR) */
+
+#define QSPI_SFAR_SFADR_SHIFT (0) /* Bits 0-31: Serial flash memory address (SFADR) */
+#define QSPI_SFAR_SFADR_MASK (0xffffffff << QSPI_SFAR_SFADR_SHIFT)
+
+/* Sampling Register (SMPR) */
+
+ /* Bits 0-4: Reserved */
+#define QSPI_SMPR_FSPHS (1 << 5) /* Bit 5: Full speed phase selection for SDR instructions (FSPHS) */
+#define QSPI_SMPR_FSDLY (1 << 6) /* Bit 6: Full speed delay section for SDR instructions (FSDLY) */
+ /* Bits 7-23: Reserved */
+#define QSPI_SMPR_DLLFSMPFA_SHIFT (24) /* Bits 24-26: Selects the nth tap provided by slave delay chain for flash memory A (DLLFSMPFA) */
+#define QSPI_SMPR_DLLFSMPFA_MASK (0x07 << QSPI_SMPR_DLLFSMPFA_SHIFT)
+#define QSPI_SMPR_DLLFSMPFA(n) ((n << QSPI_SMPR_DLLFSMPFA_SHIFT) & QSPI_SMPR_DLLFSMPFA_MASK)
+ /* Bits 27-31: Reserved */
+
+/* RX Buffer Status Register (RBSR) */
+
+#define QSPI_RBSR_RDBFL_SHIFT (0) /* Bits 0-7: RX buffer fill level (RDBFL) */
+#define QSPI_RBSR_RDBFL_MASK (0xff << QSPI_RBSR_RDBFL_SHIFT)
+ /* Bits 8-15: Reserved */
+#define QSPI_RBSR_RDCTR_SHIFT (16) /* Bits 16-31: Read counter (RDCTR) */
+#define QSPI_RBSR_RDCTR_MASK (0xffff << QSPI_RBSR_RDCTR_SHIFT)
+
+/* RX Buffer Control Register (RBCT) */
+
+#define QSPI_RBCT_WMRK_SHIFT (0) /* Bits 0-6: RX buffer watermark (WMRK) */
+#define QSPI_RBCT_WMRK_MASK (0x7f << QSPI_RBCT_WMRK_SHIFT)
+#define QSPI_RBCT_WMRK(n) ((n << QSPI_RBCT_WMRK_SHIFT) & QSPI_RBCT_WMRK_MASK)
+ /* Bit 7: Reserved */
+#define QSPI_RBCT_RXBRD (1 << 8) /* Bit 8: RX buffer readout (RXBRD) */
+# define QSPI_RBCT_RXBRD_AHB (0 << 8) /* RX buffer content is read using the AHB bus registers */
+# define QSPI_RBCT_RXBRD_IP (1 << 8) /* RX buffer content is read using the IP bus registers */
+ /* Bits 9-31: Reserved */
+
+/* Data Learning Status Flash Memory A Register (DLSR_FA) */
+
+#define QSPI_DLSR_FA_NEG_EDGE_SHIFT (0) /* Bits 0-7: DLP negative edge match signature for flash memory A (NEG_EDGE) */
+#define QSPI_DLSR_FA_NEG_EDGE_MASK (0xff << QSPI_DLSR_FA_NEG_EDGE_SHIFT)
+#define QSPI_DLSR_FA_POS_EDGE_SHIFT (8) /* Bits 8-15: DLP positive edge match signature for flash memory A (POS_EDGE) */
+#define QSPI_DLSR_FA_POS_EDGE_MASK (0xff << QSPI_DLSR_FA_POS_EDGE_SHIFT)
+ /* Bits 16-30: Reserved */
+#define QSPI_DLSR_FA_DLPFFA (1 << 31) /* Bit 31: Data learning pattern fail (DLPFFA) */
+
+/* TX Buffer Status Register (TBSR) */
+
+#define QSPI_TBSR_TRBLF_SHIFT (0) /* Bits 0-5: TX buffer fill level (TRBFL) */
+#define QSPI_TBSR_TRBLF_MASK (0x3f << QSPI_TBSR_TRBLF_SHIFT)
+ /* Bits 6-15: Reserved */
+#define QSPI_TBSR_TRCTR_SHIFT (16) /* Bits 16-31: Transmit counter (TRCTR) */
+#define QSPI_TBSR_TRCTR_MASK (0xffff << QSPI_TBSR_TRCTR_SHIFT)
+
+/* TX Buffer Data Register (TBDR) */
+
+#define QSPI_TBDR_TXDATA_SHIFT (0) /* Bits 0-31: TX data (TXDATA) */
+#define QSPI_TBDR_TXDATA_MASK (0xffffffff << QSPI_TBDR_TXDATA_SHIFT)
+
+/* TX Buffer Control Register (TBCT) */
+
+#define QSPI_TBCT_WMRK_SHIFT (0) /* Bits 0-4: Watermark for TX buffer (WMRK) */
+#define QSPI_TBCT_WMRK_MASK (0x1f << QSPI_TBCT_WMRK_SHIFT)
+#define QSPI_TBCT_WMRK(n) ((n << QSPI_TBCT_WMRK_SHIFT) & QSPI_TBCT_WMRK_MASK)
+ /* Bits 5-31: Reserved */
+
+/* Status Register (SR) */
+
+#define QSPI_SR_BUSY (1 << 0) /* Bit 0: Module busy (BUSY) */
+#define QSPI_SR_IP_ACC (1 << 1) /* Bit 1: IP access (IP_ACC) */
+#define QSPI_SR_AHB_ACC (1 << 2) /* Bit 2: AHB read access (AHB_ACC) */
+ /* Bits 3-5: Reserved */
+#define QSPI_SR_AHBTRN (1 << 6) /* Bit 6: AHB access transaction pending (AHBTRN) */
+#define QSPI_SR_AHB0NE (1 << 7) /* Bit 7: AHB 0 buffer not empty (AHB0NE) */
+#define QSPI_SR_AHB1NE (1 << 8) /* Bit 8: AHB 1 buffer not empty (AHB1NE) */
+#define QSPI_SR_AHB2NE (1 << 9) /* Bit 9: AHB 2 buffer not empty (AHB2NE) */
+#define QSPI_SR_AHB3NE (1 << 10) /* Bit 10: AHB 3 buffer not empty (AHB3NE) */
+#define QSPI_SR_AHB0FUL (1 << 11) /* Bit 11: AHB 0 buffer full (AHB0FUL) */
+#define QSPI_SR_AHB1FUL (1 << 12) /* Bit 12: AHB 1 buffer full (AHB1FUL) */
+#define QSPI_SR_AHB2FUL (1 << 13) /* Bit 13: AHB 2 buffer full (AHB2FUL) */
+#define QSPI_SR_AHB3FUL (1 << 14) /* Bit 14: AHB 3 buffer full (AHB3FUL) */
+ /* Bit 15: Reserved */
+#define QSPI_SR_RXWE (1 << 16) /* Bit 16: RX buffer watermark exceeded (RXWE) */
+ /* Bits 17-18: Reserved */
+#define QSPI_SR_RXFULL (1 << 19) /* Bit 19: RX buffer full (RXFULL) */
+ /* Bits 20-22: Reserved */
+#define QSPI_SR_RXDMA (1 << 23) /* Bit 23: RX buffer DMA (RXDMA) */
+#define QSPI_SR_TXNE (1 << 24) /* Bit 24: TX buffer not empty (TXNE) */
+#define QSPI_SR_TXWA (1 << 25) /* Bit 25: TX buffer watermark available (TXWA) */
+#define QSPI_SR_TXDMA (1 << 26) /* Bit 26: TX buffer DMA (TXDMA) */
+#define QSPI_SR_TXFUL (1 << 27) /* Bit 27: TX buffer full (TXFULL) */
+ /* Bits 28-31: Reserved */
+
+/* Flag Register (FR) */
+
+#define QSPI_FR_TFF (1 << 0) /* Bit 0: IP command transaction finished flag (TFF) */
+ /* Bits 1-5: Reserved */
+#define QSPI_FR_IPIEF (1 << 6) /* Bit 6: IP command trigger could not be executed error flag (IPIEF) */
+#define QSPI_FR_IPAEF (1 << 7) /* Bit 7: IP command trigger during AHB access error flag (IPAEF) */
+ /* Bits 8-11: Reserved */
+#define QSPI_FR_ABOF (1 << 12) /* Bit 12: AHB buffer overflow flag (ABOF) */
+#define QSPI_FR_AIBSEF (1 << 13) /* Bit 13: AHB illegal burst size error flag (AIBSEF) */
+#define QSPI_FR_AITEF (1 << 14) /* Bit 14: AHB illegal transaction error flag (AITEF) */
+ /* Bit 15: Reserved */
+#define QSPI_FR_RBDF (1 << 16) /* Bit 16: RX buffer drain flag (RBDF) */
+#define QSPI_FR_RBOF (1 << 17) /* Bit 17: RX buffer overflow flag (RBOF) */
+ /* Bits 18-22: Reserved */
+#define QSPI_FR_ILLINE (1 << 23) /* Bit 23: Illegal instruction error flag (ILLINE) */
+ /* Bits 24-25: Reserved */
+#define QSPI_FR_TBUF (1 << 26) /* Bit 26: TX buffer underrun flag (TBUF) */
+#define QSPI_FR_TBFF (1 << 27) /* Bit 27: TX buffer fill flag (TBFF) */
+ /* Bits 28-31: Reserved */
+
+/* Interrupt and DMA Request Select and Enable Register (RSER) */
+
+#define QSPI_RSER_TFIE (1 << 0) /* Bit 0: Transaction finished interrupt enable flag (TFIE) */
+ /* Bits 1-5: Reserved */
+#define QSPI_RSER_IPIEIE (1 << 6) /* Bit 6: IP command trigger during IP access error interrupt enable flag (IPIEIE) */
+#define QSPI_RSER_IPAEIE (1 << 7) /* Bit 7: IP command trigger during AHB read access error interrupt enable flag (IPAEIE) */
+ /* Bits 8-11: Reserved */
+#define QSPI_RSER_ABOIE (1 << 12) /* Bit 12: AHB buffer overflow interrupt enable flag (ABOIE) */
+#define QSPI_RSER_AIBSIE (1 << 13) /* Bit 13: AHB illegal burst size interrupt enable flag (AIBSIE) */
+#define QSPI_RSER_AITIE (1 << 14) /* Bit 14: AHB illegal transaction interrupt enable flag (AITIE) */
+ /* Bit 15: Reserved */
+#define QSPI_RSER_RBDIE (1 << 16) /* Bit 16: RX buffer drain interrupt enable (RBDIE) */
+#define QSPI_RSER_RBOIE (1 << 17) /* Bit 17: RX buffer overflow interrupt enable (RBOIE) */
+ /* Bits 18-20: Reserved */
+#define QSPI_RSER_RBDDE (1 << 21) /* Bit 21: RX buffer drain DMA enable (RBDDE) */
+ /* Bit 22: Reserved */
+#define QSPI_RSER_ILLINIE (1 << 23) /* Bit 23: Illegal instruction error interrupt enable (ILLINIE) */
+ /* Bit 24: Reserved */
+#define QSPI_RSER_TBFDE (1 << 25) /* Bit 25: TX buffer fill DMA enable (TBFDE) */
+#define QSPI_RSER_TBUIE (1 << 26) /* Bit 26: TX buffer underrun interrupt enable flag (TBUIE) */
+#define QSPI_RSER_TBFIE (1 << 27) /* Bit 27: TX buffer fill interrupt enable flag (TBFIE) */
+ /* Bits 28-31: Reserved */
+
+/* Sequence Pointer Clear Register (SPTRCLR) */
+
+#define QSPI_SPTRCLR_BFPTRC (1 << 0) /* Bit 0: Buffer pointer clear (BFPTRC) */
+ /* Bits 1-7: Reserved */
+#define QSPI_SPTRCLR_IPPTRC (1 << 8) /* Bit 8: IP pointer clear (IPPTRC) */
+ /* Bits 9-31: Reserved */
+
+/* Serial Flash Memory An/Bn Top Address Register (SFAnAD/SFBnAD) */
+
+ /* Bits 0-9: Reserved */
+#define QSPI_SFAD_TPAD_SHIFT (10) /* Bits 10-31: Top address for serial flash memory An/Bn (TPADAn/TPADBn) */
+#define QSPI_SFAD_TPAD_MASK (0x3fffff << QSPI_SFAD_TPAD_SHIFT)
+#define QSPI_SFAD_TPAD(n) ((n << QSPI_SFAD_TPAD_SHIFT) & QSPI_SFAD_TPAD_MASK)
+
+/* RX Buffer Data Register (RBDRn, n=0,...,63) */
+
+#define QSPI_RBDR_RXDATA_SHIFT (0) /* Bits 0-31: RX data (RXDATA) */
+#define QSPI_RBDR_RXDATA_MASK (0xffffffff << QSPI_RBDR_RXDATA_SHIFT)
+
+/* LUT Key Register (LUTKEY) */
+
+#define QSPI_LUTKEY_KEY_SHIFT (0) /* Bits 0-31: Key to lock or unlock the LUT (KEY) */
+#define QSPI_LUTKEY_KEY_MASK (0xffffffff << QSPI_LUTKEY_KEY_SHIFT)
+#define QSPI_LUTKEY_KEY (0x5AF05AF0UL)
+
+/* LUT Lock Configuration Register (LKCR) */
+
+#define QSPI_LKCR_LOCK (1 << 0) /* Bit 0: Lock LUT (LOCK) */
+#define QSPI_LKCR_UNLOCK (1 << 1) /* Bit 1: Unlock LUT (UNLOCK) */
+ /* Bits 2-31: Reserved */
+
+/* LUT Register (LUTn) */
+
+#define QSPI_LUT_OPRND0_SHIFT (0) /* Bits 0-7: Operand for INSTR0 (OPRND0) */
+#define QSPI_LUT_OPRND0_MASK (0xff << QSPI_LUT_OPRND0_SHIFT)
+#define QSPI_LUT_OPRND0(n) ((n << QSPI_LUT_OPRND0_SHIFT) & QSPI_LUT_OPRND0_MASK)
+#define QSPI_LUT_PAD0_SHIFT (8) /* Bits 8-9: Pad information for INSTR0 (PAD0) */
+#define QSPI_LUT_PAD0_MASK (0x03 << QSPI_LUT_PAD0_SHIFT)
+# define QSPI_LUT_PAD0_1 (0x00 << QSPI_LUT_PAD0_SHIFT) /* 1 Pad */
+# define QSPI_LUT_PAD0_2 (0x01 << QSPI_LUT_PAD0_SHIFT) /* 2 Pad */
+# define QSPI_LUT_PAD0_4 (0x02 << QSPI_LUT_PAD0_SHIFT) /* 4 Pad */
+
+#define QSPI_LUT_INSTR0_SHIFT (10) /* Bits 10-15: Instruction 0 (INSTR0) */
+#define QSPI_LUT_INSTR0_MASK (0x3f << QSPI_LUT_INSTR0_SHIFT)
+#define QSPI_LUT_INSTR0(n) ((n << QSPI_LUT_INSTR0_SHIFT) & QSPI_LUT_INSTR0_MASK)
+
+#define QSPI_LUT_OPRND1_SHIFT (16) /* Bits 16-23: Operand for INSTR1 (OPRND1) */
+#define QSPI_LUT_OPRND1_MASK (0xff << QSPI_LUT_OPRND1_SHIFT)
+#define QSPI_LUT_OPRND1(n) ((n << QSPI_LUT_OPRND1_SHIFT) & QSPI_LUT_OPRND1_MASK)
+#define QSPI_LUT_PAD1_SHIFT (24) /* Bits 24-25: Pad information for INSTR1 (PAD1) */
+#define QSPI_LUT_PAD1_MASK (0x03 << QSPI_LUT_PAD1_SHIFT)
+# define QSPI_LUT_PAD1_1 (0x00 << QSPI_LUT_PAD1_SHIFT) /* 1 Pad */
+# define QSPI_LUT_PAD1_2 (0x01 << QSPI_LUT_PAD1_SHIFT) /* 2 Pad */
+# define QSPI_LUT_PAD1_4 (0x02 << QSPI_LUT_PAD1_SHIFT) /* 4 Pad */
+
+#define QSPI_LUT_INSTR1_SHIFT (26) /* Bits 26-31: Instruction 1 (INSTR1) */
+#define QSPI_LUT_INSTR1_MASK (0x3f << QSPI_LUT_INSTR1_SHIFT)
+#define QSPI_LUT_INSTR1(n) ((n << QSPI_LUT_INSTR1_SHIFT) & QSPI_LUT_INSTR1_MASK)
+
+/* External Memory Base Address */
+
+#define QSPI_AMBA_BASE 0x68000000
+
+/* flash connection to the QSPI module */
+
+typedef enum
+{
+ QSPI_SIDE_A1 = 0x00u, /* Serial flash connected on side A1 */
Review Comment:
2 spaces
##########
arch/arm/src/s32k3xx/s32k3xx_edma.c:
##########
@@ -0,0 +1,1626 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/s32k3xx_edma.c
+ *
+ * Copyright (C) 2019, 2021 Gregory Nutt. All rights reserved.
+ * Copyright 2022 NXP
+ * Authors: Gregory Nutt <gn...@nuttx.org>
+ * David Sidrane <da...@nscdg.com>
+ * Peter van der Perk <pe...@nxp.com>
+ *
+ * This file was leveraged from the NuttX S32K1 port. Portions of that eDMA
+ * logic derived from NXP sample code which has a compatible BSD 3-clause
+ * license:
+ *
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include <queue.h>
+#include <assert.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/semaphore.h>
+
+#include "arm_internal.h"
+#include "sched/sched.h"
+
+#include "chip.h"
+#include "hardware/s32k3xx_edma.h"
+#include "hardware/s32k3xx_dmamux.h"
+#include "s32k3xx_edma.h"
+#include "s32k3xx_clocknames.h"
+#include "s32k3xx_periphclocks.h"
+
+#ifdef CONFIG_S32K3XX_EDMA
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* TCD Alignment.
+ *
+ * eDMA TCDs must be aligned with the D-Cache line boundaries to facilitate
+ * cache operations on the TCDs when the D-Cache is enabled.
+ *
+ * NOTE: The TCDs are 32-bytes in length. We implicitly assume that the
+ * D-Cache line size is also 32-bits. Otherwise, padding would be required
+ * at the ends of the TCDS and buffers to protect data after the end of from
+ * invalidation.
+ */
+
+#ifdef CONFIG_ARMV7M_DCACHE
+/* Align to the cache line size which we assume is >= 8 */
+
+# define EDMA_ALIGN ARMV7M_DCACHE_LINESIZE
+# define EDMA_ALIGN_MASK (EDMA_ALIGN-1)
Review Comment:
```suggestion
# define EDMA_ALIGN_MASK (EDMA_ALIGN - 1)
```
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h:
##########
@@ -0,0 +1,1433 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define S32K3XX_EDMA_NCHANNELS 32
+
+/* eDMA Register Offsets ****************************************************/
+
+#define S32K3XX_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */
+#define S32K3XX_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */
+#define S32K3XX_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */
+#define S32K3XX_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */
+
+#define S32K3XX_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */
+
+/* eDMA Register Addresses **************************************************/
+
+#define S32K3XX_EDMA_CSR (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CSR_OFFSET)
+#define S32K3XX_EDMA_ES (S32K3XX_EDMA_BASE + S32K3XX_EDMA_ES_OFFSET)
+#define S32K3XX_EDMA_INT (S32K3XX_EDMA_BASE + S32K3XX_EDMA_INT_OFFSET)
+#define S32K3XX_EDMA_HRS (S32K3XX_EDMA_BASE + S32K3XX_EDMA_HRS_OFFSET)
+#define S32K3XX_EDMA_CH_GRPRI(n) (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CH_GRPRI_OFFSET(n))
+
+/* eDMA Transfer Control Descriptor (TCD) Register Offsets ******************/
+
+#define S32K3XX_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH0_CSR_OFFSET (0x000000) /* Channel 0 Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH0_ES_OFFSET (0x000004) /* Channel 0 Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH0_INT_OFFSET (0x000008) /* Channel 0 Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH0_SBR_OFFSET (0x00000c) /* Channel 0 System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH0_PRI_OFFSET (0x000010) /* Channel 0 Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD0_SADDR_OFFSET (0x000020) /* TCD0 Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD0_SOFF_OFFSET (0x000024) /* TCD0 Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD0_ATTR_OFFSET (0x000026) /* TCD0 Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD0_NBYTES_OFFSET (0x000028) /* TCD0 Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET (0x00002c) /* TCD0 Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD0_DADDR_OFFSET (0x000030) /* TCD0 Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD0_DOFF_OFFSET (0x000034) /* TCD0 Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD0_CITER_OFFSET (0x000036) /* TCD0 Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET (0x000038) /* TCD0 Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD0_CSR_OFFSET (0x00003c) /* TCD0 Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD0_BITER_OFFSET (0x00003e) /* TCD0 Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH1_CSR_OFFSET (0x004000) /* Channel 1 Control and Status Register (CH1_CSR) */
+#define S32K3XX_EDMA_CH1_ES_OFFSET (0x004004) /* Channel 1 Error Status Register (CH1_ES) */
+#define S32K3XX_EDMA_CH1_INT_OFFSET (0x004008) /* Channel 1 Interrupt Status Register (CH1_INT) */
+#define S32K3XX_EDMA_CH1_SBR_OFFSET (0x00400c) /* Channel 1 System Bus Register (CH1_SBR) */
+#define S32K3XX_EDMA_CH1_PRI_OFFSET (0x004010) /* Channel 1 Priority Register (CH1_PRI) */
+#define S32K3XX_EDMA_TCD1_SADDR_OFFSET (0x004020) /* TCD1 Source Address Register (TCD1_SADDR) */
+#define S32K3XX_EDMA_TCD1_SOFF_OFFSET (0x004024) /* TCD1 Signed Source Address Offset Register (TCD1_SOFF) */
+#define S32K3XX_EDMA_TCD1_ATTR_OFFSET (0x004026) /* TCD1 Transfer Attributes (TCD1_ATTR) */
+#define S32K3XX_EDMA_TCD1_NBYTES_OFFSET (0x004028) /* TCD1 Transfer Size (TCD1_NBYTES) */
+#define S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET (0x00402c) /* TCD1 Last Source Address Adjustment / Store DADDR Address Register (TCD1_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD1_DADDR_OFFSET (0x004030) /* TCD1 Destination Address Register (TCD1_DADDR) */
+#define S32K3XX_EDMA_TCD1_DOFF_OFFSET (0x004034) /* TCD1 Signed Destination Address Offset Register (TCD1_DOFF) */
+#define S32K3XX_EDMA_TCD1_CITER_OFFSET (0x004036) /* TCD1 Current Major Loop Count Register (TCD1_CITER) */
+#define S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET (0x004038) /* TCD1 Last Destination Address Adjustment / Scatter Gather Address Register (TCD1_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD1_CSR_OFFSET (0x00403c) /* TCD1 Control and Status Register (TCD1_CSR) */
+#define S32K3XX_EDMA_TCD1_BITER_OFFSET (0x00403e) /* TCD1 Beginning Major Loop Count Register (TCD1_BITER) */
+
+#define S32K3XX_EDMA_CH2_CSR_OFFSET (0x008000) /* Channel 2 Control and Status Register (CH2_CSR) */
+#define S32K3XX_EDMA_CH2_ES_OFFSET (0x008004) /* Channel 2 Error Status Register (CH2_ES) */
+#define S32K3XX_EDMA_CH2_INT_OFFSET (0x008008) /* Channel 2 Interrupt Status Register (CH2_INT) */
+#define S32K3XX_EDMA_CH2_SBR_OFFSET (0x00800c) /* Channel 2 System Bus Register (CH2_SBR) */
+#define S32K3XX_EDMA_CH2_PRI_OFFSET (0x008010) /* Channel 2 Priority Register (CH2_PRI) */
+#define S32K3XX_EDMA_TCD2_SADDR_OFFSET (0x008020) /* TCD2 Source Address Register (TCD2_SADDR) */
+#define S32K3XX_EDMA_TCD2_SOFF_OFFSET (0x008024) /* TCD2 Signed Source Address Offset Register (TCD2_SOFF) */
+#define S32K3XX_EDMA_TCD2_ATTR_OFFSET (0x008026) /* TCD2 Transfer Attributes (TCD2_ATTR) */
+#define S32K3XX_EDMA_TCD2_NBYTES_OFFSET (0x008028) /* TCD2 Transfer Size (TCD2_NBYTES) */
+#define S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET (0x00802c) /* TCD2 Last Source Address Adjustment / Store DADDR Address Register (TCD2_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD2_DADDR_OFFSET (0x008030) /* TCD2 Destination Address Register (TCD2_DADDR) */
+#define S32K3XX_EDMA_TCD2_DOFF_OFFSET (0x008034) /* TCD2 Signed Destination Address Offset Register (TCD2_DOFF) */
+#define S32K3XX_EDMA_TCD2_CITER_OFFSET (0x008036) /* TCD2 Current Major Loop Count Register (TCD2_CITER) */
+#define S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET (0x008038) /* TCD2 Last Destination Address Adjustment / Scatter Gather Address Register (TCD2_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD2_CSR_OFFSET (0x00803c) /* TCD2 Control and Status Register (TCD2_CSR) */
+#define S32K3XX_EDMA_TCD2_BITER_OFFSET (0x00803e) /* TCD2 Beginning Major Loop Count Register (TCD2_BITER) */
+
+#define S32K3XX_EDMA_CH3_CSR_OFFSET (0x00c000) /* Channel 3 Control and Status Register (CH3_CSR) */
+#define S32K3XX_EDMA_CH3_ES_OFFSET (0x00c004) /* Channel 3 Error Status Register (CH3_ES) */
+#define S32K3XX_EDMA_CH3_INT_OFFSET (0x00c008) /* Channel 3 Interrupt Status Register (CH3_INT) */
+#define S32K3XX_EDMA_CH3_SBR_OFFSET (0x00c00c) /* Channel 3 System Bus Register (CH3_SBR) */
+#define S32K3XX_EDMA_CH3_PRI_OFFSET (0x00c010) /* Channel 3 Priority Register (CH3_PRI) */
+#define S32K3XX_EDMA_TCD3_SADDR_OFFSET (0x00c020) /* TCD3 Source Address Register (TCD3_SADDR) */
+#define S32K3XX_EDMA_TCD3_SOFF_OFFSET (0x00c024) /* TCD3 Signed Source Address Offset Register (TCD3_SOFF) */
+#define S32K3XX_EDMA_TCD3_ATTR_OFFSET (0x00c026) /* TCD3 Transfer Attributes (TCD3_ATTR) */
+#define S32K3XX_EDMA_TCD3_NBYTES_OFFSET (0x00c028) /* TCD3 Transfer Size (TCD3_NBYTES) */
+#define S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET (0x00c02c) /* TCD3 Last Source Address Adjustment / Store DADDR Address Register (TCD3_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD3_DADDR_OFFSET (0x00c030) /* TCD3 Destination Address Register (TCD3_DADDR) */
+#define S32K3XX_EDMA_TCD3_DOFF_OFFSET (0x00c034) /* TCD3 Signed Destination Address Offset Register (TCD3_DOFF) */
+#define S32K3XX_EDMA_TCD3_CITER_OFFSET (0x00c036) /* TCD3 Current Major Loop Count Register (TCD3_CITER) */
+#define S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET (0x00c038) /* TCD3 Last Destination Address Adjustment / Scatter Gather Address Register (TCD3_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD3_CSR_OFFSET (0x00c03c) /* TCD3 Control and Status Register (TCD3_CSR) */
+#define S32K3XX_EDMA_TCD3_BITER_OFFSET (0x00c03e) /* TCD3 Beginning Major Loop Count Register (TCD3_BITER) */
+
+#define S32K3XX_EDMA_CH4_CSR_OFFSET (0x010000) /* Channel 4 Control and Status Register (CH4_CSR) */
+#define S32K3XX_EDMA_CH4_ES_OFFSET (0x010004) /* Channel 4 Error Status Register (CH4_ES) */
+#define S32K3XX_EDMA_CH4_INT_OFFSET (0x010008) /* Channel 4 Interrupt Status Register (CH4_INT) */
+#define S32K3XX_EDMA_CH4_SBR_OFFSET (0x01000c) /* Channel 4 System Bus Register (CH4_SBR) */
+#define S32K3XX_EDMA_CH4_PRI_OFFSET (0x010010) /* Channel 4 Priority Register (CH4_PRI) */
+#define S32K3XX_EDMA_TCD4_SADDR_OFFSET (0x010020) /* TCD4 Source Address Register (TCD4_SADDR) */
+#define S32K3XX_EDMA_TCD4_SOFF_OFFSET (0x010024) /* TCD4 Signed Source Address Offset Register (TCD4_SOFF) */
+#define S32K3XX_EDMA_TCD4_ATTR_OFFSET (0x010026) /* TCD4 Transfer Attributes (TCD4_ATTR) */
+#define S32K3XX_EDMA_TCD4_NBYTES_OFFSET (0x010028) /* TCD4 Transfer Size (TCD4_NBYTES) */
+#define S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET (0x01002c) /* TCD4 Last Source Address Adjustment / Store DADDR Address Register (TCD4_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD4_DADDR_OFFSET (0x010030) /* TCD4 Destination Address Register (TCD4_DADDR) */
+#define S32K3XX_EDMA_TCD4_DOFF_OFFSET (0x010034) /* TCD4 Signed Destination Address Offset Register (TCD4_DOFF) */
+#define S32K3XX_EDMA_TCD4_CITER_OFFSET (0x010036) /* TCD4 Current Major Loop Count Register (TCD4_CITER) */
+#define S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET (0x010038) /* TCD4 Last Destination Address Adjustment / Scatter Gather Address Register (TCD4_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD4_CSR_OFFSET (0x01003c) /* TCD4 Control and Status Register (TCD4_CSR) */
+#define S32K3XX_EDMA_TCD4_BITER_OFFSET (0x01003e) /* TCD4 Beginning Major Loop Count Register (TCD4_BITER) */
+
+#define S32K3XX_EDMA_CH5_CSR_OFFSET (0x014000) /* Channel 5 Control and Status Register (CH5_CSR) */
+#define S32K3XX_EDMA_CH5_ES_OFFSET (0x014004) /* Channel 5 Error Status Register (CH5_ES) */
+#define S32K3XX_EDMA_CH5_INT_OFFSET (0x014008) /* Channel 5 Interrupt Status Register (CH5_INT) */
+#define S32K3XX_EDMA_CH5_SBR_OFFSET (0x01400c) /* Channel 5 System Bus Register (CH5_SBR) */
+#define S32K3XX_EDMA_CH5_PRI_OFFSET (0x014010) /* Channel 5 Priority Register (CH5_PRI) */
+#define S32K3XX_EDMA_TCD5_SADDR_OFFSET (0x014020) /* TCD5 Source Address Register (TCD5_SADDR) */
+#define S32K3XX_EDMA_TCD5_SOFF_OFFSET (0x014024) /* TCD5 Signed Source Address Offset Register (TCD5_SOFF) */
+#define S32K3XX_EDMA_TCD5_ATTR_OFFSET (0x014026) /* TCD5 Transfer Attributes (TCD5_ATTR) */
+#define S32K3XX_EDMA_TCD5_NBYTES_OFFSET (0x014028) /* TCD5 Transfer Size (TCD5_NBYTES) */
+#define S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET (0x01402c) /* TCD5 Last Source Address Adjustment / Store DADDR Address Register (TCD5_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD5_DADDR_OFFSET (0x014030) /* TCD5 Destination Address Register (TCD5_DADDR) */
+#define S32K3XX_EDMA_TCD5_DOFF_OFFSET (0x014034) /* TCD5 Signed Destination Address Offset Register (TCD5_DOFF) */
+#define S32K3XX_EDMA_TCD5_CITER_OFFSET (0x014036) /* TCD5 Current Major Loop Count Register (TCD5_CITER) */
+#define S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET (0x014038) /* TCD5 Last Destination Address Adjustment / Scatter Gather Address Register (TCD5_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD5_CSR_OFFSET (0x01403c) /* TCD5 Control and Status Register (TCD5_CSR) */
+#define S32K3XX_EDMA_TCD5_BITER_OFFSET (0x01403e) /* TCD5 Beginning Major Loop Count Register (TCD5_BITER) */
+
+#define S32K3XX_EDMA_CH6_CSR_OFFSET (0x018000) /* Channel 6 Control and Status Register (CH6_CSR) */
+#define S32K3XX_EDMA_CH6_ES_OFFSET (0x018004) /* Channel 6 Error Status Register (CH6_ES) */
+#define S32K3XX_EDMA_CH6_INT_OFFSET (0x018008) /* Channel 6 Interrupt Status Register (CH6_INT) */
+#define S32K3XX_EDMA_CH6_SBR_OFFSET (0x01800c) /* Channel 6 System Bus Register (CH6_SBR) */
+#define S32K3XX_EDMA_CH6_PRI_OFFSET (0x018010) /* Channel 6 Priority Register (CH6_PRI) */
+#define S32K3XX_EDMA_TCD6_SADDR_OFFSET (0x018020) /* TCD6 Source Address Register (TCD6_SADDR) */
+#define S32K3XX_EDMA_TCD6_SOFF_OFFSET (0x018024) /* TCD6 Signed Source Address Offset Register (TCD6_SOFF) */
+#define S32K3XX_EDMA_TCD6_ATTR_OFFSET (0x018026) /* TCD6 Transfer Attributes (TCD6_ATTR) */
+#define S32K3XX_EDMA_TCD6_NBYTES_OFFSET (0x018028) /* TCD6 Transfer Size (TCD6_NBYTES) */
+#define S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET (0x01802c) /* TCD6 Last Source Address Adjustment / Store DADDR Address Register (TCD6_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD6_DADDR_OFFSET (0x018030) /* TCD6 Destination Address Register (TCD6_DADDR) */
+#define S32K3XX_EDMA_TCD6_DOFF_OFFSET (0x018034) /* TCD6 Signed Destination Address Offset Register (TCD6_DOFF) */
+#define S32K3XX_EDMA_TCD6_CITER_OFFSET (0x018036) /* TCD6 Current Major Loop Count Register (TCD6_CITER) */
+#define S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET (0x018038) /* TCD6 Last Destination Address Adjustment / Scatter Gather Address Register (TCD6_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD6_CSR_OFFSET (0x01803c) /* TCD6 Control and Status Register (TCD6_CSR) */
+#define S32K3XX_EDMA_TCD6_BITER_OFFSET (0x01803e) /* TCD6 Beginning Major Loop Count Register (TCD6_BITER) */
+
+#define S32K3XX_EDMA_CH7_CSR_OFFSET (0x01c000) /* Channel 7 Control and Status Register (CH7_CSR) */
+#define S32K3XX_EDMA_CH7_ES_OFFSET (0x01c004) /* Channel 7 Error Status Register (CH7_ES) */
+#define S32K3XX_EDMA_CH7_INT_OFFSET (0x01c008) /* Channel 7 Interrupt Status Register (CH7_INT) */
+#define S32K3XX_EDMA_CH7_SBR_OFFSET (0x01c00c) /* Channel 7 System Bus Register (CH7_SBR) */
+#define S32K3XX_EDMA_CH7_PRI_OFFSET (0x01c010) /* Channel 7 Priority Register (CH7_PRI) */
+#define S32K3XX_EDMA_TCD7_SADDR_OFFSET (0x01c020) /* TCD7 Source Address Register (TCD7_SADDR) */
+#define S32K3XX_EDMA_TCD7_SOFF_OFFSET (0x01c024) /* TCD7 Signed Source Address Offset Register (TCD7_SOFF) */
+#define S32K3XX_EDMA_TCD7_ATTR_OFFSET (0x01c026) /* TCD7 Transfer Attributes (TCD7_ATTR) */
+#define S32K3XX_EDMA_TCD7_NBYTES_OFFSET (0x01c028) /* TCD7 Transfer Size (TCD7_NBYTES) */
+#define S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET (0x01c02c) /* TCD7 Last Source Address Adjustment / Store DADDR Address Register (TCD7_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD7_DADDR_OFFSET (0x01c030) /* TCD7 Destination Address Register (TCD7_DADDR) */
+#define S32K3XX_EDMA_TCD7_DOFF_OFFSET (0x01c034) /* TCD7 Signed Destination Address Offset Register (TCD7_DOFF) */
+#define S32K3XX_EDMA_TCD7_CITER_OFFSET (0x01c036) /* TCD7 Current Major Loop Count Register (TCD7_CITER) */
+#define S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET (0x01c038) /* TCD7 Last Destination Address Adjustment / Scatter Gather Address Register (TCD7_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD7_CSR_OFFSET (0x01c03c) /* TCD7 Control and Status Register (TCD7_CSR) */
+#define S32K3XX_EDMA_TCD7_BITER_OFFSET (0x01c03e) /* TCD7 Beginning Major Loop Count Register (TCD7_BITER) */
+
+#define S32K3XX_EDMA_CH8_CSR_OFFSET (0x020000) /* Channel 8 Control and Status Register (CH8_CSR) */
+#define S32K3XX_EDMA_CH8_ES_OFFSET (0x020004) /* Channel 8 Error Status Register (CH8_ES) */
+#define S32K3XX_EDMA_CH8_INT_OFFSET (0x020008) /* Channel 8 Interrupt Status Register (CH8_INT) */
+#define S32K3XX_EDMA_CH8_SBR_OFFSET (0x02000c) /* Channel 8 System Bus Register (CH8_SBR) */
+#define S32K3XX_EDMA_CH8_PRI_OFFSET (0x020010) /* Channel 8 Priority Register (CH8_PRI) */
+#define S32K3XX_EDMA_TCD8_SADDR_OFFSET (0x020020) /* TCD8 Source Address Register (TCD8_SADDR) */
+#define S32K3XX_EDMA_TCD8_SOFF_OFFSET (0x020024) /* TCD8 Signed Source Address Offset Register (TCD8_SOFF) */
+#define S32K3XX_EDMA_TCD8_ATTR_OFFSET (0x020026) /* TCD8 Transfer Attributes (TCD8_ATTR) */
+#define S32K3XX_EDMA_TCD8_NBYTES_OFFSET (0x020028) /* TCD8 Transfer Size (TCD8_NBYTES) */
+#define S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET (0x02002c) /* TCD8 Last Source Address Adjustment / Store DADDR Address Register (TCD8_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD8_DADDR_OFFSET (0x020030) /* TCD8 Destination Address Register (TCD8_DADDR) */
+#define S32K3XX_EDMA_TCD8_DOFF_OFFSET (0x020034) /* TCD8 Signed Destination Address Offset Register (TCD8_DOFF) */
+#define S32K3XX_EDMA_TCD8_CITER_OFFSET (0x020036) /* TCD8 Current Major Loop Count Register (TCD8_CITER) */
+#define S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET (0x020038) /* TCD8 Last Destination Address Adjustment / Scatter Gather Address Register (TCD8_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD8_CSR_OFFSET (0x02003c) /* TCD8 Control and Status Register (TCD8_CSR) */
+#define S32K3XX_EDMA_TCD8_BITER_OFFSET (0x02003e) /* TCD8 Beginning Major Loop Count Register (TCD8_BITER) */
+
+#define S32K3XX_EDMA_CH9_CSR_OFFSET (0x024000) /* Channel 9 Control and Status Register (CH9_CSR) */
+#define S32K3XX_EDMA_CH9_ES_OFFSET (0x024004) /* Channel 9 Error Status Register (CH9_ES) */
+#define S32K3XX_EDMA_CH9_INT_OFFSET (0x024008) /* Channel 9 Interrupt Status Register (CH9_INT) */
+#define S32K3XX_EDMA_CH9_SBR_OFFSET (0x02400c) /* Channel 9 System Bus Register (CH9_SBR) */
+#define S32K3XX_EDMA_CH9_PRI_OFFSET (0x024010) /* Channel 9 Priority Register (CH9_PRI) */
+#define S32K3XX_EDMA_TCD9_SADDR_OFFSET (0x024020) /* TCD9 Source Address Register (TCD9_SADDR) */
+#define S32K3XX_EDMA_TCD9_SOFF_OFFSET (0x024024) /* TCD9 Signed Source Address Offset Register (TCD9_SOFF) */
+#define S32K3XX_EDMA_TCD9_ATTR_OFFSET (0x024026) /* TCD9 Transfer Attributes (TCD9_ATTR) */
+#define S32K3XX_EDMA_TCD9_NBYTES_OFFSET (0x024028) /* TCD9 Transfer Size (TCD9_NBYTES) */
+#define S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET (0x02402c) /* TCD9 Last Source Address Adjustment / Store DADDR Address Register (TCD9_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD9_DADDR_OFFSET (0x024030) /* TCD9 Destination Address Register (TCD9_DADDR) */
+#define S32K3XX_EDMA_TCD9_DOFF_OFFSET (0x024034) /* TCD9 Signed Destination Address Offset Register (TCD9_DOFF) */
+#define S32K3XX_EDMA_TCD9_CITER_OFFSET (0x024036) /* TCD9 Current Major Loop Count Register (TCD9_CITER) */
+#define S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET (0x024038) /* TCD9 Last Destination Address Adjustment / Scatter Gather Address Register (TCD9_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD9_CSR_OFFSET (0x02403c) /* TCD9 Control and Status Register (TCD9_CSR) */
+#define S32K3XX_EDMA_TCD9_BITER_OFFSET (0x02403e) /* TCD9 Beginning Major Loop Count Register (TCD9_BITER) */
+
+#define S32K3XX_EDMA_CH10_CSR_OFFSET (0x028000) /* Channel 10 Control and Status Register (CH10_CSR) */
+#define S32K3XX_EDMA_CH10_ES_OFFSET (0x028004) /* Channel 10 Error Status Register (CH10_ES) */
+#define S32K3XX_EDMA_CH10_INT_OFFSET (0x028008) /* Channel 10 Interrupt Status Register (CH10_INT) */
+#define S32K3XX_EDMA_CH10_SBR_OFFSET (0x02800c) /* Channel 10 System Bus Register (CH10_SBR) */
+#define S32K3XX_EDMA_CH10_PRI_OFFSET (0x028010) /* Channel 10 Priority Register (CH10_PRI) */
+#define S32K3XX_EDMA_TCD10_SADDR_OFFSET (0x028020) /* TCD10 Source Address Register (TCD10_SADDR) */
+#define S32K3XX_EDMA_TCD10_SOFF_OFFSET (0x028024) /* TCD10 Signed Source Address Offset Register (TCD10_SOFF) */
+#define S32K3XX_EDMA_TCD10_ATTR_OFFSET (0x028026) /* TCD10 Transfer Attributes (TCD10_ATTR) */
+#define S32K3XX_EDMA_TCD10_NBYTES_OFFSET (0x028028) /* TCD10 Transfer Size (TCD10_NBYTES) */
+#define S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET (0x02802c) /* TCD10 Last Source Address Adjustment / Store DADDR Address Register (TCD10_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD10_DADDR_OFFSET (0x028030) /* TCD10 Destination Address Register (TCD10_DADDR) */
+#define S32K3XX_EDMA_TCD10_DOFF_OFFSET (0x028034) /* TCD10 Signed Destination Address Offset Register (TCD10_DOFF) */
+#define S32K3XX_EDMA_TCD10_CITER_OFFSET (0x028036) /* TCD10 Current Major Loop Count Register (TCD10_CITER) */
+#define S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET (0x028038) /* TCD10 Last Destination Address Adjustment / Scatter Gather Address Register (TCD10_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD10_CSR_OFFSET (0x02803c) /* TCD10 Control and Status Register (TCD10_CSR) */
+#define S32K3XX_EDMA_TCD10_BITER_OFFSET (0x02803e) /* TCD10 Beginning Major Loop Count Register (TCD10_BITER) */
+#define S32K3XX_EDMA_CH11_CSR_OFFSET (0x02c000) /* Channel 11 Control and Status Register (CH11_CSR) */
+#define S32K3XX_EDMA_CH11_ES_OFFSET (0x02c004) /* Channel 11 Error Status Register (CH11_ES) */
+#define S32K3XX_EDMA_CH11_INT_OFFSET (0x02c008) /* Channel 11 Interrupt Status Register (CH11_INT) */
+#define S32K3XX_EDMA_CH11_SBR_OFFSET (0x02c00c) /* Channel 11 System Bus Register (CH11_SBR) */
+#define S32K3XX_EDMA_CH11_PRI_OFFSET (0x02c010) /* Channel 11 Priority Register (CH11_PRI) */
+#define S32K3XX_EDMA_TCD11_SADDR_OFFSET (0x02c020) /* TCD11 Source Address Register (TCD11_SADDR) */
+#define S32K3XX_EDMA_TCD11_SOFF_OFFSET (0x02c024) /* TCD11 Signed Source Address Offset Register (TCD11_SOFF) */
+#define S32K3XX_EDMA_TCD11_ATTR_OFFSET (0x02c026) /* TCD11 Transfer Attributes (TCD11_ATTR) */
+#define S32K3XX_EDMA_TCD11_NBYTES_OFFSET (0x02c028) /* TCD11 Transfer Size (TCD11_NBYTES) */
+#define S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET (0x02c02c) /* TCD11 Last Source Address Adjustment / Store DADDR Address Register (TCD11_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD11_DADDR_OFFSET (0x02c030) /* TCD11 Destination Address Register (TCD11_DADDR) */
+#define S32K3XX_EDMA_TCD11_DOFF_OFFSET (0x02c034) /* TCD11 Signed Destination Address Offset Register (TCD11_DOFF) */
+#define S32K3XX_EDMA_TCD11_CITER_OFFSET (0x02c036) /* TCD11 Current Major Loop Count Register (TCD11_CITER) */
+#define S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET (0x02c038) /* TCD11 Last Destination Address Adjustment / Scatter Gather Address Register (TCD11_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD11_CSR_OFFSET (0x02c03c) /* TCD11 Control and Status Register (TCD11_CSR) */
+#define S32K3XX_EDMA_TCD11_BITER_OFFSET (0x02c03e) /* TCD11 Beginning Major Loop Count Register (TCD11_BITER) */
+
+#define S32K3XX_EDMA_CH12_CSR_OFFSET (0x200000) /* Channel 12 Control and Status Register (CH12_CSR) */
+#define S32K3XX_EDMA_CH12_ES_OFFSET (0x200004) /* Channel 12 Error Status Register (CH12_ES) */
+#define S32K3XX_EDMA_CH12_INT_OFFSET (0x200008) /* Channel 12 Interrupt Status Register (CH12_INT) */
+#define S32K3XX_EDMA_CH12_SBR_OFFSET (0x20000c) /* Channel 12 System Bus Register (CH12_SBR) */
+#define S32K3XX_EDMA_CH12_PRI_OFFSET (0x200010) /* Channel 12 Priority Register (CH12_PRI) */
+#define S32K3XX_EDMA_TCD12_SADDR_OFFSET (0x200020) /* TCD12 Source Address Register (TCD12_SADDR) */
+#define S32K3XX_EDMA_TCD12_SOFF_OFFSET (0x200024) /* TCD12 Signed Source Address Offset Register (TCD12_SOFF) */
+#define S32K3XX_EDMA_TCD12_ATTR_OFFSET (0x200026) /* TCD12 Transfer Attributes (TCD12_ATTR) */
+#define S32K3XX_EDMA_TCD12_NBYTES_OFFSET (0x200028) /* TCD12 Transfer Size (TCD12_NBYTES) */
+#define S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET (0x20002c) /* TCD12 Last Source Address Adjustment / Store DADDR Address Register (TCD12_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD12_DADDR_OFFSET (0x200030) /* TCD12 Destination Address Register (TCD12_DADDR) */
+#define S32K3XX_EDMA_TCD12_DOFF_OFFSET (0x200034) /* TCD12 Signed Destination Address Offset Register (TCD12_DOFF) */
+#define S32K3XX_EDMA_TCD12_CITER_OFFSET (0x200036) /* TCD12 Current Major Loop Count Register (TCD12_CITER) */
+#define S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET (0x200038) /* TCD12 Last Destination Address Adjustment / Scatter Gather Address Register (TCD12_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD12_CSR_OFFSET (0x20003c) /* TCD12 Control and Status Register (TCD12_CSR) */
+#define S32K3XX_EDMA_TCD12_BITER_OFFSET (0x20003e) /* TCD12 Beginning Major Loop Count Register (TCD12_BITER) */
+
+#define S32K3XX_EDMA_CH13_CSR_OFFSET (0x204000) /* Channel 13 Control and Status Register (CH13_CSR) */
+#define S32K3XX_EDMA_CH13_ES_OFFSET (0x204004) /* Channel 13 Error Status Register (CH13_ES) */
+#define S32K3XX_EDMA_CH13_INT_OFFSET (0x204008) /* Channel 13 Interrupt Status Register (CH13_INT) */
+#define S32K3XX_EDMA_CH13_SBR_OFFSET (0x20400c) /* Channel 13 System Bus Register (CH13_SBR) */
+#define S32K3XX_EDMA_CH13_PRI_OFFSET (0x204010) /* Channel 13 Priority Register (CH13_PRI) */
+#define S32K3XX_EDMA_TCD13_SADDR_OFFSET (0x204020) /* TCD13 Source Address Register (TCD13_SADDR) */
+#define S32K3XX_EDMA_TCD13_SOFF_OFFSET (0x204024) /* TCD13 Signed Source Address Offset Register (TCD13_SOFF) */
+#define S32K3XX_EDMA_TCD13_ATTR_OFFSET (0x204026) /* TCD13 Transfer Attributes (TCD13_ATTR) */
+#define S32K3XX_EDMA_TCD13_NBYTES_OFFSET (0x204028) /* TCD13 Transfer Size (TCD13_NBYTES) */
+#define S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET (0x20402c) /* TCD13 Last Source Address Adjustment / Store DADDR Address Register (TCD13_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD13_DADDR_OFFSET (0x204030) /* TCD13 Destination Address Register (TCD13_DADDR) */
+#define S32K3XX_EDMA_TCD13_DOFF_OFFSET (0x204034) /* TCD13 Signed Destination Address Offset Register (TCD13_DOFF) */
+#define S32K3XX_EDMA_TCD13_CITER_OFFSET (0x204036) /* TCD13 Current Major Loop Count Register (TCD13_CITER) */
+#define S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET (0x204038) /* TCD13 Last Destination Address Adjustment / Scatter Gather Address Register (TCD13_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD13_CSR_OFFSET (0x20403c) /* TCD13 Control and Status Register (TCD13_CSR) */
+#define S32K3XX_EDMA_TCD13_BITER_OFFSET (0x20403e) /* TCD13 Beginning Major Loop Count Register (TCD13_BITER) */
+
+#define S32K3XX_EDMA_CH14_CSR_OFFSET (0x208000) /* Channel 14 Control and Status Register (CH14_CSR) */
+#define S32K3XX_EDMA_CH14_ES_OFFSET (0x208004) /* Channel 14 Error Status Register (CH14_ES) */
+#define S32K3XX_EDMA_CH14_INT_OFFSET (0x208008) /* Channel 14 Interrupt Status Register (CH14_INT) */
+#define S32K3XX_EDMA_CH14_SBR_OFFSET (0x20800c) /* Channel 14 System Bus Register (CH14_SBR) */
+#define S32K3XX_EDMA_CH14_PRI_OFFSET (0x208010) /* Channel 14 Priority Register (CH14_PRI) */
+#define S32K3XX_EDMA_TCD14_SADDR_OFFSET (0x208020) /* TCD14 Source Address Register (TCD14_SADDR) */
+#define S32K3XX_EDMA_TCD14_SOFF_OFFSET (0x208024) /* TCD14 Signed Source Address Offset Register (TCD14_SOFF) */
+#define S32K3XX_EDMA_TCD14_ATTR_OFFSET (0x208026) /* TCD14 Transfer Attributes (TCD14_ATTR) */
+#define S32K3XX_EDMA_TCD14_NBYTES_OFFSET (0x208028) /* TCD14 Transfer Size (TCD14_NBYTES) */
+#define S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET (0x20802c) /* TCD14 Last Source Address Adjustment / Store DADDR Address Register (TCD14_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD14_DADDR_OFFSET (0x208030) /* TCD14 Destination Address Register (TCD14_DADDR) */
+#define S32K3XX_EDMA_TCD14_DOFF_OFFSET (0x208034) /* TCD14 Signed Destination Address Offset Register (TCD14_DOFF) */
+#define S32K3XX_EDMA_TCD14_CITER_OFFSET (0x208036) /* TCD14 Current Major Loop Count Register (TCD14_CITER) */
+#define S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET (0x208038) /* TCD14 Last Destination Address Adjustment / Scatter Gather Address Register (TCD14_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD14_CSR_OFFSET (0x20803c) /* TCD14 Control and Status Register (TCD14_CSR) */
+#define S32K3XX_EDMA_TCD14_BITER_OFFSET (0x20803e) /* TCD14 Beginning Major Loop Count Register (TCD14_BITER) */
+
+#define S32K3XX_EDMA_CH15_CSR_OFFSET (0x20c000) /* Channel 15 Control and Status Register (CH15_CSR) */
+#define S32K3XX_EDMA_CH15_ES_OFFSET (0x20c004) /* Channel 15 Error Status Register (CH15_ES) */
+#define S32K3XX_EDMA_CH15_INT_OFFSET (0x20c008) /* Channel 15 Interrupt Status Register (CH15_INT) */
+#define S32K3XX_EDMA_CH15_SBR_OFFSET (0x20c00c) /* Channel 15 System Bus Register (CH15_SBR) */
+#define S32K3XX_EDMA_CH15_PRI_OFFSET (0x20c010) /* Channel 15 Priority Register (CH15_PRI) */
+#define S32K3XX_EDMA_TCD15_SADDR_OFFSET (0x20c020) /* TCD15 Source Address Register (TCD15_SADDR) */
+#define S32K3XX_EDMA_TCD15_SOFF_OFFSET (0x20c024) /* TCD15 Signed Source Address Offset Register (TCD15_SOFF) */
+#define S32K3XX_EDMA_TCD15_ATTR_OFFSET (0x20c026) /* TCD15 Transfer Attributes (TCD15_ATTR) */
+#define S32K3XX_EDMA_TCD15_NBYTES_OFFSET (0x20c028) /* TCD15 Transfer Size (TCD15_NBYTES) */
+#define S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET (0x20c02c) /* TCD15 Last Source Address Adjustment / Store DADDR Address Register (TCD15_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD15_DADDR_OFFSET (0x20c030) /* TCD15 Destination Address Register (TCD15_DADDR) */
+#define S32K3XX_EDMA_TCD15_DOFF_OFFSET (0x20c034) /* TCD15 Signed Destination Address Offset Register (TCD15_DOFF) */
+#define S32K3XX_EDMA_TCD15_CITER_OFFSET (0x20c036) /* TCD15 Current Major Loop Count Register (TCD15_CITER) */
+#define S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET (0x20c038) /* TCD15 Last Destination Address Adjustment / Scatter Gather Address Register (TCD15_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD15_CSR_OFFSET (0x20c03c) /* TCD15 Control and Status Register (TCD15_CSR) */
+#define S32K3XX_EDMA_TCD15_BITER_OFFSET (0x20c03e) /* TCD15 Beginning Major Loop Count Register (TCD15_BITER) */
+
+#define S32K3XX_EDMA_CH16_CSR_OFFSET (0x210000) /* Channel 16 Control and Status Register (CH16_CSR) */
+#define S32K3XX_EDMA_CH16_ES_OFFSET (0x210004) /* Channel 16 Error Status Register (CH16_ES) */
+#define S32K3XX_EDMA_CH16_INT_OFFSET (0x210008) /* Channel 16 Interrupt Status Register (CH16_INT) */
+#define S32K3XX_EDMA_CH16_SBR_OFFSET (0x21000c) /* Channel 16 System Bus Register (CH16_SBR) */
+#define S32K3XX_EDMA_CH16_PRI_OFFSET (0x210010) /* Channel 16 Priority Register (CH16_PRI) */
+#define S32K3XX_EDMA_TCD16_SADDR_OFFSET (0x210020) /* TCD16 Source Address Register (TCD16_SADDR) */
+#define S32K3XX_EDMA_TCD16_SOFF_OFFSET (0x210024) /* TCD16 Signed Source Address Offset Register (TCD16_SOFF) */
+#define S32K3XX_EDMA_TCD16_ATTR_OFFSET (0x210026) /* TCD16 Transfer Attributes (TCD16_ATTR) */
+#define S32K3XX_EDMA_TCD16_NBYTES_OFFSET (0x210028) /* TCD16 Transfer Size (TCD16_NBYTES) */
+#define S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET (0x21002c) /* TCD16 Last Source Address Adjustment / Store DADDR Address Register (TCD16_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD16_DADDR_OFFSET (0x210030) /* TCD16 Destination Address Register (TCD16_DADDR) */
+#define S32K3XX_EDMA_TCD16_DOFF_OFFSET (0x210034) /* TCD16 Signed Destination Address Offset Register (TCD16_DOFF) */
+#define S32K3XX_EDMA_TCD16_CITER_OFFSET (0x210036) /* TCD16 Current Major Loop Count Register (TCD16_CITER) */
+#define S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET (0x210038) /* TCD16 Last Destination Address Adjustment / Scatter Gather Address Register (TCD16_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD16_CSR_OFFSET (0x21003c) /* TCD16 Control and Status Register (TCD16_CSR) */
+#define S32K3XX_EDMA_TCD16_BITER_OFFSET (0x21003e) /* TCD16 Beginning Major Loop Count Register (TCD16_BITER) */
+
+#define S32K3XX_EDMA_CH17_CSR_OFFSET (0x214000) /* Channel 17 Control and Status Register (CH17_CSR) */
+#define S32K3XX_EDMA_CH17_ES_OFFSET (0x214004) /* Channel 17 Error Status Register (CH17_ES) */
+#define S32K3XX_EDMA_CH17_INT_OFFSET (0x214008) /* Channel 17 Interrupt Status Register (CH17_INT) */
+#define S32K3XX_EDMA_CH17_SBR_OFFSET (0x21400c) /* Channel 17 System Bus Register (CH17_SBR) */
+#define S32K3XX_EDMA_CH17_PRI_OFFSET (0x214010) /* Channel 17 Priority Register (CH17_PRI) */
+#define S32K3XX_EDMA_TCD17_SADDR_OFFSET (0x214020) /* TCD17 Source Address Register (TCD17_SADDR) */
+#define S32K3XX_EDMA_TCD17_SOFF_OFFSET (0x214024) /* TCD17 Signed Source Address Offset Register (TCD17_SOFF) */
+#define S32K3XX_EDMA_TCD17_ATTR_OFFSET (0x214026) /* TCD17 Transfer Attributes (TCD17_ATTR) */
+#define S32K3XX_EDMA_TCD17_NBYTES_OFFSET (0x214028) /* TCD17 Transfer Size (TCD17_NBYTES) */
+#define S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET (0x21402c) /* TCD17 Last Source Address Adjustment / Store DADDR Address Register (TCD17_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD17_DADDR_OFFSET (0x214030) /* TCD17 Destination Address Register (TCD17_DADDR) */
+#define S32K3XX_EDMA_TCD17_DOFF_OFFSET (0x214034) /* TCD17 Signed Destination Address Offset Register (TCD17_DOFF) */
+#define S32K3XX_EDMA_TCD17_CITER_OFFSET (0x214036) /* TCD17 Current Major Loop Count Register (TCD17_CITER) */
+#define S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET (0x214038) /* TCD17 Last Destination Address Adjustment / Scatter Gather Address Register (TCD17_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD17_CSR_OFFSET (0x21403c) /* TCD17 Control and Status Register (TCD17_CSR) */
+#define S32K3XX_EDMA_TCD17_BITER_OFFSET (0x21403e) /* TCD17 Beginning Major Loop Count Register (TCD17_BITER) */
+
+#define S32K3XX_EDMA_CH18_CSR_OFFSET (0x218000) /* Channel 18 Control and Status Register (CH18_CSR) */
+#define S32K3XX_EDMA_CH18_ES_OFFSET (0x218004) /* Channel 18 Error Status Register (CH18_ES) */
+#define S32K3XX_EDMA_CH18_INT_OFFSET (0x218008) /* Channel 18 Interrupt Status Register (CH18_INT) */
+#define S32K3XX_EDMA_CH18_SBR_OFFSET (0x21800c) /* Channel 18 System Bus Register (CH18_SBR) */
+#define S32K3XX_EDMA_CH18_PRI_OFFSET (0x218010) /* Channel 18 Priority Register (CH18_PRI) */
+#define S32K3XX_EDMA_TCD18_SADDR_OFFSET (0x218020) /* TCD18 Source Address Register (TCD18_SADDR) */
+#define S32K3XX_EDMA_TCD18_SOFF_OFFSET (0x218024) /* TCD18 Signed Source Address Offset Register (TCD18_SOFF) */
+#define S32K3XX_EDMA_TCD18_ATTR_OFFSET (0x218026) /* TCD18 Transfer Attributes (TCD18_ATTR) */
+#define S32K3XX_EDMA_TCD18_NBYTES_OFFSET (0x218028) /* TCD18 Transfer Size (TCD18_NBYTES) */
+#define S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET (0x21802c) /* TCD18 Last Source Address Adjustment / Store DADDR Address Register (TCD18_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD18_DADDR_OFFSET (0x218030) /* TCD18 Destination Address Register (TCD18_DADDR) */
+#define S32K3XX_EDMA_TCD18_DOFF_OFFSET (0x218034) /* TCD18 Signed Destination Address Offset Register (TCD18_DOFF) */
+#define S32K3XX_EDMA_TCD18_CITER_OFFSET (0x218036) /* TCD18 Current Major Loop Count Register (TCD18_CITER) */
+#define S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET (0x218038) /* TCD18 Last Destination Address Adjustment / Scatter Gather Address Register (TCD18_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD18_CSR_OFFSET (0x21803c) /* TCD18 Control and Status Register (TCD18_CSR) */
+#define S32K3XX_EDMA_TCD18_BITER_OFFSET (0x21803e) /* TCD18 Beginning Major Loop Count Register (TCD18_BITER) */
+
+#define S32K3XX_EDMA_CH19_CSR_OFFSET (0x21c000) /* Channel 19 Control and Status Register (CH19_CSR) */
+#define S32K3XX_EDMA_CH19_ES_OFFSET (0x21c004) /* Channel 19 Error Status Register (CH19_ES) */
+#define S32K3XX_EDMA_CH19_INT_OFFSET (0x21c008) /* Channel 19 Interrupt Status Register (CH19_INT) */
+#define S32K3XX_EDMA_CH19_SBR_OFFSET (0x21c00c) /* Channel 19 System Bus Register (CH19_SBR) */
+#define S32K3XX_EDMA_CH19_PRI_OFFSET (0x21c010) /* Channel 19 Priority Register (CH19_PRI) */
+#define S32K3XX_EDMA_TCD19_SADDR_OFFSET (0x21c020) /* TCD19 Source Address Register (TCD19_SADDR) */
+#define S32K3XX_EDMA_TCD19_SOFF_OFFSET (0x21c024) /* TCD19 Signed Source Address Offset Register (TCD19_SOFF) */
+#define S32K3XX_EDMA_TCD19_ATTR_OFFSET (0x21c026) /* TCD19 Transfer Attributes (TCD19_ATTR) */
+#define S32K3XX_EDMA_TCD19_NBYTES_OFFSET (0x21c028) /* TCD19 Transfer Size (TCD19_NBYTES) */
+#define S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET (0x21c02c) /* TCD19 Last Source Address Adjustment / Store DADDR Address Register (TCD19_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD19_DADDR_OFFSET (0x21c030) /* TCD19 Destination Address Register (TCD19_DADDR) */
+#define S32K3XX_EDMA_TCD19_DOFF_OFFSET (0x21c034) /* TCD19 Signed Destination Address Offset Register (TCD19_DOFF) */
+#define S32K3XX_EDMA_TCD19_CITER_OFFSET (0x21c036) /* TCD19 Current Major Loop Count Register (TCD19_CITER) */
+#define S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET (0x21c038) /* TCD19 Last Destination Address Adjustment / Scatter Gather Address Register (TCD19_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD19_CSR_OFFSET (0x21c03c) /* TCD19 Control and Status Register (TCD19_CSR) */
+#define S32K3XX_EDMA_TCD19_BITER_OFFSET (0x21c03e) /* TCD19 Beginning Major Loop Count Register (TCD19_BITER) */
+
+#define S32K3XX_EDMA_CH20_CSR_OFFSET (0x220000) /* Channel 20 Control and Status Register (CH20_CSR) */
+#define S32K3XX_EDMA_CH20_ES_OFFSET (0x220004) /* Channel 20 Error Status Register (CH20_ES) */
+#define S32K3XX_EDMA_CH20_INT_OFFSET (0x220008) /* Channel 20 Interrupt Status Register (CH20_INT) */
+#define S32K3XX_EDMA_CH20_SBR_OFFSET (0x22000c) /* Channel 20 System Bus Register (CH20_SBR) */
+#define S32K3XX_EDMA_CH20_PRI_OFFSET (0x220010) /* Channel 20 Priority Register (CH20_PRI) */
+#define S32K3XX_EDMA_TCD20_SADDR_OFFSET (0x220020) /* TCD20 Source Address Register (TCD20_SADDR) */
+#define S32K3XX_EDMA_TCD20_SOFF_OFFSET (0x220024) /* TCD20 Signed Source Address Offset Register (TCD20_SOFF) */
+#define S32K3XX_EDMA_TCD20_ATTR_OFFSET (0x220026) /* TCD20 Transfer Attributes (TCD20_ATTR) */
+#define S32K3XX_EDMA_TCD20_NBYTES_OFFSET (0x220028) /* TCD20 Transfer Size (TCD20_NBYTES) */
+#define S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET (0x22002c) /* TCD20 Last Source Address Adjustment / Store DADDR Address Register (TCD20_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD20_DADDR_OFFSET (0x220030) /* TCD20 Destination Address Register (TCD20_DADDR) */
+#define S32K3XX_EDMA_TCD20_DOFF_OFFSET (0x220034) /* TCD20 Signed Destination Address Offset Register (TCD20_DOFF) */
+#define S32K3XX_EDMA_TCD20_CITER_OFFSET (0x220036) /* TCD20 Current Major Loop Count Register (TCD20_CITER) */
+#define S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET (0x220038) /* TCD20 Last Destination Address Adjustment / Scatter Gather Address Register (TCD20_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD20_CSR_OFFSET (0x22003c) /* TCD20 Control and Status Register (TCD20_CSR) */
+#define S32K3XX_EDMA_TCD20_BITER_OFFSET (0x22003e) /* TCD20 Beginning Major Loop Count Register (TCD20_BITER) */
+
+#define S32K3XX_EDMA_CH21_CSR_OFFSET (0x224000) /* Channel 21 Control and Status Register (CH21_CSR) */
+#define S32K3XX_EDMA_CH21_ES_OFFSET (0x224004) /* Channel 21 Error Status Register (CH21_ES) */
+#define S32K3XX_EDMA_CH21_INT_OFFSET (0x224008) /* Channel 21 Interrupt Status Register (CH21_INT) */
+#define S32K3XX_EDMA_CH21_SBR_OFFSET (0x22400c) /* Channel 21 System Bus Register (CH21_SBR) */
+#define S32K3XX_EDMA_CH21_PRI_OFFSET (0x224010) /* Channel 21 Priority Register (CH21_PRI) */
+#define S32K3XX_EDMA_TCD21_SADDR_OFFSET (0x224020) /* TCD21 Source Address Register (TCD21_SADDR) */
+#define S32K3XX_EDMA_TCD21_SOFF_OFFSET (0x224024) /* TCD21 Signed Source Address Offset Register (TCD21_SOFF) */
+#define S32K3XX_EDMA_TCD21_ATTR_OFFSET (0x224026) /* TCD21 Transfer Attributes (TCD21_ATTR) */
+#define S32K3XX_EDMA_TCD21_NBYTES_OFFSET (0x224028) /* TCD21 Transfer Size (TCD21_NBYTES) */
+#define S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET (0x22402c) /* TCD21 Last Source Address Adjustment / Store DADDR Address Register (TCD21_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD21_DADDR_OFFSET (0x224030) /* TCD21 Destination Address Register (TCD21_DADDR) */
+#define S32K3XX_EDMA_TCD21_DOFF_OFFSET (0x224034) /* TCD21 Signed Destination Address Offset Register (TCD21_DOFF) */
+#define S32K3XX_EDMA_TCD21_CITER_OFFSET (0x224036) /* TCD21 Current Major Loop Count Register (TCD21_CITER) */
+#define S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET (0x224038) /* TCD21 Last Destination Address Adjustment / Scatter Gather Address Register (TCD21_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD21_CSR_OFFSET (0x22403c) /* TCD21 Control and Status Register (TCD21_CSR) */
+#define S32K3XX_EDMA_TCD21_BITER_OFFSET (0x22403e) /* TCD21 Beginning Major Loop Count Register (TCD21_BITER) */
+
+#define S32K3XX_EDMA_CH22_CSR_OFFSET (0x228000) /* Channel 22 Control and Status Register (CH22_CSR) */
+#define S32K3XX_EDMA_CH22_ES_OFFSET (0x228004) /* Channel 22 Error Status Register (CH22_ES) */
+#define S32K3XX_EDMA_CH22_INT_OFFSET (0x228008) /* Channel 22 Interrupt Status Register (CH22_INT) */
+#define S32K3XX_EDMA_CH22_SBR_OFFSET (0x22800c) /* Channel 22 System Bus Register (CH22_SBR) */
+#define S32K3XX_EDMA_CH22_PRI_OFFSET (0x228010) /* Channel 22 Priority Register (CH22_PRI) */
+#define S32K3XX_EDMA_TCD22_SADDR_OFFSET (0x228020) /* TCD22 Source Address Register (TCD22_SADDR) */
+#define S32K3XX_EDMA_TCD22_SOFF_OFFSET (0x228024) /* TCD22 Signed Source Address Offset Register (TCD22_SOFF) */
+#define S32K3XX_EDMA_TCD22_ATTR_OFFSET (0x228026) /* TCD22 Transfer Attributes (TCD22_ATTR) */
+#define S32K3XX_EDMA_TCD22_NBYTES_OFFSET (0x228028) /* TCD22 Transfer Size (TCD22_NBYTES) */
+#define S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET (0x22802c) /* TCD22 Last Source Address Adjustment / Store DADDR Address Register (TCD22_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD22_DADDR_OFFSET (0x228030) /* TCD22 Destination Address Register (TCD22_DADDR) */
+#define S32K3XX_EDMA_TCD22_DOFF_OFFSET (0x228034) /* TCD22 Signed Destination Address Offset Register (TCD22_DOFF) */
+#define S32K3XX_EDMA_TCD22_CITER_OFFSET (0x228036) /* TCD22 Current Major Loop Count Register (TCD22_CITER) */
+#define S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET (0x228038) /* TCD22 Last Destination Address Adjustment / Scatter Gather Address Register (TCD22_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD22_CSR_OFFSET (0x22803c) /* TCD22 Control and Status Register (TCD22_CSR) */
+#define S32K3XX_EDMA_TCD22_BITER_OFFSET (0x22803e) /* TCD22 Beginning Major Loop Count Register (TCD22_BITER) */
+
+#define S32K3XX_EDMA_CH23_CSR_OFFSET (0x22c000) /* Channel 23 Control and Status Register (CH23_CSR) */
+#define S32K3XX_EDMA_CH23_ES_OFFSET (0x22c004) /* Channel 23 Error Status Register (CH23_ES) */
+#define S32K3XX_EDMA_CH23_INT_OFFSET (0x22c008) /* Channel 23 Interrupt Status Register (CH23_INT) */
+#define S32K3XX_EDMA_CH23_SBR_OFFSET (0x22c00c) /* Channel 23 System Bus Register (CH23_SBR) */
+#define S32K3XX_EDMA_CH23_PRI_OFFSET (0x22c010) /* Channel 23 Priority Register (CH23_PRI) */
+#define S32K3XX_EDMA_TCD23_SADDR_OFFSET (0x22c020) /* TCD23 Source Address Register (TCD23_SADDR) */
+#define S32K3XX_EDMA_TCD23_SOFF_OFFSET (0x22c024) /* TCD23 Signed Source Address Offset Register (TCD23_SOFF) */
+#define S32K3XX_EDMA_TCD23_ATTR_OFFSET (0x22c026) /* TCD23 Transfer Attributes (TCD23_ATTR) */
+#define S32K3XX_EDMA_TCD23_NBYTES_OFFSET (0x22c028) /* TCD23 Transfer Size (TCD23_NBYTES) */
+#define S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET (0x22c02c) /* TCD23 Last Source Address Adjustment / Store DADDR Address Register (TCD23_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD23_DADDR_OFFSET (0x22c030) /* TCD23 Destination Address Register (TCD23_DADDR) */
+#define S32K3XX_EDMA_TCD23_DOFF_OFFSET (0x22c034) /* TCD23 Signed Destination Address Offset Register (TCD23_DOFF) */
+#define S32K3XX_EDMA_TCD23_CITER_OFFSET (0x22c036) /* TCD23 Current Major Loop Count Register (TCD23_CITER) */
+#define S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET (0x22c038) /* TCD23 Last Destination Address Adjustment / Scatter Gather Address Register (TCD23_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD23_CSR_OFFSET (0x22c03c) /* TCD23 Control and Status Register (TCD23_CSR) */
+#define S32K3XX_EDMA_TCD23_BITER_OFFSET (0x22c03e) /* TCD23 Beginning Major Loop Count Register (TCD23_BITER) */
+
+#define S32K3XX_EDMA_CH24_CSR_OFFSET (0x230000) /* Channel 24 Control and Status Register (CH24_CSR) */
+#define S32K3XX_EDMA_CH24_ES_OFFSET (0x230004) /* Channel 24 Error Status Register (CH24_ES) */
+#define S32K3XX_EDMA_CH24_INT_OFFSET (0x230008) /* Channel 24 Interrupt Status Register (CH24_INT) */
+#define S32K3XX_EDMA_CH24_SBR_OFFSET (0x23000c) /* Channel 24 System Bus Register (CH24_SBR) */
+#define S32K3XX_EDMA_CH24_PRI_OFFSET (0x230010) /* Channel 24 Priority Register (CH24_PRI) */
+#define S32K3XX_EDMA_TCD24_SADDR_OFFSET (0x230020) /* TCD24 Source Address Register (TCD24_SADDR) */
+#define S32K3XX_EDMA_TCD24_SOFF_OFFSET (0x230024) /* TCD24 Signed Source Address Offset Register (TCD24_SOFF) */
+#define S32K3XX_EDMA_TCD24_ATTR_OFFSET (0x230026) /* TCD24 Transfer Attributes (TCD24_ATTR) */
+#define S32K3XX_EDMA_TCD24_NBYTES_OFFSET (0x230028) /* TCD24 Transfer Size (TCD24_NBYTES) */
+#define S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET (0x23002c) /* TCD24 Last Source Address Adjustment / Store DADDR Address Register (TCD24_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD24_DADDR_OFFSET (0x230030) /* TCD24 Destination Address Register (TCD24_DADDR) */
+#define S32K3XX_EDMA_TCD24_DOFF_OFFSET (0x230034) /* TCD24 Signed Destination Address Offset Register (TCD24_DOFF) */
+#define S32K3XX_EDMA_TCD24_CITER_OFFSET (0x230036) /* TCD24 Current Major Loop Count Register (TCD24_CITER) */
+#define S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET (0x230038) /* TCD24 Last Destination Address Adjustment / Scatter Gather Address Register (TCD24_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD24_CSR_OFFSET (0x23003c) /* TCD24 Control and Status Register (TCD24_CSR) */
+#define S32K3XX_EDMA_TCD24_BITER_OFFSET (0x23003e) /* TCD24 Beginning Major Loop Count Register (TCD24_BITER) */
+
+#define S32K3XX_EDMA_CH25_CSR_OFFSET (0x234000) /* Channel 25 Control and Status Register (CH25_CSR) */
+#define S32K3XX_EDMA_CH25_ES_OFFSET (0x234004) /* Channel 25 Error Status Register (CH25_ES) */
+#define S32K3XX_EDMA_CH25_INT_OFFSET (0x234008) /* Channel 25 Interrupt Status Register (CH25_INT) */
+#define S32K3XX_EDMA_CH25_SBR_OFFSET (0x23400c) /* Channel 25 System Bus Register (CH25_SBR) */
+#define S32K3XX_EDMA_CH25_PRI_OFFSET (0x234010) /* Channel 25 Priority Register (CH25_PRI) */
+#define S32K3XX_EDMA_TCD25_SADDR_OFFSET (0x234020) /* TCD25 Source Address Register (TCD25_SADDR) */
+#define S32K3XX_EDMA_TCD25_SOFF_OFFSET (0x234024) /* TCD25 Signed Source Address Offset Register (TCD25_SOFF) */
+#define S32K3XX_EDMA_TCD25_ATTR_OFFSET (0x234026) /* TCD25 Transfer Attributes (TCD25_ATTR) */
+#define S32K3XX_EDMA_TCD25_NBYTES_OFFSET (0x234028) /* TCD25 Transfer Size (TCD25_NBYTES) */
+#define S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET (0x23402c) /* TCD25 Last Source Address Adjustment / Store DADDR Address Register (TCD25_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD25_DADDR_OFFSET (0x234030) /* TCD25 Destination Address Register (TCD25_DADDR) */
+#define S32K3XX_EDMA_TCD25_DOFF_OFFSET (0x234034) /* TCD25 Signed Destination Address Offset Register (TCD25_DOFF) */
+#define S32K3XX_EDMA_TCD25_CITER_OFFSET (0x234036) /* TCD25 Current Major Loop Count Register (TCD25_CITER) */
+#define S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET (0x234038) /* TCD25 Last Destination Address Adjustment / Scatter Gather Address Register (TCD25_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD25_CSR_OFFSET (0x23403c) /* TCD25 Control and Status Register (TCD25_CSR) */
+#define S32K3XX_EDMA_TCD25_BITER_OFFSET (0x23403e) /* TCD25 Beginning Major Loop Count Register (TCD25_BITER) */
+
+#define S32K3XX_EDMA_CH26_CSR_OFFSET (0x238000) /* Channel 26 Control and Status Register (CH26_CSR) */
+#define S32K3XX_EDMA_CH26_ES_OFFSET (0x238004) /* Channel 26 Error Status Register (CH26_ES) */
+#define S32K3XX_EDMA_CH26_INT_OFFSET (0x238008) /* Channel 26 Interrupt Status Register (CH26_INT) */
+#define S32K3XX_EDMA_CH26_SBR_OFFSET (0x23800c) /* Channel 26 System Bus Register (CH26_SBR) */
+#define S32K3XX_EDMA_CH26_PRI_OFFSET (0x238010) /* Channel 26 Priority Register (CH26_PRI) */
+#define S32K3XX_EDMA_TCD26_SADDR_OFFSET (0x238020) /* TCD26 Source Address Register (TCD26_SADDR) */
+#define S32K3XX_EDMA_TCD26_SOFF_OFFSET (0x238024) /* TCD26 Signed Source Address Offset Register (TCD26_SOFF) */
+#define S32K3XX_EDMA_TCD26_ATTR_OFFSET (0x238026) /* TCD26 Transfer Attributes (TCD26_ATTR) */
+#define S32K3XX_EDMA_TCD26_NBYTES_OFFSET (0x238028) /* TCD26 Transfer Size (TCD26_NBYTES) */
+#define S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET (0x23802c) /* TCD26 Last Source Address Adjustment / Store DADDR Address Register (TCD26_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD26_DADDR_OFFSET (0x238030) /* TCD26 Destination Address Register (TCD26_DADDR) */
+#define S32K3XX_EDMA_TCD26_DOFF_OFFSET (0x238034) /* TCD26 Signed Destination Address Offset Register (TCD26_DOFF) */
+#define S32K3XX_EDMA_TCD26_CITER_OFFSET (0x238036) /* TCD26 Current Major Loop Count Register (TCD26_CITER) */
+#define S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET (0x238038) /* TCD26 Last Destination Address Adjustment / Scatter Gather Address Register (TCD26_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD26_CSR_OFFSET (0x23803c) /* TCD26 Control and Status Register (TCD26_CSR) */
+#define S32K3XX_EDMA_TCD26_BITER_OFFSET (0x23803e) /* TCD26 Beginning Major Loop Count Register (TCD26_BITER) */
+
+#define S32K3XX_EDMA_CH27_CSR_OFFSET (0x23c000) /* Channel 27 Control and Status Register (CH27_CSR) */
+#define S32K3XX_EDMA_CH27_ES_OFFSET (0x23c004) /* Channel 27 Error Status Register (CH27_ES) */
+#define S32K3XX_EDMA_CH27_INT_OFFSET (0x23c008) /* Channel 27 Interrupt Status Register (CH27_INT) */
+#define S32K3XX_EDMA_CH27_SBR_OFFSET (0x23c00c) /* Channel 27 System Bus Register (CH27_SBR) */
+#define S32K3XX_EDMA_CH27_PRI_OFFSET (0x23c010) /* Channel 27 Priority Register (CH27_PRI) */
+#define S32K3XX_EDMA_TCD27_SADDR_OFFSET (0x23c020) /* TCD27 Source Address Register (TCD27_SADDR) */
+#define S32K3XX_EDMA_TCD27_SOFF_OFFSET (0x23c024) /* TCD27 Signed Source Address Offset Register (TCD27_SOFF) */
+#define S32K3XX_EDMA_TCD27_ATTR_OFFSET (0x23c026) /* TCD27 Transfer Attributes (TCD27_ATTR) */
+#define S32K3XX_EDMA_TCD27_NBYTES_OFFSET (0x23c028) /* TCD27 Transfer Size (TCD27_NBYTES) */
+#define S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET (0x23c02c) /* TCD27 Last Source Address Adjustment / Store DADDR Address Register (TCD27_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD27_DADDR_OFFSET (0x23c030) /* TCD27 Destination Address Register (TCD27_DADDR) */
+#define S32K3XX_EDMA_TCD27_DOFF_OFFSET (0x23c034) /* TCD27 Signed Destination Address Offset Register (TCD27_DOFF) */
+#define S32K3XX_EDMA_TCD27_CITER_OFFSET (0x23c036) /* TCD27 Current Major Loop Count Register (TCD27_CITER) */
+#define S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET (0x23c038) /* TCD27 Last Destination Address Adjustment / Scatter Gather Address Register (TCD27_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD27_CSR_OFFSET (0x23c03c) /* TCD27 Control and Status Register (TCD27_CSR) */
+#define S32K3XX_EDMA_TCD27_BITER_OFFSET (0x23c03e) /* TCD27 Beginning Major Loop Count Register (TCD27_BITER) */
+
+#define S32K3XX_EDMA_CH28_CSR_OFFSET (0x240000) /* Channel 28 Control and Status Register (CH28_CSR) */
+#define S32K3XX_EDMA_CH28_ES_OFFSET (0x240004) /* Channel 28 Error Status Register (CH28_ES) */
+#define S32K3XX_EDMA_CH28_INT_OFFSET (0x240008) /* Channel 28 Interrupt Status Register (CH28_INT) */
+#define S32K3XX_EDMA_CH28_SBR_OFFSET (0x24000c) /* Channel 28 System Bus Register (CH28_SBR) */
+#define S32K3XX_EDMA_CH28_PRI_OFFSET (0x240010) /* Channel 28 Priority Register (CH28_PRI) */
+#define S32K3XX_EDMA_TCD28_SADDR_OFFSET (0x240020) /* TCD28 Source Address Register (TCD28_SADDR) */
+#define S32K3XX_EDMA_TCD28_SOFF_OFFSET (0x240024) /* TCD28 Signed Source Address Offset Register (TCD28_SOFF) */
+#define S32K3XX_EDMA_TCD28_ATTR_OFFSET (0x240026) /* TCD28 Transfer Attributes (TCD28_ATTR) */
+#define S32K3XX_EDMA_TCD28_NBYTES_OFFSET (0x240028) /* TCD28 Transfer Size (TCD28_NBYTES) */
+#define S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET (0x24002c) /* TCD28 Last Source Address Adjustment / Store DADDR Address Register (TCD28_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD28_DADDR_OFFSET (0x240030) /* TCD28 Destination Address Register (TCD28_DADDR) */
+#define S32K3XX_EDMA_TCD28_DOFF_OFFSET (0x240034) /* TCD28 Signed Destination Address Offset Register (TCD28_DOFF) */
+#define S32K3XX_EDMA_TCD28_CITER_OFFSET (0x240036) /* TCD28 Current Major Loop Count Register (TCD28_CITER) */
+#define S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET (0x240038) /* TCD28 Last Destination Address Adjustment / Scatter Gather Address Register (TCD28_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD28_CSR_OFFSET (0x24003c) /* TCD28 Control and Status Register (TCD28_CSR) */
+#define S32K3XX_EDMA_TCD28_BITER_OFFSET (0x24003e) /* TCD28 Beginning Major Loop Count Register (TCD28_BITER) */
+
+#define S32K3XX_EDMA_CH29_CSR_OFFSET (0x244000) /* Channel 29 Control and Status Register (CH29_CSR) */
+#define S32K3XX_EDMA_CH29_ES_OFFSET (0x244004) /* Channel 29 Error Status Register (CH29_ES) */
+#define S32K3XX_EDMA_CH29_INT_OFFSET (0x244008) /* Channel 29 Interrupt Status Register (CH29_INT) */
+#define S32K3XX_EDMA_CH29_SBR_OFFSET (0x24400c) /* Channel 29 System Bus Register (CH29_SBR) */
+#define S32K3XX_EDMA_CH29_PRI_OFFSET (0x244010) /* Channel 29 Priority Register (CH29_PRI) */
+#define S32K3XX_EDMA_TCD29_SADDR_OFFSET (0x244020) /* TCD29 Source Address Register (TCD29_SADDR) */
+#define S32K3XX_EDMA_TCD29_SOFF_OFFSET (0x244024) /* TCD29 Signed Source Address Offset Register (TCD29_SOFF) */
+#define S32K3XX_EDMA_TCD29_ATTR_OFFSET (0x244026) /* TCD29 Transfer Attributes (TCD29_ATTR) */
+#define S32K3XX_EDMA_TCD29_NBYTES_OFFSET (0x244028) /* TCD29 Transfer Size (TCD29_NBYTES) */
+#define S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET (0x24402c) /* TCD29 Last Source Address Adjustment / Store DADDR Address Register (TCD29_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD29_DADDR_OFFSET (0x244030) /* TCD29 Destination Address Register (TCD29_DADDR) */
+#define S32K3XX_EDMA_TCD29_DOFF_OFFSET (0x244034) /* TCD29 Signed Destination Address Offset Register (TCD29_DOFF) */
+#define S32K3XX_EDMA_TCD29_CITER_OFFSET (0x244036) /* TCD29 Current Major Loop Count Register (TCD29_CITER) */
+#define S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET (0x244038) /* TCD29 Last Destination Address Adjustment / Scatter Gather Address Register (TCD29_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD29_CSR_OFFSET (0x24403c) /* TCD29 Control and Status Register (TCD29_CSR) */
+#define S32K3XX_EDMA_TCD29_BITER_OFFSET (0x24403e) /* TCD29 Beginning Major Loop Count Register (TCD29_BITER) */
+
+#define S32K3XX_EDMA_CH30_CSR_OFFSET (0x248000) /* Channel 30 Control and Status Register (CH30_CSR) */
+#define S32K3XX_EDMA_CH30_ES_OFFSET (0x248004) /* Channel 30 Error Status Register (CH30_ES) */
+#define S32K3XX_EDMA_CH30_INT_OFFSET (0x248008) /* Channel 30 Interrupt Status Register (CH30_INT) */
+#define S32K3XX_EDMA_CH30_SBR_OFFSET (0x24800c) /* Channel 30 System Bus Register (CH30_SBR) */
+#define S32K3XX_EDMA_CH30_PRI_OFFSET (0x248010) /* Channel 30 Priority Register (CH30_PRI) */
+#define S32K3XX_EDMA_TCD30_SADDR_OFFSET (0x248020) /* TCD30 Source Address Register (TCD30_SADDR) */
+#define S32K3XX_EDMA_TCD30_SOFF_OFFSET (0x248024) /* TCD30 Signed Source Address Offset Register (TCD30_SOFF) */
+#define S32K3XX_EDMA_TCD30_ATTR_OFFSET (0x248026) /* TCD30 Transfer Attributes (TCD30_ATTR) */
+#define S32K3XX_EDMA_TCD30_NBYTES_OFFSET (0x248028) /* TCD30 Transfer Size (TCD30_NBYTES) */
+#define S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET (0x24802c) /* TCD30 Last Source Address Adjustment / Store DADDR Address Register (TCD30_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD30_DADDR_OFFSET (0x248030) /* TCD30 Destination Address Register (TCD30_DADDR) */
+#define S32K3XX_EDMA_TCD30_DOFF_OFFSET (0x248034) /* TCD30 Signed Destination Address Offset Register (TCD30_DOFF) */
+#define S32K3XX_EDMA_TCD30_CITER_OFFSET (0x248036) /* TCD30 Current Major Loop Count Register (TCD30_CITER) */
+#define S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET (0x248038) /* TCD30 Last Destination Address Adjustment / Scatter Gather Address Register (TCD30_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD30_CSR_OFFSET (0x24803c) /* TCD30 Control and Status Register (TCD30_CSR) */
+#define S32K3XX_EDMA_TCD30_BITER_OFFSET (0x24803e) /* TCD30 Beginning Major Loop Count Register (TCD30_BITER) */
+
+#define S32K3XX_EDMA_CH31_CSR_OFFSET (0x24c000) /* Channel 31 Control and Status Register (CH31_CSR) */
+#define S32K3XX_EDMA_CH31_ES_OFFSET (0x24c004) /* Channel 31 Error Status Register (CH31_ES) */
+#define S32K3XX_EDMA_CH31_INT_OFFSET (0x24c008) /* Channel 31 Interrupt Status Register (CH31_INT) */
+#define S32K3XX_EDMA_CH31_SBR_OFFSET (0x24c00c) /* Channel 31 System Bus Register (CH31_SBR) */
+#define S32K3XX_EDMA_CH31_PRI_OFFSET (0x24c010) /* Channel 31 Priority Register (CH31_PRI) */
+#define S32K3XX_EDMA_TCD31_SADDR_OFFSET (0x24c020) /* TCD31 Source Address Register (TCD31_SADDR) */
+#define S32K3XX_EDMA_TCD31_SOFF_OFFSET (0x24c024) /* TCD31 Signed Source Address Offset Register (TCD31_SOFF) */
+#define S32K3XX_EDMA_TCD31_ATTR_OFFSET (0x24c026) /* TCD31 Transfer Attributes (TCD31_ATTR) */
+#define S32K3XX_EDMA_TCD31_NBYTES_OFFSET (0x24c028) /* TCD31 Transfer Size (TCD31_NBYTES) */
+#define S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET (0x24c02c) /* TCD31 Last Source Address Adjustment / Store DADDR Address Register (TCD31_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD31_DADDR_OFFSET (0x24c030) /* TCD31 Destination Address Register (TCD31_DADDR) */
+#define S32K3XX_EDMA_TCD31_DOFF_OFFSET (0x24c034) /* TCD31 Signed Destination Address Offset Register (TCD31_DOFF) */
+#define S32K3XX_EDMA_TCD31_CITER_OFFSET (0x24c036) /* TCD31 Current Major Loop Count Register (TCD31_CITER) */
+#define S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET (0x24c038) /* TCD31 Last Destination Address Adjustment / Scatter Gather Address Register (TCD31_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD31_CSR_OFFSET (0x24c03c) /* TCD31 Control and Status Register (TCD31_CSR) */
+#define S32K3XX_EDMA_TCD31_BITER_OFFSET (0x24c03e) /* TCD31 Beginning Major Loop Count Register (TCD31_BITER) */
+
+/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/
+
+#define S32K3XX_EDMA_CH0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_CSR_OFFSET)
+#define S32K3XX_EDMA_CH0_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_ES_OFFSET)
+#define S32K3XX_EDMA_CH0_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_INT_OFFSET)
+#define S32K3XX_EDMA_CH0_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_SBR_OFFSET)
+#define S32K3XX_EDMA_CH0_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD0_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD0_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD0_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD0_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD0_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD0_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_CSR_OFFSET)
+#define S32K3XX_EDMA_CH1_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_ES_OFFSET)
+#define S32K3XX_EDMA_CH1_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_INT_OFFSET)
+#define S32K3XX_EDMA_CH1_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_SBR_OFFSET)
+#define S32K3XX_EDMA_CH1_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD1_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD1_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD1_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD1_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD1_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD1_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_CSR_OFFSET)
+#define S32K3XX_EDMA_CH2_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_ES_OFFSET)
+#define S32K3XX_EDMA_CH2_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_INT_OFFSET)
+#define S32K3XX_EDMA_CH2_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_SBR_OFFSET)
+#define S32K3XX_EDMA_CH2_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD2_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD2_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD2_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD2_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD2_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD2_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_CSR_OFFSET)
+#define S32K3XX_EDMA_CH3_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_ES_OFFSET)
+#define S32K3XX_EDMA_CH3_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_INT_OFFSET)
+#define S32K3XX_EDMA_CH3_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_SBR_OFFSET)
+#define S32K3XX_EDMA_CH3_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD3_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD3_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD3_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD3_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD3_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD3_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_CSR_OFFSET)
+#define S32K3XX_EDMA_CH4_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_ES_OFFSET)
+#define S32K3XX_EDMA_CH4_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_INT_OFFSET)
+#define S32K3XX_EDMA_CH4_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_SBR_OFFSET)
+#define S32K3XX_EDMA_CH4_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD4_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD4_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD4_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD4_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD4_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD4_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_CSR_OFFSET)
+#define S32K3XX_EDMA_CH5_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_ES_OFFSET)
+#define S32K3XX_EDMA_CH5_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_INT_OFFSET)
+#define S32K3XX_EDMA_CH5_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_SBR_OFFSET)
+#define S32K3XX_EDMA_CH5_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD5_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD5_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD5_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD5_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD5_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD5_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_CSR_OFFSET)
+#define S32K3XX_EDMA_CH6_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_ES_OFFSET)
+#define S32K3XX_EDMA_CH6_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_INT_OFFSET)
+#define S32K3XX_EDMA_CH6_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_SBR_OFFSET)
+#define S32K3XX_EDMA_CH6_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD6_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD6_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD6_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD6_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD6_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD6_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_CSR_OFFSET)
+#define S32K3XX_EDMA_CH7_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_ES_OFFSET)
+#define S32K3XX_EDMA_CH7_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_INT_OFFSET)
+#define S32K3XX_EDMA_CH7_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_SBR_OFFSET)
+#define S32K3XX_EDMA_CH7_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD7_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD7_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD7_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD7_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD7_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD7_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_CSR_OFFSET)
+#define S32K3XX_EDMA_CH8_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_ES_OFFSET)
+#define S32K3XX_EDMA_CH8_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_INT_OFFSET)
+#define S32K3XX_EDMA_CH8_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_SBR_OFFSET)
+#define S32K3XX_EDMA_CH8_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD8_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD8_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD8_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD8_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD8_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD8_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_CSR_OFFSET)
+#define S32K3XX_EDMA_CH9_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_ES_OFFSET)
+#define S32K3XX_EDMA_CH9_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_INT_OFFSET)
+#define S32K3XX_EDMA_CH9_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_SBR_OFFSET)
+#define S32K3XX_EDMA_CH9_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD9_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD9_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD9_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD9_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD9_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD9_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_CSR_OFFSET)
+#define S32K3XX_EDMA_CH10_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_ES_OFFSET)
+#define S32K3XX_EDMA_CH10_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_INT_OFFSET)
+#define S32K3XX_EDMA_CH10_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_SBR_OFFSET)
+#define S32K3XX_EDMA_CH10_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD10_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD10_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD10_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD10_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD10_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD10_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_CSR_OFFSET)
+#define S32K3XX_EDMA_CH11_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_ES_OFFSET)
+#define S32K3XX_EDMA_CH11_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_INT_OFFSET)
+#define S32K3XX_EDMA_CH11_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_SBR_OFFSET)
+#define S32K3XX_EDMA_CH11_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD11_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD11_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD11_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD11_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD11_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD11_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_CSR_OFFSET)
+#define S32K3XX_EDMA_CH12_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_ES_OFFSET)
+#define S32K3XX_EDMA_CH12_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_INT_OFFSET)
+#define S32K3XX_EDMA_CH12_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_SBR_OFFSET)
+#define S32K3XX_EDMA_CH12_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD12_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD12_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD12_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD12_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD12_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD12_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_CSR_OFFSET)
+#define S32K3XX_EDMA_CH13_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_ES_OFFSET)
+#define S32K3XX_EDMA_CH13_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_INT_OFFSET)
+#define S32K3XX_EDMA_CH13_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_SBR_OFFSET)
+#define S32K3XX_EDMA_CH13_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD13_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD13_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD13_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD13_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD13_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD13_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_CSR_OFFSET)
+#define S32K3XX_EDMA_CH14_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_ES_OFFSET)
+#define S32K3XX_EDMA_CH14_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_INT_OFFSET)
+#define S32K3XX_EDMA_CH14_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_SBR_OFFSET)
+#define S32K3XX_EDMA_CH14_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD14_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD14_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD14_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD14_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD14_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD14_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_CSR_OFFSET)
+#define S32K3XX_EDMA_CH15_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_ES_OFFSET)
+#define S32K3XX_EDMA_CH15_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_INT_OFFSET)
+#define S32K3XX_EDMA_CH15_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_SBR_OFFSET)
+#define S32K3XX_EDMA_CH15_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD15_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD15_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD15_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD15_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD15_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD15_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_CSR_OFFSET)
+#define S32K3XX_EDMA_CH16_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_ES_OFFSET)
+#define S32K3XX_EDMA_CH16_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_INT_OFFSET)
+#define S32K3XX_EDMA_CH16_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_SBR_OFFSET)
+#define S32K3XX_EDMA_CH16_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD16_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD16_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD16_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD16_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD16_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD16_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_CSR_OFFSET)
+#define S32K3XX_EDMA_CH17_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_ES_OFFSET)
+#define S32K3XX_EDMA_CH17_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_INT_OFFSET)
+#define S32K3XX_EDMA_CH17_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_SBR_OFFSET)
+#define S32K3XX_EDMA_CH17_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD17_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD17_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD17_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD17_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD17_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD17_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_CSR_OFFSET)
+#define S32K3XX_EDMA_CH18_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_ES_OFFSET)
+#define S32K3XX_EDMA_CH18_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_INT_OFFSET)
+#define S32K3XX_EDMA_CH18_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_SBR_OFFSET)
+#define S32K3XX_EDMA_CH18_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD18_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD18_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD18_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD18_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD18_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD18_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_CSR_OFFSET)
+#define S32K3XX_EDMA_CH19_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_ES_OFFSET)
+#define S32K3XX_EDMA_CH19_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_INT_OFFSET)
+#define S32K3XX_EDMA_CH19_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_SBR_OFFSET)
+#define S32K3XX_EDMA_CH19_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD19_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD19_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD19_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD19_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD19_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD19_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_CSR_OFFSET)
+#define S32K3XX_EDMA_CH20_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_ES_OFFSET)
+#define S32K3XX_EDMA_CH20_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_INT_OFFSET)
+#define S32K3XX_EDMA_CH20_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_SBR_OFFSET)
+#define S32K3XX_EDMA_CH20_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD20_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD20_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD20_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD20_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD20_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD20_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_CSR_OFFSET)
+#define S32K3XX_EDMA_CH21_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_ES_OFFSET)
+#define S32K3XX_EDMA_CH21_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_INT_OFFSET)
+#define S32K3XX_EDMA_CH21_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_SBR_OFFSET)
+#define S32K3XX_EDMA_CH21_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD21_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD21_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD21_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD21_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD21_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD21_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_CSR_OFFSET)
+#define S32K3XX_EDMA_CH22_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_ES_OFFSET)
+#define S32K3XX_EDMA_CH22_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_INT_OFFSET)
+#define S32K3XX_EDMA_CH22_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_SBR_OFFSET)
+#define S32K3XX_EDMA_CH22_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD22_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD22_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD22_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD22_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD22_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD22_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_CSR_OFFSET)
+#define S32K3XX_EDMA_CH23_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_ES_OFFSET)
+#define S32K3XX_EDMA_CH23_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_INT_OFFSET)
+#define S32K3XX_EDMA_CH23_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_SBR_OFFSET)
+#define S32K3XX_EDMA_CH23_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD23_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD23_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD23_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD23_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD23_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD23_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_CSR_OFFSET)
+#define S32K3XX_EDMA_CH24_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_ES_OFFSET)
+#define S32K3XX_EDMA_CH24_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_INT_OFFSET)
+#define S32K3XX_EDMA_CH24_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_SBR_OFFSET)
+#define S32K3XX_EDMA_CH24_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD24_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD24_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD24_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD24_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD24_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD24_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_CSR_OFFSET)
+#define S32K3XX_EDMA_CH25_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_ES_OFFSET)
+#define S32K3XX_EDMA_CH25_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_INT_OFFSET)
+#define S32K3XX_EDMA_CH25_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_SBR_OFFSET)
+#define S32K3XX_EDMA_CH25_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD25_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD25_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD25_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD25_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD25_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD25_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_CSR_OFFSET)
+#define S32K3XX_EDMA_CH26_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_ES_OFFSET)
+#define S32K3XX_EDMA_CH26_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_INT_OFFSET)
+#define S32K3XX_EDMA_CH26_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_SBR_OFFSET)
+#define S32K3XX_EDMA_CH26_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD26_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD26_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD26_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD26_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD26_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD26_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_CSR_OFFSET)
+#define S32K3XX_EDMA_CH27_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_ES_OFFSET)
+#define S32K3XX_EDMA_CH27_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_INT_OFFSET)
+#define S32K3XX_EDMA_CH27_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_SBR_OFFSET)
+#define S32K3XX_EDMA_CH27_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD27_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD27_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD27_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD27_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD27_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD27_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_CSR_OFFSET)
+#define S32K3XX_EDMA_CH28_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_ES_OFFSET)
+#define S32K3XX_EDMA_CH28_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_INT_OFFSET)
+#define S32K3XX_EDMA_CH28_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_SBR_OFFSET)
+#define S32K3XX_EDMA_CH28_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD28_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD28_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD28_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD28_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD28_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD28_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_CSR_OFFSET)
+#define S32K3XX_EDMA_CH29_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_ES_OFFSET)
+#define S32K3XX_EDMA_CH29_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_INT_OFFSET)
+#define S32K3XX_EDMA_CH29_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_SBR_OFFSET)
+#define S32K3XX_EDMA_CH29_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD29_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD29_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD29_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD29_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD29_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD29_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_CSR_OFFSET)
+#define S32K3XX_EDMA_CH30_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_ES_OFFSET)
+#define S32K3XX_EDMA_CH30_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_INT_OFFSET)
+#define S32K3XX_EDMA_CH30_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_SBR_OFFSET)
+#define S32K3XX_EDMA_CH30_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD30_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD30_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD30_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD30_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD30_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD30_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_CSR_OFFSET)
+#define S32K3XX_EDMA_CH31_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_ES_OFFSET)
+#define S32K3XX_EDMA_CH31_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_INT_OFFSET)
+#define S32K3XX_EDMA_CH31_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_SBR_OFFSET)
+#define S32K3XX_EDMA_CH31_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD31_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD31_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD31_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD31_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD31_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD31_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_BITER_OFFSET)
+
+uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
Review Comment:
Please move to C file
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h:
##########
@@ -0,0 +1,204 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_VIRTWRAPPER_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_VIRTWRAPPER_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* VIRTWRAPPER Register Offsets *********************************************/
+
+#define S32K3XX_VIRTWRAPPER_REG_A15_0_OFFSET (0x0000) /* Parameter_n Register (REG_A15_0) */
+#define S32K3XX_VIRTWRAPPER_REG_A31_16_OFFSET (0x0004) /* Parameter_n Register (REG_A31_16) */
+#define S32K3XX_VIRTWRAPPER_REG_A47_32_OFFSET (0x0008) /* Parameter_n Register (REG_A47_32) */
+#define S32K3XX_VIRTWRAPPER_REG_A63_48_OFFSET (0x000c) /* Parameter_n Register (REG_A63_48) */
+#define S32K3XX_VIRTWRAPPER_REG_A79_64_OFFSET (0x0010) /* Parameter_n Register (REG_A79_64) */
+#define S32K3XX_VIRTWRAPPER_REG_A95_80_OFFSET (0x0014) /* Parameter_n Register (REG_A95_80) */
+#define S32K3XX_VIRTWRAPPER_REG_A111_96_OFFSET (0x0018) /* Parameter_n Register (REG_A111_96) */
+#define S32K3XX_VIRTWRAPPER_REG_A127_112_OFFSET (0x001c) /* Parameter_n Register (REG_A127_112) */
+#define S32K3XX_VIRTWRAPPER_REG_A143_128_OFFSET (0x0020) /* Parameter_n Register (REG_A143_128) */
+#define S32K3XX_VIRTWRAPPER_REG_A159_144_OFFSET (0x0024) /* Parameter_n Register (REG_A159_144) */
+#define S32K3XX_VIRTWRAPPER_REG_A175_160_OFFSET (0x0028) /* Parameter_n Register (REG_A175_160) */
+#define S32K3XX_VIRTWRAPPER_REG_A191_176_OFFSET (0x002c) /* Parameter_n Register (REG_A191_176) */
+#define S32K3XX_VIRTWRAPPER_REG_A207_192_OFFSET (0x0030) /* Parameter_n Register (REG_A207_192) */
+#define S32K3XX_VIRTWRAPPER_REG_A223_208_OFFSET (0x0034) /* Parameter_n Register (REG_A223_208) */
+#define S32K3XX_VIRTWRAPPER_REG_A239_224_OFFSET (0x0038) /* Parameter_n Register (REG_A239_224) */
+#define S32K3XX_VIRTWRAPPER_REG_A255_240_OFFSET (0x003c) /* Parameter_n Register (REG_A255_240) */
+#define S32K3XX_VIRTWRAPPER_REG_A271_256_OFFSET (0x0040) /* Parameter_n Register (REG_A271_256) */
+#define S32K3XX_VIRTWRAPPER_REG_A287_272_OFFSET (0x0044) /* Parameter_n Register (REG_A287_272) */
+#define S32K3XX_VIRTWRAPPER_REG_A303_288_OFFSET (0x0048) /* Parameter_n Register (REG_A303_288) */
+#define S32K3XX_VIRTWRAPPER_REG_A319_304_OFFSET (0x004c) /* Parameter_n Register (REG_A319_304) */
+#define S32K3XX_VIRTWRAPPER_REG_A335_320_OFFSET (0x0050) /* Parameter_n Register (REG_A335_320) */
+#define S32K3XX_VIRTWRAPPER_REG_A351_336_OFFSET (0x0054) /* Parameter_n Register (REG_A351_336) */
+#define S32K3XX_VIRTWRAPPER_REG_A367_352_OFFSET (0x0058) /* Parameter_n Register (REG_A367_352) */
+#define S32K3XX_VIRTWRAPPER_REG_A383_368_OFFSET (0x005c) /* Parameter_n Register (REG_A383_368) */
+#define S32K3XX_VIRTWRAPPER_REG_A399_384_OFFSET (0x0060) /* Parameter_n Register (REG_A399_384) */
+#define S32K3XX_VIRTWRAPPER_REG_A415_400_OFFSET (0x0064) /* Parameter_n Register (REG_A415_400) */
+#define S32K3XX_VIRTWRAPPER_REG_A431_416_OFFSET (0x0068) /* Parameter_n Register (REG_A431_416) */
+#define S32K3XX_VIRTWRAPPER_REG_A447_432_OFFSET (0x006c) /* Parameter_n Register (REG_A447_432) */
+#define S32K3XX_VIRTWRAPPER_REG_A463_448_OFFSET (0x0070) /* Parameter_n Register (REG_A463_448) */
+#define S32K3XX_VIRTWRAPPER_REG_A479_464_OFFSET (0x0074) /* Parameter_n Register (REG_A479_464) */
+#define S32K3XX_VIRTWRAPPER_REG_A495_480_OFFSET (0x0078) /* Parameter_n Register (REG_A495_480) */
+#define S32K3XX_VIRTWRAPPER_REG_A511_496_OFFSET (0x007c) /* Parameter_n Register (REG_A511_496) */
+#define S32K3XX_VIRTWRAPPER_REG_B527_512_OFFSET (0x0080) /* Parameter_n Register (REG_B527_512) */
+#define S32K3XX_VIRTWRAPPER_REG_B543_528_OFFSET (0x0084) /* Parameter_n Register (REG_B543_528) */
+#define S32K3XX_VIRTWRAPPER_REG_B559_544_OFFSET (0x0088) /* Parameter_n Register (REG_B559_544) */
+#define S32K3XX_VIRTWRAPPER_REG_B575_560_OFFSET (0x008c) /* Parameter_n Register (REG_B575_560) */
+#define S32K3XX_VIRTWRAPPER_REG_B591_576_OFFSET (0x0090) /* Parameter_n Register (REG_B591_576) */
+#define S32K3XX_VIRTWRAPPER_REG_B607_592_OFFSET (0x0094) /* Parameter_n Register (REG_B607_592) */
+#define S32K3XX_VIRTWRAPPER_REG_B623_608_OFFSET (0x0098) /* Parameter_n Register (REG_B623_608) */
+#define S32K3XX_VIRTWRAPPER_REG_B639_624_OFFSET (0x009c) /* Parameter_n Register (REG_B639_624) */
+#define S32K3XX_VIRTWRAPPER_REG_B655_640_OFFSET (0x00a0) /* Parameter_n Register (REG_B655_640) */
+#define S32K3XX_VIRTWRAPPER_REG_B671_656_OFFSET (0x00a4) /* Parameter_n Register (REG_B671_656) */
+#define S32K3XX_VIRTWRAPPER_REG_B687_672_OFFSET (0x00a8) /* Parameter_n Register (REG_B687_672) */
+#define S32K3XX_VIRTWRAPPER_REG_B703_688_OFFSET (0x00ac) /* Parameter_n Register (REG_B703_688) */
+#define S32K3XX_VIRTWRAPPER_REG_B719_704_OFFSET (0x00b0) /* Parameter_n Register (REG_B719_704) */
+#define S32K3XX_VIRTWRAPPER_REG_B735_720_OFFSET (0x00b4) /* Parameter_n Register (REG_B735_720) */
+#define S32K3XX_VIRTWRAPPER_REG_B751_736_OFFSET (0x00b8) /* Parameter_n Register (REG_B751_736) */
+#define S32K3XX_VIRTWRAPPER_REG_B767_752_OFFSET (0x00bc) /* Parameter_n Register (REG_B767_752) */
+#define S32K3XX_VIRTWRAPPER_REG_B783_768_OFFSET (0x00c0) /* Parameter_n Register (REG_B783_768) */
+#define S32K3XX_VIRTWRAPPER_REG_B799_784_OFFSET (0x00c4) /* Parameter_n Register (REG_B799_784) */
+#define S32K3XX_VIRTWRAPPER_REG_B815_800_OFFSET (0x00c8) /* Parameter_n Register (REG_B815_800) */
+#define S32K3XX_VIRTWRAPPER_REG_B831_816_OFFSET (0x00cc) /* Parameter_n Register (REG_B831_816) */
+#define S32K3XX_VIRTWRAPPER_REG_B847_832_OFFSET (0x00d0) /* Parameter_n Register (REG_B847_832) */
+#define S32K3XX_VIRTWRAPPER_REG_B863_848_OFFSET (0x00d4) /* Parameter_n Register (REG_B863_848) */
+#define S32K3XX_VIRTWRAPPER_REG_B879_864_OFFSET (0x00d8) /* Parameter_n Register (REG_B879_864) */
+#define S32K3XX_VIRTWRAPPER_REG_B895_880_OFFSET (0x00dc) /* Parameter_n Register (REG_B895_880) */
+#define S32K3XX_VIRTWRAPPER_REG_B911_896_OFFSET (0x00e0) /* Parameter_n Register (REG_B911_896) */
+#define S32K3XX_VIRTWRAPPER_REG_B927_912_OFFSET (0x00e4) /* Parameter_n Register (REG_B927_912) */
+#define S32K3XX_VIRTWRAPPER_REG_B943_928_OFFSET (0x00e8) /* Parameter_n Register (REG_B943_928) */
+#define S32K3XX_VIRTWRAPPER_REG_B959_944_OFFSET (0x00ec) /* Parameter_n Register (REG_B959_944) */
+#define S32K3XX_VIRTWRAPPER_REG_B975_960_OFFSET (0x00f0) /* Parameter_n Register (REG_B975_960) */
+#define S32K3XX_VIRTWRAPPER_REG_B991_976_OFFSET (0x00f4) /* Parameter_n Register (REG_B991_976) */
+#define S32K3XX_VIRTWRAPPER_REG_B1007_992_OFFSET (0x00f8) /* Parameter_n Register (REG_B1007_99) */
+#define S32K3XX_VIRTWRAPPER_REG_B1023_1008_OFFSET (0x00fc) /* Parameter_n Register (REG_B1023_1008) */
+#define S32K3XX_VIRTWRAPPER_REG_C1039_1024_OFFSET (0x0100) /* Parameter_n Register (REG_C1039_1024) */
+#define S32K3XX_VIRTWRAPPER_REG_D1055_1040_OFFSET (0x0104) /* Parameter_n Register (REG_D1055_1040) */
+
+/* VIRTWRAPPER Register Addresses *******************************************/
+
+#define S32K3XX_VIRTWRAPPER_REG_A15_0 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A15_0_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A31_16 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A31_16_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A47_32 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A47_32_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A63_48 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A63_48_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A79_64 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A79_64_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A95_80 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A95_80_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A111_96 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A111_96_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A127_112 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A127_112_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A143_128 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A143_128_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A159_144 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A159_144_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A175_160 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A175_160_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A191_176 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A191_176_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A207_192 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A207_192_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A223_208 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A223_208_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A239_224 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A239_224_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A255_240 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A255_240_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A271_256 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A271_256_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A287_272 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A287_272_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A303_288 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A303_288_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A319_304 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A319_304_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A335_320 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A335_320_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A351_336 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A351_336_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A367_352 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A367_352_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A383_368 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A383_368_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A399_384 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A399_384_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A415_400 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A415_400_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A431_416 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A431_416_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A447_432 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A447_432_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A463_448 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A463_448_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A479_464 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A479_464_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A495_480 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A495_480_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A511_496 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_A511_496_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B527_512 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B527_512_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B543_528 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B543_528_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B559_544 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B559_544_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B575_560 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B575_560_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B591_576 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B591_576_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B607_592 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B607_592_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B623_608 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B623_608_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B639_624 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B639_624_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B655_640 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B655_640_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B671_656 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B671_656_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B687_672 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B687_672_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B703_688 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B703_688_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B719_704 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B719_704_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B735_720 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B735_720_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_A751_736 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B751_736_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B767_752 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B767_752_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B783_768 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B783_768_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B799_784 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B799_784_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B815_800 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B815_800_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B831_816 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B831_816_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B847_832 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B847_832_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B863_848 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B863_848_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B879_864 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B879_864_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B895_880 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B895_880_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B911_896 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B911_896_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B927_912 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B927_912_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B943_928 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B943_928_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B959_944 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B959_944_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B975_960 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B975_960_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B991_976 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B991_976_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B1007_992 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B1007_992_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_B1023_1008 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_B1023_1008_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_C1039_1024 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_C1039_1024_OFFSET)
+#define S32K3XX_VIRTWRAPPER_REG_D1055_1040 (S32K3XX_VIRTWRAPPER_OFFSET + S32K3XX_VIRTWRAPPER_REG_D1055_1040_OFFSET)
+
+/* VIRTWRAPPER Register Bitfield Definitions ********************************/
+
+/* Parameter_n Register (REG_Annn_mmm) */
+
+#define VIRTWRAPPER_REG_A_PAD_SHIFT(p) ((p) << 1) /* Bits (2*p)-(2*p+1): PAD_p, p=0..15 */
+#define VIRTWRAPPER_REG_A_PAD_MASK(p) (0x03 << VIRTWRAPPER_REG_A_PAD_SHIFT(p))
+# define VIRTWRAPPER_REG_A_PAD_CORE0(p) (0x00 << VIRTWRAPPER_REG_A_PAD_SHIFT(p)) /* SIUL2_VIRTWRAPPER_PDAC1 (Core 0) */
+# define VIRTWRAPPER_REG_A_PAD_CORE1(p) (0x01 << VIRTWRAPPER_REG_A_PAD_SHIFT(p)) /* SIUL2_VIRTWRAPPER_PDAC2 (Core 1) */
+# define VIRTWRAPPER_REG_A_PAD_SECCORE(p) (0x03 << VIRTWRAPPER_REG_A_PAD_SHIFT(p)) /* SIUL2_VIRTWRAPPER_PDAC0 (Secure Core) */
+
+/* Parameter_n Register (REG_Bnnnn_mmmm) */
+
+#define VIRTWRAPPER_REG_B_INMUX_SHIFT(i) ((i) << 1) /* Bits (2*i)-(2*i+1): INMUX_i, i=0..15 */
+#define VIRTWRAPPER_REG_B_INMUX_MASK(i) (0x03 << VIRTWRAPPER_REG_B_INMUX_SHIFT(i))
+# define VIRTWRAPPER_REG_B_INMUX_CORE0(i) (0x00 << VIRTWRAPPER_REG_B_INMUX_SHIFT(i)) /* SIUL2_VIRTWRAPPER_PDAC1 (Core 0) */
+# define VIRTWRAPPER_REG_B_INMUX_CORE1(i) (0x01 << VIRTWRAPPER_REG_B_INMUX_SHIFT(i)) /* SIUL2_VIRTWRAPPER_PDAC2 (Core 1) */
+# define VIRTWRAPPER_REG_B_INMUX_SECCORE(i) (0x03 << VIRTWRAPPER_REG_B_INMUX_SHIFT(i)) /* SIUL2_VIRTWRAPPER_PDAC0 (Secure Core) */
+
+/* Parameter_n Register (REG_C1039_1024) */
+
+#define VIRTWRAPPER_REG_C_INTC_CTRL_SHIFT (0) /* Bits 0-1: Interrupt register control (INTC_CTRL) */
+#define VIRTWRAPPER_REG_C_INTC_CTRL_MASK (0x03 << VIRTWRAPPER_REG_C_INTC_CTRL_SHIFT)
+ /* Bits 2-31: Reserved */
+
+/* Parameter_n Register (REG_D1055_1040) */
+
+ /* Bits 0-29: Reserved */
+#define VIRTWRAPPER_REG_D_REG_GCR_SHIFT (30) /* Bits 30-31: GCR REgister Of REG_PROT (REG_GCR) */
+#define VIRTWRAPPER_REG_D_REG_GCR_MASK (0x03 << VIRTWRAPPER_REG_D_REG_GCR_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_VIRTWRAPPER_H */
Review Comment:
```suggestion
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_VIRTWRAPPER_H */
```
##########
arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h:
##########
@@ -0,0 +1,505 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* QSPI Register Offsets ****************************************************/
+
+#define S32K3XX_QSPI_MCR_OFFSET (0x0000) /* Module Configuration Register (MCR) */
+#define S32K3XX_QSPI_IPCR_OFFSET (0x0008) /* IP Configuration Register (IPCR) */
+#define S32K3XX_QSPI_FLSHCR_OFFSET (0x000c) /* Flash Memory Configuration Register (FLSHCR) */
+#define S32K3XX_QSPI_BUF0CR_OFFSET (0x0010) /* Buffer 0 Configuration Register (BUF0CR) */
+#define S32K3XX_QSPI_BUF1CR_OFFSET (0x0014) /* Buffer 1 Configuration Register (BUF1CR) */
+#define S32K3XX_QSPI_BUF2CR_OFFSET (0x0018) /* Buffer 2 Configuration Register (BUF2CR) */
+#define S32K3XX_QSPI_BUF3CR_OFFSET (0x001c) /* Buffer 3 Configuration Register (BUF3CR) */
+#define S32K3XX_QSPI_BFGENCR_OFFSET (0x0020) /* Buffer Generic Configuration Register (BFGENCR) */
+#define S32K3XX_QSPI_SOCCR_OFFSET (0x0024) /* SOC Configuration Register (SOCCR) */
+#define S32K3XX_QSPI_BUF0IND_OFFSET (0x0030) /* Buffer 0 Top Index Register (BUF0IND) */
+#define S32K3XX_QSPI_BUF1IND_OFFSET (0x0034) /* Buffer 1 Top Index Register (BUF1IND) */
+#define S32K3XX_QSPI_BUF2IND_OFFSET (0x0038) /* Buffer 2 Top Index Register (BUF2IND) */
+#define S32K3XX_QSPI_DLLCRA_OFFSET (0x0060) /* DLL Flash Memory A Configuration Register (DLLCRA) */
+#define S32K3XX_QSPI_SFAR_OFFSET (0x0100) /* Serial Flash Memory Address Register (SFAR) */
+#define S32K3XX_QSPI_SMPR_OFFSET (0x0108) /* Sampling Register (SMPR) */
+#define S32K3XX_QSPI_RBSR_OFFSET (0x010c) /* RX Buffer Status Register (RBSR) */
+#define S32K3XX_QSPI_RBCT_OFFSET (0x0110) /* RX Buffer Control Register (RBCT) */
+#define S32K3XX_QSPI_DLSR_FA_OFFSET (0x0134) /* Data Learning Status Flash Memory A Register (DLSR_FA) */
+#define S32K3XX_QSPI_TBSR_OFFSET (0x0150) /* TX Buffer Status Register (TBSR) */
+#define S32K3XX_QSPI_TBDR_OFFSET (0x0154) /* TX Buffer Data Register (TBDR) */
+#define S32K3XX_QSPI_TBCT_OFFSET (0x0158) /* TX Buffer Control Register (TBCT) */
+#define S32K3XX_QSPI_SR_OFFSET (0x015c) /* Status Register (SR) */
+#define S32K3XX_QSPI_FR_OFFSET (0x0160) /* Flag Register (FR) */
+#define S32K3XX_QSPI_RSER_OFFSET (0x0164) /* Interrupt and DMA Request Select and Enable Register (RSER) */
+#define S32K3XX_QSPI_SPTRCLR_OFFSET (0x016c) /* Sequence Pointer Clear Register (SPTRCLR) */
+#define S32K3XX_QSPI_SFA1AD_OFFSET (0x0180) /* Serial Flash Memory A1 Top Address Register (SFA1AD) */
+#define S32K3XX_QSPI_SFA2AD_OFFSET (0x0184) /* Serial Flash Memory A2 Top Address Register (SFA2AD) */
+#define S32K3XX_QSPI_SFB1AD_OFFSET (0x0188) /* Serial Flash Memory B1 Top Address Register (SFB1AD) */
+#define S32K3XX_QSPI_SFB2AD_OFFSET (0x018c) /* Serial Flash Memory B2 Top Address Register (SFB2AD) */
+
+#define S32K3XX_QSPI_RBDR_OFFSET(n) (0x0200 + ((n) << 2)) /* RX Buffer Data Register (RBDRn, n=0,...,63) */
+
+#define S32K3XX_QSPI_LUTKEY_OFFSET (0x0300) /* LUT Key Register (LUTKEY) */
+#define S32K3XX_QSPI_LCKCR_OFFSET (0x0304) /* LUT Lock Configuration Register (LKCR) */
+#define S32K3XX_QSPI_LUT0_OFFSET (0x0310) /* LUT Register 0 (LUT0) */
+#define S32K3XX_QSPI_LUT1_OFFSET (0x0314) /* LUT Register 1 (LUT1) */
+#define S32K3XX_QSPI_LUT2_OFFSET (0x0318) /* LUT Register 2 (LUT2) */
+#define S32K3XX_QSPI_LUT3_OFFSET (0x031c) /* LUT Register 3 (LUT3) */
+#define S32K3XX_QSPI_LUT4_OFFSET (0x0320) /* LUT Register 4 (LUT4) */
+#define S32K3XX_QSPI_LUT5_OFFSET (0x0324) /* LUT Register 5 (LUT5) */
+#define S32K3XX_QSPI_LUT6_OFFSET (0x0328) /* LUT Register 6 (LUT6) */
+#define S32K3XX_QSPI_LUT7_OFFSET (0x032c) /* LUT Register 7 (LUT7) */
+#define S32K3XX_QSPI_LUT8_OFFSET (0x0330) /* LUT Register 8 (LUT8) */
+#define S32K3XX_QSPI_LUT9_OFFSET (0x0334) /* LUT Register 9 (LUT9) */
+#define S32K3XX_QSPI_LUT10_OFFSET (0x0338) /* LUT Register 10 (LUT10) */
+#define S32K3XX_QSPI_LUT11_OFFSET (0x033c) /* LUT Register 11 (LUT11) */
+#define S32K3XX_QSPI_LUT12_OFFSET (0x0340) /* LUT Register 12 (LUT12) */
+#define S32K3XX_QSPI_LUT13_OFFSET (0x0344) /* LUT Register 13 (LUT13) */
+#define S32K3XX_QSPI_LUT14_OFFSET (0x0348) /* LUT Register 14 (LUT14) */
+#define S32K3XX_QSPI_LUT15_OFFSET (0x034c) /* LUT Register 15 (LUT15) */
+#define S32K3XX_QSPI_LUT16_OFFSET (0x0350) /* LUT Register 16 (LUT16) */
+#define S32K3XX_QSPI_LUT17_OFFSET (0x0354) /* LUT Register 17 (LUT17) */
+#define S32K3XX_QSPI_LUT18_OFFSET (0x0358) /* LUT Register 18 (LUT18) */
+#define S32K3XX_QSPI_LUT19_OFFSET (0x035c) /* LUT Register 19 (LUT19) */
+
+/* QSPI Register Addresses **************************************************/
+
+#define S32K3XX_QSPI_MCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_MCR_OFFSET)
+#define S32K3XX_QSPI_IPCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_IPCR_OFFSET)
+#define S32K3XX_QSPI_FLSHCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FLSHCR_OFFSET)
+#define S32K3XX_QSPI_BUF0CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0CR_OFFSET)
+#define S32K3XX_QSPI_BUF1CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1CR_OFFSET)
+#define S32K3XX_QSPI_BUF2CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2CR_OFFSET)
+#define S32K3XX_QSPI_BUF3CR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF3CR_OFFSET)
+#define S32K3XX_QSPI_BFGENCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BFGENCR_OFFSET)
+#define S32K3XX_QSPI_SOCCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SOCCR_OFFSET)
+#define S32K3XX_QSPI_BUF0IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF0IND_OFFSET)
+#define S32K3XX_QSPI_BUF1IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF1IND_OFFSET)
+#define S32K3XX_QSPI_BUF2IND (S32K3XX_QSPI_BASE + S32K3XX_QSPI_BUF2IND_OFFSET)
+#define S32K3XX_QSPI_DLLCRA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLLCRA_OFFSET)
+#define S32K3XX_QSPI_SFAR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFAR_OFFSET)
+#define S32K3XX_QSPI_SMPR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SMPR_OFFSET)
+#define S32K3XX_QSPI_RBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBSR_OFFSET)
+#define S32K3XX_QSPI_RBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBCT_OFFSET)
+#define S32K3XX_QSPI_DLSR_FA (S32K3XX_QSPI_BASE + S32K3XX_QSPI_DLSR_FA_OFFSET)
+#define S32K3XX_QSPI_TBSR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBSR_OFFSET)
+#define S32K3XX_QSPI_TBDR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBDR_OFFSET)
+#define S32K3XX_QSPI_TBCT (S32K3XX_QSPI_BASE + S32K3XX_QSPI_TBCT_OFFSET)
+#define S32K3XX_QSPI_SR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SR_OFFSET)
+#define S32K3XX_QSPI_FR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_FR_OFFSET)
+#define S32K3XX_QSPI_RSER (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RSER_OFFSET)
+#define S32K3XX_QSPI_SPTRCLR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SPTRCLR_OFFSET)
+#define S32K3XX_QSPI_SFA1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA1AD_OFFSET)
+#define S32K3XX_QSPI_SFA2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFA2AD_OFFSET)
+#define S32K3XX_QSPI_SFB1AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB1AD_OFFSET)
+#define S32K3XX_QSPI_SFB2AD (S32K3XX_QSPI_BASE + S32K3XX_QSPI_SFB2AD_OFFSET)
+#define S32K3XX_QSPI_RBDR(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_RBDR_OFFSET(n))
+#define S32K3XX_QSPI_LUTKEY (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUTKEY_OFFSET)
+#define S32K3XX_QSPI_LCKCR (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LCKCR_OFFSET)
+#define S32K3XX_QSPI_LUT0 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET)
+#define S32K3XX_QSPI_LUT1 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT1_OFFSET)
+#define S32K3XX_QSPI_LUT2 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT2_OFFSET)
+#define S32K3XX_QSPI_LUT3 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT3_OFFSET)
+#define S32K3XX_QSPI_LUT4 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT4_OFFSET)
+#define S32K3XX_QSPI_LUT5 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT5_OFFSET)
+#define S32K3XX_QSPI_LUT6 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT6_OFFSET)
+#define S32K3XX_QSPI_LUT7 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT7_OFFSET)
+#define S32K3XX_QSPI_LUT8 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT8_OFFSET)
+#define S32K3XX_QSPI_LUT9 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT9_OFFSET)
+#define S32K3XX_QSPI_LUT10 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT10_OFFSET)
+#define S32K3XX_QSPI_LUT11 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT11_OFFSET)
+#define S32K3XX_QSPI_LUT12 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT12_OFFSET)
+#define S32K3XX_QSPI_LUT13 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT13_OFFSET)
+#define S32K3XX_QSPI_LUT14 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT14_OFFSET)
+#define S32K3XX_QSPI_LUT15 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT15_OFFSET)
+#define S32K3XX_QSPI_LUT16 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT16_OFFSET)
+#define S32K3XX_QSPI_LUT17 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT17_OFFSET)
+#define S32K3XX_QSPI_LUT18 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT18_OFFSET)
+#define S32K3XX_QSPI_LUT19 (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT19_OFFSET)
+
+#define S32K3XX_QSPI_LUT(n) (S32K3XX_QSPI_BASE + S32K3XX_QSPI_LUT0_OFFSET + (n*4))
+#define S32K3XX_QSPI_LUT_COUNT 20
+
+/* QSPI Register Bitfield Definitions ***************************************/
+
+/* Module Configuration Register (MCR) */
+
+#define QSPI_MCR_SWRSTSD (1 << 0) /* Bit 0: Software reset for serial flash memory domain (SWRSTSD) */
+#define QSPI_MCR_SWRSTHD (1 << 1) /* Bit 1: Software reset fo AHB domain (SWRSTHD) */
+ /* Bits 2-9: Reserved */
+#define QSPI_MCR_CLR_RXF (1 << 10) /* Bit 10: Clear RX FIFO (CLR_RXF) */
+#define QSPI_MCR_CLR_TXF (1 << 11) /* Bit 11: Clear TX FIFO/buffer (CLR_TXF) */
+ /* Bits 12-13: Reserved */
+#define QSPI_MCR_MDIS (1 << 14) /* Bit 14: Module disable (MDIS) */
+ /* Bits 15-23: Reserved */
+#define QSPI_MCR_DQS_FA_SEL_SHIFT (24) /* Bits 24-25: DQS clock for sampling read data at flash memory A (DQS_FA_SEL) */
+#define QSPI_MCR_DQS_FA_SEL_MASK (0x03 << QSPI_MCR_DQS_FA_SEL_SHIFT)
+#define QSPI_MCR_DQS_FA_SEL_INTERNAL_DQS ((0x00 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+#define QSPI_MCR_DQS_FA_SEL_LOOPBACK ((0x01 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+#define QSPI_MCR_DQS_FA_SEL_LOOPBACK_DQS ((0x02 << QSPI_MCR_DQS_FA_SEL_SHIFT) & QSPI_MCR_DQS_FA_SEL_MASK)
+ /* Bits 26-31: Reserved */
+
+/* IP Configuration Register (IPCR) */
+
+#define QSPICR_IDATSZ_SHIFT (0) /* Bits 0-15: IP data transfer size (IDATSZ) */
+#define QSPICR_IDATSZ_MASK (0xffff << QSPICR_IDATSZ_SHIFT)
+#define QSPICR_IDATSZ(n) ((n << QSPICR_IDATSZ_SHIFT) & QSPICR_IDATSZ_MASK)
+ /* Bits 16-23: Reserved */
+#define QSPICR_SEQID_SHIFT (24) /* Bits 24-27: Points to a sequence in the LUT (SEQID) */
+#define QSPICR_SEQID_MASK (0x0f << QSPICR_SEQID_SHIFT)
+#define QSPICR_SEQID(n) ((n << QSPICR_SEQID_SHIFT) & QSPICR_SEQID_MASK)
+ /* Bits 28-31: Reserved */
+
+/* Flash Memory Configuration Register (FLSHCR) */
+
+#define QSPI_FLSHCR_TCSS_SHIFT (0) /* Bits 0-3: Serial flash memory CS setup time (TCSS) */
+#define QSPI_FLSHCR_TCSS_MASK (0x0f << QSPI_FLSHCR_TCSS_SHIFT)
+#define QSPI_FLSHCR_TCSS(n) (n & QSPI_FLSHCR_TCSS_MASK)
+#define QSPI_FLSHCR_TCSH_SHIFT (8) /* Bits 8-11: Serial flash memory CS hold time (TCSH) */
+#define QSPI_FLSHCR_TCSH_MASK (0x0f << QSPI_FLSHCR_TCSH_SHIFT)
+#define QSPI_FLSHCR_TCSH(n) ((n << QSPI_FLSHCR_TCSH_SHIFT) & QSPI_FLSHCR_TCSH_MASK)
+ /* Bits 12-31: Reserved */
+
+/* Buffer n Configuration Register (BUFnCR) */
+
+#define QSPI_BUFCR_MSTRID_SHIFT (0) /* Bits 0-3: Master ID (MSTRID) */
+#define QSPI_BUFCR_MSTRID_MASK (0x0f << QSPI_BUFCR_MSTRID_SHIFT)
+#define QSPI_BUFCR_MSTRID(n) ((n << QSPI_BUFCR_MSTRID_SHIFT) & QSPI_BUFCR_MSTRID_MASK)
+ /* Bits 4-7: Reserved */
+#define QSPI_BUFCR_ADATSZ_SHIFT (8) /* Bits 8-13: AHB data transfer size (ADATSZ) */
+#define QSPI_BUFCR_ADATSZ_MASK (0x3f << QSPI_BUFCR_ADATSZ_SHIFT)
+#define QSPI_BUFCR_ADATSZ(n) ((n << QSPI_BUFCR_ADATSZ_SHIFT) & QSPI_BUFCR_ADATSZ_MASK)
+ /* Bits 14-31: Reserved */
+#define QSPI_BUF3CR_ALLMST (1 << 31) /* Bit 31: All master enable (ALLMST) */
+
+/* Buffer Generic Configuration Register (BFGENCR) */
+
+ /* Bits 0-11: Reserved */
+#define QSPI_BFGENCR_SEQID_SHIFT (12) /* Bits 12-15: Points to a sequence in the LUT (SEQID) */
+#define QSPI_BFGENCR_SEQID_MASK (0x0f << QSPI_BFGENCR_SEQID_SHIFT)
+ /* Bits 16-31: Reserved */
+
+/* SOC Configuration Register (SOCCR) */
+
+#define QSPI_SOCCR_SOCCFG_SHIFT (0) /* Bits 0-31: SOC configuration (SOCCFG) */
+#define QSPI_SOCCR_SOCCFG_MASK (0xffffffff << QSPI_SOCCR_SOCCFG_SHIFT)
+#define QSPI_SOCCR_OBE_PULL_TMG_RLX (1 << 0) /* Bit 0: obe_pull_timing_relax_b*/
+#define QSPI_SOCCR_IBE (1 << 1) /* Bit 1: IBE */
+#define QSPI_SOCCR_OBE (1 << 2) /* Bit 2: OBE */
+#define QSPI_SOCCR_DSE (1 << 3) /* Bit 3: DSE */
+#define QSPI_SOCCR_PUE (1 << 4) /* Bit 4: PUE */
+#define QSPI_SOCCR_PUS (1 << 5) /* Bit 5: PUS */
+#define QSPI_SOCCR_SRE (1 << 6) /* Bit 6: SRE */
+
+/* Buffer n Top Index Register (BUFnIND) */
+
+ /* Bits 0-2: Reserved */
+#define QSPI_BUFIND_TPINDX_SHIFT (3) /* Bits 3-8: Top index of buffer n (TPINDXn) */
+#define QSPI_BUFIND_TPINDX_MASK (0x3f << QSPI_BUFIND_TPINDX_SHIFT)
+ /* Bits 9-31: Reserved */
+
+/* DLL Flash Memory A Configuration Register (DLLCRA) */
+
+#define QSPI_DLLCRA_SLV_UPD (1 << 0) /* Bit 0: Slave update (SLV_UPD) */
+#define QSPI_DLLCRA_SLV_DLL_BYPASS (1 << 1) /* Bit 1: Slave DLL bypass (SLV_DLL_BYPASS) */
+#define QSPI_DLLCRA_SLV_EN (1 << 2) /* Bit 2: Slave enable (SLV_EN) */
+ /* Bits 3-7: Reserved */
+
+#define QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT (8) /* Bits 8-11: Delay elements in each delay tap (SLV_DLY_COARSE) */
+#define QSPI_DLLCRA_SLV_DLY_COARSE_MASK (0x0f << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT)
+#define QSPI_DLLCRA_SLV_DLY_COARSE(n) ((n << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT) & QSPI_DLLCRA_SLV_DLY_COARSE_MASK)
+#define QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT (12) /* Bits 12-14: T/16 offset delay elements in incoming DQS (SLV_DLY_OFFSET) */
+#define QSPI_DLLCRA_SLV_DLY_OFFSET_MASK (0x07 << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT)
+#define QSPI_DLLCRA_SLV_DLY(n) ((n << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT) & QSPI_DLLCRA_SLV_DLY_OFFSET_MASK)
+ /* Bit 15: Reserved */
+#define QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT (16) /* Bits 16-19: Fine offset delay elements in incoming DQS (SLV_FINE_OFFSET) */
+#define QSPI_DLLCRA_SLV_FINE_OFFSET_MASK (0x0f << QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT)
+ /* Bits 20-29: Reserved */
+#define QSPI_DLLCRA_FREQEN (1 << 30) /* Bit 30: Frequency enable (FREQEN) */
+ /* Bit 31: Reserved */
+
+/* Serial Flash Memory Address Register (SFAR) */
+
+#define QSPI_SFAR_SFADR_SHIFT (0) /* Bits 0-31: Serial flash memory address (SFADR) */
+#define QSPI_SFAR_SFADR_MASK (0xffffffff << QSPI_SFAR_SFADR_SHIFT)
+
+/* Sampling Register (SMPR) */
+
+ /* Bits 0-4: Reserved */
+#define QSPI_SMPR_FSPHS (1 << 5) /* Bit 5: Full speed phase selection for SDR instructions (FSPHS) */
+#define QSPI_SMPR_FSDLY (1 << 6) /* Bit 6: Full speed delay section for SDR instructions (FSDLY) */
+ /* Bits 7-23: Reserved */
+#define QSPI_SMPR_DLLFSMPFA_SHIFT (24) /* Bits 24-26: Selects the nth tap provided by slave delay chain for flash memory A (DLLFSMPFA) */
+#define QSPI_SMPR_DLLFSMPFA_MASK (0x07 << QSPI_SMPR_DLLFSMPFA_SHIFT)
+#define QSPI_SMPR_DLLFSMPFA(n) ((n << QSPI_SMPR_DLLFSMPFA_SHIFT) & QSPI_SMPR_DLLFSMPFA_MASK)
+ /* Bits 27-31: Reserved */
+
+/* RX Buffer Status Register (RBSR) */
+
+#define QSPI_RBSR_RDBFL_SHIFT (0) /* Bits 0-7: RX buffer fill level (RDBFL) */
+#define QSPI_RBSR_RDBFL_MASK (0xff << QSPI_RBSR_RDBFL_SHIFT)
+ /* Bits 8-15: Reserved */
+#define QSPI_RBSR_RDCTR_SHIFT (16) /* Bits 16-31: Read counter (RDCTR) */
+#define QSPI_RBSR_RDCTR_MASK (0xffff << QSPI_RBSR_RDCTR_SHIFT)
+
+/* RX Buffer Control Register (RBCT) */
+
+#define QSPI_RBCT_WMRK_SHIFT (0) /* Bits 0-6: RX buffer watermark (WMRK) */
+#define QSPI_RBCT_WMRK_MASK (0x7f << QSPI_RBCT_WMRK_SHIFT)
+#define QSPI_RBCT_WMRK(n) ((n << QSPI_RBCT_WMRK_SHIFT) & QSPI_RBCT_WMRK_MASK)
+ /* Bit 7: Reserved */
+#define QSPI_RBCT_RXBRD (1 << 8) /* Bit 8: RX buffer readout (RXBRD) */
+# define QSPI_RBCT_RXBRD_AHB (0 << 8) /* RX buffer content is read using the AHB bus registers */
+# define QSPI_RBCT_RXBRD_IP (1 << 8) /* RX buffer content is read using the IP bus registers */
+ /* Bits 9-31: Reserved */
+
+/* Data Learning Status Flash Memory A Register (DLSR_FA) */
+
+#define QSPI_DLSR_FA_NEG_EDGE_SHIFT (0) /* Bits 0-7: DLP negative edge match signature for flash memory A (NEG_EDGE) */
+#define QSPI_DLSR_FA_NEG_EDGE_MASK (0xff << QSPI_DLSR_FA_NEG_EDGE_SHIFT)
+#define QSPI_DLSR_FA_POS_EDGE_SHIFT (8) /* Bits 8-15: DLP positive edge match signature for flash memory A (POS_EDGE) */
+#define QSPI_DLSR_FA_POS_EDGE_MASK (0xff << QSPI_DLSR_FA_POS_EDGE_SHIFT)
+ /* Bits 16-30: Reserved */
+#define QSPI_DLSR_FA_DLPFFA (1 << 31) /* Bit 31: Data learning pattern fail (DLPFFA) */
+
+/* TX Buffer Status Register (TBSR) */
+
+#define QSPI_TBSR_TRBLF_SHIFT (0) /* Bits 0-5: TX buffer fill level (TRBFL) */
+#define QSPI_TBSR_TRBLF_MASK (0x3f << QSPI_TBSR_TRBLF_SHIFT)
+ /* Bits 6-15: Reserved */
+#define QSPI_TBSR_TRCTR_SHIFT (16) /* Bits 16-31: Transmit counter (TRCTR) */
+#define QSPI_TBSR_TRCTR_MASK (0xffff << QSPI_TBSR_TRCTR_SHIFT)
+
+/* TX Buffer Data Register (TBDR) */
+
+#define QSPI_TBDR_TXDATA_SHIFT (0) /* Bits 0-31: TX data (TXDATA) */
+#define QSPI_TBDR_TXDATA_MASK (0xffffffff << QSPI_TBDR_TXDATA_SHIFT)
+
+/* TX Buffer Control Register (TBCT) */
+
+#define QSPI_TBCT_WMRK_SHIFT (0) /* Bits 0-4: Watermark for TX buffer (WMRK) */
+#define QSPI_TBCT_WMRK_MASK (0x1f << QSPI_TBCT_WMRK_SHIFT)
+#define QSPI_TBCT_WMRK(n) ((n << QSPI_TBCT_WMRK_SHIFT) & QSPI_TBCT_WMRK_MASK)
+ /* Bits 5-31: Reserved */
+
+/* Status Register (SR) */
+
+#define QSPI_SR_BUSY (1 << 0) /* Bit 0: Module busy (BUSY) */
+#define QSPI_SR_IP_ACC (1 << 1) /* Bit 1: IP access (IP_ACC) */
+#define QSPI_SR_AHB_ACC (1 << 2) /* Bit 2: AHB read access (AHB_ACC) */
+ /* Bits 3-5: Reserved */
+#define QSPI_SR_AHBTRN (1 << 6) /* Bit 6: AHB access transaction pending (AHBTRN) */
+#define QSPI_SR_AHB0NE (1 << 7) /* Bit 7: AHB 0 buffer not empty (AHB0NE) */
+#define QSPI_SR_AHB1NE (1 << 8) /* Bit 8: AHB 1 buffer not empty (AHB1NE) */
+#define QSPI_SR_AHB2NE (1 << 9) /* Bit 9: AHB 2 buffer not empty (AHB2NE) */
+#define QSPI_SR_AHB3NE (1 << 10) /* Bit 10: AHB 3 buffer not empty (AHB3NE) */
+#define QSPI_SR_AHB0FUL (1 << 11) /* Bit 11: AHB 0 buffer full (AHB0FUL) */
+#define QSPI_SR_AHB1FUL (1 << 12) /* Bit 12: AHB 1 buffer full (AHB1FUL) */
+#define QSPI_SR_AHB2FUL (1 << 13) /* Bit 13: AHB 2 buffer full (AHB2FUL) */
+#define QSPI_SR_AHB3FUL (1 << 14) /* Bit 14: AHB 3 buffer full (AHB3FUL) */
+ /* Bit 15: Reserved */
+#define QSPI_SR_RXWE (1 << 16) /* Bit 16: RX buffer watermark exceeded (RXWE) */
+ /* Bits 17-18: Reserved */
+#define QSPI_SR_RXFULL (1 << 19) /* Bit 19: RX buffer full (RXFULL) */
+ /* Bits 20-22: Reserved */
+#define QSPI_SR_RXDMA (1 << 23) /* Bit 23: RX buffer DMA (RXDMA) */
+#define QSPI_SR_TXNE (1 << 24) /* Bit 24: TX buffer not empty (TXNE) */
+#define QSPI_SR_TXWA (1 << 25) /* Bit 25: TX buffer watermark available (TXWA) */
+#define QSPI_SR_TXDMA (1 << 26) /* Bit 26: TX buffer DMA (TXDMA) */
+#define QSPI_SR_TXFUL (1 << 27) /* Bit 27: TX buffer full (TXFULL) */
+ /* Bits 28-31: Reserved */
+
+/* Flag Register (FR) */
+
+#define QSPI_FR_TFF (1 << 0) /* Bit 0: IP command transaction finished flag (TFF) */
+ /* Bits 1-5: Reserved */
+#define QSPI_FR_IPIEF (1 << 6) /* Bit 6: IP command trigger could not be executed error flag (IPIEF) */
+#define QSPI_FR_IPAEF (1 << 7) /* Bit 7: IP command trigger during AHB access error flag (IPAEF) */
+ /* Bits 8-11: Reserved */
+#define QSPI_FR_ABOF (1 << 12) /* Bit 12: AHB buffer overflow flag (ABOF) */
+#define QSPI_FR_AIBSEF (1 << 13) /* Bit 13: AHB illegal burst size error flag (AIBSEF) */
+#define QSPI_FR_AITEF (1 << 14) /* Bit 14: AHB illegal transaction error flag (AITEF) */
+ /* Bit 15: Reserved */
+#define QSPI_FR_RBDF (1 << 16) /* Bit 16: RX buffer drain flag (RBDF) */
+#define QSPI_FR_RBOF (1 << 17) /* Bit 17: RX buffer overflow flag (RBOF) */
+ /* Bits 18-22: Reserved */
+#define QSPI_FR_ILLINE (1 << 23) /* Bit 23: Illegal instruction error flag (ILLINE) */
+ /* Bits 24-25: Reserved */
+#define QSPI_FR_TBUF (1 << 26) /* Bit 26: TX buffer underrun flag (TBUF) */
+#define QSPI_FR_TBFF (1 << 27) /* Bit 27: TX buffer fill flag (TBFF) */
+ /* Bits 28-31: Reserved */
+
+/* Interrupt and DMA Request Select and Enable Register (RSER) */
+
+#define QSPI_RSER_TFIE (1 << 0) /* Bit 0: Transaction finished interrupt enable flag (TFIE) */
+ /* Bits 1-5: Reserved */
+#define QSPI_RSER_IPIEIE (1 << 6) /* Bit 6: IP command trigger during IP access error interrupt enable flag (IPIEIE) */
+#define QSPI_RSER_IPAEIE (1 << 7) /* Bit 7: IP command trigger during AHB read access error interrupt enable flag (IPAEIE) */
+ /* Bits 8-11: Reserved */
+#define QSPI_RSER_ABOIE (1 << 12) /* Bit 12: AHB buffer overflow interrupt enable flag (ABOIE) */
+#define QSPI_RSER_AIBSIE (1 << 13) /* Bit 13: AHB illegal burst size interrupt enable flag (AIBSIE) */
+#define QSPI_RSER_AITIE (1 << 14) /* Bit 14: AHB illegal transaction interrupt enable flag (AITIE) */
+ /* Bit 15: Reserved */
+#define QSPI_RSER_RBDIE (1 << 16) /* Bit 16: RX buffer drain interrupt enable (RBDIE) */
+#define QSPI_RSER_RBOIE (1 << 17) /* Bit 17: RX buffer overflow interrupt enable (RBOIE) */
+ /* Bits 18-20: Reserved */
+#define QSPI_RSER_RBDDE (1 << 21) /* Bit 21: RX buffer drain DMA enable (RBDDE) */
+ /* Bit 22: Reserved */
+#define QSPI_RSER_ILLINIE (1 << 23) /* Bit 23: Illegal instruction error interrupt enable (ILLINIE) */
+ /* Bit 24: Reserved */
+#define QSPI_RSER_TBFDE (1 << 25) /* Bit 25: TX buffer fill DMA enable (TBFDE) */
+#define QSPI_RSER_TBUIE (1 << 26) /* Bit 26: TX buffer underrun interrupt enable flag (TBUIE) */
+#define QSPI_RSER_TBFIE (1 << 27) /* Bit 27: TX buffer fill interrupt enable flag (TBFIE) */
+ /* Bits 28-31: Reserved */
+
+/* Sequence Pointer Clear Register (SPTRCLR) */
+
+#define QSPI_SPTRCLR_BFPTRC (1 << 0) /* Bit 0: Buffer pointer clear (BFPTRC) */
+ /* Bits 1-7: Reserved */
+#define QSPI_SPTRCLR_IPPTRC (1 << 8) /* Bit 8: IP pointer clear (IPPTRC) */
+ /* Bits 9-31: Reserved */
+
+/* Serial Flash Memory An/Bn Top Address Register (SFAnAD/SFBnAD) */
+
+ /* Bits 0-9: Reserved */
+#define QSPI_SFAD_TPAD_SHIFT (10) /* Bits 10-31: Top address for serial flash memory An/Bn (TPADAn/TPADBn) */
+#define QSPI_SFAD_TPAD_MASK (0x3fffff << QSPI_SFAD_TPAD_SHIFT)
+#define QSPI_SFAD_TPAD(n) ((n << QSPI_SFAD_TPAD_SHIFT) & QSPI_SFAD_TPAD_MASK)
+
+/* RX Buffer Data Register (RBDRn, n=0,...,63) */
+
+#define QSPI_RBDR_RXDATA_SHIFT (0) /* Bits 0-31: RX data (RXDATA) */
+#define QSPI_RBDR_RXDATA_MASK (0xffffffff << QSPI_RBDR_RXDATA_SHIFT)
+
+/* LUT Key Register (LUTKEY) */
+
+#define QSPI_LUTKEY_KEY_SHIFT (0) /* Bits 0-31: Key to lock or unlock the LUT (KEY) */
+#define QSPI_LUTKEY_KEY_MASK (0xffffffff << QSPI_LUTKEY_KEY_SHIFT)
+#define QSPI_LUTKEY_KEY (0x5AF05AF0UL)
+
+/* LUT Lock Configuration Register (LKCR) */
+
+#define QSPI_LKCR_LOCK (1 << 0) /* Bit 0: Lock LUT (LOCK) */
+#define QSPI_LKCR_UNLOCK (1 << 1) /* Bit 1: Unlock LUT (UNLOCK) */
+ /* Bits 2-31: Reserved */
+
+/* LUT Register (LUTn) */
+
+#define QSPI_LUT_OPRND0_SHIFT (0) /* Bits 0-7: Operand for INSTR0 (OPRND0) */
+#define QSPI_LUT_OPRND0_MASK (0xff << QSPI_LUT_OPRND0_SHIFT)
+#define QSPI_LUT_OPRND0(n) ((n << QSPI_LUT_OPRND0_SHIFT) & QSPI_LUT_OPRND0_MASK)
+#define QSPI_LUT_PAD0_SHIFT (8) /* Bits 8-9: Pad information for INSTR0 (PAD0) */
+#define QSPI_LUT_PAD0_MASK (0x03 << QSPI_LUT_PAD0_SHIFT)
+# define QSPI_LUT_PAD0_1 (0x00 << QSPI_LUT_PAD0_SHIFT) /* 1 Pad */
+# define QSPI_LUT_PAD0_2 (0x01 << QSPI_LUT_PAD0_SHIFT) /* 2 Pad */
+# define QSPI_LUT_PAD0_4 (0x02 << QSPI_LUT_PAD0_SHIFT) /* 4 Pad */
+
+#define QSPI_LUT_INSTR0_SHIFT (10) /* Bits 10-15: Instruction 0 (INSTR0) */
+#define QSPI_LUT_INSTR0_MASK (0x3f << QSPI_LUT_INSTR0_SHIFT)
+#define QSPI_LUT_INSTR0(n) ((n << QSPI_LUT_INSTR0_SHIFT) & QSPI_LUT_INSTR0_MASK)
+
+#define QSPI_LUT_OPRND1_SHIFT (16) /* Bits 16-23: Operand for INSTR1 (OPRND1) */
+#define QSPI_LUT_OPRND1_MASK (0xff << QSPI_LUT_OPRND1_SHIFT)
+#define QSPI_LUT_OPRND1(n) ((n << QSPI_LUT_OPRND1_SHIFT) & QSPI_LUT_OPRND1_MASK)
+#define QSPI_LUT_PAD1_SHIFT (24) /* Bits 24-25: Pad information for INSTR1 (PAD1) */
+#define QSPI_LUT_PAD1_MASK (0x03 << QSPI_LUT_PAD1_SHIFT)
+# define QSPI_LUT_PAD1_1 (0x00 << QSPI_LUT_PAD1_SHIFT) /* 1 Pad */
+# define QSPI_LUT_PAD1_2 (0x01 << QSPI_LUT_PAD1_SHIFT) /* 2 Pad */
+# define QSPI_LUT_PAD1_4 (0x02 << QSPI_LUT_PAD1_SHIFT) /* 4 Pad */
+
+#define QSPI_LUT_INSTR1_SHIFT (26) /* Bits 26-31: Instruction 1 (INSTR1) */
+#define QSPI_LUT_INSTR1_MASK (0x3f << QSPI_LUT_INSTR1_SHIFT)
+#define QSPI_LUT_INSTR1(n) ((n << QSPI_LUT_INSTR1_SHIFT) & QSPI_LUT_INSTR1_MASK)
+
+/* External Memory Base Address */
+
+#define QSPI_AMBA_BASE 0x68000000
+
+/* flash connection to the QSPI module */
+
+typedef enum
+{
+ QSPI_SIDE_A1 = 0x00u, /* Serial flash connected on side A1 */
+ QSPI_SIDE_A2 = 0x01u, /* Serial flash connected on side A2 */
+ QSPI_SIDE_B1 = 0x02u, /* Serial flash connected on side B1 */
+ QSPI_SIDE_B2 = 0x03u, /* Serial flash connected on side B2 */
+} s32k3xx_qspi_connectiontype;
+
+/* flash operation type */
+
+typedef enum
+{
+ QSPI_OP_TYPE_CMD = 0x00u, /* Simple command */
+ QSPI_OP_TYPE_WRITE_REG = 0x01u, /* Write value in external flash register */
+ QSPI_OP_TYPE_RMW_REG = 0x02u, /* RMW command on external flash register */
+ QSPI_OP_TYPE_READ_REG = 0x03u, /* Read external flash register until expected value is read */
+ QSPI_OP_TYPE_QSPI_CFG = 0x04u, /* Re-configure QSPI controller */
+} s32k3xx_qspi_optype;
+
+/* Lut commands */
+
+typedef enum
+{
+ QSPI_LUT_INSTR_STOP = (0U << 10U), /* End of sequence */
+ QSPI_LUT_INSTR_CMD = (1U << 10U), /* Command */
+ QSPI_LUT_INSTR_ADDR = (2U << 10U), /* Address */
+ QSPI_LUT_INSTR_DUMMY = (3U << 10U), /* Dummy cycles */
+ QSPI_LUT_INSTR_MODE = (4U << 10U), /* 8-bit mode */
+ QSPI_LUT_INSTR_MODE2 = (5U << 10U), /* 2-bit mode */
+ QSPI_LUT_INSTR_MODE4 = (6U << 10U), /* 4-bit mode */
+ QSPI_LUT_INSTR_READ = (7U << 10U), /* Read data */
+ QSPI_LUT_INSTR_WRITE = (8U << 10U), /* Write data */
+ QSPI_LUT_INSTR_JMP_ON_CS = (9U << 10U), /* Jump on chip select deassert and stop */
+ QSPI_LUT_INSTR_ADDR_DDR = (10U << 10U), /* Address - DDR mode */
+ QSPI_LUT_INSTR_MODE_DDR = (11U << 10U), /* 8-bit mode - DDR mode */
+ QSPI_LUT_INSTR_MODE2_DDR = (12U << 10U), /* 2-bit mode - DDR mode */
+ QSPI_LUT_INSTR_MODE4_DDR = (13U << 10U), /* 4-bit mode - DDR mode */
+ QSPI_LUT_INSTR_READ_DDR = (14U << 10U), /* Read data - DDR mode */
+ QSPI_LUT_INSTR_WRITE_DDR = (15U << 10U), /* Write data - DDR mode */
+ QSPI_LUT_INSTR_DATA_LEARN = (16U << 10U), /* Data learning pattern */
+ QSPI_LUT_INSTR_CMD_DDR = (17U << 10U), /* Command - DDR mode */
+ QSPI_LUT_INSTR_CADDR = (18U << 10U), /* Column address */
+ QSPI_LUT_INSTR_CADDR_DDR = (19U << 10U), /* Column address - DDR mode */
+ QSPI_LUT_INSTR_JMP_TO_SEQ = (20U << 10U), /* Jump on chip select deassert and continue */
+} s32k3xx_qspi_lutcommandstype;
+
+/* Lut pad options */
+
+typedef enum
+{
+ QSPI_LUT_PADS_1 = (0U << 8U), /* 1 Pad */
+ QSPI_LUT_PADS_2 = (1U << 8U), /* 2 Pads */
+ QSPI_LUT_PADS_4 = (2U << 8U), /* 4 Pads */
+ QSPI_LUT_PADS_8 = (3U << 8U), /* 8 Pads */
+} s32k3xx_qspi_lutpadstype;
+
+#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H */
+
Review Comment:
```suggestion
```
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] PetervdPerk-NXP commented on a diff in pull request #6687: Add support for NXP S32K3XX MCU family and boards
Posted by GitBox <gi...@apache.org>.
PetervdPerk-NXP commented on code in PR #6687:
URL: https://github.com/apache/incubator-nuttx/pull/6687#discussion_r927750841
##########
boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c:
##########
@@ -0,0 +1,82 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/board.h>
+
+#include <stdint.h>
+
+#include "s32k344evb.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef OK
+# define OK 0
+#endif
Review Comment:
You're right cleaned it up
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] xiaoxiang781216 merged pull request #6687: Add support for NXP S32K3XX MCU family and boards
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 merged PR #6687:
URL: https://github.com/apache/incubator-nuttx/pull/6687
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org