You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@nuttx.apache.org by ac...@apache.org on 2024/05/02 19:30:48 UTC
(nuttx) 01/02: Add configuration option for RTL8211F RGMII PHY
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 9277be25036e9ac64da953b1a3b50b8d98bcc08e
Author: Jukka Laitinen <ju...@ssrc.tii.ae>
AuthorDate: Tue Apr 23 16:31:52 2024 +0300
Add configuration option for RTL8211F RGMII PHY
Also extend the "struct phy_desc_s" to support for 1GB PHY's, the speed
detection always needs more than one bit.
Signed-off-by: Jukka Laitinen <ju...@ssrc.tii.ae>
---
drivers/net/Kconfig | 6 ++++++
include/nuttx/net/gmii.h | 27 +++++++++++++++++++++++++++
include/nuttx/net/mii.h | 2 ++
3 files changed, 35 insertions(+)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index d277ed908e..96a0e8ec40 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -610,6 +610,9 @@ config ETH0_PHY_LAN8740A
config ETH0_PHY_LAN8742A
bool "SMSC LAN8742A PHY"
+config ETH0_PHY_RTL8211F
+ bool "Realtek RTL8211F PHY"
+
config ETH0_PHY_DM9161
bool "Davicom DM9161 PHY"
@@ -663,6 +666,9 @@ config ETH1_PHY_TJA1101
config ETH1_PHY_LAN8720
bool "SMSC LAN8720 PHY"
+config ETH1_PHY_RTL8211F
+ bool "Realtek RTL8211F PHY"
+
config ETH1_PHY_DM9161
bool "Davicom DM9161 PHY"
diff --git a/include/nuttx/net/gmii.h b/include/nuttx/net/gmii.h
index e4ab94edad..ed8511461e 100644
--- a/include/nuttx/net/gmii.h
+++ b/include/nuttx/net/gmii.h
@@ -80,6 +80,21 @@
#define GMII_KSZ90X1_RRDPSR 261 /* RGMII RX data pad skew */
#define GMII_KSZ90x1_ATR 263 /* Analog test register */
+/* Realtek RTL8211 PHY Extended Registers */
+
+#define GMII_RTL8211F_NAME "RTL8211F"
+#define GMII_RTL8211F_INER_A42 18 /* Interrupt Enable Register */
+#define GMII_RTL8211F_PHYCR1_A43 24 /* PHY Specific Control Register 1 */
+#define GMII_RTL8211F_PHYCR2_A43 25 /* PHY Specific Control Register 2 */
+#define GMII_RTL8211F_PHYSR_A43 26 /* PHY Specific Status Register */
+#define GMII_RTL8211F_INSR_A43 29 /* Interrupt Status Register */
+#define GMII_RTL8211F_PAGSR 31 /* Page Select Register */
+#define GMII_RTL8211F_PHYSCR_A46 20 /* PHY Special Cofig Register */
+#define GMII_RTL8211F_LCR_D04 16 /* LED Control Register */
+#define GMII_RTL8211F_EEELCR_D04 17 /* EEE LED Control Register */
+#define GMII_RTL8211F_MIICR_D08 21 /* MII Control Register */
+#define GMII_RTL8211F_INTBCR_D40 22 /* INTB Pin Control Register */
+
/* MII register bit settings ************************************************/
/* MII Control register bit definitions */
@@ -280,6 +295,18 @@
#define GMII_KSZ90x1_INT_RF (1 << 1) /* Remote fault interrupt */
#define GMII_KSZ90x1_INT_LU (1 << 0) /* Link up interrupt */
+/* RTL8211 register bit settings ********************************************/
+
+/* RTL8211F MII ID1/2 register bits */
+
+#define GMII_PHYID1_RTL8211F 0x001c /* ID1 value for Realtek RTL8211F */
+#define GMII_PHYID2_RTL8211F 0xc878 /* ID2 value for Realtek RTL8211F */
+#define GMII_RTL8211F_PHYSR_SPEED_MASK 0x30
+#define GMII_RTL8211F_PHYSR_10MBPS 0x00
+#define GMII_RTL8211F_PHYSR_100MBPS 0x10
+#define GMII_RTL8211F_PHYSR_1000MBPS 0x20
+#define GMII_RTL8211F_PHYSR_DUPLEX 0x8
+
/****************************************************************************
* Type Definitions
****************************************************************************/
diff --git a/include/nuttx/net/mii.h b/include/nuttx/net/mii.h
index cbc818a2d0..b9eeefc15a 100644
--- a/include/nuttx/net/mii.h
+++ b/include/nuttx/net/mii.h
@@ -951,6 +951,8 @@ struct phy_desc_s
uint16_t mbps100; /* The bit mask for 100MBP if status is not 0xffff */
uint16_t duplex; /* The bit mask for DUPLEX if status is not 0xffff */
uint16_t clause; /* The PHY clause supported. 22 or 45 */
+ uint16_t mbps1000; /* The bit mask for 1000MBP if status is not 0xffff */
+ uint16_t speed_mask; /* The bit mask for mbps10, 100, 1000 */
};
/****************************************************************************