[GitHub] [mynewt-core] nkaje commented on a change in pull request #2131: da1469x: Add Encrypted Flash Driver

[GitBox <gi...@apache.org>]

nkaje commented on a change in pull request #2131: da1469x: Add Encrypted Flash Driver
URL: https://github.com/apache/mynewt-core/pull/2131#discussion_r357482349
 
 

 ##########
 File path: hw/drivers/flash/enc_flash/ef_da1469x/src/hw_enc_flash.c
 ##########
 @@ -0,0 +1,162 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <string.h>
+
+#include <os/mynewt.h>
+#include <mcu/da1469x_clock.h>
+
+#include "enc_flash/enc_flash.h"
+#include "enc_flash/enc_flash_int.h"
+#include "mcu/da1469x_dma.h"
+#include "mcu/da1469x_otp.h"
+
+void
+do_dma_key_tx(const struct hal_flash *h_dev, uint32_t slot)
+{
+    DMA_Type *dma_regs = DMA;
+
+	/* enable OTP clock and set in read mode */
+    da1469x_clock_amba_enable(CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk);
+    da1469x_otp_set_mode(OTPC_MODE_READ);
+
+    /* disable decrypt on the fly and program start and end addresses */
+    QSPIC->QSPIC_CTR_CTRL_REG = 0;
+    QSPIC->QSPIC_CTR_SADDR_REG = h_dev->hf_base_addr;
+    QSPIC->QSPIC_CTR_EADDR_REG = h_dev->hf_size + h_dev->hf_base_addr;
+
+    /* securely DMA hardware key from secret storage to QSPI decrypt engine */
+    dma_regs->DMA_REQ_MUX_REG |= 0xf000;
+    dma_regs->DMA7_LEN_REG = 8;
+    dma_regs->DMA7_A_START_REG = MCU_OTPM_BASE + OTP_SEGMENT_USER_DATA_KEYS +
+                                 (32 * (slot));
+    dma_regs->DMA7_B_START_REG = (uint32_t)AES_HASH->CRYPTO_KEYS_START;
+    dma_regs->DMA7_CTRL_REG = DMA_DMA7_CTRL_REG_AINC_Msk |
+                              DMA_DMA7_CTRL_REG_BINC_Msk |
+                              (MCU_DMA_BUS_WIDTH_4B << DMA_DMA7_CTRL_REG_BW_Pos) |
+                              DMA_DMA7_CTRL_REG_DMA_ON_Msk;
+    while (dma_regs->DMA7_IDX_REG != 8);
+
+    /* set OTP to standby and turn off clock */
+    da1469x_otp_set_mode(OTPC_MODE_STBY);
+    da1469x_clock_amba_disable(CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk);
+}
+
+static uint32_t
+get_key_size_mask(int keysize)
+{
+    uint32_t val;
+
+    switch(keysize) {
+        case 256:
+            val = 3;
+            break;
+        case 192:
+            val = 1;
+            break;
+        case 128:
+            val = 0;
+            break;
+        default:
+            val = 0;
+   }
+   return (val << AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Pos);
+}
+
+/**
+ * AES encrypt
+ *
+ * Encrypt the plain text with the given key
+ */
+
+void
+do_encrypt(const struct hal_flash *h_dev, uint32_t *ctr, const uint8_t *src, uint8_t *tgt, int off, int cnt)
+{
+    /* Select AES CTR, set CRYPTO_ALG_MD bits to 10 */
+    uint32_t algo_sel = (2 << AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Pos);
+    uint32_t ks_mask = get_key_size_mask(MYNEWT_VAL(USER_AES_KEYSIZE));
+
+    /* XXX: for now assume we are only user of crypto block */
+    da1469x_clock_amba_enable(CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Msk);
+
+    /*
+     * AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Msk: Key Expansion needs to be
+     * set for AES 128 CTR, but not AES 256 CTR mode
+     * Set CRYPTO_CTRL_REG to:
+     *  Enable CRYPTO_OUT_MD: Write back to memory only the final block of
+     * resulting data
+     *  Set Key Size to 256 bits
+     *  Set algo mode to CTR.
+     */
+    AES_HASH->CRYPTO_CTRL_REG = AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Msk |
+                                ks_mask |
+//                                AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Msk |
 
 Review comment:
   clean up

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