You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@nuttx.apache.org by da...@apache.org on 2020/12/02 19:27:27 UTC
[incubator-nuttx] 01/02: FLASH waiting cycles are configured based
on HCLK.
This is an automated email from the ASF dual-hosted git repository.
davids5 pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit f538839720f67620f8c6a71054baf3a9608835d3
Author: Fotis Panagiotopoulos <f....@amco.gr>
AuthorDate: Fri Oct 30 14:24:24 2020 +0200
FLASH waiting cycles are configured based on HCLK.
---
arch/arm/src/stm32/stm32f10xxx_rcc.c | 31 ++++++++++++++++++++++---------
arch/arm/src/stm32/stm32f20xxx_rcc.c | 25 +++++++++++++++++++++++--
arch/arm/src/stm32/stm32f30xxx_rcc.c | 31 ++++++++++++++++++++++---------
arch/arm/src/stm32/stm32f33xxx_rcc.c | 36 ++++++++++++++++++++----------------
arch/arm/src/stm32/stm32f37xxx_rcc.c | 22 ++++++++++++++++++++--
arch/arm/src/stm32/stm32f40xxx_rcc.c | 31 +++++++++++++++++++++++++++++--
6 files changed, 136 insertions(+), 40 deletions(-)
diff --git a/arch/arm/src/stm32/stm32f10xxx_rcc.c b/arch/arm/src/stm32/stm32f10xxx_rcc.c
index b194fc9..ae2b06b 100644
--- a/arch/arm/src/stm32/stm32f10xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f10xxx_rcc.c
@@ -49,6 +49,24 @@
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
+/* The FLASH latency depends on the system clock.
+ *
+ * Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
+ * 0WS from 0-24MHz
+ * 1WS from 24-48MHz
+ * 2WS from 48-72MHz
+ */
+
+#if (STM32_SYSCLK_FREQUENCY <= 24000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_0
+#elif (STM32_SYSCLK_FREQUENCY <= 48000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_1
+#elif (STM32_SYSCLK_FREQUENCY <= 78000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_2
+#else
+# error "STM32_SYSCLK_FREQUENCY is out of range!"
+#endif
+
/****************************************************************************
* Private Data
****************************************************************************/
@@ -522,16 +540,11 @@ static void stm32_stdclockconfig(void)
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
- /* Set flash wait states
- * Sysclk runs with 72MHz -> 2 waitstates.
- * 0WS from 0-24MHz
- * 1WS from 24-48MHz
- * 2WS from 48-72MHz
- */
+ /* Enable prefetch buffer and set FLASH wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
- regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
+ regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
/* Set up PLL input scaling (with source = PLL2) */
@@ -687,11 +700,11 @@ static void stm32_stdclockconfig(void)
#ifndef CONFIG_STM32_VALUELINE
- /* Enable FLASH prefetch buffer and 2 wait states */
+ /* Enable FLASH prefetch buffer and set FLASH wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
- regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
+ regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
#endif
diff --git a/arch/arm/src/stm32/stm32f20xxx_rcc.c b/arch/arm/src/stm32/stm32f20xxx_rcc.c
index 5347c76..ac0435c 100644
--- a/arch/arm/src/stm32/stm32f20xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f20xxx_rcc.c
@@ -55,6 +55,27 @@
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
+/* The FLASH latency depends on the system clock.
+ *
+ * Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
+ * 0WS from 0-30MHz
+ * 1WS from 30-60MHz
+ * 2WS from 60-90MHz
+ * 3WS from 90-120MHz
+ */
+
+#if (STM32_SYSCLK_FREQUENCY <= 30000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_0
+#elif (STM32_SYSCLK_FREQUENCY <= 60000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_1
+#elif (STM32_SYSCLK_FREQUENCY <= 90000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_2
+#elif (STM32_SYSCLK_FREQUENCY <= 120000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_3
+#else
+# error "STM32_SYSCLK_FREQUENCY is out of range!"
+#endif
+
/****************************************************************************
* Private Data
****************************************************************************/
@@ -646,10 +667,10 @@ static void stm32_stdclockconfig(void)
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
/* Enable FLASH prefetch, instruction cache, data cache,
- * and 5 wait states.
+ * and set FLASH wait states.
*/
- regval = (FLASH_ACR_LATENCY_5
+ regval = (FLASH_ACR_LATENCY_SETTING
#ifdef CONFIG_STM32_FLASH_ICACHE
| FLASH_ACR_ICEN
#endif
diff --git a/arch/arm/src/stm32/stm32f30xxx_rcc.c b/arch/arm/src/stm32/stm32f30xxx_rcc.c
index b30a145..92b6778 100644
--- a/arch/arm/src/stm32/stm32f30xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f30xxx_rcc.c
@@ -49,6 +49,24 @@
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
+/* The FLASH latency depends on the system clock.
+ *
+ * Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
+ * 0WS from 0-24MHz
+ * 1WS from 24-48MHz
+ * 2WS from 48-72MHz
+ */
+
+#if (STM32_SYSCLK_FREQUENCY <= 24000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_0
+#elif (STM32_SYSCLK_FREQUENCY <= 48000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_1
+#elif (STM32_SYSCLK_FREQUENCY <= 72000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_2
+#else
+# error "STM32_SYSCLK_FREQUENCY is out of range!"
+#endif
+
/****************************************************************************
* Private Data
****************************************************************************/
@@ -431,16 +449,11 @@ static void stm32_stdclockconfig(void)
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
- /* Set flash wait states
- * Sysclk runs with 72MHz -> 2 waitstates.
- * 0WS from 0-24MHz
- * 1WS from 24-48MHz
- * 2WS from 48-72MHz
- */
+ /* Enable FLASH prefetch buffer and set FLASH wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
- regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
+ regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
/* Set up PLL input scaling (with source = PLL2) */
@@ -594,11 +607,11 @@ static void stm32_stdclockconfig(void)
#ifndef CONFIG_STM32_VALUELINE
/* Value-line devices don't implement flash prefetch/waitstates */
- /* Enable FLASH prefetch buffer and 2 wait states */
+ /* Enable FLASH prefetch buffer and set FLASH wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
- regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
+ regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
#endif
diff --git a/arch/arm/src/stm32/stm32f33xxx_rcc.c b/arch/arm/src/stm32/stm32f33xxx_rcc.c
index 22ae358..76759fb 100644
--- a/arch/arm/src/stm32/stm32f33xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f33xxx_rcc.c
@@ -50,6 +50,24 @@
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
+/* The FLASH latency depends on the system clock.
+ *
+ * Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
+ * 0WS from 0-24MHz
+ * 1WS from 24-48MHz
+ * 2WS from 48-72MHz
+ */
+
+#if (STM32_SYSCLK_FREQUENCY <= 24000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_0
+#elif (STM32_SYSCLK_FREQUENCY <= 48000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_1
+#elif (STM32_SYSCLK_FREQUENCY <= 72000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_2
+#else
+# error "STM32_SYSCLK_FREQUENCY is out of range!"
+#endif
+
/****************************************************************************
* Private Data
****************************************************************************/
@@ -435,25 +453,11 @@ static void stm32_stdclockconfig(void)
#endif
- /* Set flash wait states according to sysclk:
- *
- * 0WS from 0-24MHz
- * 1WS from 24-48MHz
- * 2WS from 48-72MHz
- */
+ /* Enable FLASH prefetch and wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~(FLASH_ACR_LATENCY_MASK);
-
-#if STM32_SYSCLK_FREQUENCY <= 24000000
- regval |= FLASH_ACR_LATENCY_0;
-#elif STM32_SYSCLK_FREQUENCY <= 48000000
- regval |= FLASH_ACR_LATENCY_1;
-#else
- regval |= FLASH_ACR_LATENCY_2;
-#endif
-
- regval |= FLASH_ACR_PRTFBE;
+ regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
/* Select the system clock source (probably the PLL) */
diff --git a/arch/arm/src/stm32/stm32f37xxx_rcc.c b/arch/arm/src/stm32/stm32f37xxx_rcc.c
index 41cb186..3dc1db9 100644
--- a/arch/arm/src/stm32/stm32f37xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f37xxx_rcc.c
@@ -50,6 +50,24 @@
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
+/* The FLASH latency depends on the system clock.
+ *
+ * Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
+ * 0WS from 0-24MHz
+ * 1WS from 24-48MHz
+ * 2WS from 48-72MHz
+ */
+
+#if (STM32_SYSCLK_FREQUENCY <= 24000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_0
+#elif (STM32_SYSCLK_FREQUENCY <= 48000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_1
+#elif (STM32_SYSCLK_FREQUENCY <= 72000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_2
+#else
+# error "STM32_SYSCLK_FREQUENCY is out of range!"
+#endif
+
/****************************************************************************
* Private Data
****************************************************************************/
@@ -527,11 +545,11 @@ static void stm32_stdclockconfig(void)
# endif
- /* Enable FLASH prefetch buffer and 2 wait states */
+ /* Enable FLASH prefetch buffer and set FLASH wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
- regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
+ regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
/* Set the HCLK source/divider */
diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c
index ed3373d..98ee333 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -68,6 +68,33 @@
#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000
+/* The FLASH latency depends on the system clock.
+ *
+ * Calculate the wait cycles, based on STM32_SYSCLK_FREQUENCY:
+ * 0WS from 0-30MHz
+ * 1WS from 30-60MHz
+ * 2WS from 60-90MHz
+ * 3WS from 90-120MHz
+ * 4WS from 120-150MHz
+ * 5WS from 150-180MHz
+ */
+
+#if (STM32_SYSCLK_FREQUENCY <= 30000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_0
+#elif (STM32_SYSCLK_FREQUENCY <= 60000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_1
+#elif (STM32_SYSCLK_FREQUENCY <= 90000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_2
+#elif (STM32_SYSCLK_FREQUENCY <= 120000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_3
+#elif (STM32_SYSCLK_FREQUENCY <= 150000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_4
+#elif (STM32_SYSCLK_FREQUENCY <= 180000000)
+# define FLASH_ACR_LATENCY_SETTING FLASH_ACR_LATENCY_5
+#else
+# error "STM32_SYSCLK_FREQUENCY is out of range!"
+#endif
+
/****************************************************************************
* Private Data
****************************************************************************/
@@ -778,10 +805,10 @@ static void stm32_stdclockconfig(void)
#endif
/* Enable FLASH prefetch, instruction cache, data cache,
- * and 5 wait states.
+ * and set FLASH wait states.
*/
- regval = (FLASH_ACR_LATENCY_5
+ regval = (FLASH_ACR_LATENCY_SETTING
#ifdef CONFIG_STM32_FLASH_ICACHE
| FLASH_ACR_ICEN
#endif