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Posted to commits@nuttx.apache.org by gn...@apache.org on 2020/05/13 12:41:05 UTC
[incubator-nuttx] 01/03: syscall/README.txt: Describe new
sycall.csv extensions.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch pr1030
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 27430a46a5ba8e4ef9a3b47706eabc8d90d2c143
Author: Gregory Nutt <gn...@nuttx.org>
AuthorDate: Tue May 5 18:16:17 2020 -0600
syscall/README.txt: Describe new sycall.csv extensions.
Provides documentation of recent extensions to the format of the syscall/sycall.csv file.
Updated from incubator-nuttx master
Boad specific code moved to boards directory and ipv6 support added
Added support to crashdump for rx65n on sbram
Updated from incubator-nuttx master
Boad specific code moved to boards directory and ipv6 support added
---
arch/renesas/include/rx65n/irq.h | 43 +-
arch/renesas/include/rx65n/limits.h | 41 +-
arch/renesas/include/rx65n/types.h | 41 +-
arch/renesas/src/rx65n/Make.defs | 2 +-
arch/renesas/src/rx65n/rx65n_cmtw.h | 41 +-
arch/renesas/src/rx65n/rx65n_cmtw0.h | 49 +-
arch/renesas/src/rx65n/rx65n_definitions.h | 126 ++--
arch/renesas/src/rx65n/rx65n_eth.c | 698 +++++++++------------
arch/renesas/src/rx65n/rx65n_eth.h | 60 +-
arch/renesas/src/rx65n/rx65n_hardware_setup.c | 44 +-
arch/renesas/src/rx65n/rx65n_initialstate.c | 41 +-
arch/renesas/src/rx65n/rx65n_lowputc.c | 43 +-
arch/renesas/src/rx65n/rx65n_macrodriver.h | 41 +-
arch/renesas/src/rx65n/rx65n_port.c | 267 +-------
arch/renesas/src/rx65n/rx65n_port.h | 59 +-
arch/renesas/src/rx65n/rx65n_rtc.c | 12 +-
arch/renesas/src/rx65n/rx65n_schedulesigaction.c | 6 +-
arch/renesas/src/rx65n/rx65n_sci.c | 368 ++---------
arch/renesas/src/rx65n/rx65n_sci.h | 49 +-
arch/renesas/src/rx65n/rx65n_serial.c | 25 +-
arch/renesas/src/rx65n/rx65n_timerisr.c | 41 +-
arch/renesas/src/rx65n/rx65n_vector_table.c | 2 +-
boards/renesas/rx65n/rx65n-grrose/README.txt | 27 +-
.../rx65n/rx65n-grrose/configs/ipv6/defconfig | 126 ++++
boards/renesas/rx65n/rx65n-grrose/include/board.h | 12 +-
.../rx65n/rx65n-grrose/include/rx65n_gpio.h | 232 +++++++
boards/renesas/rx65n/rx65n-grrose/src/Makefile | 2 +-
boards/renesas/rx65n/rx65n-grrose/src/rx65n_gpio.c | 358 +++++++++++
.../rx65n/rx65n-rsk1mb/include/rx65n_gpio.h | 97 +++
boards/renesas/rx65n/rx65n-rsk1mb/src/rx65n_gpio.c | 127 ++++
boards/renesas/rx65n/rx65n-rsk2mb/README.txt | 26 +
.../rx65n/rx65n-rsk2mb/configs/ipv6/defconfig | 110 ++++
boards/renesas/rx65n/rx65n-rsk2mb/include/board.h | 12 +-
.../rx65n/rx65n-rsk2mb/include/rx65n_gpio.h | 177 ++++++
boards/renesas/rx65n/rx65n-rsk2mb/src/Makefile | 2 +-
.../renesas/rx65n/rx65n-rsk2mb/src/rx65n_gpio.c | 280 ++++-----
36 files changed, 2055 insertions(+), 1632 deletions(-)
diff --git a/arch/renesas/include/rx65n/irq.h b/arch/renesas/include/rx65n/irq.h
index d7089ca..f4a2ced 100644
--- a/arch/renesas/include/rx65n/irq.h
+++ b/arch/renesas/include/rx65n/irq.h
@@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/include/rx65n/irq.h
*
- * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
- * Author: Anjana <an...@tataelxsi.co.in>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_RENESAS_INCLUDE_RX65N_IRQ_H
#define __ARCH_RENESAS_INCLUDE_RX65N_IRQ_H
@@ -603,7 +588,7 @@
/* Saved to the stacked by up_vector */
-/* Vector table offsets *************************************************************/
+/* Vector table offsets */
/* Trap instruction */
diff --git a/arch/renesas/include/rx65n/limits.h b/arch/renesas/include/rx65n/limits.h
index c31b510..a72cd69 100644
--- a/arch/renesas/include/rx65n/limits.h
+++ b/arch/renesas/include/rx65n/limits.h
@@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/include/rx65n/limits.h
*
- * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
- * Author: Anjana <an...@tataelxsi.co.in>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_RENESAS_INCLUDE_RX65N_LIMITS_H
#define __ARCH_RENESAS_INCLUDE_RX65N_LIMITS_H
diff --git a/arch/renesas/include/rx65n/types.h b/arch/renesas/include/rx65n/types.h
index 81fc4be..c300b54 100644
--- a/arch/renesas/include/rx65n/types.h
+++ b/arch/renesas/include/rx65n/types.h
@@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/include/rx65n/types.h
*
- * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
- * Author: Anjana <an...@tataelxsi.co.in>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
+ ****************************************************************************/
/* This file should never be included directly but, rather, only indirectly\
* through sys/types.h
diff --git a/arch/renesas/src/rx65n/Make.defs b/arch/renesas/src/rx65n/Make.defs
index 31cc582..33a7494 100644
--- a/arch/renesas/src/rx65n/Make.defs
+++ b/arch/renesas/src/rx65n/Make.defs
@@ -45,7 +45,7 @@ CMN_CSRCS += up_stackframe.c up_udelay.c up_unblocktask.c up_usestack.c
CHIP_ASRCS = rx65n_vector.S
CHIP_CSRCS = rx65n_lowputc.c rx65n_serial.c rx65n_copystate.c rx65n_irq.c
CHIP_CSRCS += rx65n_schedulesigaction.c rx65n_sigdeliver.c rx65n_initialstate.c
-CHIP_CSRCS += rx65n_hardware_setup.c rx65n_icu.c rx65n_port.c rx65n_sci.c
+CHIP_CSRCS += rx65n_hardware_setup.c rx65n_port.c rx65n_sci.c
CHIP_CSRCS += rx65n_cgc.c rx65n_dumpstate.c rx65n_vector_table.c
CHIP_CSRCS += rx65n_timerisr.c rx65n_sbram.c
diff --git a/arch/renesas/src/rx65n/rx65n_cmtw.h b/arch/renesas/src/rx65n/rx65n_cmtw.h
index fdef225..27f0e79 100644
--- a/arch/renesas/src/rx65n/rx65n_cmtw.h
+++ b/arch/renesas/src/rx65n/rx65n_cmtw.h
@@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_cmtw.h
*
- * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
- * Author: Surya Prakash <su...@tataelxsi.co.in>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_CMTW_H
#define __ARCH_RENESAS_SRC_RX65N_CMTW_H
diff --git a/arch/renesas/src/rx65n/rx65n_cmtw0.h b/arch/renesas/src/rx65n/rx65n_cmtw0.h
index 344abb4..3de41ed 100644
--- a/arch/renesas/src/rx65n/rx65n_cmtw0.h
+++ b/arch/renesas/src/rx65n/rx65n_cmtw0.h
@@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_cmtw0.h
*
- * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
- * Author: Surya Prakash <su...@tataelxsi.co.in>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_CMTW0_H
#define __ARCH_RENESAS_SRC_RX65N_CMTW0_H
@@ -60,7 +45,7 @@
/****************************************************************************
* Public Function Prototypes
- ***************************************************************************/
+ ****************************************************************************/
/****************************************************************************
* Name: rx65n_cmtw0_create
diff --git a/arch/renesas/src/rx65n/rx65n_definitions.h b/arch/renesas/src/rx65n/rx65n_definitions.h
index ee6fa5f..0f50081 100644
--- a/arch/renesas/src/rx65n/rx65n_definitions.h
+++ b/arch/renesas/src/rx65n/rx65n_definitions.h
@@ -431,19 +431,63 @@
#define ETH_PSR_LMON (1)
-/* End Ethernet and EDMAC Interface */
+/* EDMAC Transmit Request Register's bit */
-/* General Values LED: */
+#define ETHD_EDRRR_TR (1) /* Transmit Request */
-#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
-# define LED_ON (0)
-# define LED_OFF (1)
-#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
-# define LED_ON (1)
-# define LED_OFF (0)
-#else
-# error "No Selection for PORT definition in rx65n_port.c"
-#endif
+/* EDMAC Receive Request Register's bit */
+
+#define ETHD_EDRRR_RR (1) /* Receive descriptor read,
+ * and receive function is enabled
+ */
+
+/* Transmit Interrupt Setting Register's bit */
+
+#define ETHD_TRIMD_TIS (1) /* Transmit Interrupt is enabled */
+#define ETHD_TRIMD_TIM (1<<4) /* Write-back complete interrupt mode */
+
+/* Receive Method Control Register's bit */
+
+/* Receive Method Control Register's bit */
+
+#define ETHD_RMCR_RNR (1) /* EDRRR.RR bit (receive request bit) is not
+ * set to 0 when one frame has been received
+ */
+
+/* FIFO Depth Register's bit */
+
+#define ETHD_FDR_RFD (7) /* Receive FIFO Depth */
+#define ETHD_FDR_TFD (7<<8) /* Transmit FIFO Depth */
+
+/* ETHERC/EDMAC Transmit/Receive Status Copy Enable Register's bit */
+
+#define ETHD_TRSCER_RRFCE (1<<4) /* RRF Flag Copy Enable */
+#define ETHD_TRSCER_RMAFCE (1<<7) /* RMAF Flag Copy Enable */
+
+/* Broadcast Frame Receive Count Setting Register's field */
+
+#define ETH_BCFRR_BCF (0x0000) /* Broadcast Frame Continuous Receive Count Setting */
+
+/* PHY Interface Register's bit and values */
+
+#define ETH_PIR_MDC (1) /* MII/RMII Management Data Clock */
+#define ETH_PIR_MMD (1<<1) /* MII/RMII Management Mode */
+#define ETH_PIR_MDO (1<<2) /* MII/RMII Management Data-Out */
+#define ETH_PIR_MDI (1<<3) /* MII/RMII Management Data-In */
+
+#define ETH_PIR_RESET_ALL (0x00000000) /* Reset All Flags of PIR */
+#define ETH_PIR_SET_MDC (0x00000001) /* Setting MDC of PIR */
+#define ETH_PIR_SET_MMD (0x00000002) /* Setting MMD of PIR */
+#define ETH_PIR_SET_MMD_MDC (0x00000003) /* Setting MMD and MDC */
+#define ETH_PIR_SET_MDO_MMD (0x00000006) /* Setting MDO and MMD */
+#define ETH_PIR_SET_MDO_MMD_MDC (0x00000007) /* Setting MDO, MMD and MDC */
+
+/* Ethernet Control Register's bit and value */
+
+#define ETH_PFENET_MII_MODE (0x10)
+#define ETH_PFENET_RMII_MODE (0x00)
+
+/* End Ethernet and EDMAC Interface */
/* Bit Set Values */
@@ -499,33 +543,33 @@
#define RX65N_RTC_RCR4 (RX65N_RTC_BASE + RX65N_RTC_RCR4_OFFSET)
#define RX65N_RTC_RADJ (RX65N_RTC_BASE + RX65N_RTC_RADJ_OFFSET)
-#define RTC_RTC_ALRDIS (0x00)
-#define RTC_RCR4_RCKSEL (0x00)
-#define RTC_RCR3_RTCEN (0x01)
-#define RTC_RCR3_RTCDV (0x02)
-#define RTC_RCR2_START (0x01)
-#define RTC_RCR2_CNTMD (0x00)
-#define RTC_RCR2_RESET (0x01)
-#define RTC_ALARM_INT_ENABLE (0x01)
-#define RTC_CARRY_INT_ENABLE (0x02)
-#define RTC_PERIOD_INT_ENABLE (0x04)
-#define RTC_PERIODIC_INT_PERIOD_1 (0xe0)
-#define _04_FOUR_READ_COUNT (0x04)
-#define RTC_1_64_SEC_CYCLE (0x0005b8d9)
-#define _0F_RTC_PRIORITY_LEVEL15 (0x0f)
-#define RTC_RCR1_CUP (0x02)
-#define RX65N_SUBCLKOSC_SOSCCR (0x00080033)
-#define SUBCLKOSC_SOSCCR_SOSTP (0x01)
-#define RX65N_SUBCLKOSC_SOSCWTCR (0x0008c293)
-#define RTC_SOSCWTCR_VALUE (0x21)
-#define RTC_DUMMY_READ (3)
-#define _00_RTC_PRIORITY_LEVEL0 (0)
-#define _04_RTC_PERIOD_INT_ENABLE (0x04)
-#define RTC_RTC_CARRYDIS (0xe5)
-#define RTC_RTC_PERDIS (0xe3)
-#define RTC_RADJ_INITVALUE (0x0)
-#define RTC_RCR2_AADJE (0x10)
-#define RTC_RCR2_AADJP (0x20)
+#define RTC_RTC_ALRDIS (0x00)
+#define RTC_RCR4_RCKSEL (0x00)
+#define RTC_RCR3_RTCEN (0x01)
+#define RTC_RCR3_RTCDV (0x02)
+#define RTC_RCR2_START (0x01)
+#define RTC_RCR2_CNTMD (0x00)
+#define RTC_RCR2_RESET (0x01)
+#define RTC_ALARM_INT_ENABLE (0x01)
+#define RTC_CARRY_INT_ENABLE (0x02)
+#define RTC_PERIOD_INT_ENABLE (0x04)
+#define RTC_PERIODIC_INT_PERIOD_1 (0xe0)
+#define _04_FOUR_READ_COUNT (0x04)
+#define RTC_1_64_SEC_CYCLE (0x0005b8d9)
+#define _0F_RTC_PRIORITY_LEVEL15 (0x0f)
+#define RTC_RCR1_CUP (0x02)
+#define RX65N_SUBCLKOSC_SOSCCR (0x00080033)
+#define SUBCLKOSC_SOSCCR_SOSTP (0x01)
+#define RX65N_SUBCLKOSC_SOSCWTCR (0x0008c293)
+#define RTC_SOSCWTCR_VALUE (0x21)
+#define RTC_DUMMY_READ (3)
+#define _00_RTC_PRIORITY_LEVEL0 (0)
+#define _04_RTC_PERIOD_INT_ENABLE (0x04)
+#define RTC_RTC_CARRYDIS (0xe5)
+#define RTC_RTC_PERDIS (0xe3)
+#define RTC_RADJ_INITVALUE (0x0)
+#define RTC_RCR2_AADJE (0x10)
+#define RTC_RCR2_AADJP (0x20)
#if defined(CONFIG_RTC) || defined(CONFIG_RTC_DRIVER)
@@ -534,8 +578,8 @@
#endif
#define RX65N_RTC_WAIT_PERIOD 184
-#define RTC_RCR2_HR24 (0x40)
-#define RTC_PERIODIC_INTERRUPT_2_SEC (0xf)
+#define RTC_RCR2_HR24 (0x40)
+#define RTC_PERIODIC_INTERRUPT_2_SEC (0xf)
/* StandBy RAM Address */
@@ -569,7 +613,9 @@ enum E_RX_SCI
RX_SCI_SISR_OFFSET,
RX_SCI_SPMR_OFFSET,
RX_SCI_THRHL_OFFSET,
+ RX_SCI_THRL_OFFSET,
RX_SCI_RDRHL_OFFSET,
+ RX_SCI_RDRL_OFFSET,
RX_SCI_MDDR_OFFSET
};
#endif /* __ASSEMBLER__ */
diff --git a/arch/renesas/src/rx65n/rx65n_eth.c b/arch/renesas/src/rx65n/rx65n_eth.c
index 9b99c1c..cc23813 100644
--- a/arch/renesas/src/rx65n/rx65n_eth.c
+++ b/arch/renesas/src/rx65n/rx65n_eth.c
@@ -1,43 +1,20 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_eth.c
- * 10/100 Base-T Ethernet driver for the RX65N family
- *
- * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
- * Author: Surya <su...@tataelxsi.co.in>
- *
- * This logic derives from the NuttX Ethernet Skeleton driver, STM32 ethernet
- * driver and
- * RX65N-rsk2mb baremetal code
- * This code has a BSD compatible license that requires this copyright notice:
- *
- * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the names NuttX nor Atmel nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
****************************************************************************/
@@ -87,6 +64,7 @@
#include "rx65n_cmtw0.h"
#include <arch/board/board.h>
+#include <arch/board/rx65n_gpio.h>
#if RX65N_NETHERNET > 0
@@ -245,12 +223,12 @@
/* Define the access timing of MII/RMII register */
-#define ETHER_CFG_PHY_MII_WAIT (8) /* Please define the value of 1 or more */
+#define ETHER_CFG_PHY_MII_WAIT (8) /* define the value of 1 or more */
/* Define the waiting time for reset completion of PHY-LSI */
#define ETHER_CFG_PHY_DELAY_RESET (0x00020000L)
-#define ETHER_PHY_STATUS_CHECK_DELAY (20000)
+#define ETHER_PHY_STATUS_CHECK_DELAY (20000)
/* Group AL1 interrupt priority level.
* This definition is not used when EINT interrupt
@@ -267,18 +245,15 @@
/* This setting is reflected in all channels */
-#define ETHER_CFG_USE_LINKSTA (1)
-#if defined(CONFIG_ARCH_RX65N_RSK2MB)
+#define ETHER_CFG_USE_LINKSTA (1)
-#define ETHER_LINKUP (0)
-#define ETHER_LINKDOWN (1)
+#define ETHER_LINKUP (1)
+#define ETHER_LINKDOWN (0)
-#elif defined(CONFIG_ARCH_RX65N_GRROSE)
+/* Multicast filter */
-#define ETHER_LINKUP (1)
-#define ETHER_LINKDOWN (0)
-
-#endif
+#define ETHER_MC_FILTER_OFF (0) /* Multicast frame filter disable */
+#define ETHER_MC_FILTER_ON (1) /* Multicast frame filter enable */
/* Standard PHY Registers */
@@ -290,30 +265,6 @@
#define PHY_REG_AN_LINK_PARTNER (5)
#define PHY_REG_AN_EXPANSION (6)
-#if defined(CONFIG_ARCH_RX65N_RSK2MB)
-#define PHY_STS_REG 0x10
-#define PHY_STS_REG_LINK (1 << 0)
-#elif defined(CONFIG_ARCH_RX65N_GRROSE)
-#define PHY_STS_REG 0x1f
-#define PHY_STS_REG_AUTO_NEG (1 << 12)
-#endif
-
-/* If we want to debug PHY register. Need to define these two macro
- * #define PHY_READ_WRITE_TEST
- * #define PHY_REG_DEBUGGING
- */
-
-#if defined(PHY_READ_WRITE_TEST)
-#if defined(CONFIG_ARCH_RX65N_RSK2MB)
- #define PHY_REG_IDENTIFIER1_DEF_VAL 0x2000
- #define PHY_REG_IDENTIFIER2_DEF_VAL 0x5ce1
-#elif defined(CONFIG_ARCH_RX65N_GRROSE)
- #define PHY_REG_IDENTIFIER1_DEF_VAL 0x0007
- #define PHY_REG_IDENTIFIER2_DEF_VAL 0xc0f0 /* The The default value of LSB 4bit will vary dependent on the silicon revision number */
-#endif
- #define PHY_REG_MII_INT_CONTROL 0x11
-#endif
-
/* Phy Interrupt register */
#define PHY_REG_MICR (17)
@@ -386,7 +337,7 @@
#define NX_ALIGN32 __attribute__((aligned(32)))
/****************************************************************************
- * Private Types
+ * Public Variables
****************************************************************************/
/* Ethernet TX DMA Descriptor */
@@ -420,8 +371,8 @@ struct eth_rxdesc_s
* Private Types
****************************************************************************/
-/* The rx65n_ethmac_s encapsulates all state information for a single hardware
- * interface
+/* The rx65n_ethmac_s encapsulates all state information for a single
+ * hardware interface
*/
struct rx65n_ethmac_s
@@ -456,7 +407,8 @@ struct rx65n_ethmac_s
uint16_t inflight; /* Number of TX transfers "in_flight" */
sq_queue_t freeb; /* The free buffer list */
- uint32_t prevlinkstatus; /* Previous link status to ignore multiple link change interrupt (specific to GR-Rose) */
+ uint32_t prevlinkstatus; /* Previous link status to ignore multiple link change interrupt (specific to GR-Rose) */
+ uint8_t mc_filter_flag; /* Multicast filter */
};
/****************************************************************************
@@ -598,12 +550,6 @@ static int rx65n_phywrite (uint8_t phydevaddr, uint16_t reg_addr,
static uint16_t rx65n_phyread (uint8_t phydevaddr, uint16_t reg_addr,
uint16_t *value);
-#if defined(PHY_READ_WRITE_TEST)
-static int rx65n_phy_read_write_test();
-#endif
-#if defined(PHY_REG_DEBUGGING)
-static void rx65n_phy_reg_dump();
-#endif
void up_enable_irq(int irq);
void up_disable_irq(int irq);
@@ -615,8 +561,7 @@ struct phylinknotification_t
struct phy_notify_s *pclient;
};
-struct phylinknotification_t phylinknotification;
-phylinknotification_t phylinknotification =
+struct phylinknotification_t phylinknotification =
{
NULL, NULL, NULL
};
@@ -887,9 +832,10 @@ static int rx65n_transmit(FAR struct rx65n_ethmac_s *priv)
{
struct eth_txdesc_s *txdesc;
struct eth_txdesc_s *txfirst;
+ uint32_t regval;
- /* The internal (optimal) network buffer size may be configured to be larger
- * than the Ethernet buffer size.
+ /* The internal (optimal) network buffer size may be configured to be
+ * larger than the Ethernet buffer size.
*/
#if OPTIMAL_ETH_BUFSIZE > CONFIG_RX65N_ETH_BUFSIZE
@@ -984,9 +930,11 @@ static int rx65n_transmit(FAR struct rx65n_ethmac_s *priv)
/* Give the descriptor to DMA */
txdesc->tdes0 |= TACT;
- rx65n_putreg(1, RX65N_ETHD_EDTRR);
+ regval = rx65n_getreg(RX65N_ETHD_EDTRR);
+ regval |= (ETHD_EDRRR_TR);
+ rx65n_putreg(regval, RX65N_ETHD_EDTRR);
- txdesc = (struct eth_txdesc_s *)txdesc->tdes3;
+ txdesc = (struct eth_txdesc_s *)txdesc->tdes3;
}
}
else
@@ -1012,7 +960,9 @@ static int rx65n_transmit(FAR struct rx65n_ethmac_s *priv)
*/
txdesc->tdes0 |= TACT;
- rx65n_putreg(1, RX65N_ETHD_EDTRR);
+ regval = rx65n_getreg(RX65N_ETHD_EDTRR);
+ regval |= (ETHD_EDRRR_TR);
+ rx65n_putreg(regval, RX65N_ETHD_EDTRR);
/* Point to the next available TX descriptor */
@@ -1178,8 +1128,8 @@ static int rx65n_txpoll(struct net_driver_s *dev)
}
}
- /* If zero is returned, the polling will continue until all connections have
- * been examined.
+ /* If zero is returned, the polling will continue until all connections
+ * have been examined.
*/
return 0;
@@ -1217,9 +1167,9 @@ static void rx65n_dopoll(FAR struct rx65n_ethmac_s *priv)
* another packet for transmission.
*
* In a race condition, TACT may be cleared BUT still not available
- * because rx65n_freeframe() has not yet run. If rx65n_freeframe() has run,
- * the buffer1 pointer (tdes2) will be nullified (and inflight should be <
- * CONFIG_RX65N_ETH_NTXDESC).
+ * because rx65n_freeframe() has not yet run. If rx65n_freeframe() has
+ * run, the buffer1 pointer (tdes2) will be nullified (and inflight
+ * should be < CONFIG_RX65N_ETH_NTXDESC).
*/
if ((priv->txhead->tdes0 & TACT) == 0 &&
@@ -1290,7 +1240,8 @@ static void rx65n_enableint(FAR struct rx65n_ethmac_s *priv, uint32_t ierbit)
* None
****************************************************************************/
-static void rx65n_disableint(FAR struct rx65n_ethmac_s *priv, uint32_t ierbit)
+static void rx65n_disableint(FAR struct rx65n_ethmac_s *priv,
+ uint32_t ierbit)
{
uint32_t regval;
@@ -1325,6 +1276,7 @@ static void rx65n_freesegment(FAR struct rx65n_ethmac_s *priv,
{
struct eth_rxdesc_s *rxdesc;
int i;
+ uint32_t regval;
ninfo("rxfirst: %p segments: %d\n", rxfirst, segments);
@@ -1351,7 +1303,9 @@ static void rx65n_freesegment(FAR struct rx65n_ethmac_s *priv,
if (!(rx65n_getreg(RX65N_ETHD_EDRRR)))
{
- rx65n_putreg(0x00000001, RX65N_ETHD_EDRRR);
+ regval = rx65n_getreg(RX65N_ETHD_EDRRR);
+ regval |= (ETHD_EDRRR_RR);
+ rx65n_putreg(regval, RX65N_ETHD_EDRRR);
}
/* Reset the segment management logic */
@@ -1391,8 +1345,8 @@ static int rx65n_recvframe(FAR struct rx65n_ethmac_s *priv)
ninfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
- /* Check if there are free buffers. We cannot receive new frames in this
- * design unless there is at least one free buffer.
+ /* Check if there are free buffers. We cannot receive new frames in
+ * this design unless there is at least one free buffer.
*/
if (!rx65n_isfreebuffer(priv))
@@ -1492,8 +1446,8 @@ static int rx65n_recvframe(FAR struct rx65n_ethmac_s *priv)
(priv->dev.d_statistics.rx_packets)++;
#endif
- /* Return success, remembering where we should re-start scanning
- * and resetting the segment scanning logic
+ /* Return success, remembering where we should re-start
+ * scanning and resetting the segment scanning logic
*/
priv->rxhead = (struct eth_rxdesc_s *)rxdesc->rdes3;
@@ -1570,7 +1524,9 @@ static void rx65n_receive(FAR struct rx65n_ethmac_s *priv)
{
#ifdef CONFIG_NET_PKT
- /* When packet sockets are enabled, feed the frame into the packet tap */
+ /* When packet sockets are enabled, feed the frame into the packet
+ * tap
+ */
pkt_input(&priv->dev);
#endif
@@ -1737,7 +1693,8 @@ static void rx65n_receive(FAR struct rx65n_ethmac_s *priv)
* Function: rx65n_freeframe
*
* Description:
- * Scans the TX descriptors and frees the buffers of completed TX transfers.
+ * Scans the TX descriptors and frees the buffers of completed TX
+ * transfers.
*
* Input Parameters:
* priv - Reference to the driver state structure
@@ -1905,6 +1862,7 @@ static void rx65n_interrupt_work(FAR void *arg)
#if defined(CONFIG_ARCH_PHY_INTERRUPT)
uint16_t phyreg;
int phyreg_read_status;
+ int irqno = 0;
#endif
DEBUGASSERT(priv);
@@ -1923,22 +1881,21 @@ static void rx65n_interrupt_work(FAR void *arg)
rx65n_putreg(regval, RX65N_ETH_ECSR);
#if defined(CONFIG_ARCH_PHY_INTERRUPT)
-#if defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
- phyreg_read_status = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_STATUS, &phyreg);
- regval = (uint32_t)(phyreg & 0x04) >> 2;
-#elif defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
- phyreg_read_status = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_STS_REG, &phyreg);
- regval = (uint32_t)(phyreg & 0x01);
-#endif
+ phyreg_read_status = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR,
+ PHY_STS_READ_REG, &phyreg);
+ if (OK == phyreg_read_status)
+ {
+ regval = (uint32_t)(phyreg & PHY_STS_BIT_MASK)
+ >> PHY_STS_SHIFT_COUNT;
+ }
+
if (regval != priv->prevlinkstatus) /* Check link status by 0th bit */
{
/* Link UP or DOWN status */
if (phylinknotification.phandler != NULL)
{
- phylinknotification.phandler(NULL, (FAR void *)NULL,
+ phylinknotification.phandler(irqno, (FAR void *)NULL,
(FAR void *)phylinknotification.pclient);
priv->prevlinkstatus = regval;
}
@@ -2165,9 +2122,9 @@ static void rx65n_poll_work(FAR void *arg)
* a transmit in progress, we will miss TCP time state updates?
*
* In a race condition, TACT may be cleared BUT still not available
- * because rx65n_freeframe() has not yet run. If rx65n_freeframe() has run,
- * the buffer1 pointer (tdes2) will be nullified (and inflight should be <
- * CONFIG_RX65N_ETH_NTXDESC).
+ * because rx65n_freeframe() has not yet run. If rx65n_freeframe() has
+ * run, the buffer1 pointer (tdes2) will be nullified (and inflight
+ * should be < CONFIG_RX65N_ETH_NTXDESC).
*/
net_lock();
@@ -2300,6 +2257,7 @@ static int rx65n_ifup(struct net_driver_s *dev)
up_enable_irq(RX65N_ETH_IRQ);
+ priv->prevlinkstatus = ETHER_LINKUP;
rx65n_checksetup();
return OK;
}
@@ -2341,7 +2299,7 @@ static int rx65n_ifdown(struct net_driver_s *dev)
/* Put the EMAC in its reset, non-operational state.
* This should be a known configuration that will guarantee
- * the rx65n_ifup() alwayssuccessfully brings the interface back up.
+ * the rx65n_ifup() always successfully brings the interface back up.
*/
ret = rx65n_ethreset(priv);
@@ -2354,6 +2312,9 @@ static int rx65n_ifdown(struct net_driver_s *dev)
/* Mark the device "down" */
priv->ifup = false;
+
+ priv->prevlinkstatus = ETHER_LINKDOWN;
+
leave_critical_section(flags);
return ret;
}
@@ -2452,13 +2413,28 @@ static int rx65n_txavail(struct net_driver_s *dev)
****************************************************************************/
#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6)
-/* Currently Not supported, Need to update this code when support added */
-
static uint32_t rx65n_calcethcrc(const uint8_t *data, size_t length)
{
uint32_t crc = 0xffffffff;
+ size_t i;
+ int j;
+
+ for (i = 0; i < length; i++)
+ {
+ for (j = 0; j < 8; j++)
+ {
+ if (((crc >> 31) ^ (data[i] >> j)) & 0x01)
+ {
+ /* x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */
- /* Currently not implemented */
+ crc = (crc << 1) ^ 0x04c11db7;
+ }
+ else
+ {
+ crc = crc << 1;
+ }
+ }
+ }
return ~crc;
}
@@ -2483,11 +2459,25 @@ static uint32_t rx65n_calcethcrc(const uint8_t *data, size_t length)
****************************************************************************/
#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6)
-/* Currently Not supported, Need to update this code when support added */
-
static int rx65n_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
{
- /* Currnently not implemented */
+ uint32_t regval;
+ uint32_t crc;
+ uint32_t hashindex;
+ uint32_t temp;
+ uint32_t registeraddress;
+ regval = 0;
+
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+
+ crc = rx65n_calcethcrc(mac, 6);
+
+ hashindex = (crc >> 26) & 0x3f;
+
+ /* RX65N do not support add on mac multi cast feature because related
+ * hash table mac multi cast register is not supported in RX65N.
+ */
return OK;
}
@@ -2512,12 +2502,27 @@ static int rx65n_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
*
****************************************************************************/
-/* Currently Not supported, Need to update this code when support added */
-
#ifdef CONFIG_NET_MCASTGROUP
static int rx65n_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
{
- /* Currnently not implemented */
+ uint32_t crc;
+ uint32_t hashindex;
+ uint32_t temp;
+ uint32_t registeraddress;
+
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+
+ /* Remove the MAC address to the hardware multicast hash table */
+
+ crc = rx65n_calcethcrc(mac, 6);
+
+ hashindex = (crc >> 26) & 0x3f;
+
+ /* RX65N do not support add on mac multi cast feature because related
+ * hash table multi cast mac register not available. This function is
+ * not need to implement.
+ */
return OK;
}
@@ -2576,7 +2581,9 @@ static void rx65n_txdescinit(FAR struct rx65n_ethmac_s *priv)
txdesc->tdes1 = (uint32_t)(1 << 16);
txdesc->tdes2 = 0;
- /* Initialize the next descriptor with the Next Descriptor Polling Enable */
+ /* Initialize the next descriptor with the Next Descriptor Polling
+ * Enable
+ */
if (i < (CONFIG_RX65N_ETH_NTXDESC - 1))
{
@@ -2656,7 +2663,9 @@ static void rx65n_rxdescinit(FAR struct rx65n_ethmac_s *priv)
rxdesc->rdes2 = (uint32_t)&priv->rxbuffer[i*CONFIG_RX65N_ETH_BUFSIZE];
- /* Initialize the next descriptor with the Next Descriptor Polling Enable */
+ /* Initialize the next descriptor with the Next Descriptor Polling
+ * Enable
+ */
if (i < (CONFIG_RX65N_ETH_NRXDESC - 1))
{
@@ -2715,10 +2724,6 @@ static void rx65n_rxdescinit(FAR struct rx65n_ethmac_s *priv)
#ifdef CONFIG_NETDEV_IOCTL
static int rx65n_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
-#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
- FAR struct rx65n_ethmac_s *priv =
- (FAR struct rx65n_ethmac_s *)dev->d_private;
-#endif
int ret;
switch (cmd)
@@ -2885,7 +2890,6 @@ int arch_phy_irq(FAR const char *intf, xcpt_t handler, void *arg,
irqstate_t flags;
phy_enable_t enabler;
- int irq;
DEBUGASSERT(intf);
@@ -2942,7 +2946,7 @@ int arch_phy_irq(FAR const char *intf, xcpt_t handler, void *arg,
* Arguments : pause -
* Using state of pause frames
* Return Value : none
- ***************************************************************************/
+ ****************************************************************************/
void phy_start_autonegotiate (uint8_t pause)
{
@@ -2974,7 +2978,9 @@ void phy_start_autonegotiate (uint8_t pause)
PHY_AN_ADVERTISEMENT_SELECTOR);
}
- /* Configure what the PHY and the Ethernet controller on this board supports */
+ /* Configure what the PHY and the Ethernet controller on this board
+ * supports
+ */
rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR,
PHY_REG_AN_ADVERTISEMENT, regval);
@@ -2989,7 +2995,7 @@ void phy_start_autonegotiate (uint8_t pause)
* PHY access channel is powered off.
* Arguments : none
* Return Value : none
- ***************************************************************************/
+ ****************************************************************************/
void rx65n_power_on_control(void)
{
@@ -3039,7 +3045,7 @@ void rx65n_power_on_control(void)
* Arguments : mode -
* phy mode
* Return Value : none
- ***************************************************************************/
+ ****************************************************************************/
void rx65n_ether_set_phy_mode(uint8_t mode)
{
@@ -3049,7 +3055,7 @@ void rx65n_ether_set_phy_mode(uint8_t mode)
/* PFENET -> PHYMODE0 is Enabled Ethernet Channel0 to use MII Mode; */
- putreg8(0x10, RX65N_MPC_PFENET);
+ putreg8(ETH_PFENET_MII_MODE, RX65N_MPC_PFENET);
}
else if (PHY_RMII_SET_MODE == mode)
{
@@ -3057,7 +3063,7 @@ void rx65n_ether_set_phy_mode(uint8_t mode)
/* PFENET -> PHYMODE0 is Enabled Ethernet Channel0 to use MII Mode; */
- putreg8(0x00, RX65N_MPC_PFENET);
+ putreg8(ETH_PFENET_RMII_MODE, RX65N_MPC_PFENET);
}
else
{
@@ -3065,7 +3071,7 @@ void rx65n_ether_set_phy_mode(uint8_t mode)
/* PFENET -> PHYMODE0 is Enabled Ethernet Channel0 to use MII Mode; */
- putreg8(0x10, RX65N_MPC_PFENET);
+ putreg8(ETH_PFENET_MII_MODE, RX65N_MPC_PFENET);
}
}
@@ -3075,7 +3081,7 @@ void rx65n_ether_set_phy_mode(uint8_t mode)
* Arguments : pdata -
* pointer to store the data read
* Return Value : none
- ***************************************************************************/
+ ****************************************************************************/
static void phy_reg_read (uint16_t *pdata)
{
@@ -3098,32 +3104,33 @@ static void phy_reg_read (uint16_t *pdata)
{
/* Reset All Flags of PIR */
- rx65n_putreg(0x00000000, RX65N_ETH_PIR);
+ rx65n_putreg(ETH_PIR_RESET_ALL, RX65N_ETH_PIR);
}
for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
{
/* Setting MDC of PIR */
- rx65n_putreg(0x00000001, RX65N_ETH_PIR);
+ rx65n_putreg(ETH_PIR_SET_MDC, RX65N_ETH_PIR);
}
reg_data <<= 1;
/* MDI read */
- reg_data |= (uint16_t) (((rx65n_getreg(RX65N_ETH_PIR)) & 0x00000008) >> 3);
+ reg_data |= (uint16_t) (((rx65n_getreg(RX65N_ETH_PIR))
+ & ETH_PIR_MDI) >> 3);
for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
{
/* Setting MDC of PIR */
- rx65n_putreg(0x00000001, RX65N_ETH_PIR);
+ rx65n_putreg(ETH_PIR_SET_MDC, RX65N_ETH_PIR);
}
for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
{
- rx65n_putreg(0x00000000, RX65N_ETH_PIR); /* Reset All Flags of PIR */
+ rx65n_putreg(ETH_PIR_RESET_ALL, RX65N_ETH_PIR); /* Reset All Flags of PIR */
}
databitcnt--;
@@ -3140,7 +3147,7 @@ static void phy_reg_read (uint16_t *pdata)
* reg_addr -
* address of the PHY register
* Return Value : read value
- ***************************************************************************/
+ ****************************************************************************/
static uint16_t rx65n_phyread (uint8_t phydevaddr, uint16_t reg_addr,
uint16_t *value)
@@ -3199,14 +3206,14 @@ void rx65n_ether_enable_icu(void)
IEN(ICU, GROUPAL1) = 1;
}
-/***************************************************************************
+/****************************************************************************
* Function Name: rx65n_phy_trans_zto0
* Description : Performs bus release so that PHY can drive data
* : for read operation
* Arguments : ether_channel -
* Ethernet channel number
* Return Value : none
- ***************************************************************************/
+ ****************************************************************************/
static void rx65n_phy_trans_zto0 ()
{
@@ -3221,24 +3228,24 @@ static void rx65n_phy_trans_zto0 ()
{
/* Resetting All flags of PIR */
- rx65n_putreg(0x00000000, RX65N_ETH_PIR);
+ rx65n_putreg(ETH_PIR_RESET_ALL, RX65N_ETH_PIR);
}
for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
{
- rx65n_putreg(0x00000001, RX65N_ETH_PIR); /* Setting MDC of PIR */
+ rx65n_putreg(ETH_PIR_SET_MDC, RX65N_ETH_PIR); /* Setting MDC of PIR */
}
for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
{
- rx65n_putreg(0x00000001, RX65N_ETH_PIR); /* Setting MDC of PIR */
+ rx65n_putreg(ETH_PIR_SET_MDC, RX65N_ETH_PIR); /* Setting MDC of PIR */
}
for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
{
/* Resetting All flags of PIR */
- rx65n_putreg(0x00000000, RX65N_ETH_PIR);
+ rx65n_putreg(ETH_PIR_RESET_ALL, RX65N_ETH_PIR);
}
}
@@ -3249,7 +3256,7 @@ static void rx65n_phy_trans_zto0 ()
* Arguments : ether_channel -
* Ethernet channel number
* Return Value : none
- ***************************************************************************/
+ ****************************************************************************/
static void rx65n_phy_trans_1to0 ()
{
@@ -3272,7 +3279,7 @@ static void rx65n_phy_trans_1to0 ()
* option -
* mode
* Return Value : none
- ***************************************************************************/
+ ****************************************************************************/
static void rx65n_phy_reg_set (uint8_t phydevaddr, uint16_t reg_addr,
int32_t option)
@@ -3324,7 +3331,7 @@ static void rx65n_phy_reg_set (uint8_t phydevaddr, uint16_t reg_addr,
* Arguments : data -
* value to write
* Return Value : none
- ***************************************************************************/
+ ****************************************************************************/
static void rx65n_phy_reg_write (uint16_t data)
{
@@ -3336,7 +3343,7 @@ static void rx65n_phy_reg_write (uint16_t data)
* of "IEEE 802.3-2008_section2".
*/
- databitcnt = 16; /* Number of bit to write */
+ databitcnt = 16; /* Number of bit to write */
while (databitcnt > 0) /* writing 1 bit per loop */
{
if (0 == (data & 0x8000))
@@ -3358,7 +3365,7 @@ static void rx65n_phy_reg_write (uint16_t data)
* Description : Outputs 1 to the MII interface
* Arguments : none
* Return Value : none
- ***************************************************************************/
+ ****************************************************************************/
static void rx65n_phy_mii_write1 ()
{
@@ -3375,28 +3382,28 @@ static void rx65n_phy_mii_write1 ()
{
/* Setting MDO and MMD and by default MDI */
- rx65n_putreg(0x00000006, RX65N_ETH_PIR);
+ rx65n_putreg(ETH_PIR_SET_MDO_MMD, RX65N_ETH_PIR);
}
for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
{
/* Setting MDO, MMD and MDC and by default MDI */
- rx65n_putreg(0x00000007, RX65N_ETH_PIR);
+ rx65n_putreg(ETH_PIR_SET_MDO_MMD_MDC, RX65N_ETH_PIR);
}
for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
{
/* Setting MDO, MMD and MDC and by default MDI */
- rx65n_putreg(0x00000007, RX65N_ETH_PIR);
+ rx65n_putreg(ETH_PIR_SET_MDO_MMD_MDC, RX65N_ETH_PIR);
}
for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
{
/* Setting MDO and MMD and by default MDI */
- rx65n_putreg(0x00000006, RX65N_ETH_PIR);
+ rx65n_putreg(ETH_PIR_SET_MDO_MMD, RX65N_ETH_PIR);
}
}
@@ -3405,7 +3412,7 @@ static void rx65n_phy_mii_write1 ()
* Description : Outputs 0 to the MII interface
* Arguments : none
* Return Value : none
- ***************************************************************************/
+ ****************************************************************************/
static void rx65n_phy_mii_write0(void)
{
@@ -3421,28 +3428,28 @@ static void rx65n_phy_mii_write0(void)
{
/* Setting MMD and by default MDI */
- rx65n_putreg(0x00000002, RX65N_ETH_PIR);
+ rx65n_putreg(ETH_PIR_SET_MMD, RX65N_ETH_PIR);
}
for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
{
/* Setting MDC and MMD and by default MDI */
- rx65n_putreg(0x00000003, RX65N_ETH_PIR);
+ rx65n_putreg(ETH_PIR_SET_MMD_MDC, RX65N_ETH_PIR);
}
for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
{
/* Setting MDC and MMD and by default MDI */
- rx65n_putreg(0x00000003, RX65N_ETH_PIR);
+ rx65n_putreg(ETH_PIR_SET_MMD_MDC, RX65N_ETH_PIR);
}
for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--)
{
/* Setting MMD and by default MDI */
- rx65n_putreg(0x00000002, RX65N_ETH_PIR);
+ rx65n_putreg(ETH_PIR_SET_MMD, RX65N_ETH_PIR);
}
}
@@ -3453,7 +3460,7 @@ static void rx65n_phy_mii_write0(void)
* "1" is output via the MII management interface.
* Arguments : none
* Return Value : none
- ***************************************************************************/
+ ****************************************************************************/
static void rx65n_phy_preamble(void)
{
@@ -3487,7 +3494,7 @@ static void rx65n_phy_preamble(void)
* data -
* value
* Return Value : none
- ***************************************************************************/
+ ****************************************************************************/
static int rx65n_phywrite (uint8_t phydevaddr, uint16_t reg_addr,
uint16_t data)
@@ -3510,7 +3517,7 @@ static int rx65n_phywrite (uint8_t phydevaddr, uint16_t reg_addr,
* Description : Writes to a ETHERC/EDMAC register
* Arguments : none
* Return Value : none
- ***************************************************************************/
+ ****************************************************************************/
void rx65n_ether_interrupt_init(void)
{
@@ -3542,180 +3549,6 @@ void rx65n_ether_interrupt_init(void)
}
/****************************************************************************
- * Function: rx65n_phy_reg_dump
- *
- * Description:
- * Test PHY all register read and dump
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * OK on success; Negated errno on failure.
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-#if defined(PHY_REG_DEBUGGING)
-static void rx65n_phy_reg_dump(void)
-{
- int reg_offset;
- int ret;
- uint16_t reg;
-
- /* Info: BMCR(Basic mode control register) offset 0x0;
- * BMSR(Basic mode control register) offset 0x1
- * PHSTS(Phy status register) offset 0x10
- */
-
- for (reg_offset = 0; reg_offset < 32; reg_offset++)
- {
- reg = 0;
- ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, reg_offset, ®);
-
- /* Read data from reg variable while debugging */
-
- if (ret < 0)
- {
- nerr("ERROR: Failed to read register: %d\n", reg_offset);
- }
- }
-}
-#endif
-
-/****************************************************************************
- * Function: rx65n_phy_read_write_test
- *
- * Description:
- * Test PHY read write operation
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * OK on success; Negated errno on failure.
- *
- * Assumptions:
- *
- ****************************************************************************/
-
-#if defined(PHY_READ_WRITE_TEST)
-static int rx65n_phy_read_write_test(void)
-{
- int ret;
- uint16_t reg;
- reg = 0;
- ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, PHY_REG_IDENTIFIER1, ®);
- if (reg != PHY_REG_IDENTIFIER1_DEF_VAL)
- {
- nerr("ERROR: Failed to read PHY IDENTIFIER1 register\n");
- return R_PHY_ERROR;
- }
-
- ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, PHY_REG_IDENTIFIER2, ®);
-#if defined(CONFIG_ARCH_RX65N_GRROSE)
-
- /* The default value of LSB 4 bit will vary
- * dependent on the silicon revision number.
- */
-
- reg = reg & 0xfff0;
-#endif
- if (reg != PHY_REG_IDENTIFIER2_DEF_VAL)
- {
- nerr("ERROR: Failed to read PHY IDENTIFIER2 register\n");
- nerr("ERROR: Failed to read PHY IDENTIFIER2 register\n");
- return R_PHY_ERROR;
- }
-
-#if defined(CONFIG_ARCH_RX65N_RSK2MB)
- ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, 0x0000);
- ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, ®);
- if (reg != 0x0000)
- {
- nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n");
- return R_PHY_ERROR;
- }
-
- ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, 0x0001);
- ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, ®);
- if (reg != 0x0001)
- {
- nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n");
- return R_PHY_ERROR;
- }
-
- ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, 0x0002);
- ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, ®);
- if (reg != 0x0002)
- {
- nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n");
- return R_PHY_ERROR;
- }
-
- ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, 0x0003);
- ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, ®);
- if (reg != 0x0003)
- {
- nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n");
- return R_PHY_ERROR;
- }
-
- ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, 0x0004);
- ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, ®);
- if (reg != 0x0004)
- {
- nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n");
- return R_PHY_ERROR;
- }
-
- ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, 0x0005);
- ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, ®);
- if (reg != 0x0005)
- {
- nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n");
- return R_PHY_ERROR;
- }
-
- ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, 0x0006);
- ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, ®);
- if (reg != 0x0006)
- {
- nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n");
- return R_PHY_ERROR;
- }
-
- ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, 0x0007);
- ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR,
- PHY_REG_MII_INT_CONTROL, ®);
- if (reg != 0x0007)
- {
- nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n");
- return R_PHY_ERROR;
- }
-#endif
-
- return R_PHY_OK;
-}
-#endif
-
-/****************************************************************************
* Function: rx65n_phyinit
*
* Description:
@@ -3819,12 +3652,11 @@ static int rx65n_phyinit(FAR struct rx65n_ethmac_s *priv)
priv->mbps100 = 1;
break;
}
+
#endif
#endif
-
-error_with_reset_timeout:
-error_with_auto_neg_timeout:
-
+ error_with_reset_timeout:
+ error_with_auto_neg_timeout:
return ret;
}
@@ -3958,6 +3790,16 @@ static int rx65n_macconfig(FAR struct rx65n_ethmac_s *priv)
rx65n_putreg(regval, RX65N_ETHD_EESIPR);
rx65n_macaddress(priv);
+
+ #ifdef CONFIG_NET_ICMPv6
+ /* Set up the IPv6 multicast address */
+
+ /* Not supported So commented */
+
+ /* rx65n_ipv6multicast(priv); */
+
+ #endif
+
return OK;
}
@@ -4024,13 +3866,62 @@ static void rx65n_macaddress(FAR struct rx65n_ethmac_s *priv)
*
****************************************************************************/
-/* Currently Not supported, Need to update this code when support added */
-
#ifdef CONFIG_NET_ICMPv6
static void rx65n_ipv6multicast(FAR struct rx65n_ethmac_s *priv)
{
- /* Currnently not implemented */
+ struct net_driver_s *dev;
+ uint16_t tmp16;
+ uint8_t mac[6];
+
+ /* For ICMPv6, we need to add the IPv6 multicast address
+ *
+ * For IPv6 multicast addresses, the Ethernet MAC is derived by
+ * the four low-order octets OR'ed with the MAC 33:33:00:00:00:00,
+ * so for example the IPv6 address FF02:DEAD:BEEF::1:3 would map
+ * to the Ethernet MAC address 33:33:00:01:00:03.
+ *
+ * NOTES: This appears correct for the ICMPv6 Router Solicitation
+ * Message, but the ICMPv6 Neighbor Solicitation message seems to
+ * use 33:33:ff:01:00:03.
+ */
+
+ mac[0] = 0x33;
+ mac[1] = 0x33;
+
+ dev = &priv->dev;
+ tmp16 = dev->d_ipv6addr[6];
+ mac[2] = 0xff;
+ mac[3] = tmp16 >> 8;
+
+ tmp16 = dev->d_ipv6addr[7];
+ mac[4] = tmp16 & 0xff;
+ mac[5] = tmp16 >> 8;
+
+ ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+
+ (void)rx65n_addmac(dev, mac);
+
+#ifdef CONFIG_NET_ICMPv6_AUTOCONF
+ /* Add the IPv6 all link-local nodes Ethernet address. This is the
+ * address that we expect to receive ICMPv6 Router Advertisement
+ * packets.
+ */
+
+ (void)rx65n_addmac(dev, g_ipv6_ethallnodes.ether_addr_octet);
+
+#endif /* CONFIG_NET_ICMPv6_AUTOCONF */
+#ifdef CONFIG_NET_ICMPv6_ROUTER
+ /* Add the IPv6 all link-local routers Ethernet address. This is the
+ * address that we expect to receive ICMPv6 Router Solicitation
+ * packets.
+ */
+
+ (void)rx65n_addmac(dev, g_ipv6_ethallrouters.ether_addr_octet);
+
+#endif /* CONFIG_NET_ICMPv6_ROUTER */
}
+
#endif /* CONFIG_NET_ICMPv6 */
/****************************************************************************
@@ -4068,28 +3959,12 @@ static int rx65n_ethconfig(FAR struct rx65n_ethmac_s *priv)
* Currently we are using MII
*/
-#if defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB) || \
- defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
- rx65n_ether_set_phy_mode(PHY_MII_SET_MODE);
-#else
- rx65n_ether_set_phy_mode(PHY_RMII_SET_MODE);
-#endif
+ rx65n_ether_set_phy_mode(PHY_SET_MODE_REG);
/* ETHERC/EDMAC Power on */
rx65n_power_on_control();
- /* Test PHY read write */
-
-#if defined(PHY_READ_WRITE_TEST)
- ret = rx65n_phy_read_write_test();
- if (ret < 0)
- {
- nerr("ERROR: PHY read write failed\n");
- return ret;
- }
-#endif
-
/* Initialize the PHY */
ninfo("Initialize the PHY\n");
@@ -4164,23 +4039,30 @@ static int rx65n_ethconfig(FAR struct rx65n_ethmac_s *priv)
/* Continuous reception number of Broadcast frame */
- rx65n_putreg(0x00000000, RX65N_ETH_BCFRR);
-
-#ifdef CONFIG_NET_MCASTGROUP
+ regval = rx65n_getreg(RX65N_ETH_BCFRR);
+ regval |= (ETH_BCFRR_BCF);
+ rx65n_putreg(regval, RX65N_ETH_BCFRR);
+ regval = rx65n_getreg(RX65N_ETHD_TRSCER);
+ if (ETHER_MC_FILTER_ON == priv->mc_filter_flag)
+ {
/* Reflect the EESR.RMAF bit status in the RD0.RFS bit
* in the receive descriptor
*/
- rx65n_putreg(0x00000000, RX65N_ETHD_TRSCER);
-#else
-
+ regval &= (~((ETHD_TRSCER_RMAFCE) | (ETHD_TRSCER_RRFCE)));
+ rx65n_putreg(regval, RX65N_ETHD_TRSCER);
+ }
+ else
+ {
/* Don't reflect the EESR.RMAF bit status in the RD0.RFS
* bit in the receive descriptor
*/
- rx65n_putreg(0x00000080, RX65N_ETHD_TRSCER);
-#endif
+ regval &= (~(ETHD_TRSCER_RRFCE));
+ regval |= (ETHD_TRSCER_RMAFCE);
+ rx65n_putreg(regval, RX65N_ETHD_TRSCER);
+ }
/* Threshold of Tx_FIFO */
@@ -4188,7 +4070,9 @@ static int rx65n_ethconfig(FAR struct rx65n_ethmac_s *priv)
/* transmit fifo is 1968 bytes & receive fifo is 2048 bytes */
- rx65n_putreg(0x00000707, RX65N_ETHD_FDR);
+ regval = rx65n_getreg(RX65N_ETHD_FDR);
+ regval |= ((ETHD_FDR_RFD) | (ETHD_FDR_TFD));
+ rx65n_putreg(regval, RX65N_ETHD_FDR);
/* Configure receiving method */
@@ -4197,11 +4081,15 @@ static int rx65n_ethconfig(FAR struct rx65n_ethmac_s *priv)
* b31:b1 Reserved set to 0
*/
- rx65n_putreg(0x00000001, RX65N_ETHD_RMCR);
+ regval = rx65n_getreg(RX65N_ETHD_RMCR);
+ regval |= (ETHD_RMCR_RNR);
+ rx65n_putreg(regval, RX65N_ETHD_RMCR);
/* Transmit Interrupt Setting */
- rx65n_putreg(0x00000011, RX65N_ETHD_TRIMD);
+ regval = rx65n_getreg(RX65N_ETHD_TRIMD);
+ regval |= ((ETHD_TRIMD_TIS) | (ETHD_TRIMD_TIM));
+ rx65n_putreg(regval, RX65N_ETHD_TRIMD);
/* ETHERC/EDMAC enabling Interrupt */
@@ -4240,13 +4128,9 @@ static int rx65n_ethconfig(FAR struct rx65n_ethmac_s *priv)
/* Start DMA reception */
- rx65n_putreg(0x00000001, RX65N_ETHD_EDRRR);
-
- /* Phy debugging */
-
-#if defined(PHY_REG_DEBUGGING)
- rx65n_phy_reg_dump();
-#endif
+ regval = rx65n_getreg(RX65N_ETHD_EDRRR);
+ regval |= (ETHD_EDRRR_RR);
+ rx65n_putreg(regval, RX65N_ETHD_EDRRR);
return ret;
}
@@ -4277,39 +4161,13 @@ int rx65n_ethinitialize(int intf)
/* Initialize hardware mac address */
-#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
- uint8_t mac[6];
- mac[0] = 0x74;
- mac[1] = 0x90;
- mac[2] = 0x50;
- mac[3] = 0x00;
- mac[4] = 0x9c;
- mac[5] = 0x91;
-#elif defined (CONFIG_ARCH_BOARD_RX65N_RSK2MB)
uint8_t mac[6];
- mac[0] = 0x74;
- mac[1] = 0x90;
- mac[2] = 0x50;
- mac[3] = 0x00;
- mac[4] = 0x9c;
- mac[5] = 0x94;
-#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
- uint8_t mac[6];
- mac[0] = 0x74;
- mac[1] = 0x90;
- mac[2] = 0x50;
- mac[3] = 0x00;
- mac[4] = 0x9c;
- mac[5] = 0x97;
-#else
- uint8_t mac[6];
- mac[0] = 0x00;
- mac[1] = 0x00;
- mac[2] = 0x00;
- mac[3] = 0x00;
- mac[4] = 0x00;
- mac[5] = 0x00;
-#endif
+ mac[0] = RX65N_MAC_ADDRL & 0xff;
+ mac[1] = (RX65N_MAC_ADDRL & 0xff00) >> 8;
+ mac[2] = (RX65N_MAC_ADDRL & 0xff0000) >> 16;
+ mac[3] = (RX65N_MAC_ADDRL & 0xff000000) >> 24;
+ mac[4] = RX65N_MAC_ADDRH & 0xff;
+ mac[5] = (RX65N_MAC_ADDRH & 0xff00) >> 8;
ninfo("intf: %d\n", intf);
@@ -4343,6 +4201,10 @@ int rx65n_ethinitialize(int intf)
priv->dev.d_private = (void *)g_rx65nethmac;
+ /* Multi cast flag */
+
+ priv->mc_filter_flag = ETHER_MC_FILTER_OFF;
+
/* hw mac address */
priv->dev.d_mac.ether.ether_addr_octet[0] = mac[0];
diff --git a/arch/renesas/src/rx65n/rx65n_eth.h b/arch/renesas/src/rx65n/rx65n_eth.h
index 1084523..ea840b7 100644
--- a/arch/renesas/src/rx65n/rx65n_eth.h
+++ b/arch/renesas/src/rx65n/rx65n_eth.h
@@ -1,50 +1,36 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_eth.h
*
- * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_RX65N_ETH_H
#define __ARCH_RENESAS_SRC_RX65N_RX65N_ETH_H
/****************************************************************************
* Included Files
- ***************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
- ***************************************************************************/
+ ****************************************************************************/
/* Understood PHY types */
@@ -54,10 +40,6 @@
#define EMAC0_INTF 0
-/****************************************************************************
- * Public Functions
- ***************************************************************************/
-
#ifndef __ASSEMBLY__
#undef EXTERN
@@ -70,10 +52,6 @@ extern "C"
#endif
/****************************************************************************
- * Public Functions
- ***************************************************************************/
-
-/****************************************************************************
* Function: rx65n_ethinitialize
*
* Description:
@@ -135,4 +113,4 @@ void rx65n_txtimeout_expiry(int argc, uint32_t arg, ...);
#endif
#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_RENESAS_SRC_RX65N_RX65N_ETH_H */
+#endif /* __ARCH_RENESAS_SRC_RX65N_RX65N_ETH_H */
\ No newline at end of file
diff --git a/arch/renesas/src/rx65n/rx65n_hardware_setup.c b/arch/renesas/src/rx65n/rx65n_hardware_setup.c
index 94aedb6..64b3d9c 100644
--- a/arch/renesas/src/rx65n/rx65n_hardware_setup.c
+++ b/arch/renesas/src/rx65n/rx65n_hardware_setup.c
@@ -1,36 +1,20 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_hardware_setup.c
*
- * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
- * Author: Anjana <an...@tataelxsi.co.in>
- * Surya <su...@tataelxsi.co.in>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
****************************************************************************/
@@ -82,7 +66,6 @@ void r_system_init(void)
/* Set peripheral settings */
r_cgc_create();
- r_icu_create();
r_port_create();
#ifdef CONFIG_RX65N_EMAC0
@@ -98,9 +81,6 @@ void r_system_init(void)
/* Enable protection */
SYSTEM.PRCR.WORD = 0xa500;
-
- r_config_icu_software_start();
- r_config_icu_software2_start();
}
/****************************************************************************
diff --git a/arch/renesas/src/rx65n/rx65n_initialstate.c b/arch/renesas/src/rx65n/rx65n_initialstate.c
index 4cd55f6..70e208a 100644
--- a/arch/renesas/src/rx65n/rx65n_initialstate.c
+++ b/arch/renesas/src/rx65n/rx65n_initialstate.c
@@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_initialstate.c
*
- * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
- * Author: Anjana <an...@tataelxsi.co.in>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
+ ****************************************************************************/
/****************************************************************************
* Included Files
diff --git a/arch/renesas/src/rx65n/rx65n_lowputc.c b/arch/renesas/src/rx65n/rx65n_lowputc.c
index 95acdcc..28c8c3b 100644
--- a/arch/renesas/src/rx65n/rx65n_lowputc.c
+++ b/arch/renesas/src/rx65n/rx65n_lowputc.c
@@ -1,35 +1,20 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_lowputc.c
*
- * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
- * Author: Anjana <an...@tataelxsi.co.in>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
****************************************************************************/
@@ -51,7 +36,7 @@
* Pre-processor Definitions
****************************************************************************/
-/* Configuration **********************************************************/
+/* Configuration ************************************************************/
/* Is there a serial console? */
@@ -160,7 +145,7 @@
#define RX_SMR_VALUE (RX_SMR_MODE|RX_SMR_PARITY|RX_SMR_STOP)
-/* Clocking ***************************************************************/
+/* Clocking *****************************************************************/
#define RX_DIVISOR (8 * RX_SCI_BAUD)
#define RX_BRR ((RX_PCLKB / RX_DIVISOR) - 1)
diff --git a/arch/renesas/src/rx65n/rx65n_macrodriver.h b/arch/renesas/src/rx65n/rx65n_macrodriver.h
index 27fc714..6168841 100644
--- a/arch/renesas/src/rx65n/rx65n_macrodriver.h
+++ b/arch/renesas/src/rx65n/rx65n_macrodriver.h
@@ -1,35 +1,20 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_macrodriver.h
*
- * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
- * Author: Anjana <an...@tataelxsi.co.in>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
****************************************************************************/
@@ -37,7 +22,7 @@
#define __ARCH_RENESAS_SRC_RX65N_STATUS_H
/****************************************************************************
- * Pre-processor Definitions
+ * Included Files
****************************************************************************/
#include "rx65n/iodefine.h"
diff --git a/arch/renesas/src/rx65n/rx65n_port.c b/arch/renesas/src/rx65n/rx65n_port.c
index 796cdae..8fd9e77 100644
--- a/arch/renesas/src/rx65n/rx65n_port.c
+++ b/arch/renesas/src/rx65n/rx65n_port.c
@@ -25,6 +25,7 @@
#include "rx65n_macrodriver.h"
#include "rx65n_port.h"
#include "arch/board/board.h"
+#include "arch/board/rx65n_gpio.h"
/****************************************************************************
* Public Functions
@@ -39,87 +40,8 @@
void r_port_create(void)
{
-#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
-
- /* LED_PORTINIT(0); */
-
- PORT0.PODR.BYTE = _04_PM2_OUTPUT_1 | _08_PM3_OUTPUT_1 | _20_PM5_OUTPUT_1;
- PORT5.PODR.BYTE = _40_PM6_OUTPUT_1;
- PORT7.PODR.BYTE = _08_PM3_OUTPUT_1;
- PORT9.PODR.BYTE = _08_PM3_OUTPUT_1;
- PORTJ.PODR.BYTE = _20_PM5_OUTPUT_1;
- PORT0.DSCR.BYTE = _00_PM2_HIDRV_OFF;
- PORT0.DSCR2.BYTE = _00_PM2_HISPEED_OFF;
- PORT5.DSCR.BYTE = _20_PM5_HIDRV_ON | _00_PM6_HIDRV_OFF;
- PORT5.DSCR2.BYTE = _00_PM5_HISPEED_OFF | _00_PM6_HISPEED_OFF;
- PORT7.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
- PORT9.DSCR.BYTE = _00_PM3_HIDRV_OFF;
- PORT9.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
- PORT0.PMR.BYTE = 0x00u;
- PORT0.PDR.BYTE = _04_PM2_MODE_OUTPUT | _08_PM3_MODE_OUTPUT |
- _20_PM5_MODE_OUTPUT | _50_PDR0_DEFAULT;
- PORT5.PMR.BYTE = 0x00u;
- PORT5.PDR.BYTE = _20_PM5_MODE_OUTPUT | _40_PM6_MODE_OUTPUT |
- _80_PDR5_DEFAULT;
- PORT7.PMR.BYTE = 0x00u;
- PORT7.PDR.BYTE = _08_PM3_MODE_OUTPUT;
- PORT9.PMR.BYTE = 0x00u;
- PORT9.PDR.BYTE = _08_PM3_MODE_OUTPUT | _F0_PDR9_DEFAULT;
- PORTJ.PMR.BYTE = 0x00u;
- PORTJ.PDR.BYTE = _20_PM5_MODE_OUTPUT | _D7_PDRJ_DEFAULT;
-#elif defined (CONFIG_ARCH_BOARD_RX65N_RSK2MB)
-
- /* LED_PORTINIT(0); */
-
- PORT0.PODR.BYTE = _04_PM2_OUTPUT_1 | _08_PM3_OUTPUT_1 | _20_PM5_OUTPUT_1;
- PORT5.PODR.BYTE = _40_PM6_OUTPUT_1;
- PORT7.PODR.BYTE = _08_PM3_OUTPUT_1;
- PORT9.PODR.BYTE = _08_PM3_OUTPUT_1;
- PORTJ.PODR.BYTE = _20_PM5_OUTPUT_1;
- PORT0.DSCR.BYTE = _00_PM2_HIDRV_OFF;
- PORT0.DSCR2.BYTE = _00_PM2_HISPEED_OFF;
- PORT5.DSCR.BYTE = _20_PM5_HIDRV_ON | _00_PM6_HIDRV_OFF;
- PORT5.DSCR2.BYTE = _00_PM5_HISPEED_OFF | _00_PM6_HISPEED_OFF;
- PORT7.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
- PORT9.DSCR.BYTE = _00_PM3_HIDRV_OFF;
- PORT9.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
- PORT0.PMR.BYTE = 0x00u;
- PORT0.PDR.BYTE = _04_PM2_MODE_OUTPUT | _08_PM3_MODE_OUTPUT |
- _20_PM5_MODE_OUTPUT | _50_PDR0_DEFAULT;
- PORT5.PMR.BYTE = 0x00u;
- PORT5.PDR.BYTE = _20_PM5_MODE_OUTPUT | _40_PM6_MODE_OUTPUT |
- _80_PDR5_DEFAULT;
- PORT7.PMR.BYTE = 0x00u;
- PORT7.PDR.BYTE = _08_PM3_MODE_OUTPUT;
- PORT9.PMR.BYTE = 0x00u;
- PORT9.PDR.BYTE = _08_PM3_MODE_OUTPUT | _F0_PDR9_DEFAULT;
- PORTJ.PMR.BYTE = 0x00u;
- PORTJ.PDR.BYTE = _20_PM5_MODE_OUTPUT | _D7_PDRJ_DEFAULT;
-#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
- LED_PORTINIT(0);
-
- /* SCI0(UART) direction */
-
- PORT2.PODR.BIT.B2 = 0; PORT2.PMR.BIT.B2 = 0; PORT2.PDR.BIT.B2 = 1;
-
- /* SCI2(UART) direction */
-
- PORT1.PODR.BIT.B4 = 0; PORT1.PMR.BIT.B4 = 0; PORT1.PDR.BIT.B4 = 1;
-
- /* SCI5(UART) direction */
-
- PORTC.PODR.BIT.B4 = 0; PORTC.PMR.BIT.B4 = 0; PORTC.PDR.BIT.B4 = 1;
-
- /* SCI6(UART) direction */
-
- PORT3.PODR.BIT.B4 = 0; PORT3.PMR.BIT.B4 = 0; PORT3.PDR.BIT.B4 = 1;
-
- /* SCI8(RS485) direction */
-
- PORTC.PODR.BIT.B5 = 0; PORTC.PMR.BIT.B5 = 0; PORTC.PDR.BIT.B5 = 1;
-#else
-# error "No Selection for PORT definition in rx65n_port.c"
-#endif
+ led_port_create();
+ sci_port_create();
}
#ifdef CONFIG_RX65N_EMAC0
@@ -157,187 +79,4 @@ void r_ether_port_configuration(void)
PORT0.PMR.BIT.B5 = 0;
PORT0.PMR.BIT.B7 = 0;
}
-
-void r_ether_pheriperal_enable(void)
-{
-#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
-
- /* TODO */
-
-#elif defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
-
- /* Set ET0_TX_CLK pin */
-
- MPC.PC4PFS.BYTE = 0x11u;
- PORTC.PMR.BIT.B4 = 1u;
-
- /* Set ET0_RX_CLK pin */
-
- MPC.P76PFS.BYTE = 0x11u;
- PORT7.PMR.BIT.B6 = 1u;
-
- /* Set ET0_TX_EN pin */
-
- MPC.P80PFS.BYTE = 0x11u;
- PORT8.PMR.BIT.BT0 = 1u;
-
- /* Set ET0_ETXD3 pin */
-
- MPC.PC6PFS.BYTE = 0x11u;
- PORTC.PMR.BIT.B6 = 1u;
-
- /* Set ET0_ETXD2 pin */
-
- MPC.PC5PFS.BYTE = 0x11u;
- PORTC.PMR.BIT.B5 = 1u;
-
- /* Set ET0_ETXD1 pin */
-
- MPC.P82PFS.BYTE = 0x11u;
- PORT8.PMR.BIT.B2 = 1u;
-
- /* Set ET0_ETXD0 pin */
-
- MPC.P81PFS.BYTE = 0x11u;
- PORT8.PMR.BIT.B1 = 1u;
-
- /* Set ET0_TX_ER pin */
-
- MPC.PC3PFS.BYTE = 0x11u;
- PORTC.PMR.BIT.B3 = 1u;
-
- /* Set ET0_RX_DV pin */
-
- MPC.PC2PFS.BYTE = 0x11u;
- PORTC.PMR.BIT.B2 = 1u;
-
- /* Set ET0_ERXD3 pin */
-
- MPC.PC0PFS.BYTE = 0x11u;
- PORTC.PMR.BIT.BT0 = 1u;
-
- /* Set ET0_ERXD2 pin */
-
- MPC.PC1PFS.BYTE = 0x11u;
- PORTC.PMR.BIT.B1 = 1u;
-
- /* Set ET0_ERXD1 pin */
-
- MPC.P74PFS.BYTE = 0x11u;
- PORT7.PMR.BIT.B4 = 1u;
-
- /* Set ET0_ERXD0 pin */
-
- MPC.P75PFS.BYTE = 0x11u;
- PORT7.PMR.BIT.B5 = 1u;
-
- /* Set ET0_RX_ER pin */
-
- MPC.P77PFS.BYTE = 0x11u;
- PORT7.PMR.BIT.B7 = 1u;
-
- /* Set ET0_CRS pin */
-
- MPC.P83PFS.BYTE = 0x11u;
- PORT8.PMR.BIT.B3 = 1u;
-
- /* Set ET0_COL pin */
-
- MPC.PC7PFS.BYTE = 0x11u;
- PORTC.PMR.BIT.B7 = 1u;
-
- /* Set ET0_MDC pin */
-
- MPC.P72PFS.BYTE = 0x11u;
- PORT7.PMR.BIT.B2 = 1u;
-
- /* Set ET0_MDIO pin */
-
- MPC.P71PFS.BYTE = 0x11u;
- PORT7.PMR.BIT.B1 = 1u;
-
- /* Set ET0_LINKSTA pin */
-
- MPC.P54PFS.BYTE = 0x11u;
- PORT5.PMR.BIT.B4 = 1u;
-
- /* Set ET0_LINKSTA pin */
-
- MPC.P34PFS.BYTE = 0x11u;
- PORT3.PMR.BIT.B4 = 1u;
-
-#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
-
- /* Set ET0_MDC(PA4_ET_MDC) pin */
-
- MPC.PA4PFS.BYTE = 0x11u;
- PORTA.PMR.BIT.B4 = 1u;
-
- /* Set ET0_MDIO(PA3_ET_MDIO) pin */
-
- MPC.PA3PFS.BYTE = 0x11u;
- PORTA.PMR.BIT.B3 = 1u;
-
- /* Set REF50CK0 (PB2_ET_CLK) pin */
-
- MPC.PB2PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.B2 = 1u;
-
- /* Set RMII0_CRS_DV(PB7_ET_CRS) pin */
-
- MPC.PB7PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.B7 = 1u;
-
- /* Set RMII0_RXD0(PB1_ET_RXD0) pin */
-
- MPC.PB1PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.B1 = 1u;
-
- /* Set RMII0_RXD1(PB0_ET_RXD1) pin */
-
- MPC.PB0PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.BT0 = 1u;
-
- /* Set RMII0_RX_ER(PB3_ET_RXER) pin */
-
- MPC.PB3PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.B3 = 1u;
-
- /* Set RMII0_ETXD0(PB5_ET_TXD0) pin */
-
- MPC.PB5PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.B5 = 1u;
-
- /* Set RMII0_ETXD1(PB6_ET_TXD1) pin */
-
- MPC.PB6PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.B6 = 1u;
-
- /* Set RMII0_TXD_EN(PB4_ET_TXEN) pin */
-
- MPC.PB4PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.B4 = 1u;
-
- /* Set RXD2 pin */
-
- MPC.P52PFS.BYTE = 0x0au;
- PORT5.PMR.BIT.B2 = 1u;
-
- /* Set TXD2 pin */
-
- PORT5.PODR.BYTE |= 0x01u;
- MPC.P50PFS.BYTE = 0x0au;
- PORT5.PDR.BYTE |= 0x01u;
-
- /* Set ET0_LINKSTA(PA5_ET_LINK) pin */
-
- MPC.PA5PFS.BYTE = 0x11u;
- PORTA.PMR.BIT.B5 = 1u;
-
- /* Set ETHER reset(PA6_ET_RST) pin */
-
- MPC.PA6PFS.BYTE = 0x12u;
- PORTA.PMR.BIT.B6 = 1u;
-#endif
-}
#endif
diff --git a/arch/renesas/src/rx65n/rx65n_port.h b/arch/renesas/src/rx65n/rx65n_port.h
index 9b5b637..b49c4be 100644
--- a/arch/renesas/src/rx65n/rx65n_port.h
+++ b/arch/renesas/src/rx65n/rx65n_port.h
@@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_port.h
*
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- * Author: Anjana <an...@tataelxsi.co.in>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_PORT_H
#define __ARCH_RENESAS_SRC_RX65N_PORT_H
@@ -283,7 +268,7 @@
/****************************************************************************
* Public Function Prototypes
- ***************************************************************************/
+ ****************************************************************************/
/****************************************************************************
* Name: r_port_create
@@ -317,22 +302,6 @@ void r_port_create(void);
#ifdef CONFIG_RX65N_EMAC0
void r_ether_port_configuration(void);
-
-/****************************************************************************
- * Name: r_ether_pheriperal_enable
- *
- * Description:
- * Ethernet Pheriperal enabling
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
-void r_ether_pheriperal_enable(void);
#endif
#endif /* __ARCH_RENESAS_SRC_RX65N_PORT_H */
diff --git a/arch/renesas/src/rx65n/rx65n_rtc.c b/arch/renesas/src/rx65n/rx65n_rtc.c
index c3f8119..0967343 100644
--- a/arch/renesas/src/rx65n/rx65n_rtc.c
+++ b/arch/renesas/src/rx65n/rx65n_rtc.c
@@ -91,7 +91,7 @@ struct alm_cbinfo_s
struct prd_cbinfo_s
{
volatile periodiccb_t prd_cb; /* Client callback function */
- volatile FAR void *prd_arg; /* Argument to pass with the callback function */
+ volatile FAR void *prd_arg; /* Argument to pass with the callback function */
};
#endif
@@ -562,7 +562,9 @@ int up_rtc_settime(FAR const struct timespec *tp)
volatile uint8_t dummy_byte;
volatile uint16_t dummy_word;
- /* Break out the time values (note that the time is set only to units of seconds) */
+ /* Break out the time values (note that the time is set only to units of
+ * seconds)
+ */
(void)gmtime_r(&tp->tv_sec, &newtime);
rtc_dumptime(&newtime, "Setting time");
@@ -1050,7 +1052,7 @@ int rx65n_rtc_cancelperiodic(void)
IEN(RTC, PRD) = 0U;
- /* Clear IR flag of PRD interrupt*/
+ /* Clear IR flag of PRD interrupt */
IR(RTC, PRD) = 0U;
@@ -1059,7 +1061,7 @@ int rx65n_rtc_cancelperiodic(void)
RTC.RCR1.BIT.PIE = 0U;
while (0U != RTC.RCR1.BIT.PIE)
{
- /* Wait for this write to complete.*/
+ /* Wait for this write to complete. */
}
return OK;
@@ -1071,7 +1073,7 @@ int rx65n_rtc_cancelperiodic(void)
int rx65n_rtc_cancelcarry(void)
{
- /* Clear IR flag of CUP interrupt*/
+ /* Clear IR flag of CUP interrupt */
IR(PERIB, INTB176) = 0U;
diff --git a/arch/renesas/src/rx65n/rx65n_schedulesigaction.c b/arch/renesas/src/rx65n/rx65n_schedulesigaction.c
index 153c09e..63931fd 100644
--- a/arch/renesas/src/rx65n/rx65n_schedulesigaction.c
+++ b/arch/renesas/src/rx65n/rx65n_schedulesigaction.c
@@ -120,18 +120,20 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
tcb->xcp.sigdeliver = sigdeliver;
tcb->xcp.saved_pc = g_current_regs[REG_PC];
+ tcb->xcp.saved_sr = g_current_regs[REG_PSW];
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
g_current_regs[REG_PC] = (uint32_t)up_sigdeliver;
+ g_current_regs[REG_PSW] |= 0x00030000;
/* And make sure that the saved context in the TCB
* is the same as the interrupt return context.
*/
- up_copystate(tcb->xcp.regs, (uint32_t *)&g_current_regs);
+ up_copystate(tcb->xcp.regs, (uint32_t *)g_current_regs);
}
}
@@ -150,7 +152,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
tcb->xcp.sigdeliver = sigdeliver;
tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
- tcb->xcp.saved_sr = tcb->xcp.regs[REG_PSW];
+ tcb->xcp.saved_sr = tcb->xcp.regs[REG_PSW];
/* Then set up to vector to the trampoline with interrupts
* disabled
diff --git a/arch/renesas/src/rx65n/rx65n_sci.c b/arch/renesas/src/rx65n/rx65n_sci.c
index cae59cd..0ed8110 100644
--- a/arch/renesas/src/rx65n/rx65n_sci.c
+++ b/arch/renesas/src/rx65n/rx65n_sci.c
@@ -30,6 +30,7 @@
#include "up_arch.h"
#include "up_internal.h"
#include "rx65n_definitions.h"
+#include "arch/board/rx65n_gpio.h"
/****************************************************************************
* Public Data
@@ -368,163 +369,6 @@ static inline void rx_mpc_disable(void)
}
/****************************************************************************
- * Name: sci0_init_port
- *
- * Description:
- * SCI0 Initialization
- ****************************************************************************/
-
-#ifdef CONFIG_RX65N_SCI0
-static inline void sci0_init_port(void)
-{
-#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE
- /* Set RXD0 pin (P21) */
-
- MPC.P21PFS.BYTE = 0x0au;
- PORT2.PMR.BIT.B1 = 1u;
-
- /* Set TXD0 pin (P20) */
-
- PORT2.PODR.BIT.BT0 = 1u;
- MPC.P20PFS.BYTE = 0x0au;
- PORT2.PDR.BIT.BT0 = 1u;
- PORT2.PMR.BIT.BT0 = 1u;
-#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */
-}
-#endif
-
-/****************************************************************************
- * Name: sci1_init_port
- *
- * Description:
- * SCI1 Initialization
- ****************************************************************************/
-
-#ifdef CONFIG_RX65N_SCI1
-static inline void sci1_init_port(void)
-{
-#ifdef CONFIG_ARCH_BOARD_RX65N_RSK2MB
- /* Set RXD1 pin (PF2) */
-
- MPC.PF2PFS.BYTE = 0x0au;
- PORTF.PMR.BIT.B2 = 1u;
-
- /* Set TXD1 pin (PF1) */
-
- PORTF.PODR.BIT.B1 = 1u;
- MPC.PF1PFS.BYTE = 0x0au;
- PORTF.PDR.BIT.B1 = 1u;
- PORTF.PMR.BIT.B1 = 1u;
-
-#endif /* CONFIG_ARCH_BOARD_RX65N_RSK2MB */
-
-#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE
- /* Set RXD1 pin (P30) */
-
- MPC.P30PFS.BYTE = 0x0au;
- PORT3.PMR.BIT.BT0 = 1u;
-
- /* Set TXD1 pin (P26) */
-
- PORT2.PODR.BIT.B6 = 1u;
- MPC.P26PFS.BYTE = 0x0au;
- PORT2.PDR.BIT.B6 = 1u;
- PORT2.PMR.BIT.B6 = 1u;
-#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */
-}
-#endif
-
-/****************************************************************************
- * Name: sci2_init_port
- *
- * Description:
- * SCI2 Initialization
- ****************************************************************************/
-
-#ifdef CONFIG_RX65N_SCI2
-static inline void sci2_init_port(void)
-{
-#ifdef CONFIG_ARCH_BOARD_RX65N_RSK1MB
- /* Set RXD2 pin (P52) */
-
- MPC.P52PFS.BYTE = 0x0au;
- PORT5.PMR.BIT.B2 = 1u;
-
- /* Set TXD2 pin (P50) */
-
- PORT5.PODR.BIT.BT0 = 1u;
- MPC.P50PFS.BYTE = 0x0au;
- PORT5.PDR.BIT.BT0 = 1u;
- PORT5.PMR.BIT.BT0 = 1u;
-#endif /* CONFIG_ARCH_BOARD_RX65N_RSK1MB */
-
-#ifdef CONFIG_ARCH_BOARD_RX65N_RSK2MB
- /* Set RXD2 pin (P52) */
-
- MPC.P52PFS.BYTE = 0x0au;
- PORT5.PMR.BIT.B2 = 1u;
-
- /* Set TXD2 pin (P50) */
-
- PORT5.PODR.BIT.BT0 = 1u;
- MPC.P50PFS.BYTE = 0x0au;
- PORT5.PDR.BIT.BT0 = 1u;
- PORT5.PMR.BIT.BT0 = 1u;
-#endif /* CONFIG_ARCH_BOARD_RX65N_RSK2MB */
-
-#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE
- /* Set RXD2 pin (P12) */
-
- MPC.P12PFS.BYTE = 0x0au;
- PORT1.PMR.BIT.B2 = 1u;
-
- /* Set TXD2 pin (P13) */
-
- PORT1.PODR.BIT.B3 = 1u;
- MPC.P13PFS.BYTE = 0x0au;
- PORT1.PDR.BIT.B3 = 1u;
- PORT1.PMR.BIT.B3 = 1u;
-#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */
-}
-#endif
-
-/****************************************************************************
- * Name: sci3_init_port
- *
- * Description:
- * SCI3 Initialization
- ****************************************************************************/
-
-#ifdef CONFIG_RX65N_SCI3
-static inline void sci3_init_port(void)
-{
- /* Set RXD3 pin (PXX)
- * MPC.PXXPFS.BYTE = 0x0au;
- * PORTX.PMR.BIT.BX = 1u;
- * Set TXD3 pin (PXX)
- * PORTX.PODR.BIT.BX = 1u;
- * MPC.PXXPFS.BYTE = 0x0au;
- * PORTX.PDR.BIT.BX = 1u;
- * PORTX.PMR.BIT.BX = 1u;
- */
-
-#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE
- /* Set RXD2 pin (P25) */
-
- MPC.P25PFS.BYTE = 0x0au;
- PORT2.PMR.BIT.B5 = 1u;
-
- /* Set TXD2 pin (P23) */
-
- PORT2.PODR.BIT.B3 = 1u;
- MPC.P23PFS.BYTE = 0x0au;
- PORT2.PDR.BIT.B3 = 1u;
- PORT2.PMR.BIT.B3 = 1u;
-#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */
-}
-#endif
-
-/****************************************************************************
* Name: sci4_init_port
*
* Description:
@@ -547,60 +391,6 @@ static inline void sci4_init_port(void)
#endif
/****************************************************************************
- * Name: sci5_init_port
- *
- * Description:
- * SCI5 Initialization
- ****************************************************************************/
-
-#ifdef CONFIG_RX65N_SCI5
-static inline void sci5_init_port(void)
-{
-#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE
-
- /* Set RXD3 pin (PC2) */
-
- MPC.PC2PFS.BYTE = 0x0au;
- PORTC.PMR.BIT.B2 = 1u;
-
- /* Set TXD3 pin (PC3) */
-
- PORTC.PODR.BIT.B3 = 1u;
- MPC.PC3PFS.BYTE = 0x0au;
- PORTC.PDR.BIT.B3 = 1u;
- PORTC.PMR.BIT.B3 = 1u;
-#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */
-}
-#endif
-
-/****************************************************************************
- * Name: sci6_init_port
- *
- * Description:
- * SCI6 Initialization
- ****************************************************************************/
-
-#ifdef CONFIG_RX65N_SCI6
-static inline void sci6_init_port(void)
-{
-#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE
-
- /* Set RXD6 pin (P33) */
-
- MPC.P33PFS.BYTE = 0x0au;
- PORT3.PMR.BIT.B3 = 1u;
-
- /* Set TXD6 pin (P32) */
-
- PORT3.PODR.BIT.B2 = 1u;
- MPC.P32PFS.BYTE = 0x0au;
- PORT3.PDR.BIT.B2 = 1u;
- PORT3.PMR.BIT.B2 = 1u;
-#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */
-}
-#endif
-
-/****************************************************************************
* Name: sci7_init_port
*
* Description:
@@ -623,46 +413,6 @@ static inline void sci7_init_port(void)
#endif
/****************************************************************************
- * Name: sci8_init_port
- *
- * Description:
- * SCI8 Initialization
- ****************************************************************************/
-
-#ifdef CONFIG_RX65N_SCI8
-static inline void sci8_init_port(void)
-{
-#ifdef CONFIG_ARCH_BOARD_RX65N_RSK2MB
- /* Set RXD8 pin (PJ1) */
-
- MPC.PJ1PFS.BYTE = 0x0au;
- PORTJ.PMR.BIT.B1 = 1u;
-
- /* Set TXD8 pin (PJ2) */
-
- PORTJ.PODR.BIT.B2 = 1u;
- MPC.PJ2PFS.BYTE = 0x0au;
- PORTJ.PDR.BIT.B2 = 1u;
- PORTJ.PMR.BIT.B2 = 1u;
-#endif /* CONFIG_ARCH_BOARD_RX65N_RSK2MB */
-
-#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE
- /* Set RXD8 pin (PC6) */
-
- MPC.PC6PFS.BYTE = 0x0au;
- PORTC.PMR.BIT.B6 = 1u;
-
- /* Set TXD8 pin (PC7) */
-
- PORTC.PODR.BIT.B7 = 1u;
- MPC.PC7PFS.BYTE = 0x0au;
- PORTC.PDR.BIT.B7 = 1u;
- PORTC.PMR.BIT.B7 = 1u;
-#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */
-}
-#endif
-
-/****************************************************************************
* Name: sci9_init_port
*
* Description:
@@ -729,42 +479,6 @@ static inline void sci11_init_port(void)
#endif
/****************************************************************************
- * Name: sci12_init_port
- *
- * Description:
- * SCI12 Initialization
- ****************************************************************************/
-
-#ifdef CONFIG_RX65N_SCI12
-static inline void sci12_init_port(void)
-{
-#ifdef CONFIG_ARCH_BOARD_RX65N_RSK2MB
-
- /* Set RXD12 pin */
-
- MPC.PE2PFS.BYTE = 0x0cu;
- PORTE.PMR.BYTE |= 0x04u;
-
- /* Set TXD12 pin */
-
- PORTE.PODR.BYTE |= 0x02u;
- MPC.PE1PFS.BYTE = 0x0cu;
- PORTE.PDR.BYTE |= 0x02u;
-#endif
-
- /* Set RXD12 pin (PXX)
- * MPC.PXXPFS.BYTE = 0x0au;
- * PORTX.PMR.BIT.BX = 1u;
- * Set TXD12 pin (PXX)
- * PORTX.PODR.BIT.BX = 1u;
- * MPC.PXXPFS.BYTE = 0x0au;
- * PORTX.PDR.BIT.BX = 1u;
- * PORTX.PMR.BIT.BX = 1u;
- */
-}
-#endif
-
-/****************************************************************************
* Name: r_sci0_create
*
* Description:
@@ -906,16 +620,16 @@ void r_sci1_create(void)
{
rx_mpc_enable();
MSTP(SCI1) = 0u; /* Cancel SCI1 module stop state */
- IPR(SCI1, RXI1) = 15; /* Set interrupt priority */
- IPR(SCI1, TXI1) = 15; /* Set interrupt priority */
- SCI1.SCR.BYTE = 0u; /* Clear the control register */
+ IPR(SCI1, RXI1) = 15; /* Set interrupt priority */
+ IPR(SCI1, TXI1) = 15; /* Set interrupt priority */
+ SCI1.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
SCI1.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED;
- SCI1.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */
- SCI1.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */
- SCI1.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */
+ SCI1.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */
+ SCI1.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */
+ SCI1.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */
/* Set control registers */
@@ -1035,8 +749,8 @@ void r_sci2_create(void)
{
rx_mpc_enable();
MSTP(SCI2) = 0u; /* Cancel SCI2 module stop state */
- IPR(SCI2, RXI2) = 15; /* Set interrupt priority */
- IPR(SCI2, TXI2) = 15; /* Set interrupt priority */
+ IPR(SCI2, RXI2) = 15; /* Set interrupt priority */
+ IPR(SCI2, TXI2) = 15; /* Set interrupt priority */
SCI2.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@@ -1163,8 +877,8 @@ void r_sci3_create(void)
{
rx_mpc_enable();
MSTP(SCI3) = 0u; /* Cancel SCI3 module stop state */
- IPR(SCI3, RXI3) = 15; /* Set interrupt priority */
- IPR(SCI3, TXI3) = 15; /* Set interrupt priority */
+ IPR(SCI3, RXI3) = 15; /* Set interrupt priority */
+ IPR(SCI3, TXI3) = 15; /* Set interrupt priority */
SCI3.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@@ -1223,8 +937,8 @@ void r_sci3_stop(void)
{
SCI3.SCR.BIT.TE = 0u; /* Disable serial transmit */
SCI3.SCR.BIT.RE = 0u; /* Disable serial receive */
- SCI3.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
- SCI3.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
+ SCI3.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
+ SCI3.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
IEN(SCI3, TXI3) = 0u;
ICU.GENBL0.BIT.EN6 = 0u;
IR(SCI3, TXI3) = 0u;
@@ -1291,9 +1005,9 @@ MD_STATUS r_sci3_serial_send(uint8_t * const tx_buf, uint16_t tx_num)
void r_sci4_create(void)
{
rx_mpc_enable();
- MSTP(SCI4) = 0u; /* Cancel SCI4 module stop state */
- IPR(SCI4, RXI4) = 15; /* Set interrupt priority */
- IPR(SCI4, TXI4) = 15; /* Set interrupt priority */
+ MSTP(SCI4) = 0u; /* Cancel SCI4 module stop state */
+ IPR(SCI4, RXI4) = 15; /* Set interrupt priority */
+ IPR(SCI4, TXI4) = 15; /* Set interrupt priority */
SCI4.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@@ -1423,8 +1137,8 @@ void r_sci5_create(void)
{
rx_mpc_enable();
MSTP(SCI5) = 0u; /* Cancel SCI0 module stop state */
- IPR(SCI5, RXI5) = 15; /* Set interrupt priority */
- IPR(SCI5, TXI5) = 15; /* Set interrupt priority */
+ IPR(SCI5, RXI5) = 15; /* Set interrupt priority */
+ IPR(SCI5, TXI5) = 15; /* Set interrupt priority */
SCI5.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@@ -1483,8 +1197,8 @@ void r_sci5_stop(void)
{
SCI5.SCR.BIT.TE = 0u; /* Disable serial transmit */
SCI5.SCR.BIT.RE = 0u; /* Disable serial receive */
- SCI5.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
- SCI5.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
+ SCI5.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
+ SCI5.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
IEN(SCI5, TXI5) = 0u;
ICU.GENBL0.BIT.EN10 = 0u;
IR(SCI5, TXI5) = 0u;
@@ -1612,8 +1326,8 @@ void r_sci6_stop(void)
{
SCI6.SCR.BIT.TE = 0u; /* Disable serial transmit */
SCI6.SCR.BIT.RE = 0u; /* Disable serial receive */
- SCI6.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
- SCI6.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
+ SCI6.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
+ SCI6.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
IEN(SCI6, TXI6) = 0u;
ICU.GENBL0.BIT.EN12 = 0u;
IR(SCI6, TXI6) = 0u;
@@ -1680,9 +1394,9 @@ MD_STATUS r_sci6_serial_send(uint8_t * const tx_buf, uint16_t tx_num)
void r_sci7_create(void)
{
rx_mpc_enable();
- MSTP(SCI7) = 0u; /* Cancel SCI7 module stop state */
- IPR(SCI7, RXI7) = 15; /* Set interrupt priority */
- IPR(SCI7, TXI7) = 15; /* Set interrupt priority */
+ MSTP(SCI7) = 0u; /* Cancel SCI7 module stop state */
+ IPR(SCI7, RXI7) = 15; /* Set interrupt priority */
+ IPR(SCI7, TXI7) = 15; /* Set interrupt priority */
SCI7.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@@ -1743,7 +1457,7 @@ void r_sci7_stop(void)
SCI7.SCR.BIT.TE = 0u; /* Disable serial transmit */
SCI7.SCR.BIT.RE = 0u; /* Disable serial receive */
SCI7.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
- SCI7.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
+ SCI7.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
IEN(SCI7, TXI7) = 0u;
IR(SCI7, TXI7) = 0u;
IEN(SCI7, RXI7) = 0u;
@@ -1810,9 +1524,9 @@ MD_STATUS r_sci7_serial_send(uint8_t * const tx_buf, uint16_t tx_num)
void r_sci8_create(void)
{
rx_mpc_enable();
- MSTP(SCI8) = 0u; /* Cancel SCI8 module stop state */
- IPR(SCI8, RXI8) = 15; /* Set interrupt priority */
- IPR(SCI8, TXI8) = 15; /* Set interrupt priority */
+ MSTP(SCI8) = 0u; /* Cancel SCI8 module stop state */
+ IPR(SCI8, RXI8) = 15; /* Set interrupt priority */
+ IPR(SCI8, TXI8) = 15; /* Set interrupt priority */
SCI8.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@@ -1873,7 +1587,7 @@ void r_sci8_stop(void)
SCI8.SCR.BIT.TE = 0u; /* Disable serial transmit */
SCI8.SCR.BIT.RE = 0u; /* Disable serial receive */
SCI8.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
- SCI8.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
+ SCI8.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
IEN(SCI8, TXI8) = 0u;
IR(SCI8, TXI8) = 0u;
IEN(SCI8, RXI8) = 0u;
@@ -1940,9 +1654,9 @@ MD_STATUS r_sci8_serial_send(uint8_t * const tx_buf, uint16_t tx_num)
void r_sci9_create(void)
{
rx_mpc_enable();
- MSTP(SCI9) = 0u; /* Cancel SCI9 module stop state */
- IPR(SCI9, RXI9) = 15; /* Set interrupt priority */
- IPR(SCI9, TXI9) = 15; /* Set interrupt priority */
+ MSTP(SCI9) = 0u; /* Cancel SCI9 module stop state */
+ IPR(SCI9, RXI9) = 15; /* Set interrupt priority */
+ IPR(SCI9, TXI9) = 15; /* Set interrupt priority */
SCI9.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@@ -2003,7 +1717,7 @@ void r_sci9_stop(void)
SCI9.SCR.BIT.TE = 0u; /* Disable serial transmit */
SCI9.SCR.BIT.RE = 0u; /* Disable serial receive */
SCI9.SCR.BIT.TIE = 0u; /* disable TXI interrupt */
- SCI9.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
+ SCI9.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */
IEN(SCI9, TXI9) = 0u;
IR(SCI9, TXI9) = 0u;
IEN(SCI9, RXI9) = 0u;
@@ -2071,8 +1785,8 @@ void r_sci10_create(void)
{
rx_mpc_enable();
MSTP(SCI10) = 0u; /* Cancel SCI10 module stop state */
- IPR(SCI10, RXI10) = 15; /* Set interrupt priority */
- IPR(SCI10, TXI10) = 15; /* Set interrupt priority */
+ IPR(SCI10, RXI10) = 15; /* Set interrupt priority */
+ IPR(SCI10, TXI10) = 15; /* Set interrupt priority */
SCI10.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@@ -2201,9 +1915,9 @@ void r_sci11_create(void)
{
rx_mpc_enable();
MSTP(SCI11) = 0u; /* Cancel SCI11 module stop state */
- IPR(SCI11, RXI11) = 15; /* Set interrupt priority */
- IPR(SCI11, TXI11) = 15; /* Set interrupt priority */
- SCI11.SCR.BYTE = 0u; /* Clear the control register */
+ IPR(SCI11, RXI11) = 15; /* Set interrupt priority */
+ IPR(SCI11, TXI11) = 15; /* Set interrupt priority */
+ SCI11.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
@@ -2330,8 +2044,8 @@ void r_sci12_create(void)
{
rx_mpc_enable();
MSTP(SCI12) = 0u; /* Cancel SCI12 module stop state */
- IPR(SCI12, RXI12) = 15; /* Set interrupt priority */
- IPR(SCI12, TXI12) = 15; /* Set interrupt priority */
+ IPR(SCI12, RXI12) = 15; /* Set interrupt priority */
+ IPR(SCI12, TXI12) = 15; /* Set interrupt priority */
SCI12.SCR.BYTE = 0u; /* Clear the control register */
/* Set clock enable */
diff --git a/arch/renesas/src/rx65n/rx65n_sci.h b/arch/renesas/src/rx65n/rx65n_sci.h
index 73c37c6..e6a0dc5 100644
--- a/arch/renesas/src/rx65n/rx65n_sci.h
+++ b/arch/renesas/src/rx65n/rx65n_sci.h
@@ -1,37 +1,22 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_sci.h
*
- * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
- * Author: Anjana <an...@tataelxsi.co.in>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
#ifndef __ARCH_RENESAS_SRC_RX65N_SCI_H
#define __ARCH_RENESAS_SRC_RX65N_SCI_H
@@ -769,7 +754,7 @@
/****************************************************************************
* Public Function Prototypes
- ***************************************************************************/
+ ****************************************************************************/
/****************************************************************************
* Name: r_sci0_create
diff --git a/arch/renesas/src/rx65n/rx65n_serial.c b/arch/renesas/src/rx65n/rx65n_serial.c
index c2e7604..111b021 100644
--- a/arch/renesas/src/rx65n/rx65n_serial.c
+++ b/arch/renesas/src/rx65n/rx65n_serial.c
@@ -28,6 +28,7 @@
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
+#include <semaphore.h>
#include <string.h>
#include <errno.h>
#include <debug.h>
@@ -255,19 +256,19 @@
struct up_dev_s
{
- uint32_t scibase; /* Base address of SCI registers */
- uint32_t baud; /* Configured baud */
- volatile uint8_t scr; /* Saved SCR value */
- volatile uint8_t ssr; /* Saved SR value */
- uint8_t xmitirq; /* Base IRQ associated with xmit IRQ */
- uint8_t recvirq; /* Base IRQ associated with receive IRQ */
+ uint32_t scibase; /* Base address of SCI registers */
+ uint32_t baud; /* Configured baud */
+ volatile uint8_t scr; /* Saved SCR value */
+ volatile uint8_t ssr; /* Saved SR value */
+ uint8_t xmitirq; /* Base IRQ associated with xmit IRQ */
+ uint8_t recvirq; /* Base IRQ associated with receive IRQ */
uint8_t eriirq;
uint8_t teiirq;
uint32_t grpibase;
uint32_t erimask;
uint32_t teimask;
- uint8_t parity; /* 0=none, 1=odd, 2=even */
- uint8_t bits; /* Number of bits (7 or 8) */
+ uint8_t parity; /* 0=none, 1=odd, 2=even */
+ uint8_t bits; /* Number of bits (7 or 8) */
bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
};
@@ -1198,7 +1199,9 @@ static int up_eriinterrupt(int irq, void *context, void *arg)
priv->ssr = up_serialin(priv, RX_SCI_SSR_OFFSET);
- /* Clear all read related events (probably already done in up_receive)) */
+ /* Clear all read related events (probably already done in
+ * up_receive))
+ */
priv->ssr &= ~(RX_SCISSR_ORER | RX_SCISSR_FER | RX_SCISSR_PER);
up_serialout(priv, RX_SCI_SSR_OFFSET, priv->ssr);
@@ -1223,7 +1226,9 @@ static int up_teiinterrupt(int irq, void *context, void *arg)
priv->ssr = up_serialin(priv, RX_SCI_SSR_OFFSET);
- /* Clear all read related events (probably already done in up_receive)) */
+ /* Clear all read related events (probably already done in
+ * up_receive))
+ */
priv->ssr &= ~(RX_SCISSR_TEND);
up_serialout(priv, RX_SCI_SSR_OFFSET, priv->ssr);
diff --git a/arch/renesas/src/rx65n/rx65n_timerisr.c b/arch/renesas/src/rx65n/rx65n_timerisr.c
index 91c03d5..dfc2ad4 100644
--- a/arch/renesas/src/rx65n/rx65n_timerisr.c
+++ b/arch/renesas/src/rx65n/rx65n_timerisr.c
@@ -1,35 +1,20 @@
/****************************************************************************
* arch/renesas/src/rx65n/rx65n_timerisr.c
*
- * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved.
- * Author: Anjana <an...@tataelxsi.co.in>
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
+ * http://www.apache.org/licenses/LICENSE-2.0
*
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
*
****************************************************************************/
@@ -165,6 +150,6 @@ void up_timer_initialize(void)
/* Start the timer */
reg16 = getreg16(RX65N_CMT_CMSTR0_ADDR);
- reg16 |= RX65N_CMTCMSTR0_STR0; /* Enable TCNT0 */
+ reg16 |= RX65N_CMTCMSTR0_STR0; /* Enable TCNT0 */
putreg16(reg16, RX65N_CMT_CMSTR0_ADDR); /* TCNT0 is counting */
}
diff --git a/arch/renesas/src/rx65n/rx65n_vector_table.c b/arch/renesas/src/rx65n/rx65n_vector_table.c
index 05b6e27..0ce2400 100644
--- a/arch/renesas/src/rx65n/rx65n_vector_table.c
+++ b/arch/renesas/src/rx65n/rx65n_vector_table.c
@@ -210,7 +210,7 @@ const void *except_vectors[] EXVECT_SECT =
r_reserved_exception, /* 0xffffffd8 Reserved */
r_undefined_exception, /* 0xffffffdc Exception */
r_reserved_exception, /* 0xffffffe0 Reserved */
- r_floatingpoint_exception, /* 0xffffffe4 Exception */
+ r_floatingpoint_exception, /* 0xffffffe4 Exception */
r_undefined_exception, /* 0xffffffe8 Reserved */
r_undefined_exception, /* 0xffffffec Reserved */
r_undefined_exception, /* 0xfffffff0 Reserved */
diff --git a/boards/renesas/rx65n/rx65n-grrose/README.txt b/boards/renesas/rx65n/rx65n-grrose/README.txt
index f1734ac..7d1b514 100644
--- a/boards/renesas/rx65n/rx65n-grrose/README.txt
+++ b/boards/renesas/rx65n/rx65n-grrose/README.txt
@@ -11,7 +11,32 @@ Contents
- Serial Console
- LEDs
- Networking
-
+ - IPv6 Integration
+ - HTTP Server Integration on IPv4
+ - DHCP Client Integration on IPv4
+ - DHCP Server Integration on IPv4
+ - FTP Server Integration on IPv4
+ - FTP Client Integration on IPv4
+ - TFTP Client Integration on IPv4
+ - Telnet Server Integration on IPv4
+ - Telnet Client Integration on IPv4
+ - Ustream Socket Integration on IPv4
+ - Udgram Socket Integration on IPv4
+ - SMTP Client Integration on IPv4
+ - Raw Socket Integration
+ - Custom User Socket Integration
+ - IGMPv2 Integration
+ - Inherit telnet server Integration
+ - VNC Server Integration
+ - PPPD Integration
+ - HTTP Client Integration
+ - NTP Client Integration
+ - NFS Client Integration
+ - MLD Integration
+ - ICMPv6 AutoConfig Integration
+ - IP Forwarding Integration for IPv4
+ - DNS Name Resolution Integration for IPv4
+ - LINK MONITOR Integration
- RTC
- Debugging
diff --git a/boards/renesas/rx65n/rx65n-grrose/configs/ipv6/defconfig b/boards/renesas/rx65n/rx65n-grrose/configs/ipv6/defconfig
new file mode 100644
index 0000000..3630ce0
--- /dev/null
+++ b/boards/renesas/rx65n/rx65n-grrose/configs/ipv6/defconfig
@@ -0,0 +1,126 @@
+CONFIG_ARCH_BOARD_RX65N_GRROSE=y
+CONFIG_ARCH_BOARD="rx65n-grrose"
+CONFIG_ARCH_CHIP_R5F565NEHDFP=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH="renesas"
+CONFIG_ARCH_CHIP="rx65n"
+CONFIG_BOARD_LOOPSPERMSEC=15001
+CONFIG_MOTOROLA_SREC=y
+CONFIG_ENDIAN_LITTLE=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_MAX_TASKS=8
+CONFIG_DEBUG_FEATURES=y
+CONFIG_ARCH_INTERRUPTSTACK=1024
+CONFIG_BUILTIN=y
+CONFIG_ETH0_PHY_LAN8720A=y
+CONFIG_NET=y
+#CONFIG_NETDB_DNSCLIENT=y
+#CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETDEV_PHY_IOCTL=y
+CONFIG_NETDEV_STATISTICS=y
+#CONFIG_NETUTILS_TFTPC=y
+#CONFIG_NETUTILS_WEBCLIENT=y
+#CONFIG_NET_ARP_SEND=y
+CONFIG_NET_BROADCAST=y
+#CONFIG_NET_ICMP=y
+#CONFIG_NET_ICMP_SOCKET=y
+CONFIG_NET_SOCKOPTS=y
+CONFIG_NET_STATISTICS=y
+CONFIG_NET_TCP=y
+CONFIG_NET_TCPBACKLOG=y
+CONFIG_NET_TCP_WRITE_BUFFERS=y
+CONFIG_NET_UDP=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_NETINIT_MONITOR=y
+CONFIG_NETINIT_THREAD=y
+
+CONFIG_NETINIT_RETRYMSEC=2000
+CONFIG_NETINIT_SIGNO=18
+
+CONFIG_NUNGET_CHARS=0
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_PTHREAD_STACK_DEFAULT=1024
+CONFIG_RAM_SIZE=655360
+CONFIG_RAM_START=0x00000000
+CONFIG_RAW_BINARY=y
+CONFIG_RX65N_SCI0=y
+CONFIG_RX65N_SCI1=y
+CONFIG_RX65N_SCI2=y
+CONFIG_RX65N_SCI5=y
+CONFIG_RX65N_SCI6=y
+CONFIG_RX65N_SCI8=y
+CONFIG_SCI0_SERIALDRIVER=y
+CONFIG_SCI0_BAUD=115200
+CONFIG_SCI1_SERIAL_CONSOLE=y
+CONFIG_SCI1_SERIALDRIVER=y
+CONFIG_SCI1_BAUD=115200
+CONFIG_SCI2_SERIALDRIVER=y
+CONFIG_SCI2_BAUD=115200
+CONFIG_SCI5_SERIALDRIVER=y
+CONFIG_SCI5_BAUD=921600
+CONFIG_SCI6_SERIALDRIVER=y
+CONFIG_SCI6_BAUD=115200
+CONFIG_SCI8_SERIALDRIVER=y
+CONFIG_SCI8_BAUD=115200
+CONFIG_RX65N_EMAC=y
+CONFIG_RX65N_EMAC0=y
+CONFIG_RX65N_EMAC0_PHYSR=30
+CONFIG_RX65N_EMAC0_PHYSR_100FD=0x18
+CONFIG_RX65N_EMAC0_PHYSR_100HD=0x08
+CONFIG_RX65N_EMAC0_PHYSR_10FD=0x14
+CONFIG_RX65N_EMAC0_PHYSR_10HD=0x04
+CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y
+CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x1c
+CONFIG_RX65N_EMAC0_RMII=y
+CONFIG_RX65N_EMAC0_PHYADDR=0
+CONFIG_SCHED_WORKQUEUE=y
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_LPWORK=y
+CONFIG_SDCLONE_DISABLE=y
+#CONFIG_SYSTEM_PING=y
+CONFIG_ICU=y
+CONFIG_STDIO_DISABLE_BUFFERING=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_USERMAIN_STACKSIZE=1024
+CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_NET_ETH_PKTSIZE = 590
+CONFIG_RX65N_CMTW0=y
+CONFIG_RX65N_PERIB=y
+CONFIG_NETUTILS_DHCPC=y
+CONFIG_NETUTILS_DHCPD=y
+CONFIG_NSH_DHCPC=y
+CONFIG_NETINIT_DHCPC=y
+CONFIG_SYSTEM_DHCPC_RENEW=y
+CONFIG_SYSTEM_NSH_PRIORITY=50
+CONFIG_EXAMPLES_SERIALBLASTER=y
+CONFIG_EXAMPLES_SERIALBLASTER_STACKSIZE=2048
+CONFIG_EXAMPLES_SERIALBLASTER_PRIORITY=50
+CONFIG_EXAMPLES_SERIALBLASTER_DEVPATH="/dev/ttyS2"
+CONFIG_EXAMPLES_SERIALRX=y
+CONFIG_EXAMPLES_SERIALRX_STACKSIZE=2048
+CONFIG_EXAMPLES_SERIALRX_PRIORITY=75
+CONFIG_EXAMPLES_SERIALRX_BUFSIZE=11520
+CONFIG_EXAMPLES_SERIALRX_DEVPATH="/dev/ttyS0"
+CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y
+CONFIG_DEBUG_NET=y
+
+# CONFIG_NET_IPv4 is not set
+CONFIG_NETINIT_IPv6NETMASK_8=0xff80
+CONFIG_NET_ICMPv6=y
+CONFIG_NET_ICMPv6_NEIGHBOR=y
+CONFIG_NET_ICMPv6_SOCKET=y
+CONFIG_NET_IPv6=y
+CONFIG_SYSTEM_PING6=y
+CONFIG_NET_MLD=y
+#CONFIG_NET_MCASTGROUP=y
+CONFIG_NET_SOLINGER=y
+
diff --git a/boards/renesas/rx65n/rx65n-grrose/include/board.h b/boards/renesas/rx65n/rx65n-grrose/include/board.h
index 6c66de8..c788ebe 100644
--- a/boards/renesas/rx65n/rx65n-grrose/include/board.h
+++ b/boards/renesas/rx65n/rx65n-grrose/include/board.h
@@ -56,7 +56,17 @@
/* LED definitions */
-#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
+#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
+# define LED_ON (0)
+# define LED_OFF (1)
+#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
+# define LED_ON (1)
+# define LED_OFF (0)
+#else
+# error "No Selection for PORT definition in rx65n_port.c"
+#endif
+
+#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
#define LED0 (PORT0.PODR.BIT.B3)
#define LED1 (PORT0.PODR.BIT.B5)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
diff --git a/boards/renesas/rx65n/rx65n-grrose/include/rx65n_gpio.h b/boards/renesas/rx65n/rx65n-grrose/include/rx65n_gpio.h
new file mode 100644
index 0000000..f2adfba
--- /dev/null
+++ b/boards/renesas/rx65n/rx65n-grrose/include/rx65n_gpio.h
@@ -0,0 +1,232 @@
+/****************************************************************************
+ * boards/renesas/rx65n/rx65n-grrose/include/rx65n_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_RENESAS_RX65N_RX65N_GRROSE_INCLUDE_RX65N_GPIO_H
+#define __BOARDS_RENESAS_RX65N_RX65N_GRROSE_INCLUDE_RX65N_GPIO_H
+
+#if defined(CONFIG_ARCH_RX65N_GRROSE)
+ #define PHY_STS_REG 0x1f
+ #define PHY_STS_REG_AUTO_NEG (1 << 12)
+ #define PHY_STS_READ_REG PHY_REG_STATUS
+ #define PHY_STS_BIT_MASK (0x4)
+ #define PHY_STS_SHIFT_COUNT (0x02)
+#else
+ #define PHY_STS_REG 0x10
+ #define PHY_STS_REG_LINK (1 << 0)
+ #define PHY_STS_READ_REG PHY_STS_REG
+ #define PHY_STS_BIT_MASK (0x1)
+ #define PHY_STS_SHIFT_COUNT (0x0)
+#endif
+
+#if defined(CONFIG_ARCH_RX65N_GRROSE)
+ #define PHY_SET_MODE_REG PHY_RMII_SET_MODE
+#else
+ #define PHY_SET_MODE_REG PHY_MII_SET_MODE
+#endif
+
+#if defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
+ #define RX65N_MAC_ADDRL 0x00509074
+ #define RX65N_MAC_ADDRH 0x0000989c
+#else
+ #define RX65N_MAC_ADDRL 0x00000000
+ #define RX65N_MAC_ADDRH 0x00000000
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sci_port_create
+ *
+ * Description:
+ * Initializes SCI Ports of RX65N GRROSE
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void sci_port_create(void);
+
+/****************************************************************************
+ * Name: led_port_create
+ *
+ * Description:
+ * Initializes LED Ports of RX65N GRROSE
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void led_port_create(void);
+
+/****************************************************************************
+ * Name: r_ether_pheriperal_enable
+ *
+ * Description:
+ * Ethernet Peripheral enabling
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_EMAC0
+void r_ether_pheriperal_enable(void);
+#endif
+
+/****************************************************************************
+ * Name: sci0_init_port
+ *
+ * Description:
+ * SCI0 Initialization RX65N GRROSE
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI0
+void sci0_init_port(void);
+#endif
+
+/****************************************************************************
+ * Name: sci1_init_port
+ *
+ * Description:
+ * SCI1 Initialization RX65N GRROSE
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI1
+void sci1_init_port(void);
+#endif
+
+/****************************************************************************
+ * Name: sci2_init_port
+ *
+ * Description:
+ * SCI2 Initialization RX65N GRROSE
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI2
+void sci2_init_port(void);
+#endif
+
+/****************************************************************************
+ * Name: sci3_init_port
+ *
+ * Description:
+ * SCI3 Initialization RX65N GRROSE
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI3
+void sci3_init_port(void);
+#endif
+
+/****************************************************************************
+ * Name: sci5_init_port
+ *
+ * Description:
+ * SCI5 Initialization RX65N GRROSE
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI5
+void sci5_init_port(void);
+#endif
+
+/****************************************************************************
+ * Name: sci6_init_port
+ *
+ * Description:
+ * SCI6 Initialization RX65N GRROSE
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI6
+void sci6_init_port(void);
+#endif
+
+/****************************************************************************
+ * Name: sci8_init_port
+ *
+ * Description:
+ * SCI8 Initialization RX65N GRROSE
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI8
+void sci8_init_port(void);
+#endif
+#endif /* __BOARDS_RENESAS_RX65N_RX65N_GRROSE_INCLUDE_RX65N_GPIO_H */
+
diff --git a/boards/renesas/rx65n/rx65n-grrose/src/Makefile b/boards/renesas/rx65n/rx65n-grrose/src/Makefile
index 3cf1dfb..6cdc25e 100644
--- a/boards/renesas/rx65n/rx65n-grrose/src/Makefile
+++ b/boards/renesas/rx65n/rx65n-grrose/src/Makefile
@@ -26,7 +26,7 @@ CFLAGS += -I=$(ARCH_SRCDIR)/chip
ASRCS =
AOBJS = $(ASRCS:.asm=$(OBJEXT))
-CSRCS = rx65n_appinit.c rx65n_bringup.c rx65n_sbram.c
+CSRCS = rx65n_appinit.c rx65n_bringup.c rx65n_sbram.c rx65n_gpio.c
COBJS = $(CSRCS:.c=$(OBJEXT))
SRCS = $(ASRCS) $(CSRCS)
diff --git a/boards/renesas/rx65n/rx65n-grrose/src/rx65n_gpio.c b/boards/renesas/rx65n/rx65n-grrose/src/rx65n_gpio.c
new file mode 100644
index 0000000..c2ecf76
--- /dev/null
+++ b/boards/renesas/rx65n/rx65n-grrose/src/rx65n_gpio.c
@@ -0,0 +1,358 @@
+/****************************************************************************
+ * boards/renesas/rx65n/rx65n-grrose/src/rx65n_gpio.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "rx65n_macrodriver.h"
+#include "rx65n_port.h"
+#include "arch/board/board.h"
+#include "arch/board/rx65n_gpio.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: led_port_create
+ *
+ * Description:
+ * LED Port Initialization for RX65N GRROSE Board
+ ****************************************************************************/
+
+#if defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
+void led_port_create(void)
+{
+ /* LED Port initialization of RX65N GRROSE */
+
+ LED_PORTINIT(0);
+}
+
+/****************************************************************************
+ * Name: sci_port_create
+ *
+ * Description:
+ * SCI Port Initialization for RX65N GRROSE Board
+ ****************************************************************************/
+
+void sci_port_create(void)
+{
+ /* SCI Port initialization for RX65N-GRROSE */
+
+ /* SCI0(UART) direction */
+
+ PORT2.PODR.BIT.B2 = 0; PORT2.PMR.BIT.B2 = 0; PORT2.PDR.BIT.B2 = 1;
+
+ /* SCI2(UART) direction */
+
+ PORT1.PODR.BIT.B4 = 0; PORT1.PMR.BIT.B4 = 0; PORT1.PDR.BIT.B4 = 1;
+
+ /* SCI5(UART) direction */
+
+ PORTC.PODR.BIT.B4 = 0; PORTC.PMR.BIT.B4 = 0; PORTC.PDR.BIT.B4 = 1;
+
+ /* SCI6(UART) direction */
+
+ PORT3.PODR.BIT.B4 = 0; PORT3.PMR.BIT.B4 = 0; PORT3.PDR.BIT.B4 = 1;
+
+ /* SCI8(RS485) direction */
+
+ PORTC.PODR.BIT.B5 = 0; PORTC.PMR.BIT.B5 = 0; PORTC.PDR.BIT.B5 = 1;
+}
+
+/****************************************************************************
+ * Name: r_ether_pheriperal_enable
+ *
+ * Description:
+ * Ethernet Pheriperal enabling
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_EMAC0
+void r_ether_pheriperal_enable(void)
+{
+ /* Set ET0_MDC(PA4_ET_MDC) pin */
+
+ MPC.PA4PFS.BYTE = 0x11u;
+ PORTA.PMR.BIT.B4 = 1u;
+
+ /* Set ET0_MDIO(PA3_ET_MDIO) pin */
+
+ MPC.PA3PFS.BYTE = 0x11u;
+ PORTA.PMR.BIT.B3 = 1u;
+
+ /* Set REF50CK0 (PB2_ET_CLK) pin */
+
+ MPC.PB2PFS.BYTE = 0x12u;
+ PORTB.PMR.BIT.B2 = 1u;
+
+ /* Set RMII0_CRS_DV(PB7_ET_CRS) pin */
+
+ MPC.PB7PFS.BYTE = 0x12u;
+ PORTB.PMR.BIT.B7 = 1u;
+
+ /* Set RMII0_RXD0(PB1_ET_RXD0) pin */
+
+ MPC.PB1PFS.BYTE = 0x12u;
+ PORTB.PMR.BIT.B1 = 1u;
+
+ /* Set RMII0_RXD1(PB0_ET_RXD1) pin */
+
+ MPC.PB0PFS.BYTE = 0x12u;
+ PORTB.PMR.BIT.BT0 = 1u;
+
+ /* Set RMII0_RX_ER(PB3_ET_RXER) pin */
+
+ MPC.PB3PFS.BYTE = 0x12u;
+ PORTB.PMR.BIT.B3 = 1u;
+
+ /* Set RMII0_ETXD0(PB5_ET_TXD0) pin */
+
+ MPC.PB5PFS.BYTE = 0x12u;
+ PORTB.PMR.BIT.B5 = 1u;
+
+ /* Set RMII0_ETXD1(PB6_ET_TXD1) pin */
+
+ MPC.PB6PFS.BYTE = 0x12u;
+ PORTB.PMR.BIT.B6 = 1u;
+
+ /* Set RMII0_TXD_EN(PB4_ET_TXEN) pin */
+
+ MPC.PB4PFS.BYTE = 0x12u;
+ PORTB.PMR.BIT.B4 = 1u;
+
+ /* Set RXD2 pin */
+
+ MPC.P52PFS.BYTE = 0x0au;
+ PORT5.PMR.BIT.B2 = 1u;
+
+ /* Set TXD2 pin */
+
+ PORT5.PODR.BYTE |= 0x01u;
+ MPC.P50PFS.BYTE = 0x0au;
+ PORT5.PDR.BYTE |= 0x01u;
+
+ /* Set ET0_LINKSTA(PA5_ET_LINK) pin */
+
+ MPC.PA5PFS.BYTE = 0x11u;
+ PORTA.PMR.BIT.B5 = 1u;
+
+ /* Set ETHER reset(PA6_ET_RST) pin */
+
+ MPC.PA6PFS.BYTE = 0x12u;
+ PORTA.PMR.BIT.B6 = 1u;
+
+ /* Set VBUS pin for USB */
+
+ /* Referred from r_usb_basic_pinset.c */
+
+ MPC.P16PFS.BYTE = 0x12u;
+
+ /* PORT1.PMR.BYTE |= 0x40; */
+
+ PORT1.PMR.BIT.B6 = 1u;
+
+ /* Set USB0_OVRCURA pin */
+
+ /* GR Rose does not contain any of OVRCURA/B inputs
+ * MPC.P14PFS.BYTE = 0x12u;
+ * PORT1.PMR.BIT.B4 = 1u;
+ */
+}
+#endif
+
+/****************************************************************************
+ * Name: sci0_init_port
+ *
+ * Description:
+ * SCI0 Initialization RX65N GRROSE
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI0
+inline void sci0_init_port(void)
+{
+ /* Set RXD0 pin (P21) */
+
+ MPC.P21PFS.BYTE = 0x0au;
+ PORT2.PMR.BIT.B1 = 1u;
+
+ /* Set TXD0 pin (P20) */
+
+ PORT2.PODR.BIT.BT0 = 1u;
+ MPC.P20PFS.BYTE = 0x0au;
+ PORT2.PDR.BIT.BT0 = 1u;
+ PORT2.PMR.BIT.BT0 = 1u;
+}
+#endif
+
+/****************************************************************************
+ * Name: sci1_init_port
+ *
+ * Description:
+ * SCI1 Initialization RX65N GRROSE
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI1
+inline void sci1_init_port(void)
+{
+ /* Set RXD1 pin (P30) */
+
+ MPC.P30PFS.BYTE = 0x0au;
+ PORT3.PMR.BIT.BT0 = 1u;
+
+ /* Set TXD1 pin (P26) */
+
+ PORT2.PODR.BIT.B6 = 1u;
+ MPC.P26PFS.BYTE = 0x0au;
+ PORT2.PDR.BIT.B6 = 1u;
+ PORT2.PMR.BIT.B6 = 1u;
+}
+#endif
+
+/****************************************************************************
+ * Name: sci2_init_port
+ *
+ * Description:
+ * SCI2 Initialization RX65N GRROSE
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI2
+inline void sci2_init_port(void)
+{
+ /* Set RXD2 pin (P12) */
+
+ MPC.P12PFS.BYTE = 0x0au;
+ PORT1.PMR.BIT.B2 = 1u;
+
+ /* Set TXD2 pin (P13) */
+
+ PORT1.PODR.BIT.B3 = 1u;
+ MPC.P13PFS.BYTE = 0x0au;
+ PORT1.PDR.BIT.B3 = 1u;
+ PORT1.PMR.BIT.B3 = 1u;
+}
+#endif
+
+/****************************************************************************
+ * Name: sci3_init_port
+ *
+ * Description:
+ * SCI3 Initialization RX65N GRROSE
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI3
+inline void sci3_init_port(void)
+{
+ /* Set RXD3 pin (PXX)
+ * MPC.PXXPFS.BYTE = 0x0au;
+ * PORTX.PMR.BIT.BX = 1u;
+ * Set TXD3 pin (PXX)
+ * PORTX.PODR.BIT.BX = 1u;
+ * MPC.PXXPFS.BYTE = 0x0au;
+ * PORTX.PDR.BIT.BX = 1u;
+ * PORTX.PMR.BIT.BX = 1u;
+ */
+
+ /* Set RXD2 pin (P25) */
+
+ MPC.P25PFS.BYTE = 0x0au;
+ PORT2.PMR.BIT.B5 = 1u;
+
+ /* Set TXD2 pin (P23) */
+
+ PORT2.PODR.BIT.B3 = 1u;
+ MPC.P23PFS.BYTE = 0x0au;
+ PORT2.PDR.BIT.B3 = 1u;
+ PORT2.PMR.BIT.B3 = 1u;
+}
+#endif
+
+/****************************************************************************
+ * Name: sci5_init_port
+ *
+ * Description:
+ * SCI5 Initialization RX65N GRROSE
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI5
+inline void sci5_init_port(void)
+{
+ /* Set RXD3 pin (PC2) */
+
+ MPC.PC2PFS.BYTE = 0x0au;
+ PORTC.PMR.BIT.B2 = 1u;
+
+ /* Set TXD3 pin (PC3) */
+
+ PORTC.PODR.BIT.B3 = 1u;
+ MPC.PC3PFS.BYTE = 0x0au;
+ PORTC.PDR.BIT.B3 = 1u;
+ PORTC.PMR.BIT.B3 = 1u;
+}
+#endif
+
+/****************************************************************************
+ * Name: sci6_init_port
+ *
+ * Description:
+ * SCI6 Initialization RX65N GRROSE
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI6
+inline void sci6_init_port(void)
+{
+ /* Set RXD6 pin (P33) */
+
+ MPC.P33PFS.BYTE = 0x0au;
+ PORT3.PMR.BIT.B3 = 1u;
+
+ /* Set TXD6 pin (P32) */
+
+ PORT3.PODR.BIT.B2 = 1u;
+ MPC.P32PFS.BYTE = 0x0au;
+ PORT3.PDR.BIT.B2 = 1u;
+ PORT3.PMR.BIT.B2 = 1u;
+}
+#endif
+
+/****************************************************************************
+ * Name: sci8_init_port
+ *
+ * Description:
+ * SCI8 Initialization RX65N GRROSE
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI8
+inline void sci8_init_port(void)
+{
+ /* Set RXD8 pin (PC6) */
+
+ MPC.PC6PFS.BYTE = 0x0au;
+ PORTC.PMR.BIT.B6 = 1u;
+
+ /* Set TXD8 pin (PC7) */
+
+ PORTC.PODR.BIT.B7 = 1u;
+ MPC.PC7PFS.BYTE = 0x0au;
+ PORTC.PDR.BIT.B7 = 1u;
+ PORTC.PMR.BIT.B7 = 1u;
+}
+#endif
+#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */
\ No newline at end of file
diff --git a/boards/renesas/rx65n/rx65n-rsk1mb/include/rx65n_gpio.h b/boards/renesas/rx65n/rx65n-rsk1mb/include/rx65n_gpio.h
new file mode 100644
index 0000000..c45fd80
--- /dev/null
+++ b/boards/renesas/rx65n/rx65n-rsk1mb/include/rx65n_gpio.h
@@ -0,0 +1,97 @@
+/****************************************************************************
+ * boards/renesas/rx65n/rx65n-rsk1mb/include/rx65n_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_RENESAS_RX65N_RX65N_RSK1MB_INCLUDE_RX65N_GPIO_H
+#define __BOARDS_RENESAS_RX65N_RX65N_RSK1MB_INCLUDE_RX65N_GPIO_H
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sci_port_create
+ *
+ * Description:
+ * Initializes SCI Ports of RX65N RSK1MB
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void sci_port_create(void);
+
+/****************************************************************************
+ * Name: led_port_create
+ *
+ * Description:
+ * Initializes LED Ports of RX65N RSK1MB
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void led_port_create(void);
+
+/****************************************************************************
+ * Name: r_ether_pheriperal_enable
+ *
+ * Description:
+ * Ethernet Peripheral enabling
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_EMAC0
+void r_ether_pheriperal_enable(void);
+#endif
+
+/****************************************************************************
+ * Name: sci2_init_port
+ *
+ * Description:
+ * SCI2 Initialization RX65N RSK1MB
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI2
+void sci2_init_port(void);
+#endif
+
+#endif /* __BOARDS_RENESAS_RX65N_RX65N_RSK1MB_INCLUDE_RX65N_GPIO_H */
+
diff --git a/boards/renesas/rx65n/rx65n-rsk1mb/src/rx65n_gpio.c b/boards/renesas/rx65n/rx65n-rsk1mb/src/rx65n_gpio.c
new file mode 100644
index 0000000..35de812
--- /dev/null
+++ b/boards/renesas/rx65n/rx65n-rsk1mb/src/rx65n_gpio.c
@@ -0,0 +1,127 @@
+/****************************************************************************
+ * boards/renesas/rx65n/rx65n-rsk1mb/src/rx65n_gpio.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "rx65n_macrodriver.h"
+#include "rx65n_port.h"
+#include "arch/board/board.h"
+#include "arch/board/rx65n_gpio.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: led_port_create
+ *
+ * Description:
+ * Port Initialization for RX65N RSK1MB Board
+ ****************************************************************************/
+
+#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
+void led_port_create(void)
+{
+ /* LED Port initialization of RX65N RSK1MB */
+
+ /* LED_PORTINIT(0); */
+
+ PORT0.PODR.BYTE = _04_PM2_OUTPUT_1 | _08_PM3_OUTPUT_1 | _20_PM5_OUTPUT_1;
+ PORT0.DSCR.BYTE = _00_PM2_HIDRV_OFF;
+ PORT0.DSCR2.BYTE = _00_PM2_HISPEED_OFF;
+ PORT0.PMR.BYTE = 0x00u;
+ PORT0.PDR.BYTE = _04_PM2_MODE_OUTPUT | _08_PM3_MODE_OUTPUT |
+ _20_PM5_MODE_OUTPUT | _50_PDR0_DEFAULT;
+}
+
+/****************************************************************************
+ * Name: sci_port_create
+ *
+ * Description:
+ * SCI Port Initialization for RX65N RSK2MB Board
+ ****************************************************************************/
+
+void sci_port_create(void)
+{
+ /* SCI Port initialization for RX65N-RSK1MB */
+
+ PORT5.PODR.BYTE = _40_PM6_OUTPUT_1;
+ PORT5.DSCR.BYTE = _20_PM5_HIDRV_ON | _00_PM6_HIDRV_OFF;
+ PORT5.DSCR2.BYTE = _00_PM5_HISPEED_OFF | _00_PM6_HISPEED_OFF;
+ PORT5.PMR.BYTE = 0x00u;
+ PORT5.PDR.BYTE = _20_PM5_MODE_OUTPUT | _40_PM6_MODE_OUTPUT |
+ _80_PDR5_DEFAULT;
+
+ /* General Purpose I/O Port initialization for RX65N-RSK1MB */
+
+ PORT7.PODR.BYTE = _08_PM3_OUTPUT_1;
+ PORT9.PODR.BYTE = _08_PM3_OUTPUT_1;
+ PORTJ.PODR.BYTE = _20_PM5_OUTPUT_1;
+ PORT7.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
+ PORT9.DSCR.BYTE = _00_PM3_HIDRV_OFF;
+ PORT9.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
+ PORT7.PMR.BYTE = 0x00u;
+ PORT7.PDR.BYTE = _08_PM3_MODE_OUTPUT;
+ PORT9.PMR.BYTE = 0x00u;
+ PORT9.PDR.BYTE = _08_PM3_MODE_OUTPUT | _F0_PDR9_DEFAULT;
+ PORTJ.PMR.BYTE = 0x00u;
+ PORTJ.PDR.BYTE = _20_PM5_MODE_OUTPUT | _D7_PDRJ_DEFAULT;
+}
+
+/****************************************************************************
+ * Name: r_ether_pheriperal_enable
+ *
+ * Description:
+ * Ethernet Peripheral enabling
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_EMAC0
+void r_ether_pheriperal_enable(void)
+{
+ /* TODO */
+}
+#endif
+
+/****************************************************************************
+ * Name: sci2_init_port
+ *
+ * Description:
+ * SCI2 Initialization RX65N RSK1MB
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI2
+inline void sci2_init_port(void)
+{
+ /* Set RXD2 pin (P52) */
+
+ MPC.P52PFS.BYTE = 0x0au;
+ PORT5.PMR.BIT.B2 = 1u;
+
+ /* Set TXD2 pin (P50) */
+
+ PORT5.PODR.BIT.BT0 = 1u;
+ MPC.P50PFS.BYTE = 0x0au;
+ PORT5.PDR.BIT.BT0 = 1u;
+ PORT5.PMR.BIT.BT0 = 1u;
+}
+#endif
+#endif /* CONFIG_ARCH_BOARD_RX65N_RSK1MB*/
diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/README.txt b/boards/renesas/rx65n/rx65n-rsk2mb/README.txt
index 6747512..070c26c 100644
--- a/boards/renesas/rx65n/rx65n-rsk2mb/README.txt
+++ b/boards/renesas/rx65n/rx65n-rsk2mb/README.txt
@@ -11,6 +11,32 @@ Contents
- Serial Console
- LEDs
- Networking
+ - IPv6 Integration
+ - HTTP Server Integration on IPv4
+ - DHCP Client Integration on IPv4
+ - DHCP Server Integration on IPv4
+ - FTP Server Integration on IPv4
+ - FTP Client Integration on IPv4
+ - TFTP Client Integration on IPv4
+ - Telnet Server Integration on IPv4
+ - Telnet Client Integration on IPv4
+ - Ustream Socket Integration on IPv4
+ - Udgram Socket Integration on IPv4
+ - SMTP Client Integration on IPv4
+ - Raw Socket Integration
+ - Custom User Socket Integration
+ - IGMPv2 Integration
+ - Inherit telnet server Integration
+ - VNC Server Integration
+ - PPPD Integration
+ - HTTP Client Integration
+ - NTP Client Integration
+ - NFS Client Integration
+ - MLD Integration
+ - ICMPv6 AutoConfig Integration
+ - IP Forwarding Integration for IPv4
+ - DNS Name Resolution Integration for IPv4
+ - LINK MONITOR Integration
- RTC
- Debugging
diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/configs/ipv6/defconfig b/boards/renesas/rx65n/rx65n-rsk2mb/configs/ipv6/defconfig
new file mode 100644
index 0000000..fee3fa6
--- /dev/null
+++ b/boards/renesas/rx65n/rx65n-rsk2mb/configs/ipv6/defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARCH_BOARD_RX65N_RSK2MB=y
+CONFIG_ARCH_BOARD="rx65n"
+CONFIG_ARCH_CHIP_R5F565NEHDFC=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH="renesas"
+CONFIG_ARCH_CHIP="rx65n"
+CONFIG_BOARD_LOOPSPERMSEC=15001
+CONFIG_MOTOROLA_SREC=y
+CONFIG_ENDIAN_LITTLE=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_MAX_TASKS=8
+CONFIG_DEBUG_FEATURES=y
+CONFIG_ARCH_INTERRUPTSTACK=1024
+CONFIG_BUILTIN=y
+CONFIG_ETH0_PHY_DP83620=y
+CONFIG_NET=y
+#CONFIG_NETDB_DNSCLIENT=y
+#CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETDEV_PHY_IOCTL=y
+CONFIG_NETDEV_STATISTICS=y
+#CONFIG_NETUTILS_TFTPC=y
+#CONFIG_NETUTILS_WEBCLIENT=y
+#CONFIG_NET_ARP_SEND=y
+CONFIG_NET_BROADCAST=y
+#CONFIG_NET_ICMP=y
+#CONFIG_NET_ICMP_SOCKET=y
+CONFIG_NET_SOCKOPTS=y
+CONFIG_NET_STATISTICS=y
+CONFIG_NET_TCP=y
+CONFIG_NET_TCPBACKLOG=y
+CONFIG_NET_TCP_WRITE_BUFFERS=y
+CONFIG_NET_UDP=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_NETINIT_MONITOR=y
+CONFIG_NETINIT_THREAD=y
+
+CONFIG_NETINIT_RETRYMSEC=2000
+CONFIG_NETINIT_SIGNO=18
+
+CONFIG_NUNGET_CHARS=0
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_PTHREAD_STACK_DEFAULT=1024
+CONFIG_RAM_SIZE=262144
+CONFIG_RAM_START=0x00000000
+CONFIG_RAW_BINARY=y
+CONFIG_SCI2_SERIALDRIVER=y
+CONFIG_RX65N_SCI2=y
+CONFIG_SCI8_SERIALDRIVER=y
+CONFIG_SCI8_SERIAL_CONSOLE=y
+CONFIG_RX65N_SCI8=y
+CONFIG_RX65N_EMAC=y
+CONFIG_RX65N_EMAC0=y
+CONFIG_RX65N_EMAC0_PHYSR=30
+CONFIG_RX65N_EMAC0_PHYSR_100FD=0x4
+CONFIG_RX65N_EMAC0_PHYSR_100HD=0x0
+CONFIG_RX65N_EMAC0_PHYSR_10FD=0x6
+CONFIG_RX65N_EMAC0_PHYSR_10HD=0x2
+CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y
+CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x6
+CONFIG_RX65N_EMAC0_MII=y
+CONFIG_RX65N_EMAC0_PHYADDR=30
+CONFIG_SCHED_WORKQUEUE=y
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_LPWORK=y
+CONFIG_SDCLONE_DISABLE=y
+#CONFIG_SYSTEM_PING=y
+CONFIG_ICU=y
+CONFIG_STDIO_DISABLE_BUFFERING=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_USERMAIN_STACKSIZE=1024
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_NET_ETH_PKTSIZE = 590
+CONFIG_RX65N_CMTW0=y
+CONFIG_RX65N_PERIB=y
+CONFIG_NETUTILS_DHCPC=y
+CONFIG_NETUTILS_DHCPD=y
+CONFIG_NSH_DHCPC=y
+CONFIG_NETINIT_DHCPC=y
+CONFIG_SYSTEM_NSH_PRIORITY=50
+CONFIG_EXAMPLES_SERIALBLASTER=y
+CONFIG_EXAMPLES_SERIALBLASTER_STACKSIZE=2048
+CONFIG_EXAMPLES_SERIALBLASTER_PRIORITY=50
+CONFIG_EXAMPLES_SERIALBLASTER_DEVPATH="/dev/ttyS2"
+CONFIG_EXAMPLES_SERIALRX=y
+CONFIG_EXAMPLES_SERIALRX_STACKSIZE=2048
+CONFIG_EXAMPLES_SERIALRX_PRIORITY=75
+CONFIG_EXAMPLES_SERIALRX_BUFSIZE=11520
+CONFIG_EXAMPLES_SERIALRX_DEVPATH="/dev/ttyS0"
+CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y
+CONFIG_DEBUG_NET=y
+
+# CONFIG_NET_IPv4 is not set
+CONFIG_NETINIT_IPv6NETMASK_8=0xff80
+CONFIG_NET_ICMPv6=y
+CONFIG_NET_ICMPv6_NEIGHBOR=y
+CONFIG_NET_ICMPv6_SOCKET=y
+CONFIG_NET_IPv6=y
+CONFIG_SYSTEM_PING6=y
+CONFIG_NET_MLD=y
+#CONFIG_NET_MCASTGROUP=y
+CONFIG_NET_SOLINGER=y
+
diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/include/board.h b/boards/renesas/rx65n/rx65n-rsk2mb/include/board.h
index 9f2f42d..dc248a1 100644
--- a/boards/renesas/rx65n/rx65n-rsk2mb/include/board.h
+++ b/boards/renesas/rx65n/rx65n-rsk2mb/include/board.h
@@ -56,7 +56,17 @@
/* LED definitions */
-#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
+#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
+# define LED_ON (0)
+# define LED_OFF (1)
+#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
+# define LED_ON (1)
+# define LED_OFF (0)
+#else
+# error "No Selection for PORT definition in rx65n_port.c"
+#endif
+
+#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
#define LED0 (PORT0.PODR.BIT.B3)
#define LED1 (PORT0.PODR.BIT.B5)
#define LED_PORTINIT(X) { LED0 = LED1 = (X); \
diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/include/rx65n_gpio.h b/boards/renesas/rx65n/rx65n-rsk2mb/include/rx65n_gpio.h
new file mode 100644
index 0000000..b81f304
--- /dev/null
+++ b/boards/renesas/rx65n/rx65n-rsk2mb/include/rx65n_gpio.h
@@ -0,0 +1,177 @@
+/****************************************************************************
+ * boards/renesas/rx65n/rx65n-rsk2mb/include/rx65n_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_RENESAS_RX65N_RX65N_RSK2MB_INCLUDE_RX65N_GPIO_H
+#define __BOARDS_RENESAS_RX65N_RX65N_RSK2MB_INCLUDE_RX65N_GPIO_H
+
+#if defined(CONFIG_ARCH_RX65N_RSK2MB)
+ #define PHY_STS_REG 0x10
+ #define PHY_STS_REG_LINK (1 << 0)
+ #define PHY_STS_READ_REG PHY_STS_REG
+ #define PHY_STS_BIT_MASK (0x1)
+ #define PHY_STS_SHIFT_COUNT (0x0)
+#else
+ #define PHY_STS_REG 0x1f
+ #define PHY_STS_REG_AUTO_NEG (1 << 12)
+ #define PHY_STS_READ_REG PHY_REG_STATUS
+ #define PHY_STS_BIT_MASK (0x4)
+ #define PHY_STS_SHIFT_COUNT (0x02)
+#endif
+
+#if defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
+ #define PHY_SET_MODE_REG PHY_MII_SET_MODE
+#else
+ #define PHY_SET_MODE_REG PHY_RMII_SET_MODE
+#endif
+
+#if defined (CONFIG_ARCH_BOARD_RX65N_RSK2MB)
+ #define RX65N_MAC_ADDRL 0x00509074
+ #define RX65N_MAC_ADDRH 0x0000949c
+#else
+ #define RX65N_MAC_ADDRL 0x00000000
+ #define RX65N_MAC_ADDRH 0x00000000
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sci_port_create
+ *
+ * Description:
+ * Initializes SCI Ports of RX65N RSK2MB
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void sci_port_create(void);
+
+/****************************************************************************
+ * Name: led_port_create
+ *
+ * Description:
+ * Initializes LED Ports of RX65N RSK2MB
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void led_port_create(void);
+
+/****************************************************************************
+ * Name: r_ether_pheriperal_enable
+ *
+ * Description:
+ * Ethernet Pheriperal enabling
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_EMAC0
+void r_ether_pheriperal_enable(void);
+#endif
+
+/****************************************************************************
+ * Name: sci1_init_port
+ *
+ * Description:
+ * SCI1 Initialization RX65N RSK2MB
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI1
+void sci1_init_port(void);
+#endif
+
+/****************************************************************************
+ * Name: sci2_init_port
+ *
+ * Description:
+ * SCI2 Initialization RX65N RSK2MB
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI2
+void sci2_init_port(void);
+#endif
+
+/****************************************************************************
+ * Name: sci8_init_port
+ *
+ * Description:
+ * SCI8 Initialization RX65N RSK2MB
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI8
+void sci8_init_port(void);
+#endif
+
+/****************************************************************************
+ * Name: sci12_init_port
+ *
+ * Description:
+ * SCI12 Initialization RX65N RSK2MB
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_SCI12
+void sci12_init_port(void);
+#endif
+#endif /* __BOARDS_RENESAS_RX65N_RX65N_RSK2MB_INCLUDE_RX65N_GPIO_H */
\ No newline at end of file
diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/src/Makefile b/boards/renesas/rx65n/rx65n-rsk2mb/src/Makefile
index 801c80f..f2ba9b4 100644
--- a/boards/renesas/rx65n/rx65n-rsk2mb/src/Makefile
+++ b/boards/renesas/rx65n/rx65n-rsk2mb/src/Makefile
@@ -26,7 +26,7 @@ CFLAGS += -I=$(ARCH_SRCDIR)/chip
ASRCS =
AOBJS = $(ASRCS:.asm=$(OBJEXT))
-CSRCS = rx65n_appinit.c rx65n_bringup.c rx65n_sbram.c
+CSRCS = rx65n_appinit.c rx65n_bringup.c rx65n_sbram.c rx65n_gpio.c
COBJS = $(CSRCS:.c=$(OBJEXT))
SRCS = $(ASRCS) $(CSRCS)
diff --git a/arch/renesas/src/rx65n/rx65n_port.c b/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_gpio.c
similarity index 52%
copy from arch/renesas/src/rx65n/rx65n_port.c
copy to boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_gpio.c
index 796cdae..36c03fd 100644
--- a/arch/renesas/src/rx65n/rx65n_port.c
+++ b/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_gpio.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/renesas/src/rx65n/rx65n_port.c
+ * boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -25,147 +25,78 @@
#include "rx65n_macrodriver.h"
#include "rx65n_port.h"
#include "arch/board/board.h"
+#include "arch/board/rx65n_gpio.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: r_port_create
+ * Name: led_port_create
*
* Description:
- * Port Initialization
+ * LED Port Initialization for RX65N RSK2MB Board
****************************************************************************/
-void r_port_create(void)
+#if defined (CONFIG_ARCH_BOARD_RX65N_RSK2MB)
+void led_port_create(void)
{
-#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
+ /* LED Port initialization of RX65N RSK2MB */
/* LED_PORTINIT(0); */
- PORT0.PODR.BYTE = _04_PM2_OUTPUT_1 | _08_PM3_OUTPUT_1 | _20_PM5_OUTPUT_1;
- PORT5.PODR.BYTE = _40_PM6_OUTPUT_1;
PORT7.PODR.BYTE = _08_PM3_OUTPUT_1;
- PORT9.PODR.BYTE = _08_PM3_OUTPUT_1;
+ PORT7.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
+ PORT7.PMR.BYTE = 0x00u;
+ PORT7.PDR.BYTE = _08_PM3_MODE_OUTPUT;
+}
+
+/****************************************************************************
+ * Name: sci_port_create
+ *
+ * Description:
+ * SCI Port Initialization for RX65N RSK2MB Board
+ ****************************************************************************/
+
+void sci_port_create(void)
+{
+ /* SCI Port initialization for RX65N-RSK2MB */
+
+ PORT5.PODR.BYTE = _40_PM6_OUTPUT_1;
PORTJ.PODR.BYTE = _20_PM5_OUTPUT_1;
- PORT0.DSCR.BYTE = _00_PM2_HIDRV_OFF;
- PORT0.DSCR2.BYTE = _00_PM2_HISPEED_OFF;
PORT5.DSCR.BYTE = _20_PM5_HIDRV_ON | _00_PM6_HIDRV_OFF;
PORT5.DSCR2.BYTE = _00_PM5_HISPEED_OFF | _00_PM6_HISPEED_OFF;
- PORT7.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
- PORT9.DSCR.BYTE = _00_PM3_HIDRV_OFF;
- PORT9.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
- PORT0.PMR.BYTE = 0x00u;
- PORT0.PDR.BYTE = _04_PM2_MODE_OUTPUT | _08_PM3_MODE_OUTPUT |
- _20_PM5_MODE_OUTPUT | _50_PDR0_DEFAULT;
PORT5.PMR.BYTE = 0x00u;
PORT5.PDR.BYTE = _20_PM5_MODE_OUTPUT | _40_PM6_MODE_OUTPUT |
_80_PDR5_DEFAULT;
- PORT7.PMR.BYTE = 0x00u;
- PORT7.PDR.BYTE = _08_PM3_MODE_OUTPUT;
- PORT9.PMR.BYTE = 0x00u;
- PORT9.PDR.BYTE = _08_PM3_MODE_OUTPUT | _F0_PDR9_DEFAULT;
PORTJ.PMR.BYTE = 0x00u;
PORTJ.PDR.BYTE = _20_PM5_MODE_OUTPUT | _D7_PDRJ_DEFAULT;
-#elif defined (CONFIG_ARCH_BOARD_RX65N_RSK2MB)
- /* LED_PORTINIT(0); */
+ /* General Purpose I/O Port initialization for RX65N-RSK2MB */
PORT0.PODR.BYTE = _04_PM2_OUTPUT_1 | _08_PM3_OUTPUT_1 | _20_PM5_OUTPUT_1;
- PORT5.PODR.BYTE = _40_PM6_OUTPUT_1;
- PORT7.PODR.BYTE = _08_PM3_OUTPUT_1;
PORT9.PODR.BYTE = _08_PM3_OUTPUT_1;
- PORTJ.PODR.BYTE = _20_PM5_OUTPUT_1;
PORT0.DSCR.BYTE = _00_PM2_HIDRV_OFF;
PORT0.DSCR2.BYTE = _00_PM2_HISPEED_OFF;
- PORT5.DSCR.BYTE = _20_PM5_HIDRV_ON | _00_PM6_HIDRV_OFF;
- PORT5.DSCR2.BYTE = _00_PM5_HISPEED_OFF | _00_PM6_HISPEED_OFF;
- PORT7.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
PORT9.DSCR.BYTE = _00_PM3_HIDRV_OFF;
PORT9.DSCR2.BYTE = _00_PM3_HISPEED_OFF;
PORT0.PMR.BYTE = 0x00u;
PORT0.PDR.BYTE = _04_PM2_MODE_OUTPUT | _08_PM3_MODE_OUTPUT |
_20_PM5_MODE_OUTPUT | _50_PDR0_DEFAULT;
- PORT5.PMR.BYTE = 0x00u;
- PORT5.PDR.BYTE = _20_PM5_MODE_OUTPUT | _40_PM6_MODE_OUTPUT |
- _80_PDR5_DEFAULT;
- PORT7.PMR.BYTE = 0x00u;
- PORT7.PDR.BYTE = _08_PM3_MODE_OUTPUT;
PORT9.PMR.BYTE = 0x00u;
PORT9.PDR.BYTE = _08_PM3_MODE_OUTPUT | _F0_PDR9_DEFAULT;
- PORTJ.PMR.BYTE = 0x00u;
- PORTJ.PDR.BYTE = _20_PM5_MODE_OUTPUT | _D7_PDRJ_DEFAULT;
-#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
- LED_PORTINIT(0);
-
- /* SCI0(UART) direction */
-
- PORT2.PODR.BIT.B2 = 0; PORT2.PMR.BIT.B2 = 0; PORT2.PDR.BIT.B2 = 1;
-
- /* SCI2(UART) direction */
-
- PORT1.PODR.BIT.B4 = 0; PORT1.PMR.BIT.B4 = 0; PORT1.PDR.BIT.B4 = 1;
-
- /* SCI5(UART) direction */
-
- PORTC.PODR.BIT.B4 = 0; PORTC.PMR.BIT.B4 = 0; PORTC.PDR.BIT.B4 = 1;
-
- /* SCI6(UART) direction */
-
- PORT3.PODR.BIT.B4 = 0; PORT3.PMR.BIT.B4 = 0; PORT3.PDR.BIT.B4 = 1;
-
- /* SCI8(RS485) direction */
-
- PORTC.PODR.BIT.B5 = 0; PORTC.PMR.BIT.B5 = 0; PORTC.PDR.BIT.B5 = 1;
-#else
-# error "No Selection for PORT definition in rx65n_port.c"
-#endif
}
-#ifdef CONFIG_RX65N_EMAC0
-void r_ether_port_configuration(void)
-{
- /* Port configuration */
-
- /* Enable LEDs. */
-
- /* Start with LEDs OFF */
-
- PORT7.PODR.BIT.B3 = 1;
- PORTG.PODR.BIT.B7 = 1;
- PORTG.PODR.BIT.B6 = 1;
- PORTG.PODR.BIT.B5 = 1;
-
- /* SET LED pins as outputs */
-
- PORT7.PDR.BIT.B3 = 1;
- PORTG.PDR.BIT.B7 = 1;
- PORTG.PDR.BIT.B6 = 1;
- PORTG.PDR.BIT.B5 = 1;
-
- /* Enable Switches */
-
- /* Set pins as Inputs */
-
- PORT0.PDR.BIT.B3 = 0;
- PORT0.PDR.BIT.B5 = 0;
- PORT0.PDR.BIT.B7 = 0;
-
- /* Set port mode registers for switches. */
-
- PORT0.PMR.BIT.B3 = 0;
- PORT0.PMR.BIT.B5 = 0;
- PORT0.PMR.BIT.B7 = 0;
-}
+/****************************************************************************
+ * Name: r_ether_pheriperal_enable
+ *
+ * Description:
+ * Ethernet Pheriperal enabling
+ ****************************************************************************/
+#ifdef CONFIG_RX65N_EMAC0
void r_ether_pheriperal_enable(void)
{
-#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB)
-
- /* TODO */
-
-#elif defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB)
-
/* Set ET0_TX_CLK pin */
MPC.PC4PFS.BYTE = 0x11u;
@@ -266,78 +197,125 @@ void r_ether_pheriperal_enable(void)
MPC.P34PFS.BYTE = 0x11u;
PORT3.PMR.BIT.B4 = 1u;
-#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE)
-
- /* Set ET0_MDC(PA4_ET_MDC) pin */
+ /* Set VBUS pin for USB */
- MPC.PA4PFS.BYTE = 0x11u;
- PORTA.PMR.BIT.B4 = 1u;
+ /* Referred from r_usb_basic_pinset.c */
- /* Set ET0_MDIO(PA3_ET_MDIO) pin */
+ MPC.P16PFS.BYTE = 0x12u;
- MPC.PA3PFS.BYTE = 0x11u;
- PORTA.PMR.BIT.B3 = 1u;
+ /* PORT1.PMR.BYTE |= 0x40; */
- /* Set REF50CK0 (PB2_ET_CLK) pin */
+ PORT1.PMR.BIT.B6 = 1u;
- MPC.PB2PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.B2 = 1u;
+ /* Set USB0_OVRCURA pin */
- /* Set RMII0_CRS_DV(PB7_ET_CRS) pin */
-
- MPC.PB7PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.B7 = 1u;
-
- /* Set RMII0_RXD0(PB1_ET_RXD0) pin */
-
- MPC.PB1PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.B1 = 1u;
-
- /* Set RMII0_RXD1(PB0_ET_RXD1) pin */
+ MPC.P14PFS.BYTE = 0x12u;
+ PORT1.PMR.BIT.B4 = 1u;
+}
+#endif
- MPC.PB0PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.BT0 = 1u;
+/****************************************************************************
+ * Name: sci1_init_port
+ *
+ * Description:
+ * SCI1 Initialization RX65N RSK2MB
+ ****************************************************************************/
- /* Set RMII0_RX_ER(PB3_ET_RXER) pin */
+#ifdef CONFIG_RX65N_SCI1
+inline void sci1_init_port(void)
+{
+ /* Set RXD1 pin (PF2) */
- MPC.PB3PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.B3 = 1u;
+ MPC.PF2PFS.BYTE = 0x0au;
+ PORTF.PMR.BIT.B2 = 1u;
- /* Set RMII0_ETXD0(PB5_ET_TXD0) pin */
+ /* Set TXD1 pin (PF1) */
- MPC.PB5PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.B5 = 1u;
+ PORTF.PODR.BIT.B1 = 1u;
+ MPC.PF1PFS.BYTE = 0x0au;
+ PORTF.PDR.BIT.B1 = 1u;
+ PORTF.PMR.BIT.B1 = 1u;
+}
+#endif
- /* Set RMII0_ETXD1(PB6_ET_TXD1) pin */
+/****************************************************************************
+ * Name: sci2_init_port
+ *
+ * Description:
+ * SCI2 Initialization RX65N RSK2MB
+ ****************************************************************************/
- MPC.PB6PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.B6 = 1u;
+#ifdef CONFIG_RX65N_SCI2
+inline void sci2_init_port(void)
+{
+ /* Set RXD2 pin (P52) */
- /* Set RMII0_TXD_EN(PB4_ET_TXEN) pin */
+ MPC.P52PFS.BYTE = 0x0au;
+ PORT5.PMR.BIT.B2 = 1u;
- MPC.PB4PFS.BYTE = 0x12u;
- PORTB.PMR.BIT.B4 = 1u;
+ /* Set TXD2 pin (P50) */
- /* Set RXD2 pin */
+ PORT5.PODR.BIT.BT0 = 1u;
+ MPC.P50PFS.BYTE = 0x0au;
+ PORT5.PDR.BIT.BT0 = 1u;
+ PORT5.PMR.BIT.BT0 = 1u;
+}
+#endif
- MPC.P52PFS.BYTE = 0x0au;
- PORT5.PMR.BIT.B2 = 1u;
+/****************************************************************************
+ * Name: sci8_init_port
+ *
+ * Description:
+ * SCI8 Initialization RX65N RSK2MB
+ ****************************************************************************/
- /* Set TXD2 pin */
+#ifdef CONFIG_RX65N_SCI8
+inline void sci8_init_port(void)
+{
+ /* Set RXD8 pin (PJ1) */
- PORT5.PODR.BYTE |= 0x01u;
- MPC.P50PFS.BYTE = 0x0au;
- PORT5.PDR.BYTE |= 0x01u;
+ MPC.PJ1PFS.BYTE = 0x0au;
+ PORTJ.PMR.BIT.B1 = 1u;
- /* Set ET0_LINKSTA(PA5_ET_LINK) pin */
+ /* Set TXD8 pin (PJ2) */
- MPC.PA5PFS.BYTE = 0x11u;
- PORTA.PMR.BIT.B5 = 1u;
+ PORTJ.PODR.BIT.B2 = 1u;
+ MPC.PJ2PFS.BYTE = 0x0au;
+ PORTJ.PDR.BIT.B2 = 1u;
+ PORTJ.PMR.BIT.B2 = 1u;
+}
+#endif
- /* Set ETHER reset(PA6_ET_RST) pin */
+/****************************************************************************
+ * Name: sci12_init_port
+ *
+ * Description:
+ * SCI12 Initialization RX65N RSK2MB
+ ****************************************************************************/
- MPC.PA6PFS.BYTE = 0x12u;
- PORTA.PMR.BIT.B6 = 1u;
-#endif
+#ifdef CONFIG_RX65N_SCI12
+inline void sci12_init_port(void)
+{
+ /* Set RXD12 pin */
+
+ MPC.PE2PFS.BYTE = 0x0cu;
+ PORTE.PMR.BYTE |= 0x04u;
+
+ /* Set TXD12 pin */
+
+ PORTE.PODR.BYTE |= 0x02u;
+ MPC.PE1PFS.BYTE = 0x0cu;
+ PORTE.PDR.BYTE |= 0x02u;
+
+ /* Set RXD12 pin (PXX)
+ * MPC.PXXPFS.BYTE = 0x0au;
+ * PORTX.PMR.BIT.BX = 1u;
+ * Set TXD12 pin (PXX)
+ * PORTX.PODR.BIT.BX = 1u;
+ * MPC.PXXPFS.BYTE = 0x0au;
+ * PORTX.PDR.BIT.BX = 1u;
+ * PORTX.PMR.BIT.BX = 1u;
+ */
}
#endif
+#endif /* CONFIG_ARCH_BOARD_RX65N_RSK2MB */
\ No newline at end of file