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Posted to commits@mynewt.apache.org by cc...@apache.org on 2016/03/04 01:39:46 UTC
[06/70] [abbrv] [partial] incubator-mynewt-larva git commit: Arduino
zero BSP and Atmel MCU in a different repository.
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-larva/blob/a280628a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sercom2.h
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diff --git a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sercom2.h b/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sercom2.h
deleted file mode 100755
index 57cf5ad..0000000
--- a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sercom2.h
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@@ -1,146 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM2
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMD21_SERCOM2_INSTANCE_
-#define _SAMD21_SERCOM2_INSTANCE_
-
-/* ========== Register definition for SERCOM2 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM2_I2CM_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
-#define REG_SERCOM2_I2CM_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
-#define REG_SERCOM2_I2CM_BAUD (0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
-#define REG_SERCOM2_I2CM_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
-#define REG_SERCOM2_I2CM_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
-#define REG_SERCOM2_I2CM_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM2_I2CM_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
-#define REG_SERCOM2_I2CM_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */
-#define REG_SERCOM2_I2CM_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CM Address */
-#define REG_SERCOM2_I2CM_DATA (0x42001028U) /**< \brief (SERCOM2) I2CM Data */
-#define REG_SERCOM2_I2CM_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
-#define REG_SERCOM2_I2CS_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
-#define REG_SERCOM2_I2CS_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
-#define REG_SERCOM2_I2CS_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
-#define REG_SERCOM2_I2CS_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
-#define REG_SERCOM2_I2CS_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM2_I2CS_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
-#define REG_SERCOM2_I2CS_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */
-#define REG_SERCOM2_I2CS_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CS Address */
-#define REG_SERCOM2_I2CS_DATA (0x42001028U) /**< \brief (SERCOM2) I2CS Data */
-#define REG_SERCOM2_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM2) SPI Control A */
-#define REG_SERCOM2_SPI_CTRLB (0x42001004U) /**< \brief (SERCOM2) SPI Control B */
-#define REG_SERCOM2_SPI_BAUD (0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
-#define REG_SERCOM2_SPI_INTENCLR (0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
-#define REG_SERCOM2_SPI_INTENSET (0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
-#define REG_SERCOM2_SPI_INTFLAG (0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM2_SPI_STATUS (0x4200101AU) /**< \brief (SERCOM2) SPI Status */
-#define REG_SERCOM2_SPI_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */
-#define REG_SERCOM2_SPI_ADDR (0x42001024U) /**< \brief (SERCOM2) SPI Address */
-#define REG_SERCOM2_SPI_DATA (0x42001028U) /**< \brief (SERCOM2) SPI Data */
-#define REG_SERCOM2_SPI_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
-#define REG_SERCOM2_USART_CTRLA (0x42001000U) /**< \brief (SERCOM2) USART Control A */
-#define REG_SERCOM2_USART_CTRLB (0x42001004U) /**< \brief (SERCOM2) USART Control B */
-#define REG_SERCOM2_USART_BAUD (0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
-#define REG_SERCOM2_USART_RXPL (0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
-#define REG_SERCOM2_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
-#define REG_SERCOM2_USART_INTENSET (0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
-#define REG_SERCOM2_USART_INTFLAG (0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM2_USART_STATUS (0x4200101AU) /**< \brief (SERCOM2) USART Status */
-#define REG_SERCOM2_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */
-#define REG_SERCOM2_USART_DATA (0x42001028U) /**< \brief (SERCOM2) USART Data */
-#define REG_SERCOM2_USART_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
-#else
-#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
-#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
-#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
-#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
-#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
-#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
-#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */
-#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CM Address */
-#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CM Data */
-#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
-#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
-#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
-#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
-#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
-#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
-#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */
-#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CS Address */
-#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CS Data */
-#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) SPI Control A */
-#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) SPI Control B */
-#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
-#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
-#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
-#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) SPI Status */
-#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */
-#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) SPI Address */
-#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42001028U) /**< \brief (SERCOM2) SPI Data */
-#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
-#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) USART Control A */
-#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) USART Control B */
-#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
-#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
-#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
-#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
-#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) USART Status */
-#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */
-#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001028U) /**< \brief (SERCOM2) USART Data */
-#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM2 peripheral ========== */
-#define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger
-#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger
-#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core
-#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM2_INT_MSB 6
-
-#endif /* _SAMD21_SERCOM2_INSTANCE_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-larva/blob/a280628a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sercom3.h
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diff --git a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sercom3.h b/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sercom3.h
deleted file mode 100755
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--- a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sercom3.h
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@@ -1,146 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM3
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMD21_SERCOM3_INSTANCE_
-#define _SAMD21_SERCOM3_INSTANCE_
-
-/* ========== Register definition for SERCOM3 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM3_I2CM_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
-#define REG_SERCOM3_I2CM_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
-#define REG_SERCOM3_I2CM_BAUD (0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
-#define REG_SERCOM3_I2CM_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
-#define REG_SERCOM3_I2CM_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
-#define REG_SERCOM3_I2CM_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM3_I2CM_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
-#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */
-#define REG_SERCOM3_I2CM_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CM Address */
-#define REG_SERCOM3_I2CM_DATA (0x42001428U) /**< \brief (SERCOM3) I2CM Data */
-#define REG_SERCOM3_I2CM_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
-#define REG_SERCOM3_I2CS_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
-#define REG_SERCOM3_I2CS_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
-#define REG_SERCOM3_I2CS_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
-#define REG_SERCOM3_I2CS_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
-#define REG_SERCOM3_I2CS_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM3_I2CS_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
-#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */
-#define REG_SERCOM3_I2CS_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CS Address */
-#define REG_SERCOM3_I2CS_DATA (0x42001428U) /**< \brief (SERCOM3) I2CS Data */
-#define REG_SERCOM3_SPI_CTRLA (0x42001400U) /**< \brief (SERCOM3) SPI Control A */
-#define REG_SERCOM3_SPI_CTRLB (0x42001404U) /**< \brief (SERCOM3) SPI Control B */
-#define REG_SERCOM3_SPI_BAUD (0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
-#define REG_SERCOM3_SPI_INTENCLR (0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
-#define REG_SERCOM3_SPI_INTENSET (0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
-#define REG_SERCOM3_SPI_INTFLAG (0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM3_SPI_STATUS (0x4200141AU) /**< \brief (SERCOM3) SPI Status */
-#define REG_SERCOM3_SPI_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */
-#define REG_SERCOM3_SPI_ADDR (0x42001424U) /**< \brief (SERCOM3) SPI Address */
-#define REG_SERCOM3_SPI_DATA (0x42001428U) /**< \brief (SERCOM3) SPI Data */
-#define REG_SERCOM3_SPI_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
-#define REG_SERCOM3_USART_CTRLA (0x42001400U) /**< \brief (SERCOM3) USART Control A */
-#define REG_SERCOM3_USART_CTRLB (0x42001404U) /**< \brief (SERCOM3) USART Control B */
-#define REG_SERCOM3_USART_BAUD (0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
-#define REG_SERCOM3_USART_RXPL (0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
-#define REG_SERCOM3_USART_INTENCLR (0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
-#define REG_SERCOM3_USART_INTENSET (0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
-#define REG_SERCOM3_USART_INTFLAG (0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM3_USART_STATUS (0x4200141AU) /**< \brief (SERCOM3) USART Status */
-#define REG_SERCOM3_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */
-#define REG_SERCOM3_USART_DATA (0x42001428U) /**< \brief (SERCOM3) USART Data */
-#define REG_SERCOM3_USART_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
-#else
-#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
-#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
-#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
-#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
-#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
-#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
-#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */
-#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CM Address */
-#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CM Data */
-#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
-#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
-#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
-#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
-#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
-#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
-#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */
-#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CS Address */
-#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CS Data */
-#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) SPI Control A */
-#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) SPI Control B */
-#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
-#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
-#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
-#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) SPI Status */
-#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */
-#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) SPI Address */
-#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001428U) /**< \brief (SERCOM3) SPI Data */
-#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
-#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) USART Control A */
-#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) USART Control B */
-#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
-#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
-#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
-#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
-#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) USART Status */
-#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */
-#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001428U) /**< \brief (SERCOM3) USART Data */
-#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM3 peripheral ========== */
-#define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger
-#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger
-#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core
-#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM3_INT_MSB 6
-
-#endif /* _SAMD21_SERCOM3_INSTANCE_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-larva/blob/a280628a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sercom4.h
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diff --git a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sercom4.h b/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sercom4.h
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--- a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sercom4.h
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@@ -1,146 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM4
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMD21_SERCOM4_INSTANCE_
-#define _SAMD21_SERCOM4_INSTANCE_
-
-/* ========== Register definition for SERCOM4 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM4_I2CM_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
-#define REG_SERCOM4_I2CM_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
-#define REG_SERCOM4_I2CM_BAUD (0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
-#define REG_SERCOM4_I2CM_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
-#define REG_SERCOM4_I2CM_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
-#define REG_SERCOM4_I2CM_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM4_I2CM_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
-#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */
-#define REG_SERCOM4_I2CM_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CM Address */
-#define REG_SERCOM4_I2CM_DATA (0x42001828U) /**< \brief (SERCOM4) I2CM Data */
-#define REG_SERCOM4_I2CM_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
-#define REG_SERCOM4_I2CS_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
-#define REG_SERCOM4_I2CS_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
-#define REG_SERCOM4_I2CS_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
-#define REG_SERCOM4_I2CS_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
-#define REG_SERCOM4_I2CS_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM4_I2CS_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
-#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */
-#define REG_SERCOM4_I2CS_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CS Address */
-#define REG_SERCOM4_I2CS_DATA (0x42001828U) /**< \brief (SERCOM4) I2CS Data */
-#define REG_SERCOM4_SPI_CTRLA (0x42001800U) /**< \brief (SERCOM4) SPI Control A */
-#define REG_SERCOM4_SPI_CTRLB (0x42001804U) /**< \brief (SERCOM4) SPI Control B */
-#define REG_SERCOM4_SPI_BAUD (0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
-#define REG_SERCOM4_SPI_INTENCLR (0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
-#define REG_SERCOM4_SPI_INTENSET (0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
-#define REG_SERCOM4_SPI_INTFLAG (0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM4_SPI_STATUS (0x4200181AU) /**< \brief (SERCOM4) SPI Status */
-#define REG_SERCOM4_SPI_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */
-#define REG_SERCOM4_SPI_ADDR (0x42001824U) /**< \brief (SERCOM4) SPI Address */
-#define REG_SERCOM4_SPI_DATA (0x42001828U) /**< \brief (SERCOM4) SPI Data */
-#define REG_SERCOM4_SPI_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
-#define REG_SERCOM4_USART_CTRLA (0x42001800U) /**< \brief (SERCOM4) USART Control A */
-#define REG_SERCOM4_USART_CTRLB (0x42001804U) /**< \brief (SERCOM4) USART Control B */
-#define REG_SERCOM4_USART_BAUD (0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
-#define REG_SERCOM4_USART_RXPL (0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
-#define REG_SERCOM4_USART_INTENCLR (0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
-#define REG_SERCOM4_USART_INTENSET (0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
-#define REG_SERCOM4_USART_INTFLAG (0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM4_USART_STATUS (0x4200181AU) /**< \brief (SERCOM4) USART Status */
-#define REG_SERCOM4_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */
-#define REG_SERCOM4_USART_DATA (0x42001828U) /**< \brief (SERCOM4) USART Data */
-#define REG_SERCOM4_USART_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
-#else
-#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
-#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
-#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
-#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
-#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
-#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
-#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */
-#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CM Address */
-#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CM Data */
-#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
-#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
-#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
-#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
-#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
-#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
-#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */
-#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CS Address */
-#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CS Data */
-#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) SPI Control A */
-#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) SPI Control B */
-#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
-#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
-#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
-#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) SPI Status */
-#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */
-#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) SPI Address */
-#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001828U) /**< \brief (SERCOM4) SPI Data */
-#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
-#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) USART Control A */
-#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) USART Control B */
-#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
-#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
-#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
-#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
-#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) USART Status */
-#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */
-#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001828U) /**< \brief (SERCOM4) USART Data */
-#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM4 peripheral ========== */
-#define SERCOM4_DMAC_ID_RX 9 // Index of DMA RX trigger
-#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger
-#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core
-#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM4_INT_MSB 6
-
-#endif /* _SAMD21_SERCOM4_INSTANCE_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-larva/blob/a280628a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sercom5.h
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diff --git a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sercom5.h b/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sercom5.h
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@@ -1,146 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM5
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMD21_SERCOM5_INSTANCE_
-#define _SAMD21_SERCOM5_INSTANCE_
-
-/* ========== Register definition for SERCOM5 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM5_I2CM_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
-#define REG_SERCOM5_I2CM_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
-#define REG_SERCOM5_I2CM_BAUD (0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */
-#define REG_SERCOM5_I2CM_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
-#define REG_SERCOM5_I2CM_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
-#define REG_SERCOM5_I2CM_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM5_I2CM_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
-#define REG_SERCOM5_I2CM_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */
-#define REG_SERCOM5_I2CM_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
-#define REG_SERCOM5_I2CM_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
-#define REG_SERCOM5_I2CM_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
-#define REG_SERCOM5_I2CS_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
-#define REG_SERCOM5_I2CS_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
-#define REG_SERCOM5_I2CS_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
-#define REG_SERCOM5_I2CS_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
-#define REG_SERCOM5_I2CS_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM5_I2CS_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
-#define REG_SERCOM5_I2CS_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */
-#define REG_SERCOM5_I2CS_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
-#define REG_SERCOM5_I2CS_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
-#define REG_SERCOM5_SPI_CTRLA (0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
-#define REG_SERCOM5_SPI_CTRLB (0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
-#define REG_SERCOM5_SPI_BAUD (0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */
-#define REG_SERCOM5_SPI_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
-#define REG_SERCOM5_SPI_INTENSET (0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
-#define REG_SERCOM5_SPI_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM5_SPI_STATUS (0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
-#define REG_SERCOM5_SPI_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */
-#define REG_SERCOM5_SPI_ADDR (0x42001C24U) /**< \brief (SERCOM5) SPI Address */
-#define REG_SERCOM5_SPI_DATA (0x42001C28U) /**< \brief (SERCOM5) SPI Data */
-#define REG_SERCOM5_SPI_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
-#define REG_SERCOM5_USART_CTRLA (0x42001C00U) /**< \brief (SERCOM5) USART Control A */
-#define REG_SERCOM5_USART_CTRLB (0x42001C04U) /**< \brief (SERCOM5) USART Control B */
-#define REG_SERCOM5_USART_BAUD (0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */
-#define REG_SERCOM5_USART_RXPL (0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
-#define REG_SERCOM5_USART_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
-#define REG_SERCOM5_USART_INTENSET (0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
-#define REG_SERCOM5_USART_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM5_USART_STATUS (0x42001C1AU) /**< \brief (SERCOM5) USART Status */
-#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */
-#define REG_SERCOM5_USART_DATA (0x42001C28U) /**< \brief (SERCOM5) USART Data */
-#define REG_SERCOM5_USART_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
-#else
-#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
-#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
-#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */
-#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
-#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
-#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
-#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */
-#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
-#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
-#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
-#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
-#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
-#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
-#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
-#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
-#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */
-#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
-#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
-#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
-#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
-#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */
-#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
-#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
-#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
-#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */
-#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) SPI Address */
-#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001C28U) /**< \brief (SERCOM5) SPI Data */
-#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
-#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) USART Control A */
-#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) USART Control B */
-#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */
-#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
-#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
-#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
-#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) USART Status */
-#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */
-#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C28U) /**< \brief (SERCOM5) USART Data */
-#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM5 peripheral ========== */
-#define SERCOM5_DMAC_ID_RX 11 // Index of DMA RX trigger
-#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger
-#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core
-#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM5_INT_MSB 6
-
-#endif /* _SAMD21_SERCOM5_INSTANCE_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-larva/blob/a280628a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sysctrl.h
----------------------------------------------------------------------
diff --git a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sysctrl.h b/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sysctrl.h
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index e2b181b..0000000
--- a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/sysctrl.h
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@@ -1,123 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SYSCTRL
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMD21_SYSCTRL_INSTANCE_
-#define _SAMD21_SYSCTRL_INSTANCE_
-
-/* ========== Register definition for SYSCTRL peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SYSCTRL_INTENCLR (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */
-#define REG_SYSCTRL_INTENSET (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */
-#define REG_SYSCTRL_INTFLAG (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
-#define REG_SYSCTRL_PCLKSR (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */
-#define REG_SYSCTRL_XOSC (0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
-#define REG_SYSCTRL_XOSC32K (0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
-#define REG_SYSCTRL_OSC32K (0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
-#define REG_SYSCTRL_OSCULP32K (0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
-#define REG_SYSCTRL_OSC8M (0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
-#define REG_SYSCTRL_DFLLCTRL (0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */
-#define REG_SYSCTRL_DFLLVAL (0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */
-#define REG_SYSCTRL_DFLLMUL (0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */
-#define REG_SYSCTRL_DFLLSYNC (0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */
-#define REG_SYSCTRL_BOD33 (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
-#define REG_SYSCTRL_VREG (0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
-#define REG_SYSCTRL_VREF (0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
-#define REG_SYSCTRL_DPLLCTRLA (0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */
-#define REG_SYSCTRL_DPLLRATIO (0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */
-#define REG_SYSCTRL_DPLLCTRLB (0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */
-#define REG_SYSCTRL_DPLLSTATUS (0x40000850U) /**< \brief (SYSCTRL) DPLL Status */
-#else
-#define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */
-#define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */
-#define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
-#define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */
-#define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
-#define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
-#define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
-#define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
-#define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
-#define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */
-#define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */
-#define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */
-#define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */
-#define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
-#define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
-#define REG_SYSCTRL_VREF (*(RwReg *)0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
-#define REG_SYSCTRL_DPLLCTRLA (*(RwReg8 *)0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */
-#define REG_SYSCTRL_DPLLRATIO (*(RwReg *)0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */
-#define REG_SYSCTRL_DPLLCTRLB (*(RwReg *)0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */
-#define REG_SYSCTRL_DPLLSTATUS (*(RoReg8 *)0x40000850U) /**< \brief (SYSCTRL) DPLL Status */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SYSCTRL peripheral ========== */
-#define SYSCTRL_BGAP_CALIB_MSB 11
-#define SYSCTRL_BOD33_CALIB_MSB 5
-#define SYSCTRL_DFLL48M_COARSE_MSB 5
-#define SYSCTRL_DFLL48M_FINE_MSB 9
-#define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
-#define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL
-#define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K
-#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
-#define SYSCTRL_POR33_ENTEST_MSB 1
-#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
-#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
-#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
-#define SYSCTRL_VREF_CONTROL_MSB 48
-#define SYSCTRL_VREF_STATUS_MSB 7
-#define SYSCTRL_VREG_LEVEL_MSB 2
-#define SYSCTRL_BOD12_VERSION 0x111
-#define SYSCTRL_BOD33_VERSION 0x111
-#define SYSCTRL_DFLL48M_VERSION 0x301
-#define SYSCTRL_FDPLL_VERSION 0x111
-#define SYSCTRL_OSCULP32K_VERSION 0x111
-#define SYSCTRL_OSC8M_VERSION 0x120
-#define SYSCTRL_OSC32K_VERSION 0x112
-#define SYSCTRL_VREF_VERSION 0x201
-#define SYSCTRL_VREG_VERSION 0x201
-#define SYSCTRL_XOSC_VERSION 0x114
-#define SYSCTRL_XOSC32K_VERSION 0x113
-
-#endif /* _SAMD21_SYSCTRL_INSTANCE_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-larva/blob/a280628a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/tc3.h
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diff --git a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/tc3.h b/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/tc3.h
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--- a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/tc3.h
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@@ -1,114 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TC3
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMD21_TC3_INSTANCE_
-#define _SAMD21_TC3_INSTANCE_
-
-/* ========== Register definition for TC3 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A */
-#define REG_TC3_READREQ (0x42002C02U) /**< \brief (TC3) Read Request */
-#define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear */
-#define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set */
-#define REG_TC3_CTRLC (0x42002C06U) /**< \brief (TC3) Control C */
-#define REG_TC3_DBGCTRL (0x42002C08U) /**< \brief (TC3) Debug Control */
-#define REG_TC3_EVCTRL (0x42002C0AU) /**< \brief (TC3) Event Control */
-#define REG_TC3_INTENCLR (0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
-#define REG_TC3_INTENSET (0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
-#define REG_TC3_INTFLAG (0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
-#define REG_TC3_STATUS (0x42002C0FU) /**< \brief (TC3) Status */
-#define REG_TC3_COUNT16_COUNT (0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
-#define REG_TC3_COUNT16_CC0 (0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
-#define REG_TC3_COUNT16_CC1 (0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
-#define REG_TC3_COUNT32_COUNT (0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
-#define REG_TC3_COUNT32_CC0 (0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
-#define REG_TC3_COUNT32_CC1 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
-#define REG_TC3_COUNT8_COUNT (0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
-#define REG_TC3_COUNT8_PER (0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
-#define REG_TC3_COUNT8_CC0 (0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
-#define REG_TC3_COUNT8_CC1 (0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
-#else
-#define REG_TC3_CTRLA (*(RwReg16*)0x42002C00U) /**< \brief (TC3) Control A */
-#define REG_TC3_READREQ (*(RwReg16*)0x42002C02U) /**< \brief (TC3) Read Request */
-#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */
-#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */
-#define REG_TC3_CTRLC (*(RwReg8 *)0x42002C06U) /**< \brief (TC3) Control C */
-#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Debug Control */
-#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C0AU) /**< \brief (TC3) Event Control */
-#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
-#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
-#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
-#define REG_TC3_STATUS (*(RoReg8 *)0x42002C0FU) /**< \brief (TC3) Status */
-#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
-#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
-#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
-#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
-#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
-#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
-#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
-#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
-#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
-#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC3 peripheral ========== */
-#define TC3_CC8_NUM 2 // Number of 8-bit Counters
-#define TC3_CC16_NUM 2 // Number of 16-bit Counters
-#define TC3_CC32_NUM 2 // Number of 32-bit Counters
-#define TC3_DITHERING_EXT 0 // Dithering feature implemented
-#define TC3_DMAC_ID_MC_0 25
-#define TC3_DMAC_ID_MC_1 26
-#define TC3_DMAC_ID_MC_LSB 25
-#define TC3_DMAC_ID_MC_MSB 26
-#define TC3_DMAC_ID_MC_SIZE 2
-#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger
-#define TC3_GCLK_ID 27 // Index of Generic Clock
-#define TC3_MASTER 0
-#define TC3_OW_NUM 2 // Number of Output Waveforms
-#define TC3_PERIOD_EXT 0 // Period feature implemented
-#define TC3_SHADOW_EXT 0 // Shadow feature implemented
-
-#endif /* _SAMD21_TC3_INSTANCE_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-larva/blob/a280628a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/tc4.h
----------------------------------------------------------------------
diff --git a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/tc4.h b/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/tc4.h
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--- a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/tc4.h
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@@ -1,114 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TC4
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMD21_TC4_INSTANCE_
-#define _SAMD21_TC4_INSTANCE_
-
-/* ========== Register definition for TC4 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC4_CTRLA (0x42003000U) /**< \brief (TC4) Control A */
-#define REG_TC4_READREQ (0x42003002U) /**< \brief (TC4) Read Request */
-#define REG_TC4_CTRLBCLR (0x42003004U) /**< \brief (TC4) Control B Clear */
-#define REG_TC4_CTRLBSET (0x42003005U) /**< \brief (TC4) Control B Set */
-#define REG_TC4_CTRLC (0x42003006U) /**< \brief (TC4) Control C */
-#define REG_TC4_DBGCTRL (0x42003008U) /**< \brief (TC4) Debug Control */
-#define REG_TC4_EVCTRL (0x4200300AU) /**< \brief (TC4) Event Control */
-#define REG_TC4_INTENCLR (0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
-#define REG_TC4_INTENSET (0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
-#define REG_TC4_INTFLAG (0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
-#define REG_TC4_STATUS (0x4200300FU) /**< \brief (TC4) Status */
-#define REG_TC4_COUNT16_COUNT (0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
-#define REG_TC4_COUNT16_CC0 (0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
-#define REG_TC4_COUNT16_CC1 (0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
-#define REG_TC4_COUNT32_COUNT (0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
-#define REG_TC4_COUNT32_CC0 (0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
-#define REG_TC4_COUNT32_CC1 (0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
-#define REG_TC4_COUNT8_COUNT (0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
-#define REG_TC4_COUNT8_PER (0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
-#define REG_TC4_COUNT8_CC0 (0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
-#define REG_TC4_COUNT8_CC1 (0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
-#else
-#define REG_TC4_CTRLA (*(RwReg16*)0x42003000U) /**< \brief (TC4) Control A */
-#define REG_TC4_READREQ (*(RwReg16*)0x42003002U) /**< \brief (TC4) Read Request */
-#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42003004U) /**< \brief (TC4) Control B Clear */
-#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42003005U) /**< \brief (TC4) Control B Set */
-#define REG_TC4_CTRLC (*(RwReg8 *)0x42003006U) /**< \brief (TC4) Control C */
-#define REG_TC4_DBGCTRL (*(RwReg8 *)0x42003008U) /**< \brief (TC4) Debug Control */
-#define REG_TC4_EVCTRL (*(RwReg16*)0x4200300AU) /**< \brief (TC4) Event Control */
-#define REG_TC4_INTENCLR (*(RwReg8 *)0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
-#define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
-#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
-#define REG_TC4_STATUS (*(RoReg8 *)0x4200300FU) /**< \brief (TC4) Status */
-#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
-#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
-#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
-#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
-#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
-#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
-#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
-#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
-#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
-#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC4 peripheral ========== */
-#define TC4_CC8_NUM 2 // Number of 8-bit Counters
-#define TC4_CC16_NUM 2 // Number of 16-bit Counters
-#define TC4_CC32_NUM 2 // Number of 32-bit Counters
-#define TC4_DITHERING_EXT 0 // Dithering feature implemented
-#define TC4_DMAC_ID_MC_0 28
-#define TC4_DMAC_ID_MC_1 29
-#define TC4_DMAC_ID_MC_LSB 28
-#define TC4_DMAC_ID_MC_MSB 29
-#define TC4_DMAC_ID_MC_SIZE 2
-#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger
-#define TC4_GCLK_ID 28 // Index of Generic Clock
-#define TC4_MASTER 1
-#define TC4_OW_NUM 2 // Number of Output Waveforms
-#define TC4_PERIOD_EXT 0 // Period feature implemented
-#define TC4_SHADOW_EXT 0 // Shadow feature implemented
-
-#endif /* _SAMD21_TC4_INSTANCE_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-larva/blob/a280628a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/tc5.h
----------------------------------------------------------------------
diff --git a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/tc5.h b/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/tc5.h
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@@ -1,114 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TC5
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMD21_TC5_INSTANCE_
-#define _SAMD21_TC5_INSTANCE_
-
-/* ========== Register definition for TC5 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC5_CTRLA (0x42003400U) /**< \brief (TC5) Control A */
-#define REG_TC5_READREQ (0x42003402U) /**< \brief (TC5) Read Request */
-#define REG_TC5_CTRLBCLR (0x42003404U) /**< \brief (TC5) Control B Clear */
-#define REG_TC5_CTRLBSET (0x42003405U) /**< \brief (TC5) Control B Set */
-#define REG_TC5_CTRLC (0x42003406U) /**< \brief (TC5) Control C */
-#define REG_TC5_DBGCTRL (0x42003408U) /**< \brief (TC5) Debug Control */
-#define REG_TC5_EVCTRL (0x4200340AU) /**< \brief (TC5) Event Control */
-#define REG_TC5_INTENCLR (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
-#define REG_TC5_INTENSET (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
-#define REG_TC5_INTFLAG (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
-#define REG_TC5_STATUS (0x4200340FU) /**< \brief (TC5) Status */
-#define REG_TC5_COUNT16_COUNT (0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
-#define REG_TC5_COUNT16_CC0 (0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
-#define REG_TC5_COUNT16_CC1 (0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
-#define REG_TC5_COUNT32_COUNT (0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
-#define REG_TC5_COUNT32_CC0 (0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
-#define REG_TC5_COUNT32_CC1 (0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
-#define REG_TC5_COUNT8_COUNT (0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
-#define REG_TC5_COUNT8_PER (0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
-#define REG_TC5_COUNT8_CC0 (0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
-#define REG_TC5_COUNT8_CC1 (0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
-#else
-#define REG_TC5_CTRLA (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A */
-#define REG_TC5_READREQ (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request */
-#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear */
-#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set */
-#define REG_TC5_CTRLC (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C */
-#define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Control */
-#define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control */
-#define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
-#define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
-#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
-#define REG_TC5_STATUS (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status */
-#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
-#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
-#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
-#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
-#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
-#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
-#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
-#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
-#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
-#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC5 peripheral ========== */
-#define TC5_CC8_NUM 2 // Number of 8-bit Counters
-#define TC5_CC16_NUM 2 // Number of 16-bit Counters
-#define TC5_CC32_NUM 2 // Number of 32-bit Counters
-#define TC5_DITHERING_EXT 0 // Dithering feature implemented
-#define TC5_DMAC_ID_MC_0 31
-#define TC5_DMAC_ID_MC_1 32
-#define TC5_DMAC_ID_MC_LSB 31
-#define TC5_DMAC_ID_MC_MSB 32
-#define TC5_DMAC_ID_MC_SIZE 2
-#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
-#define TC5_GCLK_ID 28 // Index of Generic Clock
-#define TC5_MASTER 0
-#define TC5_OW_NUM 2 // Number of Output Waveforms
-#define TC5_PERIOD_EXT 0 // Period feature implemented
-#define TC5_SHADOW_EXT 0 // Shadow feature implemented
-
-#endif /* _SAMD21_TC5_INSTANCE_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-larva/blob/a280628a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/tc6.h
----------------------------------------------------------------------
diff --git a/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/tc6.h b/hw/mcu/atmel/samd21xx/src/sam0/utils/cmsis/samd21/include/instance/tc6.h
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-/**
- * \file
- *
- * \brief Instance description for TC6
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMD21_TC6_INSTANCE_
-#define _SAMD21_TC6_INSTANCE_
-
-/* ========== Register definition for TC6 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC6_CTRLA (0x42003800U) /**< \brief (TC6) Control A */
-#define REG_TC6_READREQ (0x42003802U) /**< \brief (TC6) Read Request */
-#define REG_TC6_CTRLBCLR (0x42003804U) /**< \brief (TC6) Control B Clear */
-#define REG_TC6_CTRLBSET (0x42003805U) /**< \brief (TC6) Control B Set */
-#define REG_TC6_CTRLC (0x42003806U) /**< \brief (TC6) Control C */
-#define REG_TC6_DBGCTRL (0x42003808U) /**< \brief (TC6) Debug Control */
-#define REG_TC6_EVCTRL (0x4200380AU) /**< \brief (TC6) Event Control */
-#define REG_TC6_INTENCLR (0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
-#define REG_TC6_INTENSET (0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
-#define REG_TC6_INTFLAG (0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
-#define REG_TC6_STATUS (0x4200380FU) /**< \brief (TC6) Status */
-#define REG_TC6_COUNT16_COUNT (0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
-#define REG_TC6_COUNT16_CC0 (0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
-#define REG_TC6_COUNT16_CC1 (0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
-#define REG_TC6_COUNT32_COUNT (0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
-#define REG_TC6_COUNT32_CC0 (0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
-#define REG_TC6_COUNT32_CC1 (0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
-#define REG_TC6_COUNT8_COUNT (0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
-#define REG_TC6_COUNT8_PER (0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
-#define REG_TC6_COUNT8_CC0 (0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
-#define REG_TC6_COUNT8_CC1 (0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
-#else
-#define REG_TC6_CTRLA (*(RwReg16*)0x42003800U) /**< \brief (TC6) Control A */
-#define REG_TC6_READREQ (*(RwReg16*)0x42003802U) /**< \brief (TC6) Read Request */
-#define REG_TC6_CTRLBCLR (*(RwReg8 *)0x42003804U) /**< \brief (TC6) Control B Clear */
-#define REG_TC6_CTRLBSET (*(RwReg8 *)0x42003805U) /**< \brief (TC6) Control B Set */
-#define REG_TC6_CTRLC (*(RwReg8 *)0x42003806U) /**< \brief (TC6) Control C */
-#define REG_TC6_DBGCTRL (*(RwReg8 *)0x42003808U) /**< \brief (TC6) Debug Control */
-#define REG_TC6_EVCTRL (*(RwReg16*)0x4200380AU) /**< \brief (TC6) Event Control */
-#define REG_TC6_INTENCLR (*(RwReg8 *)0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
-#define REG_TC6_INTENSET (*(RwReg8 *)0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
-#define REG_TC6_INTFLAG (*(RwReg8 *)0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
-#define REG_TC6_STATUS (*(RoReg8 *)0x4200380FU) /**< \brief (TC6) Status */
-#define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
-#define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
-#define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
-#define REG_TC6_COUNT32_COUNT (*(RwReg *)0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
-#define REG_TC6_COUNT32_CC0 (*(RwReg *)0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
-#define REG_TC6_COUNT32_CC1 (*(RwReg *)0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
-#define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
-#define REG_TC6_COUNT8_PER (*(RwReg8 *)0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
-#define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
-#define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC6 peripheral ========== */
-#define TC6_CC8_NUM 2 // Number of 8-bit Counters
-#define TC6_CC16_NUM 2 // Number of 16-bit Counters
-#define TC6_CC32_NUM 2 // Number of 32-bit Counters
-#define TC6_DITHERING_EXT 0 // Dithering feature implemented
-#define TC6_DMAC_ID_MC_0 34
-#define TC6_DMAC_ID_MC_1 35
-#define TC6_DMAC_ID_MC_LSB 34
-#define TC6_DMAC_ID_MC_MSB 35
-#define TC6_DMAC_ID_MC_SIZE 2
-#define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger
-#define TC6_GCLK_ID 29 // Index of Generic Clock
-#define TC6_MASTER 1
-#define TC6_OW_NUM 2 // Number of Output Waveforms
-#define TC6_PERIOD_EXT 0 // Period feature implemented
-#define TC6_SHADOW_EXT 0 // Shadow feature implemented
-
-#endif /* _SAMD21_TC6_INSTANCE_ */