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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/02/24 18:17:43 UTC
[incubator-nuttx] branch master updated (9603b8f -> 3511ec8)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 9603b8f Add DAC2 configuration for stm32f405.
new b49ee3d xtensa/esp32s3: Add support for Main System Watchdog Timers
new 3511ec8 esp32s3-devkit: Initialize Watchdog Timers on bringup
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/xtensa/src/esp32s3/Kconfig | 31 +
arch/xtensa/src/esp32s3/Make.defs | 4 +
arch/xtensa/src/esp32s3/esp32s3_wdt.c | 879 ++++++++++-
arch/xtensa/src/esp32s3/esp32s3_wdt.h | 115 ++
.../src/esp32s3/esp32s3_wdt_lowerhalf.c} | 298 ++--
.../src/esp32s3/esp32s3_wdt_lowerhalf.h} | 19 +-
.../hardware/esp32s3_efuse.h} | 1599 ++++++++++----------
arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h | 37 +
.../common/include/esp32s3_board_wdt.h} | 10 +-
boards/xtensa/esp32s3/common/src/Make.defs | 4 +
.../esp32s3/common/src/esp32s3_board_wdt.c} | 39 +-
.../configs/{nsh => watchdog}/defconfig | 4 +
.../esp32s3/esp32s3-devkit/src/esp32s3_bringup.c | 14 +
13 files changed, 2045 insertions(+), 1008 deletions(-)
copy arch/{risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.c => xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c} (67%)
copy arch/{risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.h => xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.h} (78%)
copy arch/xtensa/src/{esp32s2/hardware/esp32s2_efuse.h => esp32s3/hardware/esp32s3_efuse.h} (66%)
copy boards/xtensa/{esp32/common/include/esp32_board_wdt.h => esp32s3/common/include/esp32s3_board_wdt.h} (87%)
copy boards/{risc-v/esp32c3/esp32c3-devkit/src/esp32c3_wdt.c => xtensa/esp32s3/common/src/esp32s3_board_wdt.c} (72%)
copy boards/xtensa/esp32s3/esp32s3-devkit/configs/{nsh => watchdog}/defconfig (93%)
[incubator-nuttx] 02/02: esp32s3-devkit: Initialize Watchdog Timers on bringup
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 3511ec823ce8115da53ecd44630424ab0f5ac7e1
Author: Gustavo Henrique Nihei <gu...@espressif.com>
AuthorDate: Tue Feb 22 10:33:04 2022 -0300
esp32s3-devkit: Initialize Watchdog Timers on bringup
Signed-off-by: Gustavo Henrique Nihei <gu...@espressif.com>
---
.../esp32s3/common/include/esp32s3_board_wdt.h | 73 +++++++++++++++++++
boards/xtensa/esp32s3/common/src/Make.defs | 4 ++
.../src/esp32s3_board_wdt.c} | 82 +++++++++-------------
.../esp32s3-devkit/configs/watchdog/defconfig | 51 ++++++++++++++
.../esp32s3/esp32s3-devkit/src/esp32s3_bringup.c | 14 ++++
5 files changed, 174 insertions(+), 50 deletions(-)
diff --git a/boards/xtensa/esp32s3/common/include/esp32s3_board_wdt.h b/boards/xtensa/esp32s3/common/include/esp32s3_board_wdt.h
new file mode 100644
index 0000000..f697729
--- /dev/null
+++ b/boards/xtensa/esp32s3/common/include/esp32s3_board_wdt.h
@@ -0,0 +1,73 @@
+/****************************************************************************
+ * boards/xtensa/esp32s3/common/include/esp32s3_board_wdt.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_XTENSA_ESP32S3_COMMON_INCLUDE_ESP32S3_BOARD_WDT_H
+#define __BOARDS_XTENSA_ESP32S3_COMMON_INCLUDE_ESP32S3_BOARD_WDT_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_WATCHDOG
+
+/****************************************************************************
+ * Name: board_wdt_init
+ *
+ * Description:
+ * Configure the watchdog timer driver.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+int board_wdt_init(void);
+
+#endif /* CONFIG_WATCHDOG */
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __BOARDS_XTENSA_ESP32S3_COMMON_INCLUDE_ESP32S3_BOARD_WDT_H */
diff --git a/boards/xtensa/esp32s3/common/src/Make.defs b/boards/xtensa/esp32s3/common/src/Make.defs
index e504c22..7069365 100644
--- a/boards/xtensa/esp32s3/common/src/Make.defs
+++ b/boards/xtensa/esp32s3/common/src/Make.defs
@@ -22,6 +22,10 @@ ifeq ($(CONFIG_ESP32S3_TIMER),y)
CSRCS += esp32s3_board_tim.c
endif
+ifeq ($(CONFIG_WATCHDOG),y)
+ CSRCS += esp32s3_board_wdt.c
+endif
+
DEPPATH += --dep-path src
VPATH += :src
CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src)
diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/common/src/esp32s3_board_wdt.c
similarity index 54%
copy from boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c
copy to boards/xtensa/esp32s3/common/src/esp32s3_board_wdt.c
index a01e583..c3f6942 100644
--- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c
+++ b/boards/xtensa/esp32s3/common/src/esp32s3_board_wdt.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c
+ * boards/xtensa/esp32s3/common/src/esp32s3_board_wdt.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -24,84 +24,66 @@
#include <nuttx/config.h>
-#include <stdio.h>
-#include <fcntl.h>
-#include <unistd.h>
-#include <syslog.h>
-#include <sys/stat.h>
-#include <sys/ioctl.h>
#include <sys/types.h>
-#include <syslog.h>
#include <debug.h>
-#include <stdio.h>
-#include <errno.h>
-#include <nuttx/fs/fs.h>
-
-#ifdef CONFIG_ESP32S3_TIMER
-# include "esp32s3_board_tim.h"
-#endif
+#include "esp32s3_board_wdt.h"
+#include "esp32s3_wdt_lowerhalf.h"
+#include "esp32s3_wdt.h"
#include "esp32s3-devkit.h"
/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: esp32s3_bringup
+ * Name: board_wdt_init
*
* Description:
- * Perform architecture-specific initialization
- *
- * CONFIG_BOARD_LATE_INITIALIZE=y :
- * Called from board_late_initialize().
+ * Configure the watchdog timer driver.
*
- * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y :
- * Called from the NSH library
+ * Returned Value:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
*
****************************************************************************/
-int esp32s3_bringup(void)
+int board_wdt_init(void)
{
- int ret;
+ int ret = OK;
-#ifdef CONFIG_FS_PROCFS
- /* Mount the procfs file system */
-
- ret = nx_mount(NULL, "/proc", "procfs", 0, NULL);
+#ifdef CONFIG_ESP32S3_MWDT0
+ ret = esp32s3_wdt_initialize("/dev/watchdog0", ESP32S3_WDT_MWDT0);
if (ret < 0)
{
- syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret);
+ syslog(LOG_ERR, "Failed to initialize MWDT0: %d\n", ret);
+ return ret;
}
-#endif
-
-#ifdef CONFIG_FS_TMPFS
- /* Mount the tmpfs file system */
+#endif /* CONFIG_ESP32S3_MWDT0 */
- ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL);
+#ifdef CONFIG_ESP32S3_MWDT1
+ ret = esp32s3_wdt_initialize("/dev/watchdog1", ESP32S3_WDT_MWDT1);
if (ret < 0)
{
- syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n",
- CONFIG_LIBC_TMPDIR, ret);
+ syslog(LOG_ERR, "Failed to initialize MWDT1: %d\n", ret);
+ return ret;
}
-#endif
-
-#ifdef CONFIG_ESP32S3_TIMER
- /* Configure general purpose timers */
+#endif /* CONFIG_ESP32S3_MWDT1 */
- ret = board_tim_init();
+#ifdef CONFIG_ESP32S3_RWDT
+ ret = esp32s3_wdt_initialize("/dev/watchdog2", ESP32S3_WDT_RWDT);
if (ret < 0)
{
- syslog(LOG_ERR, "Failed to initialize timers: %d\n", ret);
+ syslog(LOG_ERR, "Failed to initialize RWDT: %d\n", ret);
+ return ret;
}
-#endif
+#endif /* CONFIG_ESP32S3_RWDT */
- /* If we got here then perhaps not all initialization was successful, but
- * at least enough succeeded to bring-up NSH with perhaps reduced
- * capabilities.
- */
-
- UNUSED(ret);
- return OK;
+ return ret;
}
+
diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/watchdog/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/watchdog/defconfig
new file mode 100644
index 0000000..19d61e1
--- /dev/null
+++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/watchdog/defconfig
@@ -0,0 +1,51 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_LEDS is not set
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_NSH_CMDPARMS is not set
+CONFIG_ARCH="xtensa"
+CONFIG_ARCH_BOARD="esp32s3-devkit"
+CONFIG_ARCH_BOARD_ESP32S3_DEVKIT=y
+CONFIG_ARCH_CHIP="esp32s3"
+CONFIG_ARCH_CHIP_ESP32S3=y
+CONFIG_ARCH_CHIP_ESP32S3WROOM1=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_XTENSA=y
+CONFIG_BOARD_LOOPSPERMSEC=16717
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_ESP32S3_MWDT0=y
+CONFIG_ESP32S3_MWDT1=y
+CONFIG_ESP32S3_UART0=y
+CONFIG_EXAMPLES_WATCHDOG=y
+CONFIG_FS_PROCFS=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_IDLETHREAD_STACKSIZE=3072
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_MM_REGIONS=3
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=114688
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_START_DAY=6
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2011
+CONFIG_SYSTEM_NSH=y
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_WATCHDOG=y
diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c
index a01e583..a5d54cd 100644
--- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c
+++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c
@@ -42,6 +42,10 @@
# include "esp32s3_board_tim.h"
#endif
+#ifdef CONFIG_WATCHDOG
+# include "esp32s3_board_wdt.h"
+#endif
+
#include "esp32s3-devkit.h"
/****************************************************************************
@@ -97,6 +101,16 @@ int esp32s3_bringup(void)
}
#endif
+#ifdef CONFIG_WATCHDOG
+ /* Configure watchdog timer */
+
+ ret = board_wdt_init();
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "Failed to initialize watchdog timer: %d\n", ret);
+ }
+#endif
+
/* If we got here then perhaps not all initialization was successful, but
* at least enough succeeded to bring-up NSH with perhaps reduced
* capabilities.
[incubator-nuttx] 01/02: xtensa/esp32s3: Add support for Main System Watchdog Timers
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit b49ee3d4ede1c59f8f1c5cb618423d79cc10e70c
Author: Gustavo Henrique Nihei <gu...@espressif.com>
AuthorDate: Tue Feb 22 10:31:36 2022 -0300
xtensa/esp32s3: Add support for Main System Watchdog Timers
Support for RTC Watchdog Timer is currently in place, but not yet
functional due to not yet implemented RTC driver.
Signed-off-by: Gustavo Henrique Nihei <gu...@espressif.com>
---
arch/xtensa/src/esp32s3/Kconfig | 31 +
arch/xtensa/src/esp32s3/Make.defs | 4 +
arch/xtensa/src/esp32s3/esp32s3_wdt.c | 879 +++++-
arch/xtensa/src/esp32s3/esp32s3_wdt.h | 115 +
arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c | 741 +++++
.../{esp32s3_wdt.c => esp32s3_wdt_lowerhalf.h} | 39 +-
arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h | 3245 ++++++++++++++++++++
arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h | 37 +
8 files changed, 5074 insertions(+), 17 deletions(-)
diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig
index 65ef822..e875786 100644
--- a/arch/xtensa/src/esp32s3/Kconfig
+++ b/arch/xtensa/src/esp32s3/Kconfig
@@ -306,6 +306,10 @@ config ESP32S3_TIMER
bool
default n
+config ESP32S3_WDT
+ bool
+ default n
+
config ESP32S3_UART0
bool "UART 0"
default n
@@ -355,6 +359,33 @@ config ESP32S3_TIMER3
---help---
Enables Timer 3
+config ESP32S3_MWDT0
+ bool "Main System Watchdog Timer (Group 0)"
+ default n
+ select ESP32S3_WDT
+ ---help---
+ Includes MWDT0. This watchdog timer is part of the Group 0
+ timer submodule.
+
+config ESP32S3_MWDT1
+ bool "Main System Watchdog Timer (Group 1)"
+ default n
+ select ESP32S3_WDT
+ ---help---
+ Includes MWDT1. This watchdog timer is part of the Group 0
+ timer submodule.
+
+config ESP32S3_RWDT
+ bool "RTC Watchdog Timer"
+ default n
+ select ESP32S3_WDT
+ ---help---
+ Includes RWDT. This watchdog timer is from the RTC module.
+ When it is selected, if the developer sets it to reset on expiration
+ it will reset Main System and the RTC module. If you don't want
+ to have the RTC module reset, please, use the Timers' Module WDTs.
+ They will only reset Main System.
+
endmenu # ESP32-S3 Peripheral Selection
menu "UART configuration"
diff --git a/arch/xtensa/src/esp32s3/Make.defs b/arch/xtensa/src/esp32s3/Make.defs
index aa94e75..f645ec1 100644
--- a/arch/xtensa/src/esp32s3/Make.defs
+++ b/arch/xtensa/src/esp32s3/Make.defs
@@ -79,3 +79,7 @@ ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += esp32s3_tim_lowerhalf.c
endif
endif
+
+ifeq ($(CONFIG_WATCHDOG),y)
+CHIP_CSRCS += esp32s3_wdt_lowerhalf.c
+endif
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wdt.c b/arch/xtensa/src/esp32s3/esp32s3_wdt.c
index 8592acd..43036bc 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_wdt.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_wdt.c
@@ -22,16 +22,831 @@
* Included Files
****************************************************************************/
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <stdbool.h>
+#include <assert.h>
+#include <debug.h>
+
#include "xtensa.h"
+#include "hardware/esp32s3_rtccntl.h"
+#include "hardware/esp32s3_tim.h"
+#include "hardware/esp32s3_efuse.h"
+#include "esp32s3_irq.h"
#include "esp32s3_wdt.h"
-#include "hardware/esp32s3_rtccntl.h"
+
+#ifdef CONFIG_ESP32S3_RWDT
+# error "RWDT not yet supported due to missing RTC driver!"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Check whether the provided device is a RTC Watchdog Timer */
+
+#define IS_RWDT(dev) (((struct esp32s3_wdt_priv_s *)dev)->base == \
+ RTC_CNTL_RTC_OPTIONS0_REG)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct esp32s3_wdt_priv_s
+{
+ struct esp32s3_wdt_ops_s *ops;
+ uint32_t base; /* WDT register base address */
+ uint8_t cpu; /* CPU ID */
+ uint8_t periph; /* Peripheral ID */
+ uint8_t irq; /* Interrupt ID */
+ int32_t cpuint; /* CPU interrupt assigned to this WDT */
+ bool inuse; /* Flag indicating if this WDT is in use */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* WDT registers access *****************************************************/
+
+static void wdt_putreg(struct esp32s3_wdt_dev_s *dev, uint32_t offset,
+ uint32_t value);
+static void wdt_modifyreg32(struct esp32s3_wdt_dev_s *dev, uint32_t offset,
+ uint32_t clearbits, uint32_t setbits);
+static uint32_t wdt_getreg(struct esp32s3_wdt_dev_s *dev, uint32_t offset);
+
+/* WDT operations ***********************************************************/
+
+static void wdt_start(struct esp32s3_wdt_dev_s *dev);
+static void wdt_stop(struct esp32s3_wdt_dev_s *dev);
+static void wdt_enablewp(struct esp32s3_wdt_dev_s *dev);
+static void wdt_disablewp(struct esp32s3_wdt_dev_s *dev);
+static void wdt_pre(struct esp32s3_wdt_dev_s *dev,
+ uint16_t value);
+static int32_t wdt_settimeout(struct esp32s3_wdt_dev_s *dev,
+ uint32_t value,
+ enum esp32s3_wdt_stage_e stage);
+static void wdt_feed(struct esp32s3_wdt_dev_s *dev);
+static int32_t wdt_config_stage(struct esp32s3_wdt_dev_s *dev,
+ enum esp32s3_wdt_stage_e stage,
+ enum esp32s3_wdt_stage_action_e cfg);
+static int32_t wdt_setisr(struct esp32s3_wdt_dev_s *dev,
+ xcpt_t handler, void *arg);
+static void wdt_enableint(struct esp32s3_wdt_dev_s *dev);
+static void wdt_disableint(struct esp32s3_wdt_dev_s *dev);
+static void wdt_ackint(struct esp32s3_wdt_dev_s *dev);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* ESP32-S3 WDT ops */
+
+struct esp32s3_wdt_ops_s esp32s3_mwdt_ops =
+{
+ .start = wdt_start,
+ .stop = wdt_stop,
+ .enablewp = wdt_enablewp,
+ .disablewp = wdt_disablewp,
+ .pre = wdt_pre,
+ .settimeout = wdt_settimeout,
+ .feed = wdt_feed,
+ .stg_conf = wdt_config_stage,
+ .rtc_clk = NULL,
+ .setisr = wdt_setisr,
+ .enableint = wdt_enableint,
+ .disableint = wdt_disableint,
+ .ackint = wdt_ackint,
+};
+
+struct esp32s3_wdt_ops_s esp32s3_rwdt_ops =
+{
+ .start = wdt_start,
+ .stop = wdt_stop,
+ .enablewp = wdt_enablewp,
+ .disablewp = wdt_disablewp,
+ .pre = NULL,
+ .settimeout = wdt_settimeout,
+ .feed = wdt_feed,
+ .stg_conf = wdt_config_stage,
+ .rtc_clk = NULL,
+ .setisr = wdt_setisr,
+ .enableint = wdt_enableint,
+ .disableint = wdt_disableint,
+ .ackint = wdt_ackint,
+};
+
+#ifdef CONFIG_ESP32S3_MWDT0
+struct esp32s3_wdt_priv_s g_esp32s3_mwdt0_priv =
+{
+ .ops = &esp32s3_mwdt_ops,
+ .base = TIMG_T0CONFIG_REG(0),
+ .periph = ESP32S3_PERIPH_TG_WDT_LEVEL,
+ .irq = ESP32S3_IRQ_TG_WDT_LEVEL,
+ .cpuint = -ENOMEM,
+ .inuse = false,
+};
+#endif
+
+#ifdef CONFIG_ESP32S3_MWDT1
+struct esp32s3_wdt_priv_s g_esp32s3_mwdt1_priv =
+{
+ .ops = &esp32s3_mwdt_ops,
+ .base = TIMG_T0CONFIG_REG(1),
+ .periph = ESP32S3_PERIPH_TG1_WDT_LEVEL,
+ .irq = ESP32S3_IRQ_TG1_WDT_LEVEL,
+ .cpuint = -ENOMEM,
+ .inuse = false,
+};
+#endif
+
+#ifdef CONFIG_ESP32S3_RWDT
+struct esp32s3_wdt_priv_s g_esp32s3_rwdt_priv =
+{
+ .ops = &esp32s3_rwdt_ops,
+ .base = RTC_CNTL_RTC_OPTIONS0_REG,
+ .periph = ESP32S3_PERIPH_RTC_CORE,
+ .irq = ESP32S3_IRQ_RTC_CORE,
+ .cpuint = -ENOMEM,
+ .inuse = false,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: wdt_putreg
+ *
+ * Description:
+ * Write a 32-bit register value by offset.
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ * offset - Offset value to the base address of the WDT device.
+ * value - Value to written to the specified memory region.
+ *
+ ****************************************************************************/
+
+static void wdt_putreg(struct esp32s3_wdt_dev_s *dev, uint32_t offset,
+ uint32_t value)
+{
+ DEBUGASSERT(dev != NULL);
+
+ putreg32(value, ((struct esp32s3_wdt_priv_s *)dev)->base + offset);
+}
+
+/****************************************************************************
+ * Name: wdt_modifyreg32
+ *
+ * Description:
+ * Atomically modify a 32-bit register value by offset.
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ * offset - Offset value to the base address of the WDT device.
+ * clearbits - Bits to be cleared on the specified memory region.
+ * setbits - Bits to be set on the specified memory region.
+ *
+ ****************************************************************************/
+
+static void wdt_modifyreg32(struct esp32s3_wdt_dev_s *dev, uint32_t offset,
+ uint32_t clearbits, uint32_t setbits)
+{
+ DEBUGASSERT(dev != NULL);
+
+ modifyreg32(((struct esp32s3_wdt_priv_s *)dev)->base + offset,
+ clearbits, setbits);
+}
+
+/****************************************************************************
+ * Name: wdt_getreg
+ *
+ * Description:
+ * Read a 32-bit register value by offset.
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ * offset - Offset value to the base address of the WDT device.
+ *
+ * Returned Values:
+ * A 32-bit value from the provided memory region of the WDT device.
+ *
+ ****************************************************************************/
+
+static uint32_t wdt_getreg(struct esp32s3_wdt_dev_s *dev, uint32_t offset)
+{
+ DEBUGASSERT(dev != NULL);
+
+ return getreg32(((struct esp32s3_wdt_priv_s *)dev)->base + offset);
+}
+
+/****************************************************************************
+ * Name: wdt_start
+ *
+ * Description:
+ * Release the counter.
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ *
+ ****************************************************************************/
+
+static void wdt_start(struct esp32s3_wdt_dev_s *dev)
+{
+ DEBUGASSERT(dev != NULL);
+
+ if (IS_RWDT(dev))
+ {
+ wdt_modifyreg32(dev, RWDT_CONFIG0_OFFSET, 0, RTC_CNTL_WDT_EN);
+ }
+ else
+ {
+ wdt_modifyreg32(dev, MWDT_CONFIG0_OFFSET, 0, TIMG_WDT_EN);
+ }
+}
+
+/****************************************************************************
+ * Name: wdt_config_stage
+ *
+ * Description:
+ * Configure the action to be triggered by a stage on expiration.
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ * stage - WDT stage to be configured.
+ * cfg - Action to be executed on stage expiration.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int32_t wdt_config_stage(struct esp32s3_wdt_dev_s *dev,
+ enum esp32s3_wdt_stage_e stage,
+ enum esp32s3_wdt_stage_action_e cfg)
+{
+ int32_t ret = OK;
+ uint32_t mask;
+
+ DEBUGASSERT(dev != NULL);
+
+ switch (stage)
+ {
+ case ESP32S3_WDT_STAGE0:
+ {
+ if (IS_RWDT(dev))
+ {
+ mask = (uint32_t)cfg << RTC_CNTL_WDT_STG0_S;
+ wdt_modifyreg32(dev, RWDT_CONFIG0_OFFSET, RTC_CNTL_WDT_STG0_M,
+ mask);
+ }
+ else
+ {
+ mask = (uint32_t)cfg << TIMG_WDT_STG0_S;
+ wdt_modifyreg32(dev, MWDT_CONFIG0_OFFSET, TIMG_WDT_STG0_M, mask);
+ }
+ break;
+ }
+
+ case ESP32S3_WDT_STAGE1:
+ {
+ if (IS_RWDT(dev))
+ {
+ mask = (uint32_t)cfg << RTC_CNTL_WDT_STG1_S;
+ wdt_modifyreg32(dev, RWDT_CONFIG0_OFFSET, RTC_CNTL_WDT_STG1_M,
+ mask);
+ }
+ else
+ {
+ mask = (uint32_t)cfg << TIMG_WDT_STG1_S;
+ wdt_modifyreg32(dev, MWDT_CONFIG0_OFFSET, TIMG_WDT_STG1_M, mask);
+ }
+ break;
+ }
+
+ case ESP32S3_WDT_STAGE2:
+ {
+ if (IS_RWDT(dev))
+ {
+ mask = (uint32_t)cfg << RTC_CNTL_WDT_STG2_S;
+ wdt_modifyreg32(dev, RWDT_CONFIG0_OFFSET, RTC_CNTL_WDT_STG2_M,
+ mask);
+ }
+ else
+ {
+ mask = (uint32_t)cfg << TIMG_WDT_STG2_S;
+ wdt_modifyreg32(dev, MWDT_CONFIG0_OFFSET, TIMG_WDT_STG2_M, mask);
+ }
+ break;
+ }
+
+ case ESP32S3_WDT_STAGE3:
+ {
+ if (IS_RWDT(dev))
+ {
+ mask = (uint32_t)cfg << RTC_CNTL_WDT_STG3_S;
+ wdt_modifyreg32(dev, RWDT_CONFIG0_OFFSET, RTC_CNTL_WDT_STG3_M,
+ mask);
+ }
+ else
+ {
+ mask = (uint32_t)cfg << TIMG_WDT_STG3_S;
+ wdt_modifyreg32(dev, MWDT_CONFIG0_OFFSET, TIMG_WDT_STG3_M, mask);
+ }
+ break;
+ }
+
+ default:
+ {
+ wderr("ERROR: unsupported stage %d\n", stage);
+ ret = -EINVAL;
+ goto errout;
+ }
+ }
+
+ errout:
+ return ret;
+}
+
+/****************************************************************************
+ * Name: wdt_stop
+ *
+ * Description:
+ * Disable the watchdog.
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ *
+ ****************************************************************************/
+
+static void wdt_stop(struct esp32s3_wdt_dev_s *dev)
+{
+ DEBUGASSERT(dev != NULL);
+
+ if (IS_RWDT(dev))
+ {
+ wdt_modifyreg32(dev, RWDT_CONFIG0_OFFSET, RTC_CNTL_WDT_EN, 0);
+ }
+ else
+ {
+ wdt_modifyreg32(dev, MWDT_CONFIG0_OFFSET, TIMG_WDT_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: wdt_enablewp
+ *
+ * Description:
+ * Enable write protection (WP) on registers against accidental writing.
+ * TRM recommends to change any WDT register through this sequence:
+ * - Disable WP
+ * - Do the op
+ * - Re-enable WP
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ *
+ ****************************************************************************/
+
+static void wdt_enablewp(struct esp32s3_wdt_dev_s *dev)
+{
+ DEBUGASSERT(dev != NULL);
+
+ if (IS_RWDT(dev))
+ {
+ wdt_putreg(dev, RWDT_WP_REG, 0);
+ }
+ else
+ {
+ wdt_putreg(dev, MWDT_WP_REG, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: wdt_disablewp
+ *
+ * Description:
+ * Disable write protection (WP) on registers against accidental writing.
+ * TRM recommends to change any WDT register through this sequence:
+ * - Disable WP
+ * - Do the op
+ * - Re-enable WP
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ *
+ ****************************************************************************/
+
+static void wdt_disablewp(struct esp32s3_wdt_dev_s *dev)
+{
+ DEBUGASSERT(dev != NULL);
+
+ if (IS_RWDT(dev))
+ {
+ wdt_putreg(dev, RWDT_WP_REG, RTC_CNTL_WDT_WKEY_VALUE);
+ }
+ else
+ {
+ wdt_putreg(dev, MWDT_WP_REG, TIMG_WDT_WKEY_VALUE);
+ }
+}
+
+/****************************************************************************
+ * Name: wdt_pre
+ *
+ * Description:
+ * Set a prescale value.
+ * The MWDT clock period is 12.5 ns * value (pre).
+ * NOTE: There's no prescaler register for RWDT and its source clock is
+ * clocked from the RTC slow clock.
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ * pre - Prescaler value to be configured.
+ *
+ ****************************************************************************/
+
+static void wdt_pre(struct esp32s3_wdt_dev_s *dev, uint16_t pre)
+{
+ uint32_t mask = (uint32_t)pre << TIMG_WDT_CLK_PRESCALE_S;
+
+ DEBUGASSERT(dev != NULL);
+
+ wdt_modifyreg32(dev, MWDT_CLK_PRESCALE_OFFSET, TIMG_WDT_CLK_PRESCALE_M,
+ mask);
+}
+
+/****************************************************************************
+ * Name: wdt_settimeout
+ *
+ * Description:
+ * Set the WDT timeout.
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ * value - Timeout value in number of WDT cycles.
+ * stage - Stage whose timeout value needs to be configured.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int32_t wdt_settimeout(struct esp32s3_wdt_dev_s *dev, uint32_t value,
+ enum esp32s3_wdt_stage_e stage)
+{
+ int32_t ret = OK;
+
+ DEBUGASSERT(dev != NULL);
+
+ switch (stage)
+ {
+ case ESP32S3_WDT_STAGE0:
+ {
+ if (IS_RWDT(dev))
+ {
+ /* The timeout of only stage 0 happens at:
+ * Thold0 = RTC_CNTL_WDT_STG0_HOLD << (EFUSE_WDT_DELAY_SEL + 1)
+ */
+
+ uint32_t delay;
+ delay = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG,
+ EFUSE_WDT_DELAY_SEL);
+ value = value >> (delay + 1);
+ wdt_putreg(dev, RWDT_STAGE0_TIMEOUT_OFFSET, value);
+ }
+ else
+ {
+ wdt_putreg(dev, MWDT_STAGE0_TIMEOUT_OFFSET, value);
+ }
+ break;
+ }
+
+ case ESP32S3_WDT_STAGE1:
+ {
+ if (IS_RWDT(dev))
+ {
+ wdt_putreg(dev, RWDT_STAGE1_TIMEOUT_OFFSET, value);
+ }
+ else
+ {
+ wdt_putreg(dev, MWDT_STAGE1_TIMEOUT_OFFSET, value);
+ }
+ break;
+ }
+
+ case ESP32S3_WDT_STAGE2:
+ {
+ if (IS_RWDT(dev))
+ {
+ wdt_putreg(dev, RWDT_STAGE2_TIMEOUT_OFFSET, value);
+ }
+ else
+ {
+ wdt_putreg(dev, MWDT_STAGE2_TIMEOUT_OFFSET, value);
+ }
+ break;
+ }
+
+ case ESP32S3_WDT_STAGE3:
+ {
+ if (IS_RWDT(dev))
+ {
+ wdt_putreg(dev, RWDT_STAGE3_TIMEOUT_OFFSET, value);
+ }
+ else
+ {
+ wdt_putreg(dev, MWDT_STAGE3_TIMEOUT_OFFSET, value);
+ }
+ break;
+ }
+
+ default:
+ {
+ wderr("ERROR: unsupported stage %d\n", stage);
+ ret = -EINVAL;
+ goto errout;
+ }
+ }
+
+ errout:
+ return ret;
+}
+
+/****************************************************************************
+ * Name: wdt_feed
+ *
+ * Description:
+ * Feed the watchdog.
+ * The watchdog timer returns to stage 0 and its counter restarts from 0.
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ *
+ ****************************************************************************/
+
+static void wdt_feed(struct esp32s3_wdt_dev_s *dev)
+{
+ DEBUGASSERT(dev != NULL);
+
+ if (IS_RWDT(dev))
+ {
+ wdt_modifyreg32(dev, RWDT_FEED_OFFSET, 0, RTC_CNTL_RTC_WDT_FEED);
+ }
+ else
+ {
+ wdt_putreg(dev, MWDT_FEED_OFFSET, TIMG_WDT_FEED);
+ }
+}
+
+/****************************************************************************
+ * Name: wdt_setisr
+ *
+ * Description:
+ * Allocate a Level CPU Interrupt, connect the peripheral source to this
+ * Interrupt, register the callback and enable the interrupt.
+ * In case a NULL handler is provided, deallocate the interrupt and
+ * unregister the previously provided handler.
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ * handler - Callback to be invoked on watchdog timer interrupt.
+ * arg - Argument to be passed to the handler callback.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int32_t wdt_setisr(struct esp32s3_wdt_dev_s *dev, xcpt_t handler,
+ void *arg)
+{
+ struct esp32s3_wdt_priv_s *wdt = NULL;
+ int32_t ret = OK;
+
+ DEBUGASSERT(dev != NULL);
+
+ wdt = (struct esp32s3_wdt_priv_s *)dev;
+
+ /* Disable interrupt when callback is removed. */
+
+ if (handler == NULL)
+ {
+ /* If a CPU Interrupt was previously allocated, then deallocate it */
+
+ if (wdt->cpuint >= 0)
+ {
+ /* Disable CPU Interrupt, free a previously allocated
+ * CPU Interrupt
+ */
+
+ up_disable_irq(wdt->irq);
+ esp32s3_teardown_irq(wdt->cpu, wdt->periph, wdt->cpuint);
+ irq_detach(wdt->irq);
+ }
+
+ ret = OK;
+ goto errout;
+ }
+
+ /* Otherwise set callback and enable interrupt. */
+
+ else
+ {
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ wdt->cpu = up_cpu_index();
+ wdt->cpuint = esp32s3_setup_irq(wdt->cpu, wdt->periph,
+ 1, ESP32S3_CPUINT_LEVEL);
+ if (wdt->cpuint < 0)
+ {
+ wderr("ERROR: No CPU Interrupt available");
+ ret = wdt->cpuint;
+ goto errout;
+ }
+
+ /* Associate an IRQ Number (from the WDT) to an ISR */
+
+ ret = irq_attach(wdt->irq, handler, arg);
+
+ if (ret != OK)
+ {
+ esp32s3_teardown_irq(wdt->cpu, wdt->periph, wdt->cpuint);
+ wderr("ERROR: Failed to associate an IRQ Number");
+ goto errout;
+ }
+
+ /* Enable the CPU Interrupt that is linked to the WDT */
+
+ up_enable_irq(wdt->irq);
+ }
+
+errout:
+ return ret;
+}
+
+/****************************************************************************
+ * Name: wdt_enableint
+ *
+ * Description:
+ * Enable a Level Interrupt at timeout.
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ *
+ ****************************************************************************/
+
+static void wdt_enableint(struct esp32s3_wdt_dev_s *dev)
+{
+ DEBUGASSERT(dev != NULL);
+
+ if (IS_RWDT(dev))
+ {
+ wdt_modifyreg32(dev, RWDT_INT_ENA_REG_OFFSET, 0,
+ RTC_CNTL_RTC_WDT_INT_ENA);
+ }
+ else
+ {
+ wdt_modifyreg32(dev, MWDT_INT_ENA_REG_OFFSET, 0, TIMG_WDT_INT_ENA);
+ }
+}
+
+/****************************************************************************
+ * Name: wdt_disableint
+ *
+ * Description:
+ * Disable a Level Interrupt at timeout.
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ *
+ ****************************************************************************/
+
+static void wdt_disableint(struct esp32s3_wdt_dev_s *dev)
+{
+ DEBUGASSERT(dev != NULL);
+
+ if (IS_RWDT(dev))
+ {
+ wdt_modifyreg32(dev, RWDT_INT_ENA_REG_OFFSET, RTC_CNTL_RTC_WDT_INT_ENA,
+ 0);
+ }
+ else
+ {
+ wdt_modifyreg32(dev, MWDT_INT_ENA_REG_OFFSET, TIMG_WDT_INT_ENA, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: wdt_ackint
+ *
+ * Description:
+ * Acknowledge an interrupt.
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ *
+ ****************************************************************************/
+
+static void wdt_ackint(struct esp32s3_wdt_dev_s *dev)
+{
+ DEBUGASSERT(dev != NULL);
+
+ if (IS_RWDT(dev))
+ {
+ wdt_putreg(dev, RWDT_INT_CLR_REG_OFFSET, RTC_CNTL_RTC_WDT_INT_CLR);
+ }
+ else
+ {
+ wdt_putreg(dev, MWDT_INT_CLR_REG_OFFSET, TIMG_WDT_INT_CLR);
+ }
+}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
+ * Name: esp32s3_wdt_init
+ *
+ * Description:
+ * Initialize WDT device.
+ *
+ * Parameters:
+ * wdt_id - A Watchdog Timer instance to be initialized.
+ *
+ * Return Values:
+ * Pointer to the driver state structure.
+ *
+ ****************************************************************************/
+
+struct esp32s3_wdt_dev_s *esp32s3_wdt_init(enum esp32s3_wdt_inst_e wdt_id)
+{
+ struct esp32s3_wdt_priv_s *wdt = NULL;
+
+ /* Get WDT instance */
+
+ switch (wdt_id)
+ {
+#ifdef CONFIG_ESP32S3_MWDT0
+ case ESP32S3_WDT_MWDT0:
+ {
+ wdt = &g_esp32s3_mwdt0_priv;
+ break;
+ }
+
+#endif
+
+#ifdef CONFIG_ESP32S3_MWDT1
+ case ESP32S3_WDT_MWDT1:
+ {
+ wdt = &g_esp32s3_mwdt1_priv;
+ break;
+ }
+#endif
+
+#ifdef CONFIG_ESP32S3_RWDT
+ case ESP32S3_WDT_RWDT:
+ {
+ wdt = &g_esp32s3_rwdt_priv;
+ break;
+ }
+
+#endif
+
+ default:
+ {
+ wderr("ERROR: unsupported WDT %d\n", wdt_id);
+ goto errout;
+ }
+ }
+
+ /* If some code is using it then sends an error message,
+ * Otherwise, inform it has been used.
+ */
+
+ if (wdt->inuse == true)
+ {
+ wderr("ERROR: WDT %d is already in use\n", wdt_id);
+ wdt = NULL;
+ }
+ else
+ {
+ wdt->inuse = true;
+ }
+
+ errout:
+ return (struct esp32s3_wdt_dev_s *)wdt;
+}
+
+/****************************************************************************
* Name: esp32s3_wdt_early_deinit
*
* Description:
@@ -48,3 +863,65 @@ void esp32s3_wdt_early_deinit(void)
putreg32(regval, RTC_CNTL_RTC_WDTCONFIG0_REG);
putreg32(0, RTC_CNTL_RTC_WDTWPROTECT_REG);
}
+
+/****************************************************************************
+ * Name: esp32s3_wdt_deinit
+ *
+ * Description:
+ * Deinitialize a WDT device.
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ *
+ ****************************************************************************/
+
+void esp32s3_wdt_deinit(struct esp32s3_wdt_dev_s *dev)
+{
+ struct esp32s3_wdt_priv_s *wdt = NULL;
+
+ DEBUGASSERT(dev != NULL);
+
+ wdt = (struct esp32s3_wdt_priv_s *)dev;
+
+ wdt->inuse = false;
+}
+
+/****************************************************************************
+ * Name: esp32s3_wdt_is_running
+ *
+ * Description:
+ * Check whether the WDT is already started.
+ *
+ * Parameters:
+ * dev - Pointer to the driver state structure.
+ *
+ * Returned Values:
+ * true if the Watchdog Timer is already started, false otherwise.
+ *
+ ****************************************************************************/
+
+bool esp32s3_wdt_is_running(struct esp32s3_wdt_dev_s *dev)
+{
+ uint32_t status = 0;
+
+ DEBUGASSERT(dev != NULL);
+
+ if (IS_RWDT(dev))
+ {
+ status = wdt_getreg(dev, RWDT_CONFIG0_OFFSET);
+ if ((status & RTC_CNTL_WDT_EN) == RTC_CNTL_WDT_EN)
+ {
+ return true;
+ }
+ }
+ else
+ {
+ status = wdt_getreg(dev, MWDT_CONFIG0_OFFSET);
+ if ((status & TIMG_WDT_EN) == TIMG_WDT_EN)
+ {
+ return true;
+ }
+ }
+
+ return false;
+}
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wdt.h b/arch/xtensa/src/esp32s3/esp32s3_wdt.h
index ee8f4e9..cac3f96 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_wdt.h
+++ b/arch/xtensa/src/esp32s3/esp32s3_wdt.h
@@ -25,10 +25,125 @@
* Included Files
****************************************************************************/
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <nuttx/irq.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Helpers ******************************************************************/
+
+#define ESP32S3_WDT_START(d) ((d)->ops->start(d))
+#define ESP32S3_WDT_STOP(d) ((d)->ops->stop(d))
+#define ESP32S3_WDT_LOCK(d) ((d)->ops->enablewp(d))
+#define ESP32S3_WDT_UNLOCK(d) ((d)->ops->disablewp(d))
+#define ESP32S3_MWDT_PRE(d, v) ((d)->ops->pre(d, v))
+#define ESP32S3_WDT_STO(d, v, s) ((d)->ops->settimeout(d, v, s))
+#define ESP32S3_WDT_FEED(d) ((d)->ops->feed(d))
+#define ESP32S3_WDT_STG_CONF(d, s, c) ((d)->ops->stg_conf(d, s, c))
+#define ESP32S3_RWDT_CLK(d) ((d)->ops->rtc_clk(d))
+#define ESP32S3_WDT_SETISR(d, hnd, arg) ((d)->ops->setisr(d, hnd, arg))
+#define ESP32S3_WDT_ENABLEINT(d) ((d)->ops->enableint(d))
+#define ESP32S3_WDT_DISABLEINT(d) ((d)->ops->disableint(d))
+#define ESP32S3_WDT_ACKINT(d) ((d)->ops->ackint(d))
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* Instances of Watchdog Timer */
+
+enum esp32s3_wdt_inst_e
+{
+ ESP32S3_WDT_MWDT0 = 0, /* Main System Watchdog Timer (MWDT) of Timer Group 0 */
+ ESP32S3_WDT_MWDT1, /* Main System Watchdog Timer (MWDT) of Timer Group 1 */
+ ESP32S3_WDT_RWDT /* RTC Watchdog Timer (RWDT) */
+};
+
+/* Stages of a Watchdog Timer. A WDT has 4 stages. */
+
+enum esp32s3_wdt_stage_e
+{
+ ESP32S3_WDT_STAGE0 = 0, /* Stage 0 */
+ ESP32S3_WDT_STAGE1 = 1, /* Stage 1 */
+ ESP32S3_WDT_STAGE2 = 2, /* Stage 2 */
+ ESP32S3_WDT_STAGE3 = 3 /* Stage 3 */
+};
+
+/**
+ * Behavior of the WDT stage if it times out.
+ *
+ * @note These enum values should be compatible with the
+ * corresponding register field values.
+ */
+
+enum esp32s3_wdt_stage_action_e
+{
+ ESP32S3_WDT_STAGE_ACTION_OFF = 0, /* Disabled. This stage will have no effects on the system. */
+ ESP32S3_WDT_STAGE_ACTION_INT = 1, /* Trigger an interrupt when the stage expires. */
+ ESP32S3_WDT_STAGE_ACTION_RESET_CPU = 2, /* Reset a CPU core when the stage expires. */
+ ESP32S3_WDT_STAGE_ACTION_RESET_SYSTEM = 3, /* Reset the main system when the stage expires.
+ * This includes the CPU and all peripherals.
+ * The RTC is an exception and will not be reset.
+ */
+ ESP32S3_WDT_STAGE_ACTION_RESET_RTC = 4 /* Reset the main system and the RTC when the stage expires.
+ * ONLY AVAILABLE FOR RWDT.
+ */
+};
+
+/* ESP32-S3 WDT device */
+
+struct esp32s3_wdt_dev_s
+{
+ struct esp32s3_wdt_ops_s *ops;
+};
+
+/* ESP32-S3 WDT operations
+ *
+ * This is a struct containing the pointers to the WDT operations.
+ */
+
+struct esp32s3_wdt_ops_s
+{
+ /* WDT tasks */
+
+ void (*start)(struct esp32s3_wdt_dev_s *dev);
+ void (*stop)(struct esp32s3_wdt_dev_s *dev);
+
+ /* WDT configuration */
+
+ void (*enablewp)(struct esp32s3_wdt_dev_s *dev);
+ void (*disablewp)(struct esp32s3_wdt_dev_s *dev);
+ void (*pre)(struct esp32s3_wdt_dev_s *dev, uint16_t value);
+ int32_t (*settimeout)(struct esp32s3_wdt_dev_s *dev,
+ uint32_t value,
+ enum esp32s3_wdt_stage_e stage);
+ void (*feed)(struct esp32s3_wdt_dev_s *dev);
+ int32_t (*stg_conf)(struct esp32s3_wdt_dev_s *dev,
+ enum esp32s3_wdt_stage_e stage,
+ enum esp32s3_wdt_stage_action_e conf);
+ uint16_t (*rtc_clk)(struct esp32s3_wdt_dev_s *dev);
+
+ /* WDT interrupts */
+
+ int32_t (*setisr)(struct esp32s3_wdt_dev_s *dev, xcpt_t handler,
+ void *arg);
+ void (*enableint)(struct esp32s3_wdt_dev_s *dev);
+ void (*disableint)(struct esp32s3_wdt_dev_s *dev);
+ void (*ackint)(struct esp32s3_wdt_dev_s *dev);
+};
+
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
+struct esp32s3_wdt_dev_s *esp32s3_wdt_init(enum esp32s3_wdt_inst_e wdt_id);
void esp32s3_wdt_early_deinit(void);
+void esp32s3_wdt_deinit(struct esp32s3_wdt_dev_s *dev);
+bool esp32s3_wdt_is_running(struct esp32s3_wdt_dev_s *dev);
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WDT_H */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c b/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c
new file mode 100644
index 0000000..be27a8a
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c
@@ -0,0 +1,741 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdbool.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/clock.h>
+#include <nuttx/timers/watchdog.h>
+
+#include "xtensa.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_wdt.h"
+#include "esp32s3_wdt_lowerhalf.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* MWDT clock period in microseconds */
+
+#define MWDT_CLK_PERIOD_US (500)
+
+/* Number of MWDT cycles per microseconds */
+
+#define MWDT_CYCLES_PER_MS (USEC_PER_MSEC / MWDT_CLK_PERIOD_US)
+
+/* Convert MWDT timeout cycles to milliseconds */
+
+#define MWDT_TIMEOUT_MS(t) ((t) * MWDT_CYCLES_PER_MS)
+
+/* Maximum number of MWDT cycles supported for timeout */
+
+#define MWDT_MAX_TIMEOUT_MS (UINT32_MAX / MWDT_CYCLES_PER_MS)
+
+/* MWDT clock prescaler value */
+
+#define MWDT_CLK_PRESCALER_VALUE (MWDT_CLK_PERIOD_US * NSEC_PER_USEC / 12.5)
+
+/* Maximum number of cycles supported for a RWDT stage timeout */
+
+#define RWDT_FULL_STAGE (UINT32_MAX)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+enum wdt_peripheral_e
+{
+ RTC,
+ TIMER,
+};
+
+/* This structure provides the private representation of the "lower-half"
+ * driver state structure. This structure must be cast-compatible with the
+ * well-known watchdog_lowerhalf_s structure.
+ */
+
+struct esp32s3_wdt_lowerhalf_s
+{
+ const struct watchdog_ops_s *ops; /* Lower half operations */
+ struct esp32s3_wdt_dev_s *wdt; /* ESP32-S3 watchdog driver */
+ uint32_t timeout; /* The current timeout */
+ enum wdt_peripheral_e peripheral; /* Indicates if it is from RTC or Timer Module */
+ uint32_t lastreset; /* The last reset time */
+ bool started; /* True: Timer has been started */
+ xcpt_t handler; /* User Handler */
+ void *upper; /* Pointer to watchdog_upperhalf_s */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Interrupt handling *******************************************************/
+
+static int wdt_handler(int irq, void *context, void *arg);
+
+/* "Lower half" driver methods **********************************************/
+
+static int wdt_lh_start(struct watchdog_lowerhalf_s *lower);
+static int wdt_lh_stop(struct watchdog_lowerhalf_s *lower);
+static int wdt_lh_keepalive(struct watchdog_lowerhalf_s *lower);
+static int wdt_lh_getstatus(struct watchdog_lowerhalf_s *lower,
+ struct watchdog_status_s *status);
+static int wdt_lh_settimeout(struct watchdog_lowerhalf_s *lower,
+ uint32_t timeout);
+static xcpt_t wdt_lh_capture(struct watchdog_lowerhalf_s *lower,
+ xcpt_t handler);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* "Lower half" driver methods */
+
+static const struct watchdog_ops_s g_esp32s3_wdg_ops =
+{
+ .start = wdt_lh_start,
+ .stop = wdt_lh_stop,
+ .keepalive = wdt_lh_keepalive,
+ .getstatus = wdt_lh_getstatus,
+ .settimeout = wdt_lh_settimeout,
+ .capture = wdt_lh_capture,
+ .ioctl = NULL,
+};
+
+#ifdef CONFIG_ESP32S3_MWDT0
+/* MWDT0 lower-half */
+
+static struct esp32s3_wdt_lowerhalf_s g_esp32s3_mwdt0_lowerhalf =
+{
+ .ops = &g_esp32s3_wdg_ops,
+};
+#endif
+
+#ifdef CONFIG_ESP32S3_MWDT1
+/* MWDT1 lower-half */
+
+static struct esp32s3_wdt_lowerhalf_s g_esp32s3_mwdt1_lowerhalf =
+{
+ .ops = &g_esp32s3_wdg_ops,
+};
+#endif
+
+#ifdef CONFIG_ESP32S3_RWDT
+/* RWDT lower-half */
+
+static struct esp32s3_wdt_lowerhalf_s g_esp32s3_rwdt_lowerhalf =
+{
+ .ops = &g_esp32s3_wdg_ops,
+};
+#endif
+
+/****************************************************************************
+ * Name: wdt_lh_start
+ *
+ * Description:
+ * Start the watchdog timer, register a callback if there is one and
+ * enables interrupt, otherwise, configure it to reset system on
+ * expiration.
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the
+ * "lower-half" driver state structure.
+ *
+ * Returned Values:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int wdt_lh_start(struct watchdog_lowerhalf_s *lower)
+{
+ struct esp32s3_wdt_lowerhalf_s *priv =
+ (struct esp32s3_wdt_lowerhalf_s *)lower;
+ int ret = OK;
+
+ wdinfo("Entry: wdt_lh_start\n");
+
+ DEBUGASSERT(priv);
+
+ if (priv->started == true)
+ {
+ /* Return EBUSY to indicate that the timer was already running */
+
+ ret = -EBUSY;
+ goto errout;
+ }
+
+ /* If WDT was not started yet */
+
+ else
+ {
+ irqstate_t flags;
+
+ priv->started = true;
+
+ /* Unlock WDT */
+
+ ESP32S3_WDT_UNLOCK(priv->wdt);
+
+ /* No User Handler */
+
+ if (priv->handler == NULL)
+ {
+ /* Then configure it to reset on wdt expiration */
+
+ if (priv->peripheral == TIMER)
+ {
+ ESP32S3_WDT_STG_CONF(priv->wdt, ESP32S3_WDT_STAGE0,
+ ESP32S3_WDT_STAGE_ACTION_RESET_SYSTEM);
+ }
+ else
+ {
+ ESP32S3_WDT_STG_CONF(priv->wdt, ESP32S3_WDT_STAGE0,
+ ESP32S3_WDT_STAGE_ACTION_RESET_RTC);
+ }
+ }
+
+ /* User handler was already provided */
+
+ else
+ {
+ /* Then configure it to call the user handler on wdt expiration */
+
+ ESP32S3_WDT_STG_CONF(priv->wdt, ESP32S3_WDT_STAGE0,
+ ESP32S3_WDT_STAGE_ACTION_INT);
+
+ /* Set the lower-half handler and enable interrupt */
+
+ flags = enter_critical_section();
+ ESP32S3_WDT_SETISR(priv->wdt, wdt_handler, priv);
+ leave_critical_section(flags);
+ ESP32S3_WDT_ENABLEINT(priv->wdt);
+ }
+
+ flags = enter_critical_section();
+ priv->lastreset = clock_systime_ticks();
+ ESP32S3_WDT_START(priv->wdt);
+ leave_critical_section(flags);
+
+ /* Lock it again */
+
+ ESP32S3_WDT_LOCK(priv->wdt);
+ }
+
+ errout:
+ return ret;
+}
+
+/****************************************************************************
+ * Name: wdt_lh_stop
+ *
+ * Description:
+ * Stop the watchdog timer. In case a callback was previously configured,
+ * unregister and deallocate it.
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the
+ * "lower-half" driver state structure.
+ *
+ ****************************************************************************/
+
+static int wdt_lh_stop(struct watchdog_lowerhalf_s *lower)
+{
+ struct esp32s3_wdt_lowerhalf_s *priv =
+ (struct esp32s3_wdt_lowerhalf_s *)lower;
+
+ /* Unlock WDT */
+
+ ESP32S3_WDT_UNLOCK(priv->wdt);
+
+ /* Disable the WDT */
+
+ ESP32S3_WDT_STOP(priv->wdt);
+
+ /* In case there is some callback registered, disable and deallocate */
+
+ if (priv->handler != NULL)
+ {
+ irqstate_t flags;
+
+ ESP32S3_WDT_DISABLEINT(priv->wdt);
+
+ flags = enter_critical_section();
+ ESP32S3_WDT_SETISR(priv->wdt, NULL, NULL);
+ leave_critical_section(flags);
+ }
+
+ /* Lock it again */
+
+ ESP32S3_WDT_LOCK(priv->wdt);
+
+ priv->started = false;
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: wdt_lh_keepalive
+ *
+ * Description:
+ * Reset the watchdog timer, prevent any
+ * imminent watchdog timeouts. This is sometimes referred as "pinging"
+ * the watchdog timer or "petting the dog".
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the
+ * "lower-half" driver state structure.
+ *
+ *
+ ****************************************************************************/
+
+static int wdt_lh_keepalive(struct watchdog_lowerhalf_s *lower)
+{
+ struct esp32s3_wdt_lowerhalf_s *priv =
+ (struct esp32s3_wdt_lowerhalf_s *)lower;
+ irqstate_t flags;
+
+ wdinfo("Entry\n");
+
+ /* Unlock */
+
+ ESP32S3_WDT_UNLOCK(priv->wdt);
+
+ /* Feed the dog and updates the lastreset variable */
+
+ flags = enter_critical_section();
+ priv->lastreset = clock_systime_ticks();
+ ESP32S3_WDT_FEED(priv->wdt);
+ leave_critical_section(flags);
+
+ /* Lock */
+
+ ESP32S3_WDT_LOCK(priv->wdt);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: wdt_lh_getstatus
+ *
+ * Description:
+ * Get the current watchdog timer status
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of
+ * the "lower-half" driver state structure.
+ * status - The location to return the watchdog status information.
+ *
+ ****************************************************************************/
+
+static int wdt_lh_getstatus(struct watchdog_lowerhalf_s *lower,
+ struct watchdog_status_s *status)
+{
+ struct esp32s3_wdt_lowerhalf_s *priv =
+ (struct esp32s3_wdt_lowerhalf_s *)lower;
+ uint32_t ticks;
+ uint32_t elapsed;
+
+ DEBUGASSERT(priv);
+
+ /* Flags */
+
+ status->flags = 0;
+
+ /* If no handler was settled, then RESET on expiration.
+ * Otherwise, call the user handler.
+ */
+
+ if (priv->handler == NULL)
+ {
+ status->flags |= WDFLAGS_RESET;
+ }
+ else
+ {
+ status->flags |= WDFLAGS_CAPTURE;
+ }
+
+ if (priv->started)
+ {
+ status->flags |= WDFLAGS_ACTIVE;
+ }
+
+ /* Return the current timeout in milliseconds */
+
+ status->timeout = priv->timeout;
+
+ /* Get the elapsed time since the last ping */
+
+ ticks = clock_systime_ticks() - priv->lastreset;
+ elapsed = (uint32_t)TICK2MSEC(ticks);
+
+ if (elapsed < priv->timeout)
+ {
+ /* Return the approximate time until the watchdog timer expiration */
+
+ status->timeleft = priv->timeout - elapsed;
+ }
+ else
+ {
+ status->timeleft = 0;
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: wdt_lh_settimeout
+ *
+ * Description:
+ * Set a new timeout value (and reset the watchdog timer)
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of
+ * the "lower-half" driver state structure.
+ * timeout - The new timeout value in milliseconds.
+ *
+ * Returned Values:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int wdt_lh_settimeout(struct watchdog_lowerhalf_s *lower,
+ uint32_t timeout)
+{
+ struct esp32s3_wdt_lowerhalf_s *priv =
+ (struct esp32s3_wdt_lowerhalf_s *)lower;
+ uint16_t rtc_cycles = 0;
+ uint32_t rtc_ms_max = 0;
+
+ wdinfo("Entry: timeout=%" PRIu32 "\n", timeout);
+ DEBUGASSERT(priv);
+
+ /* Unlock WDT */
+
+ ESP32S3_WDT_UNLOCK(priv->wdt);
+
+ /* Write the timeout value */
+
+ priv->timeout = timeout;
+
+ /* Watchdog from Timer Module */
+
+ if (priv->peripheral == TIMER)
+ {
+ /* Is this timeout a valid value for Timer's WDT? */
+
+ if (timeout == 0 || timeout > MWDT_MAX_TIMEOUT_MS)
+ {
+ wderr("Cannot represent timeout=%" PRIu32 " > %" PRIu32 "\n",
+ timeout, MWDT_MAX_TIMEOUT_MS);
+ return -ERANGE;
+ }
+ else
+ {
+ ESP32S3_WDT_STO(priv->wdt, MWDT_TIMEOUT_MS(timeout),
+ ESP32S3_WDT_STAGE0);
+ }
+ }
+
+ /* Watchdog from RTC Module */
+
+ else
+ {
+ rtc_cycles = ESP32S3_RWDT_CLK(priv->wdt);
+ rtc_ms_max = (RWDT_FULL_STAGE / (uint32_t)rtc_cycles);
+
+ /* Is this timeout a valid value for RTC WDT? */
+
+ if (timeout == 0 || timeout > rtc_ms_max)
+ {
+ wderr("Cannot represent timeout=%" PRIu32 " > %" PRIu32 "\n",
+ timeout, rtc_ms_max);
+ return -ERANGE;
+ }
+ else
+ {
+ timeout = timeout * rtc_cycles;
+ ESP32S3_WDT_STO(priv->wdt, timeout, ESP32S3_WDT_STAGE0);
+ }
+ }
+
+ /* Reset the wdt */
+
+ ESP32S3_WDT_FEED(priv->wdt);
+
+ /* Lock it again */
+
+ ESP32S3_WDT_LOCK(priv->wdt);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: wdt_lh_capture
+ *
+ * Description:
+ * Don't reset on watchdog timer timeout; instead, call this user provider
+ * timeout handler. NOTE: Providing handler==NULL will restore the reset
+ * behavior.
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the
+ * "lower-half" driver state structure.
+ * newhandler - The new watchdog expiration function pointer. If this
+ * function pointer is NULL, then the reset-on-expiration
+ * behavior is restored,
+ *
+ * Returned Value:
+ * The previous watchdog expiration function pointer or NULL if there was
+ * no previous function pointer, i.e., if the previous behavior was
+ * reset-on-expiration (NULL is also returned if an error occurs).
+ *
+ ****************************************************************************/
+
+static xcpt_t wdt_lh_capture(struct watchdog_lowerhalf_s *lower,
+ xcpt_t handler)
+{
+ struct esp32s3_wdt_lowerhalf_s *priv =
+ (struct esp32s3_wdt_lowerhalf_s *)lower;
+ irqstate_t flags;
+ xcpt_t oldhandler;
+
+ DEBUGASSERT(priv);
+
+ wdinfo("Entry: handler=0x%" PRIxPTR "\n", (uintptr_t) handler);
+
+ /* Get the old handler to return it */
+
+ oldhandler = priv->handler;
+
+ ESP32S3_WDT_UNLOCK(priv->wdt);
+
+ flags = enter_critical_section();
+
+ /* Save the new user handler */
+
+ priv->handler = handler;
+
+ /* There is a user callback and the timer has already been started.
+ * The user wants to set a callback after starting the wdt or wants to
+ * change the callback function once a callback has already been settled.
+ */
+
+ if (priv->handler != NULL && priv->started == true)
+ {
+ /* Deallocate the previous allocated interrupt
+ * If there is a previous allocated interrupt.
+ */
+
+ if (oldhandler != NULL)
+ {
+ ESP32S3_WDT_SETISR(priv->wdt, NULL, NULL);
+ }
+ else
+ {
+ /* If it was previous configured to reset on timeout
+ * then change to interrupt.
+ */
+
+ ESP32S3_WDT_STG_CONF(priv->wdt, ESP32S3_WDT_STAGE0,
+ ESP32S3_WDT_STAGE_ACTION_INT);
+ }
+
+ /* Set the lower-half handler and enable interrupt */
+
+ ESP32S3_WDT_SETISR(priv->wdt, wdt_handler, priv);
+ ESP32S3_WDT_ENABLEINT(priv->wdt);
+ }
+
+ /* In case the user wants to disable the callback */
+
+ else
+ {
+ ESP32S3_WDT_DISABLEINT(priv->wdt);
+ ESP32S3_WDT_SETISR(priv->wdt, NULL, NULL);
+
+ /* Then configure it to reset on WDT expiration */
+
+ if (priv->peripheral == TIMER)
+ {
+ ESP32S3_WDT_STG_CONF(priv->wdt, ESP32S3_WDT_STAGE0,
+ ESP32S3_WDT_STAGE_ACTION_RESET_SYSTEM);
+ }
+ else
+ {
+ ESP32S3_WDT_STG_CONF(priv->wdt, ESP32S3_WDT_STAGE0,
+ ESP32S3_WDT_STAGE_ACTION_RESET_RTC);
+ }
+ }
+
+ leave_critical_section(flags);
+ ESP32S3_WDT_LOCK(priv->wdt);
+ return oldhandler;
+}
+
+/* Interrupt handling *******************************************************/
+
+static int wdt_handler(int irq, void *context, void *arg)
+{
+ struct esp32s3_wdt_lowerhalf_s *priv = arg;
+
+ /* Run the user callback */
+
+ priv->handler(irq, context, priv->upper);
+
+ /* Clear the Interrupt */
+
+ ESP32S3_WDT_UNLOCK(priv->wdt);
+
+ ESP32S3_WDT_ACKINT(priv->wdt);
+
+ ESP32S3_WDT_LOCK(priv->wdt);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_wdt_initialize
+ *
+ * Description:
+ * Initialize the watchdog timer. The watchdog timer is initialized
+ * and registered as 'devpath'.
+ *
+ * Input Parameters:
+ * devpath - The full path to the watchdog. This should
+ * be of the form /dev/watchdogX
+ * wdt - WDT instance to be initialized.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; a negated errno value is returned on
+ * any failure.
+ *
+ ****************************************************************************/
+
+int esp32s3_wdt_initialize(const char *devpath, enum esp32s3_wdt_inst_e wdt)
+{
+ struct esp32s3_wdt_lowerhalf_s *lower = NULL;
+ int ret = OK;
+
+ DEBUGASSERT(devpath);
+
+ switch (wdt)
+ {
+#ifdef CONFIG_ESP32S3_MWDT0
+ case ESP32S3_WDT_MWDT0:
+ {
+ lower = &g_esp32s3_mwdt0_lowerhalf;
+ lower->peripheral = TIMER;
+ break;
+ }
+#endif
+
+#ifdef CONFIG_ESP32S3_MWDT1
+ case ESP32S3_WDT_MWDT1:
+ {
+ lower = &g_esp32s3_mwdt1_lowerhalf;
+ lower->peripheral = TIMER;
+ break;
+ }
+#endif
+
+#ifdef CONFIG_ESP32S3_RWDT
+ case ESP32S3_WDT_RWDT:
+ {
+ lower = &g_esp32s3_rwdt_lowerhalf;
+ lower->peripheral = RTC;
+ break;
+ }
+#endif
+
+ default:
+ {
+ ret = -ENODEV;
+ goto errout;
+ }
+ }
+
+ /* Initialize the elements of lower-half state structure */
+
+ lower->handler = NULL;
+ lower->timeout = 0;
+ lower->wdt = esp32s3_wdt_init(wdt);
+
+ if (lower->wdt == NULL)
+ {
+ ret = -EINVAL;
+ goto errout;
+ }
+
+ lower->started = esp32s3_wdt_is_running(lower->wdt);
+
+ ESP32S3_WDT_UNLOCK(lower->wdt);
+
+ /* If it is a Main System Watchdog Timer configure the Prescale to
+ * have a 500us period.
+ */
+
+ if (lower->peripheral == TIMER)
+ {
+ ESP32S3_MWDT_PRE(lower->wdt, MWDT_CLK_PRESCALER_VALUE);
+ }
+
+ ESP32S3_WDT_LOCK(lower->wdt);
+
+ /* Register the watchdog driver as /dev/watchdogX. If the registration goes
+ * right the returned value from watchdog_register is a pointer to
+ * watchdog_upperhalf_s that can be either used with watchdog_unregister()
+ * or with the handler's arg.
+ */
+
+ lower->upper = watchdog_register(devpath,
+ (struct watchdog_lowerhalf_s *)lower);
+ if (lower->upper == NULL)
+ {
+ /* The actual cause of the failure may have been a failure to allocate
+ * perhaps a failure to register the watchdog driver (such as if the
+ * 'devpath' were not unique). We know here but we return EEXIST to
+ * indicate the failure (implying the non-unique devpath).
+ */
+
+ ret = -EEXIST;
+ goto errout;
+ }
+
+errout:
+ return ret;
+}
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wdt.c b/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.h
similarity index 62%
copy from arch/xtensa/src/esp32s3/esp32s3_wdt.c
copy to arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.h
index 8592acd..767772a 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_wdt.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/xtensa/src/esp32s3/esp32s3_wdt.c
+ * arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,33 +18,40 @@
*
****************************************************************************/
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WDT_LOWERHALF_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WDT_LOWERHALF_H
+
/****************************************************************************
* Included Files
****************************************************************************/
-#include "xtensa.h"
-
#include "esp32s3_wdt.h"
-#include "hardware/esp32s3_rtccntl.h"
/****************************************************************************
- * Public Functions
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
****************************************************************************/
/****************************************************************************
- * Name: esp32s3_wdt_early_deinit
+ * Name: esp32s3_wdt_initialize
*
* Description:
- * Disable the WDT(s) that was/were enabled by the bootloader.
+ * Initialize the watchdog timer. The watchdog timer is initialized
+ * and registered as 'devpath'.
+ *
+ * Input Parameters:
+ * devpath - The full path to the watchdog.
+ * wdt - WDT instance to be initialized.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; a negated errno value is returned on
+ * any failure.
*
****************************************************************************/
-void esp32s3_wdt_early_deinit(void)
-{
- uint32_t regval;
- putreg32(RTC_CNTL_WDT_WKEY_VALUE, RTC_CNTL_RTC_WDTWPROTECT_REG);
- regval = getreg32(RTC_CNTL_RTC_WDTCONFIG0_REG);
- regval &= ~RTC_CNTL_WDT_EN;
- putreg32(regval, RTC_CNTL_RTC_WDTCONFIG0_REG);
- putreg32(0, RTC_CNTL_RTC_WDTWPROTECT_REG);
-}
+int esp32s3_wdt_initialize(const char *devpath, enum esp32s3_wdt_inst_e wdt);
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WDT_LOWERHALF_H */
diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h
new file mode 100644
index 0000000..45dcedc
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h
@@ -0,0 +1,3245 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EFUSE_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EFUSE_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* EFUSE_PGM_DATA0_REG register
+ * Register 0 that stores data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
+
+/* EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ * The content of the 0th 32-bit data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA_0 0xffffffff
+#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
+#define EFUSE_PGM_DATA_0_V 0xffffffff
+#define EFUSE_PGM_DATA_0_S 0
+
+/* EFUSE_PGM_DATA1_REG register
+ * Register 1 that stores data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
+
+/* EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ * The content of the 1st 32-bit data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA_1 0xffffffff
+#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
+#define EFUSE_PGM_DATA_1_V 0xffffffff
+#define EFUSE_PGM_DATA_1_S 0
+
+/* EFUSE_PGM_DATA2_REG register
+ * Register 2 that stores data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
+
+/* EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ * The content of the 2nd 32-bit data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA_2 0xffffffff
+#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
+#define EFUSE_PGM_DATA_2_V 0xffffffff
+#define EFUSE_PGM_DATA_2_S 0
+
+/* EFUSE_PGM_DATA3_REG register
+ * Register 3 that stores data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
+
+/* EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
+ * The content of the 3rd 32-bit data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA_3 0xffffffff
+#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
+#define EFUSE_PGM_DATA_3_V 0xffffffff
+#define EFUSE_PGM_DATA_3_S 0
+
+/* EFUSE_PGM_DATA4_REG register
+ * Register 4 that stores data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
+
+/* EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
+ * The content of the 4th 32-bit data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA_4 0xffffffff
+#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
+#define EFUSE_PGM_DATA_4_V 0xffffffff
+#define EFUSE_PGM_DATA_4_S 0
+
+/* EFUSE_PGM_DATA5_REG register
+ * Register 5 that stores data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
+
+/* EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
+ * The content of the 5th 32-bit data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA_5 0xffffffff
+#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
+#define EFUSE_PGM_DATA_5_V 0xffffffff
+#define EFUSE_PGM_DATA_5_S 0
+
+/* EFUSE_PGM_DATA6_REG register
+ * Register 6 that stores data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
+
+/* EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
+ * The content of the 6th 32-bit data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA_6 0xffffffff
+#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
+#define EFUSE_PGM_DATA_6_V 0xffffffff
+#define EFUSE_PGM_DATA_6_S 0
+
+/* EFUSE_PGM_DATA7_REG register
+ * Register 7 that stores data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
+
+/* EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
+ * The content of the 7th 32-bit data to be programmed.
+ */
+
+#define EFUSE_PGM_DATA_7 0xffffffff
+#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
+#define EFUSE_PGM_DATA_7_V 0xffffffff
+#define EFUSE_PGM_DATA_7_S 0
+
+/* EFUSE_PGM_CHECK_VALUE0_REG register
+ * Register 0 that stores the RS code to be programmed.
+ */
+
+#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
+
+/* EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ * The content of the 0th 32-bit RS code to be programmed.
+ */
+
+#define EFUSE_PGM_RS_DATA_0 0xffffffff
+#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
+#define EFUSE_PGM_RS_DATA_0_V 0xffffffff
+#define EFUSE_PGM_RS_DATA_0_S 0
+
+/* EFUSE_PGM_CHECK_VALUE1_REG register
+ * Register 1 that stores the RS code to be programmed.
+ */
+
+#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
+
+/* EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ * The content of the 1st 32-bit RS code to be programmed.
+ */
+
+#define EFUSE_PGM_RS_DATA_1 0xffffffff
+#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
+#define EFUSE_PGM_RS_DATA_1_V 0xffffffff
+#define EFUSE_PGM_RS_DATA_1_S 0
+
+/* EFUSE_PGM_CHECK_VALUE2_REG register
+ * Register 2 that stores the RS code to be programmed.
+ */
+
+#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
+
+/* EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ * The content of the 2nd 32-bit RS code to be programmed.
+ */
+
+#define EFUSE_PGM_RS_DATA_2 0xffffffff
+#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
+#define EFUSE_PGM_RS_DATA_2_V 0xffffffff
+#define EFUSE_PGM_RS_DATA_2_S 0
+
+/* EFUSE_RD_WR_DIS_REG register
+ * BLOCK0 data register 0.
+ */
+
+#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
+
+/* EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ * Disable programming of individual eFuses.
+ */
+
+#define EFUSE_WR_DIS 0xffffffff
+#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
+#define EFUSE_WR_DIS_V 0xffffffff
+#define EFUSE_WR_DIS_S 0
+
+/* EFUSE_RD_REPEAT_DATA0_REG register
+ * BLOCK0 data register 1.
+ */
+
+#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
+
+/* EFUSE_VDD_SPI_DREFH : RO; bitpos: [31:30]; default: 0;
+ * SPI regulator high voltage reference.
+ */
+
+#define EFUSE_VDD_SPI_DREFH 0x00000003
+#define EFUSE_VDD_SPI_DREFH_M (EFUSE_VDD_SPI_DREFH_V << EFUSE_VDD_SPI_DREFH_S)
+#define EFUSE_VDD_SPI_DREFH_V 0x00000003
+#define EFUSE_VDD_SPI_DREFH_S 30
+
+/* EFUSE_VDD_SPI_MODECURLIM : RO; bitpos: [29]; default: 0;
+ * SPI regulator switches current limit mode.
+ */
+
+#define EFUSE_VDD_SPI_MODECURLIM (BIT(29))
+#define EFUSE_VDD_SPI_MODECURLIM_M (EFUSE_VDD_SPI_MODECURLIM_V << EFUSE_VDD_SPI_MODECURLIM_S)
+#define EFUSE_VDD_SPI_MODECURLIM_V 0x00000001
+#define EFUSE_VDD_SPI_MODECURLIM_S 29
+
+/* EFUSE_BTLC_GPIO_ENABLE : RO; bitpos: [28:27]; default: 0;
+ * Bluetooth GPIO signal output security level control.
+ */
+
+#define EFUSE_BTLC_GPIO_ENABLE 0x00000003
+#define EFUSE_BTLC_GPIO_ENABLE_M (EFUSE_BTLC_GPIO_ENABLE_V << EFUSE_BTLC_GPIO_ENABLE_S)
+#define EFUSE_BTLC_GPIO_ENABLE_V 0x00000003
+#define EFUSE_BTLC_GPIO_ENABLE_S 27
+
+/* EFUSE_EXT_PHY_ENABLE : RO; bitpos: [26]; default: 0;
+ * Set this bit to enable external PHY.
+ */
+
+#define EFUSE_EXT_PHY_ENABLE (BIT(26))
+#define EFUSE_EXT_PHY_ENABLE_M (EFUSE_EXT_PHY_ENABLE_V << EFUSE_EXT_PHY_ENABLE_S)
+#define EFUSE_EXT_PHY_ENABLE_V 0x00000001
+#define EFUSE_EXT_PHY_ENABLE_S 26
+
+/* EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0;
+ * Set this bit to exchange USB D+ and D- pins.
+ */
+
+#define EFUSE_USB_EXCHG_PINS (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S)
+#define EFUSE_USB_EXCHG_PINS_V 0x00000001
+#define EFUSE_USB_EXCHG_PINS_S 25
+
+/* EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
+ * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of
+ * 80 mV, stored in eFuse.
+ */
+
+#define EFUSE_USB_DREFL 0x00000003
+#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
+#define EFUSE_USB_DREFL_V 0x00000003
+#define EFUSE_USB_DREFL_S 23
+
+/* EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
+ * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80
+ * mV, stored in eFuse.
+ */
+
+#define EFUSE_USB_DREFH 0x00000003
+#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
+#define EFUSE_USB_DREFH_V 0x00000003
+#define EFUSE_USB_DREFH_S 21
+
+/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
+ * Set this bit to disable flash encryption when in download boot modes.
+ */
+
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20
+
+/* EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
+ * Set this bit to disable JTAG in the hard way. JTAG is disabled
+ * permanently.
+ */
+
+#define EFUSE_DIS_PAD_JTAG (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
+#define EFUSE_DIS_PAD_JTAG_V 0x00000001
+#define EFUSE_DIS_PAD_JTAG_S 19
+
+/* EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
+ * Set these bits to disable JTAG in the soft way (odd number 1 means
+ * disable ). JTAG can be enabled in HMAC module.
+ */
+
+#define EFUSE_SOFT_DIS_JTAG 0x00000007
+#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
+#define EFUSE_SOFT_DIS_JTAG_V 0x00000007
+#define EFUSE_SOFT_DIS_JTAG_S 16
+
+/* EFUSE_DIS_APP_CPU : RO; bitpos: [15]; default: 0;
+ * Disable app cpu.
+ */
+
+#define EFUSE_DIS_APP_CPU (BIT(15))
+#define EFUSE_DIS_APP_CPU_M (EFUSE_DIS_APP_CPU_V << EFUSE_DIS_APP_CPU_S)
+#define EFUSE_DIS_APP_CPU_V 0x00000001
+#define EFUSE_DIS_APP_CPU_S 15
+
+/* EFUSE_DIS_CAN : RO; bitpos: [14]; default: 0;
+ * Set this bit to disable CAN function.
+ */
+
+#define EFUSE_DIS_CAN (BIT(14))
+#define EFUSE_DIS_CAN_M (EFUSE_DIS_CAN_V << EFUSE_DIS_CAN_S)
+#define EFUSE_DIS_CAN_V 0x00000001
+#define EFUSE_DIS_CAN_S 14
+
+/* EFUSE_DIS_USB : RO; bitpos: [13]; default: 0;
+ * Set this bit to disable USB function.
+ */
+
+#define EFUSE_DIS_USB (BIT(13))
+#define EFUSE_DIS_USB_M (EFUSE_DIS_USB_V << EFUSE_DIS_USB_S)
+#define EFUSE_DIS_USB_V 0x00000001
+#define EFUSE_DIS_USB_S 13
+
+/* EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
+ * Set this bit to disable the function that forces chip into download mode.
+ */
+
+#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001
+#define EFUSE_DIS_FORCE_DOWNLOAD_S 12
+
+/* EFUSE_DIS_DOWNLOAD_DCACHE : RO; bitpos: [11]; default: 0;
+ * Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1,
+ * 2, 3, 6, 7).
+ */
+
+#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11))
+#define EFUSE_DIS_DOWNLOAD_DCACHE_M (EFUSE_DIS_DOWNLOAD_DCACHE_V << EFUSE_DIS_DOWNLOAD_DCACHE_S)
+#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x00000001
+#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11
+
+/* EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0;
+ * Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1,
+ * 2, 3, 6, 7).
+ */
+
+#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S)
+#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001
+#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10
+
+/* EFUSE_DIS_DCACHE : RO; bitpos: [9]; default: 0;
+ * Set this bit to disable Dcache.
+ */
+
+#define EFUSE_DIS_DCACHE (BIT(9))
+#define EFUSE_DIS_DCACHE_M (EFUSE_DIS_DCACHE_V << EFUSE_DIS_DCACHE_S)
+#define EFUSE_DIS_DCACHE_V 0x00000001
+#define EFUSE_DIS_DCACHE_S 9
+
+/* EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0;
+ * Set this bit to disable Icache.
+ */
+
+#define EFUSE_DIS_ICACHE (BIT(8))
+#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S)
+#define EFUSE_DIS_ICACHE_V 0x00000001
+#define EFUSE_DIS_ICACHE_S 8
+
+/* EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0;
+ * Set this bit to disable boot from RTC RAM.
+ */
+
+#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_M (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S)
+#define EFUSE_DIS_RTC_RAM_BOOT_V 0x00000001
+#define EFUSE_DIS_RTC_RAM_BOOT_S 7
+
+/* EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
+ * Set this bit to disable reading from BlOCK4-10.
+ */
+
+#define EFUSE_RD_DIS 0x0000007f
+#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
+#define EFUSE_RD_DIS_V 0x0000007f
+#define EFUSE_RD_DIS_S 0
+
+/* EFUSE_RD_REPEAT_DATA1_REG register
+ * BLOCK0 data register 2.
+ */
+
+#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
+
+/* EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
+ * Purpose of Key1.
+ */
+
+#define EFUSE_KEY_PURPOSE_1 0x0000000f
+#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
+#define EFUSE_KEY_PURPOSE_1_V 0x0000000f
+#define EFUSE_KEY_PURPOSE_1_S 28
+
+/* EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
+ * Purpose of Key0.
+ */
+
+#define EFUSE_KEY_PURPOSE_0 0x0000000f
+#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
+#define EFUSE_KEY_PURPOSE_0_V 0x0000000f
+#define EFUSE_KEY_PURPOSE_0_S 24
+
+/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
+ * Set this bit to enable revoking third secure boot key.
+ */
+
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23
+
+/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
+ * Set this bit to enable revoking second secure boot key.
+ */
+
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22
+
+/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
+ * Set this bit to enable revoking first secure boot key.
+ */
+
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21
+
+/* EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
+ * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable.
+ * even number of 1: disable.
+ */
+
+#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18
+
+/* EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
+ * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0:
+ * 40000. 1: 80000. 2: 160000. 3:320000.
+ */
+
+#define EFUSE_WDT_DELAY_SEL 0x00000003
+#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
+#define EFUSE_WDT_DELAY_SEL_V 0x00000003
+#define EFUSE_WDT_DELAY_SEL_S 16
+
+/* EFUSE_VDD_SPI_DCAP : RO; bitpos: [15:14]; default: 0;
+ * Prevents SPI regulator from overshoot.
+ */
+
+#define EFUSE_VDD_SPI_DCAP 0x00000003
+#define EFUSE_VDD_SPI_DCAP_M (EFUSE_VDD_SPI_DCAP_V << EFUSE_VDD_SPI_DCAP_S)
+#define EFUSE_VDD_SPI_DCAP_V 0x00000003
+#define EFUSE_VDD_SPI_DCAP_S 14
+
+/* EFUSE_VDD_SPI_INIT : RO; bitpos: [13:12]; default: 0;
+ * Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K
+ * 3: 2 K.
+ */
+
+#define EFUSE_VDD_SPI_INIT 0x00000003
+#define EFUSE_VDD_SPI_INIT_M (EFUSE_VDD_SPI_INIT_V << EFUSE_VDD_SPI_INIT_S)
+#define EFUSE_VDD_SPI_INIT_V 0x00000003
+#define EFUSE_VDD_SPI_INIT_S 12
+
+/* EFUSE_VDD_SPI_DCURLIM : RO; bitpos: [11:9]; default: 0;
+ * Tunes the current limit threshold of SPI regulator when tieh=0, about 800
+ * mA/(8+d).
+ */
+
+#define EFUSE_VDD_SPI_DCURLIM 0x00000007
+#define EFUSE_VDD_SPI_DCURLIM_M (EFUSE_VDD_SPI_DCURLIM_V << EFUSE_VDD_SPI_DCURLIM_S)
+#define EFUSE_VDD_SPI_DCURLIM_V 0x00000007
+#define EFUSE_VDD_SPI_DCURLIM_S 9
+
+/* EFUSE_VDD_SPI_ENCURLIM : RO; bitpos: [8]; default: 0;
+ * Set SPI regulator to 1 to enable output current limit.
+ */
+
+#define EFUSE_VDD_SPI_ENCURLIM (BIT(8))
+#define EFUSE_VDD_SPI_ENCURLIM_M (EFUSE_VDD_SPI_ENCURLIM_V << EFUSE_VDD_SPI_ENCURLIM_S)
+#define EFUSE_VDD_SPI_ENCURLIM_V 0x00000001
+#define EFUSE_VDD_SPI_ENCURLIM_S 8
+
+/* EFUSE_VDD_SPI_EN_INIT : RO; bitpos: [7]; default: 0;
+ * Set SPI regulator to 0 to configure init[1:0]=0.
+ */
+
+#define EFUSE_VDD_SPI_EN_INIT (BIT(7))
+#define EFUSE_VDD_SPI_EN_INIT_M (EFUSE_VDD_SPI_EN_INIT_V << EFUSE_VDD_SPI_EN_INIT_S)
+#define EFUSE_VDD_SPI_EN_INIT_V 0x00000001
+#define EFUSE_VDD_SPI_EN_INIT_S 7
+
+/* EFUSE_VDD_SPI_FORCE : RO; bitpos: [6]; default: 0;
+ * Set this bit and force to use the configuration of eFuse to configure
+ * VDD_SPI.
+ */
+
+#define EFUSE_VDD_SPI_FORCE (BIT(6))
+#define EFUSE_VDD_SPI_FORCE_M (EFUSE_VDD_SPI_FORCE_V << EFUSE_VDD_SPI_FORCE_S)
+#define EFUSE_VDD_SPI_FORCE_V 0x00000001
+#define EFUSE_VDD_SPI_FORCE_S 6
+
+/* EFUSE_VDD_SPI_TIEH : RO; bitpos: [5]; default: 0;
+ * SPI regulator output is short connected to VDD3P3_RTC_IO.
+ */
+
+#define EFUSE_VDD_SPI_TIEH (BIT(5))
+#define EFUSE_VDD_SPI_TIEH_M (EFUSE_VDD_SPI_TIEH_V << EFUSE_VDD_SPI_TIEH_S)
+#define EFUSE_VDD_SPI_TIEH_V 0x00000001
+#define EFUSE_VDD_SPI_TIEH_S 5
+
+/* EFUSE_VDD_SPI_XPD : RO; bitpos: [4]; default: 0;
+ * SPI regulator power up signal.
+ */
+
+#define EFUSE_VDD_SPI_XPD (BIT(4))
+#define EFUSE_VDD_SPI_XPD_M (EFUSE_VDD_SPI_XPD_V << EFUSE_VDD_SPI_XPD_S)
+#define EFUSE_VDD_SPI_XPD_V 0x00000001
+#define EFUSE_VDD_SPI_XPD_S 4
+
+/* EFUSE_VDD_SPI_DREFL : RO; bitpos: [3:2]; default: 0;
+ * SPI regulator low voltage reference.
+ */
+
+#define EFUSE_VDD_SPI_DREFL 0x00000003
+#define EFUSE_VDD_SPI_DREFL_M (EFUSE_VDD_SPI_DREFL_V << EFUSE_VDD_SPI_DREFL_S)
+#define EFUSE_VDD_SPI_DREFL_V 0x00000003
+#define EFUSE_VDD_SPI_DREFL_S 2
+
+/* EFUSE_VDD_SPI_DREFM : RO; bitpos: [1:0]; default: 0;
+ * SPI regulator medium voltage reference.
+ */
+
+#define EFUSE_VDD_SPI_DREFM 0x00000003
+#define EFUSE_VDD_SPI_DREFM_M (EFUSE_VDD_SPI_DREFM_V << EFUSE_VDD_SPI_DREFM_S)
+#define EFUSE_VDD_SPI_DREFM_V 0x00000003
+#define EFUSE_VDD_SPI_DREFM_S 0
+
+/* EFUSE_RD_REPEAT_DATA2_REG register
+ * BLOCK0 data register 3.
+ */
+
+#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
+
+/* EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
+ * Configures flash waiting time after power-up, in unit of ms. If the value
+ * is less than 15, the waiting time is the configurable value. Otherwise,
+ * the waiting time is twice the configurable value.
+ */
+
+#define EFUSE_FLASH_TPUW 0x0000000f
+#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
+#define EFUSE_FLASH_TPUW_V 0x0000000f
+#define EFUSE_FLASH_TPUW_S 28
+
+/* EFUSE_POWER_GLITCH_DSENSE : RO; bitpos: [27:26]; default: 0;
+ * Sample delay configuration of power glitch.
+ */
+
+#define EFUSE_POWER_GLITCH_DSENSE 0x00000003
+#define EFUSE_POWER_GLITCH_DSENSE_M (EFUSE_POWER_GLITCH_DSENSE_V << EFUSE_POWER_GLITCH_DSENSE_S)
+#define EFUSE_POWER_GLITCH_DSENSE_V 0x00000003
+#define EFUSE_POWER_GLITCH_DSENSE_S 26
+
+/* EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0;
+ * This bit is used to switch internal PHY and external PHY for USB OTG and
+ * USB Device. 0: internal PHY is assigned to USB Device while external PHY
+ * is assigned to USB OTG. 1: internal PHY is assigned to USB OTG while
+ * external PHY is assigned to USB Device.
+ */
+
+#define EFUSE_USB_PHY_SEL (BIT(25))
+#define EFUSE_USB_PHY_SEL_M (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S)
+#define EFUSE_USB_PHY_SEL_V 0x00000001
+#define EFUSE_USB_PHY_SEL_S 25
+
+/* EFUSE_STRAP_JTAG_SEL : RO; bitpos: [24]; default: 0;
+ * Set this bit to enable selection between usb_to_jtag and pad_to_jtag
+ * through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag
+ * are equal to 0.
+ */
+
+#define EFUSE_STRAP_JTAG_SEL (BIT(24))
+#define EFUSE_STRAP_JTAG_SEL_M (EFUSE_STRAP_JTAG_SEL_V << EFUSE_STRAP_JTAG_SEL_S)
+#define EFUSE_STRAP_JTAG_SEL_V 0x00000001
+#define EFUSE_STRAP_JTAG_SEL_S 24
+
+/* EFUSE_DIS_USB_DEVICE : RO; bitpos: [23]; default: 0;
+ * Set this bit to disable usb device.
+ */
+
+#define EFUSE_DIS_USB_DEVICE (BIT(23))
+#define EFUSE_DIS_USB_DEVICE_M (EFUSE_DIS_USB_DEVICE_V << EFUSE_DIS_USB_DEVICE_S)
+#define EFUSE_DIS_USB_DEVICE_V 0x00000001
+#define EFUSE_DIS_USB_DEVICE_S 23
+
+/* EFUSE_DIS_USB_JTAG : RO; bitpos: [22]; default: 0;
+ * Set this bit to disable function of usb switch to jtag in module of usb
+ * device.
+ */
+
+#define EFUSE_DIS_USB_JTAG (BIT(22))
+#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
+#define EFUSE_DIS_USB_JTAG_V 0x00000001
+#define EFUSE_DIS_USB_JTAG_S 22
+
+/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
+ * Set this bit to enable revoking aggressive secure boot.
+ */
+
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21
+
+/* EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
+ * Set this bit to enable secure boot.
+ */
+
+#define EFUSE_SECURE_BOOT_EN (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
+#define EFUSE_SECURE_BOOT_EN_V 0x00000001
+#define EFUSE_SECURE_BOOT_EN_S 20
+
+/* EFUSE_RPT4_RESERVED0 : RO; bitpos: [19:16]; default: 0;
+ * Reserved (used for four backups method).
+ */
+
+#define EFUSE_RPT4_RESERVED0 0x0000000f
+#define EFUSE_RPT4_RESERVED0_M (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S)
+#define EFUSE_RPT4_RESERVED0_V 0x0000000f
+#define EFUSE_RPT4_RESERVED0_S 16
+
+/* EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
+ * Purpose of Key5.
+ */
+
+#define EFUSE_KEY_PURPOSE_5 0x0000000f
+#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
+#define EFUSE_KEY_PURPOSE_5_V 0x0000000f
+#define EFUSE_KEY_PURPOSE_5_S 12
+
+/* EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
+ * Purpose of Key4.
+ */
+
+#define EFUSE_KEY_PURPOSE_4 0x0000000f
+#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
+#define EFUSE_KEY_PURPOSE_4_V 0x0000000f
+#define EFUSE_KEY_PURPOSE_4_S 8
+
+/* EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
+ * Purpose of Key3.
+ */
+
+#define EFUSE_KEY_PURPOSE_3 0x0000000f
+#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
+#define EFUSE_KEY_PURPOSE_3_V 0x0000000f
+#define EFUSE_KEY_PURPOSE_3_S 4
+
+/* EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
+ * Purpose of Key2.
+ */
+
+#define EFUSE_KEY_PURPOSE_2 0x0000000f
+#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
+#define EFUSE_KEY_PURPOSE_2_V 0x0000000f
+#define EFUSE_KEY_PURPOSE_2_S 0
+
+/* EFUSE_RD_REPEAT_DATA3_REG register
+ * BLOCK0 data register 4.
+ */
+
+#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
+
+/* EFUSE_RPT4_RESERVED1 : RO; bitpos: [31]; default: 0;
+ * Reserved (used for four backups method).
+ */
+
+#define EFUSE_RPT4_RESERVED1 (BIT(31))
+#define EFUSE_RPT4_RESERVED1_M (EFUSE_RPT4_RESERVED1_V << EFUSE_RPT4_RESERVED1_S)
+#define EFUSE_RPT4_RESERVED1_V 0x00000001
+#define EFUSE_RPT4_RESERVED1_S 31
+
+/* EFUSE_POWERGLITCH_EN : RO; bitpos: [30]; default: 0;
+ * Set this bit to enable power glitch function.
+ */
+
+#define EFUSE_POWERGLITCH_EN (BIT(30))
+#define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
+#define EFUSE_POWERGLITCH_EN_V 0x00000001
+#define EFUSE_POWERGLITCH_EN_S 30
+
+/* EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0;
+ * Secure version (used by ESP-IDF anti-rollback feature).
+ */
+
+#define EFUSE_SECURE_VERSION 0x0000ffff
+#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
+#define EFUSE_SECURE_VERSION_V 0x0000ffff
+#define EFUSE_SECURE_VERSION_S 14
+
+/* EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0;
+ * Set this bit to force ROM code to send a resume command during SPI boot.
+ */
+
+#define EFUSE_FORCE_SEND_RESUME (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
+#define EFUSE_FORCE_SEND_RESUME_V 0x00000001
+#define EFUSE_FORCE_SEND_RESUME_S 13
+
+/* EFUSE_FLASH_ECC_EN : RO; bitpos: [12]; default: 0;
+ * Set 1 to enable ECC for flash boot.
+ */
+
+#define EFUSE_FLASH_ECC_EN (BIT(12))
+#define EFUSE_FLASH_ECC_EN_M (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S)
+#define EFUSE_FLASH_ECC_EN_V 0x00000001
+#define EFUSE_FLASH_ECC_EN_S 12
+
+/* EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [11:10]; default: 0;
+ * Set Flash page size.
+ */
+
+#define EFUSE_FLASH_PAGE_SIZE 0x00000003
+#define EFUSE_FLASH_PAGE_SIZE_M (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S)
+#define EFUSE_FLASH_PAGE_SIZE_V 0x00000003
+#define EFUSE_FLASH_PAGE_SIZE_S 10
+
+/* EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0;
+ * Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
+ */
+
+#define EFUSE_FLASH_TYPE (BIT(9))
+#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S)
+#define EFUSE_FLASH_TYPE_V 0x00000001
+#define EFUSE_FLASH_TYPE_S 9
+
+/* EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0;
+ * GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1:
+ * VDD_SPI.
+ */
+
+#define EFUSE_PIN_POWER_SELECTION (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_M (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S)
+#define EFUSE_PIN_POWER_SELECTION_V 0x00000001
+#define EFUSE_PIN_POWER_SELECTION_S 8
+
+/* EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
+ * Set the default UARTboot message output mode. 00: Enabled. 01: Enabled
+ * when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset.
+ * 11:disabled.
+ */
+
+#define EFUSE_UART_PRINT_CONTROL 0x00000003
+#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
+#define EFUSE_UART_PRINT_CONTROL_V 0x00000003
+#define EFUSE_UART_PRINT_CONTROL_S 6
+
+/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
+ * Set this bit to enable secure UART download mode.
+ */
+
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5
+
+/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
+ * Set this bit to disable UART download mode through USB.
+ */
+
+#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (EFUSE_DIS_USB_DOWNLOAD_MODE_V << EFUSE_DIS_USB_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x00000001
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4
+
+/* EFUSE_FLASH_ECC_MODE : RO; bitpos: [3]; default: 0;
+ * Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode.
+ * 1:ROM would use 16to17 byte mode.
+ */
+
+#define EFUSE_FLASH_ECC_MODE (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_M (EFUSE_FLASH_ECC_MODE_V << EFUSE_FLASH_ECC_MODE_S)
+#define EFUSE_FLASH_ECC_MODE_V 0x00000001
+#define EFUSE_FLASH_ECC_MODE_S 3
+
+/* EFUSE_UART_PRINT_CHANNEL : RO; bitpos: [2]; default: 0;
+ * Selectes the default UART print channel. 0: UART0. 1: UART1.
+ */
+
+#define EFUSE_UART_PRINT_CHANNEL (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_M (EFUSE_UART_PRINT_CHANNEL_V << EFUSE_UART_PRINT_CHANNEL_S)
+#define EFUSE_UART_PRINT_CHANNEL_V 0x00000001
+#define EFUSE_UART_PRINT_CHANNEL_S 2
+
+/* EFUSE_DIS_LEGACY_SPI_BOOT : RO; bitpos: [1]; default: 0;
+ * Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).
+ */
+
+#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_M (EFUSE_DIS_LEGACY_SPI_BOOT_V << EFUSE_DIS_LEGACY_SPI_BOOT_S)
+#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x00000001
+#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1
+
+/* EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
+ * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
+ */
+
+#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001
+#define EFUSE_DIS_DOWNLOAD_MODE_S 0
+
+/* EFUSE_RD_REPEAT_DATA4_REG register
+ * BLOCK0 data register 5.
+ */
+
+#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
+
+/* EFUSE_RPT4_RESERVED2 : RO; bitpos: [23:0]; default: 0;
+ * Reserved (used for four backups method).
+ */
+
+#define EFUSE_RPT4_RESERVED2 0x00ffffff
+#define EFUSE_RPT4_RESERVED2_M (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S)
+#define EFUSE_RPT4_RESERVED2_V 0x00ffffff
+#define EFUSE_RPT4_RESERVED2_S 0
+
+/* EFUSE_RD_MAC_SPI_SYS_0_REG register
+ * BLOCK1 data register 0.
+ */
+
+#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
+
+/* EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
+ * Stores the low 32 bits of MAC address.
+ */
+
+#define EFUSE_MAC_0 0xffffffff
+#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
+#define EFUSE_MAC_0_V 0xffffffff
+#define EFUSE_MAC_0_S 0
+
+/* EFUSE_RD_MAC_SPI_SYS_1_REG register
+ * BLOCK1 data register 1.
+ */
+
+#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
+
+/* EFUSE_SPI_PAD_CONF_0 : RO; bitpos: [31:16]; default: 0;
+ * Stores the zeroth part of SPI_PAD_CONF.
+ */
+
+#define EFUSE_SPI_PAD_CONF_0 0x0000ffff
+#define EFUSE_SPI_PAD_CONF_0_M (EFUSE_SPI_PAD_CONF_0_V << EFUSE_SPI_PAD_CONF_0_S)
+#define EFUSE_SPI_PAD_CONF_0_V 0x0000ffff
+#define EFUSE_SPI_PAD_CONF_0_S 16
+
+/* EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
+ * Stores the high 16 bits of MAC address.
+ */
+
+#define EFUSE_MAC_1 0x0000ffff
+#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
+#define EFUSE_MAC_1_V 0x0000ffff
+#define EFUSE_MAC_1_S 0
+
+/* EFUSE_RD_MAC_SPI_SYS_2_REG register
+ * BLOCK1 data register 2.
+ */
+
+#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
+
+/* EFUSE_SPI_PAD_CONF_1 : RO; bitpos: [31:0]; default: 0;
+ * Stores the first part of SPI_PAD_CONF.
+ */
+
+#define EFUSE_SPI_PAD_CONF_1 0xffffffff
+#define EFUSE_SPI_PAD_CONF_1_M (EFUSE_SPI_PAD_CONF_1_V << EFUSE_SPI_PAD_CONF_1_S)
+#define EFUSE_SPI_PAD_CONF_1_V 0xffffffff
+#define EFUSE_SPI_PAD_CONF_1_S 0
+
+/* EFUSE_RD_MAC_SPI_SYS_3_REG register
+ * BLOCK1 data register 3.
+ */
+
+#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
+
+/* EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
+ * Stores the fist 14 bits of the zeroth part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART0_0 0x00003fff
+#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
+#define EFUSE_SYS_DATA_PART0_0_V 0x00003fff
+#define EFUSE_SYS_DATA_PART0_0_S 18
+
+/* EFUSE_SPI_PAD_CONF_2 : RO; bitpos: [17:0]; default: 0;
+ * Stores the second part of SPI_PAD_CONF.
+ */
+
+#define EFUSE_SPI_PAD_CONF_2 0x0003ffff
+#define EFUSE_SPI_PAD_CONF_2_M (EFUSE_SPI_PAD_CONF_2_V << EFUSE_SPI_PAD_CONF_2_S)
+#define EFUSE_SPI_PAD_CONF_2_V 0x0003ffff
+#define EFUSE_SPI_PAD_CONF_2_S 0
+
+/* EFUSE_RD_MAC_SPI_SYS_4_REG register
+ * BLOCK1 data register 4.
+ */
+
+#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
+
+/* EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fist 32 bits of the zeroth part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART0_1 0xffffffff
+#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
+#define EFUSE_SYS_DATA_PART0_1_V 0xffffffff
+#define EFUSE_SYS_DATA_PART0_1_S 0
+
+/* EFUSE_RD_MAC_SPI_SYS_5_REG register
+ * BLOCK1 data register 5.
+ */
+
+#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
+
+/* EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
+ * Stores the second 32 bits of the zeroth part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART0_2 0xffffffff
+#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
+#define EFUSE_SYS_DATA_PART0_2_V 0xffffffff
+#define EFUSE_SYS_DATA_PART0_2_S 0
+
+/* EFUSE_RD_SYS_PART1_DATA0_REG register
+ * Register 0 of BLOCK2 (system).
+ */
+
+#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
+
+/* EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0;
+ * Stores the zeroth 32 bits of the first part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART1_0 0xffffffff
+#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S)
+#define EFUSE_SYS_DATA_PART1_0_V 0xffffffff
+#define EFUSE_SYS_DATA_PART1_0_S 0
+
+/* EFUSE_RD_SYS_PART1_DATA1_REG register
+ * Register 1 of BLOCK2 (system).
+ */
+
+#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
+
+/* EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0;
+ * Stores the first 32 bits of the first part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART1_1 0xffffffff
+#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S)
+#define EFUSE_SYS_DATA_PART1_1_V 0xffffffff
+#define EFUSE_SYS_DATA_PART1_1_S 0
+
+/* EFUSE_RD_SYS_PART1_DATA2_REG register
+ * Register 2 of BLOCK2 (system).
+ */
+
+#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
+
+/* EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0;
+ * Stores the second 32 bits of the first part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART1_2 0xffffffff
+#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S)
+#define EFUSE_SYS_DATA_PART1_2_V 0xffffffff
+#define EFUSE_SYS_DATA_PART1_2_S 0
+
+/* EFUSE_RD_SYS_PART1_DATA3_REG register
+ * Register 3 of BLOCK2 (system).
+ */
+
+#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
+
+/* EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0;
+ * Stores the third 32 bits of the first part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART1_3 0xffffffff
+#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S)
+#define EFUSE_SYS_DATA_PART1_3_V 0xffffffff
+#define EFUSE_SYS_DATA_PART1_3_S 0
+
+/* EFUSE_RD_SYS_PART1_DATA4_REG register
+ * Register 4 of BLOCK2 (system).
+ */
+
+#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
+
+/* EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fourth 32 bits of the first part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART1_4 0xffffffff
+#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
+#define EFUSE_SYS_DATA_PART1_4_V 0xffffffff
+#define EFUSE_SYS_DATA_PART1_4_S 0
+
+/* EFUSE_RD_SYS_PART1_DATA5_REG register
+ * Register 5 of BLOCK2 (system).
+ */
+
+#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
+
+/* EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fifth 32 bits of the first part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART1_5 0xffffffff
+#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
+#define EFUSE_SYS_DATA_PART1_5_V 0xffffffff
+#define EFUSE_SYS_DATA_PART1_5_S 0
+
+/* EFUSE_RD_SYS_PART1_DATA6_REG register
+ * Register 6 of BLOCK2 (system).
+ */
+
+#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
+
+/* EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
+ * Stores the sixth 32 bits of the first part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART1_6 0xffffffff
+#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
+#define EFUSE_SYS_DATA_PART1_6_V 0xffffffff
+#define EFUSE_SYS_DATA_PART1_6_S 0
+
+/* EFUSE_RD_SYS_PART1_DATA7_REG register
+ * Register 7 of BLOCK2 (system).
+ */
+
+#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
+
+/* EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
+ * Stores the seventh 32 bits of the first part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART1_7 0xffffffff
+#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
+#define EFUSE_SYS_DATA_PART1_7_V 0xffffffff
+#define EFUSE_SYS_DATA_PART1_7_S 0
+
+/* EFUSE_RD_USR_DATA0_REG register
+ * Register 0 of BLOCK3 (user).
+ */
+
+#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
+
+/* EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
+ * Stores the zeroth 32 bits of BLOCK3 (user).
+ */
+
+#define EFUSE_USR_DATA0 0xffffffff
+#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
+#define EFUSE_USR_DATA0_V 0xffffffff
+#define EFUSE_USR_DATA0_S 0
+
+/* EFUSE_RD_USR_DATA1_REG register
+ * Register 1 of BLOCK3 (user).
+ */
+
+#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
+
+/* EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
+ * Stores the first 32 bits of BLOCK3 (user).
+ */
+
+#define EFUSE_USR_DATA1 0xffffffff
+#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
+#define EFUSE_USR_DATA1_V 0xffffffff
+#define EFUSE_USR_DATA1_S 0
+
+/* EFUSE_RD_USR_DATA2_REG register
+ * Register 2 of BLOCK3 (user).
+ */
+
+#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
+
+/* EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
+ * Stores the second 32 bits of BLOCK3 (user).
+ */
+
+#define EFUSE_USR_DATA2 0xffffffff
+#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
+#define EFUSE_USR_DATA2_V 0xffffffff
+#define EFUSE_USR_DATA2_S 0
+
+/* EFUSE_RD_USR_DATA3_REG register
+ * Register 3 of BLOCK3 (user).
+ */
+
+#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
+
+/* EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
+ * Stores the third 32 bits of BLOCK3 (user).
+ */
+
+#define EFUSE_USR_DATA3 0xffffffff
+#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
+#define EFUSE_USR_DATA3_V 0xffffffff
+#define EFUSE_USR_DATA3_S 0
+
+/* EFUSE_RD_USR_DATA4_REG register
+ * Register 4 of BLOCK3 (user).
+ */
+
+#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
+
+/* EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fourth 32 bits of BLOCK3 (user).
+ */
+
+#define EFUSE_USR_DATA4 0xffffffff
+#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
+#define EFUSE_USR_DATA4_V 0xffffffff
+#define EFUSE_USR_DATA4_S 0
+
+/* EFUSE_RD_USR_DATA5_REG register
+ * Register 5 of BLOCK3 (user).
+ */
+
+#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
+
+/* EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fifth 32 bits of BLOCK3 (user).
+ */
+
+#define EFUSE_USR_DATA5 0xffffffff
+#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
+#define EFUSE_USR_DATA5_V 0xffffffff
+#define EFUSE_USR_DATA5_S 0
+
+/* EFUSE_RD_USR_DATA6_REG register
+ * Register 6 of BLOCK3 (user).
+ */
+
+#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
+
+/* EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0;
+ * Stores the sixth 32 bits of BLOCK3 (user).
+ */
+
+#define EFUSE_USR_DATA6 0xffffffff
+#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S)
+#define EFUSE_USR_DATA6_V 0xffffffff
+#define EFUSE_USR_DATA6_S 0
+
+/* EFUSE_RD_USR_DATA7_REG register
+ * Register 7 of BLOCK3 (user).
+ */
+
+#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
+
+/* EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0;
+ * Stores the seventh 32 bits of BLOCK3 (user).
+ */
+
+#define EFUSE_USR_DATA7 0xffffffff
+#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S)
+#define EFUSE_USR_DATA7_V 0xffffffff
+#define EFUSE_USR_DATA7_S 0
+
+/* EFUSE_RD_KEY0_DATA0_REG register
+ * Register 0 of BLOCK4 (KEY0).
+ */
+
+#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
+
+/* EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
+ * Stores the zeroth 32 bits of KEY0.
+ */
+
+#define EFUSE_KEY0_DATA0 0xffffffff
+#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
+#define EFUSE_KEY0_DATA0_V 0xffffffff
+#define EFUSE_KEY0_DATA0_S 0
+
+/* EFUSE_RD_KEY0_DATA1_REG register
+ * Register 1 of BLOCK4 (KEY0).
+ */
+
+#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
+
+/* EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
+ * Stores the first 32 bits of KEY0.
+ */
+
+#define EFUSE_KEY0_DATA1 0xffffffff
+#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
+#define EFUSE_KEY0_DATA1_V 0xffffffff
+#define EFUSE_KEY0_DATA1_S 0
+
+/* EFUSE_RD_KEY0_DATA2_REG register
+ * Register 2 of BLOCK4 (KEY0).
+ */
+
+#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
+
+/* EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
+ * Stores the second 32 bits of KEY0.
+ */
+
+#define EFUSE_KEY0_DATA2 0xffffffff
+#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
+#define EFUSE_KEY0_DATA2_V 0xffffffff
+#define EFUSE_KEY0_DATA2_S 0
+
+/* EFUSE_RD_KEY0_DATA3_REG register
+ * Register 3 of BLOCK4 (KEY0).
+ */
+
+#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
+
+/* EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
+ * Stores the third 32 bits of KEY0.
+ */
+
+#define EFUSE_KEY0_DATA3 0xffffffff
+#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
+#define EFUSE_KEY0_DATA3_V 0xffffffff
+#define EFUSE_KEY0_DATA3_S 0
+
+/* EFUSE_RD_KEY0_DATA4_REG register
+ * Register 4 of BLOCK4 (KEY0).
+ */
+
+#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
+
+/* EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fourth 32 bits of KEY0.
+ */
+
+#define EFUSE_KEY0_DATA4 0xffffffff
+#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
+#define EFUSE_KEY0_DATA4_V 0xffffffff
+#define EFUSE_KEY0_DATA4_S 0
+
+/* EFUSE_RD_KEY0_DATA5_REG register
+ * Register 5 of BLOCK4 (KEY0).
+ */
+
+#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
+
+/* EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fifth 32 bits of KEY0.
+ */
+
+#define EFUSE_KEY0_DATA5 0xffffffff
+#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
+#define EFUSE_KEY0_DATA5_V 0xffffffff
+#define EFUSE_KEY0_DATA5_S 0
+
+/* EFUSE_RD_KEY0_DATA6_REG register
+ * Register 6 of BLOCK4 (KEY0).
+ */
+
+#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
+
+/* EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
+ * Stores the sixth 32 bits of KEY0.
+ */
+
+#define EFUSE_KEY0_DATA6 0xffffffff
+#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
+#define EFUSE_KEY0_DATA6_V 0xffffffff
+#define EFUSE_KEY0_DATA6_S 0
+
+/* EFUSE_RD_KEY0_DATA7_REG register
+ * Register 7 of BLOCK4 (KEY0).
+ */
+
+#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
+
+/* EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
+ * Stores the seventh 32 bits of KEY0.
+ */
+
+#define EFUSE_KEY0_DATA7 0xffffffff
+#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
+#define EFUSE_KEY0_DATA7_V 0xffffffff
+#define EFUSE_KEY0_DATA7_S 0
+
+/* EFUSE_RD_KEY1_DATA0_REG register
+ * Register 0 of BLOCK5 (KEY1).
+ */
+
+#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
+
+/* EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
+ * Stores the zeroth 32 bits of KEY1.
+ */
+
+#define EFUSE_KEY1_DATA0 0xffffffff
+#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
+#define EFUSE_KEY1_DATA0_V 0xffffffff
+#define EFUSE_KEY1_DATA0_S 0
+
+/* EFUSE_RD_KEY1_DATA1_REG register
+ * Register 1 of BLOCK5 (KEY1).
+ */
+
+#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
+
+/* EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
+ * Stores the first 32 bits of KEY1.
+ */
+
+#define EFUSE_KEY1_DATA1 0xffffffff
+#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
+#define EFUSE_KEY1_DATA1_V 0xffffffff
+#define EFUSE_KEY1_DATA1_S 0
+
+/* EFUSE_RD_KEY1_DATA2_REG register
+ * Register 2 of BLOCK5 (KEY1).
+ */
+
+#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
+
+/* EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
+ * Stores the second 32 bits of KEY1.
+ */
+
+#define EFUSE_KEY1_DATA2 0xffffffff
+#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
+#define EFUSE_KEY1_DATA2_V 0xffffffff
+#define EFUSE_KEY1_DATA2_S 0
+
+/* EFUSE_RD_KEY1_DATA3_REG register
+ * Register 3 of BLOCK5 (KEY1).
+ */
+
+#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
+
+/* EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
+ * Stores the third 32 bits of KEY1.
+ */
+
+#define EFUSE_KEY1_DATA3 0xffffffff
+#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
+#define EFUSE_KEY1_DATA3_V 0xffffffff
+#define EFUSE_KEY1_DATA3_S 0
+
+/* EFUSE_RD_KEY1_DATA4_REG register
+ * Register 4 of BLOCK5 (KEY1).
+ */
+
+#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
+
+/* EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fourth 32 bits of KEY1.
+ */
+
+#define EFUSE_KEY1_DATA4 0xffffffff
+#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
+#define EFUSE_KEY1_DATA4_V 0xffffffff
+#define EFUSE_KEY1_DATA4_S 0
+
+/* EFUSE_RD_KEY1_DATA5_REG register
+ * Register 5 of BLOCK5 (KEY1).
+ */
+
+#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
+
+/* EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fifth 32 bits of KEY1.
+ */
+
+#define EFUSE_KEY1_DATA5 0xffffffff
+#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
+#define EFUSE_KEY1_DATA5_V 0xffffffff
+#define EFUSE_KEY1_DATA5_S 0
+
+/* EFUSE_RD_KEY1_DATA6_REG register
+ * Register 6 of BLOCK5 (KEY1).
+ */
+
+#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
+
+/* EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
+ * Stores the sixth 32 bits of KEY1.
+ */
+
+#define EFUSE_KEY1_DATA6 0xffffffff
+#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
+#define EFUSE_KEY1_DATA6_V 0xffffffff
+#define EFUSE_KEY1_DATA6_S 0
+
+/* EFUSE_RD_KEY1_DATA7_REG register
+ * Register 7 of BLOCK5 (KEY1).
+ */
+
+#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
+
+/* EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
+ * Stores the seventh 32 bits of KEY1.
+ */
+
+#define EFUSE_KEY1_DATA7 0xffffffff
+#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
+#define EFUSE_KEY1_DATA7_V 0xffffffff
+#define EFUSE_KEY1_DATA7_S 0
+
+/* EFUSE_RD_KEY2_DATA0_REG register
+ * Register 0 of BLOCK6 (KEY2).
+ */
+
+#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
+
+/* EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
+ * Stores the zeroth 32 bits of KEY2.
+ */
+
+#define EFUSE_KEY2_DATA0 0xffffffff
+#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
+#define EFUSE_KEY2_DATA0_V 0xffffffff
+#define EFUSE_KEY2_DATA0_S 0
+
+/* EFUSE_RD_KEY2_DATA1_REG register
+ * Register 1 of BLOCK6 (KEY2).
+ */
+
+#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
+
+/* EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
+ * Stores the first 32 bits of KEY2.
+ */
+
+#define EFUSE_KEY2_DATA1 0xffffffff
+#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
+#define EFUSE_KEY2_DATA1_V 0xffffffff
+#define EFUSE_KEY2_DATA1_S 0
+
+/* EFUSE_RD_KEY2_DATA2_REG register
+ * Register 2 of BLOCK6 (KEY2).
+ */
+
+#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
+
+/* EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
+ * Stores the second 32 bits of KEY2.
+ */
+
+#define EFUSE_KEY2_DATA2 0xffffffff
+#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
+#define EFUSE_KEY2_DATA2_V 0xffffffff
+#define EFUSE_KEY2_DATA2_S 0
+
+/* EFUSE_RD_KEY2_DATA3_REG register
+ * Register 3 of BLOCK6 (KEY2).
+ */
+
+#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
+
+/* EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
+ * Stores the third 32 bits of KEY2.
+ */
+
+#define EFUSE_KEY2_DATA3 0xffffffff
+#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
+#define EFUSE_KEY2_DATA3_V 0xffffffff
+#define EFUSE_KEY2_DATA3_S 0
+
+/* EFUSE_RD_KEY2_DATA4_REG register
+ * Register 4 of BLOCK6 (KEY2).
+ */
+
+#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
+
+/* EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fourth 32 bits of KEY2.
+ */
+
+#define EFUSE_KEY2_DATA4 0xffffffff
+#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
+#define EFUSE_KEY2_DATA4_V 0xffffffff
+#define EFUSE_KEY2_DATA4_S 0
+
+/* EFUSE_RD_KEY2_DATA5_REG register
+ * Register 5 of BLOCK6 (KEY2).
+ */
+
+#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
+
+/* EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fifth 32 bits of KEY2.
+ */
+
+#define EFUSE_KEY2_DATA5 0xffffffff
+#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
+#define EFUSE_KEY2_DATA5_V 0xffffffff
+#define EFUSE_KEY2_DATA5_S 0
+
+/* EFUSE_RD_KEY2_DATA6_REG register
+ * Register 6 of BLOCK6 (KEY2).
+ */
+
+#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
+
+/* EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
+ * Stores the sixth 32 bits of KEY2.
+ */
+
+#define EFUSE_KEY2_DATA6 0xffffffff
+#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
+#define EFUSE_KEY2_DATA6_V 0xffffffff
+#define EFUSE_KEY2_DATA6_S 0
+
+/* EFUSE_RD_KEY2_DATA7_REG register
+ * Register 7 of BLOCK6 (KEY2).
+ */
+
+#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
+
+/* EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
+ * Stores the seventh 32 bits of KEY2.
+ */
+
+#define EFUSE_KEY2_DATA7 0xffffffff
+#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
+#define EFUSE_KEY2_DATA7_V 0xffffffff
+#define EFUSE_KEY2_DATA7_S 0
+
+/* EFUSE_RD_KEY3_DATA0_REG register
+ * Register 0 of BLOCK7 (KEY3).
+ */
+
+#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
+
+/* EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
+ * Stores the zeroth 32 bits of KEY3.
+ */
+
+#define EFUSE_KEY3_DATA0 0xffffffff
+#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
+#define EFUSE_KEY3_DATA0_V 0xffffffff
+#define EFUSE_KEY3_DATA0_S 0
+
+/* EFUSE_RD_KEY3_DATA1_REG register
+ * Register 1 of BLOCK7 (KEY3).
+ */
+
+#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
+
+/* EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
+ * Stores the first 32 bits of KEY3.
+ */
+
+#define EFUSE_KEY3_DATA1 0xffffffff
+#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
+#define EFUSE_KEY3_DATA1_V 0xffffffff
+#define EFUSE_KEY3_DATA1_S 0
+
+/* EFUSE_RD_KEY3_DATA2_REG register
+ * Register 2 of BLOCK7 (KEY3).
+ */
+
+#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
+
+/* EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
+ * Stores the second 32 bits of KEY3.
+ */
+
+#define EFUSE_KEY3_DATA2 0xffffffff
+#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
+#define EFUSE_KEY3_DATA2_V 0xffffffff
+#define EFUSE_KEY3_DATA2_S 0
+
+/* EFUSE_RD_KEY3_DATA3_REG register
+ * Register 3 of BLOCK7 (KEY3).
+ */
+
+#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
+
+/* EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
+ * Stores the third 32 bits of KEY3.
+ */
+
+#define EFUSE_KEY3_DATA3 0xffffffff
+#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
+#define EFUSE_KEY3_DATA3_V 0xffffffff
+#define EFUSE_KEY3_DATA3_S 0
+
+/* EFUSE_RD_KEY3_DATA4_REG register
+ * Register 4 of BLOCK7 (KEY3).
+ */
+
+#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
+
+/* EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fourth 32 bits of KEY3.
+ */
+
+#define EFUSE_KEY3_DATA4 0xffffffff
+#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
+#define EFUSE_KEY3_DATA4_V 0xffffffff
+#define EFUSE_KEY3_DATA4_S 0
+
+/* EFUSE_RD_KEY3_DATA5_REG register
+ * Register 5 of BLOCK7 (KEY3).
+ */
+
+#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
+
+/* EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fifth 32 bits of KEY3.
+ */
+
+#define EFUSE_KEY3_DATA5 0xffffffff
+#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
+#define EFUSE_KEY3_DATA5_V 0xffffffff
+#define EFUSE_KEY3_DATA5_S 0
+
+/* EFUSE_RD_KEY3_DATA6_REG register
+ * Register 6 of BLOCK7 (KEY3).
+ */
+
+#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
+
+/* EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
+ * Stores the sixth 32 bits of KEY3.
+ */
+
+#define EFUSE_KEY3_DATA6 0xffffffff
+#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
+#define EFUSE_KEY3_DATA6_V 0xffffffff
+#define EFUSE_KEY3_DATA6_S 0
+
+/* EFUSE_RD_KEY3_DATA7_REG register
+ * Register 7 of BLOCK7 (KEY3).
+ */
+
+#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
+
+/* EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
+ * Stores the seventh 32 bits of KEY3.
+ */
+
+#define EFUSE_KEY3_DATA7 0xffffffff
+#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
+#define EFUSE_KEY3_DATA7_V 0xffffffff
+#define EFUSE_KEY3_DATA7_S 0
+
+/* EFUSE_RD_KEY4_DATA0_REG register
+ * Register 0 of BLOCK8 (KEY4).
+ */
+
+#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
+
+/* EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
+ * Stores the zeroth 32 bits of KEY4.
+ */
+
+#define EFUSE_KEY4_DATA0 0xffffffff
+#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
+#define EFUSE_KEY4_DATA0_V 0xffffffff
+#define EFUSE_KEY4_DATA0_S 0
+
+/* EFUSE_RD_KEY4_DATA1_REG register
+ * Register 1 of BLOCK8 (KEY4).
+ */
+
+#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
+
+/* EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
+ * Stores the first 32 bits of KEY4.
+ */
+
+#define EFUSE_KEY4_DATA1 0xffffffff
+#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
+#define EFUSE_KEY4_DATA1_V 0xffffffff
+#define EFUSE_KEY4_DATA1_S 0
+
+/* EFUSE_RD_KEY4_DATA2_REG register
+ * Register 2 of BLOCK8 (KEY4).
+ */
+
+#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
+
+/* EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
+ * Stores the second 32 bits of KEY4.
+ */
+
+#define EFUSE_KEY4_DATA2 0xffffffff
+#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
+#define EFUSE_KEY4_DATA2_V 0xffffffff
+#define EFUSE_KEY4_DATA2_S 0
+
+/* EFUSE_RD_KEY4_DATA3_REG register
+ * Register 3 of BLOCK8 (KEY4).
+ */
+
+#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
+
+/* EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
+ * Stores the third 32 bits of KEY4.
+ */
+
+#define EFUSE_KEY4_DATA3 0xffffffff
+#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
+#define EFUSE_KEY4_DATA3_V 0xffffffff
+#define EFUSE_KEY4_DATA3_S 0
+
+/* EFUSE_RD_KEY4_DATA4_REG register
+ * Register 4 of BLOCK8 (KEY4).
+ */
+
+#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
+
+/* EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fourth 32 bits of KEY4.
+ */
+
+#define EFUSE_KEY4_DATA4 0xffffffff
+#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
+#define EFUSE_KEY4_DATA4_V 0xffffffff
+#define EFUSE_KEY4_DATA4_S 0
+
+/* EFUSE_RD_KEY4_DATA5_REG register
+ * Register 5 of BLOCK8 (KEY4).
+ */
+
+#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
+
+/* EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fifth 32 bits of KEY4.
+ */
+
+#define EFUSE_KEY4_DATA5 0xffffffff
+#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
+#define EFUSE_KEY4_DATA5_V 0xffffffff
+#define EFUSE_KEY4_DATA5_S 0
+
+/* EFUSE_RD_KEY4_DATA6_REG register
+ * Register 6 of BLOCK8 (KEY4).
+ */
+
+#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
+
+/* EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
+ * Stores the sixth 32 bits of KEY4.
+ */
+
+#define EFUSE_KEY4_DATA6 0xffffffff
+#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
+#define EFUSE_KEY4_DATA6_V 0xffffffff
+#define EFUSE_KEY4_DATA6_S 0
+
+/* EFUSE_RD_KEY4_DATA7_REG register
+ * Register 7 of BLOCK8 (KEY4).
+ */
+
+#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
+
+/* EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
+ * Stores the seventh 32 bits of KEY4.
+ */
+
+#define EFUSE_KEY4_DATA7 0xffffffff
+#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
+#define EFUSE_KEY4_DATA7_V 0xffffffff
+#define EFUSE_KEY4_DATA7_S 0
+
+/* EFUSE_RD_KEY5_DATA0_REG register
+ * Register 0 of BLOCK9 (KEY5).
+ */
+
+#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
+
+/* EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
+ * Stores the zeroth 32 bits of KEY5.
+ */
+
+#define EFUSE_KEY5_DATA0 0xffffffff
+#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
+#define EFUSE_KEY5_DATA0_V 0xffffffff
+#define EFUSE_KEY5_DATA0_S 0
+
+/* EFUSE_RD_KEY5_DATA1_REG register
+ * Register 1 of BLOCK9 (KEY5).
+ */
+
+#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
+
+/* EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
+ * Stores the first 32 bits of KEY5.
+ */
+
+#define EFUSE_KEY5_DATA1 0xffffffff
+#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
+#define EFUSE_KEY5_DATA1_V 0xffffffff
+#define EFUSE_KEY5_DATA1_S 0
+
+/* EFUSE_RD_KEY5_DATA2_REG register
+ * Register 2 of BLOCK9 (KEY5).
+ */
+
+#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
+
+/* EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
+ * Stores the second 32 bits of KEY5.
+ */
+
+#define EFUSE_KEY5_DATA2 0xffffffff
+#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
+#define EFUSE_KEY5_DATA2_V 0xffffffff
+#define EFUSE_KEY5_DATA2_S 0
+
+/* EFUSE_RD_KEY5_DATA3_REG register
+ * Register 3 of BLOCK9 (KEY5).
+ */
+
+#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
+
+/* EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
+ * Stores the third 32 bits of KEY5.
+ */
+
+#define EFUSE_KEY5_DATA3 0xffffffff
+#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
+#define EFUSE_KEY5_DATA3_V 0xffffffff
+#define EFUSE_KEY5_DATA3_S 0
+
+/* EFUSE_RD_KEY5_DATA4_REG register
+ * Register 4 of BLOCK9 (KEY5).
+ */
+
+#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
+
+/* EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fourth 32 bits of KEY5.
+ */
+
+#define EFUSE_KEY5_DATA4 0xffffffff
+#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
+#define EFUSE_KEY5_DATA4_V 0xffffffff
+#define EFUSE_KEY5_DATA4_S 0
+
+/* EFUSE_RD_KEY5_DATA5_REG register
+ * Register 5 of BLOCK9 (KEY5).
+ */
+
+#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
+
+/* EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
+ * Stores the fifth 32 bits of KEY5.
+ */
+
+#define EFUSE_KEY5_DATA5 0xffffffff
+#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
+#define EFUSE_KEY5_DATA5_V 0xffffffff
+#define EFUSE_KEY5_DATA5_S 0
+
+/* EFUSE_RD_KEY5_DATA6_REG register
+ * Register 6 of BLOCK9 (KEY5).
+ */
+
+#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
+
+/* EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
+ * Stores the sixth 32 bits of KEY5.
+ */
+
+#define EFUSE_KEY5_DATA6 0xffffffff
+#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
+#define EFUSE_KEY5_DATA6_V 0xffffffff
+#define EFUSE_KEY5_DATA6_S 0
+
+/* EFUSE_RD_KEY5_DATA7_REG register
+ * Register 7 of BLOCK9 (KEY5).
+ */
+
+#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
+
+/* EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
+ * Stores the seventh 32 bits of KEY5.
+ */
+
+#define EFUSE_KEY5_DATA7 0xffffffff
+#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
+#define EFUSE_KEY5_DATA7_V 0xffffffff
+#define EFUSE_KEY5_DATA7_S 0
+
+/* EFUSE_RD_SYS_PART2_DATA0_REG register
+ * Register 0 of BLOCK10 (system).
+ */
+
+#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
+
+/* EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
+ * Stores the 0th 32 bits of the 2nd part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART2_0 0xffffffff
+#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
+#define EFUSE_SYS_DATA_PART2_0_V 0xffffffff
+#define EFUSE_SYS_DATA_PART2_0_S 0
+
+/* EFUSE_RD_SYS_PART2_DATA1_REG register
+ * Register 1 of BLOCK9 (KEY5).
+ */
+
+#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
+
+/* EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
+ * Stores the 1st 32 bits of the 2nd part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART2_1 0xffffffff
+#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
+#define EFUSE_SYS_DATA_PART2_1_V 0xffffffff
+#define EFUSE_SYS_DATA_PART2_1_S 0
+
+/* EFUSE_RD_SYS_PART2_DATA2_REG register
+ * Register 2 of BLOCK10 (system).
+ */
+
+#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
+
+/* EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
+ * Stores the 2nd 32 bits of the 2nd part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART2_2 0xffffffff
+#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
+#define EFUSE_SYS_DATA_PART2_2_V 0xffffffff
+#define EFUSE_SYS_DATA_PART2_2_S 0
+
+/* EFUSE_RD_SYS_PART2_DATA3_REG register
+ * Register 3 of BLOCK10 (system).
+ */
+
+#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
+
+/* EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
+ * Stores the 3rd 32 bits of the 2nd part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART2_3 0xffffffff
+#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
+#define EFUSE_SYS_DATA_PART2_3_V 0xffffffff
+#define EFUSE_SYS_DATA_PART2_3_S 0
+
+/* EFUSE_RD_SYS_PART2_DATA4_REG register
+ * Register 4 of BLOCK10 (system).
+ */
+
+#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
+
+/* EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
+ * Stores the 4th 32 bits of the 2nd part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART2_4 0xffffffff
+#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
+#define EFUSE_SYS_DATA_PART2_4_V 0xffffffff
+#define EFUSE_SYS_DATA_PART2_4_S 0
+
+/* EFUSE_RD_SYS_PART2_DATA5_REG register
+ * Register 5 of BLOCK10 (system).
+ */
+
+#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
+
+/* EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
+ * Stores the 5th 32 bits of the 2nd part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART2_5 0xffffffff
+#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
+#define EFUSE_SYS_DATA_PART2_5_V 0xffffffff
+#define EFUSE_SYS_DATA_PART2_5_S 0
+
+/* EFUSE_RD_SYS_PART2_DATA6_REG register
+ * Register 6 of BLOCK10 (system).
+ */
+
+#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
+
+/* EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
+ * Stores the 6th 32 bits of the 2nd part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART2_6 0xffffffff
+#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
+#define EFUSE_SYS_DATA_PART2_6_V 0xffffffff
+#define EFUSE_SYS_DATA_PART2_6_S 0
+
+/* EFUSE_RD_SYS_PART2_DATA7_REG register
+ * Register 7 of BLOCK10 (system).
+ */
+
+#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
+
+/* EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
+ * Stores the 7th 32 bits of the 2nd part of system data.
+ */
+
+#define EFUSE_SYS_DATA_PART2_7 0xffffffff
+#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
+#define EFUSE_SYS_DATA_PART2_7_V 0xffffffff
+#define EFUSE_SYS_DATA_PART2_7_S 0
+
+/* EFUSE_RD_REPEAT_ERR0_REG register
+ * Programming error record register 0 of BLOCK0.
+ */
+
+#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
+
+/* EFUSE_VDD_SPI_DREFH_ERR : RO; bitpos: [31:30]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003
+#define EFUSE_VDD_SPI_DREFH_ERR_M (EFUSE_VDD_SPI_DREFH_ERR_V << EFUSE_VDD_SPI_DREFH_ERR_S)
+#define EFUSE_VDD_SPI_DREFH_ERR_V 0x00000003
+#define EFUSE_VDD_SPI_DREFH_ERR_S 30
+
+/* EFUSE_VDD_SPI_MODECURLIM_ERR : RO; bitpos: [29]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29))
+#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (EFUSE_VDD_SPI_MODECURLIM_ERR_V << EFUSE_VDD_SPI_MODECURLIM_ERR_S)
+#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x00000001
+#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29
+
+/* EFUSE_BTLC_GPIO_ENABLE_ERR : RO; bitpos: [28:27]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_M (EFUSE_BTLC_GPIO_ENABLE_ERR_V << EFUSE_BTLC_GPIO_ENABLE_ERR_S)
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_V 0x00000003
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_S 27
+
+/* EFUSE_EXT_PHY_ENABLE_ERR : RO; bitpos: [26]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(26))
+#define EFUSE_EXT_PHY_ENABLE_ERR_M (EFUSE_EXT_PHY_ENABLE_ERR_V << EFUSE_EXT_PHY_ENABLE_ERR_S)
+#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x00000001
+#define EFUSE_EXT_PHY_ENABLE_ERR_S 26
+
+/* EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S)
+#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001
+#define EFUSE_USB_EXCHG_PINS_ERR_S 25
+
+/* EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_USB_DREFL_ERR 0x00000003
+#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S)
+#define EFUSE_USB_DREFL_ERR_V 0x00000003
+#define EFUSE_USB_DREFL_ERR_S 23
+
+/* EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_USB_DREFH_ERR 0x00000003
+#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S)
+#define EFUSE_USB_DREFH_ERR_V 0x00000003
+#define EFUSE_USB_DREFH_ERR_S 21
+
+/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20
+
+/* EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
+#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001
+#define EFUSE_DIS_PAD_JTAG_ERR_S 19
+
+/* EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007
+#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
+#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007
+#define EFUSE_SOFT_DIS_JTAG_ERR_S 16
+
+/* EFUSE_DIS_APP_CPU_ERR : RO; bitpos: [15]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_APP_CPU_ERR (BIT(15))
+#define EFUSE_DIS_APP_CPU_ERR_M (EFUSE_DIS_APP_CPU_ERR_V << EFUSE_DIS_APP_CPU_ERR_S)
+#define EFUSE_DIS_APP_CPU_ERR_V 0x00000001
+#define EFUSE_DIS_APP_CPU_ERR_S 15
+
+/* EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_CAN_ERR (BIT(14))
+#define EFUSE_DIS_CAN_ERR_M (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S)
+#define EFUSE_DIS_CAN_ERR_V 0x00000001
+#define EFUSE_DIS_CAN_ERR_S 14
+
+/* EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_USB_ERR (BIT(13))
+#define EFUSE_DIS_USB_ERR_M (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S)
+#define EFUSE_DIS_USB_ERR_V 0x00000001
+#define EFUSE_DIS_USB_ERR_S 13
+
+/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12
+
+/* EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO; bitpos: [11]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11))
+#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V << EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x00000001
+#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11
+
+/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10
+
+/* EFUSE_DIS_DCACHE_ERR : RO; bitpos: [9]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_DCACHE_ERR (BIT(9))
+#define EFUSE_DIS_DCACHE_ERR_M (EFUSE_DIS_DCACHE_ERR_V << EFUSE_DIS_DCACHE_ERR_S)
+#define EFUSE_DIS_DCACHE_ERR_V 0x00000001
+#define EFUSE_DIS_DCACHE_ERR_S 9
+
+/* EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_ICACHE_ERR (BIT(8))
+#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S)
+#define EFUSE_DIS_ICACHE_ERR_V 0x00000001
+#define EFUSE_DIS_ICACHE_ERR_S 8
+
+/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S)
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x00000001
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7
+
+/* EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_RD_DIS_ERR 0x0000007f
+#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
+#define EFUSE_RD_DIS_ERR_V 0x0000007f
+#define EFUSE_RD_DIS_ERR_S 0
+
+/* EFUSE_RD_REPEAT_ERR1_REG register
+ * Programming error record register 1 of BLOCK0.
+ */
+
+#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
+
+/* EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000f
+#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
+#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000f
+#define EFUSE_KEY_PURPOSE_1_ERR_S 28
+
+/* EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000f
+#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
+#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000f
+#define EFUSE_KEY_PURPOSE_0_ERR_S 24
+
+/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23
+
+/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22
+
+/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21
+
+/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18
+
+/* EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003
+#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
+#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003
+#define EFUSE_WDT_DELAY_SEL_ERR_S 16
+
+/* EFUSE_VDD_SPI_DCAP_ERR : RO; bitpos: [15:14]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003
+#define EFUSE_VDD_SPI_DCAP_ERR_M (EFUSE_VDD_SPI_DCAP_ERR_V << EFUSE_VDD_SPI_DCAP_ERR_S)
+#define EFUSE_VDD_SPI_DCAP_ERR_V 0x00000003
+#define EFUSE_VDD_SPI_DCAP_ERR_S 14
+
+/* EFUSE_VDD_SPI_INIT_ERR : RO; bitpos: [13:12]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_VDD_SPI_INIT_ERR 0x00000003
+#define EFUSE_VDD_SPI_INIT_ERR_M (EFUSE_VDD_SPI_INIT_ERR_V << EFUSE_VDD_SPI_INIT_ERR_S)
+#define EFUSE_VDD_SPI_INIT_ERR_V 0x00000003
+#define EFUSE_VDD_SPI_INIT_ERR_S 12
+
+/* EFUSE_VDD_SPI_DCURLIM_ERR : RO; bitpos: [11:9]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007
+#define EFUSE_VDD_SPI_DCURLIM_ERR_M (EFUSE_VDD_SPI_DCURLIM_ERR_V << EFUSE_VDD_SPI_DCURLIM_ERR_S)
+#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x00000007
+#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9
+
+/* EFUSE_VDD_SPI_ENCURLIM_ERR : RO; bitpos: [8]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8))
+#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (EFUSE_VDD_SPI_ENCURLIM_ERR_V << EFUSE_VDD_SPI_ENCURLIM_ERR_S)
+#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x00000001
+#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8
+
+/* EFUSE_VDD_SPI_EN_INIT_ERR : RO; bitpos: [7]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7))
+#define EFUSE_VDD_SPI_EN_INIT_ERR_M (EFUSE_VDD_SPI_EN_INIT_ERR_V << EFUSE_VDD_SPI_EN_INIT_ERR_S)
+#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x00000001
+#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7
+
+/* EFUSE_VDD_SPI_FORCE_ERR : RO; bitpos: [6]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6))
+#define EFUSE_VDD_SPI_FORCE_ERR_M (EFUSE_VDD_SPI_FORCE_ERR_V << EFUSE_VDD_SPI_FORCE_ERR_S)
+#define EFUSE_VDD_SPI_FORCE_ERR_V 0x00000001
+#define EFUSE_VDD_SPI_FORCE_ERR_S 6
+
+/* EFUSE_VDD_SPI_TIEH_ERR : RO; bitpos: [5]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5))
+#define EFUSE_VDD_SPI_TIEH_ERR_M (EFUSE_VDD_SPI_TIEH_ERR_V << EFUSE_VDD_SPI_TIEH_ERR_S)
+#define EFUSE_VDD_SPI_TIEH_ERR_V 0x00000001
+#define EFUSE_VDD_SPI_TIEH_ERR_S 5
+
+/* EFUSE_VDD_SPI_XPD_ERR : RO; bitpos: [4]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_VDD_SPI_XPD_ERR (BIT(4))
+#define EFUSE_VDD_SPI_XPD_ERR_M (EFUSE_VDD_SPI_XPD_ERR_V << EFUSE_VDD_SPI_XPD_ERR_S)
+#define EFUSE_VDD_SPI_XPD_ERR_V 0x00000001
+#define EFUSE_VDD_SPI_XPD_ERR_S 4
+
+/* EFUSE_VDD_SPI_DREFL_ERR : RO; bitpos: [3:2]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003
+#define EFUSE_VDD_SPI_DREFL_ERR_M (EFUSE_VDD_SPI_DREFL_ERR_V << EFUSE_VDD_SPI_DREFL_ERR_S)
+#define EFUSE_VDD_SPI_DREFL_ERR_V 0x00000003
+#define EFUSE_VDD_SPI_DREFL_ERR_S 2
+
+/* EFUSE_VDD_SPI_DREFM_ERR : RO; bitpos: [1:0]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003
+#define EFUSE_VDD_SPI_DREFM_ERR_M (EFUSE_VDD_SPI_DREFM_ERR_V << EFUSE_VDD_SPI_DREFM_ERR_S)
+#define EFUSE_VDD_SPI_DREFM_ERR_V 0x00000003
+#define EFUSE_VDD_SPI_DREFM_ERR_S 0
+
+/* EFUSE_RD_REPEAT_ERR2_REG register
+ * Programming error record register 2 of BLOCK0.
+ */
+
+#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
+
+/* EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_FLASH_TPUW_ERR 0x0000000f
+#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
+#define EFUSE_FLASH_TPUW_ERR_V 0x0000000f
+#define EFUSE_FLASH_TPUW_ERR_S 28
+
+/* EFUSE_POWER_GLITCH_DSENSE_ERR : RO; bitpos: [27:26]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_POWER_GLITCH_DSENSE_ERR 0x00000003
+#define EFUSE_POWER_GLITCH_DSENSE_ERR_M (EFUSE_POWER_GLITCH_DSENSE_ERR_V << EFUSE_POWER_GLITCH_DSENSE_ERR_S)
+#define EFUSE_POWER_GLITCH_DSENSE_ERR_V 0x00000003
+#define EFUSE_POWER_GLITCH_DSENSE_ERR_S 26
+
+/* EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_USB_PHY_SEL_ERR (BIT(25))
+#define EFUSE_USB_PHY_SEL_ERR_M (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S)
+#define EFUSE_USB_PHY_SEL_ERR_V 0x00000001
+#define EFUSE_USB_PHY_SEL_ERR_S 25
+
+/* EFUSE_STRAP_JTAG_SEL_ERR : RO; bitpos: [24]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_STRAP_JTAG_SEL_ERR (BIT(24))
+#define EFUSE_STRAP_JTAG_SEL_ERR_M (EFUSE_STRAP_JTAG_SEL_ERR_V << EFUSE_STRAP_JTAG_SEL_ERR_S)
+#define EFUSE_STRAP_JTAG_SEL_ERR_V 0x00000001
+#define EFUSE_STRAP_JTAG_SEL_ERR_S 24
+
+/* EFUSE_DIS_USB_DEVICE_ERR : RO; bitpos: [23]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_USB_DEVICE_ERR (BIT(23))
+#define EFUSE_DIS_USB_DEVICE_ERR_M (EFUSE_DIS_USB_DEVICE_ERR_V << EFUSE_DIS_USB_DEVICE_ERR_S)
+#define EFUSE_DIS_USB_DEVICE_ERR_V 0x00000001
+#define EFUSE_DIS_USB_DEVICE_ERR_S 23
+
+/* EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [22]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_USB_JTAG_ERR (BIT(22))
+#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
+#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001
+#define EFUSE_DIS_USB_JTAG_ERR_S 22
+
+/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21
+
+/* EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001
+#define EFUSE_SECURE_BOOT_EN_ERR_S 20
+
+/* EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [19:16]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_RPT4_RESERVED0_ERR 0x0000000f
+#define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S)
+#define EFUSE_RPT4_RESERVED0_ERR_V 0x0000000f
+#define EFUSE_RPT4_RESERVED0_ERR_S 16
+
+/* EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000f
+#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
+#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000f
+#define EFUSE_KEY_PURPOSE_5_ERR_S 12
+
+/* EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000f
+#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
+#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000f
+#define EFUSE_KEY_PURPOSE_4_ERR_S 8
+
+/* EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000f
+#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
+#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000f
+#define EFUSE_KEY_PURPOSE_3_ERR_S 4
+
+/* EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000f
+#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
+#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000f
+#define EFUSE_KEY_PURPOSE_2_ERR_S 0
+
+/* EFUSE_RD_REPEAT_ERR3_REG register
+ * Programming error record register 3 of BLOCK0.
+ */
+
+#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
+
+/* EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [31]; default: 0;
+ * Reserved.
+ */
+
+#define EFUSE_RPT4_RESERVED1_ERR (BIT(31))
+#define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S)
+#define EFUSE_RPT4_RESERVED1_ERR_V 0x00000001
+#define EFUSE_RPT4_RESERVED1_ERR_S 31
+
+/* EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [30]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_POWERGLITCH_EN_ERR (BIT(30))
+#define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
+#define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001
+#define EFUSE_POWERGLITCH_EN_ERR_S 30
+
+/* EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_SECURE_VERSION_ERR 0x0000ffff
+#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
+#define EFUSE_SECURE_VERSION_ERR_V 0x0000ffff
+#define EFUSE_SECURE_VERSION_ERR_S 14
+
+/* EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
+#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001
+#define EFUSE_FORCE_SEND_RESUME_ERR_S 13
+
+/* EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [12]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_FLASH_ECC_EN_ERR (BIT(12))
+#define EFUSE_FLASH_ECC_EN_ERR_M (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S)
+#define EFUSE_FLASH_ECC_EN_ERR_V 0x00000001
+#define EFUSE_FLASH_ECC_EN_ERR_S 12
+
+/* EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [11:10]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_FLASH_PAGE_SIZE_ERR 0x00000003
+#define EFUSE_FLASH_PAGE_SIZE_ERR_M (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S)
+#define EFUSE_FLASH_PAGE_SIZE_ERR_V 0x00000003
+#define EFUSE_FLASH_PAGE_SIZE_ERR_S 10
+
+/* EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_FLASH_TYPE_ERR (BIT(9))
+#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S)
+#define EFUSE_FLASH_TYPE_ERR_V 0x00000001
+#define EFUSE_FLASH_TYPE_ERR_S 9
+
+/* EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_ERR_M (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S)
+#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x00000001
+#define EFUSE_PIN_POWER_SELECTION_ERR_S 8
+
+/* EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003
+#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
+#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003
+#define EFUSE_UART_PRINT_CONTROL_ERR_S 6
+
+/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5
+
+/* EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x00000001
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4
+
+/* EFUSE_FLASH_ECC_MODE_ERR : RO; bitpos: [3]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_FLASH_ECC_MODE_ERR (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_ERR_M (EFUSE_FLASH_ECC_MODE_ERR_V << EFUSE_FLASH_ECC_MODE_ERR_S)
+#define EFUSE_FLASH_ECC_MODE_ERR_V 0x00000001
+#define EFUSE_FLASH_ECC_MODE_ERR_S 3
+
+/* EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_ERR_M (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S)
+#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x00000001
+#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2
+
+/* EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S)
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x00000001
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1
+
+/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0
+
+/* EFUSE_RD_REPEAT_ERR4_REG register
+ * Programming error record register 4 of BLOCK0.
+ */
+
+#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190)
+
+/* EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [23:0]; default: 0;
+ * If any bits in this filed are 1, then it indicates a programming error.
+ */
+
+#define EFUSE_RPT4_RESERVED2_ERR 0x00ffffff
+#define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S)
+#define EFUSE_RPT4_RESERVED2_ERR_V 0x00ffffff
+#define EFUSE_RPT4_RESERVED2_ERR_S 0
+
+/* EFUSE_RD_RS_ERR0_REG register
+ * Programming error record register 0 of BLOCK1-10.
+ */
+
+#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
+
+/* EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0;
+ * 0: Means no failure and that the data of key4 is reliable 1: Means that
+ * programming key4 failed and the number of error bytes is over 6.
+ */
+
+#define EFUSE_KEY4_FAIL (BIT(31))
+#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
+#define EFUSE_KEY4_FAIL_V 0x00000001
+#define EFUSE_KEY4_FAIL_S 31
+
+/* EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
+ * The value of this signal means the number of error bytes.
+ */
+
+#define EFUSE_KEY4_ERR_NUM 0x00000007
+#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
+#define EFUSE_KEY4_ERR_NUM_V 0x00000007
+#define EFUSE_KEY4_ERR_NUM_S 28
+
+/* EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0;
+ * 0: Means no failure and that the data of key3 is reliable 1: Means that
+ * programming key3 failed and the number of error bytes is over 6.
+ */
+
+#define EFUSE_KEY3_FAIL (BIT(27))
+#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
+#define EFUSE_KEY3_FAIL_V 0x00000001
+#define EFUSE_KEY3_FAIL_S 27
+
+/* EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
+ * The value of this signal means the number of error bytes.
+ */
+
+#define EFUSE_KEY3_ERR_NUM 0x00000007
+#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
+#define EFUSE_KEY3_ERR_NUM_V 0x00000007
+#define EFUSE_KEY3_ERR_NUM_S 24
+
+/* EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0;
+ * 0: Means no failure and that the data of key2 is reliable 1: Means that
+ * programming key2 failed and the number of error bytes is over 6.
+ */
+
+#define EFUSE_KEY2_FAIL (BIT(23))
+#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
+#define EFUSE_KEY2_FAIL_V 0x00000001
+#define EFUSE_KEY2_FAIL_S 23
+
+/* EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
+ * The value of this signal means the number of error bytes.
+ */
+
+#define EFUSE_KEY2_ERR_NUM 0x00000007
+#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
+#define EFUSE_KEY2_ERR_NUM_V 0x00000007
+#define EFUSE_KEY2_ERR_NUM_S 20
+
+/* EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0;
+ * 0: Means no failure and that the data of key1 is reliable 1: Means that
+ * programming key1 failed and the number of error bytes is over 6.
+ */
+
+#define EFUSE_KEY1_FAIL (BIT(19))
+#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
+#define EFUSE_KEY1_FAIL_V 0x00000001
+#define EFUSE_KEY1_FAIL_S 19
+
+/* EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
+ * The value of this signal means the number of error bytes.
+ */
+
+#define EFUSE_KEY1_ERR_NUM 0x00000007
+#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
+#define EFUSE_KEY1_ERR_NUM_V 0x00000007
+#define EFUSE_KEY1_ERR_NUM_S 16
+
+/* EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0;
+ * 0: Means no failure and that the data of key0 is reliable 1: Means that
+ * programming key0 failed and the number of error bytes is over 6.
+ */
+
+#define EFUSE_KEY0_FAIL (BIT(15))
+#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
+#define EFUSE_KEY0_FAIL_V 0x00000001
+#define EFUSE_KEY0_FAIL_S 15
+
+/* EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
+ * The value of this signal means the number of error bytes.
+ */
+
+#define EFUSE_KEY0_ERR_NUM 0x00000007
+#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
+#define EFUSE_KEY0_ERR_NUM_V 0x00000007
+#define EFUSE_KEY0_ERR_NUM_S 12
+
+/* EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
+ * 0: Means no failure and that the user data is reliable 1: Means that
+ * programming user data failed and the number of error bytes is over 6.
+ */
+
+#define EFUSE_USR_DATA_FAIL (BIT(11))
+#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
+#define EFUSE_USR_DATA_FAIL_V 0x00000001
+#define EFUSE_USR_DATA_FAIL_S 11
+
+/* EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
+ * The value of this signal means the number of error bytes.
+ */
+
+#define EFUSE_USR_DATA_ERR_NUM 0x00000007
+#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
+#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007
+#define EFUSE_USR_DATA_ERR_NUM_S 8
+
+/* EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0;
+ * 0: Means no failure and that the data of system part1 is reliable 1:
+ * Means that programming user data failed and the number of error bytes is
+ * over 6.
+ */
+
+#define EFUSE_SYS_PART1_FAIL (BIT(7))
+#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
+#define EFUSE_SYS_PART1_FAIL_V 0x00000001
+#define EFUSE_SYS_PART1_FAIL_S 7
+
+/* EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0;
+ * The value of this signal means the number of error bytes.
+ */
+
+#define EFUSE_SYS_PART1_NUM 0x00000007
+#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S)
+#define EFUSE_SYS_PART1_NUM_V 0x00000007
+#define EFUSE_SYS_PART1_NUM_S 4
+
+/* EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0;
+ * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means
+ * that programming user data failed and the number of error bytes is over 6.
+ */
+
+#define EFUSE_MAC_SPI_8M_FAIL (BIT(3))
+#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S)
+#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001
+#define EFUSE_MAC_SPI_8M_FAIL_S 3
+
+/* EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ * The value of this signal means the number of error bytes.
+ */
+
+#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007
+#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S)
+#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007
+#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0
+
+/* EFUSE_RD_RS_ERR1_REG register
+ * Programming error record register 1 of BLOCK1-10.
+ */
+
+#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
+
+/* EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0;
+ * 0: Means no failure and that the data of system part2 is reliable 1:
+ * Means that programming user data failed and the number of error bytes is
+ * over 6.
+ */
+
+#define EFUSE_SYS_PART2_FAIL (BIT(7))
+#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S)
+#define EFUSE_SYS_PART2_FAIL_V 0x00000001
+#define EFUSE_SYS_PART2_FAIL_S 7
+
+/* EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ * The value of this signal means the number of error bytes.
+ */
+
+#define EFUSE_SYS_PART2_ERR_NUM 0x00000007
+#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
+#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007
+#define EFUSE_SYS_PART2_ERR_NUM_S 4
+
+/* EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0;
+ * 0: Means no failure and that the data of KEY5 is reliable 1: Means that
+ * programming user data failed and the number of error bytes is over 6.
+ */
+
+#define EFUSE_KEY5_FAIL (BIT(3))
+#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
+#define EFUSE_KEY5_FAIL_V 0x00000001
+#define EFUSE_KEY5_FAIL_S 3
+
+/* EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ * The value of this signal means the number of error bytes.
+ */
+
+#define EFUSE_KEY5_ERR_NUM 0x00000007
+#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
+#define EFUSE_KEY5_ERR_NUM_V 0x00000007
+#define EFUSE_KEY5_ERR_NUM_S 0
+
+/* EFUSE_CLK_REG register
+ * eFuse clcok configuration register.
+ */
+
+#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
+
+/* EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
+ * Set this bit and force to enable clock signal of eFuse memory.
+ */
+
+#define EFUSE_CLK_EN (BIT(16))
+#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
+#define EFUSE_CLK_EN_V 0x00000001
+#define EFUSE_CLK_EN_S 16
+
+/* EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
+ * Set this bit to force eFuse SRAM into working mode.
+ */
+
+#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2))
+#define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S)
+#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001
+#define EFUSE_EFUSE_MEM_FORCE_PU_S 2
+
+/* EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
+ * Set this bit and force to activate clock signal of eFuse SRAM.
+ */
+
+#define EFUSE_MEM_CLK_FORCE_ON (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
+#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001
+#define EFUSE_MEM_CLK_FORCE_ON_S 1
+
+/* EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ * Set this bit to force eFuse SRAM into power-saving mode.
+ */
+
+#define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0))
+#define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S)
+#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001
+#define EFUSE_EFUSE_MEM_FORCE_PD_S 0
+
+/* EFUSE_CONF_REG register
+ * eFuse operation mode configuraiton register
+ */
+
+#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
+
+/* EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
+ * 0x5A5A: Operate programming command 0x5AA5: Operate read command.
+ */
+
+#define EFUSE_OP_CODE 0x0000ffff
+#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
+#define EFUSE_OP_CODE_V 0x0000ffff
+#define EFUSE_OP_CODE_S 0
+
+/* EFUSE_STATUS_REG register
+ * eFuse status register.
+ */
+
+#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
+
+/* EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0;
+ * Indicates the number of error bits during programming BLOCK0.
+ */
+
+#define EFUSE_REPEAT_ERR_CNT 0x000000ff
+#define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S)
+#define EFUSE_REPEAT_ERR_CNT_V 0x000000ff
+#define EFUSE_REPEAT_ERR_CNT_S 10
+
+/* EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
+ * The value of OTP_VDDQ_IS_SW.
+ */
+
+#define EFUSE_OTP_VDDQ_IS_SW (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
+#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001
+#define EFUSE_OTP_VDDQ_IS_SW_S 9
+
+/* EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
+ * The value of OTP_PGENB_SW.
+ */
+
+#define EFUSE_OTP_PGENB_SW (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
+#define EFUSE_OTP_PGENB_SW_V 0x00000001
+#define EFUSE_OTP_PGENB_SW_S 8
+
+/* EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
+ * The value of OTP_CSB_SW.
+ */
+
+#define EFUSE_OTP_CSB_SW (BIT(7))
+#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
+#define EFUSE_OTP_CSB_SW_V 0x00000001
+#define EFUSE_OTP_CSB_SW_S 7
+
+/* EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
+ * The value of OTP_STROBE_SW.
+ */
+
+#define EFUSE_OTP_STROBE_SW (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
+#define EFUSE_OTP_STROBE_SW_V 0x00000001
+#define EFUSE_OTP_STROBE_SW_S 6
+
+/* EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
+ * The value of OTP_VDDQ_C_SYNC2.
+ */
+
+#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
+#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001
+#define EFUSE_OTP_VDDQ_C_SYNC2_S 5
+
+/* EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
+ * The value of OTP_LOAD_SW.
+ */
+
+#define EFUSE_OTP_LOAD_SW (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
+#define EFUSE_OTP_LOAD_SW_V 0x00000001
+#define EFUSE_OTP_LOAD_SW_S 4
+
+/* EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
+ * Indicates the state of the eFuse state machine.
+ */
+
+#define EFUSE_STATE 0x0000000f
+#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S)
+#define EFUSE_STATE_V 0x0000000f
+#define EFUSE_STATE_S 0
+
+/* EFUSE_CMD_REG register
+ * eFuse command register.
+ */
+
+#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
+
+/* EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
+ * The serial number of the block to be programmed. Value 0-10 corresponds
+ * to block number 0-10, respectively.
+ */
+
+#define EFUSE_BLK_NUM 0x0000000f
+#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
+#define EFUSE_BLK_NUM_V 0x0000000f
+#define EFUSE_BLK_NUM_S 2
+
+/* EFUSE_PGM_CMD : R/WS/SC; bitpos: [1]; default: 0;
+ * Set this bit to send programming command.
+ */
+
+#define EFUSE_PGM_CMD (BIT(1))
+#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
+#define EFUSE_PGM_CMD_V 0x00000001
+#define EFUSE_PGM_CMD_S 1
+
+/* EFUSE_READ_CMD : R/WS/SC; bitpos: [0]; default: 0;
+ * Set this bit to send read command.
+ */
+
+#define EFUSE_READ_CMD (BIT(0))
+#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
+#define EFUSE_READ_CMD_V 0x00000001
+#define EFUSE_READ_CMD_S 0
+
+/* EFUSE_INT_RAW_REG register
+ * eFuse raw interrupt register.
+ */
+
+#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
+
+/* EFUSE_PGM_DONE_INT_RAW : R/WC/SS; bitpos: [1]; default: 0;
+ * The raw bit signal for pgm_done interrupt.
+ */
+
+#define EFUSE_PGM_DONE_INT_RAW (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
+#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001
+#define EFUSE_PGM_DONE_INT_RAW_S 1
+
+/* EFUSE_READ_DONE_INT_RAW : R/WC/SS; bitpos: [0]; default: 0;
+ * The raw bit signal for read_done interrupt.
+ */
+
+#define EFUSE_READ_DONE_INT_RAW (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
+#define EFUSE_READ_DONE_INT_RAW_V 0x00000001
+#define EFUSE_READ_DONE_INT_RAW_S 0
+
+/* EFUSE_INT_ST_REG register
+ * eFuse interrupt status register.
+ */
+
+#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
+
+/* EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ * The status signal for pgm_done interrupt.
+ */
+
+#define EFUSE_PGM_DONE_INT_ST (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
+#define EFUSE_PGM_DONE_INT_ST_V 0x00000001
+#define EFUSE_PGM_DONE_INT_ST_S 1
+
+/* EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ * The status signal for read_done interrupt.
+ */
+
+#define EFUSE_READ_DONE_INT_ST (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
+#define EFUSE_READ_DONE_INT_ST_V 0x00000001
+#define EFUSE_READ_DONE_INT_ST_S 0
+
+/* EFUSE_INT_ENA_REG register
+ * eFuse interrupt enable register.
+ */
+
+#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
+
+/* EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ * The enable signal for pgm_done interrupt.
+ */
+
+#define EFUSE_PGM_DONE_INT_ENA (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
+#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001
+#define EFUSE_PGM_DONE_INT_ENA_S 1
+
+/* EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ * The enable signal for read_done interrupt.
+ */
+
+#define EFUSE_READ_DONE_INT_ENA (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
+#define EFUSE_READ_DONE_INT_ENA_V 0x00000001
+#define EFUSE_READ_DONE_INT_ENA_S 0
+
+/* EFUSE_INT_CLR_REG register
+ * eFuse interrupt clear register.
+ */
+
+#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
+
+/* EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0;
+ * The clear signal for pgm_done interrupt.
+ */
+
+#define EFUSE_PGM_DONE_INT_CLR (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
+#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001
+#define EFUSE_PGM_DONE_INT_CLR_S 1
+
+/* EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0;
+ * The clear signal for read_done interrupt.
+ */
+
+#define EFUSE_READ_DONE_INT_CLR (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
+#define EFUSE_READ_DONE_INT_CLR_V 0x00000001
+#define EFUSE_READ_DONE_INT_CLR_S 0
+
+/* EFUSE_DAC_CONF_REG register
+ * Controls the eFuse programming voltage.
+ */
+
+#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
+
+/* EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
+ * Reduces the power supply of the programming voltage.
+ */
+
+#define EFUSE_OE_CLR (BIT(17))
+#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
+#define EFUSE_OE_CLR_V 0x00000001
+#define EFUSE_OE_CLR_S 17
+
+/* EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
+ * Controls the rising period of the programming voltage.
+ */
+
+#define EFUSE_DAC_NUM 0x000000ff
+#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
+#define EFUSE_DAC_NUM_V 0x000000ff
+#define EFUSE_DAC_NUM_S 9
+
+/* EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
+ * Don't care.
+ */
+
+#define EFUSE_DAC_CLK_PAD_SEL (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
+#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001
+#define EFUSE_DAC_CLK_PAD_SEL_S 8
+
+/* EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28;
+ * Controls the division factor of the rising clock of the programming
+ * voltage.
+ */
+
+#define EFUSE_DAC_CLK_DIV 0x000000ff
+#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
+#define EFUSE_DAC_CLK_DIV_V 0x000000ff
+#define EFUSE_DAC_CLK_DIV_S 0
+
+/* EFUSE_RD_TIM_CONF_REG register
+ * Configures read timing parameters.
+ */
+
+#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
+
+/* EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18;
+ * Configures the initial read time of eFuse.
+ */
+
+#define EFUSE_READ_INIT_NUM 0x000000ff
+#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
+#define EFUSE_READ_INIT_NUM_V 0x000000ff
+#define EFUSE_READ_INIT_NUM_S 24
+
+/* EFUSE_WR_TIM_CONF1_REG register
+ * Configurarion register 1 of eFuse programming timing parameters.
+ */
+
+#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4)
+
+/* EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368;
+ * Configures the power up time for VDDQ.
+ */
+
+#define EFUSE_PWR_ON_NUM 0x0000ffff
+#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
+#define EFUSE_PWR_ON_NUM_V 0x0000ffff
+#define EFUSE_PWR_ON_NUM_S 8
+
+/* EFUSE_WR_TIM_CONF2_REG register
+ * Configurarion register 2 of eFuse programming timing parameters.
+ */
+
+#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8)
+
+/* EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400;
+ * Configures the power outage time for VDDQ.
+ */
+
+#define EFUSE_PWR_OFF_NUM 0x0000ffff
+#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
+#define EFUSE_PWR_OFF_NUM_V 0x0000ffff
+#define EFUSE_PWR_OFF_NUM_S 0
+
+/* EFUSE_DATE_REG register
+ * eFuse version register.
+ */
+
+#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
+
+/* EFUSE_DATE : R/W; bitpos: [27:0]; default: 34607760;
+ * Stores eFuse version.
+ */
+
+#define EFUSE_DATE 0x0fffffff
+#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S)
+#define EFUSE_DATE_V 0x0fffffff
+#define EFUSE_DATE_S 0
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EFUSE_H */
diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h
index de022c8..9b61615 100644
--- a/arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h
+++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h
@@ -31,12 +31,49 @@
* Pre-processor Definitions
****************************************************************************/
+/* Offset relative to each watchdog timer instance memory base */
+
+#define RWDT_CONFIG0_OFFSET 0x0090
+
+/* RWDT */
+
+#define RWDT_STAGE0_TIMEOUT_OFFSET 0x0094
+#define RWDT_STAGE1_TIMEOUT_OFFSET 0x0098
+#define RWDT_STAGE2_TIMEOUT_OFFSET 0x009c
+#define RWDT_STAGE3_TIMEOUT_OFFSET 0x00a0
+#define RWDT_FEED_OFFSET 0x00a4
+#define RWDT_WP_REG 0x00a8
+#define RWDT_INT_ENA_REG_OFFSET 0x0040
+#define RWDT_INT_CLR_REG_OFFSET 0x004c
+
/* The value that needs to be written to RTC_CNTL_WDT_WKEY to
* write-enable the wdt registers
*/
#define RTC_CNTL_WDT_WKEY_VALUE 0x50d83aa1
+/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG
+ * to write-enable the wdt registers
+ */
+
+#define RTC_CNTL_SWD_WKEY_VALUE 0x8f1d312a
+
+/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH
+ * and RTC_CNTL_WDT_SYS_RESET_LENGTH
+ */
+
+#define RTC_WDT_RESET_LENGTH_100_NS 0
+#define RTC_WDT_RESET_LENGTH_200_NS 1
+#define RTC_WDT_RESET_LENGTH_300_NS 2
+#define RTC_WDT_RESET_LENGTH_400_NS 3
+#define RTC_WDT_RESET_LENGTH_500_NS 4
+#define RTC_WDT_RESET_LENGTH_800_NS 5
+#define RTC_WDT_RESET_LENGTH_1600_NS 6
+#define RTC_WDT_RESET_LENGTH_3200_NS 7
+
+#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG
+#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG
+
/* RTC_CNTL_RTC_OPTIONS0_REG register
* RTC common configure register
*/