[incubator-nuttx] 01/02: xtensa/esp32: Fix RTC watchdog timer deinit at startup

[ac...@apache.org]

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commit 8c70e4f1c1cd6c115d1fe6b58c1f905a92f538b3
Author: Gustavo Henrique Nihei <gu...@espressif.com>
AuthorDate: Thu Jun 24 14:32:03 2021 -0300

    xtensa/esp32: Fix RTC watchdog timer deinit at startup
    
    Write protection must be disabled before performing changes to the WDT
    registers. Furthermore, the routine was resetting the wrong field from
    the RTC WDT register.
    The RTC_CNTL_WDT_FLASHBOOT_MOD_EN field relates to Flash Boot Protection
    and it is enabled by the 1st stage bootloader. The 2nd stage bootloader
    takes care of disabling it.
    Then the 2nd stage bootloader enables the RTC WDT for checking the
    startup sequence of the application image.
    
    Signed-off-by: Gustavo Henrique Nihei <gu...@espressif.com>
---
 arch/xtensa/src/esp32/esp32_start.c            | 4 +++-
 arch/xtensa/src/esp32/hardware/esp32_rtccntl.h | 6 ++++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c
index 4587f7d..a70549f 100644
--- a/arch/xtensa/src/esp32/esp32_start.c
+++ b/arch/xtensa/src/esp32/esp32_start.c
@@ -88,9 +88,11 @@ void IRAM_ATTR __start(void)
 
   /* Kill the watchdog timer */
 
+  putreg32(RTC_CNTL_WDT_WKEY_VALUE, RTC_CNTL_WDTWPROTECT_REG);
   regval  = getreg32(RTC_CNTL_WDTCONFIG0_REG);
-  regval &= ~RTC_CNTL_WDT_FLASHBOOT_MOD_EN;
+  regval &= ~RTC_CNTL_WDT_EN;
   putreg32(regval, RTC_CNTL_WDTCONFIG0_REG);
+  putreg32(0, RTC_CNTL_WDTWPROTECT_REG);
 
   /* Make sure that normal interrupts are disabled.  This is really only an
    * issue when we are started in un-usual ways (such as from IRAM).  In this
diff --git a/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h b/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h
index 640fab1..e661726 100644
--- a/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h
+++ b/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h
@@ -47,6 +47,12 @@
 #define RWDT_INT_ENA_REG_OFFSET     0x003c
 #define RWDT_INT_CLR_REG_OFFSET     0x0048
 
+/* The value that needs to be written to RTC_CNTL_WDT_WKEY to
+ * write-enable the wdt registers
+ */
+
+#define RTC_CNTL_WDT_WKEY_VALUE     0x50d83aa1
+
 /* CLK */
 #define CK_XTAL_32K_MASK            (BIT(30))
 #define CK8M_D256_OUT_MASK          (BIT(31))