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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/11/03 11:49:30 UTC
[incubator-nuttx] branch master updated: arch/armv7-ar: add isb after CACHE and TLB operations.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new cdeddcb028 arch/armv7-ar: add isb after CACHE and TLB operations.
cdeddcb028 is described below
commit cdeddcb028e02860ee30ea0d126ed912bb48b232
Author: zhangyuan21 <zh...@xiaomi.com>
AuthorDate: Wed Nov 2 09:52:34 2022 +0800
arch/armv7-ar: add isb after CACHE and TLB operations.
---
arch/arm/src/armv7-a/arm_cpuhead.S | 2 ++
arch/arm/src/armv7-a/arm_head.S | 4 ++++
arch/arm/src/armv7-a/arm_pghead.S | 2 ++
arch/arm/src/armv7-r/arm_head.S | 2 ++
4 files changed, 10 insertions(+)
diff --git a/arch/arm/src/armv7-a/arm_cpuhead.S b/arch/arm/src/armv7-a/arm_cpuhead.S
index 56ca754c2b..07cd6fb12b 100644
--- a/arch/arm/src/armv7-a/arm_cpuhead.S
+++ b/arch/arm/src/armv7-a/arm_cpuhead.S
@@ -211,6 +211,7 @@ __cpu3_start:
mcr CP15_BPIALL(r0) /* Invalidate entire branch prediction array */
mcr CP15_ICIALLU(r0) /* Invalidate I-cache */
#endif
+ isb
/* Load the page table address.
*
@@ -369,6 +370,7 @@ __cpu3_start:
/* Then write the configured control register */
mcr CP15_SCTLR(r0) /* Write control reg */
+ isb
.rept 12 /* Cortex A8 wants lots of NOPs here */
nop
.endr
diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S
index 0ce90ec415..1452602202 100644
--- a/arch/arm/src/armv7-a/arm_head.S
+++ b/arch/arm/src/armv7-a/arm_head.S
@@ -208,6 +208,7 @@ __cpu0_start:
bic r0, r0, #(SCTLR_M | SCTLR_C)
bic r0, r0, #(SCTLR_I)
mcr CP15_SCTLR(r0)
+ isb
/* Clear the 16K level 1 page table */
@@ -364,6 +365,8 @@ __cpu0_start:
mcr CP15_ICIALLU(r0) /* Invalidate I-cache */
#endif
+ isb
+
/* Load the page table address.
*
* NOTES:
@@ -523,6 +526,7 @@ __cpu0_start:
/* Then write the configured control register */
mcr CP15_SCTLR(r0) /* Write control reg */
+ isb
.rept 12 /* Cortex A8 wants lots of NOPs here */
nop
.endr
diff --git a/arch/arm/src/armv7-a/arm_pghead.S b/arch/arm/src/armv7-a/arm_pghead.S
index df56291712..5c82b3f0f3 100644
--- a/arch/arm/src/armv7-a/arm_pghead.S
+++ b/arch/arm/src/armv7-a/arm_pghead.S
@@ -320,6 +320,7 @@ __start:
mcr CP15_TLBIALL(r0,c5)
mcr CP15_BPIALL(r0) /* Invalidate entire branch prediction array */
mcr CP15_ICIALLU(r0) /* Invalidate I-cache */
+ isb
/* Load the page table address.
*
@@ -467,6 +468,7 @@ __start:
/* Then write the configured control register */
mcr CP15_SCTLR(r0) /* Write control reg */
+ isb
.rept 12 /* Cortex A8 wants lots of NOPs here */
nop
.endr
diff --git a/arch/arm/src/armv7-r/arm_head.S b/arch/arm/src/armv7-r/arm_head.S
index a881845437..8d163a0ed0 100644
--- a/arch/arm/src/armv7-r/arm_head.S
+++ b/arch/arm/src/armv7-r/arm_head.S
@@ -161,6 +161,7 @@ __start:
mcr CP15_BPIALL(r0) /* Invalidate entire branch prediction array */
mcr CP15_ICIALLU(r0) /* Invalidate I-cache */
mcr CP15_DCIALLU(r0) /* Invalidate D-cache */
+ isb
/* Configure the system control register (see sctrl.h) */
@@ -313,6 +314,7 @@ __start:
/* Then write the configured control register */
mcr CP15_SCTLR(r0) /* Write control reg */
+ isb
.rept 12 /* Some CPUs want want lots of NOPs here */
nop
.endr