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Posted to commits@nuttx.apache.org by gu...@apache.org on 2021/05/07 19:46:51 UTC
[incubator-nuttx] branch master updated (b8ed17b -> 90a4e8d)
This is an automated email from the ASF dual-hosted git repository.
gustavonihei pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from b8ed17b libc/termios: Implement TCSADRAIN and TCSAFLUSH for tcsetattr
new bd8e37b risc-v/esp32c3: Add ESP32-C3 (G)DMA driver and testing
new 90a4e8d risc-v/esp32c3: Fix DMA channels' interrupt IDs
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/risc-v/include/esp32c3/irq.h | 10 +-
arch/risc-v/src/esp32c3/Kconfig | 24 +
arch/risc-v/src/esp32c3/Make.defs | 4 +
arch/risc-v/src/esp32c3/esp32c3_dma.c | 516 +++
arch/risc-v/src/esp32c3/esp32c3_dma.h | 223 ++
arch/risc-v/src/esp32c3/hardware/esp32c3_dma.h | 3898 ++++++++++++++++++++
.../esp32c3-devkit/configs/{nsh => dma}/defconfig | 20 +-
7 files changed, 4675 insertions(+), 20 deletions(-)
create mode 100644 arch/risc-v/src/esp32c3/esp32c3_dma.c
create mode 100644 arch/risc-v/src/esp32c3/esp32c3_dma.h
create mode 100644 arch/risc-v/src/esp32c3/hardware/esp32c3_dma.h
copy boards/risc-v/esp32c3/esp32c3-devkit/configs/{nsh => dma}/defconfig (66%)
[incubator-nuttx] 02/02: risc-v/esp32c3: Fix DMA channels'
interrupt IDs
Posted by gu...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gustavonihei pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 90a4e8d718c269ac110289ea0fac368abe78ef54
Author: Gustavo Henrique Nihei <gu...@espressif.com>
AuthorDate: Fri Apr 30 14:22:06 2021 -0300
risc-v/esp32c3: Fix DMA channels' interrupt IDs
---
arch/risc-v/include/esp32c3/irq.h | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/risc-v/include/esp32c3/irq.h b/arch/risc-v/include/esp32c3/irq.h
index a6ec2a7..d7aff5e 100644
--- a/arch/risc-v/include/esp32c3/irq.h
+++ b/arch/risc-v/include/esp32c3/irq.h
@@ -29,6 +29,8 @@
# include <arch/csr.h>
#endif
+#include <sys/types.h>
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -95,8 +97,8 @@
#define ESP32C3_PERIPH_ICACHE_SYNC0 42
#define ESP32C3_PERIPH_APB_ADC 43
#define ESP32C3_PERIPH_DMA_CH0 44
-#define ESP32C3_PERIPH_DMA_CH0 45
-#define ESP32C3_PERIPH_DMA_CH0 46
+#define ESP32C3_PERIPH_DMA_CH1 45
+#define ESP32C3_PERIPH_DMA_CH2 46
#define ESP32C3_PERIPH_RSA 47
#define ESP32C3_PERIPH_AES 48
#define ESP32C3_PERIPH_SHA 49
@@ -186,8 +188,8 @@
#define ESP32C3_IRQ_ICACHE_SYNC0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_ICACHE_SYNC0)
#define ESP32C3_IRQ_APB_ADC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_APB_ADC)
#define ESP32C3_IRQ_DMA_CH0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH0)
-#define ESP32C3_IRQ_DMA_CH0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH0)
-#define ESP32C3_IRQ_DMA_CH0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH0)
+#define ESP32C3_IRQ_DMA_CH1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH1)
+#define ESP32C3_IRQ_DMA_CH2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH2)
#define ESP32C3_IRQ_RSA (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RSA)
#define ESP32C3_IRQ_AES (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_AES)
#define ESP32C3_IRQ_SHA (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SHA)
[incubator-nuttx] 01/02: risc-v/esp32c3: Add ESP32-C3 (G)DMA driver
and testing
Posted by gu...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gustavonihei pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit bd8e37bb4b0adc71ad1577557e73e82c8066fc39
Author: Dong Heng <do...@espressif.com>
AuthorDate: Fri Apr 30 14:14:45 2021 +0800
risc-v/esp32c3: Add ESP32-C3 (G)DMA driver and testing
---
arch/risc-v/src/esp32c3/Kconfig | 24 +
arch/risc-v/src/esp32c3/Make.defs | 4 +
arch/risc-v/src/esp32c3/esp32c3_dma.c | 516 +++
arch/risc-v/src/esp32c3/esp32c3_dma.h | 223 ++
arch/risc-v/src/esp32c3/hardware/esp32c3_dma.h | 3898 ++++++++++++++++++++
.../esp32c3/esp32c3-devkit/configs/dma/defconfig | 32 +
6 files changed, 4697 insertions(+)
diff --git a/arch/risc-v/src/esp32c3/Kconfig b/arch/risc-v/src/esp32c3/Kconfig
index 72e5090..8899081 100644
--- a/arch/risc-v/src/esp32c3/Kconfig
+++ b/arch/risc-v/src/esp32c3/Kconfig
@@ -237,6 +237,11 @@ config ESP32C3_SPI2
select ESP32C3_SPI
select SPI
+config ESP32C3_DMA
+ bool "General DMA (GDMA)"
+ default n
+ select ARCH_DMA
+
config ESP32C3_MWDT0
bool "Main System Watchdog Timer (Group 0)"
default n
@@ -542,4 +547,23 @@ config ESP32C3_PARTITION_MOUNT
endmenu # ESP32C3_PARTITION
+menu "GDMA Configuration"
+ depends on ESP32C3_DMA
+
+config ESP32C3_DMA_M2M_TEST
+ bool "Test GDMA M2M"
+ default n
+
+config ESP32C3_DMA_M2M_TEST_LOOPS
+ int "Test GDMA M2M loops"
+ default 256
+ depends on ESP32C3_DMA_M2M_TEST
+
+config ESP32C3_DMA_M2M_TEST_BUFSIZE
+ int "Test GDMA M2M buffer size"
+ default 16000
+ depends on ESP32C3_DMA_M2M_TEST
+
+endmenu # GDMA Configuration
+
endif # ARCH_CHIP_ESP32C3
diff --git a/arch/risc-v/src/esp32c3/Make.defs b/arch/risc-v/src/esp32c3/Make.defs
index 7c333a7..369dceb 100644
--- a/arch/risc-v/src/esp32c3/Make.defs
+++ b/arch/risc-v/src/esp32c3/Make.defs
@@ -108,6 +108,10 @@ ifeq ($(CONFIG_ESP32C3_DISABLE_STDC_ATOMIC),)
CHIP_CSRCS += esp32c3_std_atomic.c
endif
+ifeq ($(CONFIG_ESP32C3_DMA),y)
+CHIP_CSRCS += esp32c3_dma.c
+endif
+
ifeq ($(CONFIG_ESP32C3_WIRELESS),y)
WIRELESS_DRV_UNPACK = esp-wireless-drivers-3rdparty
WIRELESS_DRV_ID = 2b53111
diff --git a/arch/risc-v/src/esp32c3/esp32c3_dma.c b/arch/risc-v/src/esp32c3/esp32c3_dma.c
new file mode 100644
index 0000000..384c6de
--- /dev/null
+++ b/arch/risc-v/src/esp32c3/esp32c3_dma.c
@@ -0,0 +1,516 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c3/esp32c3_dma.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/kmalloc.h>
+#include <arch/irq.h>
+
+#include "riscv_arch.h"
+
+#include "esp32c3_dma.h"
+
+#include "hardware/esp32c3_dma.h"
+#include "hardware/esp32c3_soc.h"
+#include "hardware/esp32c3_system.h"
+
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+#define REG_OFF (DMA_OUT_CONF0_CH1_REG - DMA_OUT_CONF0_CH0_REG)
+
+#define SET_REG(_r, _ch, _v) putreg32((_v), (_r) + (_ch) * REG_OFF)
+#define GET_REG(_r, _ch, _v) getreg32((_r) + (_ch) * REG_OFF)
+
+#define SET_BITS(_r, _ch, _b) modifyreg32((_r) + (_ch) * REG_OFF, 0, (_b))
+#define CLR_BITS(_r, _ch, _b) modifyreg32((_r) + (_ch) * REG_OFF, (_b), 0)
+
+#ifndef MIN
+# define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#ifndef ALIGN_UP
+# define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static bool g_dma_chan_used[ESP32C3_DMA_CHAN_MAX];
+static sem_t g_dma_exc_sem = SEM_INITIALIZER(1);
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c3_dma_request
+ *
+ * Description:
+ * Request DMA channel and config it with given parameters.
+ *
+ * Input Parameters:
+ * periph - Peripheral for which the DMA channel request was made
+ * tx_prio - Interrupt priority
+ * rx_prio - Interrupt flags
+ *
+ * Returned Value:
+ * DMA channel number (>=0) if success or -1 if fail.
+ *
+ ****************************************************************************/
+
+int32_t esp32c3_dma_request(enum esp32c3_dma_periph_e periph,
+ uint32_t tx_prio,
+ uint32_t rx_prio)
+{
+ int chan;
+
+ DEBUGASSERT((periph < ESP32C3_DMA_PERIPH_NUM) &&
+ (periph != ESP32C3_DMA_PERIPH_RD0) &&
+ (periph != ESP32C3_DMA_PERIPH_RD1));
+
+ DEBUGASSERT(tx_prio <= ESP32C3_DMA_TX_PRIO_MAX);
+ DEBUGASSERT(rx_prio <= ESP32C3_DMA_RX_PRIO_MAX);
+
+ dmainfo("periph=%" PRIu32 " tx_prio=%" PRIu32 " rx_prio=%" PRIu32 "\n",
+ (uint32_t)periph, tx_prio, rx_prio);
+
+ nxsem_wait_uninterruptible(&g_dma_exc_sem);
+
+ for (chan = 0; chan < ESP32C3_DMA_CHAN_MAX; chan++)
+ {
+ if (!g_dma_chan_used[chan])
+ {
+ g_dma_chan_used[chan] = true;
+ break;
+ }
+ }
+
+ if (chan == ESP32C3_DMA_CHAN_MAX)
+ {
+ dmaerr("No available GDMA channel for allocation\n");
+
+ nxsem_post(&g_dma_exc_sem);
+
+ return ERROR;
+ }
+
+ dmainfo("Allocated channel=%d\n", chan);
+
+ if (periph == ESP32C3_DMA_PERIPH_MEM)
+ {
+ /* Enable DMA channel M2M mode */
+
+ SET_BITS(DMA_IN_CONF0_CH0_REG, chan, DMA_MEM_TRANS_EN_CH0_M);
+
+ /* Just setting a valid value to the register */
+
+ SET_REG(DMA_OUT_PERI_SEL_CH0_REG, chan, 0);
+ SET_REG(DMA_IN_PERI_SEL_CH0_REG, chan, 0);
+ }
+ else
+ {
+ /* Disable DMA channel M2M mode */
+
+ CLR_BITS(DMA_IN_CONF0_CH0_REG, chan, DMA_MEM_TRANS_EN_CH0_M);
+
+ /* Connect DMA TX/RX channel to a given peripheral */
+
+ SET_REG(DMA_OUT_PERI_SEL_CH0_REG, chan, periph);
+ SET_REG(DMA_IN_PERI_SEL_CH0_REG, chan, periph);
+ }
+
+ SET_REG(DMA_OUT_PRI_CH0_REG, chan, tx_prio);
+ SET_REG(DMA_IN_PRI_CH0_REG, chan, rx_prio);
+
+ nxsem_post(&g_dma_exc_sem);
+
+ return chan;
+}
+
+/****************************************************************************
+ * Name: esp32c3_dma_setup
+ *
+ * Description:
+ * Set up DMA descriptor with given parameters.
+ *
+ * Input Parameters:
+ * chan - DMA channel
+ * tx - true: TX mode; false: RX mode
+ * dmadesc - DMA descriptor pointer
+ * num - DMA descriptor number
+ * pbuf - Buffer pointer
+ * len - Buffer length by byte
+ *
+ * Returned Value:
+ * Bind pbuf data bytes.
+ *
+ ****************************************************************************/
+
+uint32_t esp32c3_dma_setup(int chan, bool tx,
+ struct esp32c3_dmadesc_s *dmadesc, uint32_t num,
+ uint8_t *pbuf, uint32_t len)
+{
+ int i;
+ uint32_t regval;
+ uint32_t bytes = len;
+ uint8_t *pdata = pbuf;
+ uint32_t data_len;
+ uint32_t buf_len;
+
+ DEBUGASSERT(chan >= 0);
+ DEBUGASSERT(dmadesc != NULL);
+ DEBUGASSERT(num > 0);
+ DEBUGASSERT(pbuf != NULL);
+ DEBUGASSERT(len > 0);
+
+ for (i = 0; i < num; i++)
+ {
+ data_len = MIN(bytes, ESP32C3_DMA_BUFLEN_MAX);
+
+ /* Buffer length must be rounded to next 32-bit boundary. */
+
+ buf_len = ALIGN_UP(data_len, sizeof(uintptr_t));
+
+ dmadesc[i].ctrl = (data_len << ESP32C3_DMA_CTRL_DATALEN_S) |
+ (buf_len << ESP32C3_DMA_CTRL_BUFLEN_S) |
+ ESP32C3_DMA_CTRL_OWN;
+ dmadesc[i].pbuf = pdata;
+ dmadesc[i].next = &dmadesc[i + 1];
+
+ bytes -= data_len;
+ if (bytes == 0)
+ {
+ break;
+ }
+
+ pdata += data_len;
+ }
+
+ dmadesc[i].ctrl |= ESP32C3_DMA_CTRL_EOF;
+ dmadesc[i].next = NULL;
+
+ if (tx)
+ {
+ /* Reset DMA TX channel FSM and FIFO pointer */
+
+ SET_BITS(DMA_OUT_CONF0_CH0_REG, chan, DMA_OUT_RST_CH0_M);
+ CLR_BITS(DMA_OUT_CONF0_CH0_REG, chan, DMA_OUT_RST_CH0_M);
+
+ /* Set the descriptor link base address for TX channel */
+
+ regval = (uint32_t)dmadesc & DMA_OUTLINK_ADDR_CH0;
+ SET_BITS(DMA_OUT_LINK_CH0_REG, chan, regval);
+ }
+ else
+ {
+ /* Reset DMA RX channel FSM and FIFO pointer */
+
+ SET_BITS(DMA_IN_CONF0_CH0_REG, chan, DMA_IN_RST_CH0_M);
+ CLR_BITS(DMA_IN_CONF0_CH0_REG, chan, DMA_IN_RST_CH0_M);
+
+ /* Set the descriptor link base address for RX channel */
+
+ regval = (uint32_t)dmadesc & DMA_INLINK_ADDR_CH0;
+ SET_BITS(DMA_IN_LINK_CH0_REG, chan, regval);
+ }
+
+ return len - bytes;
+}
+
+/****************************************************************************
+ * Name: esp32c3_dma_enable
+ *
+ * Description:
+ * Enable DMA channel transmission.
+ *
+ * Input Parameters:
+ * chan - DMA channel
+ * tx - true: TX mode; false: RX mode
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp32c3_dma_enable(int chan, bool tx)
+{
+ if (tx)
+ {
+ SET_BITS(DMA_OUT_LINK_CH0_REG, chan, DMA_OUTLINK_START_CH0_M);
+ }
+ else
+ {
+ SET_BITS(DMA_IN_LINK_CH0_REG, chan, DMA_INLINK_START_CH0_M);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32c3_dma_disable
+ *
+ * Description:
+ * Disable DMA channel transmission.
+ *
+ * Input Parameters:
+ * chan - DMA channel
+ * tx - true: TX mode; false: RX mode
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp32c3_dma_disable(int chan, bool tx)
+{
+ if (tx)
+ {
+ SET_BITS(DMA_OUT_LINK_CH0_REG, chan, DMA_OUTLINK_STOP_CH0_M);
+ }
+ else
+ {
+ SET_BITS(DMA_IN_LINK_CH0_REG, chan, DMA_INLINK_STOP_CH0_M);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32c3_dma_wait_idle
+ *
+ * Description:
+ * Wait until transmission ends.
+ *
+ * Input Parameters:
+ * chan - DMA channel
+ * tx - true: TX mode; false: RX mode
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp32c3_dma_wait_idle(int chan, bool tx)
+{
+ uint32_t regval;
+ uint32_t regaddr;
+ uint32_t waitbits;
+
+ if (tx)
+ {
+ regaddr = DMA_OUT_LINK_CH0_REG + chan * REG_OFF;
+ waitbits = DMA_OUTLINK_PARK_CH0;
+ }
+ else
+ {
+ regaddr = DMA_IN_LINK_CH0_REG + chan * REG_OFF;
+ waitbits = DMA_INLINK_PARK_CH0;
+ }
+
+ do
+ {
+ regval = getreg32(regaddr);
+ }
+ while ((waitbits & regval) == 0);
+}
+
+/****************************************************************************
+ * Name: esp32c3_dma_init
+ *
+ * Description:
+ * Initialize DMA driver.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp32c3_dma_init(void)
+{
+ modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, 0, SYSTEM_DMA_CLK_EN_M);
+ modifyreg32(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST_M, 0);
+
+ modifyreg32(DMA_MISC_CONF_REG, 0, DMA_CLK_EN_M);
+}
+
+/****************************************************************************
+ * Name: esp32c3_dma_main
+ *
+ * Description:
+ * ESP32-C3 DMA testing example.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32C3_DMA_M2M_TEST
+void esp32c3_dma_main(int argc, char *argv[])
+{
+ int chan;
+ struct esp32c3_dmadesc_s *rx_dmadesc;
+ struct esp32c3_dmadesc_s *tx_dmadesc;
+ uint8_t *rxbuf;
+ uint8_t *txbuf;
+ bool success = true;
+
+ const size_t bufsize = CONFIG_ESP32C3_DMA_M2M_TEST_BUFSIZE;
+#if (CONFIG_ESP32C3_DMA_M2M_TEST_BUFSIZE % ESP32C3_DMA_BUFLEN_MAX) > 0
+ const size_t dmadesc_num = bufsize / ESP32C3_DMA_BUFLEN_MAX + 1;
+#else
+ const size_t dmadesc_num = bufsize / ESP32C3_DMA_BUFLEN_MAX;
+#endif
+
+ syslog(LOG_INFO, "----- BEGIN TEST -----\n");
+
+ rxbuf = kmm_malloc(bufsize);
+ if (rxbuf == NULL)
+ {
+ syslog(LOG_ERR, "Failed to malloc RX buffer\n");
+
+ success = false;
+ goto test_end;
+ }
+
+ txbuf = kmm_malloc(bufsize);
+ if (txbuf == NULL)
+ {
+ syslog(LOG_ERR, "Failed to malloc TX buffer\n");
+ kmm_free(rxbuf);
+
+ success = false;
+ goto test_end;
+ }
+
+ rx_dmadesc = kmm_malloc(sizeof(struct esp32c3_dmadesc_s) * dmadesc_num);
+ if (rx_dmadesc == NULL)
+ {
+ syslog(LOG_ERR, "Failed to malloc RX DMA descriptor\n");
+ kmm_free(txbuf);
+ kmm_free(rxbuf);
+
+ success = false;
+ goto test_end;
+ }
+
+ tx_dmadesc = kmm_malloc(sizeof(struct esp32c3_dmadesc_s) * dmadesc_num);
+ if (txbuf == NULL)
+ {
+ syslog(LOG_ERR, "Failed to malloc TX DMA descriptor\n");
+ kmm_free(rx_dmadesc);
+ kmm_free(txbuf);
+ kmm_free(rxbuf);
+
+ success = false;
+ goto test_end;
+ }
+
+ esp32c3_dma_init();
+
+ chan = esp32c3_dma_request(ESP32C3_DMA_PERIPH_MEM, 1, 1);
+ if (chan < 0)
+ {
+ syslog(LOG_ERR, "Request DMA channel error\n");
+
+ success = false;
+ goto test_end_cleanup;
+ }
+
+ for (int i = 1; i <= CONFIG_ESP32C3_DMA_M2M_TEST_LOOPS; ++i)
+ {
+ const uint8_t watermark = i & UINT8_MAX;
+ size_t j = 0;
+
+ /* Prepare buffers for DMA transfer */
+
+ memset(rxbuf, 0, bufsize);
+ memset(txbuf, watermark, bufsize);
+
+ /* Setup DMA descriptors.
+ * Intentionally ignore the last byte for TX.
+ */
+
+ esp32c3_dma_setup(chan, false, rx_dmadesc, dmadesc_num,
+ rxbuf, bufsize);
+ esp32c3_dma_setup(chan, true, tx_dmadesc, dmadesc_num,
+ txbuf, bufsize - 1);
+
+ /* Start DMA transfer */
+
+ esp32c3_dma_enable(chan, false);
+ esp32c3_dma_enable(chan, true);
+
+ /* Wait for DMA transfer to complete */
+
+ esp32c3_dma_wait_idle(chan, true);
+ esp32c3_dma_wait_idle(chan, false);
+
+ /* Verify if last byte on RX buffer is unchanged */
+
+ if (rxbuf[bufsize - 1] != 0)
+ {
+ success = false;
+ goto test_end_cleanup;
+ }
+
+ /* Verify if RX buffer contains expected values */
+
+ for (j = 0; j < bufsize - 1; ++j)
+ {
+ if (rxbuf[j] != watermark)
+ {
+ syslog(LOG_ERR,
+ "DMA-M2M-TEST loop %d fail buf[%zu]=%" PRIu8 "\n",
+ i, j, rxbuf[j]);
+
+ success = false;
+ goto test_end_cleanup;
+ }
+ }
+
+ syslog(LOG_INFO, "DMA-M2M-TEST loop %d OK\n", i);
+ }
+
+test_end_cleanup:
+ kmm_free(tx_dmadesc);
+ kmm_free(rx_dmadesc);
+ kmm_free(txbuf);
+ kmm_free(rxbuf);
+
+test_end:
+ syslog(LOG_INFO, "----- END TEST -----\n");
+
+ syslog(LOG_INFO, "\n");
+
+ syslog(LOG_INFO, "----- RESULT: %s -----\n",
+ success ? "SUCCESS" : "FAILED");
+}
+#endif
diff --git a/arch/risc-v/src/esp32c3/esp32c3_dma.h b/arch/risc-v/src/esp32c3/esp32c3_dma.h
new file mode 100644
index 0000000..5dbb72c
--- /dev/null
+++ b/arch/risc-v/src/esp32c3/esp32c3_dma.h
@@ -0,0 +1,223 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c3/esp32c3_dma.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_DMA_H
+#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_DMA_H
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+/* DMA max data length */
+
+#define ESP32C3_DMA_DATALEN_MAX (0x1000 - 4)
+
+/* DMA max buffer length */
+
+#define ESP32C3_DMA_BUFLEN_MAX ESP32C3_DMA_DATALEN_MAX
+
+/* DMA channel number */
+
+#define ESP32C3_DMA_CHAN_MAX (3)
+
+/* DMA RX MAX priority */
+
+#define ESP32C3_DMA_RX_PRIO_MAX (15)
+
+/* DMA TX MAX priority */
+
+#define ESP32C3_DMA_TX_PRIO_MAX (15)
+
+/* DMA descriptor */
+
+#define ESP32C3_DMA_CTRL_OWN (1 << 31) /* Owned by DMA */
+#define ESP32C3_DMA_CTRL_EOF (1 << 30) /* End of frame */
+#define ESP32C3_DMA_CTRL_ERREOF (1 << 28) /* Received data error */
+#define ESP32C3_DMA_CTRL_DATALEN_S (12) /* Data length shift */
+#define ESP32C3_DMA_CTRL_DATALEN_V (0xfff) /* Data length value */
+#define ESP32C3_DMA_CTRL_BUFLEN_S (0) /* Buffer length shift */
+#define ESP32C3_DMA_CTRL_BUFLEN_V (0xfff) /* Buffer length value */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+enum esp32c3_dma_periph_e
+{
+ ESP32C3_DMA_PERIPH_MEM = -1,
+ ESP32C3_DMA_PERIPH_SPI = 0,
+ ESP32C3_DMA_PERIPH_UCHI0 = 2,
+ ESP32C3_DMA_PERIPH_I2S = 3,
+ ESP32C3_DMA_PERIPH_RD0 = 4,
+ ESP32C3_DMA_PERIPH_RD1 = 5,
+ ESP32C3_DMA_PERIPH_AES = 6,
+ ESP32C3_DMA_PERIPH_SHA = 7,
+ ESP32C3_DMA_PERIPH_ADC = 8,
+ ESP32C3_DMA_PERIPH_NUM,
+};
+
+/* DMA descriptor type */
+
+struct esp32c3_dmadesc_s
+{
+ uint32_t ctrl; /* DMA control block */
+ uint8_t *pbuf; /* DMA TX/RX buffer address */
+ struct esp32c3_dmadesc_s *next; /* Next DMA descriptor address */
+};
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c3_dma_request
+ *
+ * Description:
+ * Request DMA channel and config it with given parameters.
+ *
+ * Input Parameters:
+ * periph - Peripheral for which the DMA channel request was made
+ * tx_prio - Interrupt priority
+ * rx_prio - Interrupt flags
+ *
+ * Returned Value:
+ * DMA channel number (>=0) if success or -1 if fail.
+ *
+ ****************************************************************************/
+
+int32_t esp32c3_dma_request(enum esp32c3_dma_periph_e periph,
+ uint32_t tx_prio,
+ uint32_t rx_prio);
+
+/****************************************************************************
+ * Name: esp32c3_dma_setup
+ *
+ * Description:
+ * Set up DMA descriptor with given parameters.
+ *
+ * Input Parameters:
+ * chan - DMA channel
+ * tx - true: TX mode; false: RX mode
+ * dmadesc - DMA descriptor pointer
+ * num - DMA descriptor number
+ * pbuf - Buffer pointer
+ * len - Buffer length by byte
+ *
+ * Returned Value:
+ * Bind pbuf data bytes.
+ *
+ ****************************************************************************/
+
+uint32_t esp32c3_dma_setup(int chan, bool tx,
+ struct esp32c3_dmadesc_s *dmadesc, uint32_t num,
+ uint8_t *pbuf, uint32_t len);
+
+/****************************************************************************
+ * Name: esp32c3_dma_enable
+ *
+ * Description:
+ * Enable DMA channel transmission.
+ *
+ * Input Parameters:
+ * chan - DMA channel
+ * tx - true: TX mode; false: RX mode
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp32c3_dma_enable(int chan, bool tx);
+
+/****************************************************************************
+ * Name: esp32c3_dma_disable
+ *
+ * Description:
+ * Disable DMA channel transmission.
+ *
+ * Input Parameters:
+ * chan - DMA channel
+ * tx - true: TX mode; false: RX mode
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp32c3_dma_disable(int chan, bool tx);
+
+/****************************************************************************
+ * Name: esp32c3_dma_wait_idle
+ *
+ * Description:
+ * Wait until transmission ends.
+ *
+ * Input Parameters:
+ * chan - DMA channel
+ * tx - true: TX mode; false: RX mode
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp32c3_dma_wait_idle(int chan, bool tx);
+
+/****************************************************************************
+ * Name: esp32c3_dma_init
+ *
+ * Description:
+ * Initialize DMA driver.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp32c3_dma_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+#undef EXTERN
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_DMA_H */
diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_dma.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_dma.h
new file mode 100644
index 0000000..78b5746
--- /dev/null
+++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_dma.h
@@ -0,0 +1,3898 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c3/hardware/esp32c3_dma.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_DMA_H
+#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_DMA_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32c3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* DMA_INT_RAW_CH0_REG register
+ * DMA_INT_RAW_CH0_REG.
+ */
+
+#define DMA_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x0)
+
+/* DMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ * This raw interrupt bit turns to high level when level 1 fifo of Tx
+ * channel 0 is underflow.
+ */
+
+#define DMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(12))
+#define DMA_OUTFIFO_UDF_CH0_INT_RAW_M (DMA_OUTFIFO_UDF_CH0_INT_RAW_V << DMA_OUTFIFO_UDF_CH0_INT_RAW_S)
+#define DMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001
+#define DMA_OUTFIFO_UDF_CH0_INT_RAW_S 12
+
+/* DMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ * This raw interrupt bit turns to high level when level 1 fifo of Tx
+ * channel 0 is overflow.
+ */
+
+#define DMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(11))
+#define DMA_OUTFIFO_OVF_CH0_INT_RAW_M (DMA_OUTFIFO_OVF_CH0_INT_RAW_V << DMA_OUTFIFO_OVF_CH0_INT_RAW_S)
+#define DMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001
+#define DMA_OUTFIFO_OVF_CH0_INT_RAW_S 11
+
+/* DMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ * This raw interrupt bit turns to high level when level 1 fifo of Rx
+ * channel 0 is underflow.
+ */
+
+#define DMA_INFIFO_UDF_CH0_INT_RAW (BIT(10))
+#define DMA_INFIFO_UDF_CH0_INT_RAW_M (DMA_INFIFO_UDF_CH0_INT_RAW_V << DMA_INFIFO_UDF_CH0_INT_RAW_S)
+#define DMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001
+#define DMA_INFIFO_UDF_CH0_INT_RAW_S 10
+
+/* DMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ * This raw interrupt bit turns to high level when level 1 fifo of Rx
+ * channel 0 is overflow.
+ */
+
+#define DMA_INFIFO_OVF_CH0_INT_RAW (BIT(9))
+#define DMA_INFIFO_OVF_CH0_INT_RAW_M (DMA_INFIFO_OVF_CH0_INT_RAW_V << DMA_INFIFO_OVF_CH0_INT_RAW_S)
+#define DMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001
+#define DMA_INFIFO_OVF_CH0_INT_RAW_S 9
+
+/* DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ * The raw interrupt bit turns to high level when data corresponding a
+ * outlink (includes one link descriptor or few link descriptors) is
+ * transmitted out for Tx channel 0.
+ */
+
+#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S)
+#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001
+#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 8
+
+/* DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ * The raw interrupt bit turns to high level when Rx buffer pointed by
+ * inlink is full and receiving data is not completed, but there is no more
+ * inlink for Rx channel 0.
+ */
+
+#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S)
+#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001
+#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 7
+
+/* DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ * The raw interrupt bit turns to high level when detecting outlink
+ * descriptor error, including owner error, the second and third word error
+ * of outlink descriptor for Tx channel 0.
+ */
+
+#define DMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_M (DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << DMA_OUT_DSCR_ERR_CH0_INT_RAW_S)
+#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001
+#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_S 6
+
+/* DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ * The raw interrupt bit turns to high level when detecting inlink
+ * descriptor error, including owner error, the second and third word error
+ * of inlink descriptor for Rx channel 0.
+ */
+
+#define DMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(5))
+#define DMA_IN_DSCR_ERR_CH0_INT_RAW_M (DMA_IN_DSCR_ERR_CH0_INT_RAW_V << DMA_IN_DSCR_ERR_CH0_INT_RAW_S)
+#define DMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001
+#define DMA_IN_DSCR_ERR_CH0_INT_RAW_S 5
+
+/* DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ * The raw interrupt bit turns to high level when the last data pointed by
+ * one outlink descriptor has been read from memory for Tx channel 0.
+ */
+
+#define DMA_OUT_EOF_CH0_INT_RAW (BIT(4))
+#define DMA_OUT_EOF_CH0_INT_RAW_M (DMA_OUT_EOF_CH0_INT_RAW_V << DMA_OUT_EOF_CH0_INT_RAW_S)
+#define DMA_OUT_EOF_CH0_INT_RAW_V 0x00000001
+#define DMA_OUT_EOF_CH0_INT_RAW_S 4
+
+/* DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ * The raw interrupt bit turns to high level when the last data pointed by
+ * one outlink descriptor has been transmitted to peripherals for Tx channel
+ * 0.
+ */
+
+#define DMA_OUT_DONE_CH0_INT_RAW (BIT(3))
+#define DMA_OUT_DONE_CH0_INT_RAW_M (DMA_OUT_DONE_CH0_INT_RAW_V << DMA_OUT_DONE_CH0_INT_RAW_S)
+#define DMA_OUT_DONE_CH0_INT_RAW_V 0x00000001
+#define DMA_OUT_DONE_CH0_INT_RAW_S 3
+
+/* DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ * The raw interrupt bit turns to high level when data error is detected
+ * only in the case that the peripheral is UHCI0 for Rx channel 0. For other
+ * peripherals, this raw interrupt is reserved.
+ */
+
+#define DMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2))
+#define DMA_IN_ERR_EOF_CH0_INT_RAW_M (DMA_IN_ERR_EOF_CH0_INT_RAW_V << DMA_IN_ERR_EOF_CH0_INT_RAW_S)
+#define DMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001
+#define DMA_IN_ERR_EOF_CH0_INT_RAW_S 2
+
+/* DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ * The raw interrupt bit turns to high level when the last data pointed by
+ * one inlink descriptor has been received for Rx channel 0. For UHCI0, the
+ * raw interrupt bit turns to high level when the last data pointed by one
+ * inlink descriptor has been received and no data error is detected for Rx
+ * channel 0.
+ */
+
+#define DMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1))
+#define DMA_IN_SUC_EOF_CH0_INT_RAW_M (DMA_IN_SUC_EOF_CH0_INT_RAW_V << DMA_IN_SUC_EOF_CH0_INT_RAW_S)
+#define DMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001
+#define DMA_IN_SUC_EOF_CH0_INT_RAW_S 1
+
+/* DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ * The raw interrupt bit turns to high level when the last data pointed by
+ * one inlink descriptor has been received for Rx channel 0.
+ */
+
+#define DMA_IN_DONE_CH0_INT_RAW (BIT(0))
+#define DMA_IN_DONE_CH0_INT_RAW_M (DMA_IN_DONE_CH0_INT_RAW_V << DMA_IN_DONE_CH0_INT_RAW_S)
+#define DMA_IN_DONE_CH0_INT_RAW_V 0x00000001
+#define DMA_IN_DONE_CH0_INT_RAW_S 0
+
+/* DMA_INT_ST_CH0_REG register
+ * DMA_INT_ST_CH0_REG.
+ */
+
+#define DMA_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x4)
+
+/* DMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0;
+ * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_UDF_CH0_INT_ST (BIT(12))
+#define DMA_OUTFIFO_UDF_CH0_INT_ST_M (DMA_OUTFIFO_UDF_CH0_INT_ST_V << DMA_OUTFIFO_UDF_CH0_INT_ST_S)
+#define DMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001
+#define DMA_OUTFIFO_UDF_CH0_INT_ST_S 12
+
+/* DMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0;
+ * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_OVF_CH0_INT_ST (BIT(11))
+#define DMA_OUTFIFO_OVF_CH0_INT_ST_M (DMA_OUTFIFO_OVF_CH0_INT_ST_V << DMA_OUTFIFO_OVF_CH0_INT_ST_S)
+#define DMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001
+#define DMA_OUTFIFO_OVF_CH0_INT_ST_S 11
+
+/* DMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_UDF_CH0_INT_ST (BIT(10))
+#define DMA_INFIFO_UDF_CH0_INT_ST_M (DMA_INFIFO_UDF_CH0_INT_ST_V << DMA_INFIFO_UDF_CH0_INT_ST_S)
+#define DMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001
+#define DMA_INFIFO_UDF_CH0_INT_ST_S 10
+
+/* DMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_OVF_CH0_INT_ST (BIT(9))
+#define DMA_INFIFO_OVF_CH0_INT_ST_M (DMA_INFIFO_OVF_CH0_INT_ST_V << DMA_INFIFO_OVF_CH0_INT_ST_S)
+#define DMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001
+#define DMA_INFIFO_OVF_CH0_INT_ST_S 9
+
+/* DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_M (DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << DMA_OUT_TOTAL_EOF_CH0_INT_ST_S)
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_S 8
+
+/* DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_M (DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << DMA_IN_DSCR_EMPTY_CH0_INT_ST_S)
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_S 7
+
+/* DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH0_INT_ST_M (DMA_OUT_DSCR_ERR_CH0_INT_ST_V << DMA_OUT_DSCR_ERR_CH0_INT_ST_S)
+#define DMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001
+#define DMA_OUT_DSCR_ERR_CH0_INT_ST_S 6
+
+/* DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_ERR_CH0_INT_ST (BIT(5))
+#define DMA_IN_DSCR_ERR_CH0_INT_ST_M (DMA_IN_DSCR_ERR_CH0_INT_ST_V << DMA_IN_DSCR_ERR_CH0_INT_ST_S)
+#define DMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001
+#define DMA_IN_DSCR_ERR_CH0_INT_ST_S 5
+
+/* DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_EOF_CH0_INT_ST (BIT(4))
+#define DMA_OUT_EOF_CH0_INT_ST_M (DMA_OUT_EOF_CH0_INT_ST_V << DMA_OUT_EOF_CH0_INT_ST_S)
+#define DMA_OUT_EOF_CH0_INT_ST_V 0x00000001
+#define DMA_OUT_EOF_CH0_INT_ST_S 4
+
+/* DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DONE_CH0_INT_ST (BIT(3))
+#define DMA_OUT_DONE_CH0_INT_ST_M (DMA_OUT_DONE_CH0_INT_ST_V << DMA_OUT_DONE_CH0_INT_ST_S)
+#define DMA_OUT_DONE_CH0_INT_ST_V 0x00000001
+#define DMA_OUT_DONE_CH0_INT_ST_S 3
+
+/* DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_ERR_EOF_CH0_INT_ST (BIT(2))
+#define DMA_IN_ERR_EOF_CH0_INT_ST_M (DMA_IN_ERR_EOF_CH0_INT_ST_V << DMA_IN_ERR_EOF_CH0_INT_ST_S)
+#define DMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001
+#define DMA_IN_ERR_EOF_CH0_INT_ST_S 2
+
+/* DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_SUC_EOF_CH0_INT_ST (BIT(1))
+#define DMA_IN_SUC_EOF_CH0_INT_ST_M (DMA_IN_SUC_EOF_CH0_INT_ST_V << DMA_IN_SUC_EOF_CH0_INT_ST_S)
+#define DMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001
+#define DMA_IN_SUC_EOF_CH0_INT_ST_S 1
+
+/* DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ * The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+
+#define DMA_IN_DONE_CH0_INT_ST (BIT(0))
+#define DMA_IN_DONE_CH0_INT_ST_M (DMA_IN_DONE_CH0_INT_ST_V << DMA_IN_DONE_CH0_INT_ST_S)
+#define DMA_IN_DONE_CH0_INT_ST_V 0x00000001
+#define DMA_IN_DONE_CH0_INT_ST_S 0
+
+/* DMA_INT_ENA_CH0_REG register
+ * DMA_INT_ENA_CH0_REG.
+ */
+
+#define DMA_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x8)
+
+/* DMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(12))
+#define DMA_OUTFIFO_UDF_CH0_INT_ENA_M (DMA_OUTFIFO_UDF_CH0_INT_ENA_V << DMA_OUTFIFO_UDF_CH0_INT_ENA_S)
+#define DMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001
+#define DMA_OUTFIFO_UDF_CH0_INT_ENA_S 12
+
+/* DMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0;
+ * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(11))
+#define DMA_OUTFIFO_OVF_CH0_INT_ENA_M (DMA_OUTFIFO_OVF_CH0_INT_ENA_V << DMA_OUTFIFO_OVF_CH0_INT_ENA_S)
+#define DMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001
+#define DMA_OUTFIFO_OVF_CH0_INT_ENA_S 11
+
+/* DMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_UDF_CH0_INT_ENA (BIT(10))
+#define DMA_INFIFO_UDF_CH0_INT_ENA_M (DMA_INFIFO_UDF_CH0_INT_ENA_V << DMA_INFIFO_UDF_CH0_INT_ENA_S)
+#define DMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001
+#define DMA_INFIFO_UDF_CH0_INT_ENA_S 10
+
+/* DMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_OVF_CH0_INT_ENA (BIT(9))
+#define DMA_INFIFO_OVF_CH0_INT_ENA_M (DMA_INFIFO_OVF_CH0_INT_ENA_V << DMA_INFIFO_OVF_CH0_INT_ENA_S)
+#define DMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001
+#define DMA_INFIFO_OVF_CH0_INT_ENA_S 9
+
+/* DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S)
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 8
+
+/* DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S)
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 7
+
+/* DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_M (DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << DMA_OUT_DSCR_ERR_CH0_INT_ENA_S)
+#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001
+#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_S 6
+
+/* DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(5))
+#define DMA_IN_DSCR_ERR_CH0_INT_ENA_M (DMA_IN_DSCR_ERR_CH0_INT_ENA_V << DMA_IN_DSCR_ERR_CH0_INT_ENA_S)
+#define DMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001
+#define DMA_IN_DSCR_ERR_CH0_INT_ENA_S 5
+
+/* DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ * The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_EOF_CH0_INT_ENA (BIT(4))
+#define DMA_OUT_EOF_CH0_INT_ENA_M (DMA_OUT_EOF_CH0_INT_ENA_V << DMA_OUT_EOF_CH0_INT_ENA_S)
+#define DMA_OUT_EOF_CH0_INT_ENA_V 0x00000001
+#define DMA_OUT_EOF_CH0_INT_ENA_S 4
+
+/* DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ * The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DONE_CH0_INT_ENA (BIT(3))
+#define DMA_OUT_DONE_CH0_INT_ENA_M (DMA_OUT_DONE_CH0_INT_ENA_V << DMA_OUT_DONE_CH0_INT_ENA_S)
+#define DMA_OUT_DONE_CH0_INT_ENA_V 0x00000001
+#define DMA_OUT_DONE_CH0_INT_ENA_S 3
+
+/* DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2))
+#define DMA_IN_ERR_EOF_CH0_INT_ENA_M (DMA_IN_ERR_EOF_CH0_INT_ENA_V << DMA_IN_ERR_EOF_CH0_INT_ENA_S)
+#define DMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001
+#define DMA_IN_ERR_EOF_CH0_INT_ENA_S 2
+
+/* DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1))
+#define DMA_IN_SUC_EOF_CH0_INT_ENA_M (DMA_IN_SUC_EOF_CH0_INT_ENA_V << DMA_IN_SUC_EOF_CH0_INT_ENA_S)
+#define DMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001
+#define DMA_IN_SUC_EOF_CH0_INT_ENA_S 1
+
+/* DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ * The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+
+#define DMA_IN_DONE_CH0_INT_ENA (BIT(0))
+#define DMA_IN_DONE_CH0_INT_ENA_M (DMA_IN_DONE_CH0_INT_ENA_V << DMA_IN_DONE_CH0_INT_ENA_S)
+#define DMA_IN_DONE_CH0_INT_ENA_V 0x00000001
+#define DMA_IN_DONE_CH0_INT_ENA_S 0
+
+/* DMA_INT_CLR_CH0_REG register
+ * DMA_INT_CLR_CH0_REG.
+ */
+
+#define DMA_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0xc)
+
+/* DMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0;
+ * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(12))
+#define DMA_OUTFIFO_UDF_CH0_INT_CLR_M (DMA_OUTFIFO_UDF_CH0_INT_CLR_V << DMA_OUTFIFO_UDF_CH0_INT_CLR_S)
+#define DMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001
+#define DMA_OUTFIFO_UDF_CH0_INT_CLR_S 12
+
+/* DMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0;
+ * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(11))
+#define DMA_OUTFIFO_OVF_CH0_INT_CLR_M (DMA_OUTFIFO_OVF_CH0_INT_CLR_V << DMA_OUTFIFO_OVF_CH0_INT_CLR_S)
+#define DMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001
+#define DMA_OUTFIFO_OVF_CH0_INT_CLR_S 11
+
+/* DMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_UDF_CH0_INT_CLR (BIT(10))
+#define DMA_INFIFO_UDF_CH0_INT_CLR_M (DMA_INFIFO_UDF_CH0_INT_CLR_V << DMA_INFIFO_UDF_CH0_INT_CLR_S)
+#define DMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001
+#define DMA_INFIFO_UDF_CH0_INT_CLR_S 10
+
+/* DMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_OVF_CH0_INT_CLR (BIT(9))
+#define DMA_INFIFO_OVF_CH0_INT_CLR_M (DMA_INFIFO_OVF_CH0_INT_CLR_V << DMA_INFIFO_OVF_CH0_INT_CLR_S)
+#define DMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001
+#define DMA_INFIFO_OVF_CH0_INT_CLR_S 9
+
+/* DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S)
+#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001
+#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 8
+
+/* DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S)
+#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001
+#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 7
+
+/* DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_M (DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << DMA_OUT_DSCR_ERR_CH0_INT_CLR_S)
+#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001
+#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_S 6
+
+/* DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(5))
+#define DMA_IN_DSCR_ERR_CH0_INT_CLR_M (DMA_IN_DSCR_ERR_CH0_INT_CLR_V << DMA_IN_DSCR_ERR_CH0_INT_CLR_S)
+#define DMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001
+#define DMA_IN_DSCR_ERR_CH0_INT_CLR_S 5
+
+/* DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ * Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_EOF_CH0_INT_CLR (BIT(4))
+#define DMA_OUT_EOF_CH0_INT_CLR_M (DMA_OUT_EOF_CH0_INT_CLR_V << DMA_OUT_EOF_CH0_INT_CLR_S)
+#define DMA_OUT_EOF_CH0_INT_CLR_V 0x00000001
+#define DMA_OUT_EOF_CH0_INT_CLR_S 4
+
+/* DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ * Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DONE_CH0_INT_CLR (BIT(3))
+#define DMA_OUT_DONE_CH0_INT_CLR_M (DMA_OUT_DONE_CH0_INT_CLR_V << DMA_OUT_DONE_CH0_INT_CLR_S)
+#define DMA_OUT_DONE_CH0_INT_CLR_V 0x00000001
+#define DMA_OUT_DONE_CH0_INT_CLR_S 3
+
+/* DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2))
+#define DMA_IN_ERR_EOF_CH0_INT_CLR_M (DMA_IN_ERR_EOF_CH0_INT_CLR_V << DMA_IN_ERR_EOF_CH0_INT_CLR_S)
+#define DMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001
+#define DMA_IN_ERR_EOF_CH0_INT_CLR_S 2
+
+/* DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1))
+#define DMA_IN_SUC_EOF_CH0_INT_CLR_M (DMA_IN_SUC_EOF_CH0_INT_CLR_V << DMA_IN_SUC_EOF_CH0_INT_CLR_S)
+#define DMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001
+#define DMA_IN_SUC_EOF_CH0_INT_CLR_S 1
+
+/* DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ * Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+
+#define DMA_IN_DONE_CH0_INT_CLR (BIT(0))
+#define DMA_IN_DONE_CH0_INT_CLR_M (DMA_IN_DONE_CH0_INT_CLR_V << DMA_IN_DONE_CH0_INT_CLR_S)
+#define DMA_IN_DONE_CH0_INT_CLR_V 0x00000001
+#define DMA_IN_DONE_CH0_INT_CLR_S 0
+
+/* DMA_INT_RAW_CH1_REG register
+ * DMA_INT_RAW_CH1_REG.
+ */
+
+#define DMA_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x10)
+
+/* DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ * This raw interrupt bit turns to high level when level 1 fifo of Tx
+ * channel 1 is underflow.
+ */
+
+#define DMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(12))
+#define DMA_OUTFIFO_UDF_CH1_INT_RAW_M (DMA_OUTFIFO_UDF_CH1_INT_RAW_V << DMA_OUTFIFO_UDF_CH1_INT_RAW_S)
+#define DMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001
+#define DMA_OUTFIFO_UDF_CH1_INT_RAW_S 12
+
+/* DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ * This raw interrupt bit turns to high level when level 1 fifo of Tx
+ * channel 1 is overflow.
+ */
+
+#define DMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(11))
+#define DMA_OUTFIFO_OVF_CH1_INT_RAW_M (DMA_OUTFIFO_OVF_CH1_INT_RAW_V << DMA_OUTFIFO_OVF_CH1_INT_RAW_S)
+#define DMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001
+#define DMA_OUTFIFO_OVF_CH1_INT_RAW_S 11
+
+/* DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ * This raw interrupt bit turns to high level when level 1 fifo of Rx
+ * channel 1 is underflow.
+ */
+
+#define DMA_INFIFO_UDF_CH1_INT_RAW (BIT(10))
+#define DMA_INFIFO_UDF_CH1_INT_RAW_M (DMA_INFIFO_UDF_CH1_INT_RAW_V << DMA_INFIFO_UDF_CH1_INT_RAW_S)
+#define DMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001
+#define DMA_INFIFO_UDF_CH1_INT_RAW_S 10
+
+/* DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ * This raw interrupt bit turns to high level when level 1 fifo of Rx
+ * channel 1 is overflow.
+ */
+
+#define DMA_INFIFO_OVF_CH1_INT_RAW (BIT(9))
+#define DMA_INFIFO_OVF_CH1_INT_RAW_M (DMA_INFIFO_OVF_CH1_INT_RAW_V << DMA_INFIFO_OVF_CH1_INT_RAW_S)
+#define DMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001
+#define DMA_INFIFO_OVF_CH1_INT_RAW_S 9
+
+/* DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ * The raw interrupt bit turns to high level when data corresponding a
+ * outlink (includes one link descriptor or few link descriptors) is
+ * transmitted out for Tx channel 1.
+ */
+
+#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S)
+#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001
+#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 8
+
+/* DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ * The raw interrupt bit turns to high level when Rx buffer pointed by
+ * inlink is full and receiving data is not completed, but there is no more
+ * inlink for Rx channel 1.
+ */
+
+#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S)
+#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001
+#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 7
+
+/* DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ * The raw interrupt bit turns to high level when detecting outlink
+ * descriptor error, including owner error, the second and third word error
+ * of outlink descriptor for Tx channel 1.
+ */
+
+#define DMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_M (DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << DMA_OUT_DSCR_ERR_CH1_INT_RAW_S)
+#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001
+#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_S 6
+
+/* DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ * The raw interrupt bit turns to high level when detecting inlink
+ * descriptor error, including owner error, the second and third word error
+ * of inlink descriptor for Rx channel 1.
+ */
+
+#define DMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(5))
+#define DMA_IN_DSCR_ERR_CH1_INT_RAW_M (DMA_IN_DSCR_ERR_CH1_INT_RAW_V << DMA_IN_DSCR_ERR_CH1_INT_RAW_S)
+#define DMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001
+#define DMA_IN_DSCR_ERR_CH1_INT_RAW_S 5
+
+/* DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ * The raw interrupt bit turns to high level when the last data pointed by
+ * one outlink descriptor has been read from memory for Tx channel 1.
+ */
+
+#define DMA_OUT_EOF_CH1_INT_RAW (BIT(4))
+#define DMA_OUT_EOF_CH1_INT_RAW_M (DMA_OUT_EOF_CH1_INT_RAW_V << DMA_OUT_EOF_CH1_INT_RAW_S)
+#define DMA_OUT_EOF_CH1_INT_RAW_V 0x00000001
+#define DMA_OUT_EOF_CH1_INT_RAW_S 4
+
+/* DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ * The raw interrupt bit turns to high level when the last data pointed by
+ * one outlink descriptor has been transmitted to peripherals for Tx channel
+ * 1.
+ */
+
+#define DMA_OUT_DONE_CH1_INT_RAW (BIT(3))
+#define DMA_OUT_DONE_CH1_INT_RAW_M (DMA_OUT_DONE_CH1_INT_RAW_V << DMA_OUT_DONE_CH1_INT_RAW_S)
+#define DMA_OUT_DONE_CH1_INT_RAW_V 0x00000001
+#define DMA_OUT_DONE_CH1_INT_RAW_S 3
+
+/* DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ * The raw interrupt bit turns to high level when data error is detected
+ * only in the case that the peripheral is UHCI0 for Rx channel 1. For other
+ * peripherals, this raw interrupt is reserved.
+ */
+
+#define DMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2))
+#define DMA_IN_ERR_EOF_CH1_INT_RAW_M (DMA_IN_ERR_EOF_CH1_INT_RAW_V << DMA_IN_ERR_EOF_CH1_INT_RAW_S)
+#define DMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001
+#define DMA_IN_ERR_EOF_CH1_INT_RAW_S 2
+
+/* DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ * The raw interrupt bit turns to high level when the last data pointed by
+ * one inlink descriptor has been received for Rx channel 1. For UHCI0, the
+ * raw interrupt bit turns to high level when the last data pointed by one
+ * inlink descriptor has been received and no data error is detected for Rx
+ * channel 1.
+ */
+
+#define DMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1))
+#define DMA_IN_SUC_EOF_CH1_INT_RAW_M (DMA_IN_SUC_EOF_CH1_INT_RAW_V << DMA_IN_SUC_EOF_CH1_INT_RAW_S)
+#define DMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001
+#define DMA_IN_SUC_EOF_CH1_INT_RAW_S 1
+
+/* DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ * The raw interrupt bit turns to high level when the last data pointed by
+ * one inlink descriptor has been received for Rx channel 1.
+ */
+
+#define DMA_IN_DONE_CH1_INT_RAW (BIT(0))
+#define DMA_IN_DONE_CH1_INT_RAW_M (DMA_IN_DONE_CH1_INT_RAW_V << DMA_IN_DONE_CH1_INT_RAW_S)
+#define DMA_IN_DONE_CH1_INT_RAW_V 0x00000001
+#define DMA_IN_DONE_CH1_INT_RAW_S 0
+
+/* DMA_INT_ST_CH1_REG register
+ * DMA_INT_ST_CH1_REG.
+ */
+
+#define DMA_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x14)
+
+/* DMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [12]; default: 0;
+ * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_UDF_CH1_INT_ST (BIT(12))
+#define DMA_OUTFIFO_UDF_CH1_INT_ST_M (DMA_OUTFIFO_UDF_CH1_INT_ST_V << DMA_OUTFIFO_UDF_CH1_INT_ST_S)
+#define DMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001
+#define DMA_OUTFIFO_UDF_CH1_INT_ST_S 12
+
+/* DMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [11]; default: 0;
+ * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_OVF_CH1_INT_ST (BIT(11))
+#define DMA_OUTFIFO_OVF_CH1_INT_ST_M (DMA_OUTFIFO_OVF_CH1_INT_ST_V << DMA_OUTFIFO_OVF_CH1_INT_ST_S)
+#define DMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001
+#define DMA_OUTFIFO_OVF_CH1_INT_ST_S 11
+
+/* DMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_UDF_CH1_INT_ST (BIT(10))
+#define DMA_INFIFO_UDF_CH1_INT_ST_M (DMA_INFIFO_UDF_CH1_INT_ST_V << DMA_INFIFO_UDF_CH1_INT_ST_S)
+#define DMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001
+#define DMA_INFIFO_UDF_CH1_INT_ST_S 10
+
+/* DMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_OVF_CH1_INT_ST (BIT(9))
+#define DMA_INFIFO_OVF_CH1_INT_ST_M (DMA_INFIFO_OVF_CH1_INT_ST_V << DMA_INFIFO_OVF_CH1_INT_ST_S)
+#define DMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001
+#define DMA_INFIFO_OVF_CH1_INT_ST_S 9
+
+/* DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_M (DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << DMA_OUT_TOTAL_EOF_CH1_INT_ST_S)
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_S 8
+
+/* DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_M (DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << DMA_IN_DSCR_EMPTY_CH1_INT_ST_S)
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_S 7
+
+/* DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH1_INT_ST_M (DMA_OUT_DSCR_ERR_CH1_INT_ST_V << DMA_OUT_DSCR_ERR_CH1_INT_ST_S)
+#define DMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001
+#define DMA_OUT_DSCR_ERR_CH1_INT_ST_S 6
+
+/* DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_ERR_CH1_INT_ST (BIT(5))
+#define DMA_IN_DSCR_ERR_CH1_INT_ST_M (DMA_IN_DSCR_ERR_CH1_INT_ST_V << DMA_IN_DSCR_ERR_CH1_INT_ST_S)
+#define DMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001
+#define DMA_IN_DSCR_ERR_CH1_INT_ST_S 5
+
+/* DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_EOF_CH1_INT_ST (BIT(4))
+#define DMA_OUT_EOF_CH1_INT_ST_M (DMA_OUT_EOF_CH1_INT_ST_V << DMA_OUT_EOF_CH1_INT_ST_S)
+#define DMA_OUT_EOF_CH1_INT_ST_V 0x00000001
+#define DMA_OUT_EOF_CH1_INT_ST_S 4
+
+/* DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DONE_CH1_INT_ST (BIT(3))
+#define DMA_OUT_DONE_CH1_INT_ST_M (DMA_OUT_DONE_CH1_INT_ST_V << DMA_OUT_DONE_CH1_INT_ST_S)
+#define DMA_OUT_DONE_CH1_INT_ST_V 0x00000001
+#define DMA_OUT_DONE_CH1_INT_ST_S 3
+
+/* DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_ERR_EOF_CH1_INT_ST (BIT(2))
+#define DMA_IN_ERR_EOF_CH1_INT_ST_M (DMA_IN_ERR_EOF_CH1_INT_ST_V << DMA_IN_ERR_EOF_CH1_INT_ST_S)
+#define DMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001
+#define DMA_IN_ERR_EOF_CH1_INT_ST_S 2
+
+/* DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_SUC_EOF_CH1_INT_ST (BIT(1))
+#define DMA_IN_SUC_EOF_CH1_INT_ST_M (DMA_IN_SUC_EOF_CH1_INT_ST_V << DMA_IN_SUC_EOF_CH1_INT_ST_S)
+#define DMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001
+#define DMA_IN_SUC_EOF_CH1_INT_ST_S 1
+
+/* DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ * The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+
+#define DMA_IN_DONE_CH1_INT_ST (BIT(0))
+#define DMA_IN_DONE_CH1_INT_ST_M (DMA_IN_DONE_CH1_INT_ST_V << DMA_IN_DONE_CH1_INT_ST_S)
+#define DMA_IN_DONE_CH1_INT_ST_V 0x00000001
+#define DMA_IN_DONE_CH1_INT_ST_S 0
+
+/* DMA_INT_ENA_CH1_REG register
+ * DMA_INT_ENA_CH1_REG.
+ */
+
+#define DMA_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x18)
+
+/* DMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0;
+ * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(12))
+#define DMA_OUTFIFO_UDF_CH1_INT_ENA_M (DMA_OUTFIFO_UDF_CH1_INT_ENA_V << DMA_OUTFIFO_UDF_CH1_INT_ENA_S)
+#define DMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001
+#define DMA_OUTFIFO_UDF_CH1_INT_ENA_S 12
+
+/* DMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(11))
+#define DMA_OUTFIFO_OVF_CH1_INT_ENA_M (DMA_OUTFIFO_OVF_CH1_INT_ENA_V << DMA_OUTFIFO_OVF_CH1_INT_ENA_S)
+#define DMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001
+#define DMA_OUTFIFO_OVF_CH1_INT_ENA_S 11
+
+/* DMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_UDF_CH1_INT_ENA (BIT(10))
+#define DMA_INFIFO_UDF_CH1_INT_ENA_M (DMA_INFIFO_UDF_CH1_INT_ENA_V << DMA_INFIFO_UDF_CH1_INT_ENA_S)
+#define DMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001
+#define DMA_INFIFO_UDF_CH1_INT_ENA_S 10
+
+/* DMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_OVF_CH1_INT_ENA (BIT(9))
+#define DMA_INFIFO_OVF_CH1_INT_ENA_M (DMA_INFIFO_OVF_CH1_INT_ENA_V << DMA_INFIFO_OVF_CH1_INT_ENA_S)
+#define DMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001
+#define DMA_INFIFO_OVF_CH1_INT_ENA_S 9
+
+/* DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S)
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 8
+
+/* DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S)
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 7
+
+/* DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_M (DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << DMA_OUT_DSCR_ERR_CH1_INT_ENA_S)
+#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001
+#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_S 6
+
+/* DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(5))
+#define DMA_IN_DSCR_ERR_CH1_INT_ENA_M (DMA_IN_DSCR_ERR_CH1_INT_ENA_V << DMA_IN_DSCR_ERR_CH1_INT_ENA_S)
+#define DMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001
+#define DMA_IN_DSCR_ERR_CH1_INT_ENA_S 5
+
+/* DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ * The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_EOF_CH1_INT_ENA (BIT(4))
+#define DMA_OUT_EOF_CH1_INT_ENA_M (DMA_OUT_EOF_CH1_INT_ENA_V << DMA_OUT_EOF_CH1_INT_ENA_S)
+#define DMA_OUT_EOF_CH1_INT_ENA_V 0x00000001
+#define DMA_OUT_EOF_CH1_INT_ENA_S 4
+
+/* DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ * The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DONE_CH1_INT_ENA (BIT(3))
+#define DMA_OUT_DONE_CH1_INT_ENA_M (DMA_OUT_DONE_CH1_INT_ENA_V << DMA_OUT_DONE_CH1_INT_ENA_S)
+#define DMA_OUT_DONE_CH1_INT_ENA_V 0x00000001
+#define DMA_OUT_DONE_CH1_INT_ENA_S 3
+
+/* DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2))
+#define DMA_IN_ERR_EOF_CH1_INT_ENA_M (DMA_IN_ERR_EOF_CH1_INT_ENA_V << DMA_IN_ERR_EOF_CH1_INT_ENA_S)
+#define DMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001
+#define DMA_IN_ERR_EOF_CH1_INT_ENA_S 2
+
+/* DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1))
+#define DMA_IN_SUC_EOF_CH1_INT_ENA_M (DMA_IN_SUC_EOF_CH1_INT_ENA_V << DMA_IN_SUC_EOF_CH1_INT_ENA_S)
+#define DMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001
+#define DMA_IN_SUC_EOF_CH1_INT_ENA_S 1
+
+/* DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ * The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+
+#define DMA_IN_DONE_CH1_INT_ENA (BIT(0))
+#define DMA_IN_DONE_CH1_INT_ENA_M (DMA_IN_DONE_CH1_INT_ENA_V << DMA_IN_DONE_CH1_INT_ENA_S)
+#define DMA_IN_DONE_CH1_INT_ENA_V 0x00000001
+#define DMA_IN_DONE_CH1_INT_ENA_S 0
+
+/* DMA_INT_CLR_CH1_REG register
+ * DMA_INT_CLR_CH1_REG.
+ */
+
+#define DMA_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x1c)
+
+/* DMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [12]; default: 0;
+ * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(12))
+#define DMA_OUTFIFO_UDF_CH1_INT_CLR_M (DMA_OUTFIFO_UDF_CH1_INT_CLR_V << DMA_OUTFIFO_UDF_CH1_INT_CLR_S)
+#define DMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001
+#define DMA_OUTFIFO_UDF_CH1_INT_CLR_S 12
+
+/* DMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [11]; default: 0;
+ * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(11))
+#define DMA_OUTFIFO_OVF_CH1_INT_CLR_M (DMA_OUTFIFO_OVF_CH1_INT_CLR_V << DMA_OUTFIFO_OVF_CH1_INT_CLR_S)
+#define DMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001
+#define DMA_OUTFIFO_OVF_CH1_INT_CLR_S 11
+
+/* DMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_UDF_CH1_INT_CLR (BIT(10))
+#define DMA_INFIFO_UDF_CH1_INT_CLR_M (DMA_INFIFO_UDF_CH1_INT_CLR_V << DMA_INFIFO_UDF_CH1_INT_CLR_S)
+#define DMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001
+#define DMA_INFIFO_UDF_CH1_INT_CLR_S 10
+
+/* DMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_OVF_CH1_INT_CLR (BIT(9))
+#define DMA_INFIFO_OVF_CH1_INT_CLR_M (DMA_INFIFO_OVF_CH1_INT_CLR_V << DMA_INFIFO_OVF_CH1_INT_CLR_S)
+#define DMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001
+#define DMA_INFIFO_OVF_CH1_INT_CLR_S 9
+
+/* DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S)
+#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001
+#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 8
+
+/* DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S)
+#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001
+#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 7
+
+/* DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_M (DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << DMA_OUT_DSCR_ERR_CH1_INT_CLR_S)
+#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001
+#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_S 6
+
+/* DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(5))
+#define DMA_IN_DSCR_ERR_CH1_INT_CLR_M (DMA_IN_DSCR_ERR_CH1_INT_CLR_V << DMA_IN_DSCR_ERR_CH1_INT_CLR_S)
+#define DMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001
+#define DMA_IN_DSCR_ERR_CH1_INT_CLR_S 5
+
+/* DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ * Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_EOF_CH1_INT_CLR (BIT(4))
+#define DMA_OUT_EOF_CH1_INT_CLR_M (DMA_OUT_EOF_CH1_INT_CLR_V << DMA_OUT_EOF_CH1_INT_CLR_S)
+#define DMA_OUT_EOF_CH1_INT_CLR_V 0x00000001
+#define DMA_OUT_EOF_CH1_INT_CLR_S 4
+
+/* DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ * Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DONE_CH1_INT_CLR (BIT(3))
+#define DMA_OUT_DONE_CH1_INT_CLR_M (DMA_OUT_DONE_CH1_INT_CLR_V << DMA_OUT_DONE_CH1_INT_CLR_S)
+#define DMA_OUT_DONE_CH1_INT_CLR_V 0x00000001
+#define DMA_OUT_DONE_CH1_INT_CLR_S 3
+
+/* DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2))
+#define DMA_IN_ERR_EOF_CH1_INT_CLR_M (DMA_IN_ERR_EOF_CH1_INT_CLR_V << DMA_IN_ERR_EOF_CH1_INT_CLR_S)
+#define DMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001
+#define DMA_IN_ERR_EOF_CH1_INT_CLR_S 2
+
+/* DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1))
+#define DMA_IN_SUC_EOF_CH1_INT_CLR_M (DMA_IN_SUC_EOF_CH1_INT_CLR_V << DMA_IN_SUC_EOF_CH1_INT_CLR_S)
+#define DMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001
+#define DMA_IN_SUC_EOF_CH1_INT_CLR_S 1
+
+/* DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ * Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+
+#define DMA_IN_DONE_CH1_INT_CLR (BIT(0))
+#define DMA_IN_DONE_CH1_INT_CLR_M (DMA_IN_DONE_CH1_INT_CLR_V << DMA_IN_DONE_CH1_INT_CLR_S)
+#define DMA_IN_DONE_CH1_INT_CLR_V 0x00000001
+#define DMA_IN_DONE_CH1_INT_CLR_S 0
+
+/* DMA_INT_RAW_CH2_REG register
+ * DMA_INT_RAW_CH2_REG.
+ */
+
+#define DMA_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x20)
+
+/* DMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ * This raw interrupt bit turns to high level when level 1 fifo of Tx
+ * channel 2 is underflow.
+ */
+
+#define DMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(12))
+#define DMA_OUTFIFO_UDF_CH2_INT_RAW_M (DMA_OUTFIFO_UDF_CH2_INT_RAW_V << DMA_OUTFIFO_UDF_CH2_INT_RAW_S)
+#define DMA_OUTFIFO_UDF_CH2_INT_RAW_V 0x00000001
+#define DMA_OUTFIFO_UDF_CH2_INT_RAW_S 12
+
+/* DMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ * This raw interrupt bit turns to high level when level 1 fifo of Tx
+ * channel 2 is overflow.
+ */
+
+#define DMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(11))
+#define DMA_OUTFIFO_OVF_CH2_INT_RAW_M (DMA_OUTFIFO_OVF_CH2_INT_RAW_V << DMA_OUTFIFO_OVF_CH2_INT_RAW_S)
+#define DMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x00000001
+#define DMA_OUTFIFO_OVF_CH2_INT_RAW_S 11
+
+/* DMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ * This raw interrupt bit turns to high level when level 1 fifo of Rx
+ * channel 2 is underflow.
+ */
+
+#define DMA_INFIFO_UDF_CH2_INT_RAW (BIT(10))
+#define DMA_INFIFO_UDF_CH2_INT_RAW_M (DMA_INFIFO_UDF_CH2_INT_RAW_V << DMA_INFIFO_UDF_CH2_INT_RAW_S)
+#define DMA_INFIFO_UDF_CH2_INT_RAW_V 0x00000001
+#define DMA_INFIFO_UDF_CH2_INT_RAW_S 10
+
+/* DMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ * This raw interrupt bit turns to high level when level 1 fifo of Rx
+ * channel 2 is overflow.
+ */
+
+#define DMA_INFIFO_OVF_CH2_INT_RAW (BIT(9))
+#define DMA_INFIFO_OVF_CH2_INT_RAW_M (DMA_INFIFO_OVF_CH2_INT_RAW_V << DMA_INFIFO_OVF_CH2_INT_RAW_S)
+#define DMA_INFIFO_OVF_CH2_INT_RAW_V 0x00000001
+#define DMA_INFIFO_OVF_CH2_INT_RAW_S 9
+
+/* DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ * The raw interrupt bit turns to high level when data corresponding a
+ * outlink (includes one link descriptor or few link descriptors) is
+ * transmitted out for Tx channel 2.
+ */
+
+#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S)
+#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001
+#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 8
+
+/* DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ * The raw interrupt bit turns to high level when Rx buffer pointed by
+ * inlink is full and receiving data is not completed, but there is no more
+ * inlink for Rx channel 2.
+ */
+
+#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S)
+#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001
+#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 7
+
+/* DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ * The raw interrupt bit turns to high level when detecting outlink
+ * descriptor error, including owner error, the second and third word error
+ * of outlink descriptor for Tx channel 2.
+ */
+
+#define DMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_M (DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << DMA_OUT_DSCR_ERR_CH2_INT_RAW_S)
+#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001
+#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_S 6
+
+/* DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ * The raw interrupt bit turns to high level when detecting inlink
+ * descriptor error, including owner error, the second and third word error
+ * of inlink descriptor for Rx channel 2.
+ */
+
+#define DMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(5))
+#define DMA_IN_DSCR_ERR_CH2_INT_RAW_M (DMA_IN_DSCR_ERR_CH2_INT_RAW_V << DMA_IN_DSCR_ERR_CH2_INT_RAW_S)
+#define DMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001
+#define DMA_IN_DSCR_ERR_CH2_INT_RAW_S 5
+
+/* DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ * The raw interrupt bit turns to high level when the last data pointed by
+ * one outlink descriptor has been read from memory for Tx channel 2.
+ */
+
+#define DMA_OUT_EOF_CH2_INT_RAW (BIT(4))
+#define DMA_OUT_EOF_CH2_INT_RAW_M (DMA_OUT_EOF_CH2_INT_RAW_V << DMA_OUT_EOF_CH2_INT_RAW_S)
+#define DMA_OUT_EOF_CH2_INT_RAW_V 0x00000001
+#define DMA_OUT_EOF_CH2_INT_RAW_S 4
+
+/* DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ * The raw interrupt bit turns to high level when the last data pointed by
+ * one outlink descriptor has been transmitted to peripherals for Tx channel
+ * 2.
+ */
+
+#define DMA_OUT_DONE_CH2_INT_RAW (BIT(3))
+#define DMA_OUT_DONE_CH2_INT_RAW_M (DMA_OUT_DONE_CH2_INT_RAW_V << DMA_OUT_DONE_CH2_INT_RAW_S)
+#define DMA_OUT_DONE_CH2_INT_RAW_V 0x00000001
+#define DMA_OUT_DONE_CH2_INT_RAW_S 3
+
+/* DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ * The raw interrupt bit turns to high level when data error is detected
+ * only in the case that the peripheral is UHCI0 for Rx channel 2. For other
+ * peripherals, this raw interrupt is reserved.
+ */
+
+#define DMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2))
+#define DMA_IN_ERR_EOF_CH2_INT_RAW_M (DMA_IN_ERR_EOF_CH2_INT_RAW_V << DMA_IN_ERR_EOF_CH2_INT_RAW_S)
+#define DMA_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001
+#define DMA_IN_ERR_EOF_CH2_INT_RAW_S 2
+
+/* DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ * The raw interrupt bit turns to high level when the last data pointed by
+ * one inlink descriptor has been received for Rx channel 2. For UHCI0, the
+ * raw interrupt bit turns to high level when the last data pointed by one
+ * inlink descriptor has been received and no data error is detected for Rx
+ * channel 2.
+ */
+
+#define DMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1))
+#define DMA_IN_SUC_EOF_CH2_INT_RAW_M (DMA_IN_SUC_EOF_CH2_INT_RAW_V << DMA_IN_SUC_EOF_CH2_INT_RAW_S)
+#define DMA_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001
+#define DMA_IN_SUC_EOF_CH2_INT_RAW_S 1
+
+/* DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ * The raw interrupt bit turns to high level when the last data pointed by
+ * one inlink descriptor has been received for Rx channel 2.
+ */
+
+#define DMA_IN_DONE_CH2_INT_RAW (BIT(0))
+#define DMA_IN_DONE_CH2_INT_RAW_M (DMA_IN_DONE_CH2_INT_RAW_V << DMA_IN_DONE_CH2_INT_RAW_S)
+#define DMA_IN_DONE_CH2_INT_RAW_V 0x00000001
+#define DMA_IN_DONE_CH2_INT_RAW_S 0
+
+/* DMA_INT_ST_CH2_REG register
+ * DMA_INT_ST_CH2_REG.
+ */
+
+#define DMA_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x24)
+
+/* DMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [12]; default: 0;
+ * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_UDF_CH2_INT_ST (BIT(12))
+#define DMA_OUTFIFO_UDF_CH2_INT_ST_M (DMA_OUTFIFO_UDF_CH2_INT_ST_V << DMA_OUTFIFO_UDF_CH2_INT_ST_S)
+#define DMA_OUTFIFO_UDF_CH2_INT_ST_V 0x00000001
+#define DMA_OUTFIFO_UDF_CH2_INT_ST_S 12
+
+/* DMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [11]; default: 0;
+ * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_OVF_CH2_INT_ST (BIT(11))
+#define DMA_OUTFIFO_OVF_CH2_INT_ST_M (DMA_OUTFIFO_OVF_CH2_INT_ST_V << DMA_OUTFIFO_OVF_CH2_INT_ST_S)
+#define DMA_OUTFIFO_OVF_CH2_INT_ST_V 0x00000001
+#define DMA_OUTFIFO_OVF_CH2_INT_ST_S 11
+
+/* DMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [10]; default: 0;
+ * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_UDF_CH2_INT_ST (BIT(10))
+#define DMA_INFIFO_UDF_CH2_INT_ST_M (DMA_INFIFO_UDF_CH2_INT_ST_V << DMA_INFIFO_UDF_CH2_INT_ST_S)
+#define DMA_INFIFO_UDF_CH2_INT_ST_V 0x00000001
+#define DMA_INFIFO_UDF_CH2_INT_ST_S 10
+
+/* DMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_OVF_CH2_INT_ST (BIT(9))
+#define DMA_INFIFO_OVF_CH2_INT_ST_M (DMA_INFIFO_OVF_CH2_INT_ST_V << DMA_INFIFO_OVF_CH2_INT_ST_S)
+#define DMA_INFIFO_OVF_CH2_INT_ST_V 0x00000001
+#define DMA_INFIFO_OVF_CH2_INT_ST_S 9
+
+/* DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_M (DMA_OUT_TOTAL_EOF_CH2_INT_ST_V << DMA_OUT_TOTAL_EOF_CH2_INT_ST_S)
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_S 8
+
+/* DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_M (DMA_IN_DSCR_EMPTY_CH2_INT_ST_V << DMA_IN_DSCR_EMPTY_CH2_INT_ST_S)
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_S 7
+
+/* DMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH2_INT_ST_M (DMA_OUT_DSCR_ERR_CH2_INT_ST_V << DMA_OUT_DSCR_ERR_CH2_INT_ST_S)
+#define DMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001
+#define DMA_OUT_DSCR_ERR_CH2_INT_ST_S 6
+
+/* DMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_ERR_CH2_INT_ST (BIT(5))
+#define DMA_IN_DSCR_ERR_CH2_INT_ST_M (DMA_IN_DSCR_ERR_CH2_INT_ST_V << DMA_IN_DSCR_ERR_CH2_INT_ST_S)
+#define DMA_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001
+#define DMA_IN_DSCR_ERR_CH2_INT_ST_S 5
+
+/* DMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_EOF_CH2_INT_ST (BIT(4))
+#define DMA_OUT_EOF_CH2_INT_ST_M (DMA_OUT_EOF_CH2_INT_ST_V << DMA_OUT_EOF_CH2_INT_ST_S)
+#define DMA_OUT_EOF_CH2_INT_ST_V 0x00000001
+#define DMA_OUT_EOF_CH2_INT_ST_S 4
+
+/* DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DONE_CH2_INT_ST (BIT(3))
+#define DMA_OUT_DONE_CH2_INT_ST_M (DMA_OUT_DONE_CH2_INT_ST_V << DMA_OUT_DONE_CH2_INT_ST_S)
+#define DMA_OUT_DONE_CH2_INT_ST_V 0x00000001
+#define DMA_OUT_DONE_CH2_INT_ST_S 3
+
+/* DMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_ERR_EOF_CH2_INT_ST (BIT(2))
+#define DMA_IN_ERR_EOF_CH2_INT_ST_M (DMA_IN_ERR_EOF_CH2_INT_ST_V << DMA_IN_ERR_EOF_CH2_INT_ST_S)
+#define DMA_IN_ERR_EOF_CH2_INT_ST_V 0x00000001
+#define DMA_IN_ERR_EOF_CH2_INT_ST_S 2
+
+/* DMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_SUC_EOF_CH2_INT_ST (BIT(1))
+#define DMA_IN_SUC_EOF_CH2_INT_ST_M (DMA_IN_SUC_EOF_CH2_INT_ST_V << DMA_IN_SUC_EOF_CH2_INT_ST_S)
+#define DMA_IN_SUC_EOF_CH2_INT_ST_V 0x00000001
+#define DMA_IN_SUC_EOF_CH2_INT_ST_S 1
+
+/* DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ * The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+
+#define DMA_IN_DONE_CH2_INT_ST (BIT(0))
+#define DMA_IN_DONE_CH2_INT_ST_M (DMA_IN_DONE_CH2_INT_ST_V << DMA_IN_DONE_CH2_INT_ST_S)
+#define DMA_IN_DONE_CH2_INT_ST_V 0x00000001
+#define DMA_IN_DONE_CH2_INT_ST_S 0
+
+/* DMA_INT_ENA_CH2_REG register
+ * DMA_INT_ENA_CH2_REG.
+ */
+
+#define DMA_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x28)
+
+/* DMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0;
+ * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_UDF_CH2_INT_ENA (BIT(12))
+#define DMA_OUTFIFO_UDF_CH2_INT_ENA_M (DMA_OUTFIFO_UDF_CH2_INT_ENA_V << DMA_OUTFIFO_UDF_CH2_INT_ENA_S)
+#define DMA_OUTFIFO_UDF_CH2_INT_ENA_V 0x00000001
+#define DMA_OUTFIFO_UDF_CH2_INT_ENA_S 12
+
+/* DMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0;
+ * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_OVF_CH2_INT_ENA (BIT(11))
+#define DMA_OUTFIFO_OVF_CH2_INT_ENA_M (DMA_OUTFIFO_OVF_CH2_INT_ENA_V << DMA_OUTFIFO_OVF_CH2_INT_ENA_S)
+#define DMA_OUTFIFO_OVF_CH2_INT_ENA_V 0x00000001
+#define DMA_OUTFIFO_OVF_CH2_INT_ENA_S 11
+
+/* DMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [10]; default: 0;
+ * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_UDF_CH2_INT_ENA (BIT(10))
+#define DMA_INFIFO_UDF_CH2_INT_ENA_M (DMA_INFIFO_UDF_CH2_INT_ENA_V << DMA_INFIFO_UDF_CH2_INT_ENA_S)
+#define DMA_INFIFO_UDF_CH2_INT_ENA_V 0x00000001
+#define DMA_INFIFO_UDF_CH2_INT_ENA_S 10
+
+/* DMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_OVF_CH2_INT_ENA (BIT(9))
+#define DMA_INFIFO_OVF_CH2_INT_ENA_M (DMA_INFIFO_OVF_CH2_INT_ENA_V << DMA_INFIFO_OVF_CH2_INT_ENA_S)
+#define DMA_INFIFO_OVF_CH2_INT_ENA_V 0x00000001
+#define DMA_INFIFO_OVF_CH2_INT_ENA_S 9
+
+/* DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S)
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 8
+
+/* DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S)
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 7
+
+/* DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_M (DMA_OUT_DSCR_ERR_CH2_INT_ENA_V << DMA_OUT_DSCR_ERR_CH2_INT_ENA_S)
+#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001
+#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_S 6
+
+/* DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(5))
+#define DMA_IN_DSCR_ERR_CH2_INT_ENA_M (DMA_IN_DSCR_ERR_CH2_INT_ENA_V << DMA_IN_DSCR_ERR_CH2_INT_ENA_S)
+#define DMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001
+#define DMA_IN_DSCR_ERR_CH2_INT_ENA_S 5
+
+/* DMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ * The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_EOF_CH2_INT_ENA (BIT(4))
+#define DMA_OUT_EOF_CH2_INT_ENA_M (DMA_OUT_EOF_CH2_INT_ENA_V << DMA_OUT_EOF_CH2_INT_ENA_S)
+#define DMA_OUT_EOF_CH2_INT_ENA_V 0x00000001
+#define DMA_OUT_EOF_CH2_INT_ENA_S 4
+
+/* DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ * The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DONE_CH2_INT_ENA (BIT(3))
+#define DMA_OUT_DONE_CH2_INT_ENA_M (DMA_OUT_DONE_CH2_INT_ENA_V << DMA_OUT_DONE_CH2_INT_ENA_S)
+#define DMA_OUT_DONE_CH2_INT_ENA_V 0x00000001
+#define DMA_OUT_DONE_CH2_INT_ENA_S 3
+
+/* DMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2))
+#define DMA_IN_ERR_EOF_CH2_INT_ENA_M (DMA_IN_ERR_EOF_CH2_INT_ENA_V << DMA_IN_ERR_EOF_CH2_INT_ENA_S)
+#define DMA_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001
+#define DMA_IN_ERR_EOF_CH2_INT_ENA_S 2
+
+/* DMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1))
+#define DMA_IN_SUC_EOF_CH2_INT_ENA_M (DMA_IN_SUC_EOF_CH2_INT_ENA_V << DMA_IN_SUC_EOF_CH2_INT_ENA_S)
+#define DMA_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001
+#define DMA_IN_SUC_EOF_CH2_INT_ENA_S 1
+
+/* DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ * The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+
+#define DMA_IN_DONE_CH2_INT_ENA (BIT(0))
+#define DMA_IN_DONE_CH2_INT_ENA_M (DMA_IN_DONE_CH2_INT_ENA_V << DMA_IN_DONE_CH2_INT_ENA_S)
+#define DMA_IN_DONE_CH2_INT_ENA_V 0x00000001
+#define DMA_IN_DONE_CH2_INT_ENA_S 0
+
+/* DMA_INT_CLR_CH2_REG register
+ * DMA_INT_CLR_CH2_REG.
+ */
+
+#define DMA_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x2c)
+
+/* DMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [12]; default: 0;
+ * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_UDF_CH2_INT_CLR (BIT(12))
+#define DMA_OUTFIFO_UDF_CH2_INT_CLR_M (DMA_OUTFIFO_UDF_CH2_INT_CLR_V << DMA_OUTFIFO_UDF_CH2_INT_CLR_S)
+#define DMA_OUTFIFO_UDF_CH2_INT_CLR_V 0x00000001
+#define DMA_OUTFIFO_UDF_CH2_INT_CLR_S 12
+
+/* DMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [11]; default: 0;
+ * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_OUTFIFO_OVF_CH2_INT_CLR (BIT(11))
+#define DMA_OUTFIFO_OVF_CH2_INT_CLR_M (DMA_OUTFIFO_OVF_CH2_INT_CLR_V << DMA_OUTFIFO_OVF_CH2_INT_CLR_S)
+#define DMA_OUTFIFO_OVF_CH2_INT_CLR_V 0x00000001
+#define DMA_OUTFIFO_OVF_CH2_INT_CLR_S 11
+
+/* DMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [10]; default: 0;
+ * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_UDF_CH2_INT_CLR (BIT(10))
+#define DMA_INFIFO_UDF_CH2_INT_CLR_M (DMA_INFIFO_UDF_CH2_INT_CLR_V << DMA_INFIFO_UDF_CH2_INT_CLR_S)
+#define DMA_INFIFO_UDF_CH2_INT_CLR_V 0x00000001
+#define DMA_INFIFO_UDF_CH2_INT_CLR_S 10
+
+/* DMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+
+#define DMA_INFIFO_OVF_CH2_INT_CLR (BIT(9))
+#define DMA_INFIFO_OVF_CH2_INT_CLR_M (DMA_INFIFO_OVF_CH2_INT_CLR_V << DMA_INFIFO_OVF_CH2_INT_CLR_S)
+#define DMA_INFIFO_OVF_CH2_INT_CLR_V 0x00000001
+#define DMA_INFIFO_OVF_CH2_INT_CLR_S 9
+
+/* DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S)
+#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001
+#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 8
+
+/* DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S)
+#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001
+#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 7
+
+/* DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_M (DMA_OUT_DSCR_ERR_CH2_INT_CLR_V << DMA_OUT_DSCR_ERR_CH2_INT_CLR_S)
+#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001
+#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_S 6
+
+/* DMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+ */
+
+#define DMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(5))
+#define DMA_IN_DSCR_ERR_CH2_INT_CLR_M (DMA_IN_DSCR_ERR_CH2_INT_CLR_V << DMA_IN_DSCR_ERR_CH2_INT_CLR_S)
+#define DMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001
+#define DMA_IN_DSCR_ERR_CH2_INT_CLR_S 5
+
+/* DMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ * Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+
+#define DMA_OUT_EOF_CH2_INT_CLR (BIT(4))
+#define DMA_OUT_EOF_CH2_INT_CLR_M (DMA_OUT_EOF_CH2_INT_CLR_V << DMA_OUT_EOF_CH2_INT_CLR_S)
+#define DMA_OUT_EOF_CH2_INT_CLR_V 0x00000001
+#define DMA_OUT_EOF_CH2_INT_CLR_S 4
+
+/* DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ * Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+
+#define DMA_OUT_DONE_CH2_INT_CLR (BIT(3))
+#define DMA_OUT_DONE_CH2_INT_CLR_M (DMA_OUT_DONE_CH2_INT_CLR_V << DMA_OUT_DONE_CH2_INT_CLR_S)
+#define DMA_OUT_DONE_CH2_INT_CLR_V 0x00000001
+#define DMA_OUT_DONE_CH2_INT_CLR_S 3
+
+/* DMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2))
+#define DMA_IN_ERR_EOF_CH2_INT_CLR_M (DMA_IN_ERR_EOF_CH2_INT_CLR_V << DMA_IN_ERR_EOF_CH2_INT_CLR_S)
+#define DMA_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001
+#define DMA_IN_ERR_EOF_CH2_INT_CLR_S 2
+
+/* DMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+
+#define DMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1))
+#define DMA_IN_SUC_EOF_CH2_INT_CLR_M (DMA_IN_SUC_EOF_CH2_INT_CLR_V << DMA_IN_SUC_EOF_CH2_INT_CLR_S)
+#define DMA_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001
+#define DMA_IN_SUC_EOF_CH2_INT_CLR_S 1
+
+/* DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ * Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+
+#define DMA_IN_DONE_CH2_INT_CLR (BIT(0))
+#define DMA_IN_DONE_CH2_INT_CLR_M (DMA_IN_DONE_CH2_INT_CLR_V << DMA_IN_DONE_CH2_INT_CLR_S)
+#define DMA_IN_DONE_CH2_INT_CLR_V 0x00000001
+#define DMA_IN_DONE_CH2_INT_CLR_S 0
+
+/* DMA_AHB_TEST_REG register
+ * DMA_AHB_TEST_REG.
+ */
+
+#define DMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x40)
+
+/* DMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0;
+ * reserved
+ */
+
+#define DMA_AHB_TESTADDR 0x00000003
+#define DMA_AHB_TESTADDR_M (DMA_AHB_TESTADDR_V << DMA_AHB_TESTADDR_S)
+#define DMA_AHB_TESTADDR_V 0x00000003
+#define DMA_AHB_TESTADDR_S 4
+
+/* DMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0;
+ * reserved
+ */
+
+#define DMA_AHB_TESTMODE 0x00000007
+#define DMA_AHB_TESTMODE_M (DMA_AHB_TESTMODE_V << DMA_AHB_TESTMODE_S)
+#define DMA_AHB_TESTMODE_V 0x00000007
+#define DMA_AHB_TESTMODE_S 0
+
+/* DMA_MISC_CONF_REG register
+ * DMA_MISC_CONF_REG.
+ */
+
+#define DMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x44)
+
+/* DMA_CLK_EN : R/W; bitpos: [3]; default: 0;
+ * reg_clk_en
+ */
+
+#define DMA_CLK_EN (BIT(3))
+#define DMA_CLK_EN_M (DMA_CLK_EN_V << DMA_CLK_EN_S)
+#define DMA_CLK_EN_V 0x00000001
+#define DMA_CLK_EN_S 3
+
+/* DMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0;
+ * Set this bit to disable priority arbitration function.
+ */
+
+#define DMA_ARB_PRI_DIS (BIT(2))
+#define DMA_ARB_PRI_DIS_M (DMA_ARB_PRI_DIS_V << DMA_ARB_PRI_DIS_S)
+#define DMA_ARB_PRI_DIS_V 0x00000001
+#define DMA_ARB_PRI_DIS_S 2
+
+/* DMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0;
+ * Set this bit, then clear this bit to reset the internal ahb FSM.
+ */
+
+#define DMA_AHBM_RST_INTER (BIT(0))
+#define DMA_AHBM_RST_INTER_M (DMA_AHBM_RST_INTER_V << DMA_AHBM_RST_INTER_S)
+#define DMA_AHBM_RST_INTER_V 0x00000001
+#define DMA_AHBM_RST_INTER_S 0
+
+/* DMA_DATE_REG register
+ * DMA_DATE_REG.
+ */
+
+#define DMA_DATE_REG (DR_REG_GDMA_BASE + 0x48)
+
+/* DMA_DATE : R/W; bitpos: [31:0]; default: 33587792;
+ * register version.
+ */
+
+#define DMA_DATE 0xFFFFFFFF
+#define DMA_DATE_M (DMA_DATE_V << DMA_DATE_S)
+#define DMA_DATE_V 0xFFFFFFFF
+#define DMA_DATE_S 0
+
+/* DMA_IN_CONF0_CH0_REG register
+ * DMA_IN_CONF0_CH0_REG.
+ */
+
+#define DMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x70)
+
+/* DMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0;
+ * Set this bit 1 to enable automatic transmitting data from memory to
+ * memory via DMA.
+ */
+
+#define DMA_MEM_TRANS_EN_CH0 (BIT(4))
+#define DMA_MEM_TRANS_EN_CH0_M (DMA_MEM_TRANS_EN_CH0_V << DMA_MEM_TRANS_EN_CH0_S)
+#define DMA_MEM_TRANS_EN_CH0_V 0x00000001
+#define DMA_MEM_TRANS_EN_CH0_S 4
+
+/* DMA_IN_DATA_BURST_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ * Set this bit to 1 to enable INCR burst transfer for Rx channel 0
+ * receiving data when accessing internal SRAM.
+ */
+
+#define DMA_IN_DATA_BURST_EN_CH0 (BIT(3))
+#define DMA_IN_DATA_BURST_EN_CH0_M (DMA_IN_DATA_BURST_EN_CH0_V << DMA_IN_DATA_BURST_EN_CH0_S)
+#define DMA_IN_DATA_BURST_EN_CH0_V 0x00000001
+#define DMA_IN_DATA_BURST_EN_CH0_S 3
+
+/* DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading
+ * link descriptor when accessing internal SRAM.
+ */
+
+#define DMA_INDSCR_BURST_EN_CH0 (BIT(2))
+#define DMA_INDSCR_BURST_EN_CH0_M (DMA_INDSCR_BURST_EN_CH0_V << DMA_INDSCR_BURST_EN_CH0_S)
+#define DMA_INDSCR_BURST_EN_CH0_V 0x00000001
+#define DMA_INDSCR_BURST_EN_CH0_S 2
+
+/* DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ * reserved
+ */
+
+#define DMA_IN_LOOP_TEST_CH0 (BIT(1))
+#define DMA_IN_LOOP_TEST_CH0_M (DMA_IN_LOOP_TEST_CH0_V << DMA_IN_LOOP_TEST_CH0_S)
+#define DMA_IN_LOOP_TEST_CH0_V 0x00000001
+#define DMA_IN_LOOP_TEST_CH0_S 1
+
+/* DMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ * This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.
+ */
+
+#define DMA_IN_RST_CH0 (BIT(0))
+#define DMA_IN_RST_CH0_M (DMA_IN_RST_CH0_V << DMA_IN_RST_CH0_S)
+#define DMA_IN_RST_CH0_V 0x00000001
+#define DMA_IN_RST_CH0_S 0
+
+/* DMA_IN_CONF1_CH0_REG register
+ * DMA_IN_CONF1_CH0_REG.
+ */
+
+#define DMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x74)
+
+/* DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ * Set this bit to enable checking the owner attribute of the link
+ * descriptor.
+ */
+
+#define DMA_IN_CHECK_OWNER_CH0 (BIT(12))
+#define DMA_IN_CHECK_OWNER_CH0_M (DMA_IN_CHECK_OWNER_CH0_V << DMA_IN_CHECK_OWNER_CH0_S)
+#define DMA_IN_CHECK_OWNER_CH0_V 0x00000001
+#define DMA_IN_CHECK_OWNER_CH0_S 12
+
+/* DMA_INFIFO_STATUS_CH0_REG register
+ * DMA_INFIFO_STATUS_CH0_REG.
+ */
+
+#define DMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x78)
+
+/* DMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0;
+ * reserved
+ */
+
+#define DMA_IN_BUF_HUNGRY_CH0 (BIT(27))
+#define DMA_IN_BUF_HUNGRY_CH0_M (DMA_IN_BUF_HUNGRY_CH0_V << DMA_IN_BUF_HUNGRY_CH0_S)
+#define DMA_IN_BUF_HUNGRY_CH0_V 0x00000001
+#define DMA_IN_BUF_HUNGRY_CH0_S 27
+
+/* DMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1;
+ * reserved
+ */
+
+#define DMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26))
+#define DMA_IN_REMAIN_UNDER_4B_CH0_M (DMA_IN_REMAIN_UNDER_4B_CH0_V << DMA_IN_REMAIN_UNDER_4B_CH0_S)
+#define DMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001
+#define DMA_IN_REMAIN_UNDER_4B_CH0_S 26
+
+/* DMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1;
+ * reserved
+ */
+
+#define DMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25))
+#define DMA_IN_REMAIN_UNDER_3B_CH0_M (DMA_IN_REMAIN_UNDER_3B_CH0_V << DMA_IN_REMAIN_UNDER_3B_CH0_S)
+#define DMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001
+#define DMA_IN_REMAIN_UNDER_3B_CH0_S 25
+
+/* DMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1;
+ * reserved
+ */
+
+#define DMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24))
+#define DMA_IN_REMAIN_UNDER_2B_CH0_M (DMA_IN_REMAIN_UNDER_2B_CH0_V << DMA_IN_REMAIN_UNDER_2B_CH0_S)
+#define DMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001
+#define DMA_IN_REMAIN_UNDER_2B_CH0_S 24
+
+/* DMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1;
+ * reserved
+ */
+
+#define DMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23))
+#define DMA_IN_REMAIN_UNDER_1B_CH0_M (DMA_IN_REMAIN_UNDER_1B_CH0_V << DMA_IN_REMAIN_UNDER_1B_CH0_S)
+#define DMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001
+#define DMA_IN_REMAIN_UNDER_1B_CH0_S 23
+
+/* DMA_INFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0;
+ * The register stores the byte number of the data in L1 Rx FIFO for Rx
+ * channel 0.
+ */
+
+#define DMA_INFIFO_CNT_CH0 0x0000003F
+#define DMA_INFIFO_CNT_CH0_M (DMA_INFIFO_CNT_CH0_V << DMA_INFIFO_CNT_CH0_S)
+#define DMA_INFIFO_CNT_CH0_V 0x0000003F
+#define DMA_INFIFO_CNT_CH0_S 2
+
+/* DMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ * L1 Rx FIFO empty signal for Rx channel 0.
+ */
+
+#define DMA_INFIFO_EMPTY_CH0 (BIT(1))
+#define DMA_INFIFO_EMPTY_CH0_M (DMA_INFIFO_EMPTY_CH0_V << DMA_INFIFO_EMPTY_CH0_S)
+#define DMA_INFIFO_EMPTY_CH0_V 0x00000001
+#define DMA_INFIFO_EMPTY_CH0_S 1
+
+/* DMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1;
+ * L1 Rx FIFO full signal for Rx channel 0.
+ */
+
+#define DMA_INFIFO_FULL_CH0 (BIT(0))
+#define DMA_INFIFO_FULL_CH0_M (DMA_INFIFO_FULL_CH0_V << DMA_INFIFO_FULL_CH0_S)
+#define DMA_INFIFO_FULL_CH0_V 0x00000001
+#define DMA_INFIFO_FULL_CH0_S 0
+
+/* DMA_IN_POP_CH0_REG register
+ * DMA_IN_POP_CH0_REG.
+ */
+
+#define DMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x7c)
+
+/* DMA_INFIFO_POP_CH0 : R/W/SC; bitpos: [12]; default: 0;
+ * Set this bit to pop data from DMA FIFO.
+ */
+
+#define DMA_INFIFO_POP_CH0 (BIT(12))
+#define DMA_INFIFO_POP_CH0_M (DMA_INFIFO_POP_CH0_V << DMA_INFIFO_POP_CH0_S)
+#define DMA_INFIFO_POP_CH0_V 0x00000001
+#define DMA_INFIFO_POP_CH0_S 12
+
+/* DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048;
+ * This register stores the data popping from DMA FIFO.
+ */
+
+#define DMA_INFIFO_RDATA_CH0 0x00000FFF
+#define DMA_INFIFO_RDATA_CH0_M (DMA_INFIFO_RDATA_CH0_V << DMA_INFIFO_RDATA_CH0_S)
+#define DMA_INFIFO_RDATA_CH0_V 0x00000FFF
+#define DMA_INFIFO_RDATA_CH0_S 0
+
+/* DMA_IN_LINK_CH0_REG register
+ * DMA_IN_LINK_CH0_REG.
+ */
+
+#define DMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80)
+
+/* DMA_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1;
+ * 1: the inlink descriptor's FSM is in idle state. 0: the inlink
+ * descriptor's FSM is working.
+ */
+
+#define DMA_INLINK_PARK_CH0 (BIT(24))
+#define DMA_INLINK_PARK_CH0_M (DMA_INLINK_PARK_CH0_V << DMA_INLINK_PARK_CH0_S)
+#define DMA_INLINK_PARK_CH0_V 0x00000001
+#define DMA_INLINK_PARK_CH0_S 24
+
+/* DMA_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0;
+ * Set this bit to mount a new inlink descriptor.
+ */
+
+#define DMA_INLINK_RESTART_CH0 (BIT(23))
+#define DMA_INLINK_RESTART_CH0_M (DMA_INLINK_RESTART_CH0_V << DMA_INLINK_RESTART_CH0_S)
+#define DMA_INLINK_RESTART_CH0_V 0x00000001
+#define DMA_INLINK_RESTART_CH0_S 23
+
+/* DMA_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ * Set this bit to start dealing with the inlink descriptors.
+ */
+
+#define DMA_INLINK_START_CH0 (BIT(22))
+#define DMA_INLINK_START_CH0_M (DMA_INLINK_START_CH0_V << DMA_INLINK_START_CH0_S)
+#define DMA_INLINK_START_CH0_V 0x00000001
+#define DMA_INLINK_START_CH0_S 22
+
+/* DMA_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ * Set this bit to stop dealing with the inlink descriptors.
+ */
+
+#define DMA_INLINK_STOP_CH0 (BIT(21))
+#define DMA_INLINK_STOP_CH0_M (DMA_INLINK_STOP_CH0_V << DMA_INLINK_STOP_CH0_S)
+#define DMA_INLINK_STOP_CH0_V 0x00000001
+#define DMA_INLINK_STOP_CH0_S 21
+
+/* DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1;
+ * Set this bit to return to current inlink descriptor's address, when there
+ * are some errors in current receiving data.
+ */
+
+#define DMA_INLINK_AUTO_RET_CH0 (BIT(20))
+#define DMA_INLINK_AUTO_RET_CH0_M (DMA_INLINK_AUTO_RET_CH0_V << DMA_INLINK_AUTO_RET_CH0_S)
+#define DMA_INLINK_AUTO_RET_CH0_V 0x00000001
+#define DMA_INLINK_AUTO_RET_CH0_S 20
+
+/* DMA_INLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0;
+ * This register stores the 20 least significant bits of the first inlink
+ * descriptor's address.
+ */
+
+#define DMA_INLINK_ADDR_CH0 0x000FFFFF
+#define DMA_INLINK_ADDR_CH0_M (DMA_INLINK_ADDR_CH0_V << DMA_INLINK_ADDR_CH0_S)
+#define DMA_INLINK_ADDR_CH0_V 0x000FFFFF
+#define DMA_INLINK_ADDR_CH0_S 0
+
+/* DMA_IN_STATE_CH0_REG register
+ * DMA_IN_STATE_CH0_REG.
+ */
+
+#define DMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x84)
+
+/* DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ * reserved
+ */
+
+#define DMA_IN_STATE_CH0 0x00000007
+#define DMA_IN_STATE_CH0_M (DMA_IN_STATE_CH0_V << DMA_IN_STATE_CH0_S)
+#define DMA_IN_STATE_CH0_V 0x00000007
+#define DMA_IN_STATE_CH0_S 20
+
+/* DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ * reserved
+ */
+
+#define DMA_IN_DSCR_STATE_CH0 0x00000003
+#define DMA_IN_DSCR_STATE_CH0_M (DMA_IN_DSCR_STATE_CH0_V << DMA_IN_DSCR_STATE_CH0_S)
+#define DMA_IN_DSCR_STATE_CH0_V 0x00000003
+#define DMA_IN_DSCR_STATE_CH0_S 18
+
+/* DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ * This register stores the current inlink descriptor's address.
+ */
+
+#define DMA_INLINK_DSCR_ADDR_CH0 0x0003FFFF
+#define DMA_INLINK_DSCR_ADDR_CH0_M (DMA_INLINK_DSCR_ADDR_CH0_V << DMA_INLINK_DSCR_ADDR_CH0_S)
+#define DMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFF
+#define DMA_INLINK_DSCR_ADDR_CH0_S 0
+
+/* DMA_IN_SUC_EOF_DES_ADDR_CH0_REG register
+ * DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.
+ */
+
+#define DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88)
+
+/* DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ * This register stores the address of the inlink descriptor when the EOF
+ * bit in this descriptor is 1.
+ */
+
+#define DMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFF
+#define DMA_IN_SUC_EOF_DES_ADDR_CH0_M (DMA_IN_SUC_EOF_DES_ADDR_CH0_V << DMA_IN_SUC_EOF_DES_ADDR_CH0_S)
+#define DMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFF
+#define DMA_IN_SUC_EOF_DES_ADDR_CH0_S 0
+
+/* DMA_IN_ERR_EOF_DES_ADDR_CH0_REG register
+ * DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.
+ */
+
+#define DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8c)
+
+/* DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ * This register stores the address of the inlink descriptor when there are
+ * some errors in current receiving data. Only used when peripheral is UHCI0.
+ */
+
+#define DMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFF
+#define DMA_IN_ERR_EOF_DES_ADDR_CH0_M (DMA_IN_ERR_EOF_DES_ADDR_CH0_V << DMA_IN_ERR_EOF_DES_ADDR_CH0_S)
+#define DMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFF
+#define DMA_IN_ERR_EOF_DES_ADDR_CH0_S 0
+
+/* DMA_IN_DSCR_CH0_REG register
+ * DMA_IN_DSCR_CH0_REG.
+ */
+
+#define DMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x90)
+
+/* DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ * The address of the current inlink descriptor x.
+ */
+
+#define DMA_INLINK_DSCR_CH0 0xFFFFFFFF
+#define DMA_INLINK_DSCR_CH0_M (DMA_INLINK_DSCR_CH0_V << DMA_INLINK_DSCR_CH0_S)
+#define DMA_INLINK_DSCR_CH0_V 0xFFFFFFFF
+#define DMA_INLINK_DSCR_CH0_S 0
+
+/* DMA_IN_DSCR_BF0_CH0_REG register
+ * DMA_IN_DSCR_BF0_CH0_REG.
+ */
+
+#define DMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x94)
+
+/* DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ * The address of the last inlink descriptor x-1.
+ */
+
+#define DMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF0_CH0_M (DMA_INLINK_DSCR_BF0_CH0_V << DMA_INLINK_DSCR_BF0_CH0_S)
+#define DMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF0_CH0_S 0
+
+/* DMA_IN_DSCR_BF1_CH0_REG register
+ * DMA_IN_DSCR_BF1_CH0_REG.
+ */
+
+#define DMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x98)
+
+/* DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ * The address of the second-to-last inlink descriptor x-2.
+ */
+
+#define DMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF1_CH0_M (DMA_INLINK_DSCR_BF1_CH0_V << DMA_INLINK_DSCR_BF1_CH0_S)
+#define DMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF1_CH0_S 0
+
+/* DMA_IN_PRI_CH0_REG register
+ * DMA_IN_PRI_CH0_REG.
+ */
+
+#define DMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x9c)
+
+/* DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ * The priority of Rx channel 0. The larger of the value, the higher of the
+ * priority.
+ */
+
+#define DMA_RX_PRI_CH0 0x0000000F
+#define DMA_RX_PRI_CH0_M (DMA_RX_PRI_CH0_V << DMA_RX_PRI_CH0_S)
+#define DMA_RX_PRI_CH0_V 0x0000000F
+#define DMA_RX_PRI_CH0_S 0
+
+/* DMA_IN_PERI_SEL_CH0_REG register
+ * DMA_IN_PERI_SEL_CH0_REG.
+ */
+
+#define DMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xa0)
+
+/* DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1:
+ * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+ * ADC_DAC.
+ */
+
+#define DMA_PERI_IN_SEL_CH0 0x0000003F
+#define DMA_PERI_IN_SEL_CH0_M (DMA_PERI_IN_SEL_CH0_V << DMA_PERI_IN_SEL_CH0_S)
+#define DMA_PERI_IN_SEL_CH0_V 0x0000003F
+#define DMA_PERI_IN_SEL_CH0_S 0
+
+/* DMA_OUT_CONF0_CH0_REG register
+ * DMA_OUT_CONF0_CH0_REG.
+ */
+
+#define DMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0xd0)
+
+/* DMA_OUT_DATA_BURST_EN_CH0 : R/W; bitpos: [5]; default: 0;
+ * Set this bit to 1 to enable INCR burst transfer for Tx channel 0
+ * transmitting data when accessing internal SRAM.
+ */
+
+#define DMA_OUT_DATA_BURST_EN_CH0 (BIT(5))
+#define DMA_OUT_DATA_BURST_EN_CH0_M (DMA_OUT_DATA_BURST_EN_CH0_V << DMA_OUT_DATA_BURST_EN_CH0_S)
+#define DMA_OUT_DATA_BURST_EN_CH0_V 0x00000001
+#define DMA_OUT_DATA_BURST_EN_CH0_S 5
+
+/* DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0;
+ * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading
+ * link descriptor when accessing internal SRAM.
+ */
+
+#define DMA_OUTDSCR_BURST_EN_CH0 (BIT(4))
+#define DMA_OUTDSCR_BURST_EN_CH0_M (DMA_OUTDSCR_BURST_EN_CH0_V << DMA_OUTDSCR_BURST_EN_CH0_S)
+#define DMA_OUTDSCR_BURST_EN_CH0_V 0x00000001
+#define DMA_OUTDSCR_BURST_EN_CH0_S 4
+
+/* DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1;
+ * EOF flag generation mode when transmitting data. 1: EOF flag for Tx
+ * channel 0 is generated when data need to transmit has been popped from
+ * FIFO in DMA
+ */
+
+#define DMA_OUT_EOF_MODE_CH0 (BIT(3))
+#define DMA_OUT_EOF_MODE_CH0_M (DMA_OUT_EOF_MODE_CH0_V << DMA_OUT_EOF_MODE_CH0_S)
+#define DMA_OUT_EOF_MODE_CH0_V 0x00000001
+#define DMA_OUT_EOF_MODE_CH0_S 3
+
+/* DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable automatic outlink-writeback when all the data in
+ * tx buffer has been transmitted.
+ */
+
+#define DMA_OUT_AUTO_WRBACK_CH0 (BIT(2))
+#define DMA_OUT_AUTO_WRBACK_CH0_M (DMA_OUT_AUTO_WRBACK_CH0_V << DMA_OUT_AUTO_WRBACK_CH0_S)
+#define DMA_OUT_AUTO_WRBACK_CH0_V 0x00000001
+#define DMA_OUT_AUTO_WRBACK_CH0_S 2
+
+/* DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ * reserved
+ */
+
+#define DMA_OUT_LOOP_TEST_CH0 (BIT(1))
+#define DMA_OUT_LOOP_TEST_CH0_M (DMA_OUT_LOOP_TEST_CH0_V << DMA_OUT_LOOP_TEST_CH0_S)
+#define DMA_OUT_LOOP_TEST_CH0_V 0x00000001
+#define DMA_OUT_LOOP_TEST_CH0_S 1
+
+/* DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ * This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.
+ */
+
+#define DMA_OUT_RST_CH0 (BIT(0))
+#define DMA_OUT_RST_CH0_M (DMA_OUT_RST_CH0_V << DMA_OUT_RST_CH0_S)
+#define DMA_OUT_RST_CH0_V 0x00000001
+#define DMA_OUT_RST_CH0_S 0
+
+/* DMA_OUT_CONF1_CH0_REG register
+ * DMA_OUT_CONF1_CH0_REG.
+ */
+
+#define DMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0xd4)
+
+/* DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ * Set this bit to enable checking the owner attribute of the link
+ * descriptor.
+ */
+
+#define DMA_OUT_CHECK_OWNER_CH0 (BIT(12))
+#define DMA_OUT_CHECK_OWNER_CH0_M (DMA_OUT_CHECK_OWNER_CH0_V << DMA_OUT_CHECK_OWNER_CH0_S)
+#define DMA_OUT_CHECK_OWNER_CH0_V 0x00000001
+#define DMA_OUT_CHECK_OWNER_CH0_S 12
+
+/* DMA_OUTFIFO_STATUS_CH0_REG register
+ * DMA_OUTFIFO_STATUS_CH0_REG.
+ */
+
+#define DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0xd8)
+
+/* DMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1;
+ * reserved
+ */
+
+#define DMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26))
+#define DMA_OUT_REMAIN_UNDER_4B_CH0_M (DMA_OUT_REMAIN_UNDER_4B_CH0_V << DMA_OUT_REMAIN_UNDER_4B_CH0_S)
+#define DMA_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001
+#define DMA_OUT_REMAIN_UNDER_4B_CH0_S 26
+
+/* DMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1;
+ * reserved
+ */
+
+#define DMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25))
+#define DMA_OUT_REMAIN_UNDER_3B_CH0_M (DMA_OUT_REMAIN_UNDER_3B_CH0_V << DMA_OUT_REMAIN_UNDER_3B_CH0_S)
+#define DMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001
+#define DMA_OUT_REMAIN_UNDER_3B_CH0_S 25
+
+/* DMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1;
+ * reserved
+ */
+
+#define DMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24))
+#define DMA_OUT_REMAIN_UNDER_2B_CH0_M (DMA_OUT_REMAIN_UNDER_2B_CH0_V << DMA_OUT_REMAIN_UNDER_2B_CH0_S)
+#define DMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001
+#define DMA_OUT_REMAIN_UNDER_2B_CH0_S 24
+
+/* DMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1;
+ * reserved
+ */
+
+#define DMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23))
+#define DMA_OUT_REMAIN_UNDER_1B_CH0_M (DMA_OUT_REMAIN_UNDER_1B_CH0_V << DMA_OUT_REMAIN_UNDER_1B_CH0_S)
+#define DMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001
+#define DMA_OUT_REMAIN_UNDER_1B_CH0_S 23
+
+/* DMA_OUTFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0;
+ * The register stores the byte number of the data in L1 Tx FIFO for Tx
+ * channel 0.
+ */
+
+#define DMA_OUTFIFO_CNT_CH0 0x0000003F
+#define DMA_OUTFIFO_CNT_CH0_M (DMA_OUTFIFO_CNT_CH0_V << DMA_OUTFIFO_CNT_CH0_S)
+#define DMA_OUTFIFO_CNT_CH0_V 0x0000003F
+#define DMA_OUTFIFO_CNT_CH0_S 2
+
+/* DMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ * L1 Tx FIFO empty signal for Tx channel 0.
+ */
+
+#define DMA_OUTFIFO_EMPTY_CH0 (BIT(1))
+#define DMA_OUTFIFO_EMPTY_CH0_M (DMA_OUTFIFO_EMPTY_CH0_V << DMA_OUTFIFO_EMPTY_CH0_S)
+#define DMA_OUTFIFO_EMPTY_CH0_V 0x00000001
+#define DMA_OUTFIFO_EMPTY_CH0_S 1
+
+/* DMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0;
+ * L1 Tx FIFO full signal for Tx channel 0.
+ */
+
+#define DMA_OUTFIFO_FULL_CH0 (BIT(0))
+#define DMA_OUTFIFO_FULL_CH0_M (DMA_OUTFIFO_FULL_CH0_V << DMA_OUTFIFO_FULL_CH0_S)
+#define DMA_OUTFIFO_FULL_CH0_V 0x00000001
+#define DMA_OUTFIFO_FULL_CH0_S 0
+
+/* DMA_OUT_PUSH_CH0_REG register
+ * DMA_OUT_PUSH_CH0_REG.
+ */
+
+#define DMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0xdc)
+
+/* DMA_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [9]; default: 0;
+ * Set this bit to push data into DMA FIFO.
+ */
+
+#define DMA_OUTFIFO_PUSH_CH0 (BIT(9))
+#define DMA_OUTFIFO_PUSH_CH0_M (DMA_OUTFIFO_PUSH_CH0_V << DMA_OUTFIFO_PUSH_CH0_S)
+#define DMA_OUTFIFO_PUSH_CH0_V 0x00000001
+#define DMA_OUTFIFO_PUSH_CH0_S 9
+
+/* DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0;
+ * This register stores the data that need to be pushed into DMA FIFO.
+ */
+
+#define DMA_OUTFIFO_WDATA_CH0 0x000001FF
+#define DMA_OUTFIFO_WDATA_CH0_M (DMA_OUTFIFO_WDATA_CH0_V << DMA_OUTFIFO_WDATA_CH0_S)
+#define DMA_OUTFIFO_WDATA_CH0_V 0x000001FF
+#define DMA_OUTFIFO_WDATA_CH0_S 0
+
+/* DMA_OUT_LINK_CH0_REG register
+ * DMA_OUT_LINK_CH0_REG.
+ */
+
+#define DMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0xe0)
+
+/* DMA_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1;
+ * 1: the outlink descriptor's FSM is in idle state. 0: the outlink
+ * descriptor's FSM is working.
+ */
+
+#define DMA_OUTLINK_PARK_CH0 (BIT(23))
+#define DMA_OUTLINK_PARK_CH0_M (DMA_OUTLINK_PARK_CH0_V << DMA_OUTLINK_PARK_CH0_S)
+#define DMA_OUTLINK_PARK_CH0_V 0x00000001
+#define DMA_OUTLINK_PARK_CH0_S 23
+
+/* DMA_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ * Set this bit to restart a new outlink from the last address.
+ */
+
+#define DMA_OUTLINK_RESTART_CH0 (BIT(22))
+#define DMA_OUTLINK_RESTART_CH0_M (DMA_OUTLINK_RESTART_CH0_V << DMA_OUTLINK_RESTART_CH0_S)
+#define DMA_OUTLINK_RESTART_CH0_V 0x00000001
+#define DMA_OUTLINK_RESTART_CH0_S 22
+
+/* DMA_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ * Set this bit to start dealing with the outlink descriptors.
+ */
+
+#define DMA_OUTLINK_START_CH0 (BIT(21))
+#define DMA_OUTLINK_START_CH0_M (DMA_OUTLINK_START_CH0_V << DMA_OUTLINK_START_CH0_S)
+#define DMA_OUTLINK_START_CH0_V 0x00000001
+#define DMA_OUTLINK_START_CH0_S 21
+
+/* DMA_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0;
+ * Set this bit to stop dealing with the outlink descriptors.
+ */
+
+#define DMA_OUTLINK_STOP_CH0 (BIT(20))
+#define DMA_OUTLINK_STOP_CH0_M (DMA_OUTLINK_STOP_CH0_V << DMA_OUTLINK_STOP_CH0_S)
+#define DMA_OUTLINK_STOP_CH0_V 0x00000001
+#define DMA_OUTLINK_STOP_CH0_S 20
+
+/* DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0;
+ * This register stores the 20 least significant bits of the first outlink
+ * descriptor's address.
+ */
+
+#define DMA_OUTLINK_ADDR_CH0 0x000FFFFF
+#define DMA_OUTLINK_ADDR_CH0_M (DMA_OUTLINK_ADDR_CH0_V << DMA_OUTLINK_ADDR_CH0_S)
+#define DMA_OUTLINK_ADDR_CH0_V 0x000FFFFF
+#define DMA_OUTLINK_ADDR_CH0_S 0
+
+/* DMA_OUT_STATE_CH0_REG register
+ * DMA_OUT_STATE_CH0_REG.
+ */
+
+#define DMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0xe4)
+
+/* DMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ * reserved
+ */
+
+#define DMA_OUT_STATE_CH0 0x00000007
+#define DMA_OUT_STATE_CH0_M (DMA_OUT_STATE_CH0_V << DMA_OUT_STATE_CH0_S)
+#define DMA_OUT_STATE_CH0_V 0x00000007
+#define DMA_OUT_STATE_CH0_S 20
+
+/* DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ * reserved
+ */
+
+#define DMA_OUT_DSCR_STATE_CH0 0x00000003
+#define DMA_OUT_DSCR_STATE_CH0_M (DMA_OUT_DSCR_STATE_CH0_V << DMA_OUT_DSCR_STATE_CH0_S)
+#define DMA_OUT_DSCR_STATE_CH0_V 0x00000003
+#define DMA_OUT_DSCR_STATE_CH0_S 18
+
+/* DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ * This register stores the current outlink descriptor's address.
+ */
+
+#define DMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFF
+#define DMA_OUTLINK_DSCR_ADDR_CH0_M (DMA_OUTLINK_DSCR_ADDR_CH0_V << DMA_OUTLINK_DSCR_ADDR_CH0_S)
+#define DMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFF
+#define DMA_OUTLINK_DSCR_ADDR_CH0_S 0
+
+/* DMA_OUT_EOF_DES_ADDR_CH0_REG register
+ * DMA_OUT_EOF_DES_ADDR_CH0_REG.
+ */
+
+#define DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xe8)
+
+/* DMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ * This register stores the address of the outlink descriptor when the EOF
+ * bit in this descriptor is 1.
+ */
+
+#define DMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFF
+#define DMA_OUT_EOF_DES_ADDR_CH0_M (DMA_OUT_EOF_DES_ADDR_CH0_V << DMA_OUT_EOF_DES_ADDR_CH0_S)
+#define DMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFF
+#define DMA_OUT_EOF_DES_ADDR_CH0_S 0
+
+/* DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register
+ * DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.
+ */
+
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xec)
+
+/* DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ * This register stores the address of the outlink descriptor before the
+ * last outlink descriptor.
+ */
+
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFF
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_M (DMA_OUT_EOF_BFR_DES_ADDR_CH0_V << DMA_OUT_EOF_BFR_DES_ADDR_CH0_S)
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFF
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0
+
+/* DMA_OUT_DSCR_CH0_REG register
+ * DMA_OUT_DSCR_CH0_REG.
+ */
+
+#define DMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0xf0)
+
+/* DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ * The address of the current outlink descriptor y.
+ */
+
+#define DMA_OUTLINK_DSCR_CH0 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_CH0_M (DMA_OUTLINK_DSCR_CH0_V << DMA_OUTLINK_DSCR_CH0_S)
+#define DMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_CH0_S 0
+
+/* DMA_OUT_DSCR_BF0_CH0_REG register
+ * DMA_OUT_DSCR_BF0_CH0_REG.
+ */
+
+#define DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0xf4)
+
+/* DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ * The address of the last outlink descriptor y-1.
+ */
+
+#define DMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF0_CH0_M (DMA_OUTLINK_DSCR_BF0_CH0_V << DMA_OUTLINK_DSCR_BF0_CH0_S)
+#define DMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF0_CH0_S 0
+
+/* DMA_OUT_DSCR_BF1_CH0_REG register
+ * DMA_OUT_DSCR_BF1_CH0_REG.
+ */
+
+#define DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0xf8)
+
+/* DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ * The address of the second-to-last inlink descriptor x-2.
+ */
+
+#define DMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF1_CH0_M (DMA_OUTLINK_DSCR_BF1_CH0_V << DMA_OUTLINK_DSCR_BF1_CH0_S)
+#define DMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF1_CH0_S 0
+
+/* DMA_OUT_PRI_CH0_REG register
+ * DMA_OUT_PRI_CH0_REG.
+ */
+
+#define DMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0xfc)
+
+/* DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ * The priority of Tx channel 0. The larger of the value, the higher of the
+ * priority.
+ */
+
+#define DMA_TX_PRI_CH0 0x0000000F
+#define DMA_TX_PRI_CH0_M (DMA_TX_PRI_CH0_V << DMA_TX_PRI_CH0_S)
+#define DMA_TX_PRI_CH0_V 0x0000000F
+#define DMA_TX_PRI_CH0_S 0
+
+/* DMA_OUT_PERI_SEL_CH0_REG register
+ * DMA_OUT_PERI_SEL_CH0_REG.
+ */
+
+#define DMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x100)
+
+/* DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1:
+ * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+ * ADC_DAC.
+ */
+
+#define DMA_PERI_OUT_SEL_CH0 0x0000003F
+#define DMA_PERI_OUT_SEL_CH0_M (DMA_PERI_OUT_SEL_CH0_V << DMA_PERI_OUT_SEL_CH0_S)
+#define DMA_PERI_OUT_SEL_CH0_V 0x0000003F
+#define DMA_PERI_OUT_SEL_CH0_S 0
+
+/* DMA_IN_CONF0_CH1_REG register
+ * DMA_IN_CONF0_CH1_REG.
+ */
+
+#define DMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x130)
+
+/* DMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0;
+ * Set this bit 1 to enable automatic transmitting data from memory to
+ * memory via DMA.
+ */
+
+#define DMA_MEM_TRANS_EN_CH1 (BIT(4))
+#define DMA_MEM_TRANS_EN_CH1_M (DMA_MEM_TRANS_EN_CH1_V << DMA_MEM_TRANS_EN_CH1_S)
+#define DMA_MEM_TRANS_EN_CH1_V 0x00000001
+#define DMA_MEM_TRANS_EN_CH1_S 4
+
+/* DMA_IN_DATA_BURST_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ * Set this bit to 1 to enable INCR burst transfer for Rx channel 1
+ * receiving data when accessing internal SRAM.
+ */
+
+#define DMA_IN_DATA_BURST_EN_CH1 (BIT(3))
+#define DMA_IN_DATA_BURST_EN_CH1_M (DMA_IN_DATA_BURST_EN_CH1_V << DMA_IN_DATA_BURST_EN_CH1_S)
+#define DMA_IN_DATA_BURST_EN_CH1_V 0x00000001
+#define DMA_IN_DATA_BURST_EN_CH1_S 3
+
+/* DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading
+ * link descriptor when accessing internal SRAM.
+ */
+
+#define DMA_INDSCR_BURST_EN_CH1 (BIT(2))
+#define DMA_INDSCR_BURST_EN_CH1_M (DMA_INDSCR_BURST_EN_CH1_V << DMA_INDSCR_BURST_EN_CH1_S)
+#define DMA_INDSCR_BURST_EN_CH1_V 0x00000001
+#define DMA_INDSCR_BURST_EN_CH1_S 2
+
+/* DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
+ * reserved
+ */
+
+#define DMA_IN_LOOP_TEST_CH1 (BIT(1))
+#define DMA_IN_LOOP_TEST_CH1_M (DMA_IN_LOOP_TEST_CH1_V << DMA_IN_LOOP_TEST_CH1_S)
+#define DMA_IN_LOOP_TEST_CH1_V 0x00000001
+#define DMA_IN_LOOP_TEST_CH1_S 1
+
+/* DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0;
+ * This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.
+ */
+
+#define DMA_IN_RST_CH1 (BIT(0))
+#define DMA_IN_RST_CH1_M (DMA_IN_RST_CH1_V << DMA_IN_RST_CH1_S)
+#define DMA_IN_RST_CH1_V 0x00000001
+#define DMA_IN_RST_CH1_S 0
+
+/* DMA_IN_CONF1_CH1_REG register
+ * DMA_IN_CONF1_CH1_REG.
+ */
+
+#define DMA_IN_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x134)
+
+/* DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
+ * Set this bit to enable checking the owner attribute of the link
+ * descriptor.
+ */
+
+#define DMA_IN_CHECK_OWNER_CH1 (BIT(12))
+#define DMA_IN_CHECK_OWNER_CH1_M (DMA_IN_CHECK_OWNER_CH1_V << DMA_IN_CHECK_OWNER_CH1_S)
+#define DMA_IN_CHECK_OWNER_CH1_V 0x00000001
+#define DMA_IN_CHECK_OWNER_CH1_S 12
+
+/* DMA_INFIFO_STATUS_CH1_REG register
+ * DMA_INFIFO_STATUS_CH1_REG.
+ */
+
+#define DMA_INFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x138)
+
+/* DMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0;
+ * reserved
+ */
+
+#define DMA_IN_BUF_HUNGRY_CH1 (BIT(27))
+#define DMA_IN_BUF_HUNGRY_CH1_M (DMA_IN_BUF_HUNGRY_CH1_V << DMA_IN_BUF_HUNGRY_CH1_S)
+#define DMA_IN_BUF_HUNGRY_CH1_V 0x00000001
+#define DMA_IN_BUF_HUNGRY_CH1_S 27
+
+/* DMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1;
+ * reserved
+ */
+
+#define DMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26))
+#define DMA_IN_REMAIN_UNDER_4B_CH1_M (DMA_IN_REMAIN_UNDER_4B_CH1_V << DMA_IN_REMAIN_UNDER_4B_CH1_S)
+#define DMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001
+#define DMA_IN_REMAIN_UNDER_4B_CH1_S 26
+
+/* DMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1;
+ * reserved
+ */
+
+#define DMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25))
+#define DMA_IN_REMAIN_UNDER_3B_CH1_M (DMA_IN_REMAIN_UNDER_3B_CH1_V << DMA_IN_REMAIN_UNDER_3B_CH1_S)
+#define DMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001
+#define DMA_IN_REMAIN_UNDER_3B_CH1_S 25
+
+/* DMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1;
+ * reserved
+ */
+
+#define DMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24))
+#define DMA_IN_REMAIN_UNDER_2B_CH1_M (DMA_IN_REMAIN_UNDER_2B_CH1_V << DMA_IN_REMAIN_UNDER_2B_CH1_S)
+#define DMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001
+#define DMA_IN_REMAIN_UNDER_2B_CH1_S 24
+
+/* DMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1;
+ * reserved
+ */
+
+#define DMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23))
+#define DMA_IN_REMAIN_UNDER_1B_CH1_M (DMA_IN_REMAIN_UNDER_1B_CH1_V << DMA_IN_REMAIN_UNDER_1B_CH1_S)
+#define DMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001
+#define DMA_IN_REMAIN_UNDER_1B_CH1_S 23
+
+/* DMA_INFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0;
+ * The register stores the byte number of the data in L1 Rx FIFO for Rx
+ * channel 1.
+ */
+
+#define DMA_INFIFO_CNT_CH1 0x0000003F
+#define DMA_INFIFO_CNT_CH1_M (DMA_INFIFO_CNT_CH1_V << DMA_INFIFO_CNT_CH1_S)
+#define DMA_INFIFO_CNT_CH1_V 0x0000003F
+#define DMA_INFIFO_CNT_CH1_S 2
+
+/* DMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
+ * L1 Rx FIFO empty signal for Rx channel 1.
+ */
+
+#define DMA_INFIFO_EMPTY_CH1 (BIT(1))
+#define DMA_INFIFO_EMPTY_CH1_M (DMA_INFIFO_EMPTY_CH1_V << DMA_INFIFO_EMPTY_CH1_S)
+#define DMA_INFIFO_EMPTY_CH1_V 0x00000001
+#define DMA_INFIFO_EMPTY_CH1_S 1
+
+/* DMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1;
+ * L1 Rx FIFO full signal for Rx channel 1.
+ */
+
+#define DMA_INFIFO_FULL_CH1 (BIT(0))
+#define DMA_INFIFO_FULL_CH1_M (DMA_INFIFO_FULL_CH1_V << DMA_INFIFO_FULL_CH1_S)
+#define DMA_INFIFO_FULL_CH1_V 0x00000001
+#define DMA_INFIFO_FULL_CH1_S 0
+
+/* DMA_IN_POP_CH1_REG register
+ * DMA_IN_POP_CH1_REG.
+ */
+
+#define DMA_IN_POP_CH1_REG (DR_REG_GDMA_BASE + 0x13c)
+
+/* DMA_INFIFO_POP_CH1 : R/W/SC; bitpos: [12]; default: 0;
+ * Set this bit to pop data from DMA FIFO.
+ */
+
+#define DMA_INFIFO_POP_CH1 (BIT(12))
+#define DMA_INFIFO_POP_CH1_M (DMA_INFIFO_POP_CH1_V << DMA_INFIFO_POP_CH1_S)
+#define DMA_INFIFO_POP_CH1_V 0x00000001
+#define DMA_INFIFO_POP_CH1_S 12
+
+/* DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048;
+ * This register stores the data popping from DMA FIFO.
+ */
+
+#define DMA_INFIFO_RDATA_CH1 0x00000FFF
+#define DMA_INFIFO_RDATA_CH1_M (DMA_INFIFO_RDATA_CH1_V << DMA_INFIFO_RDATA_CH1_S)
+#define DMA_INFIFO_RDATA_CH1_V 0x00000FFF
+#define DMA_INFIFO_RDATA_CH1_S 0
+
+/* DMA_IN_LINK_CH1_REG register
+ * DMA_IN_LINK_CH1_REG.
+ */
+
+#define DMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140)
+
+/* DMA_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1;
+ * 1: the inlink descriptor's FSM is in idle state. 0: the inlink
+ * descriptor's FSM is working.
+ */
+
+#define DMA_INLINK_PARK_CH1 (BIT(24))
+#define DMA_INLINK_PARK_CH1_M (DMA_INLINK_PARK_CH1_V << DMA_INLINK_PARK_CH1_S)
+#define DMA_INLINK_PARK_CH1_V 0x00000001
+#define DMA_INLINK_PARK_CH1_S 24
+
+/* DMA_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0;
+ * Set this bit to mount a new inlink descriptor.
+ */
+
+#define DMA_INLINK_RESTART_CH1 (BIT(23))
+#define DMA_INLINK_RESTART_CH1_M (DMA_INLINK_RESTART_CH1_V << DMA_INLINK_RESTART_CH1_S)
+#define DMA_INLINK_RESTART_CH1_V 0x00000001
+#define DMA_INLINK_RESTART_CH1_S 23
+
+/* DMA_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ * Set this bit to start dealing with the inlink descriptors.
+ */
+
+#define DMA_INLINK_START_CH1 (BIT(22))
+#define DMA_INLINK_START_CH1_M (DMA_INLINK_START_CH1_V << DMA_INLINK_START_CH1_S)
+#define DMA_INLINK_START_CH1_V 0x00000001
+#define DMA_INLINK_START_CH1_S 22
+
+/* DMA_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ * Set this bit to stop dealing with the inlink descriptors.
+ */
+
+#define DMA_INLINK_STOP_CH1 (BIT(21))
+#define DMA_INLINK_STOP_CH1_M (DMA_INLINK_STOP_CH1_V << DMA_INLINK_STOP_CH1_S)
+#define DMA_INLINK_STOP_CH1_V 0x00000001
+#define DMA_INLINK_STOP_CH1_S 21
+
+/* DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1;
+ * Set this bit to return to current inlink descriptor's address, when there
+ * are some errors in current receiving data.
+ */
+
+#define DMA_INLINK_AUTO_RET_CH1 (BIT(20))
+#define DMA_INLINK_AUTO_RET_CH1_M (DMA_INLINK_AUTO_RET_CH1_V << DMA_INLINK_AUTO_RET_CH1_S)
+#define DMA_INLINK_AUTO_RET_CH1_V 0x00000001
+#define DMA_INLINK_AUTO_RET_CH1_S 20
+
+/* DMA_INLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0;
+ * This register stores the 20 least significant bits of the first inlink
+ * descriptor's address.
+ */
+
+#define DMA_INLINK_ADDR_CH1 0x000FFFFF
+#define DMA_INLINK_ADDR_CH1_M (DMA_INLINK_ADDR_CH1_V << DMA_INLINK_ADDR_CH1_S)
+#define DMA_INLINK_ADDR_CH1_V 0x000FFFFF
+#define DMA_INLINK_ADDR_CH1_S 0
+
+/* DMA_IN_STATE_CH1_REG register
+ * DMA_IN_STATE_CH1_REG.
+ */
+
+#define DMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x144)
+
+/* DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ * reserved
+ */
+
+#define DMA_IN_STATE_CH1 0x00000007
+#define DMA_IN_STATE_CH1_M (DMA_IN_STATE_CH1_V << DMA_IN_STATE_CH1_S)
+#define DMA_IN_STATE_CH1_V 0x00000007
+#define DMA_IN_STATE_CH1_S 20
+
+/* DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ * reserved
+ */
+
+#define DMA_IN_DSCR_STATE_CH1 0x00000003
+#define DMA_IN_DSCR_STATE_CH1_M (DMA_IN_DSCR_STATE_CH1_V << DMA_IN_DSCR_STATE_CH1_S)
+#define DMA_IN_DSCR_STATE_CH1_V 0x00000003
+#define DMA_IN_DSCR_STATE_CH1_S 18
+
+/* DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ * This register stores the current inlink descriptor's address.
+ */
+
+#define DMA_INLINK_DSCR_ADDR_CH1 0x0003FFFF
+#define DMA_INLINK_DSCR_ADDR_CH1_M (DMA_INLINK_DSCR_ADDR_CH1_V << DMA_INLINK_DSCR_ADDR_CH1_S)
+#define DMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFF
+#define DMA_INLINK_DSCR_ADDR_CH1_S 0
+
+/* DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register
+ * DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.
+ */
+
+#define DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148)
+
+/* DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ * This register stores the address of the inlink descriptor when the EOF
+ * bit in this descriptor is 1.
+ */
+
+#define DMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFF
+#define DMA_IN_SUC_EOF_DES_ADDR_CH1_M (DMA_IN_SUC_EOF_DES_ADDR_CH1_V << DMA_IN_SUC_EOF_DES_ADDR_CH1_S)
+#define DMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFF
+#define DMA_IN_SUC_EOF_DES_ADDR_CH1_S 0
+
+/* DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register
+ * DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.
+ */
+
+#define DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14c)
+
+/* DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ * This register stores the address of the inlink descriptor when there are
+ * some errors in current receiving data. Only used when peripheral is UHCI0.
+ */
+
+#define DMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFF
+#define DMA_IN_ERR_EOF_DES_ADDR_CH1_M (DMA_IN_ERR_EOF_DES_ADDR_CH1_V << DMA_IN_ERR_EOF_DES_ADDR_CH1_S)
+#define DMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFF
+#define DMA_IN_ERR_EOF_DES_ADDR_CH1_S 0
+
+/* DMA_IN_DSCR_CH1_REG register
+ * DMA_IN_DSCR_CH1_REG.
+ */
+
+#define DMA_IN_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x150)
+
+/* DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ * The address of the current inlink descriptor x.
+ */
+
+#define DMA_INLINK_DSCR_CH1 0xFFFFFFFF
+#define DMA_INLINK_DSCR_CH1_M (DMA_INLINK_DSCR_CH1_V << DMA_INLINK_DSCR_CH1_S)
+#define DMA_INLINK_DSCR_CH1_V 0xFFFFFFFF
+#define DMA_INLINK_DSCR_CH1_S 0
+
+/* DMA_IN_DSCR_BF0_CH1_REG register
+ * DMA_IN_DSCR_BF0_CH1_REG.
+ */
+
+#define DMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x154)
+
+/* DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ * The address of the last inlink descriptor x-1.
+ */
+
+#define DMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF0_CH1_M (DMA_INLINK_DSCR_BF0_CH1_V << DMA_INLINK_DSCR_BF0_CH1_S)
+#define DMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF0_CH1_S 0
+
+/* DMA_IN_DSCR_BF1_CH1_REG register
+ * DMA_IN_DSCR_BF1_CH1_REG.
+ */
+
+#define DMA_IN_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x158)
+
+/* DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ * The address of the second-to-last inlink descriptor x-2.
+ */
+
+#define DMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF1_CH1_M (DMA_INLINK_DSCR_BF1_CH1_V << DMA_INLINK_DSCR_BF1_CH1_S)
+#define DMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF1_CH1_S 0
+
+/* DMA_IN_PRI_CH1_REG register
+ * DMA_IN_PRI_CH1_REG.
+ */
+
+#define DMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x15c)
+
+/* DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
+ * The priority of Rx channel 1. The larger of the value, the higher of the
+ * priority.
+ */
+
+#define DMA_RX_PRI_CH1 0x0000000F
+#define DMA_RX_PRI_CH1_M (DMA_RX_PRI_CH1_V << DMA_RX_PRI_CH1_S)
+#define DMA_RX_PRI_CH1_V 0x0000000F
+#define DMA_RX_PRI_CH1_S 0
+
+/* DMA_IN_PERI_SEL_CH1_REG register
+ * DMA_IN_PERI_SEL_CH1_REG.
+ */
+
+#define DMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x160)
+
+/* DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
+ * This register is used to select peripheral for Rx channel 1. 0:SPI2. 1:
+ * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+ * ADC_DAC.
+ */
+
+#define DMA_PERI_IN_SEL_CH1 0x0000003F
+#define DMA_PERI_IN_SEL_CH1_M (DMA_PERI_IN_SEL_CH1_V << DMA_PERI_IN_SEL_CH1_S)
+#define DMA_PERI_IN_SEL_CH1_V 0x0000003F
+#define DMA_PERI_IN_SEL_CH1_S 0
+
+/* DMA_OUT_CONF0_CH1_REG register
+ * DMA_OUT_CONF0_CH1_REG.
+ */
+
+#define DMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x190)
+
+/* DMA_OUT_DATA_BURST_EN_CH1 : R/W; bitpos: [5]; default: 0;
+ * Set this bit to 1 to enable INCR burst transfer for Tx channel 1
+ * transmitting data when accessing internal SRAM.
+ */
+
+#define DMA_OUT_DATA_BURST_EN_CH1 (BIT(5))
+#define DMA_OUT_DATA_BURST_EN_CH1_M (DMA_OUT_DATA_BURST_EN_CH1_V << DMA_OUT_DATA_BURST_EN_CH1_S)
+#define DMA_OUT_DATA_BURST_EN_CH1_V 0x00000001
+#define DMA_OUT_DATA_BURST_EN_CH1_S 5
+
+/* DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0;
+ * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading
+ * link descriptor when accessing internal SRAM.
+ */
+
+#define DMA_OUTDSCR_BURST_EN_CH1 (BIT(4))
+#define DMA_OUTDSCR_BURST_EN_CH1_M (DMA_OUTDSCR_BURST_EN_CH1_V << DMA_OUTDSCR_BURST_EN_CH1_S)
+#define DMA_OUTDSCR_BURST_EN_CH1_V 0x00000001
+#define DMA_OUTDSCR_BURST_EN_CH1_S 4
+
+/* DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1;
+ * EOF flag generation mode when transmitting data. 1: EOF flag for Tx
+ * channel 1 is generated when data need to transmit has been popped from
+ * FIFO in DMA
+ */
+
+#define DMA_OUT_EOF_MODE_CH1 (BIT(3))
+#define DMA_OUT_EOF_MODE_CH1_M (DMA_OUT_EOF_MODE_CH1_V << DMA_OUT_EOF_MODE_CH1_S)
+#define DMA_OUT_EOF_MODE_CH1_V 0x00000001
+#define DMA_OUT_EOF_MODE_CH1_S 3
+
+/* DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable automatic outlink-writeback when all the data in
+ * tx buffer has been transmitted.
+ */
+
+#define DMA_OUT_AUTO_WRBACK_CH1 (BIT(2))
+#define DMA_OUT_AUTO_WRBACK_CH1_M (DMA_OUT_AUTO_WRBACK_CH1_V << DMA_OUT_AUTO_WRBACK_CH1_S)
+#define DMA_OUT_AUTO_WRBACK_CH1_V 0x00000001
+#define DMA_OUT_AUTO_WRBACK_CH1_S 2
+
+/* DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
+ * reserved
+ */
+
+#define DMA_OUT_LOOP_TEST_CH1 (BIT(1))
+#define DMA_OUT_LOOP_TEST_CH1_M (DMA_OUT_LOOP_TEST_CH1_V << DMA_OUT_LOOP_TEST_CH1_S)
+#define DMA_OUT_LOOP_TEST_CH1_V 0x00000001
+#define DMA_OUT_LOOP_TEST_CH1_S 1
+
+/* DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0;
+ * This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.
+ */
+
+#define DMA_OUT_RST_CH1 (BIT(0))
+#define DMA_OUT_RST_CH1_M (DMA_OUT_RST_CH1_V << DMA_OUT_RST_CH1_S)
+#define DMA_OUT_RST_CH1_V 0x00000001
+#define DMA_OUT_RST_CH1_S 0
+
+/* DMA_OUT_CONF1_CH1_REG register
+ * DMA_OUT_CONF1_CH1_REG.
+ */
+
+#define DMA_OUT_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x194)
+
+/* DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
+ * Set this bit to enable checking the owner attribute of the link
+ * descriptor.
+ */
+
+#define DMA_OUT_CHECK_OWNER_CH1 (BIT(12))
+#define DMA_OUT_CHECK_OWNER_CH1_M (DMA_OUT_CHECK_OWNER_CH1_V << DMA_OUT_CHECK_OWNER_CH1_S)
+#define DMA_OUT_CHECK_OWNER_CH1_V 0x00000001
+#define DMA_OUT_CHECK_OWNER_CH1_S 12
+
+/* DMA_OUTFIFO_STATUS_CH1_REG register
+ * DMA_OUTFIFO_STATUS_CH1_REG.
+ */
+
+#define DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x198)
+
+/* DMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1;
+ * reserved
+ */
+
+#define DMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26))
+#define DMA_OUT_REMAIN_UNDER_4B_CH1_M (DMA_OUT_REMAIN_UNDER_4B_CH1_V << DMA_OUT_REMAIN_UNDER_4B_CH1_S)
+#define DMA_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001
+#define DMA_OUT_REMAIN_UNDER_4B_CH1_S 26
+
+/* DMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1;
+ * reserved
+ */
+
+#define DMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25))
+#define DMA_OUT_REMAIN_UNDER_3B_CH1_M (DMA_OUT_REMAIN_UNDER_3B_CH1_V << DMA_OUT_REMAIN_UNDER_3B_CH1_S)
+#define DMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001
+#define DMA_OUT_REMAIN_UNDER_3B_CH1_S 25
+
+/* DMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1;
+ * reserved
+ */
+
+#define DMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24))
+#define DMA_OUT_REMAIN_UNDER_2B_CH1_M (DMA_OUT_REMAIN_UNDER_2B_CH1_V << DMA_OUT_REMAIN_UNDER_2B_CH1_S)
+#define DMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001
+#define DMA_OUT_REMAIN_UNDER_2B_CH1_S 24
+
+/* DMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1;
+ * reserved
+ */
+
+#define DMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23))
+#define DMA_OUT_REMAIN_UNDER_1B_CH1_M (DMA_OUT_REMAIN_UNDER_1B_CH1_V << DMA_OUT_REMAIN_UNDER_1B_CH1_S)
+#define DMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001
+#define DMA_OUT_REMAIN_UNDER_1B_CH1_S 23
+
+/* DMA_OUTFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0;
+ * The register stores the byte number of the data in L1 Tx FIFO for Tx
+ * channel 1.
+ */
+
+#define DMA_OUTFIFO_CNT_CH1 0x0000003F
+#define DMA_OUTFIFO_CNT_CH1_M (DMA_OUTFIFO_CNT_CH1_V << DMA_OUTFIFO_CNT_CH1_S)
+#define DMA_OUTFIFO_CNT_CH1_V 0x0000003F
+#define DMA_OUTFIFO_CNT_CH1_S 2
+
+/* DMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
+ * L1 Tx FIFO empty signal for Tx channel 1.
+ */
+
+#define DMA_OUTFIFO_EMPTY_CH1 (BIT(1))
+#define DMA_OUTFIFO_EMPTY_CH1_M (DMA_OUTFIFO_EMPTY_CH1_V << DMA_OUTFIFO_EMPTY_CH1_S)
+#define DMA_OUTFIFO_EMPTY_CH1_V 0x00000001
+#define DMA_OUTFIFO_EMPTY_CH1_S 1
+
+/* DMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0;
+ * L1 Tx FIFO full signal for Tx channel 1.
+ */
+
+#define DMA_OUTFIFO_FULL_CH1 (BIT(0))
+#define DMA_OUTFIFO_FULL_CH1_M (DMA_OUTFIFO_FULL_CH1_V << DMA_OUTFIFO_FULL_CH1_S)
+#define DMA_OUTFIFO_FULL_CH1_V 0x00000001
+#define DMA_OUTFIFO_FULL_CH1_S 0
+
+/* DMA_OUT_PUSH_CH1_REG register
+ * DMA_OUT_PUSH_CH1_REG.
+ */
+
+#define DMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x19c)
+
+/* DMA_OUTFIFO_PUSH_CH1 : R/W/SC; bitpos: [9]; default: 0;
+ * Set this bit to push data into DMA FIFO.
+ */
+
+#define DMA_OUTFIFO_PUSH_CH1 (BIT(9))
+#define DMA_OUTFIFO_PUSH_CH1_M (DMA_OUTFIFO_PUSH_CH1_V << DMA_OUTFIFO_PUSH_CH1_S)
+#define DMA_OUTFIFO_PUSH_CH1_V 0x00000001
+#define DMA_OUTFIFO_PUSH_CH1_S 9
+
+/* DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0;
+ * This register stores the data that need to be pushed into DMA FIFO.
+ */
+
+#define DMA_OUTFIFO_WDATA_CH1 0x000001FF
+#define DMA_OUTFIFO_WDATA_CH1_M (DMA_OUTFIFO_WDATA_CH1_V << DMA_OUTFIFO_WDATA_CH1_S)
+#define DMA_OUTFIFO_WDATA_CH1_V 0x000001FF
+#define DMA_OUTFIFO_WDATA_CH1_S 0
+
+/* DMA_OUT_LINK_CH1_REG register
+ * DMA_OUT_LINK_CH1_REG.
+ */
+
+#define DMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x1a0)
+
+/* DMA_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1;
+ * 1: the outlink descriptor's FSM is in idle state. 0: the outlink
+ * descriptor's FSM is working.
+ */
+
+#define DMA_OUTLINK_PARK_CH1 (BIT(23))
+#define DMA_OUTLINK_PARK_CH1_M (DMA_OUTLINK_PARK_CH1_V << DMA_OUTLINK_PARK_CH1_S)
+#define DMA_OUTLINK_PARK_CH1_V 0x00000001
+#define DMA_OUTLINK_PARK_CH1_S 23
+
+/* DMA_OUTLINK_RESTART_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ * Set this bit to restart a new outlink from the last address.
+ */
+
+#define DMA_OUTLINK_RESTART_CH1 (BIT(22))
+#define DMA_OUTLINK_RESTART_CH1_M (DMA_OUTLINK_RESTART_CH1_V << DMA_OUTLINK_RESTART_CH1_S)
+#define DMA_OUTLINK_RESTART_CH1_V 0x00000001
+#define DMA_OUTLINK_RESTART_CH1_S 22
+
+/* DMA_OUTLINK_START_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ * Set this bit to start dealing with the outlink descriptors.
+ */
+
+#define DMA_OUTLINK_START_CH1 (BIT(21))
+#define DMA_OUTLINK_START_CH1_M (DMA_OUTLINK_START_CH1_V << DMA_OUTLINK_START_CH1_S)
+#define DMA_OUTLINK_START_CH1_V 0x00000001
+#define DMA_OUTLINK_START_CH1_S 21
+
+/* DMA_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0;
+ * Set this bit to stop dealing with the outlink descriptors.
+ */
+
+#define DMA_OUTLINK_STOP_CH1 (BIT(20))
+#define DMA_OUTLINK_STOP_CH1_M (DMA_OUTLINK_STOP_CH1_V << DMA_OUTLINK_STOP_CH1_S)
+#define DMA_OUTLINK_STOP_CH1_V 0x00000001
+#define DMA_OUTLINK_STOP_CH1_S 20
+
+/* DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0;
+ * This register stores the 20 least significant bits of the first outlink
+ * descriptor's address.
+ */
+
+#define DMA_OUTLINK_ADDR_CH1 0x000FFFFF
+#define DMA_OUTLINK_ADDR_CH1_M (DMA_OUTLINK_ADDR_CH1_V << DMA_OUTLINK_ADDR_CH1_S)
+#define DMA_OUTLINK_ADDR_CH1_V 0x000FFFFF
+#define DMA_OUTLINK_ADDR_CH1_S 0
+
+/* DMA_OUT_STATE_CH1_REG register
+ * DMA_OUT_STATE_CH1_REG.
+ */
+
+#define DMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x1a4)
+
+/* DMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ * reserved
+ */
+
+#define DMA_OUT_STATE_CH1 0x00000007
+#define DMA_OUT_STATE_CH1_M (DMA_OUT_STATE_CH1_V << DMA_OUT_STATE_CH1_S)
+#define DMA_OUT_STATE_CH1_V 0x00000007
+#define DMA_OUT_STATE_CH1_S 20
+
+/* DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ * reserved
+ */
+
+#define DMA_OUT_DSCR_STATE_CH1 0x00000003
+#define DMA_OUT_DSCR_STATE_CH1_M (DMA_OUT_DSCR_STATE_CH1_V << DMA_OUT_DSCR_STATE_CH1_S)
+#define DMA_OUT_DSCR_STATE_CH1_V 0x00000003
+#define DMA_OUT_DSCR_STATE_CH1_S 18
+
+/* DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ * This register stores the current outlink descriptor's address.
+ */
+
+#define DMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFF
+#define DMA_OUTLINK_DSCR_ADDR_CH1_M (DMA_OUTLINK_DSCR_ADDR_CH1_V << DMA_OUTLINK_DSCR_ADDR_CH1_S)
+#define DMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFF
+#define DMA_OUTLINK_DSCR_ADDR_CH1_S 0
+
+/* DMA_OUT_EOF_DES_ADDR_CH1_REG register
+ * DMA_OUT_EOF_DES_ADDR_CH1_REG.
+ */
+
+#define DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1a8)
+
+/* DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ * This register stores the address of the outlink descriptor when the EOF
+ * bit in this descriptor is 1.
+ */
+
+#define DMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFF
+#define DMA_OUT_EOF_DES_ADDR_CH1_M (DMA_OUT_EOF_DES_ADDR_CH1_V << DMA_OUT_EOF_DES_ADDR_CH1_S)
+#define DMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFF
+#define DMA_OUT_EOF_DES_ADDR_CH1_S 0
+
+/* DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register
+ * DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.
+ */
+
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1ac)
+
+/* DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ * This register stores the address of the outlink descriptor before the
+ * last outlink descriptor.
+ */
+
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFF
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_M (DMA_OUT_EOF_BFR_DES_ADDR_CH1_V << DMA_OUT_EOF_BFR_DES_ADDR_CH1_S)
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFF
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0
+
+/* DMA_OUT_DSCR_CH1_REG register
+ * DMA_OUT_DSCR_CH1_REG.
+ */
+
+#define DMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x1b0)
+
+/* DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ * The address of the current outlink descriptor y.
+ */
+
+#define DMA_OUTLINK_DSCR_CH1 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_CH1_M (DMA_OUTLINK_DSCR_CH1_V << DMA_OUTLINK_DSCR_CH1_S)
+#define DMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_CH1_S 0
+
+/* DMA_OUT_DSCR_BF0_CH1_REG register
+ * DMA_OUT_DSCR_BF0_CH1_REG.
+ */
+
+#define DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x1b4)
+
+/* DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ * The address of the last outlink descriptor y-1.
+ */
+
+#define DMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF0_CH1_M (DMA_OUTLINK_DSCR_BF0_CH1_V << DMA_OUTLINK_DSCR_BF0_CH1_S)
+#define DMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF0_CH1_S 0
+
+/* DMA_OUT_DSCR_BF1_CH1_REG register
+ * DMA_OUT_DSCR_BF1_CH1_REG.
+ */
+
+#define DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x1b8)
+
+/* DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ * The address of the second-to-last inlink descriptor x-2.
+ */
+
+#define DMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF1_CH1_M (DMA_OUTLINK_DSCR_BF1_CH1_V << DMA_OUTLINK_DSCR_BF1_CH1_S)
+#define DMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF1_CH1_S 0
+
+/* DMA_OUT_PRI_CH1_REG register
+ * DMA_OUT_PRI_CH1_REG.
+ */
+
+#define DMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x1bc)
+
+/* DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
+ * The priority of Tx channel 1. The larger of the value, the higher of the
+ * priority.
+ */
+
+#define DMA_TX_PRI_CH1 0x0000000F
+#define DMA_TX_PRI_CH1_M (DMA_TX_PRI_CH1_V << DMA_TX_PRI_CH1_S)
+#define DMA_TX_PRI_CH1_V 0x0000000F
+#define DMA_TX_PRI_CH1_S 0
+
+/* DMA_OUT_PERI_SEL_CH1_REG register
+ * DMA_OUT_PERI_SEL_CH1_REG.
+ */
+
+#define DMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x1c0)
+
+/* DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
+ * This register is used to select peripheral for Tx channel 1. 0:SPI2. 1:
+ * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+ * ADC_DAC.
+ */
+
+#define DMA_PERI_OUT_SEL_CH1 0x0000003F
+#define DMA_PERI_OUT_SEL_CH1_M (DMA_PERI_OUT_SEL_CH1_V << DMA_PERI_OUT_SEL_CH1_S)
+#define DMA_PERI_OUT_SEL_CH1_V 0x0000003F
+#define DMA_PERI_OUT_SEL_CH1_S 0
+
+/* DMA_IN_CONF0_CH2_REG register
+ * DMA_IN_CONF0_CH2_REG.
+ */
+
+#define DMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1f0)
+
+/* DMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0;
+ * Set this bit 1 to enable automatic transmitting data from memory to
+ * memory via DMA.
+ */
+
+#define DMA_MEM_TRANS_EN_CH2 (BIT(4))
+#define DMA_MEM_TRANS_EN_CH2_M (DMA_MEM_TRANS_EN_CH2_V << DMA_MEM_TRANS_EN_CH2_S)
+#define DMA_MEM_TRANS_EN_CH2_V 0x00000001
+#define DMA_MEM_TRANS_EN_CH2_S 4
+
+/* DMA_IN_DATA_BURST_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ * Set this bit to 1 to enable INCR burst transfer for Rx channel 2
+ * receiving data when accessing internal SRAM.
+ */
+
+#define DMA_IN_DATA_BURST_EN_CH2 (BIT(3))
+#define DMA_IN_DATA_BURST_EN_CH2_M (DMA_IN_DATA_BURST_EN_CH2_V << DMA_IN_DATA_BURST_EN_CH2_S)
+#define DMA_IN_DATA_BURST_EN_CH2_V 0x00000001
+#define DMA_IN_DATA_BURST_EN_CH2_S 3
+
+/* DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading
+ * link descriptor when accessing internal SRAM.
+ */
+
+#define DMA_INDSCR_BURST_EN_CH2 (BIT(2))
+#define DMA_INDSCR_BURST_EN_CH2_M (DMA_INDSCR_BURST_EN_CH2_V << DMA_INDSCR_BURST_EN_CH2_S)
+#define DMA_INDSCR_BURST_EN_CH2_V 0x00000001
+#define DMA_INDSCR_BURST_EN_CH2_S 2
+
+/* DMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
+ * reserved
+ */
+
+#define DMA_IN_LOOP_TEST_CH2 (BIT(1))
+#define DMA_IN_LOOP_TEST_CH2_M (DMA_IN_LOOP_TEST_CH2_V << DMA_IN_LOOP_TEST_CH2_S)
+#define DMA_IN_LOOP_TEST_CH2_V 0x00000001
+#define DMA_IN_LOOP_TEST_CH2_S 1
+
+/* DMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0;
+ * This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.
+ */
+
+#define DMA_IN_RST_CH2 (BIT(0))
+#define DMA_IN_RST_CH2_M (DMA_IN_RST_CH2_V << DMA_IN_RST_CH2_S)
+#define DMA_IN_RST_CH2_V 0x00000001
+#define DMA_IN_RST_CH2_S 0
+
+/* DMA_IN_CONF1_CH2_REG register
+ * DMA_IN_CONF1_CH2_REG.
+ */
+
+#define DMA_IN_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x1f4)
+
+/* DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
+ * Set this bit to enable checking the owner attribute of the link
+ * descriptor.
+ */
+
+#define DMA_IN_CHECK_OWNER_CH2 (BIT(12))
+#define DMA_IN_CHECK_OWNER_CH2_M (DMA_IN_CHECK_OWNER_CH2_V << DMA_IN_CHECK_OWNER_CH2_S)
+#define DMA_IN_CHECK_OWNER_CH2_V 0x00000001
+#define DMA_IN_CHECK_OWNER_CH2_S 12
+
+/* DMA_INFIFO_STATUS_CH2_REG register
+ * DMA_INFIFO_STATUS_CH2_REG.
+ */
+
+#define DMA_INFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x1f8)
+
+/* DMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0;
+ * reserved
+ */
+
+#define DMA_IN_BUF_HUNGRY_CH2 (BIT(27))
+#define DMA_IN_BUF_HUNGRY_CH2_M (DMA_IN_BUF_HUNGRY_CH2_V << DMA_IN_BUF_HUNGRY_CH2_S)
+#define DMA_IN_BUF_HUNGRY_CH2_V 0x00000001
+#define DMA_IN_BUF_HUNGRY_CH2_S 27
+
+/* DMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1;
+ * reserved
+ */
+
+#define DMA_IN_REMAIN_UNDER_4B_CH2 (BIT(26))
+#define DMA_IN_REMAIN_UNDER_4B_CH2_M (DMA_IN_REMAIN_UNDER_4B_CH2_V << DMA_IN_REMAIN_UNDER_4B_CH2_S)
+#define DMA_IN_REMAIN_UNDER_4B_CH2_V 0x00000001
+#define DMA_IN_REMAIN_UNDER_4B_CH2_S 26
+
+/* DMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1;
+ * reserved
+ */
+
+#define DMA_IN_REMAIN_UNDER_3B_CH2 (BIT(25))
+#define DMA_IN_REMAIN_UNDER_3B_CH2_M (DMA_IN_REMAIN_UNDER_3B_CH2_V << DMA_IN_REMAIN_UNDER_3B_CH2_S)
+#define DMA_IN_REMAIN_UNDER_3B_CH2_V 0x00000001
+#define DMA_IN_REMAIN_UNDER_3B_CH2_S 25
+
+/* DMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1;
+ * reserved
+ */
+
+#define DMA_IN_REMAIN_UNDER_2B_CH2 (BIT(24))
+#define DMA_IN_REMAIN_UNDER_2B_CH2_M (DMA_IN_REMAIN_UNDER_2B_CH2_V << DMA_IN_REMAIN_UNDER_2B_CH2_S)
+#define DMA_IN_REMAIN_UNDER_2B_CH2_V 0x00000001
+#define DMA_IN_REMAIN_UNDER_2B_CH2_S 24
+
+/* DMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1;
+ * reserved
+ */
+
+#define DMA_IN_REMAIN_UNDER_1B_CH2 (BIT(23))
+#define DMA_IN_REMAIN_UNDER_1B_CH2_M (DMA_IN_REMAIN_UNDER_1B_CH2_V << DMA_IN_REMAIN_UNDER_1B_CH2_S)
+#define DMA_IN_REMAIN_UNDER_1B_CH2_V 0x00000001
+#define DMA_IN_REMAIN_UNDER_1B_CH2_S 23
+
+/* DMA_INFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0;
+ * The register stores the byte number of the data in L1 Rx FIFO for Rx
+ * channel 2.
+ */
+
+#define DMA_INFIFO_CNT_CH2 0x0000003F
+#define DMA_INFIFO_CNT_CH2_M (DMA_INFIFO_CNT_CH2_V << DMA_INFIFO_CNT_CH2_S)
+#define DMA_INFIFO_CNT_CH2_V 0x0000003F
+#define DMA_INFIFO_CNT_CH2_S 2
+
+/* DMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
+ * L1 Rx FIFO empty signal for Rx channel 2.
+ */
+
+#define DMA_INFIFO_EMPTY_CH2 (BIT(1))
+#define DMA_INFIFO_EMPTY_CH2_M (DMA_INFIFO_EMPTY_CH2_V << DMA_INFIFO_EMPTY_CH2_S)
+#define DMA_INFIFO_EMPTY_CH2_V 0x00000001
+#define DMA_INFIFO_EMPTY_CH2_S 1
+
+/* DMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1;
+ * L1 Rx FIFO full signal for Rx channel 2.
+ */
+
+#define DMA_INFIFO_FULL_CH2 (BIT(0))
+#define DMA_INFIFO_FULL_CH2_M (DMA_INFIFO_FULL_CH2_V << DMA_INFIFO_FULL_CH2_S)
+#define DMA_INFIFO_FULL_CH2_V 0x00000001
+#define DMA_INFIFO_FULL_CH2_S 0
+
+/* DMA_IN_POP_CH2_REG register
+ * DMA_IN_POP_CH2_REG.
+ */
+
+#define DMA_IN_POP_CH2_REG (DR_REG_GDMA_BASE + 0x1fc)
+
+/* DMA_INFIFO_POP_CH2 : R/W/SC; bitpos: [12]; default: 0;
+ * Set this bit to pop data from DMA FIFO.
+ */
+
+#define DMA_INFIFO_POP_CH2 (BIT(12))
+#define DMA_INFIFO_POP_CH2_M (DMA_INFIFO_POP_CH2_V << DMA_INFIFO_POP_CH2_S)
+#define DMA_INFIFO_POP_CH2_V 0x00000001
+#define DMA_INFIFO_POP_CH2_S 12
+
+/* DMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048;
+ * This register stores the data popping from DMA FIFO.
+ */
+
+#define DMA_INFIFO_RDATA_CH2 0x00000FFF
+#define DMA_INFIFO_RDATA_CH2_M (DMA_INFIFO_RDATA_CH2_V << DMA_INFIFO_RDATA_CH2_S)
+#define DMA_INFIFO_RDATA_CH2_V 0x00000FFF
+#define DMA_INFIFO_RDATA_CH2_S 0
+
+/* DMA_IN_LINK_CH2_REG register
+ * DMA_IN_LINK_CH2_REG.
+ */
+
+#define DMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200)
+
+/* DMA_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1;
+ * 1: the inlink descriptor's FSM is in idle state. 0: the inlink
+ * descriptor's FSM is working.
+ */
+
+#define DMA_INLINK_PARK_CH2 (BIT(24))
+#define DMA_INLINK_PARK_CH2_M (DMA_INLINK_PARK_CH2_V << DMA_INLINK_PARK_CH2_S)
+#define DMA_INLINK_PARK_CH2_V 0x00000001
+#define DMA_INLINK_PARK_CH2_S 24
+
+/* DMA_INLINK_RESTART_CH2 : R/W/SC; bitpos: [23]; default: 0;
+ * Set this bit to mount a new inlink descriptor.
+ */
+
+#define DMA_INLINK_RESTART_CH2 (BIT(23))
+#define DMA_INLINK_RESTART_CH2_M (DMA_INLINK_RESTART_CH2_V << DMA_INLINK_RESTART_CH2_S)
+#define DMA_INLINK_RESTART_CH2_V 0x00000001
+#define DMA_INLINK_RESTART_CH2_S 23
+
+/* DMA_INLINK_START_CH2 : R/W/SC; bitpos: [22]; default: 0;
+ * Set this bit to start dealing with the inlink descriptors.
+ */
+
+#define DMA_INLINK_START_CH2 (BIT(22))
+#define DMA_INLINK_START_CH2_M (DMA_INLINK_START_CH2_V << DMA_INLINK_START_CH2_S)
+#define DMA_INLINK_START_CH2_V 0x00000001
+#define DMA_INLINK_START_CH2_S 22
+
+/* DMA_INLINK_STOP_CH2 : R/W/SC; bitpos: [21]; default: 0;
+ * Set this bit to stop dealing with the inlink descriptors.
+ */
+
+#define DMA_INLINK_STOP_CH2 (BIT(21))
+#define DMA_INLINK_STOP_CH2_M (DMA_INLINK_STOP_CH2_V << DMA_INLINK_STOP_CH2_S)
+#define DMA_INLINK_STOP_CH2_V 0x00000001
+#define DMA_INLINK_STOP_CH2_S 21
+
+/* DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1;
+ * Set this bit to return to current inlink descriptor's address, when there
+ * are some errors in current receiving data.
+ */
+
+#define DMA_INLINK_AUTO_RET_CH2 (BIT(20))
+#define DMA_INLINK_AUTO_RET_CH2_M (DMA_INLINK_AUTO_RET_CH2_V << DMA_INLINK_AUTO_RET_CH2_S)
+#define DMA_INLINK_AUTO_RET_CH2_V 0x00000001
+#define DMA_INLINK_AUTO_RET_CH2_S 20
+
+/* DMA_INLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0;
+ * This register stores the 20 least significant bits of the first inlink
+ * descriptor's address.
+ */
+
+#define DMA_INLINK_ADDR_CH2 0x000FFFFF
+#define DMA_INLINK_ADDR_CH2_M (DMA_INLINK_ADDR_CH2_V << DMA_INLINK_ADDR_CH2_S)
+#define DMA_INLINK_ADDR_CH2_V 0x000FFFFF
+#define DMA_INLINK_ADDR_CH2_S 0
+
+/* DMA_IN_STATE_CH2_REG register
+ * DMA_IN_STATE_CH2_REG.
+ */
+
+#define DMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x204)
+
+/* DMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ * reserved
+ */
+
+#define DMA_IN_STATE_CH2 0x00000007
+#define DMA_IN_STATE_CH2_M (DMA_IN_STATE_CH2_V << DMA_IN_STATE_CH2_S)
+#define DMA_IN_STATE_CH2_V 0x00000007
+#define DMA_IN_STATE_CH2_S 20
+
+/* DMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ * reserved
+ */
+
+#define DMA_IN_DSCR_STATE_CH2 0x00000003
+#define DMA_IN_DSCR_STATE_CH2_M (DMA_IN_DSCR_STATE_CH2_V << DMA_IN_DSCR_STATE_CH2_S)
+#define DMA_IN_DSCR_STATE_CH2_V 0x00000003
+#define DMA_IN_DSCR_STATE_CH2_S 18
+
+/* DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ * This register stores the current inlink descriptor's address.
+ */
+
+#define DMA_INLINK_DSCR_ADDR_CH2 0x0003FFFF
+#define DMA_INLINK_DSCR_ADDR_CH2_M (DMA_INLINK_DSCR_ADDR_CH2_V << DMA_INLINK_DSCR_ADDR_CH2_S)
+#define DMA_INLINK_DSCR_ADDR_CH2_V 0x0003FFFF
+#define DMA_INLINK_DSCR_ADDR_CH2_S 0
+
+/* DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register
+ * DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.
+ */
+
+#define DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208)
+
+/* DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ * This register stores the address of the inlink descriptor when the EOF
+ * bit in this descriptor is 1.
+ */
+
+#define DMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFF
+#define DMA_IN_SUC_EOF_DES_ADDR_CH2_M (DMA_IN_SUC_EOF_DES_ADDR_CH2_V << DMA_IN_SUC_EOF_DES_ADDR_CH2_S)
+#define DMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFF
+#define DMA_IN_SUC_EOF_DES_ADDR_CH2_S 0
+
+/* DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register
+ * DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.
+ */
+
+#define DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20c)
+
+/* DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ * This register stores the address of the inlink descriptor when there are
+ * some errors in current receiving data. Only used when peripheral is UHCI0.
+ */
+
+#define DMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFF
+#define DMA_IN_ERR_EOF_DES_ADDR_CH2_M (DMA_IN_ERR_EOF_DES_ADDR_CH2_V << DMA_IN_ERR_EOF_DES_ADDR_CH2_S)
+#define DMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFF
+#define DMA_IN_ERR_EOF_DES_ADDR_CH2_S 0
+
+/* DMA_IN_DSCR_CH2_REG register
+ * DMA_IN_DSCR_CH2_REG.
+ */
+
+#define DMA_IN_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x210)
+
+/* DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ * The address of the current inlink descriptor x.
+ */
+
+#define DMA_INLINK_DSCR_CH2 0xFFFFFFFF
+#define DMA_INLINK_DSCR_CH2_M (DMA_INLINK_DSCR_CH2_V << DMA_INLINK_DSCR_CH2_S)
+#define DMA_INLINK_DSCR_CH2_V 0xFFFFFFFF
+#define DMA_INLINK_DSCR_CH2_S 0
+
+/* DMA_IN_DSCR_BF0_CH2_REG register
+ * DMA_IN_DSCR_BF0_CH2_REG.
+ */
+
+#define DMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x214)
+
+/* DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ * The address of the last inlink descriptor x-1.
+ */
+
+#define DMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF0_CH2_M (DMA_INLINK_DSCR_BF0_CH2_V << DMA_INLINK_DSCR_BF0_CH2_S)
+#define DMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF0_CH2_S 0
+
+/* DMA_IN_DSCR_BF1_CH2_REG register
+ * DMA_IN_DSCR_BF1_CH2_REG.
+ */
+
+#define DMA_IN_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x218)
+
+/* DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ * The address of the second-to-last inlink descriptor x-2.
+ */
+
+#define DMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF1_CH2_M (DMA_INLINK_DSCR_BF1_CH2_V << DMA_INLINK_DSCR_BF1_CH2_S)
+#define DMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF1_CH2_S 0
+
+/* DMA_IN_PRI_CH2_REG register
+ * DMA_IN_PRI_CH2_REG.
+ */
+
+#define DMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x21c)
+
+/* DMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
+ * The priority of Rx channel 2. The larger of the value, the higher of the
+ * priority.
+ */
+
+#define DMA_RX_PRI_CH2 0x0000000F
+#define DMA_RX_PRI_CH2_M (DMA_RX_PRI_CH2_V << DMA_RX_PRI_CH2_S)
+#define DMA_RX_PRI_CH2_V 0x0000000F
+#define DMA_RX_PRI_CH2_S 0
+
+/* DMA_IN_PERI_SEL_CH2_REG register
+ * DMA_IN_PERI_SEL_CH2_REG.
+ */
+
+#define DMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x220)
+
+/* DMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
+ * This register is used to select peripheral for Rx channel 2. 0:SPI2. 1:
+ * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+ * ADC_DAC.
+ */
+
+#define DMA_PERI_IN_SEL_CH2 0x0000003F
+#define DMA_PERI_IN_SEL_CH2_M (DMA_PERI_IN_SEL_CH2_V << DMA_PERI_IN_SEL_CH2_S)
+#define DMA_PERI_IN_SEL_CH2_V 0x0000003F
+#define DMA_PERI_IN_SEL_CH2_S 0
+
+/* DMA_OUT_CONF0_CH2_REG register
+ * DMA_OUT_CONF0_CH2_REG.
+ */
+
+#define DMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x250)
+
+/* DMA_OUT_DATA_BURST_EN_CH2 : R/W; bitpos: [5]; default: 0;
+ * Set this bit to 1 to enable INCR burst transfer for Tx channel 2
+ * transmitting data when accessing internal SRAM.
+ */
+
+#define DMA_OUT_DATA_BURST_EN_CH2 (BIT(5))
+#define DMA_OUT_DATA_BURST_EN_CH2_M (DMA_OUT_DATA_BURST_EN_CH2_V << DMA_OUT_DATA_BURST_EN_CH2_S)
+#define DMA_OUT_DATA_BURST_EN_CH2_V 0x00000001
+#define DMA_OUT_DATA_BURST_EN_CH2_S 5
+
+/* DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0;
+ * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading
+ * link descriptor when accessing internal SRAM.
+ */
+
+#define DMA_OUTDSCR_BURST_EN_CH2 (BIT(4))
+#define DMA_OUTDSCR_BURST_EN_CH2_M (DMA_OUTDSCR_BURST_EN_CH2_V << DMA_OUTDSCR_BURST_EN_CH2_S)
+#define DMA_OUTDSCR_BURST_EN_CH2_V 0x00000001
+#define DMA_OUTDSCR_BURST_EN_CH2_S 4
+
+/* DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1;
+ * EOF flag generation mode when transmitting data. 1: EOF flag for Tx
+ * channel 2 is generated when data need to transmit has been popped from
+ * FIFO in DMA
+ */
+
+#define DMA_OUT_EOF_MODE_CH2 (BIT(3))
+#define DMA_OUT_EOF_MODE_CH2_M (DMA_OUT_EOF_MODE_CH2_V << DMA_OUT_EOF_MODE_CH2_S)
+#define DMA_OUT_EOF_MODE_CH2_V 0x00000001
+#define DMA_OUT_EOF_MODE_CH2_S 3
+
+/* DMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable automatic outlink-writeback when all the data in
+ * tx buffer has been transmitted.
+ */
+
+#define DMA_OUT_AUTO_WRBACK_CH2 (BIT(2))
+#define DMA_OUT_AUTO_WRBACK_CH2_M (DMA_OUT_AUTO_WRBACK_CH2_V << DMA_OUT_AUTO_WRBACK_CH2_S)
+#define DMA_OUT_AUTO_WRBACK_CH2_V 0x00000001
+#define DMA_OUT_AUTO_WRBACK_CH2_S 2
+
+/* DMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
+ * reserved
+ */
+
+#define DMA_OUT_LOOP_TEST_CH2 (BIT(1))
+#define DMA_OUT_LOOP_TEST_CH2_M (DMA_OUT_LOOP_TEST_CH2_V << DMA_OUT_LOOP_TEST_CH2_S)
+#define DMA_OUT_LOOP_TEST_CH2_V 0x00000001
+#define DMA_OUT_LOOP_TEST_CH2_S 1
+
+/* DMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0;
+ * This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.
+ */
+
+#define DMA_OUT_RST_CH2 (BIT(0))
+#define DMA_OUT_RST_CH2_M (DMA_OUT_RST_CH2_V << DMA_OUT_RST_CH2_S)
+#define DMA_OUT_RST_CH2_V 0x00000001
+#define DMA_OUT_RST_CH2_S 0
+
+/* DMA_OUT_CONF1_CH2_REG register
+ * DMA_OUT_CONF1_CH2_REG.
+ */
+
+#define DMA_OUT_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x254)
+
+/* DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
+ * Set this bit to enable checking the owner attribute of the link
+ * descriptor.
+ */
+
+#define DMA_OUT_CHECK_OWNER_CH2 (BIT(12))
+#define DMA_OUT_CHECK_OWNER_CH2_M (DMA_OUT_CHECK_OWNER_CH2_V << DMA_OUT_CHECK_OWNER_CH2_S)
+#define DMA_OUT_CHECK_OWNER_CH2_V 0x00000001
+#define DMA_OUT_CHECK_OWNER_CH2_S 12
+
+/* DMA_OUTFIFO_STATUS_CH2_REG register
+ * DMA_OUTFIFO_STATUS_CH2_REG.
+ */
+
+#define DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x258)
+
+/* DMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1;
+ * reserved
+ */
+
+#define DMA_OUT_REMAIN_UNDER_4B_CH2 (BIT(26))
+#define DMA_OUT_REMAIN_UNDER_4B_CH2_M (DMA_OUT_REMAIN_UNDER_4B_CH2_V << DMA_OUT_REMAIN_UNDER_4B_CH2_S)
+#define DMA_OUT_REMAIN_UNDER_4B_CH2_V 0x00000001
+#define DMA_OUT_REMAIN_UNDER_4B_CH2_S 26
+
+/* DMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1;
+ * reserved
+ */
+
+#define DMA_OUT_REMAIN_UNDER_3B_CH2 (BIT(25))
+#define DMA_OUT_REMAIN_UNDER_3B_CH2_M (DMA_OUT_REMAIN_UNDER_3B_CH2_V << DMA_OUT_REMAIN_UNDER_3B_CH2_S)
+#define DMA_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001
+#define DMA_OUT_REMAIN_UNDER_3B_CH2_S 25
+
+/* DMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1;
+ * reserved
+ */
+
+#define DMA_OUT_REMAIN_UNDER_2B_CH2 (BIT(24))
+#define DMA_OUT_REMAIN_UNDER_2B_CH2_M (DMA_OUT_REMAIN_UNDER_2B_CH2_V << DMA_OUT_REMAIN_UNDER_2B_CH2_S)
+#define DMA_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001
+#define DMA_OUT_REMAIN_UNDER_2B_CH2_S 24
+
+/* DMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1;
+ * reserved
+ */
+
+#define DMA_OUT_REMAIN_UNDER_1B_CH2 (BIT(23))
+#define DMA_OUT_REMAIN_UNDER_1B_CH2_M (DMA_OUT_REMAIN_UNDER_1B_CH2_V << DMA_OUT_REMAIN_UNDER_1B_CH2_S)
+#define DMA_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001
+#define DMA_OUT_REMAIN_UNDER_1B_CH2_S 23
+
+/* DMA_OUTFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0;
+ * The register stores the byte number of the data in L1 Tx FIFO for Tx
+ * channel 2.
+ */
+
+#define DMA_OUTFIFO_CNT_CH2 0x0000003F
+#define DMA_OUTFIFO_CNT_CH2_M (DMA_OUTFIFO_CNT_CH2_V << DMA_OUTFIFO_CNT_CH2_S)
+#define DMA_OUTFIFO_CNT_CH2_V 0x0000003F
+#define DMA_OUTFIFO_CNT_CH2_S 2
+
+/* DMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
+ * L1 Tx FIFO empty signal for Tx channel 2.
+ */
+
+#define DMA_OUTFIFO_EMPTY_CH2 (BIT(1))
+#define DMA_OUTFIFO_EMPTY_CH2_M (DMA_OUTFIFO_EMPTY_CH2_V << DMA_OUTFIFO_EMPTY_CH2_S)
+#define DMA_OUTFIFO_EMPTY_CH2_V 0x00000001
+#define DMA_OUTFIFO_EMPTY_CH2_S 1
+
+/* DMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0;
+ * L1 Tx FIFO full signal for Tx channel 2.
+ */
+
+#define DMA_OUTFIFO_FULL_CH2 (BIT(0))
+#define DMA_OUTFIFO_FULL_CH2_M (DMA_OUTFIFO_FULL_CH2_V << DMA_OUTFIFO_FULL_CH2_S)
+#define DMA_OUTFIFO_FULL_CH2_V 0x00000001
+#define DMA_OUTFIFO_FULL_CH2_S 0
+
+/* DMA_OUT_PUSH_CH2_REG register
+ * DMA_OUT_PUSH_CH2_REG.
+ */
+
+#define DMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x25c)
+
+/* DMA_OUTFIFO_PUSH_CH2 : R/W/SC; bitpos: [9]; default: 0;
+ * Set this bit to push data into DMA FIFO.
+ */
+
+#define DMA_OUTFIFO_PUSH_CH2 (BIT(9))
+#define DMA_OUTFIFO_PUSH_CH2_M (DMA_OUTFIFO_PUSH_CH2_V << DMA_OUTFIFO_PUSH_CH2_S)
+#define DMA_OUTFIFO_PUSH_CH2_V 0x00000001
+#define DMA_OUTFIFO_PUSH_CH2_S 9
+
+/* DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0;
+ * This register stores the data that need to be pushed into DMA FIFO.
+ */
+
+#define DMA_OUTFIFO_WDATA_CH2 0x000001FF
+#define DMA_OUTFIFO_WDATA_CH2_M (DMA_OUTFIFO_WDATA_CH2_V << DMA_OUTFIFO_WDATA_CH2_S)
+#define DMA_OUTFIFO_WDATA_CH2_V 0x000001FF
+#define DMA_OUTFIFO_WDATA_CH2_S 0
+
+/* DMA_OUT_LINK_CH2_REG register
+ * DMA_OUT_LINK_CH2_REG.
+ */
+
+#define DMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x260)
+
+/* DMA_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1;
+ * 1: the outlink descriptor's FSM is in idle state. 0: the outlink
+ * descriptor's FSM is working.
+ */
+
+#define DMA_OUTLINK_PARK_CH2 (BIT(23))
+#define DMA_OUTLINK_PARK_CH2_M (DMA_OUTLINK_PARK_CH2_V << DMA_OUTLINK_PARK_CH2_S)
+#define DMA_OUTLINK_PARK_CH2_V 0x00000001
+#define DMA_OUTLINK_PARK_CH2_S 23
+
+/* DMA_OUTLINK_RESTART_CH2 : R/W/SC; bitpos: [22]; default: 0;
+ * Set this bit to restart a new outlink from the last address.
+ */
+
+#define DMA_OUTLINK_RESTART_CH2 (BIT(22))
+#define DMA_OUTLINK_RESTART_CH2_M (DMA_OUTLINK_RESTART_CH2_V << DMA_OUTLINK_RESTART_CH2_S)
+#define DMA_OUTLINK_RESTART_CH2_V 0x00000001
+#define DMA_OUTLINK_RESTART_CH2_S 22
+
+/* DMA_OUTLINK_START_CH2 : R/W/SC; bitpos: [21]; default: 0;
+ * Set this bit to start dealing with the outlink descriptors.
+ */
+
+#define DMA_OUTLINK_START_CH2 (BIT(21))
+#define DMA_OUTLINK_START_CH2_M (DMA_OUTLINK_START_CH2_V << DMA_OUTLINK_START_CH2_S)
+#define DMA_OUTLINK_START_CH2_V 0x00000001
+#define DMA_OUTLINK_START_CH2_S 21
+
+/* DMA_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0;
+ * Set this bit to stop dealing with the outlink descriptors.
+ */
+
+#define DMA_OUTLINK_STOP_CH2 (BIT(20))
+#define DMA_OUTLINK_STOP_CH2_M (DMA_OUTLINK_STOP_CH2_V << DMA_OUTLINK_STOP_CH2_S)
+#define DMA_OUTLINK_STOP_CH2_V 0x00000001
+#define DMA_OUTLINK_STOP_CH2_S 20
+
+/* DMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0;
+ * This register stores the 20 least significant bits of the first outlink
+ * descriptor's address.
+ */
+
+#define DMA_OUTLINK_ADDR_CH2 0x000FFFFF
+#define DMA_OUTLINK_ADDR_CH2_M (DMA_OUTLINK_ADDR_CH2_V << DMA_OUTLINK_ADDR_CH2_S)
+#define DMA_OUTLINK_ADDR_CH2_V 0x000FFFFF
+#define DMA_OUTLINK_ADDR_CH2_S 0
+
+/* DMA_OUT_STATE_CH2_REG register
+ * DMA_OUT_STATE_CH2_REG.
+ */
+
+#define DMA_OUT_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x264)
+
+/* DMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ * reserved
+ */
+
+#define DMA_OUT_STATE_CH2 0x00000007
+#define DMA_OUT_STATE_CH2_M (DMA_OUT_STATE_CH2_V << DMA_OUT_STATE_CH2_S)
+#define DMA_OUT_STATE_CH2_V 0x00000007
+#define DMA_OUT_STATE_CH2_S 20
+
+/* DMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ * reserved
+ */
+
+#define DMA_OUT_DSCR_STATE_CH2 0x00000003
+#define DMA_OUT_DSCR_STATE_CH2_M (DMA_OUT_DSCR_STATE_CH2_V << DMA_OUT_DSCR_STATE_CH2_S)
+#define DMA_OUT_DSCR_STATE_CH2_V 0x00000003
+#define DMA_OUT_DSCR_STATE_CH2_S 18
+
+/* DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ * This register stores the current outlink descriptor's address.
+ */
+
+#define DMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFF
+#define DMA_OUTLINK_DSCR_ADDR_CH2_M (DMA_OUTLINK_DSCR_ADDR_CH2_V << DMA_OUTLINK_DSCR_ADDR_CH2_S)
+#define DMA_OUTLINK_DSCR_ADDR_CH2_V 0x0003FFFF
+#define DMA_OUTLINK_DSCR_ADDR_CH2_S 0
+
+/* DMA_OUT_EOF_DES_ADDR_CH2_REG register
+ * DMA_OUT_EOF_DES_ADDR_CH2_REG.
+ */
+
+#define DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x268)
+
+/* DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ * This register stores the address of the outlink descriptor when the EOF
+ * bit in this descriptor is 1.
+ */
+
+#define DMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFF
+#define DMA_OUT_EOF_DES_ADDR_CH2_M (DMA_OUT_EOF_DES_ADDR_CH2_V << DMA_OUT_EOF_DES_ADDR_CH2_S)
+#define DMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFF
+#define DMA_OUT_EOF_DES_ADDR_CH2_S 0
+
+/* DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register
+ * DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.
+ */
+
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x26c)
+
+/* DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ * This register stores the address of the outlink descriptor before the
+ * last outlink descriptor.
+ */
+
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFF
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_M (DMA_OUT_EOF_BFR_DES_ADDR_CH2_V << DMA_OUT_EOF_BFR_DES_ADDR_CH2_S)
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFF
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0
+
+/* DMA_OUT_DSCR_CH2_REG register
+ * DMA_OUT_DSCR_CH2_REG.
+ */
+
+#define DMA_OUT_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x270)
+
+/* DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ * The address of the current outlink descriptor y.
+ */
+
+#define DMA_OUTLINK_DSCR_CH2 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_CH2_M (DMA_OUTLINK_DSCR_CH2_V << DMA_OUTLINK_DSCR_CH2_S)
+#define DMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_CH2_S 0
+
+/* DMA_OUT_DSCR_BF0_CH2_REG register
+ * DMA_OUT_DSCR_BF0_CH2_REG.
+ */
+
+#define DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x274)
+
+/* DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ * The address of the last outlink descriptor y-1.
+ */
+
+#define DMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF0_CH2_M (DMA_OUTLINK_DSCR_BF0_CH2_V << DMA_OUTLINK_DSCR_BF0_CH2_S)
+#define DMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF0_CH2_S 0
+
+/* DMA_OUT_DSCR_BF1_CH2_REG register
+ * DMA_OUT_DSCR_BF1_CH2_REG.
+ */
+
+#define DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x278)
+
+/* DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ * The address of the second-to-last inlink descriptor x-2.
+ */
+
+#define DMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF1_CH2_M (DMA_OUTLINK_DSCR_BF1_CH2_V << DMA_OUTLINK_DSCR_BF1_CH2_S)
+#define DMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF1_CH2_S 0
+
+/* DMA_OUT_PRI_CH2_REG register
+ * DMA_OUT_PRI_CH2_REG.
+ */
+
+#define DMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x27c)
+
+/* DMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
+ * The priority of Tx channel 2. The larger of the value, the higher of the
+ * priority.
+ */
+
+#define DMA_TX_PRI_CH2 0x0000000F
+#define DMA_TX_PRI_CH2_M (DMA_TX_PRI_CH2_V << DMA_TX_PRI_CH2_S)
+#define DMA_TX_PRI_CH2_V 0x0000000F
+#define DMA_TX_PRI_CH2_S 0
+
+/* DMA_OUT_PERI_SEL_CH2_REG register
+ * DMA_OUT_PERI_SEL_CH2_REG.
+ */
+
+#define DMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x280)
+
+/* DMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
+ * This register is used to select peripheral for Tx channel 2. 0:SPI2. 1:
+ * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+ * ADC_DAC.
+ */
+
+#define DMA_PERI_OUT_SEL_CH2 0x0000003F
+#define DMA_PERI_OUT_SEL_CH2_M (DMA_PERI_OUT_SEL_CH2_V << DMA_PERI_OUT_SEL_CH2_S)
+#define DMA_PERI_OUT_SEL_CH2_V 0x0000003F
+#define DMA_PERI_OUT_SEL_CH2_S 0
+
+#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_DMA_H */
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/dma/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/dma/defconfig
new file mode 100644
index 0000000..dc5ca2a
--- /dev/null
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/dma/defconfig
@@ -0,0 +1,32 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_BOARD="esp32c3-devkit"
+CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y
+CONFIG_ARCH_CHIP="esp32c3"
+CONFIG_ARCH_CHIP_ESP32C3=y
+CONFIG_ARCH_CHIP_ESP32C3WROOM02=y
+CONFIG_ARCH_INTERRUPTSTACK=1536
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=15000
+CONFIG_BUILTIN=y
+CONFIG_ESP32C3_DMA=y
+CONFIG_ESP32C3_DMA_M2M_TEST=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_MAX_TASKS=8
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_RAW_BINARY=y
+CONFIG_START_DAY=29
+CONFIG_START_MONTH=11
+CONFIG_START_YEAR=2019
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_USER_ENTRYPOINT="esp32c3_dma_main"