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Posted to commits@mynewt.apache.org by GitBox <gi...@apache.org> on 2021/02/04 02:37:07 UTC

[GitHub] [mynewt-core] mlaz opened a new pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

mlaz opened a new pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466


   This PR comprises:
   - Updated NXP SDK to 2.9.0
   - Common HAL for Kinetis chips.
   - Improved GPIO driver, with interrupt support.
   - I2C and SPI drivers.
   - QSPI driver.
   
   I'll follow up witth another PR adding K8xf support.


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[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot commented on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-772985131


   
   <!-- license-bot -->
   
   ## RAT Report (2021-02-04 02:46:05)
   
   ## New files with unknown licenses
   
   * <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c">hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c</a>
   
   ## 122 new files were excluded from check (.rat-excludes)
   
   <details>
     <summary>Detailed analysis</summary>
   
   ## New files in this PR
   
   | License | File |
   |---------|------|
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/pkg.yml">hw/mcu/nxp/kinetis/pkg.yml</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/syscfg.yml">hw/mcu/nxp/kinetis/syscfg.yml</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c">hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/include/hal_lpuart_nxp.h">hw/mcu/nxp/kinetis/include/hal_lpuart_nxp.h</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/include/mcu/kinetis_common.h">hw/mcu/nxp/kinetis/include/mcu/kinetis_common.h</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/include/mcu/kinetis_hal.h">hw/mcu/nxp/kinetis/include/mcu/kinetis_hal.h</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/src/hal_flash.c">hw/mcu/nxp/kinetis/src/hal_flash.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/src/hal_gpio.c">hw/mcu/nxp/kinetis/src/hal_gpio.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/src/hal_i2c.c">hw/mcu/nxp/kinetis/src/hal_i2c.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/src/hal_lpuart.c">hw/mcu/nxp/kinetis/src/hal_lpuart.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/src/hal_qspi.c">hw/mcu/nxp/kinetis/src/hal_qspi.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/src/hal_spi.c">hw/mcu/nxp/kinetis/src/hal_spi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c</a> |
   </details>
   
   


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[GitHub] [mynewt-core] utzig edited a comment on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
utzig edited a comment on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-773691606


   @mlaz I am fine with this now, please force-push again to check if no RAT issues remain, for some reason it was no updating the message.


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[GitHub] [mynewt-core] utzig commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
utzig commented on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-773691606


   @mlaz I am fine with this now, please force-push again to check if not RAT issues remain, for some reason it was no updating the message.


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[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot commented on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-773679886


   
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[GitHub] [mynewt-core] mlaz commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
mlaz commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570622483



##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,623 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type *dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void *txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave *) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }

Review comment:
       Unfortunately `ctarConfig` is `dspi_master_ctar_config_t` on `dspi_master_config_t` and `dspi_slave_ctar_config_t` on `dspi_slave_config_t`
   




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[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

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   <!-- license-bot -->
   
   ## RAT Report (2021-02-04 02:38:07)
   
   ## New files with unknown licenses
   
   * <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c">hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c</a>
   
   ## 122 new files were excluded from check (.rat-excludes)
   
   <details>
     <summary>Detailed analysis</summary>
   
   ## New files in this PR
   
   | License | File |
   |---------|------|
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/syscfg.yml">hw/mcu/nxp/kinetis/syscfg.yml</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/MK64F12/syscfg.yml">hw/mcu/nxp/kinetis/MK64F12/syscfg.yml</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c">hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/include/hal_lpuart_nxp.h">hw/mcu/nxp/kinetis/include/hal_lpuart_nxp.h</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/include/mcu/kinetis_common.h">hw/mcu/nxp/kinetis/include/mcu/kinetis_common.h</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/include/mcu/kinetis_hal.h">hw/mcu/nxp/kinetis/include/mcu/kinetis_hal.h</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/src/hal_flash.c">hw/mcu/nxp/kinetis/src/hal_flash.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/src/hal_gpio.c">hw/mcu/nxp/kinetis/src/hal_gpio.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/src/hal_i2c.c">hw/mcu/nxp/kinetis/src/hal_i2c.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/src/hal_lpuart.c">hw/mcu/nxp/kinetis/src/hal_lpuart.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/src/hal_qspi.c">hw/mcu/nxp/kinetis/src/hal_qspi.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/src/hal_spi.c">hw/mcu/nxp/kinetis/src/hal_spi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c</a> |
   </details>
   
   


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[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
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URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-773687640


   
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[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

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[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

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apache-mynewt-bot removed a comment on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-772985131


   
   <!-- license-bot -->
   
   ## RAT Report (2021-02-04 02:46:05)
   
   ## New files with unknown licenses
   
   * <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c">hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c</a>
   
   ## 122 new files were excluded from check (.rat-excludes)
   
   <details>
     <summary>Detailed analysis</summary>
   
   ## New files in this PR
   
   | License | File |
   |---------|------|
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/pkg.yml">hw/mcu/nxp/kinetis/pkg.yml</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/syscfg.yml">hw/mcu/nxp/kinetis/syscfg.yml</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c">hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/include/hal_lpuart_nxp.h">hw/mcu/nxp/kinetis/include/hal_lpuart_nxp.h</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/include/mcu/kinetis_common.h">hw/mcu/nxp/kinetis/include/mcu/kinetis_common.h</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/include/mcu/kinetis_hal.h">hw/mcu/nxp/kinetis/include/mcu/kinetis_hal.h</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/src/hal_flash.c">hw/mcu/nxp/kinetis/src/hal_flash.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/src/hal_gpio.c">hw/mcu/nxp/kinetis/src/hal_gpio.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/src/hal_i2c.c">hw/mcu/nxp/kinetis/src/hal_i2c.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/src/hal_lpuart.c">hw/mcu/nxp/kinetis/src/hal_lpuart.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/src/hal_qspi.c">hw/mcu/nxp/kinetis/src/hal_qspi.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/2fc4dc30408d87955342081c77f4e01350e5ba4a/hw/mcu/nxp/kinetis/src/hal_spi.c">hw/mcu/nxp/kinetis/src/hal_spi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c</a> |
   </details>
   
   


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[GitHub] [mynewt-core] mlaz commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
mlaz commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570522918



##########
File path: hw/mcu/nxp/kinetis/src/hal_flash.c
##########
@@ -0,0 +1,178 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+*
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * Internal flash for MK82F25615.

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_hw_id.c
##########
@@ -22,26 +22,27 @@
 
 #include <hal/hal_bsp.h>
 
-#include "MK64F12.h"
+#include "fsl_sim.h"
 
 #ifndef min
 #define min(a, b) ((a)<(b)?(a):(b))
 #endif
 
-#define MK64F12_HW_ID_LEN     7
+#define MK8xF_HW_ID_LEN sizeof(sim_uid_t)

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_watchdog.c
##########
@@ -25,7 +25,7 @@
 #include "fsl_wdog.h"
 #include "fsl_rcm.h"
 
-/* #define WATCHDOG_STUB */
+//#define WATCHDOG_STUB

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,412 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type* dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port; 
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *userData)
+{
+    struct nxp_hal_i2c *i2c = userData;
+    i2c->stat = status;
+    os_sem_release(&i2c->sync);
+}
+
+static struct nxp_hal_i2c*
+hal_i2c_resolve(uint8_t i2c_num)
+{
+    if (i2c_num >= NXP_HAL_I2C_MAX) {
+        return NULL;
+    }
+
+    return i2c_modules[i2c_num];
+}
+
+static void
+i2c_init_hw(struct nxp_hal_i2c *i2c, int pin_scl, int pin_sda)
+{
+    uint32_t clock_freq;
+    i2c_master_config_t master_cfg;
+
+    const port_pin_config_t pincfg = {
+        kPORT_PullUp,
+        kPORT_FastSlewRate,
+        kPORT_PassiveFilterDisable,
+        kPORT_OpenDrainEnable,
+        kPORT_LowDriveStrength,
+        i2c->mux,
+        kPORT_UnlockRegister
+    };
+    PORT_SetPinConfig(i2c->port, i2c->scl_pin, &pincfg);
+    PORT_SetPinConfig(i2c->port, i2c->sda_pin, &pincfg);
+
+    clock_freq = CLOCK_GetFreq(kCLOCK_BusClk);
+    I2C_MasterGetDefaultConfig(&master_cfg);
+    I2C_MasterInit(i2c->dev, &master_cfg, clock_freq);
+
+    I2C_MasterTransferCreateHandle(i2c->dev, &i2c->handle, master_xfer_cb, i2c);
+    NVIC_ClearPendingIRQ(i2c->irqn);
+    NVIC_SetVector(i2c->irqn, (uint32_t) i2c->irq_handler);
+    NVIC_EnableIRQ(i2c->irqn);
+}
+
+static int
+i2c_config(struct nxp_hal_i2c *i2c, uint32_t frequency)
+{
+    uint32_t clock_freq;
+    uint32_t baudrate;
+
+    switch (frequency) {
+    case 100:
+        baudrate = 100000U;
+        break;
+    case 400:
+        baudrate = 400000U;
+        break;
+    case 1000:
+        baudrate = 1000000U;
+        break;
+    default:

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,624 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type* dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void* txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave*) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }
+    return 0;
+}
+
+int
+hal_spi_enable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (spi->enabled) {
+        return 0;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+    master = (struct nxp_spi_master*) spi;
+    DSPI_MasterInit(spi->dev,
+                    &master->config,
+                    CLOCK_GetFreq(kCLOCK_BusClk));
+    } else {
+    slave = (struct nxp_spi_slave*) spi;
+    DSPI_SlaveInit(spi->dev, &slave->config);
+    }

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
+
+    /* Clear Tx FIFO */
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    /* Write enable */
+    cmd_write_enable();
+
+    /* Write data into TX FIFO, needs to write at least 16 bytes of data */
+    QSPI_WriteBlocking(QuadSPI0, val, 16U);
+
+    /* Set seq id, write register */
+    QSPI_ExecuteIPCommand(QuadSPI0, 20);
+
+    /* Wait until finished */
+    check_if_finished();
+}
+
+static int
+nxp_qspi_init(const struct hal_flash *dev)
+{
+    qspi_config_t qspi_cfg = {0};
+
+    /*Get QSPI default settings and configure the qspi */
+    QSPI_GetDefaultQspiConfig(&qspi_cfg);
+
+    /*Set AHB buffer size for reading data through AHB bus */
+/* #if MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) <= FSL_FEATURE_QSPI_AHB_BUFFER_SIZE */
+    qspi_cfg.AHBbufferSize[3] = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+/* #else */
+/*     qspi_cfg.AHBbufferSize[3] = FSL_FEATURE_QSPI_AHB_BUFFER_SIZE; */
+/* #endif */

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,624 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type* dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void* txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave*) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }
+    return 0;
+}
+
+int
+hal_spi_enable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (spi->enabled) {
+        return 0;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+    master = (struct nxp_spi_master*) spi;
+    DSPI_MasterInit(spi->dev,
+                    &master->config,
+                    CLOCK_GetFreq(kCLOCK_BusClk));
+    } else {
+    slave = (struct nxp_spi_slave*) spi;
+    DSPI_SlaveInit(spi->dev, &slave->config);
+    }
+
+    spi->enabled = true;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_SetVector(spi->irqn, (uint32_t) spi->irq_handler);
+    NVIC_EnableIRQ(spi->irqn);
+    return 0;
+}
+
+int
+hal_spi_disable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (!spi->enabled) {
+        return 0;
+    }
+
+    DSPI_Deinit(spi->dev);
+
+    spi->enabled = false;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_DisableIRQ(spi->irqn);
+    return 0;
+}
+
+uint16_t
+hal_spi_tx_val(int spi_num, uint16_t val)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    uint16_t retval = 0;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t*) &val;
+        xfer.rxData = (uint8_t*) &retval;
+        xfer.dataSize = 1;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return retval;
+    }
+    return 0xFFFF; /* Invalid API. */
+}
+
+int
+hal_spi_txrx(int spi_num, void *txbuf, void *rxbuf, int len)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    status_t rc;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t*) txbuf;
+        xfer.rxData = (uint8_t*) rxbuf;
+        xfer.dataSize = len;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        rc = DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return (rc == kStatus_Success) ? 0 : rc;
+    }
+    return -1;
+}
+
+int
+hal_spi_set_txrx_cb(int spi_num, hal_spi_txrx_cb txrx_cb, void *arg)
+{
+    struct nxp_hal_spi *spi;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    spi->txrx_cb = txrx_cb;
+    spi->txrx_cb_arg = arg;
+    return 0;
+}
+
+int
+hal_spi_txrx_noblock(int spi_num, void *txbuf, void *rxbuf, int len)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_transfer_t xfer;
+    status_t rc;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+        //master->handle

Review comment:
       Done

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
+
+    /* Clear Tx FIFO */
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    /* Write enable */
+    cmd_write_enable();
+
+    /* Write data into TX FIFO, needs to write at least 16 bytes of data */
+    QSPI_WriteBlocking(QuadSPI0, val, 16U);
+
+    /* Set seq id, write register */
+    QSPI_ExecuteIPCommand(QuadSPI0, 20);
+
+    /* Wait until finished */
+    check_if_finished();
+}
+
+static int
+nxp_qspi_init(const struct hal_flash *dev)
+{
+    qspi_config_t qspi_cfg = {0};
+
+    /*Get QSPI default settings and configure the qspi */
+    QSPI_GetDefaultQspiConfig(&qspi_cfg);
+
+    /*Set AHB buffer size for reading data through AHB bus */
+/* #if MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) <= FSL_FEATURE_QSPI_AHB_BUFFER_SIZE */
+    qspi_cfg.AHBbufferSize[3] = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+/* #else */
+/*     qspi_cfg.AHBbufferSize[3] = FSL_FEATURE_QSPI_AHB_BUFFER_SIZE; */
+/* #endif */
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SCKA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SSA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA0), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA1), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA2), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIO3A), MYNEWT_VAL(QSPIA_MUX));
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SCKB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SSB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB0), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB1), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB2), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOBA), MYNEWT_VAL(QSPIB_MUX));
+
+    //Configure the baudrate too.
+
+    QSPI_Init(QuadSPI0, &qspi_cfg, CLOCK_GetFreq(kCLOCK_McgPll0Clk));
+
+    memcpy(g_qspi_flash_cfg.lookuptable, lut, sizeof(lut));
+    /*According to serial flash feature to configure flash settings */
+    QSPI_SetFlashConfig(QuadSPI0, &g_qspi_flash_cfg);
+
+#if FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC
+    QSPI_ClearCache(QuadSPI0);
+#endif
+
+    enable_quad_mode();
+    return 0;
+}
+
+static const struct hal_flash_funcs nxp_qspi_funcs = {
+        .hff_read = nxp_qspi_read,
+        .hff_write = nxp_qspi_write,
+        .hff_erase_sector = nxp_qspi_erase_sector,
+        .hff_sector_info = nxp_qspi_sector_info,
+        .hff_init = nxp_qspi_init,
+        .hff_erase = nxp_qspi_erase
+    };
+
+const struct hal_flash nxp_qspi_dev = {
+        .hf_itf = &nxp_qspi_funcs,
+        .hf_base_addr = FSL_FEATURE_QSPI_AMBA_BASE,
+        .hf_size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE),
+        .hf_sector_cnt = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT),
+        .hf_align = 8,
+        .hf_erased_val = 0xff,
+    };

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
+
+    /* Clear Tx FIFO */
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    /* Write enable */
+    cmd_write_enable();
+
+    /* Write data into TX FIFO, needs to write at least 16 bytes of data */
+    QSPI_WriteBlocking(QuadSPI0, val, 16U);
+
+    /* Set seq id, write register */
+    QSPI_ExecuteIPCommand(QuadSPI0, 20);
+
+    /* Wait until finished */
+    check_if_finished();
+}
+
+static int
+nxp_qspi_init(const struct hal_flash *dev)
+{
+    qspi_config_t qspi_cfg = {0};
+
+    /*Get QSPI default settings and configure the qspi */
+    QSPI_GetDefaultQspiConfig(&qspi_cfg);
+
+    /*Set AHB buffer size for reading data through AHB bus */
+/* #if MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) <= FSL_FEATURE_QSPI_AHB_BUFFER_SIZE */
+    qspi_cfg.AHBbufferSize[3] = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+/* #else */
+/*     qspi_cfg.AHBbufferSize[3] = FSL_FEATURE_QSPI_AHB_BUFFER_SIZE; */
+/* #endif */
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SCKA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SSA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA0), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA1), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA2), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIO3A), MYNEWT_VAL(QSPIA_MUX));
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SCKB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SSB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB0), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB1), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB2), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOBA), MYNEWT_VAL(QSPIB_MUX));
+
+    //Configure the baudrate too.

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_lpuart.c
##########
@@ -0,0 +1,460 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+
+#include "os/mynewt.h"
+#include "hal/hal_uart.h"
+#include "hal/hal_gpio.h"
+#include "hal/hal_system.h"
+#include "mcu/cmsis_nvic.h"
+#include "bsp/bsp.h"
+
+#include "mcu/frdm-k8xf_hal.h"
+#include "syscfg/syscfg.h"
+#include "mcu/kinetis_common.h"
+
+#include "fsl_clock.h"
+#include "fsl_port.h"
+#include "fsl_lpuart.h"
+
+#include "hal_lpuart_nxp.h"
+
+/*! @brief Ring buffer size (Unit: Byte). */
+#define TX_BUF_SZ  32
+#define RX_BUF_SZ  128
+
+struct uart_ring {
+    uint16_t ur_head;
+    uint16_t ur_tail;
+    uint16_t ur_size;
+    uint8_t _pad;
+    uint8_t *ur_buf;
+};
+
+struct hal_uart {
+    LPUART_Type      *u_base;
+    clock_name_t     clk_src;
+    uint32_t         u_irq;
+    PORT_Type       *p_base;
+    clock_ip_name_t  p_clock;
+    int  u_pin_rx;
+    int  u_pin_tx;
+    /* TODO: support flow control pins */
+    hal_uart_rx_char u_rx_func;
+    hal_uart_tx_char u_tx_func;
+    hal_uart_tx_done u_tx_done;
+    void *u_func_arg;
+    uint8_t u_configured:1;
+    uint8_t u_open:1;
+    uint8_t u_tx_started:1;
+    uint8_t u_rx_stall:1;
+    struct uart_ring ur_tx;
+    uint8_t tx_buffer[TX_BUF_SZ];
+    struct uart_ring ur_rx;
+    uint8_t rx_buffer[RX_BUF_SZ];
+};
+
+/* UART configurations */
+static struct hal_uart uarts[FSL_FEATURE_SOC_LPUART_COUNT];
+
+static uint8_t const s_uartExists[] = NXP_UART_EXISTS;
+static uint8_t const s_uartEnabled[] = NXP_UART_ENABLED;
+static LPUART_Type *const s_uartBases[] = LPUART_BASE_PTRS;
+static clock_name_t s_uartClocks[] = NXP_UART_CLOCKS;
+static uint8_t const s_uartIRQ[] = LPUART_RX_TX_IRQS;
+static PORT_Type *const s_uartPort[] = NXP_UART_PORTS;
+static clock_ip_name_t const s_uartPortClocks[] = NXP_UART_PORT_CLOCKS;
+static uint8_t const s_uartPIN_RX[] = NXP_UART_PIN_RX;
+static uint8_t const s_uartPIN_TX[] = NXP_UART_PIN_TX;
+
+static void uart_irq0(void);
+static void uart_irq1(void);
+static void uart_irq2(void);
+static void uart_irq3(void);
+static void uart_irq4(void);
+static void (*s_uartirqs[])(void) = {
+    uart_irq0, uart_irq1, uart_irq2, uart_irq3, uart_irq4
+};
+
+/*
+ * RING BUFFER FUNCTIONS
+ */
+
+static uint8_t ur_is_empty(struct uart_ring *ur)
+{
+    return (ur->ur_head == ur->ur_tail);
+}
+
+static uint8_t ur_is_full(struct uart_ring *ur)
+{
+    return (((ur->ur_tail + 1) % ur->ur_size) == ur->ur_head);
+}
+
+static void ur_bump(struct uart_ring *ur)
+{
+    if (!ur_is_empty(ur)) {
+        ur->ur_head++;
+        ur->ur_head %= ur->ur_size;
+        return;
+    }
+}
+
+static uint8_t ur_read(struct uart_ring *ur)
+{
+    return ur->ur_buf[ur->ur_head];
+}
+
+static int ur_queue(struct uart_ring *ur, uint8_t data)
+{
+    if (!ur_is_full(ur)) {
+        ur->ur_buf[ur->ur_tail] = data;
+        ur->ur_tail++;
+        ur->ur_tail %= ur->ur_size;
+        return 0;
+    }
+    return -1;
+}
+
+/*
+ * END RING BUFFER FUNCTIONS
+ */
+
+int hal_uart_init_cbs(int port,
+                      hal_uart_tx_char tx_func,
+                      hal_uart_tx_done tx_done,
+                      hal_uart_rx_char rx_func,
+                      void *arg)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    u->u_rx_func = rx_func;
+    u->u_tx_func = tx_func;
+    u->u_tx_done = tx_done;
+    u->u_func_arg = arg;
+
+    return 0;
+}
+
+void hal_uart_blocking_tx(int port, uint8_t byte)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    LPUART_WriteBlocking(u->u_base, &byte, 1);
+}
+
+static int
+hal_uart_tx_fill_buf(struct hal_uart *u)
+{
+    int data = 0;
+    int i = 0;
+    os_sr_t sr;
+
+    OS_ENTER_CRITICAL(sr);
+    while (!ur_is_full(&u->ur_tx)) {
+        if (u->u_tx_func) {
+            data = u->u_tx_func(u->u_func_arg);
+        }
+        if (data <= 0) {
+            break;
+        }
+        i++;
+        ur_queue(&u->ur_tx, data);
+    }
+    OS_EXIT_CRITICAL(sr);
+    return i;
+}
+
+void hal_uart_start_tx(int port)
+{
+    struct hal_uart *u;
+    int data = -1;
+    int rc;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    /* main loop */
+    while (true)
+    {
+        /* add data to TX ring buffer */
+        if (u->u_tx_started == 0) {
+            rc = hal_uart_tx_fill_buf(u);
+            if (rc > 0) {
+                u->u_tx_started = 1;
+            }
+        }
+
+        /* Send data only when UART TX register is empty and TX ring buffer has data to send out. */
+        while (!ur_is_empty(&u->ur_tx) &&
+               (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base))) {
+            data = ur_read(&u->ur_tx);
+            LPUART_WriteByte(u->u_base, data);
+            ur_bump(&u->ur_tx);
+        }
+
+        if (ur_is_empty(&u->ur_tx)) {
+            if (u->u_tx_done) {
+                u->u_tx_done(u->u_func_arg);
+            }
+            u->u_tx_started = 0;
+            break;
+        }
+    }
+}
+
+void
+hal_uart_start_rx(int port)
+{
+    struct hal_uart *u;
+    os_sr_t sr;
+    int rc = 0;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    u->u_rx_stall = 0;
+
+    /* Send back what's in the RX ring buffer until it's empty or we get an
+     * error */
+    while ((rc >= 0) && !ur_is_empty(&u->ur_rx)) {
+        OS_ENTER_CRITICAL(sr);
+        rc = u->u_rx_func(u->u_func_arg, ur_read(&u->ur_rx));
+        if (rc >= 0) {
+            ur_bump(&u->ur_rx);
+        } else {
+            u->u_rx_stall = 1;
+        }
+        OS_EXIT_CRITICAL(sr);
+    }
+}
+
+static void
+uart_irq_handler(int port)
+{
+    struct hal_uart *u;
+    uint32_t status;
+    uint8_t data;
+
+    u = &uarts[port];
+    if (u->u_configured && u->u_open) {
+        status = LPUART_GetStatusFlags(u->u_base);
+        /* Check for RX data */
+        if (status & (kLPUART_RxDataRegFullFlag | kLPUART_RxOverrunFlag)) {
+            data = LPUART_ReadByte(u->u_base);
+            if (u->u_rx_stall || u->u_rx_func(u->u_func_arg, data) < 0) {
+                /*
+                 * RX queue full.
+                 */
+                u->u_rx_stall = 1;
+                ur_queue(&u->ur_rx, data);
+            }
+        }
+        /* Check for TX complete */
+        if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base)) {
+            if (u->u_tx_started) {
+                u->u_tx_started = 0;
+                if (u->u_tx_done)
+                    u->u_tx_done(u->u_func_arg);
+            }
+        }
+    }
+}
+
+static void
+uart_irq0(void)
+{
+    uart_irq_handler(0);
+}
+
+static void
+uart_irq1(void)
+{
+    uart_irq_handler(1);
+}
+
+static void
+uart_irq2(void)
+{
+    uart_irq_handler(2);
+}
+
+static void
+uart_irq3(void)
+{
+    uart_irq_handler(3);
+}
+
+static void
+uart_irq4(void)
+{
+    uart_irq_handler(4);
+}
+
+int
+hal_uart_config(int port,
+                int32_t speed,
+                uint8_t databits,
+                uint8_t stopbits,
+                enum hal_uart_parity parity,
+                enum hal_uart_flow_ctl flow_ctl)
+{
+    struct hal_uart *u;
+    lpuart_config_t uconfig;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || u->u_open) {
+        return -1;
+    }
+
+    /* PIN config (all UARTs use kPORT_MuxAlt3) */
+    CLOCK_EnableClock(u->p_clock);
+    PORT_SetPinMux(u->p_base, u->u_pin_rx, kPORT_MuxAlt3);
+    PORT_SetPinMux(u->p_base, u->u_pin_tx, kPORT_MuxAlt3);
+
+    /* UART CONFIG */
+    CLOCK_SetLpuartClock(2U);
+
+    LPUART_GetDefaultConfig(&uconfig);
+    uconfig.baudRate_Bps = speed;
+
+    /* TODO: only handles 8 databits currently */
+    switch (stopbits) {
+    case 1:
+        uconfig.stopBitCount = kLPUART_OneStopBit;
+        break;
+    case 2:
+        uconfig.stopBitCount = kLPUART_TwoStopBit;
+        break;
+    default:
+        return -1;
+    }
+
+    switch (parity) {
+    case HAL_UART_PARITY_NONE:
+        uconfig.parityMode = kLPUART_ParityDisabled;
+        break;
+    case HAL_UART_PARITY_ODD:
+        uconfig.parityMode = kLPUART_ParityOdd;
+        break;
+    case HAL_UART_PARITY_EVEN:
+        uconfig.parityMode = kLPUART_ParityEven;
+        break;
+    }
+
+    /* TODO: HW flow control not supported */
+    assert(flow_ctl == HAL_UART_FLOW_CTL_NONE);

Review comment:
       Addressed, good catch.

##########
File path: hw/mcu/nxp/kinetis/src/hal_lpuart.c
##########
@@ -0,0 +1,460 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+
+#include "os/mynewt.h"
+#include "hal/hal_uart.h"
+#include "hal/hal_gpio.h"
+#include "hal/hal_system.h"
+#include "mcu/cmsis_nvic.h"
+#include "bsp/bsp.h"
+
+#include "mcu/frdm-k8xf_hal.h"

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_lpuart.c
##########
@@ -0,0 +1,478 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+
+#include "os/mynewt.h"
+#include "hal/hal_uart.h"
+#include "hal/hal_gpio.h"
+#include "hal/hal_system.h"
+#include "mcu/cmsis_nvic.h"
+#include "bsp/bsp.h"
+#include "syscfg/syscfg.h"
+#include "mcu/kinetis_common.h"
+
+#include "fsl_clock.h"
+#include "fsl_port.h"
+#include "fsl_lpuart.h"
+
+#include "hal_lpuart_nxp.h"
+
+/*! @brief Ring buffer size (Unit: Byte). */
+#define TX_BUF_SZ  32
+#define RX_BUF_SZ  128
+
+struct uart_ring {
+    uint16_t ur_head;
+    uint16_t ur_tail;
+    uint16_t ur_size;
+    uint8_t _pad;
+    uint8_t *ur_buf;
+};
+
+struct hal_uart {
+    LPUART_Type *u_base;
+    clock_name_t clk_src;
+    uint32_t u_irq;
+    PORT_Type *p_base;
+    clock_ip_name_t p_clock;
+    int u_pin_rx;
+    int u_pin_tx;
+    hal_uart_rx_char u_rx_func;
+    hal_uart_tx_char u_tx_func;
+    hal_uart_tx_done u_tx_done;
+    void *u_func_arg;
+    uint8_t u_configured : 1;
+    uint8_t u_open : 1;
+    uint8_t u_tx_started : 1;
+    uint8_t u_rx_stall : 1;
+    struct uart_ring ur_tx;
+    uint8_t tx_buffer[TX_BUF_SZ];
+    struct uart_ring ur_rx;
+    uint8_t rx_buffer[RX_BUF_SZ];
+};
+
+/* UART configurations */
+static struct hal_uart uarts[FSL_FEATURE_SOC_LPUART_COUNT];
+
+static uint8_t const s_uartExists[] = NXP_UART_EXISTS;
+static uint8_t const s_uartEnabled[] = NXP_UART_ENABLED;
+static LPUART_Type *const s_uartBases[] = LPUART_BASE_PTRS;
+static clock_name_t s_uartClocks[] = NXP_UART_CLOCKS;
+static uint8_t const s_uartIRQ[] = LPUART_RX_TX_IRQS;
+static PORT_Type *const s_uartPort[] = NXP_UART_PORTS;
+static clock_ip_name_t const s_uartPortClocks[] = NXP_UART_PORT_CLOCKS;
+static uint8_t const s_uartPIN_RX[] = NXP_UART_PIN_RX;
+static uint8_t const s_uartPIN_TX[] = NXP_UART_PIN_TX;
+
+static void uart_irq0(void);
+static void uart_irq1(void);
+static void uart_irq2(void);
+static void uart_irq3(void);
+static void uart_irq4(void);
+static void (*s_uartirqs[])(void) = {
+    uart_irq0, uart_irq1, uart_irq2, uart_irq3, uart_irq4
+};
+
+/*
+ * RING BUFFER FUNCTIONS
+ */
+
+static uint8_t
+ur_is_empty(struct uart_ring *ur)
+{
+    return (ur->ur_head == ur->ur_tail);
+}
+
+static uint8_t
+ur_is_full(struct uart_ring *ur)
+{
+    return (((ur->ur_tail + 1) % ur->ur_size) == ur->ur_head);
+}
+
+static void
+ur_bump(struct uart_ring *ur)
+{
+    if (!ur_is_empty(ur)) {
+        ur->ur_head++;
+        ur->ur_head %= ur->ur_size;
+        return;
+    }
+}
+
+static uint8_t
+ur_read(struct uart_ring *ur)
+{
+    return ur->ur_buf[ur->ur_head];
+}
+
+static int
+ur_queue(struct uart_ring *ur, uint8_t data)
+{
+    if (!ur_is_full(ur)) {
+        ur->ur_buf[ur->ur_tail] = data;
+        ur->ur_tail++;
+        ur->ur_tail %= ur->ur_size;
+        return 0;
+    }
+    return -1;
+}
+
+/*
+ * END RING BUFFER FUNCTIONS
+ */
+
+int
+hal_uart_init_cbs(int port,
+                  hal_uart_tx_char tx_func,
+                  hal_uart_tx_done tx_done,
+                  hal_uart_rx_char rx_func,
+                  void *arg)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    u->u_rx_func = rx_func;
+    u->u_tx_func = tx_func;
+    u->u_tx_done = tx_done;
+    u->u_func_arg = arg;
+
+    return 0;
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t byte)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    LPUART_WriteBlocking(u->u_base, &byte, 1);
+}
+
+static int
+hal_uart_tx_fill_buf(struct hal_uart *u)
+{
+    int data = 0;
+    int i = 0;
+    os_sr_t sr;
+
+    OS_ENTER_CRITICAL(sr);
+    while (!ur_is_full(&u->ur_tx)) {
+        if (u->u_tx_func) {
+            data = u->u_tx_func(u->u_func_arg);
+        }
+        if (data <= 0) {
+            break;
+        }
+        i++;
+        ur_queue(&u->ur_tx, data);
+    }
+    OS_EXIT_CRITICAL(sr);
+    return i;
+}
+
+void
+hal_uart_start_tx(int port)
+{
+    struct hal_uart *u;
+    int data = -1;
+    int rc;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    /* main loop */
+    while (true) {
+        /* add data to TX ring buffer */
+        if (u->u_tx_started == 0) {
+            rc = hal_uart_tx_fill_buf(u);
+            if (rc > 0) {
+                u->u_tx_started = 1;
+            }
+        }
+
+        /* Send data only when UART TX register is empty and TX ring buffer has data to send out. */
+        while (!ur_is_empty(&u->ur_tx) &&
+               (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base))) {
+            data = ur_read(&u->ur_tx);
+            LPUART_WriteByte(u->u_base, data);
+            ur_bump(&u->ur_tx);
+        }
+
+        if (ur_is_empty(&u->ur_tx)) {
+            if (u->u_tx_done) {
+                u->u_tx_done(u->u_func_arg);
+            }
+            u->u_tx_started = 0;
+            break;
+        }
+    }
+}
+
+void
+hal_uart_start_rx(int port)
+{
+    struct hal_uart *u;
+    os_sr_t sr;
+    int rc = 0;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    u->u_rx_stall = 0;
+
+    /* Send back what's in the RX ring buffer until it's empty or we get an
+     * error */
+    while ((rc >= 0) && !ur_is_empty(&u->ur_rx)) {
+        OS_ENTER_CRITICAL(sr);
+        rc = u->u_rx_func(u->u_func_arg, ur_read(&u->ur_rx));
+        if (rc >= 0) {
+            ur_bump(&u->ur_rx);
+        } else {
+            u->u_rx_stall = 1;
+        }
+        OS_EXIT_CRITICAL(sr);
+    }
+}
+
+static void
+uart_irq_handler(int port)
+{
+    struct hal_uart *u;
+    uint32_t status;
+    uint8_t data;
+
+    u = &uarts[port];
+    if (u->u_configured && u->u_open) {
+        status = LPUART_GetStatusFlags(u->u_base);
+        /* Check for RX data */
+        if (status & (kLPUART_RxDataRegFullFlag | kLPUART_RxOverrunFlag)) {
+            data = LPUART_ReadByte(u->u_base);
+            if (u->u_rx_stall || u->u_rx_func(u->u_func_arg, data) < 0) {
+                /*
+                 * RX queue full.
+                 */
+                u->u_rx_stall = 1;
+                ur_queue(&u->ur_rx, data);
+            }
+        }
+        /* Check for TX complete */
+        if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base)) {
+            if (u->u_tx_started) {
+                u->u_tx_started = 0;
+                if (u->u_tx_done) {
+                    u->u_tx_done(u->u_func_arg);
+                }
+            }
+        }
+    }
+}
+
+static void
+uart_irq0(void)
+{
+    uart_irq_handler(0);
+}
+
+static void
+uart_irq1(void)
+{
+    uart_irq_handler(1);
+}
+
+static void
+uart_irq2(void)
+{
+    uart_irq_handler(2);
+}
+
+static void
+uart_irq3(void)
+{
+    uart_irq_handler(3);
+}
+
+static void
+uart_irq4(void)
+{
+    uart_irq_handler(4);
+}
+
+int
+hal_uart_config(int port,
+                int32_t speed,
+                uint8_t databits,
+                uint8_t stopbits,
+                enum hal_uart_parity parity,
+                enum hal_uart_flow_ctl flow_ctl)
+{
+    struct hal_uart *u;
+    lpuart_config_t uconfig;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || u->u_open) {
+        return -1;
+    }
+
+    /* PIN config (all UARTs use kPORT_MuxAlt3) */
+    CLOCK_EnableClock(u->p_clock);
+    PORT_SetPinMux(u->p_base, u->u_pin_rx, kPORT_MuxAlt3);
+    PORT_SetPinMux(u->p_base, u->u_pin_tx, kPORT_MuxAlt3);
+
+    /* UART CONFIG */
+    CLOCK_SetLpuartClock(2U);
+
+    LPUART_GetDefaultConfig(&uconfig);
+    uconfig.baudRate_Bps = speed;
+
+    switch (databits) {
+    case 8:
+        uconfig.dataBitsCount = kLPUART_EightDataBits;
+        break;
+    case 7:
+#if FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        uconfig.dataBitsCount = kLPUART_SevenDataBits;
+        break;
+#endif /* Fallthrought */
+    default:
+        uconfig.parityMode = kLPUART_ParityEven;
+        return -1;

Review comment:
       hah good catch!

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,623 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type *dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void *txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave *) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }

Review comment:
       Unfortunately `ctarConfig` is `dspi_master_ctar_config_t` on `dspi_master_config_t` and `dspi_slave_ctar_config_t` on `dspi_slave_config_t`
   

##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,408 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type *dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *userData)

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_lpuart.c
##########
@@ -0,0 +1,478 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+
+#include "os/mynewt.h"
+#include "hal/hal_uart.h"
+#include "hal/hal_gpio.h"
+#include "hal/hal_system.h"
+#include "mcu/cmsis_nvic.h"
+#include "bsp/bsp.h"
+#include "syscfg/syscfg.h"
+#include "mcu/kinetis_common.h"
+
+#include "fsl_clock.h"
+#include "fsl_port.h"
+#include "fsl_lpuart.h"
+
+#include "hal_lpuart_nxp.h"
+
+/*! @brief Ring buffer size (Unit: Byte). */
+#define TX_BUF_SZ  32
+#define RX_BUF_SZ  128
+
+struct uart_ring {
+    uint16_t ur_head;
+    uint16_t ur_tail;
+    uint16_t ur_size;
+    uint8_t _pad;
+    uint8_t *ur_buf;
+};
+
+struct hal_uart {
+    LPUART_Type *u_base;
+    clock_name_t clk_src;
+    uint32_t u_irq;
+    PORT_Type *p_base;
+    clock_ip_name_t p_clock;
+    int u_pin_rx;
+    int u_pin_tx;
+    hal_uart_rx_char u_rx_func;
+    hal_uart_tx_char u_tx_func;
+    hal_uart_tx_done u_tx_done;
+    void *u_func_arg;
+    uint8_t u_configured : 1;
+    uint8_t u_open : 1;
+    uint8_t u_tx_started : 1;
+    uint8_t u_rx_stall : 1;
+    struct uart_ring ur_tx;
+    uint8_t tx_buffer[TX_BUF_SZ];
+    struct uart_ring ur_rx;
+    uint8_t rx_buffer[RX_BUF_SZ];
+};
+
+/* UART configurations */
+static struct hal_uart uarts[FSL_FEATURE_SOC_LPUART_COUNT];
+
+static uint8_t const s_uartExists[] = NXP_UART_EXISTS;
+static uint8_t const s_uartEnabled[] = NXP_UART_ENABLED;
+static LPUART_Type *const s_uartBases[] = LPUART_BASE_PTRS;
+static clock_name_t s_uartClocks[] = NXP_UART_CLOCKS;
+static uint8_t const s_uartIRQ[] = LPUART_RX_TX_IRQS;
+static PORT_Type *const s_uartPort[] = NXP_UART_PORTS;
+static clock_ip_name_t const s_uartPortClocks[] = NXP_UART_PORT_CLOCKS;
+static uint8_t const s_uartPIN_RX[] = NXP_UART_PIN_RX;
+static uint8_t const s_uartPIN_TX[] = NXP_UART_PIN_TX;
+
+static void uart_irq0(void);
+static void uart_irq1(void);
+static void uart_irq2(void);
+static void uart_irq3(void);
+static void uart_irq4(void);
+static void (*s_uartirqs[])(void) = {
+    uart_irq0, uart_irq1, uart_irq2, uart_irq3, uart_irq4
+};
+
+/*
+ * RING BUFFER FUNCTIONS
+ */
+
+static uint8_t
+ur_is_empty(struct uart_ring *ur)
+{
+    return (ur->ur_head == ur->ur_tail);
+}
+
+static uint8_t
+ur_is_full(struct uart_ring *ur)
+{
+    return (((ur->ur_tail + 1) % ur->ur_size) == ur->ur_head);
+}
+
+static void
+ur_bump(struct uart_ring *ur)
+{
+    if (!ur_is_empty(ur)) {
+        ur->ur_head++;
+        ur->ur_head %= ur->ur_size;
+        return;
+    }
+}
+
+static uint8_t
+ur_read(struct uart_ring *ur)
+{
+    return ur->ur_buf[ur->ur_head];
+}
+
+static int
+ur_queue(struct uart_ring *ur, uint8_t data)
+{
+    if (!ur_is_full(ur)) {
+        ur->ur_buf[ur->ur_tail] = data;
+        ur->ur_tail++;
+        ur->ur_tail %= ur->ur_size;
+        return 0;
+    }
+    return -1;
+}
+
+/*
+ * END RING BUFFER FUNCTIONS
+ */
+
+int
+hal_uart_init_cbs(int port,
+                  hal_uart_tx_char tx_func,
+                  hal_uart_tx_done tx_done,
+                  hal_uart_rx_char rx_func,
+                  void *arg)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    u->u_rx_func = rx_func;
+    u->u_tx_func = tx_func;
+    u->u_tx_done = tx_done;
+    u->u_func_arg = arg;
+
+    return 0;
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t byte)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    LPUART_WriteBlocking(u->u_base, &byte, 1);
+}
+
+static int
+hal_uart_tx_fill_buf(struct hal_uart *u)
+{
+    int data = 0;
+    int i = 0;
+    os_sr_t sr;
+
+    OS_ENTER_CRITICAL(sr);
+    while (!ur_is_full(&u->ur_tx)) {
+        if (u->u_tx_func) {
+            data = u->u_tx_func(u->u_func_arg);
+        }
+        if (data <= 0) {
+            break;
+        }
+        i++;
+        ur_queue(&u->ur_tx, data);
+    }
+    OS_EXIT_CRITICAL(sr);
+    return i;
+}
+
+void
+hal_uart_start_tx(int port)
+{
+    struct hal_uart *u;
+    int data = -1;
+    int rc;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    /* main loop */
+    while (true) {
+        /* add data to TX ring buffer */
+        if (u->u_tx_started == 0) {
+            rc = hal_uart_tx_fill_buf(u);
+            if (rc > 0) {
+                u->u_tx_started = 1;
+            }
+        }
+
+        /* Send data only when UART TX register is empty and TX ring buffer has data to send out. */
+        while (!ur_is_empty(&u->ur_tx) &&
+               (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base))) {
+            data = ur_read(&u->ur_tx);
+            LPUART_WriteByte(u->u_base, data);
+            ur_bump(&u->ur_tx);
+        }
+
+        if (ur_is_empty(&u->ur_tx)) {
+            if (u->u_tx_done) {
+                u->u_tx_done(u->u_func_arg);
+            }
+            u->u_tx_started = 0;
+            break;
+        }
+    }
+}
+
+void
+hal_uart_start_rx(int port)
+{
+    struct hal_uart *u;
+    os_sr_t sr;
+    int rc = 0;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    u->u_rx_stall = 0;
+
+    /* Send back what's in the RX ring buffer until it's empty or we get an
+     * error */
+    while ((rc >= 0) && !ur_is_empty(&u->ur_rx)) {
+        OS_ENTER_CRITICAL(sr);
+        rc = u->u_rx_func(u->u_func_arg, ur_read(&u->ur_rx));
+        if (rc >= 0) {
+            ur_bump(&u->ur_rx);
+        } else {
+            u->u_rx_stall = 1;
+        }
+        OS_EXIT_CRITICAL(sr);
+    }
+}
+
+static void
+uart_irq_handler(int port)
+{
+    struct hal_uart *u;
+    uint32_t status;
+    uint8_t data;
+
+    u = &uarts[port];
+    if (u->u_configured && u->u_open) {
+        status = LPUART_GetStatusFlags(u->u_base);
+        /* Check for RX data */
+        if (status & (kLPUART_RxDataRegFullFlag | kLPUART_RxOverrunFlag)) {
+            data = LPUART_ReadByte(u->u_base);
+            if (u->u_rx_stall || u->u_rx_func(u->u_func_arg, data) < 0) {
+                /*
+                 * RX queue full.
+                 */
+                u->u_rx_stall = 1;
+                ur_queue(&u->ur_rx, data);
+            }
+        }
+        /* Check for TX complete */
+        if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base)) {
+            if (u->u_tx_started) {
+                u->u_tx_started = 0;
+                if (u->u_tx_done) {
+                    u->u_tx_done(u->u_func_arg);
+                }
+            }
+        }
+    }
+}
+
+static void
+uart_irq0(void)
+{
+    uart_irq_handler(0);
+}
+
+static void
+uart_irq1(void)
+{
+    uart_irq_handler(1);
+}
+
+static void
+uart_irq2(void)
+{
+    uart_irq_handler(2);
+}
+
+static void
+uart_irq3(void)
+{
+    uart_irq_handler(3);
+}
+
+static void
+uart_irq4(void)
+{
+    uart_irq_handler(4);
+}
+
+int
+hal_uart_config(int port,
+                int32_t speed,
+                uint8_t databits,
+                uint8_t stopbits,
+                enum hal_uart_parity parity,
+                enum hal_uart_flow_ctl flow_ctl)
+{
+    struct hal_uart *u;
+    lpuart_config_t uconfig;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || u->u_open) {
+        return -1;
+    }
+
+    /* PIN config (all UARTs use kPORT_MuxAlt3) */
+    CLOCK_EnableClock(u->p_clock);
+    PORT_SetPinMux(u->p_base, u->u_pin_rx, kPORT_MuxAlt3);
+    PORT_SetPinMux(u->p_base, u->u_pin_tx, kPORT_MuxAlt3);
+
+    /* UART CONFIG */
+    CLOCK_SetLpuartClock(2U);
+
+    LPUART_GetDefaultConfig(&uconfig);
+    uconfig.baudRate_Bps = speed;
+
+    switch (databits) {
+    case 8:
+        uconfig.dataBitsCount = kLPUART_EightDataBits;
+        break;
+    case 7:
+#if FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        uconfig.dataBitsCount = kLPUART_SevenDataBits;
+        break;
+#endif /* Fallthrought */
+    default:
+        uconfig.parityMode = kLPUART_ParityEven;
+        return -1;

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,623 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type *dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void *txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);

Review comment:
       Addressed, good catch.

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,623 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type *dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void *txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave *) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }
+    return 0;
+}
+
+int
+hal_spi_enable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (spi->enabled) {
+        return 0;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        DSPI_MasterInit(spi->dev,
+                        &master->config,
+                        CLOCK_GetFreq(kCLOCK_BusClk));
+    } else {
+        slave = (struct nxp_spi_slave *) spi;
+        DSPI_SlaveInit(spi->dev, &slave->config);
+    }
+
+    spi->enabled = true;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_SetVector(spi->irqn, (uint32_t) spi->irq_handler);
+    NVIC_EnableIRQ(spi->irqn);
+    return 0;
+}
+
+int
+hal_spi_disable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (!spi->enabled) {
+        return 0;
+    }
+
+    DSPI_Deinit(spi->dev);
+
+    spi->enabled = false;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_DisableIRQ(spi->irqn);
+    return 0;
+}
+
+uint16_t
+hal_spi_tx_val(int spi_num, uint16_t val)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    uint16_t retval = 0;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t *) &val;
+        xfer.rxData = (uint8_t *) &retval;
+        xfer.dataSize = 1;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return retval;
+    }
+    return 0xFFFF; /* Invalid API. */
+}
+
+int
+hal_spi_txrx(int spi_num, void *txbuf, void *rxbuf, int len)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    status_t rc;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t *) txbuf;
+        xfer.rxData = (uint8_t *) rxbuf;
+        xfer.dataSize = len;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        rc = DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return (rc == kStatus_Success) ? 0 : rc;

Review comment:
       Addressed, good catch!

##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,408 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type *dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *user_data)
+{
+    struct nxp_hal_i2c *i2c = userData;

Review comment:
       I did!

##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,408 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type *dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *user_data)
+{
+    struct nxp_hal_i2c *i2c = userData;

Review comment:
       I did! You are too fast!




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[GitHub] [mynewt-core] utzig commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
utzig commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570142953



##########
File path: hw/mcu/nxp/kinetis/src/hal_hw_id.c
##########
@@ -22,26 +22,27 @@
 
 #include <hal/hal_bsp.h>
 
-#include "MK64F12.h"
+#include "fsl_sim.h"
 
 #ifndef min
 #define min(a, b) ((a)<(b)?(a):(b))
 #endif
 
-#define MK64F12_HW_ID_LEN     7
+#define MK8xF_HW_ID_LEN sizeof(sim_uid_t)

Review comment:
       Should be called `KINETIS_HW_ID_LEN` or some similar family name.

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,624 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type* dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void* txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave*) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }
+    return 0;
+}
+
+int
+hal_spi_enable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (spi->enabled) {
+        return 0;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+    master = (struct nxp_spi_master*) spi;
+    DSPI_MasterInit(spi->dev,
+                    &master->config,
+                    CLOCK_GetFreq(kCLOCK_BusClk));
+    } else {
+    slave = (struct nxp_spi_slave*) spi;
+    DSPI_SlaveInit(spi->dev, &slave->config);
+    }

Review comment:
       `if` and `else` blocks are indented incorrectly.

##########
File path: hw/mcu/nxp/kinetis/src/hal_lpuart.c
##########
@@ -0,0 +1,460 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+
+#include "os/mynewt.h"
+#include "hal/hal_uart.h"
+#include "hal/hal_gpio.h"
+#include "hal/hal_system.h"
+#include "mcu/cmsis_nvic.h"
+#include "bsp/bsp.h"
+
+#include "mcu/frdm-k8xf_hal.h"

Review comment:
       Don't other Kinetis MCU families also support LP-UARTS?

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
+
+    /* Clear Tx FIFO */
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    /* Write enable */
+    cmd_write_enable();
+
+    /* Write data into TX FIFO, needs to write at least 16 bytes of data */
+    QSPI_WriteBlocking(QuadSPI0, val, 16U);
+
+    /* Set seq id, write register */
+    QSPI_ExecuteIPCommand(QuadSPI0, 20);
+
+    /* Wait until finished */
+    check_if_finished();
+}
+
+static int
+nxp_qspi_init(const struct hal_flash *dev)
+{
+    qspi_config_t qspi_cfg = {0};
+
+    /*Get QSPI default settings and configure the qspi */
+    QSPI_GetDefaultQspiConfig(&qspi_cfg);
+
+    /*Set AHB buffer size for reading data through AHB bus */
+/* #if MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) <= FSL_FEATURE_QSPI_AHB_BUFFER_SIZE */
+    qspi_cfg.AHBbufferSize[3] = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+/* #else */
+/*     qspi_cfg.AHBbufferSize[3] = FSL_FEATURE_QSPI_AHB_BUFFER_SIZE; */
+/* #endif */
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SCKA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SSA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA0), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA1), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA2), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIO3A), MYNEWT_VAL(QSPIA_MUX));
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SCKB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SSB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB0), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB1), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB2), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOBA), MYNEWT_VAL(QSPIB_MUX));
+
+    //Configure the baudrate too.
+
+    QSPI_Init(QuadSPI0, &qspi_cfg, CLOCK_GetFreq(kCLOCK_McgPll0Clk));
+
+    memcpy(g_qspi_flash_cfg.lookuptable, lut, sizeof(lut));
+    /*According to serial flash feature to configure flash settings */
+    QSPI_SetFlashConfig(QuadSPI0, &g_qspi_flash_cfg);
+
+#if FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC
+    QSPI_ClearCache(QuadSPI0);
+#endif
+
+    enable_quad_mode();
+    return 0;
+}
+
+static const struct hal_flash_funcs nxp_qspi_funcs = {
+        .hff_read = nxp_qspi_read,
+        .hff_write = nxp_qspi_write,
+        .hff_erase_sector = nxp_qspi_erase_sector,
+        .hff_sector_info = nxp_qspi_sector_info,
+        .hff_init = nxp_qspi_init,
+        .hff_erase = nxp_qspi_erase
+    };
+
+const struct hal_flash nxp_qspi_dev = {
+        .hf_itf = &nxp_qspi_funcs,
+        .hf_base_addr = FSL_FEATURE_QSPI_AMBA_BASE,
+        .hf_size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE),
+        .hf_sector_cnt = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT),
+        .hf_align = 8,
+        .hf_erased_val = 0xff,
+    };

Review comment:
       Both structs need to be dedented.

##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,412 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type* dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port; 
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *userData)
+{
+    struct nxp_hal_i2c *i2c = userData;
+    i2c->stat = status;
+    os_sem_release(&i2c->sync);
+}
+
+static struct nxp_hal_i2c*
+hal_i2c_resolve(uint8_t i2c_num)
+{
+    if (i2c_num >= NXP_HAL_I2C_MAX) {
+        return NULL;
+    }
+
+    return i2c_modules[i2c_num];
+}
+
+static void
+i2c_init_hw(struct nxp_hal_i2c *i2c, int pin_scl, int pin_sda)
+{
+    uint32_t clock_freq;
+    i2c_master_config_t master_cfg;
+
+    const port_pin_config_t pincfg = {
+        kPORT_PullUp,
+        kPORT_FastSlewRate,
+        kPORT_PassiveFilterDisable,
+        kPORT_OpenDrainEnable,
+        kPORT_LowDriveStrength,
+        i2c->mux,
+        kPORT_UnlockRegister
+    };
+    PORT_SetPinConfig(i2c->port, i2c->scl_pin, &pincfg);
+    PORT_SetPinConfig(i2c->port, i2c->sda_pin, &pincfg);
+
+    clock_freq = CLOCK_GetFreq(kCLOCK_BusClk);
+    I2C_MasterGetDefaultConfig(&master_cfg);
+    I2C_MasterInit(i2c->dev, &master_cfg, clock_freq);
+
+    I2C_MasterTransferCreateHandle(i2c->dev, &i2c->handle, master_xfer_cb, i2c);
+    NVIC_ClearPendingIRQ(i2c->irqn);
+    NVIC_SetVector(i2c->irqn, (uint32_t) i2c->irq_handler);
+    NVIC_EnableIRQ(i2c->irqn);
+}
+
+static int
+i2c_config(struct nxp_hal_i2c *i2c, uint32_t frequency)
+{
+    uint32_t clock_freq;
+    uint32_t baudrate;
+
+    switch (frequency) {
+    case 100:
+        baudrate = 100000U;
+        break;
+    case 400:
+        baudrate = 400000U;
+        break;
+    case 1000:
+        baudrate = 1000000U;
+        break;
+    default:

Review comment:
       Could also be:
   
   ```
       case 100: /* fallthrough */
       case 400: /* fallthrough */
       case 1000:
           baudrate = frequency * 1000;
           break;
   ```

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,624 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type* dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void* txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave*) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }
+    return 0;
+}
+
+int
+hal_spi_enable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (spi->enabled) {
+        return 0;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+    master = (struct nxp_spi_master*) spi;
+    DSPI_MasterInit(spi->dev,
+                    &master->config,
+                    CLOCK_GetFreq(kCLOCK_BusClk));
+    } else {
+    slave = (struct nxp_spi_slave*) spi;
+    DSPI_SlaveInit(spi->dev, &slave->config);
+    }
+
+    spi->enabled = true;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_SetVector(spi->irqn, (uint32_t) spi->irq_handler);
+    NVIC_EnableIRQ(spi->irqn);
+    return 0;
+}
+
+int
+hal_spi_disable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (!spi->enabled) {
+        return 0;
+    }
+
+    DSPI_Deinit(spi->dev);
+
+    spi->enabled = false;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_DisableIRQ(spi->irqn);
+    return 0;
+}
+
+uint16_t
+hal_spi_tx_val(int spi_num, uint16_t val)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    uint16_t retval = 0;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t*) &val;
+        xfer.rxData = (uint8_t*) &retval;
+        xfer.dataSize = 1;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return retval;
+    }
+    return 0xFFFF; /* Invalid API. */
+}
+
+int
+hal_spi_txrx(int spi_num, void *txbuf, void *rxbuf, int len)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    status_t rc;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t*) txbuf;
+        xfer.rxData = (uint8_t*) rxbuf;
+        xfer.dataSize = len;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        rc = DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return (rc == kStatus_Success) ? 0 : rc;
+    }
+    return -1;
+}
+
+int
+hal_spi_set_txrx_cb(int spi_num, hal_spi_txrx_cb txrx_cb, void *arg)
+{
+    struct nxp_hal_spi *spi;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    spi->txrx_cb = txrx_cb;
+    spi->txrx_cb_arg = arg;
+    return 0;
+}
+
+int
+hal_spi_txrx_noblock(int spi_num, void *txbuf, void *rxbuf, int len)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_transfer_t xfer;
+    status_t rc;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+        //master->handle

Review comment:
       Remove the comment.

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
+
+    /* Clear Tx FIFO */
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    /* Write enable */
+    cmd_write_enable();
+
+    /* Write data into TX FIFO, needs to write at least 16 bytes of data */
+    QSPI_WriteBlocking(QuadSPI0, val, 16U);
+
+    /* Set seq id, write register */
+    QSPI_ExecuteIPCommand(QuadSPI0, 20);
+
+    /* Wait until finished */
+    check_if_finished();
+}
+
+static int
+nxp_qspi_init(const struct hal_flash *dev)
+{
+    qspi_config_t qspi_cfg = {0};
+
+    /*Get QSPI default settings and configure the qspi */
+    QSPI_GetDefaultQspiConfig(&qspi_cfg);
+
+    /*Set AHB buffer size for reading data through AHB bus */
+/* #if MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) <= FSL_FEATURE_QSPI_AHB_BUFFER_SIZE */
+    qspi_cfg.AHBbufferSize[3] = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+/* #else */
+/*     qspi_cfg.AHBbufferSize[3] = FSL_FEATURE_QSPI_AHB_BUFFER_SIZE; */
+/* #endif */

Review comment:
       Commented out code should be removed?

##########
File path: hw/mcu/nxp/kinetis/src/hal_lpuart.c
##########
@@ -0,0 +1,460 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+
+#include "os/mynewt.h"
+#include "hal/hal_uart.h"
+#include "hal/hal_gpio.h"
+#include "hal/hal_system.h"
+#include "mcu/cmsis_nvic.h"
+#include "bsp/bsp.h"
+
+#include "mcu/frdm-k8xf_hal.h"
+#include "syscfg/syscfg.h"
+#include "mcu/kinetis_common.h"
+
+#include "fsl_clock.h"
+#include "fsl_port.h"
+#include "fsl_lpuart.h"
+
+#include "hal_lpuart_nxp.h"
+
+/*! @brief Ring buffer size (Unit: Byte). */
+#define TX_BUF_SZ  32
+#define RX_BUF_SZ  128
+
+struct uart_ring {
+    uint16_t ur_head;
+    uint16_t ur_tail;
+    uint16_t ur_size;
+    uint8_t _pad;
+    uint8_t *ur_buf;
+};
+
+struct hal_uart {
+    LPUART_Type      *u_base;
+    clock_name_t     clk_src;
+    uint32_t         u_irq;
+    PORT_Type       *p_base;
+    clock_ip_name_t  p_clock;
+    int  u_pin_rx;
+    int  u_pin_tx;
+    /* TODO: support flow control pins */
+    hal_uart_rx_char u_rx_func;
+    hal_uart_tx_char u_tx_func;
+    hal_uart_tx_done u_tx_done;
+    void *u_func_arg;
+    uint8_t u_configured:1;
+    uint8_t u_open:1;
+    uint8_t u_tx_started:1;
+    uint8_t u_rx_stall:1;
+    struct uart_ring ur_tx;
+    uint8_t tx_buffer[TX_BUF_SZ];
+    struct uart_ring ur_rx;
+    uint8_t rx_buffer[RX_BUF_SZ];
+};
+
+/* UART configurations */
+static struct hal_uart uarts[FSL_FEATURE_SOC_LPUART_COUNT];
+
+static uint8_t const s_uartExists[] = NXP_UART_EXISTS;
+static uint8_t const s_uartEnabled[] = NXP_UART_ENABLED;
+static LPUART_Type *const s_uartBases[] = LPUART_BASE_PTRS;
+static clock_name_t s_uartClocks[] = NXP_UART_CLOCKS;
+static uint8_t const s_uartIRQ[] = LPUART_RX_TX_IRQS;
+static PORT_Type *const s_uartPort[] = NXP_UART_PORTS;
+static clock_ip_name_t const s_uartPortClocks[] = NXP_UART_PORT_CLOCKS;
+static uint8_t const s_uartPIN_RX[] = NXP_UART_PIN_RX;
+static uint8_t const s_uartPIN_TX[] = NXP_UART_PIN_TX;
+
+static void uart_irq0(void);
+static void uart_irq1(void);
+static void uart_irq2(void);
+static void uart_irq3(void);
+static void uart_irq4(void);
+static void (*s_uartirqs[])(void) = {
+    uart_irq0, uart_irq1, uart_irq2, uart_irq3, uart_irq4
+};
+
+/*
+ * RING BUFFER FUNCTIONS
+ */
+
+static uint8_t ur_is_empty(struct uart_ring *ur)
+{
+    return (ur->ur_head == ur->ur_tail);
+}
+
+static uint8_t ur_is_full(struct uart_ring *ur)
+{
+    return (((ur->ur_tail + 1) % ur->ur_size) == ur->ur_head);
+}
+
+static void ur_bump(struct uart_ring *ur)
+{
+    if (!ur_is_empty(ur)) {
+        ur->ur_head++;
+        ur->ur_head %= ur->ur_size;
+        return;
+    }
+}
+
+static uint8_t ur_read(struct uart_ring *ur)
+{
+    return ur->ur_buf[ur->ur_head];
+}
+
+static int ur_queue(struct uart_ring *ur, uint8_t data)
+{
+    if (!ur_is_full(ur)) {
+        ur->ur_buf[ur->ur_tail] = data;
+        ur->ur_tail++;
+        ur->ur_tail %= ur->ur_size;
+        return 0;
+    }
+    return -1;
+}
+
+/*
+ * END RING BUFFER FUNCTIONS
+ */
+
+int hal_uart_init_cbs(int port,
+                      hal_uart_tx_char tx_func,
+                      hal_uart_tx_done tx_done,
+                      hal_uart_rx_char rx_func,
+                      void *arg)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    u->u_rx_func = rx_func;
+    u->u_tx_func = tx_func;
+    u->u_tx_done = tx_done;
+    u->u_func_arg = arg;
+
+    return 0;
+}
+
+void hal_uart_blocking_tx(int port, uint8_t byte)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    LPUART_WriteBlocking(u->u_base, &byte, 1);
+}
+
+static int
+hal_uart_tx_fill_buf(struct hal_uart *u)
+{
+    int data = 0;
+    int i = 0;
+    os_sr_t sr;
+
+    OS_ENTER_CRITICAL(sr);
+    while (!ur_is_full(&u->ur_tx)) {
+        if (u->u_tx_func) {
+            data = u->u_tx_func(u->u_func_arg);
+        }
+        if (data <= 0) {
+            break;
+        }
+        i++;
+        ur_queue(&u->ur_tx, data);
+    }
+    OS_EXIT_CRITICAL(sr);
+    return i;
+}
+
+void hal_uart_start_tx(int port)
+{
+    struct hal_uart *u;
+    int data = -1;
+    int rc;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    /* main loop */
+    while (true)
+    {
+        /* add data to TX ring buffer */
+        if (u->u_tx_started == 0) {
+            rc = hal_uart_tx_fill_buf(u);
+            if (rc > 0) {
+                u->u_tx_started = 1;
+            }
+        }
+
+        /* Send data only when UART TX register is empty and TX ring buffer has data to send out. */
+        while (!ur_is_empty(&u->ur_tx) &&
+               (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base))) {
+            data = ur_read(&u->ur_tx);
+            LPUART_WriteByte(u->u_base, data);
+            ur_bump(&u->ur_tx);
+        }
+
+        if (ur_is_empty(&u->ur_tx)) {
+            if (u->u_tx_done) {
+                u->u_tx_done(u->u_func_arg);
+            }
+            u->u_tx_started = 0;
+            break;
+        }
+    }
+}
+
+void
+hal_uart_start_rx(int port)
+{
+    struct hal_uart *u;
+    os_sr_t sr;
+    int rc = 0;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    u->u_rx_stall = 0;
+
+    /* Send back what's in the RX ring buffer until it's empty or we get an
+     * error */
+    while ((rc >= 0) && !ur_is_empty(&u->ur_rx)) {
+        OS_ENTER_CRITICAL(sr);
+        rc = u->u_rx_func(u->u_func_arg, ur_read(&u->ur_rx));
+        if (rc >= 0) {
+            ur_bump(&u->ur_rx);
+        } else {
+            u->u_rx_stall = 1;
+        }
+        OS_EXIT_CRITICAL(sr);
+    }
+}
+
+static void
+uart_irq_handler(int port)
+{
+    struct hal_uart *u;
+    uint32_t status;
+    uint8_t data;
+
+    u = &uarts[port];
+    if (u->u_configured && u->u_open) {
+        status = LPUART_GetStatusFlags(u->u_base);
+        /* Check for RX data */
+        if (status & (kLPUART_RxDataRegFullFlag | kLPUART_RxOverrunFlag)) {
+            data = LPUART_ReadByte(u->u_base);
+            if (u->u_rx_stall || u->u_rx_func(u->u_func_arg, data) < 0) {
+                /*
+                 * RX queue full.
+                 */
+                u->u_rx_stall = 1;
+                ur_queue(&u->ur_rx, data);
+            }
+        }
+        /* Check for TX complete */
+        if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base)) {
+            if (u->u_tx_started) {
+                u->u_tx_started = 0;
+                if (u->u_tx_done)
+                    u->u_tx_done(u->u_func_arg);
+            }
+        }
+    }
+}
+
+static void
+uart_irq0(void)
+{
+    uart_irq_handler(0);
+}
+
+static void
+uart_irq1(void)
+{
+    uart_irq_handler(1);
+}
+
+static void
+uart_irq2(void)
+{
+    uart_irq_handler(2);
+}
+
+static void
+uart_irq3(void)
+{
+    uart_irq_handler(3);
+}
+
+static void
+uart_irq4(void)
+{
+    uart_irq_handler(4);
+}
+
+int
+hal_uart_config(int port,
+                int32_t speed,
+                uint8_t databits,
+                uint8_t stopbits,
+                enum hal_uart_parity parity,
+                enum hal_uart_flow_ctl flow_ctl)
+{
+    struct hal_uart *u;
+    lpuart_config_t uconfig;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || u->u_open) {
+        return -1;
+    }
+
+    /* PIN config (all UARTs use kPORT_MuxAlt3) */
+    CLOCK_EnableClock(u->p_clock);
+    PORT_SetPinMux(u->p_base, u->u_pin_rx, kPORT_MuxAlt3);
+    PORT_SetPinMux(u->p_base, u->u_pin_tx, kPORT_MuxAlt3);
+
+    /* UART CONFIG */
+    CLOCK_SetLpuartClock(2U);
+
+    LPUART_GetDefaultConfig(&uconfig);
+    uconfig.baudRate_Bps = speed;
+
+    /* TODO: only handles 8 databits currently */
+    switch (stopbits) {
+    case 1:
+        uconfig.stopBitCount = kLPUART_OneStopBit;
+        break;
+    case 2:
+        uconfig.stopBitCount = kLPUART_TwoStopBit;
+        break;
+    default:
+        return -1;
+    }
+
+    switch (parity) {
+    case HAL_UART_PARITY_NONE:
+        uconfig.parityMode = kLPUART_ParityDisabled;
+        break;
+    case HAL_UART_PARITY_ODD:
+        uconfig.parityMode = kLPUART_ParityOdd;
+        break;
+    case HAL_UART_PARITY_EVEN:
+        uconfig.parityMode = kLPUART_ParityEven;
+        break;
+    }
+
+    /* TODO: HW flow control not supported */
+    assert(flow_ctl == HAL_UART_FLOW_CTL_NONE);

Review comment:
       Maybe `return -1`?

##########
File path: hw/mcu/nxp/kinetis/src/hal_flash.c
##########
@@ -0,0 +1,178 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+*
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * Internal flash for MK82F25615.

Review comment:
       Not just `MK82F25615` but the `Kinetis family`

##########
File path: hw/mcu/nxp/kinetis/src/hal_watchdog.c
##########
@@ -25,7 +25,7 @@
 #include "fsl_wdog.h"
 #include "fsl_rcm.h"
 
-/* #define WATCHDOG_STUB */
+//#define WATCHDOG_STUB

Review comment:
       You can just remove this line.

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
+
+    /* Clear Tx FIFO */
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    /* Write enable */
+    cmd_write_enable();
+
+    /* Write data into TX FIFO, needs to write at least 16 bytes of data */
+    QSPI_WriteBlocking(QuadSPI0, val, 16U);
+
+    /* Set seq id, write register */
+    QSPI_ExecuteIPCommand(QuadSPI0, 20);
+
+    /* Wait until finished */
+    check_if_finished();
+}
+
+static int
+nxp_qspi_init(const struct hal_flash *dev)
+{
+    qspi_config_t qspi_cfg = {0};
+
+    /*Get QSPI default settings and configure the qspi */
+    QSPI_GetDefaultQspiConfig(&qspi_cfg);
+
+    /*Set AHB buffer size for reading data through AHB bus */
+/* #if MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) <= FSL_FEATURE_QSPI_AHB_BUFFER_SIZE */
+    qspi_cfg.AHBbufferSize[3] = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+/* #else */
+/*     qspi_cfg.AHBbufferSize[3] = FSL_FEATURE_QSPI_AHB_BUFFER_SIZE; */
+/* #endif */
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SCKA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SSA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA0), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA1), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA2), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIO3A), MYNEWT_VAL(QSPIA_MUX));
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SCKB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SSB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB0), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB1), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB2), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOBA), MYNEWT_VAL(QSPIB_MUX));
+
+    //Configure the baudrate too.

Review comment:
       A `TODO`?

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */

Review comment:
       Should all those commented out lines be removed?

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }

Review comment:
       Can be all on the same line?




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[GitHub] [mynewt-core] utzig commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
utzig commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570630077



##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,408 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type *dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *user_data)
+{
+    struct nxp_hal_i2c *i2c = userData;

Review comment:
       I believe you also have to fix this one! :-)




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[GitHub] [mynewt-core] mlaz commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
mlaz commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570523751



##########
File path: hw/mcu/nxp/kinetis/src/hal_lpuart.c
##########
@@ -0,0 +1,460 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+
+#include "os/mynewt.h"
+#include "hal/hal_uart.h"
+#include "hal/hal_gpio.h"
+#include "hal/hal_system.h"
+#include "mcu/cmsis_nvic.h"
+#include "bsp/bsp.h"
+
+#include "mcu/frdm-k8xf_hal.h"
+#include "syscfg/syscfg.h"
+#include "mcu/kinetis_common.h"
+
+#include "fsl_clock.h"
+#include "fsl_port.h"
+#include "fsl_lpuart.h"
+
+#include "hal_lpuart_nxp.h"
+
+/*! @brief Ring buffer size (Unit: Byte). */
+#define TX_BUF_SZ  32
+#define RX_BUF_SZ  128
+
+struct uart_ring {
+    uint16_t ur_head;
+    uint16_t ur_tail;
+    uint16_t ur_size;
+    uint8_t _pad;
+    uint8_t *ur_buf;
+};
+
+struct hal_uart {
+    LPUART_Type      *u_base;
+    clock_name_t     clk_src;
+    uint32_t         u_irq;
+    PORT_Type       *p_base;
+    clock_ip_name_t  p_clock;
+    int  u_pin_rx;
+    int  u_pin_tx;
+    /* TODO: support flow control pins */
+    hal_uart_rx_char u_rx_func;
+    hal_uart_tx_char u_tx_func;
+    hal_uart_tx_done u_tx_done;
+    void *u_func_arg;
+    uint8_t u_configured:1;
+    uint8_t u_open:1;
+    uint8_t u_tx_started:1;
+    uint8_t u_rx_stall:1;
+    struct uart_ring ur_tx;
+    uint8_t tx_buffer[TX_BUF_SZ];
+    struct uart_ring ur_rx;
+    uint8_t rx_buffer[RX_BUF_SZ];
+};
+
+/* UART configurations */
+static struct hal_uart uarts[FSL_FEATURE_SOC_LPUART_COUNT];
+
+static uint8_t const s_uartExists[] = NXP_UART_EXISTS;
+static uint8_t const s_uartEnabled[] = NXP_UART_ENABLED;
+static LPUART_Type *const s_uartBases[] = LPUART_BASE_PTRS;
+static clock_name_t s_uartClocks[] = NXP_UART_CLOCKS;
+static uint8_t const s_uartIRQ[] = LPUART_RX_TX_IRQS;
+static PORT_Type *const s_uartPort[] = NXP_UART_PORTS;
+static clock_ip_name_t const s_uartPortClocks[] = NXP_UART_PORT_CLOCKS;
+static uint8_t const s_uartPIN_RX[] = NXP_UART_PIN_RX;
+static uint8_t const s_uartPIN_TX[] = NXP_UART_PIN_TX;
+
+static void uart_irq0(void);
+static void uart_irq1(void);
+static void uart_irq2(void);
+static void uart_irq3(void);
+static void uart_irq4(void);
+static void (*s_uartirqs[])(void) = {
+    uart_irq0, uart_irq1, uart_irq2, uart_irq3, uart_irq4
+};
+
+/*
+ * RING BUFFER FUNCTIONS
+ */
+
+static uint8_t ur_is_empty(struct uart_ring *ur)
+{
+    return (ur->ur_head == ur->ur_tail);
+}
+
+static uint8_t ur_is_full(struct uart_ring *ur)
+{
+    return (((ur->ur_tail + 1) % ur->ur_size) == ur->ur_head);
+}
+
+static void ur_bump(struct uart_ring *ur)
+{
+    if (!ur_is_empty(ur)) {
+        ur->ur_head++;
+        ur->ur_head %= ur->ur_size;
+        return;
+    }
+}
+
+static uint8_t ur_read(struct uart_ring *ur)
+{
+    return ur->ur_buf[ur->ur_head];
+}
+
+static int ur_queue(struct uart_ring *ur, uint8_t data)
+{
+    if (!ur_is_full(ur)) {
+        ur->ur_buf[ur->ur_tail] = data;
+        ur->ur_tail++;
+        ur->ur_tail %= ur->ur_size;
+        return 0;
+    }
+    return -1;
+}
+
+/*
+ * END RING BUFFER FUNCTIONS
+ */
+
+int hal_uart_init_cbs(int port,
+                      hal_uart_tx_char tx_func,
+                      hal_uart_tx_done tx_done,
+                      hal_uart_rx_char rx_func,
+                      void *arg)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    u->u_rx_func = rx_func;
+    u->u_tx_func = tx_func;
+    u->u_tx_done = tx_done;
+    u->u_func_arg = arg;
+
+    return 0;
+}
+
+void hal_uart_blocking_tx(int port, uint8_t byte)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    LPUART_WriteBlocking(u->u_base, &byte, 1);
+}
+
+static int
+hal_uart_tx_fill_buf(struct hal_uart *u)
+{
+    int data = 0;
+    int i = 0;
+    os_sr_t sr;
+
+    OS_ENTER_CRITICAL(sr);
+    while (!ur_is_full(&u->ur_tx)) {
+        if (u->u_tx_func) {
+            data = u->u_tx_func(u->u_func_arg);
+        }
+        if (data <= 0) {
+            break;
+        }
+        i++;
+        ur_queue(&u->ur_tx, data);
+    }
+    OS_EXIT_CRITICAL(sr);
+    return i;
+}
+
+void hal_uart_start_tx(int port)
+{
+    struct hal_uart *u;
+    int data = -1;
+    int rc;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    /* main loop */
+    while (true)
+    {
+        /* add data to TX ring buffer */
+        if (u->u_tx_started == 0) {
+            rc = hal_uart_tx_fill_buf(u);
+            if (rc > 0) {
+                u->u_tx_started = 1;
+            }
+        }
+
+        /* Send data only when UART TX register is empty and TX ring buffer has data to send out. */
+        while (!ur_is_empty(&u->ur_tx) &&
+               (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base))) {
+            data = ur_read(&u->ur_tx);
+            LPUART_WriteByte(u->u_base, data);
+            ur_bump(&u->ur_tx);
+        }
+
+        if (ur_is_empty(&u->ur_tx)) {
+            if (u->u_tx_done) {
+                u->u_tx_done(u->u_func_arg);
+            }
+            u->u_tx_started = 0;
+            break;
+        }
+    }
+}
+
+void
+hal_uart_start_rx(int port)
+{
+    struct hal_uart *u;
+    os_sr_t sr;
+    int rc = 0;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    u->u_rx_stall = 0;
+
+    /* Send back what's in the RX ring buffer until it's empty or we get an
+     * error */
+    while ((rc >= 0) && !ur_is_empty(&u->ur_rx)) {
+        OS_ENTER_CRITICAL(sr);
+        rc = u->u_rx_func(u->u_func_arg, ur_read(&u->ur_rx));
+        if (rc >= 0) {
+            ur_bump(&u->ur_rx);
+        } else {
+            u->u_rx_stall = 1;
+        }
+        OS_EXIT_CRITICAL(sr);
+    }
+}
+
+static void
+uart_irq_handler(int port)
+{
+    struct hal_uart *u;
+    uint32_t status;
+    uint8_t data;
+
+    u = &uarts[port];
+    if (u->u_configured && u->u_open) {
+        status = LPUART_GetStatusFlags(u->u_base);
+        /* Check for RX data */
+        if (status & (kLPUART_RxDataRegFullFlag | kLPUART_RxOverrunFlag)) {
+            data = LPUART_ReadByte(u->u_base);
+            if (u->u_rx_stall || u->u_rx_func(u->u_func_arg, data) < 0) {
+                /*
+                 * RX queue full.
+                 */
+                u->u_rx_stall = 1;
+                ur_queue(&u->ur_rx, data);
+            }
+        }
+        /* Check for TX complete */
+        if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base)) {
+            if (u->u_tx_started) {
+                u->u_tx_started = 0;
+                if (u->u_tx_done)
+                    u->u_tx_done(u->u_func_arg);
+            }
+        }
+    }
+}
+
+static void
+uart_irq0(void)
+{
+    uart_irq_handler(0);
+}
+
+static void
+uart_irq1(void)
+{
+    uart_irq_handler(1);
+}
+
+static void
+uart_irq2(void)
+{
+    uart_irq_handler(2);
+}
+
+static void
+uart_irq3(void)
+{
+    uart_irq_handler(3);
+}
+
+static void
+uart_irq4(void)
+{
+    uart_irq_handler(4);
+}
+
+int
+hal_uart_config(int port,
+                int32_t speed,
+                uint8_t databits,
+                uint8_t stopbits,
+                enum hal_uart_parity parity,
+                enum hal_uart_flow_ctl flow_ctl)
+{
+    struct hal_uart *u;
+    lpuart_config_t uconfig;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || u->u_open) {
+        return -1;
+    }
+
+    /* PIN config (all UARTs use kPORT_MuxAlt3) */
+    CLOCK_EnableClock(u->p_clock);
+    PORT_SetPinMux(u->p_base, u->u_pin_rx, kPORT_MuxAlt3);
+    PORT_SetPinMux(u->p_base, u->u_pin_tx, kPORT_MuxAlt3);
+
+    /* UART CONFIG */
+    CLOCK_SetLpuartClock(2U);
+
+    LPUART_GetDefaultConfig(&uconfig);
+    uconfig.baudRate_Bps = speed;
+
+    /* TODO: only handles 8 databits currently */
+    switch (stopbits) {
+    case 1:
+        uconfig.stopBitCount = kLPUART_OneStopBit;
+        break;
+    case 2:
+        uconfig.stopBitCount = kLPUART_TwoStopBit;
+        break;
+    default:
+        return -1;
+    }
+
+    switch (parity) {
+    case HAL_UART_PARITY_NONE:
+        uconfig.parityMode = kLPUART_ParityDisabled;
+        break;
+    case HAL_UART_PARITY_ODD:
+        uconfig.parityMode = kLPUART_ParityOdd;
+        break;
+    case HAL_UART_PARITY_EVEN:
+        uconfig.parityMode = kLPUART_ParityEven;
+        break;
+    }
+
+    /* TODO: HW flow control not supported */
+    assert(flow_ctl == HAL_UART_FLOW_CTL_NONE);

Review comment:
       Addressed, good catch.

##########
File path: hw/mcu/nxp/kinetis/src/hal_lpuart.c
##########
@@ -0,0 +1,460 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+
+#include "os/mynewt.h"
+#include "hal/hal_uart.h"
+#include "hal/hal_gpio.h"
+#include "hal/hal_system.h"
+#include "mcu/cmsis_nvic.h"
+#include "bsp/bsp.h"
+
+#include "mcu/frdm-k8xf_hal.h"

Review comment:
       Addressed.




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[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot removed a comment on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-772985567


   
   <!-- style-bot -->
   
   ## Style check summary
   
   ### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
   
   
   #### hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c
   <details>
   
   ```diff
   @@ -187,15 +187,15 @@
     ******************************************************************************/
    
    #ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
   -static void CLOCK_FllStableDelay(void)
   +static void
   +CLOCK_FllStableDelay(void)
    {
        /*
           Should wait at least 1ms. Because in these modes, the core clock is 100MHz
           at most, so this function could obtain the 1ms delay.
         */
        volatile uint32_t i = 30000U;
   -    while (0U != (i--))
   -    {
   +    while (0U != (i--)) {
            __NOP();
        }
    }
   @@ -207,34 +207,35 @@
    extern void CLOCK_FllStableDelay(void);
    #endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */
    
   -static uint32_t CLOCK_GetMcgExtClkFreq(void)
   +static uint32_t
   +CLOCK_GetMcgExtClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (MCG_C7_OSCSEL_VAL)
   -    {
   -        case 0U:
   -            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   -            assert(0U != g_xtal0Freq);
   -            freq = g_xtal0Freq;
   -            break;
   -        case 1U:
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(0U != g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 2U:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (MCG_C7_OSCSEL_VAL) {
   +    case 0U:
   +        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   +        assert(0U != g_xtal0Freq);
   +        freq = g_xtal0Freq;
   +        break;
   +    case 1U:
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(0U != g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 2U:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllExtRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllExtRefClkFreq(void)
    {
        /* FllExtRef = McgExtRef / FllExtRefDiv */
        uint8_t frdiv;
   @@ -246,54 +247,50 @@
        frdiv = MCG_C1_FRDIV_VAL;
        freq >>= frdiv;
    
   -    range  = MCG_C2_RANGE_VAL;
   +    range = MCG_C2_RANGE_VAL;
        oscsel = MCG_C7_OSCSEL_VAL;
    
        /*
           When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536.
           1. MCG_C7[OSCSEL] selects IRC48M.
           2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0.
   -    */
   -    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel))
   -    {
   -        switch (frdiv)
   -        {
   -            case 0:
   -            case 1:
   -            case 2:
   -            case 3:
   -            case 4:
   -            case 5:
   -                freq >>= 5u;
   -                break;
   -            case 6:
   -                /* 64*20=1280 */
   -                freq /= 20u;
   -                break;
   -            case 7:
   -                /* 128*12=1536 */
   -                freq /= 12u;
   -                break;
   -            default:
   -                freq = 0u;
   -                break;
   +     */
   +    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel)) {
   +        switch (frdiv) {
   +        case 0:
   +        case 1:
   +        case 2:
   +        case 3:
   +        case 4:
   +        case 5:
   +            freq >>= 5u;
   +            break;
   +        case 6:
   +            /* 64*20=1280 */
   +            freq /= 20u;
   +            break;
   +        case 7:
   +            /* 128*12=1536 */
   +            freq /= 12u;
   +            break;
   +        default:
   +            freq = 0u;
   +            break;
            }
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetInternalRefClkSelectFreq(void)
   +static uint32_t
   +CLOCK_GetInternalRefClkSelectFreq(void)
    {
        uint32_t freq;
    
   -    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL)
   -    {
   +    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL) {
            /* Slow internal reference clock selected*/
            freq = s_slowIrcFreq;
   -    }
   -    else
   -    {
   +    } else   {
            /* Fast internal reference clock selected*/
            freq = s_fastIrcFreq >> MCG_SC_FCRDIV_VAL;
        }
   @@ -301,44 +298,40 @@
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If use external reference clock. */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            freq = CLOCK_GetFllExtRefClkFreq();
        }
        /* If use internal reference clock. */
   -    else
   -    {
   +    else {
            freq = s_slowIrcFreq;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetPll0RefFreq(void)
   +static uint32_t
   +CLOCK_GetPll0RefFreq(void)
    {
        /* MCG external reference clock. */
        return CLOCK_GetMcgExtClkFreq();
    }
    
   -static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
   +static uint8_t
   +CLOCK_GetOscRangeFromFreq(uint32_t freq)
    {
        uint8_t range;
    
   -    if (freq <= 39063U)
   -    {
   +    if (freq <= 39063U) {
            range = 0U;
   -    }
   -    else if (freq <= 8000000U)
   -    {
   +    } else if (freq <= 8000000U)   {
            range = 1U;
   -    }
   -    else
   -    {
   +    } else   {
            range = 2U;
        }
    
   @@ -350,17 +343,15 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetOsc0ErClkFreq(void)
   +uint32_t
   +CLOCK_GetOsc0ErClkFreq(void)
    {
        uint32_t freq;
   -    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)
   -    {
   +    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U) {
            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
            assert(g_xtal0Freq);
            freq = g_xtal0Freq;
   -    }
   -    else
   -    {
   +    } else   {
            freq = 0U;
        }
    
   @@ -372,26 +363,26 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetEr32kClkFreq(void)
   +uint32_t
   +CLOCK_GetEr32kClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT1_OSC32KSEL_VAL)
   -    {
   -        case 0U: /* OSC 32k clock  */
   -            freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   -            break;
   -        case 2U: /* RTC 32k clock  */
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 3U: /* LPO clock      */
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT1_OSC32KSEL_VAL) {
   +    case 0U:     /* OSC 32k clock  */
   +        freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   +        break;
   +    case 2U:     /* RTC 32k clock  */
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 3U:     /* LPO clock      */
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
        return freq;
    }
   @@ -401,24 +392,24 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPllFllSelClkFreq(void)
   +uint32_t
   +CLOCK_GetPllFllSelClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT2_PLLFLLSEL_VAL)
   -    {
   -        case 0U: /* FLL. */
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case 1U: /* PLL. */
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case 3U: /* MCG IRC48M. */
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT2_PLLFLLSEL_VAL) {
   +    case 0U:     /* FLL. */
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case 1U:     /* PLL. */
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case 3U:     /* MCG IRC48M. */
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -429,7 +420,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPlatClkFreq(void)
   +uint32_t
   +CLOCK_GetPlatClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -439,7 +431,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlashClkFreq(void)
   +uint32_t
   +CLOCK_GetFlashClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
    }
   @@ -449,7 +442,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlexBusClkFreq(void)
   +uint32_t
   +CLOCK_GetFlexBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
    }
   @@ -459,7 +453,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetBusClkFreq(void)
   +uint32_t
   +CLOCK_GetBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
    }
   @@ -469,7 +464,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetCoreSysClkFreq(void)
   +uint32_t
   +CLOCK_GetCoreSysClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -484,55 +480,55 @@
     * param clockName Clock names defined in clock_name_t
     * return Clock frequency value in Hertz
     */
   -uint32_t CLOCK_GetFreq(clock_name_t clockName)
   +uint32_t
   +CLOCK_GetFreq(clock_name_t clockName)
    {
        uint32_t freq;
    
   -    switch (clockName)
   -    {
   -        case kCLOCK_CoreSysClk:
   -        case kCLOCK_PlatClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   -            break;
   -        case kCLOCK_BusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlexBusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlashClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   -            break;
   -        case kCLOCK_PllFllSelClk:
   -            freq = CLOCK_GetPllFllSelClkFreq();
   -            break;
   -        case kCLOCK_Er32kClk:
   -            freq = CLOCK_GetEr32kClkFreq();
   -            break;
   -        case kCLOCK_Osc0ErClk:
   -            freq = CLOCK_GetOsc0ErClkFreq();
   -            break;
   -        case kCLOCK_McgFixedFreqClk:
   -            freq = CLOCK_GetFixedFreqClkFreq();
   -            break;
   -        case kCLOCK_McgInternalRefClk:
   -            freq = CLOCK_GetInternalRefClkFreq();
   -            break;
   -        case kCLOCK_McgFllClk:
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case kCLOCK_McgPll0Clk:
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case kCLOCK_McgIrc48MClk:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        case kCLOCK_LpoClk:
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (clockName) {
   +    case kCLOCK_CoreSysClk:
   +    case kCLOCK_PlatClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   +        break;
   +    case kCLOCK_BusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlexBusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlashClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   +        break;
   +    case kCLOCK_PllFllSelClk:
   +        freq = CLOCK_GetPllFllSelClkFreq();
   +        break;
   +    case kCLOCK_Er32kClk:
   +        freq = CLOCK_GetEr32kClkFreq();
   +        break;
   +    case kCLOCK_Osc0ErClk:
   +        freq = CLOCK_GetOsc0ErClkFreq();
   +        break;
   +    case kCLOCK_McgFixedFreqClk:
   +        freq = CLOCK_GetFixedFreqClkFreq();
   +        break;
   +    case kCLOCK_McgInternalRefClk:
   +        freq = CLOCK_GetInternalRefClkFreq();
   +        break;
   +    case kCLOCK_McgFllClk:
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case kCLOCK_McgPll0Clk:
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case kCLOCK_McgIrc48MClk:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    case kCLOCK_LpoClk:
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -545,7 +541,8 @@
     *
     * param config Pointer to the configure structure.
     */
   -void CLOCK_SetSimConfig(sim_clock_config_t const *config)
   +void
   +CLOCK_SetSimConfig(sim_clock_config_t const *config)
    {
        SIM->CLKDIV1 = config->clkdiv1;
        CLOCK_SetPllFllSelClock(config->pllFllSel);
   @@ -559,35 +556,32 @@
     * retval true The clock is set successfully.
     * retval false The clock source is invalid to get proper USB FS clock.
     */
   -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
   +bool
   +CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
    {
        bool ret = true;
    
        CLOCK_DisableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcExt == src)
   -    {
   +    if (kCLOCK_UsbSrcExt == src) {
            SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
   -    }
   -    else
   -    {
   -        switch (freq)
   -        {
   -            case 120000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 96000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            case 72000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 48000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            default:
   -                ret = false;
   -                break;
   +    } else   {
   +        switch (freq) {
   +        case 120000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 96000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        case 72000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 48000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        default:
   +            ret = false;
   +            break;
            }
    
            SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src);
   @@ -595,8 +589,7 @@
    
        CLOCK_EnableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcIrc48M == src)
   -    {
   +    if (kCLOCK_UsbSrcIrc48M == src) {
            USB0->CLK_RECOVER_IRC_EN = 0x03U;
            USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
        }
   @@ -611,28 +604,28 @@
     *
     * return The frequency of MCGOUTCLK.
     */
   -uint32_t CLOCK_GetOutClkFreq(void)
   +uint32_t
   +CLOCK_GetOutClkFreq(void)
    {
        uint32_t mcgoutclk;
        uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
    
   -    switch (clkst)
   -    {
   -        case (uint32_t)kMCG_ClkOutStatPll:
   -            mcgoutclk = CLOCK_GetPll0Freq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatFll:
   -            mcgoutclk = CLOCK_GetFllFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatInt:
   -            mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatExt:
   -            mcgoutclk = CLOCK_GetMcgExtClkFreq();
   -            break;
   -        default:
   -            mcgoutclk = 0U;
   -            break;
   +    switch (clkst) {
   +    case (uint32_t)kMCG_ClkOutStatPll:
   +        mcgoutclk = CLOCK_GetPll0Freq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatFll:
   +        mcgoutclk = CLOCK_GetFllFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatInt:
   +        mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatExt:
   +        mcgoutclk = CLOCK_GetMcgExtClkFreq();
   +        break;
   +    default:
   +        mcgoutclk = 0U;
   +        break;
        }
    
        return mcgoutclk;
   @@ -647,7 +640,8 @@
     *
     * return The frequency of MCGFLLCLK.
     */
   -uint32_t CLOCK_GetFllFreq(void)
   +uint32_t
   +CLOCK_GetFllFreq(void)
    {
        static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}};
    
   @@ -656,23 +650,17 @@
        uint32_t ret;
    
        /* If FLL is not enabled currently, then return 0U. */
   -    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U)))
   -    {
   +    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) {
            ret = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            /* Get FLL reference clock frequency. */
            freq = CLOCK_GetFllRefClkFreq();
   -        if (0U == freq)
   -        {
   +        if (0U == freq) {
                ret = freq;
   -        }
   -        else
   -        {
   -            drs   = MCG_C4_DRST_DRS_VAL;
   +        } else   {
   +            drs = MCG_C4_DRST_DRS_VAL;
                dmx32 = MCG_C4_DMX32_VAL;
   -            ret   = freq * fllFactorTable[drs][dmx32];
   +            ret = freq * fllFactorTable[drs][dmx32];
            }
        }
    
   @@ -687,17 +675,15 @@
     *
     * return The frequency of MCGIRCLK.
     */
   -uint32_t CLOCK_GetInternalRefClkFreq(void)
   +uint32_t
   +CLOCK_GetInternalRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If MCGIRCLK is gated. */
   -    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK))
   -    {
   +    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            freq = CLOCK_GetInternalRefClkSelectFreq();
        }
    
   @@ -712,18 +698,16 @@
     *
     * return The frequency of MCGFFCLK.
     */
   -uint32_t CLOCK_GetFixedFreqClkFreq(void)
   +uint32_t
   +CLOCK_GetFixedFreqClkFreq(void)
    {
        uint32_t freq = CLOCK_GetFllRefClkFreq();
        uint32_t ret;
    
        /* MCGFFCLK must be no more than MCGOUTCLK/8. */
   -    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq))
   -    {
   +    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq)) {
            ret = freq;
   -    }
   -    else
   -    {
   +    } else   {
            ret = 0U;
        }
    
   @@ -738,7 +722,8 @@
     *
     * return The frequency of MCGPLL0CLK.
     */
   -uint32_t CLOCK_GetPll0Freq(void)
   +uint32_t
   +CLOCK_GetPll0Freq(void)
    {
        uint32_t mcgpll0clk;
        uint32_t freq;
   @@ -746,12 +731,9 @@
        uint8_t mcgpll0prdiv;
        uint8_t mcgpll0vdiv;
        /* If PLL0 is not enabled, return 0. */
   -    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            mcgpll0clk = CLOCK_GetPll0RefFreq();
    
            /*
   @@ -783,36 +765,31 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success External reference clock set successfully.
     */
   -status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
    {
        bool needDelay;
        uint32_t i;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */
   -    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK)))
   -    {
   +    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) {
            return kStatus_MCG_SourceUsed;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
    
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel)
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel) {
            /* If change OSCSEL, need to delay, ERR009878. */
            needDelay = true;
   -    }
   -    else
   -    {
   +    } else   {
            needDelay = false;
        }
    
        MCG->C7 = (uint8_t)(MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
   -    if (needDelay)
   -    {
   +    if (needDelay) {
            /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
            i = 1500U;
   -        while (0U != (i--))
   -        {
   +        while (0U != (i--)) {
                __NOP();
            }
        }
   @@ -836,34 +813,30 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success MCGIRCLK configuration finished successfully.
     */
   -status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
   +status_t
   +CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
    {
        uint32_t mcgOutClkState = (uint32_t)MCG_S_CLKST_VAL;
   -    mcg_irc_mode_t curIrcs  = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   -    uint8_t curFcrdiv       = MCG_SC_FCRDIV_VAL;
   +    mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   +    uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If MCGIRCLK is used as system clock source. */
   -    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState)
   -    {
   +    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState) {
            /* If need to change MCGIRCLK source or driver, return error. */
   -        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs))
   -        {
   +        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) {
                return kStatus_MCG_SourceUsed;
            }
        }
    #endif
    
        /* If need to update the FCRDIV. */
   -    if (fcrdiv != curFcrdiv)
   -    {
   +    if (fcrdiv != curFcrdiv) {
            /* If fast IRC is in use currently, change to slow IRC. */
            if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) &&
   -            (kMCG_IrcFast == curIrcs))
   -        {
   +            (kMCG_IrcFast == curIrcs)) {
                MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
   -            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow)
   -            {
   +            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow) {
                }
            }
            /* Update FCRDIV. */
   @@ -876,10 +849,8 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode);
    
        /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
   -    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable)))
   -    {
   -        while (MCG_S_IRCST_VAL != (uint8_t)ircs)
   -        {
   +    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable))) {
   +        while (MCG_S_IRCST_VAL != (uint8_t)ircs) {
            }
        }
    
   @@ -901,7 +872,8 @@
     * param vdiv       VDIV value to generate desired PLL frequency.
     * return Closest frequency match that the PLL was able generate.
     */
   -uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
   +uint32_t
   +CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
    {
        uint8_t ret_prdiv;               /* PRDIV to return. */
        uint8_t ret_vdiv;                /* VDIV to return.  */
   @@ -910,7 +882,7 @@
        uint8_t prdiv_cur;               /* PRDIV value for iteration.    */
        uint8_t vdiv_cur;                /* VDIV value for iteration.     */
        uint32_t ret_freq = 0U;          /* PLL output frequency to return. */
   -    uint32_t diff     = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */
   +    uint32_t diff = 0xFFFFFFFFU;     /* Difference between desireFreq and return frequency. */
        uint32_t ref_div;                /* Reference frequency after PRDIV. */
    
        /*
   @@ -929,8 +901,7 @@
        /* Reference frequency is out of range. */
        if ((refFreq < (uint32_t)FSL_FEATURE_MCG_PLL_REF_MIN) ||
            (refFreq > ((uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX *
   -                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE))))
   -    {
   +                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) {
            return 0U;
        }
    
   @@ -940,62 +911,52 @@
            (uint8_t)((refFreq + (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX);
    
        /* PRDIV traversal. */
   -    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--)
   -    {
   +    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) {
            /* Reference frequency after PRDIV. */
            ref_div = refFreq / prdiv_cur;
    
            vdiv_cur = (uint8_t)(desireFreq / ref_div);
    
            if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) ||
   -            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                /* No VDIV is available with this PRDIV. */
                continue;
            }
    
            ret_freq = vdiv_cur * ref_div;
    
   -        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE)
   -        {
   -            if (ret_freq == desireFreq) /* If desire frequency is got. */
   -            {
   +        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) {
   +            if (ret_freq == desireFreq) { /* If desire frequency is got. */
                    *prdiv = prdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -                *vdiv  = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +                *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
                    return ret_freq;
                }
                /* New PRDIV/VDIV is closer. */
   -            if (diff > desireFreq - ret_freq)
   -            {
   -                diff      = desireFreq - ret_freq;
   +            if (diff > desireFreq - ret_freq) {
   +                diff = desireFreq - ret_freq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
            vdiv_cur++;
   -        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                ret_freq += ref_div;
                /* New PRDIV/VDIV is closer. */
   -            if (diff > ret_freq - desireFreq)
   -            {
   -                diff      = ret_freq - desireFreq;
   +            if (diff > ret_freq - desireFreq) {
   +                diff = ret_freq - desireFreq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
        }
    
   -    if (0xFFFFFFFFU != diff)
   -    {
   +    if (0xFFFFFFFFU != diff) {
            /* PRDIV/VDIV found. */
   -        *prdiv   = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -        *vdiv    = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +        *prdiv = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   +        *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
            ret_freq = (refFreq / ret_prdiv) * ret_vdiv;
            return ret_freq;
   -    }
   -    else
   -    {
   +    } else   {
            /* No proper PRDIV/VDIV found. */
            return 0U;
        }
   @@ -1012,7 +973,8 @@
     *
     * param config Pointer to the configuration structure.
     */
   -void CLOCK_EnablePll0(mcg_pll_config_t const *config)
   +void
   +CLOCK_EnablePll0(mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1027,8 +989,7 @@
        MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode);
    
        /* Wait for PLL lock. */
   -    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
        }
    }
    
   @@ -1039,23 +1000,18 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
    {
        /* Clear the previous flag, MCG_SC[LOCS0]. */
        MCG->SC &= ~(uint8_t)MCG_SC_ATMF_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= ~(uint8_t)MCG_C6_CME0_MASK;
   -    }
   -    else
   -    {
   -        if (kMCG_MonitorInt == mode)
   -        {
   +    } else   {
   +        if (kMCG_MonitorInt == mode) {
                MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK;
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C2 |= MCG_C2_LOCRE0_MASK;
            }
            MCG->C6 |= MCG_C6_CME0_MASK;
   @@ -1069,16 +1025,15 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8 = MCG->C8;
    
        mcg_c8 &= ~(uint8_t)(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK);
    
   -    if (kMCG_MonitorNone != mode)
   -    {
   -        if (kMCG_MonitorReset == mode)
   -        {
   +    if (kMCG_MonitorNone != mode) {
   +        if (kMCG_MonitorReset == mode) {
                mcg_c8 |= MCG_C8_LOCRE1_MASK;
            }
            mcg_c8 |= MCG_C8_CME1_MASK;
   @@ -1093,29 +1048,24 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8;
    
        /* Clear previous flag. */
        MCG->S = MCG_S_LOLS0_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= (uint8_t)(~MCG_C6_LOLIE0_MASK);
   -    }
   -    else
   -    {
   +    } else   {
            mcg_c8 = MCG->C8;
    
            mcg_c8 &= (uint8_t)(~MCG_C8_LOCS1_MASK);
    
   -        if (kMCG_MonitorInt == mode)
   -        {
   +        if (kMCG_MonitorInt == mode) {
                mcg_c8 &= (uint8_t)(~MCG_C8_LOLRE_MASK);
   -        }
   -        else
   -        {
   +        } else   {
                mcg_c8 |= MCG_C8_LOLRE_MASK;
            }
            MCG->C8 = mcg_c8;
   @@ -1149,29 +1099,25 @@
     *
     * return  Logical OR value of the ref _mcg_status_flags_t.
     */
   -uint32_t CLOCK_GetStatusFlags(void)
   -{
   -    uint32_t ret  = 0U;
   +uint32_t
   +CLOCK_GetStatusFlags(void)
   +{
   +    uint32_t ret = 0U;
        uint8_t mcg_s = MCG->S;
    
   -    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U)
   -    {
   +    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0LostFlag;
        }
   -    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0InitFlag;
        }
   -    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK))
   -    {
   +    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK)) {
            ret |= (uint32_t)kMCG_RtcOscLostFlag;
        }
   -    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LostFlag;
        }
   -    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LockFlag;
        }
        return ret;
   @@ -1193,21 +1139,19 @@
     * param mask The status flags to clear. This is a logical OR of members of the
     *             enumeration ref _mcg_status_flags_t.
     */
   -void CLOCK_ClearStatusFlags(uint32_t mask)
   +void
   +CLOCK_ClearStatusFlags(uint32_t mask)
    {
        uint8_t reg;
    
   -    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL) {
            MCG->SC &= (uint8_t)(~MCG_SC_ATMF_MASK);
        }
   -    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag))
   -    {
   -        reg     = MCG->C8;
   +    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag)) {
   +        reg = MCG->C8;
            MCG->C8 = reg;
        }
   -    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL) {
            MCG->S = MCG_S_LOLS0_MASK;
        }
    }
   @@ -1219,7 +1163,8 @@
     *
     * param  config Pointer to the OSC0 configuration structure.
     */
   -void CLOCK_InitOsc0(osc_config_t const *config)
   +void
   +CLOCK_InitOsc0(osc_config_t const *config)
    {
        uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq);
    
   @@ -1228,11 +1173,9 @@
        MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode);
        OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
    
   -    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U))
   -    {
   +    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)) {
            /* Wait for stable. */
   -        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -        {
   +        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
            }
        }
    }
   @@ -1242,7 +1185,8 @@
     *
     * This function deinitializes the OSC0.
     */
   -void CLOCK_DeinitOsc0(void)
   +void
   +CLOCK_DeinitOsc0(void)
    {
        OSC0->CR = 0U;
        MCG->C2 &= ~(uint8_t)OSC_MODE_MASK;
   @@ -1253,7 +1197,8 @@
     *
     * param freq The Slow IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetSlowIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetSlowIrcFreq(uint32_t freq)
    {
        s_slowIrcFreq = freq;
    }
   @@ -1263,7 +1208,8 @@
     *
     * param freq The Fast IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetFastIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetFastIrcFreq(uint32_t freq)
    {
        s_fastIrcFreq = freq;
    }
   @@ -1286,7 +1232,8 @@
     * retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
     * retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
     */
   -status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
   +status_t
   +CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
    {
        uint32_t multi; /* extFreq / desireFreq */
        uint32_t actv;  /* Auto trim value. */
   @@ -1299,30 +1246,24 @@
            {TRIM_FIRC_MIN, TRIM_FIRC_MAX}  /* Fast IRC. */
        };
    
   -    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN))
   -    {
   +    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) {
            status = kStatus_MCG_AtmBusClockInvalid;
        }
        /* Check desired frequency range. */
   -    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1]))
   -    {
   +    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) {
            status = kStatus_MCG_AtmDesiredFreqInvalid;
        }
        /*
           Make sure internal reference clock is not used to generate bus clock.
           Here only need to check (MCG_S_IREFST == 1).
         */
   -    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK))
   -    {
   +    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) {
            status = kStatus_MCG_AtmIrcUsed;
   -    }
   -    else
   -    {
   +    } else   {
            multi = extFreq / desireFreq;
   -        actv  = multi * 21U;
   -
   -        if (kMCG_AtmSel4m == atms)
   -        {
   +        actv = multi * 21U;
   +
   +        if (kMCG_AtmSel4m == atms) {
                actv *= 128U;
            }
    
   @@ -1336,27 +1277,20 @@
            MCG->SC = (mcg_sc | MCG_SC_ATME_MASK);
    
            /* Wait for MCG finished. */
   -        while (0U != (MCG->SC & MCG_SC_ATME_MASK))
   -        {
   +        while (0U != (MCG->SC & MCG_SC_ATME_MASK)) {
            }
    
            /* Error occurs? */
   -        if (0U != (MCG->SC & MCG_SC_ATMF_MASK))
   -        {
   +        if (0U != (MCG->SC & MCG_SC_ATMF_MASK)) {
                /* Clear the failed flag. */
                MCG->SC = mcg_sc;
   -            status  = kStatus_MCG_AtmHardwareFail;
   -        }
   -        else
   -        {
   +            status = kStatus_MCG_AtmHardwareFail;
   +        } else   {
                *actualFreq = extFreq / multi;
    
   -            if (kMCG_AtmSel4m == atms)
   -            {
   +            if (kMCG_AtmSel4m == atms) {
                    s_fastIrcFreq = *actualFreq;
   -            }
   -            else
   -            {
   +            } else   {
                    s_slowIrcFreq = *actualFreq;
                }
            }
   @@ -1372,103 +1306,83 @@
     *
     * return Current MCG mode or error code; See ref mcg_mode_t.
     */
   -mcg_mode_t CLOCK_GetMode(void)
   +mcg_mode_t
   +CLOCK_GetMode(void)
    {
        mcg_mode_t mode = kMCG_ModeError;
   -    uint32_t clkst  = (uint32_t)MCG_S_CLKST_VAL;
   +    uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
        uint32_t irefst = (uint32_t)MCG_S_IREFST_VAL;
   -    uint32_t lp     = (uint32_t)MCG_C2_LP_VAL;
   -    uint32_t pllst  = MCG_S_PLLST_VAL;
   +    uint32_t lp = (uint32_t)MCG_C2_LP_VAL;
   +    uint32_t pllst = MCG_S_PLLST_VAL;
    
        /*------------------------------------------------------------------
                               Mode and Registers
   -    ____________________________________________________________________
   -
   -      Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   -    ____________________________________________________________________
   -
   -      FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -      PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   -    ____________________________________________________________________
   -
   -      PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -    ----------------------------------------------------------------------*/
   -
   -    if (clkst == (uint32_t)kMCG_ClkOutStatFll)
   -    {
   -        if ((uint32_t)kMCG_FllSrcExternal == irefst)
   -        {
   +       ____________________________________________________________________
   +
   +       Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   +       ____________________________________________________________________
   +
   +       FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   +       ____________________________________________________________________
   +
   +       PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       ----------------------------------------------------------------------*/
   +
   +    if (clkst == (uint32_t)kMCG_ClkOutStatFll) {
   +        if ((uint32_t)kMCG_FllSrcExternal == irefst) {
                mode = kMCG_ModeFEE;
   -        }
   -        else
   -        {
   +        } else   {
                mode = kMCG_ModeFEI;
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatInt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatInt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPI;
   -        }
   -        else
   -        {
   +        } else   {
                {
                    mode = kMCG_ModeFBI;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatExt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatExt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPE;
   -        }
   -        else
   -        {
   -            if ((uint32_t)kMCG_PllstPll == pllst)
   -            {
   +        } else   {
   +            if ((uint32_t)kMCG_PllstPll == pllst) {
                    mode = kMCG_ModePBE;
   -            }
   -            else
   -            {
   +            } else   {
                    mode = kMCG_ModeFBE;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatPll)
   -    {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatPll)   {
            {
                mode = kMCG_ModePEE;
            }
   -    }
   -    else
   -    {
   +    } else   {
            /*do nothing*/
        }
    
   @@ -1490,15 +1404,15 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to a frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode)))
   -    {
   +    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1510,8 +1424,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1523,13 +1436,11 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1538,13 +1449,11 @@
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1566,15 +1475,15 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode)))
   -    {
   +    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1586,8 +1495,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1600,45 +1508,37 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
        /* Set DRS and DMX32. */
   -    mcg_c4  = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
   +    mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
        MCG->C4 = mcg_c4;
    
        /* Wait for DRST_DRS update. */
   -    while (MCG->C4 != mcg_c4)
   -    {
   +    while (MCG->C4 != mcg_c4) {
        }
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1661,7 +1561,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1670,9 +1571,7 @@
        mcg_mode_t mode = CLOCK_GetMode();
    
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModeBLPI == mode)))
   -
   -    {
   +          (kMCG_ModeBLPI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1687,8 +1586,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1700,26 +1598,22 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   -    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) {
        }
    
        MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1741,7 +1635,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1749,16 +1644,14 @@
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode)))
   -    {
   +          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
    
        /* Change to FLL mode. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Set LP bit to enable the FLL */
   @@ -1772,8 +1665,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1786,24 +1678,19 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for Reference clock Status bit to clear */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1812,13 +1699,11 @@
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for clock status bits to show clock source is ext ref clk */
   -    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for fll stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1834,11 +1719,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpiMode(void)
   +status_t
   +CLOCK_SetBlpiMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1858,11 +1743,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpeMode(void)
   +status_t
   +CLOCK_SetBlpeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1892,7 +1777,8 @@
     * configuration structure not necessary. In this case, pass in NULL.
     * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
     */
   -status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1907,14 +1793,12 @@
    
        /* Wait for CLKST clock status bits to show clock source is ext ref clk */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* Disable PLL first, then configure PLL. */
        MCG->C6 &= (uint8_t)(~MCG_C6_PLLS_MASK);
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Configure the PLL. */
   @@ -1926,8 +1810,7 @@
        MCG->C6 |= MCG_C6_PLLS_MASK;
    
        /* Wait for PLL mode changed. */
   -    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U) {
        }
    
        return kStatus_Success;
   @@ -1945,12 +1828,12 @@
     *       PRDIV/VDIV are different than in the PBE mode, set them up
     *       in PBE mode and wait. When the clock is stable, switch to PEE mode.
     */
   -status_t CLOCK_SetPeeMode(void)
   +status_t
   +CLOCK_SetPeeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (kMCG_ModePBE != mode)
   -    {
   +    if (kMCG_ModePBE != mode) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1959,8 +1842,7 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
    
        /* Wait for clock status bits to update */
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -1982,11 +1864,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
     */
   -status_t CLOCK_ExternalModeToFbeModeQuick(void)
   +status_t
   +CLOCK_ExternalModeToFbeModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) != 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) != 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1995,14 +1877,12 @@
        MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK);
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
        }
    
        /* Disable PLL. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        return kStatus_Success;
   @@ -2024,11 +1904,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
     */
   -status_t CLOCK_InternalModeToFbiModeQuick(void)
   +status_t
   +CLOCK_InternalModeToFbiModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) == 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) == 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif
   @@ -2037,8 +1917,7 @@
        MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        return kStatus_Success;
   @@ -2059,7 +1938,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
    }
   @@ -2079,8 +1959,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToFeeMode(
   -    mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeeMode(mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2100,15 +1980,15 @@
     * retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
   +status_t
   +CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
    {
        /* If reset mode is FEI mode, set MCGIRCLK and always success. */
        (void)CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
    
        /* If reset mode is not BLPI, first enter FBI mode. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        /* Enter BLPI mode. */
   @@ -2128,7 +2008,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2138,20 +2019,16 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* In FBE now, start to enter BLPE. */
   @@ -2173,7 +2050,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -2183,8 +2061,7 @@
    
        /* Change to use PLL output clock. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -2233,7 +2110,8 @@
     * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
     * function.
     */
   -status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
   +status_t
   +CLOCK_SetMcgConfig(const mcg_config_t *config)
    {
        mcg_mode_t next_mode;
        status_t status = kStatus_Success;
   @@ -2241,11 +2119,9 @@
        mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0;
    
        /* If need to change external clock, MCG_C7[OSCSEL]. */
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel))
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel)) {
            /* If external clock is in use, change to FEI first. */
   -        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -        {
   +        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
                (void)CLOCK_ExternalModeToFbeModeQuick();
                (void)CLOCK_SetFeiMode(config->dmx32, config->drs, NULL);
            }
   @@ -2254,8 +2130,7 @@
        }
    
        /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
   -    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt) {
            MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */
    
            {
   @@ -2268,67 +2143,56 @@
    
        next_mode = CLOCK_GetMode();
    
   -    do
   -    {
   +    do{
            next_mode = mcgModeMatrix[next_mode][config->mcgMode];
    
   -        switch (next_mode)
   -        {
   -            case kMCG_ModeFEI:
   -                status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFEE:
   -                status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFBI:
   -                status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeFBE:
   -                status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeBLPI:
   -                status = CLOCK_SetBlpiMode();
   -                break;
   -            case kMCG_ModeBLPE:
   -                status = CLOCK_SetBlpeMode();
   -                break;
   -            case kMCG_ModePBE:
   -                /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   -                if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode))
   +        switch (next_mode) {
   +        case kMCG_ModeFEI:
   +            status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFEE:
   +            status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFBI:
   +            status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeFBE:
   +            status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeBLPI:
   +            status = CLOCK_SetBlpiMode();
   +            break;
   +        case kMCG_ModeBLPE:
   +            status = CLOCK_SetBlpeMode();
   +            break;
   +        case kMCG_ModePBE:
   +            /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   +            if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) {
                    {
   -                    {
   -                        status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
   -                    }
   +                    status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
                    }
   -                else
   -                {
   -                    MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -                    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -                    {
   -                    }
   +            } else   {
   +                MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   +                while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
                    }
   -                break;
   -            case kMCG_ModePEE:
   -                status = CLOCK_SetPeeMode();
   -                break;
   -            default:
   -                assert(false);
   -                break;
   -        }
   -        if (kStatus_Success != status)
   -        {
   +            }
                break;
   +        case kMCG_ModePEE:
   +            status = CLOCK_SetPeeMode();
   +            break;
   +        default:
   +            assert(false);
   +            break;
   +        }
   +        if (kStatus_Success != status) {
   +            break;
            }
        } while (next_mode != config->mcgMode);
    
   -    if (status == kStatus_Success)
   -    {
   -        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U)
   -        {
   +    if (status == kStatus_Success) {
   +        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U) {
                CLOCK_EnablePll0(&config->pll0Config);
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/include/hal_lpuart_nxp.h
   <details>
   
   ```diff
   @@ -21,7 +21,7 @@
    #define __MCU_K8XF_HAL_UART_H_
    
    #ifdef __cplusplus
   - extern "C" {
   +extern "C" {
    #endif
    
    #define NXP_UART_EXISTS      { 1, \
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/include/mcu/kinetis_common.h
   <details>
   
   ```diff
   @@ -21,7 +21,7 @@
    #define __KINETIS_COMMON_H_
    
    #ifdef __cplusplus
   - extern "C" {
   +extern "C" {
    #endif
    
    #if MYNEWT_VAL(BSP_MK64F12)
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/include/mcu/kinetis_hal.h
   <details>
   
   ```diff
   @@ -21,7 +21,7 @@
    #define __KINETIS_HAL_H_
    
    #ifdef __cplusplus
   - extern "C" {
   +extern "C" {
    #endif
    
    struct nxp_hal_i2c_cfg {
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_flash.c
   <details>
   
   ```diff
   @@ -6,7 +6,7 @@
     * to you under the Apache License, Version 2.0 (the
     * "License"); you may not use this file except in compliance
     * with the License.  You may obtain a copy of the License at
   -*
   + *
     *  http://www.apache.org/licenses/LICENSE-2.0
     *
     * Unless required by applicable law or agreed to in writing,
   @@ -40,13 +40,13 @@
    #define KINETIS_FLASH_ALIGN MYNEWT_VAL(MCU_FLASH_MIN_WRITE_SIZE)
    
    static int kinetis_flash_read(const struct hal_flash *dev, uint32_t address,
   -        void *dst, uint32_t num_bytes);
   +                              void *dst, uint32_t num_bytes);
    static int kinetis_flash_write(const struct hal_flash *dev, uint32_t address,
   -        const void *src, uint32_t num_bytes);
   +                               const void *src, uint32_t num_bytes);
    static int kinetis_flash_erase_sector(const struct hal_flash *dev,
   -        uint32_t sector_address);
   +                                      uint32_t sector_address);
    static int kinetis_flash_sector_info(const struct hal_flash *dev, int idx,
   -        uint32_t *addr, uint32_t *sz);
   +                                     uint32_t *addr, uint32_t *sz);
    static int kinetis_flash_init(const struct hal_flash *dev);
    
    static const struct hal_flash_funcs kinetis_flash_funcs = {
   @@ -68,9 +68,9 @@
    
    static int
    kinetis_flash_read(const struct hal_flash *dev,
   -                 uint32_t address,
   -                 void *dst,
   -                 uint32_t num_bytes)
   +                   uint32_t address,
   +                   void *dst,
   +                   uint32_t num_bytes)
    {
        memcpy(dst, (void *)address, num_bytes);
        return 0;
   @@ -78,9 +78,9 @@
    
    static int
    kinetis_flash_write(const struct hal_flash *dev,
   -                  uint32_t address,
   -                  const void *src,
   -                  uint32_t len)
   +                    uint32_t address,
   +                    const void *src,
   +                    uint32_t len)
    {
        uint8_t padded[KINETIS_FLASH_ALIGN];
        uint8_t pad_len;
   @@ -142,9 +142,9 @@
    
    static int
    kinetis_flash_sector_info(const struct hal_flash *dev,
   -                        int idx,
   -                        uint32_t *addr,
   -                        uint32_t *sz)
   +                          int idx,
   +                          uint32_t *addr,
   +                          uint32_t *sz)
    {
        uint32_t sector_size;
        FLASH_GetProperty(&kinetis_config,
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_gpio.c
   <details>
   
   ```diff
   @@ -53,8 +53,7 @@
    uint16_t
    hal_to_fsl_pull(hal_gpio_pull_t pull)
    {
   -    switch ((int)pull)
   -    {
   +    switch ((int)pull) {
        case HAL_GPIO_PULL_UP:
            return kPORT_PullUp;
        case HAL_GPIO_PULL_DOWN:
   @@ -304,9 +303,9 @@
    #endif
            memset(&hal_gpio_irqs[entry], 0, sizeof(struct hal_gpio_irq));
            if (hal_gpio_find_port(GPIO_PORT(pin)) < 0) {
   -                NVIC_ClearPendingIRQ(GPIO_PORT(pin));
   -                NVIC_DisableIRQ(GPIO_PORT(pin));
   -            }
   +            NVIC_ClearPendingIRQ(GPIO_PORT(pin));
   +            NVIC_DisableIRQ(GPIO_PORT(pin));
   +        }
        }
    }
    
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_i2c.c
   <details>
   
   ```diff
   @@ -33,10 +33,10 @@
    #define NXP_HAL_I2C_MAX 4
    
    struct nxp_hal_i2c {
   -    I2C_Type* dev;
   +    I2C_Type * dev;
        uint32_t scl_pin;
        uint32_t sda_pin;
   -    PORT_Type *port; 
   +    PORT_Type *port;
        port_mux_t mux;
        IRQn_Type irqn;
        void (*irq_handler)(void);
   @@ -170,7 +170,7 @@
        os_sem_release(&i2c->sync);
    }
    
   -static struct nxp_hal_i2c*
   +static struct nxp_hal_i2c *
    hal_i2c_resolve(uint8_t i2c_num)
    {
        if (i2c_num >= NXP_HAL_I2C_MAX) {
   @@ -289,7 +289,7 @@
    
        i2c = hal_i2c_resolve(i2c_num);
        if (!i2c) {
   -       return HAL_I2C_ERR_INVAL;
   +        return HAL_I2C_ERR_INVAL;
        }
    
        return i2c_config(i2c, cfg->frequency);
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_lpuart.c
   <details>
   
   ```diff
   @@ -50,22 +50,22 @@
    };
    
    struct hal_uart {
   -    LPUART_Type      *u_base;
   -    clock_name_t     clk_src;
   -    uint32_t         u_irq;
   -    PORT_Type       *p_base;
   -    clock_ip_name_t  p_clock;
   -    int  u_pin_rx;
   -    int  u_pin_tx;
   +    LPUART_Type *u_base;
   +    clock_name_t clk_src;
   +    uint32_t u_irq;
   +    PORT_Type *p_base;
   +    clock_ip_name_t p_clock;
   +    int u_pin_rx;
   +    int u_pin_tx;
        /* TODO: support flow control pins */
        hal_uart_rx_char u_rx_func;
        hal_uart_tx_char u_tx_func;
        hal_uart_tx_done u_tx_done;
        void *u_func_arg;
   -    uint8_t u_configured:1;
   -    uint8_t u_open:1;
   -    uint8_t u_tx_started:1;
   -    uint8_t u_rx_stall:1;
   +    uint8_t u_configured : 1;
   +    uint8_t u_open : 1;
   +    uint8_t u_tx_started : 1;
   +    uint8_t u_rx_stall : 1;
        struct uart_ring ur_tx;
        uint8_t tx_buffer[TX_BUF_SZ];
        struct uart_ring ur_rx;
   @@ -98,17 +98,20 @@
     * RING BUFFER FUNCTIONS
     */
    
   -static uint8_t ur_is_empty(struct uart_ring *ur)
   +static uint8_t
   +ur_is_empty(struct uart_ring *ur)
    {
        return (ur->ur_head == ur->ur_tail);
    }
    
   -static uint8_t ur_is_full(struct uart_ring *ur)
   +static uint8_t
   +ur_is_full(struct uart_ring *ur)
    {
        return (((ur->ur_tail + 1) % ur->ur_size) == ur->ur_head);
    }
    
   -static void ur_bump(struct uart_ring *ur)
   +static void
   +ur_bump(struct uart_ring *ur)
    {
        if (!ur_is_empty(ur)) {
            ur->ur_head++;
   @@ -117,12 +120,14 @@
        }
    }
    
   -static uint8_t ur_read(struct uart_ring *ur)
   +static uint8_t
   +ur_read(struct uart_ring *ur)
    {
        return ur->ur_buf[ur->ur_head];
    }
    
   -static int ur_queue(struct uart_ring *ur, uint8_t data)
   +static int
   +ur_queue(struct uart_ring *ur, uint8_t data)
    {
        if (!ur_is_full(ur)) {
            ur->ur_buf[ur->ur_tail] = data;
   @@ -137,11 +142,12 @@
     * END RING BUFFER FUNCTIONS
     */
    
   -int hal_uart_init_cbs(int port,
   -                      hal_uart_tx_char tx_func,
   -                      hal_uart_tx_done tx_done,
   -                      hal_uart_rx_char rx_func,
   -                      void *arg)
   +int
   +hal_uart_init_cbs(int port,
   +                  hal_uart_tx_char tx_func,
   +                  hal_uart_tx_done tx_done,
   +                  hal_uart_rx_char rx_func,
   +                  void *arg)
    {
        struct hal_uart *u;
    
   @@ -157,7 +163,8 @@
        return 0;
    }
    
   -void hal_uart_blocking_tx(int port, uint8_t byte)
   +void
   +hal_uart_blocking_tx(int port, uint8_t byte)
    {
        struct hal_uart *u;
    
   @@ -194,7 +201,8 @@
        return i;
    }
    
   -void hal_uart_start_tx(int port)
   +void
   +hal_uart_start_tx(int port)
    {
        struct hal_uart *u;
        int data = -1;
   @@ -209,8 +217,7 @@
        }
    
        /* main loop */
   -    while (true)
   -    {
   +    while (true) {
            /* add data to TX ring buffer */
            if (u->u_tx_started == 0) {
                rc = hal_uart_tx_fill_buf(u);
   @@ -293,8 +300,9 @@
            if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base)) {
                if (u->u_tx_started) {
                    u->u_tx_started = 0;
   -                if (u->u_tx_done)
   +                if (u->u_tx_done) {
                        u->u_tx_done(u->u_func_arg);
   +                }
                }
            }
        }
   @@ -434,24 +442,23 @@
    {
        if (s_uartExists[port]) {
            if (s_uartEnabled[port]) {
   -            uarts[port].u_base        = s_uartBases[port];
   -            uarts[port].clk_src       = s_uartClocks[port];
   -            uarts[port].u_irq         = s_uartIRQ[port];
   -            uarts[port].p_base        = s_uartPort[port];
   -            uarts[port].p_clock       = s_uartPortClocks[port];
   -            uarts[port].u_pin_rx      = s_uartPIN_RX[port];
   -            uarts[port].u_pin_tx      = s_uartPIN_TX[port];
   -            uarts[port].ur_tx.ur_buf  = uarts[port].tx_buffer;
   +            uarts[port].u_base = s_uartBases[port];
   +            uarts[port].clk_src = s_uartClocks[port];
   +            uarts[port].u_irq = s_uartIRQ[port];
   +            uarts[port].p_base = s_uartPort[port];
   +            uarts[port].p_clock = s_uartPortClocks[port];
   +            uarts[port].u_pin_rx = s_uartPIN_RX[port];
   +            uarts[port].u_pin_tx = s_uartPIN_TX[port];
   +            uarts[port].ur_tx.ur_buf = uarts[port].tx_buffer;
                uarts[port].ur_tx.ur_size = TX_BUF_SZ;
                uarts[port].ur_tx.ur_head = 0;
                uarts[port].ur_tx.ur_tail = 0;
   -            uarts[port].ur_rx.ur_buf  = uarts[port].rx_buffer;
   +            uarts[port].ur_rx.ur_buf = uarts[port].rx_buffer;
                uarts[port].ur_rx.ur_size = RX_BUF_SZ;
                uarts[port].ur_rx.ur_head = 0;
                uarts[port].ur_rx.ur_tail = 0;
   -            uarts[port].u_configured  = 1;
   -        }
   -        else {
   +            uarts[port].u_configured = 1;
   +        } else   {
                uarts[port].u_configured = 0;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_qspi.c
   <details>
   
   ```diff
   @@ -107,7 +107,8 @@
        [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
    
        /* Match MISRA rule */
   -    [63] = 0};
   +    [63] = 0
   +};
    
    qspi_flash_config_t g_qspi_flash_cfg = {
        .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
   @@ -132,15 +133,12 @@
    {
        uint32_t val = 0;
        /* Check WIP bit */
   -    do
   -    {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +    do{
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
            QSPI_ExecuteIPCommand(QuadSPI0, 12U);
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            val = QuadSPI0->RBDR[0];
            /* Clear ARDB area */
   @@ -151,19 +149,17 @@
    static void
    cmd_write_enable()
    {
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ExecuteIPCommand(QuadSPI0, 4U);
    }
    
    static void
   -read_page(uint32_t address, uint32_t* dst)
   +read_page(uint32_t address, uint32_t * dst)
    {
        int i;
   -    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
   -    {
   -        dst[i] = ((uint32_t*)address)[i];
   +    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++) {
   +        dst[i] = ((uint32_t *)address)[i];
        }
    }
    
   @@ -195,15 +191,13 @@
    {
        uint32_t leftLongWords = 0;
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
    
        QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
        cmd_write_enable();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
    
        /* First write some data into TXFIFO to prevent from underrun */
   @@ -219,8 +213,7 @@
    
        /* Wait until flash finished program */
        check_if_finished();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess)) {
        }
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   @@ -244,7 +237,7 @@
    
        npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        while (npages) {
   -        write_page(address, (uint32_t*) src);
   +        write_page(address, (uint32_t *) src);
            npages--;
            address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        }
   @@ -253,13 +246,12 @@
    
    static int
    nxp_qspi_erase_sector(const struct hal_flash *dev,
   -                         uint32_t sector_address)
   +                      uint32_t sector_address)
    {
        sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
        sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
        QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
   @@ -286,8 +278,7 @@
        nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
        while (nsects) {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
            QSPI_SetIPCommandAddress(QuadSPI0, address);
   @@ -296,7 +287,7 @@
            check_if_finished();
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
   -    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   +        (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
            QSPI_ClearCache(QuadSPI0);
    #endif
            nsects--;
   @@ -323,8 +314,7 @@
    {
        uint32_t val[4] = {0x40U, 0, 0, 0};
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
    
   @@ -373,7 +363,7 @@
        PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB2), MYNEWT_VAL(QSPIB_MUX));
        PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOBA), MYNEWT_VAL(QSPIB_MUX));
    
   -    //Configure the baudrate too.
   +    /*Configure the baudrate too. */
    
        QSPI_Init(QuadSPI0, &qspi_cfg, CLOCK_GetFreq(kCLOCK_McgPll0Clk));
    
   @@ -390,21 +380,21 @@
    }
    
    static const struct hal_flash_funcs nxp_qspi_funcs = {
   -        .hff_read = nxp_qspi_read,
   -        .hff_write = nxp_qspi_write,
   -        .hff_erase_sector = nxp_qspi_erase_sector,
   -        .hff_sector_info = nxp_qspi_sector_info,
   -        .hff_init = nxp_qspi_init,
   -        .hff_erase = nxp_qspi_erase
   -    };
   +    .hff_read = nxp_qspi_read,
   +    .hff_write = nxp_qspi_write,
   +    .hff_erase_sector = nxp_qspi_erase_sector,
   +    .hff_sector_info = nxp_qspi_sector_info,
   +    .hff_init = nxp_qspi_init,
   +    .hff_erase = nxp_qspi_erase
   +};
    
    const struct hal_flash nxp_qspi_dev = {
   -        .hf_itf = &nxp_qspi_funcs,
   -        .hf_base_addr = FSL_FEATURE_QSPI_AMBA_BASE,
   -        .hf_size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE),
   -        .hf_sector_cnt = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT),
   -        .hf_align = 8,
   -        .hf_erased_val = 0xff,
   -    };
   -
   -#endif
   +    .hf_itf = &nxp_qspi_funcs,
   +    .hf_base_addr = FSL_FEATURE_QSPI_AMBA_BASE,
   +    .hf_size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE),
   +    .hf_sector_cnt = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT),
   +    .hf_align = 8,
   +    .hf_erased_val = 0xff,
   +};
   +
   +#endif
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_spi.c
   <details>
   
   ```diff
   @@ -38,7 +38,7 @@
    };
    
    struct nxp_hal_spi {
   -    SPI_Type* dev;
   +    SPI_Type * dev;
        uint32_t clk_pin;
        uint32_t pcs_pin;
        uint32_t sout_pin;
   @@ -48,7 +48,7 @@
        IRQn_Type irqn;
        void (*irq_handler)(void);
        hal_spi_txrx_cb txrx_cb;
   -    void* txrx_cb_arg;
   +    void * txrx_cb_arg;
        bool enabled;
        enum spi_type_t type;
    };
   @@ -265,7 +265,7 @@
    static void
    hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
    {
   -    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
   +    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
    
        if (status == kStatus_Success) {
            if (spi->txrx_cb) {
   @@ -277,7 +277,7 @@
    static void
    hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
    {
   -    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
   +    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
    
        if (status == kStatus_Success) {
            if (spi->txrx_cb) {
   @@ -293,7 +293,7 @@
        struct nxp_spi_master *master;
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   +        master = (struct nxp_spi_master *) spi;
            PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
   @@ -311,7 +311,7 @@
        struct nxp_spi_slave *slave;
    
        if (spi->type == HAL_SPI_TYPE_SLAVE) {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
   @@ -406,7 +406,7 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   +        master = (struct nxp_spi_master *) spi;
    
            master->config.ctarConfig.baudRate = settings->baudrate;
            master->config.ctarConfig.pcsToSckDelayInNanoSec =
   @@ -424,7 +424,7 @@
            master->config.ctarConfig.cpol = cpol;
            master->config.ctarConfig.cpha = cpha;
        } else {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            slave->config.ctarConfig.bitsPerFrame =
                (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
            slave->config.ctarConfig.cpol = cpol;
   @@ -448,13 +448,13 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -    master = (struct nxp_spi_master*) spi;
   -    DSPI_MasterInit(spi->dev,
   +        master = (struct nxp_spi_master *) spi;
   +        DSPI_MasterInit(spi->dev,
                        &master->config,
                        CLOCK_GetFreq(kCLOCK_BusClk));
        } else {
   -    slave = (struct nxp_spi_slave*) spi;
   -    DSPI_SlaveInit(spi->dev, &slave->config);
   +        slave = (struct nxp_spi_slave *) spi;
   +        DSPI_SlaveInit(spi->dev, &slave->config);
        }
    
        spi->enabled = true;
   @@ -496,8 +496,8 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        xfer.txData = (uint8_t*) &val;
   -        xfer.rxData = (uint8_t*) &retval;
   +        xfer.txData = (uint8_t *) &val;
   +        xfer.rxData = (uint8_t *) &retval;
            xfer.dataSize = 1;
            xfer.configFlags = kDSPI_MasterCtar0;
            DSPI_MasterTransferBlocking(spi->dev, &xfer);
   @@ -518,8 +518,8 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        xfer.txData = (uint8_t*) txbuf;
   -        xfer.rxData = (uint8_t*) rxbuf;
   +        xfer.txData = (uint8_t *) txbuf;
   +        xfer.rxData = (uint8_t *) rxbuf;
            xfer.dataSize = len;
            xfer.configFlags = kDSPI_MasterCtar0;
            rc = DSPI_MasterTransferBlocking(spi->dev, &xfer);
   @@ -556,26 +556,26 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   -        //master->handle
   +        master = (struct nxp_spi_master *) spi;
   +        /*master->handle */
            DSPI_MasterTransferCreateHandle(spi->dev,
                                            &master->handle,
                                            hal_spi_master_xfer_cb,
                                            spi);
            xfer.configFlags = kDSPI_MasterCtar0;
   -        xfer.txData = (uint8_t*) txbuf;
   -        xfer.rxData = (uint8_t*) rxbuf;
   +        xfer.txData = (uint8_t *) txbuf;
   +        xfer.rxData = (uint8_t *) rxbuf;
            xfer.dataSize = len;
            rc = DSPI_MasterTransferNonBlocking(spi->dev, &master->handle, &xfer);
        } else {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            DSPI_SlaveTransferCreateHandle(spi->dev,
                                           &slave->handle,
                                           hal_spi_slave_xfer_cb,
                                           spi);
            xfer.configFlags = kDSPI_SlaveCtar0;
   -        xfer.txData = (uint8_t*) txbuf;
   -        xfer.rxData = (uint8_t*) rxbuf;
   +        xfer.txData = (uint8_t *) txbuf;
   +        xfer.rxData = (uint8_t *) rxbuf;
            xfer.dataSize = len;
            rc = DSPI_SlaveTransferNonBlocking(spi->dev, &slave->handle, &xfer);
    
   @@ -614,10 +614,10 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   +        master = (struct nxp_spi_master *) spi;
            DSPI_MasterTransferAbort(spi->dev, &master->handle);
        } else {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            DSPI_SlaveTransferAbort(spi->dev, &slave->handle);
        }
        return 0;
   ```
   
   </details>
   
   #### hw/bsp/frdm-k64f/src/hal_bsp.c
   <details>
   
   ```diff
   @@ -98,7 +98,8 @@
        }
    };
    
   -static void init_hardware(void)
   +static void
   +init_hardware(void)
    {
        /* Disable the MPU otherwise USB cannot access the bus */
        SYSMPU->CESR = 0;
   ```
   
   </details>


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[GitHub] [mynewt-core] mlaz merged pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
mlaz merged pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466


   


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[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

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apache-mynewt-bot commented on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-773577569


   
   <!-- style-bot -->
   
   ## Style check summary
   
   ### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
   
   
   #### hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c
   <details>
   
   ```diff
   @@ -187,15 +187,15 @@
     ******************************************************************************/
    
    #ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
   -static void CLOCK_FllStableDelay(void)
   +static void
   +CLOCK_FllStableDelay(void)
    {
        /*
           Should wait at least 1ms. Because in these modes, the core clock is 100MHz
           at most, so this function could obtain the 1ms delay.
         */
        volatile uint32_t i = 30000U;
   -    while (0U != (i--))
   -    {
   +    while (0U != (i--)) {
            __NOP();
        }
    }
   @@ -207,34 +207,35 @@
    extern void CLOCK_FllStableDelay(void);
    #endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */
    
   -static uint32_t CLOCK_GetMcgExtClkFreq(void)
   +static uint32_t
   +CLOCK_GetMcgExtClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (MCG_C7_OSCSEL_VAL)
   -    {
   -        case 0U:
   -            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   -            assert(0U != g_xtal0Freq);
   -            freq = g_xtal0Freq;
   -            break;
   -        case 1U:
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(0U != g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 2U:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (MCG_C7_OSCSEL_VAL) {
   +    case 0U:
   +        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   +        assert(0U != g_xtal0Freq);
   +        freq = g_xtal0Freq;
   +        break;
   +    case 1U:
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(0U != g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 2U:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllExtRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllExtRefClkFreq(void)
    {
        /* FllExtRef = McgExtRef / FllExtRefDiv */
        uint8_t frdiv;
   @@ -246,54 +247,50 @@
        frdiv = MCG_C1_FRDIV_VAL;
        freq >>= frdiv;
    
   -    range  = MCG_C2_RANGE_VAL;
   +    range = MCG_C2_RANGE_VAL;
        oscsel = MCG_C7_OSCSEL_VAL;
    
        /*
           When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536.
           1. MCG_C7[OSCSEL] selects IRC48M.
           2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0.
   -    */
   -    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel))
   -    {
   -        switch (frdiv)
   -        {
   -            case 0:
   -            case 1:
   -            case 2:
   -            case 3:
   -            case 4:
   -            case 5:
   -                freq >>= 5u;
   -                break;
   -            case 6:
   -                /* 64*20=1280 */
   -                freq /= 20u;
   -                break;
   -            case 7:
   -                /* 128*12=1536 */
   -                freq /= 12u;
   -                break;
   -            default:
   -                freq = 0u;
   -                break;
   +     */
   +    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel)) {
   +        switch (frdiv) {
   +        case 0:
   +        case 1:
   +        case 2:
   +        case 3:
   +        case 4:
   +        case 5:
   +            freq >>= 5u;
   +            break;
   +        case 6:
   +            /* 64*20=1280 */
   +            freq /= 20u;
   +            break;
   +        case 7:
   +            /* 128*12=1536 */
   +            freq /= 12u;
   +            break;
   +        default:
   +            freq = 0u;
   +            break;
            }
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetInternalRefClkSelectFreq(void)
   +static uint32_t
   +CLOCK_GetInternalRefClkSelectFreq(void)
    {
        uint32_t freq;
    
   -    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL)
   -    {
   +    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL) {
            /* Slow internal reference clock selected*/
            freq = s_slowIrcFreq;
   -    }
   -    else
   -    {
   +    } else   {
            /* Fast internal reference clock selected*/
            freq = s_fastIrcFreq >> MCG_SC_FCRDIV_VAL;
        }
   @@ -301,44 +298,40 @@
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If use external reference clock. */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            freq = CLOCK_GetFllExtRefClkFreq();
        }
        /* If use internal reference clock. */
   -    else
   -    {
   +    else {
            freq = s_slowIrcFreq;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetPll0RefFreq(void)
   +static uint32_t
   +CLOCK_GetPll0RefFreq(void)
    {
        /* MCG external reference clock. */
        return CLOCK_GetMcgExtClkFreq();
    }
    
   -static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
   +static uint8_t
   +CLOCK_GetOscRangeFromFreq(uint32_t freq)
    {
        uint8_t range;
    
   -    if (freq <= 39063U)
   -    {
   +    if (freq <= 39063U) {
            range = 0U;
   -    }
   -    else if (freq <= 8000000U)
   -    {
   +    } else if (freq <= 8000000U)   {
            range = 1U;
   -    }
   -    else
   -    {
   +    } else   {
            range = 2U;
        }
    
   @@ -350,17 +343,15 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetOsc0ErClkFreq(void)
   +uint32_t
   +CLOCK_GetOsc0ErClkFreq(void)
    {
        uint32_t freq;
   -    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)
   -    {
   +    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U) {
            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
            assert(g_xtal0Freq);
            freq = g_xtal0Freq;
   -    }
   -    else
   -    {
   +    } else   {
            freq = 0U;
        }
    
   @@ -372,26 +363,26 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetEr32kClkFreq(void)
   +uint32_t
   +CLOCK_GetEr32kClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT1_OSC32KSEL_VAL)
   -    {
   -        case 0U: /* OSC 32k clock  */
   -            freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   -            break;
   -        case 2U: /* RTC 32k clock  */
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 3U: /* LPO clock      */
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT1_OSC32KSEL_VAL) {
   +    case 0U:     /* OSC 32k clock  */
   +        freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   +        break;
   +    case 2U:     /* RTC 32k clock  */
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 3U:     /* LPO clock      */
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
        return freq;
    }
   @@ -401,24 +392,24 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPllFllSelClkFreq(void)
   +uint32_t
   +CLOCK_GetPllFllSelClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT2_PLLFLLSEL_VAL)
   -    {
   -        case 0U: /* FLL. */
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case 1U: /* PLL. */
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case 3U: /* MCG IRC48M. */
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT2_PLLFLLSEL_VAL) {
   +    case 0U:     /* FLL. */
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case 1U:     /* PLL. */
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case 3U:     /* MCG IRC48M. */
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -429,7 +420,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPlatClkFreq(void)
   +uint32_t
   +CLOCK_GetPlatClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -439,7 +431,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlashClkFreq(void)
   +uint32_t
   +CLOCK_GetFlashClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
    }
   @@ -449,7 +442,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlexBusClkFreq(void)
   +uint32_t
   +CLOCK_GetFlexBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
    }
   @@ -459,7 +453,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetBusClkFreq(void)
   +uint32_t
   +CLOCK_GetBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
    }
   @@ -469,7 +464,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetCoreSysClkFreq(void)
   +uint32_t
   +CLOCK_GetCoreSysClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -484,55 +480,55 @@
     * param clockName Clock names defined in clock_name_t
     * return Clock frequency value in Hertz
     */
   -uint32_t CLOCK_GetFreq(clock_name_t clockName)
   +uint32_t
   +CLOCK_GetFreq(clock_name_t clockName)
    {
        uint32_t freq;
    
   -    switch (clockName)
   -    {
   -        case kCLOCK_CoreSysClk:
   -        case kCLOCK_PlatClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   -            break;
   -        case kCLOCK_BusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlexBusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlashClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   -            break;
   -        case kCLOCK_PllFllSelClk:
   -            freq = CLOCK_GetPllFllSelClkFreq();
   -            break;
   -        case kCLOCK_Er32kClk:
   -            freq = CLOCK_GetEr32kClkFreq();
   -            break;
   -        case kCLOCK_Osc0ErClk:
   -            freq = CLOCK_GetOsc0ErClkFreq();
   -            break;
   -        case kCLOCK_McgFixedFreqClk:
   -            freq = CLOCK_GetFixedFreqClkFreq();
   -            break;
   -        case kCLOCK_McgInternalRefClk:
   -            freq = CLOCK_GetInternalRefClkFreq();
   -            break;
   -        case kCLOCK_McgFllClk:
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case kCLOCK_McgPll0Clk:
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case kCLOCK_McgIrc48MClk:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        case kCLOCK_LpoClk:
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (clockName) {
   +    case kCLOCK_CoreSysClk:
   +    case kCLOCK_PlatClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   +        break;
   +    case kCLOCK_BusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlexBusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlashClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   +        break;
   +    case kCLOCK_PllFllSelClk:
   +        freq = CLOCK_GetPllFllSelClkFreq();
   +        break;
   +    case kCLOCK_Er32kClk:
   +        freq = CLOCK_GetEr32kClkFreq();
   +        break;
   +    case kCLOCK_Osc0ErClk:
   +        freq = CLOCK_GetOsc0ErClkFreq();
   +        break;
   +    case kCLOCK_McgFixedFreqClk:
   +        freq = CLOCK_GetFixedFreqClkFreq();
   +        break;
   +    case kCLOCK_McgInternalRefClk:
   +        freq = CLOCK_GetInternalRefClkFreq();
   +        break;
   +    case kCLOCK_McgFllClk:
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case kCLOCK_McgPll0Clk:
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case kCLOCK_McgIrc48MClk:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    case kCLOCK_LpoClk:
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -545,7 +541,8 @@
     *
     * param config Pointer to the configure structure.
     */
   -void CLOCK_SetSimConfig(sim_clock_config_t const *config)
   +void
   +CLOCK_SetSimConfig(sim_clock_config_t const *config)
    {
        SIM->CLKDIV1 = config->clkdiv1;
        CLOCK_SetPllFllSelClock(config->pllFllSel);
   @@ -559,35 +556,32 @@
     * retval true The clock is set successfully.
     * retval false The clock source is invalid to get proper USB FS clock.
     */
   -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
   +bool
   +CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
    {
        bool ret = true;
    
        CLOCK_DisableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcExt == src)
   -    {
   +    if (kCLOCK_UsbSrcExt == src) {
            SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
   -    }
   -    else
   -    {
   -        switch (freq)
   -        {
   -            case 120000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 96000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            case 72000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 48000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            default:
   -                ret = false;
   -                break;
   +    } else   {
   +        switch (freq) {
   +        case 120000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 96000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        case 72000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 48000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        default:
   +            ret = false;
   +            break;
            }
    
            SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src);
   @@ -595,8 +589,7 @@
    
        CLOCK_EnableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcIrc48M == src)
   -    {
   +    if (kCLOCK_UsbSrcIrc48M == src) {
            USB0->CLK_RECOVER_IRC_EN = 0x03U;
            USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
        }
   @@ -611,28 +604,28 @@
     *
     * return The frequency of MCGOUTCLK.
     */
   -uint32_t CLOCK_GetOutClkFreq(void)
   +uint32_t
   +CLOCK_GetOutClkFreq(void)
    {
        uint32_t mcgoutclk;
        uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
    
   -    switch (clkst)
   -    {
   -        case (uint32_t)kMCG_ClkOutStatPll:
   -            mcgoutclk = CLOCK_GetPll0Freq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatFll:
   -            mcgoutclk = CLOCK_GetFllFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatInt:
   -            mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatExt:
   -            mcgoutclk = CLOCK_GetMcgExtClkFreq();
   -            break;
   -        default:
   -            mcgoutclk = 0U;
   -            break;
   +    switch (clkst) {
   +    case (uint32_t)kMCG_ClkOutStatPll:
   +        mcgoutclk = CLOCK_GetPll0Freq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatFll:
   +        mcgoutclk = CLOCK_GetFllFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatInt:
   +        mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatExt:
   +        mcgoutclk = CLOCK_GetMcgExtClkFreq();
   +        break;
   +    default:
   +        mcgoutclk = 0U;
   +        break;
        }
    
        return mcgoutclk;
   @@ -647,7 +640,8 @@
     *
     * return The frequency of MCGFLLCLK.
     */
   -uint32_t CLOCK_GetFllFreq(void)
   +uint32_t
   +CLOCK_GetFllFreq(void)
    {
        static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}};
    
   @@ -656,23 +650,17 @@
        uint32_t ret;
    
        /* If FLL is not enabled currently, then return 0U. */
   -    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U)))
   -    {
   +    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) {
            ret = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            /* Get FLL reference clock frequency. */
            freq = CLOCK_GetFllRefClkFreq();
   -        if (0U == freq)
   -        {
   +        if (0U == freq) {
                ret = freq;
   -        }
   -        else
   -        {
   -            drs   = MCG_C4_DRST_DRS_VAL;
   +        } else   {
   +            drs = MCG_C4_DRST_DRS_VAL;
                dmx32 = MCG_C4_DMX32_VAL;
   -            ret   = freq * fllFactorTable[drs][dmx32];
   +            ret = freq * fllFactorTable[drs][dmx32];
            }
        }
    
   @@ -687,17 +675,15 @@
     *
     * return The frequency of MCGIRCLK.
     */
   -uint32_t CLOCK_GetInternalRefClkFreq(void)
   +uint32_t
   +CLOCK_GetInternalRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If MCGIRCLK is gated. */
   -    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK))
   -    {
   +    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            freq = CLOCK_GetInternalRefClkSelectFreq();
        }
    
   @@ -712,18 +698,16 @@
     *
     * return The frequency of MCGFFCLK.
     */
   -uint32_t CLOCK_GetFixedFreqClkFreq(void)
   +uint32_t
   +CLOCK_GetFixedFreqClkFreq(void)
    {
        uint32_t freq = CLOCK_GetFllRefClkFreq();
        uint32_t ret;
    
        /* MCGFFCLK must be no more than MCGOUTCLK/8. */
   -    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq))
   -    {
   +    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq)) {
            ret = freq;
   -    }
   -    else
   -    {
   +    } else   {
            ret = 0U;
        }
    
   @@ -738,7 +722,8 @@
     *
     * return The frequency of MCGPLL0CLK.
     */
   -uint32_t CLOCK_GetPll0Freq(void)
   +uint32_t
   +CLOCK_GetPll0Freq(void)
    {
        uint32_t mcgpll0clk;
        uint32_t freq;
   @@ -746,12 +731,9 @@
        uint8_t mcgpll0prdiv;
        uint8_t mcgpll0vdiv;
        /* If PLL0 is not enabled, return 0. */
   -    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            mcgpll0clk = CLOCK_GetPll0RefFreq();
    
            /*
   @@ -783,36 +765,31 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success External reference clock set successfully.
     */
   -status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
    {
        bool needDelay;
        uint32_t i;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */
   -    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK)))
   -    {
   +    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) {
            return kStatus_MCG_SourceUsed;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
    
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel)
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel) {
            /* If change OSCSEL, need to delay, ERR009878. */
            needDelay = true;
   -    }
   -    else
   -    {
   +    } else   {
            needDelay = false;
        }
    
        MCG->C7 = (uint8_t)(MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
   -    if (needDelay)
   -    {
   +    if (needDelay) {
            /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
            i = 1500U;
   -        while (0U != (i--))
   -        {
   +        while (0U != (i--)) {
                __NOP();
            }
        }
   @@ -836,34 +813,30 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success MCGIRCLK configuration finished successfully.
     */
   -status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
   +status_t
   +CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
    {
        uint32_t mcgOutClkState = (uint32_t)MCG_S_CLKST_VAL;
   -    mcg_irc_mode_t curIrcs  = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   -    uint8_t curFcrdiv       = MCG_SC_FCRDIV_VAL;
   +    mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   +    uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If MCGIRCLK is used as system clock source. */
   -    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState)
   -    {
   +    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState) {
            /* If need to change MCGIRCLK source or driver, return error. */
   -        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs))
   -        {
   +        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) {
                return kStatus_MCG_SourceUsed;
            }
        }
    #endif
    
        /* If need to update the FCRDIV. */
   -    if (fcrdiv != curFcrdiv)
   -    {
   +    if (fcrdiv != curFcrdiv) {
            /* If fast IRC is in use currently, change to slow IRC. */
            if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) &&
   -            (kMCG_IrcFast == curIrcs))
   -        {
   +            (kMCG_IrcFast == curIrcs)) {
                MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
   -            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow)
   -            {
   +            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow) {
                }
            }
            /* Update FCRDIV. */
   @@ -876,10 +849,8 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode);
    
        /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
   -    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable)))
   -    {
   -        while (MCG_S_IRCST_VAL != (uint8_t)ircs)
   -        {
   +    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable))) {
   +        while (MCG_S_IRCST_VAL != (uint8_t)ircs) {
            }
        }
    
   @@ -901,7 +872,8 @@
     * param vdiv       VDIV value to generate desired PLL frequency.
     * return Closest frequency match that the PLL was able generate.
     */
   -uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
   +uint32_t
   +CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
    {
        uint8_t ret_prdiv;               /* PRDIV to return. */
        uint8_t ret_vdiv;                /* VDIV to return.  */
   @@ -910,7 +882,7 @@
        uint8_t prdiv_cur;               /* PRDIV value for iteration.    */
        uint8_t vdiv_cur;                /* VDIV value for iteration.     */
        uint32_t ret_freq = 0U;          /* PLL output frequency to return. */
   -    uint32_t diff     = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */
   +    uint32_t diff = 0xFFFFFFFFU;     /* Difference between desireFreq and return frequency. */
        uint32_t ref_div;                /* Reference frequency after PRDIV. */
    
        /*
   @@ -929,8 +901,7 @@
        /* Reference frequency is out of range. */
        if ((refFreq < (uint32_t)FSL_FEATURE_MCG_PLL_REF_MIN) ||
            (refFreq > ((uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX *
   -                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE))))
   -    {
   +                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) {
            return 0U;
        }
    
   @@ -940,62 +911,52 @@
            (uint8_t)((refFreq + (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX);
    
        /* PRDIV traversal. */
   -    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--)
   -    {
   +    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) {
            /* Reference frequency after PRDIV. */
            ref_div = refFreq / prdiv_cur;
    
            vdiv_cur = (uint8_t)(desireFreq / ref_div);
    
            if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) ||
   -            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                /* No VDIV is available with this PRDIV. */
                continue;
            }
    
            ret_freq = vdiv_cur * ref_div;
    
   -        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE)
   -        {
   -            if (ret_freq == desireFreq) /* If desire frequency is got. */
   -            {
   +        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) {
   +            if (ret_freq == desireFreq) { /* If desire frequency is got. */
                    *prdiv = prdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -                *vdiv  = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +                *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
                    return ret_freq;
                }
                /* New PRDIV/VDIV is closer. */
   -            if (diff > desireFreq - ret_freq)
   -            {
   -                diff      = desireFreq - ret_freq;
   +            if (diff > desireFreq - ret_freq) {
   +                diff = desireFreq - ret_freq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
            vdiv_cur++;
   -        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                ret_freq += ref_div;
                /* New PRDIV/VDIV is closer. */
   -            if (diff > ret_freq - desireFreq)
   -            {
   -                diff      = ret_freq - desireFreq;
   +            if (diff > ret_freq - desireFreq) {
   +                diff = ret_freq - desireFreq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
        }
    
   -    if (0xFFFFFFFFU != diff)
   -    {
   +    if (0xFFFFFFFFU != diff) {
            /* PRDIV/VDIV found. */
   -        *prdiv   = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -        *vdiv    = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +        *prdiv = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   +        *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
            ret_freq = (refFreq / ret_prdiv) * ret_vdiv;
            return ret_freq;
   -    }
   -    else
   -    {
   +    } else   {
            /* No proper PRDIV/VDIV found. */
            return 0U;
        }
   @@ -1012,7 +973,8 @@
     *
     * param config Pointer to the configuration structure.
     */
   -void CLOCK_EnablePll0(mcg_pll_config_t const *config)
   +void
   +CLOCK_EnablePll0(mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1027,8 +989,7 @@
        MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode);
    
        /* Wait for PLL lock. */
   -    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
        }
    }
    
   @@ -1039,23 +1000,18 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
    {
        /* Clear the previous flag, MCG_SC[LOCS0]. */
        MCG->SC &= ~(uint8_t)MCG_SC_ATMF_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= ~(uint8_t)MCG_C6_CME0_MASK;
   -    }
   -    else
   -    {
   -        if (kMCG_MonitorInt == mode)
   -        {
   +    } else   {
   +        if (kMCG_MonitorInt == mode) {
                MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK;
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C2 |= MCG_C2_LOCRE0_MASK;
            }
            MCG->C6 |= MCG_C6_CME0_MASK;
   @@ -1069,16 +1025,15 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8 = MCG->C8;
    
        mcg_c8 &= ~(uint8_t)(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK);
    
   -    if (kMCG_MonitorNone != mode)
   -    {
   -        if (kMCG_MonitorReset == mode)
   -        {
   +    if (kMCG_MonitorNone != mode) {
   +        if (kMCG_MonitorReset == mode) {
                mcg_c8 |= MCG_C8_LOCRE1_MASK;
            }
            mcg_c8 |= MCG_C8_CME1_MASK;
   @@ -1093,29 +1048,24 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8;
    
        /* Clear previous flag. */
        MCG->S = MCG_S_LOLS0_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= (uint8_t)(~MCG_C6_LOLIE0_MASK);
   -    }
   -    else
   -    {
   +    } else   {
            mcg_c8 = MCG->C8;
    
            mcg_c8 &= (uint8_t)(~MCG_C8_LOCS1_MASK);
    
   -        if (kMCG_MonitorInt == mode)
   -        {
   +        if (kMCG_MonitorInt == mode) {
                mcg_c8 &= (uint8_t)(~MCG_C8_LOLRE_MASK);
   -        }
   -        else
   -        {
   +        } else   {
                mcg_c8 |= MCG_C8_LOLRE_MASK;
            }
            MCG->C8 = mcg_c8;
   @@ -1149,29 +1099,25 @@
     *
     * return  Logical OR value of the ref _mcg_status_flags_t.
     */
   -uint32_t CLOCK_GetStatusFlags(void)
   -{
   -    uint32_t ret  = 0U;
   +uint32_t
   +CLOCK_GetStatusFlags(void)
   +{
   +    uint32_t ret = 0U;
        uint8_t mcg_s = MCG->S;
    
   -    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U)
   -    {
   +    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0LostFlag;
        }
   -    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0InitFlag;
        }
   -    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK))
   -    {
   +    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK)) {
            ret |= (uint32_t)kMCG_RtcOscLostFlag;
        }
   -    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LostFlag;
        }
   -    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LockFlag;
        }
        return ret;
   @@ -1193,21 +1139,19 @@
     * param mask The status flags to clear. This is a logical OR of members of the
     *             enumeration ref _mcg_status_flags_t.
     */
   -void CLOCK_ClearStatusFlags(uint32_t mask)
   +void
   +CLOCK_ClearStatusFlags(uint32_t mask)
    {
        uint8_t reg;
    
   -    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL) {
            MCG->SC &= (uint8_t)(~MCG_SC_ATMF_MASK);
        }
   -    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag))
   -    {
   -        reg     = MCG->C8;
   +    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag)) {
   +        reg = MCG->C8;
            MCG->C8 = reg;
        }
   -    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL) {
            MCG->S = MCG_S_LOLS0_MASK;
        }
    }
   @@ -1219,7 +1163,8 @@
     *
     * param  config Pointer to the OSC0 configuration structure.
     */
   -void CLOCK_InitOsc0(osc_config_t const *config)
   +void
   +CLOCK_InitOsc0(osc_config_t const *config)
    {
        uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq);
    
   @@ -1228,11 +1173,9 @@
        MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode);
        OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
    
   -    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U))
   -    {
   +    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)) {
            /* Wait for stable. */
   -        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -        {
   +        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
            }
        }
    }
   @@ -1242,7 +1185,8 @@
     *
     * This function deinitializes the OSC0.
     */
   -void CLOCK_DeinitOsc0(void)
   +void
   +CLOCK_DeinitOsc0(void)
    {
        OSC0->CR = 0U;
        MCG->C2 &= ~(uint8_t)OSC_MODE_MASK;
   @@ -1253,7 +1197,8 @@
     *
     * param freq The Slow IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetSlowIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetSlowIrcFreq(uint32_t freq)
    {
        s_slowIrcFreq = freq;
    }
   @@ -1263,7 +1208,8 @@
     *
     * param freq The Fast IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetFastIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetFastIrcFreq(uint32_t freq)
    {
        s_fastIrcFreq = freq;
    }
   @@ -1286,7 +1232,8 @@
     * retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
     * retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
     */
   -status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
   +status_t
   +CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
    {
        uint32_t multi; /* extFreq / desireFreq */
        uint32_t actv;  /* Auto trim value. */
   @@ -1299,30 +1246,24 @@
            {TRIM_FIRC_MIN, TRIM_FIRC_MAX}  /* Fast IRC. */
        };
    
   -    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN))
   -    {
   +    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) {
            status = kStatus_MCG_AtmBusClockInvalid;
        }
        /* Check desired frequency range. */
   -    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1]))
   -    {
   +    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) {
            status = kStatus_MCG_AtmDesiredFreqInvalid;
        }
        /*
           Make sure internal reference clock is not used to generate bus clock.
           Here only need to check (MCG_S_IREFST == 1).
         */
   -    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK))
   -    {
   +    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) {
            status = kStatus_MCG_AtmIrcUsed;
   -    }
   -    else
   -    {
   +    } else   {
            multi = extFreq / desireFreq;
   -        actv  = multi * 21U;
   -
   -        if (kMCG_AtmSel4m == atms)
   -        {
   +        actv = multi * 21U;
   +
   +        if (kMCG_AtmSel4m == atms) {
                actv *= 128U;
            }
    
   @@ -1336,27 +1277,20 @@
            MCG->SC = (mcg_sc | MCG_SC_ATME_MASK);
    
            /* Wait for MCG finished. */
   -        while (0U != (MCG->SC & MCG_SC_ATME_MASK))
   -        {
   +        while (0U != (MCG->SC & MCG_SC_ATME_MASK)) {
            }
    
            /* Error occurs? */
   -        if (0U != (MCG->SC & MCG_SC_ATMF_MASK))
   -        {
   +        if (0U != (MCG->SC & MCG_SC_ATMF_MASK)) {
                /* Clear the failed flag. */
                MCG->SC = mcg_sc;
   -            status  = kStatus_MCG_AtmHardwareFail;
   -        }
   -        else
   -        {
   +            status = kStatus_MCG_AtmHardwareFail;
   +        } else   {
                *actualFreq = extFreq / multi;
    
   -            if (kMCG_AtmSel4m == atms)
   -            {
   +            if (kMCG_AtmSel4m == atms) {
                    s_fastIrcFreq = *actualFreq;
   -            }
   -            else
   -            {
   +            } else   {
                    s_slowIrcFreq = *actualFreq;
                }
            }
   @@ -1372,103 +1306,83 @@
     *
     * return Current MCG mode or error code; See ref mcg_mode_t.
     */
   -mcg_mode_t CLOCK_GetMode(void)
   +mcg_mode_t
   +CLOCK_GetMode(void)
    {
        mcg_mode_t mode = kMCG_ModeError;
   -    uint32_t clkst  = (uint32_t)MCG_S_CLKST_VAL;
   +    uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
        uint32_t irefst = (uint32_t)MCG_S_IREFST_VAL;
   -    uint32_t lp     = (uint32_t)MCG_C2_LP_VAL;
   -    uint32_t pllst  = MCG_S_PLLST_VAL;
   +    uint32_t lp = (uint32_t)MCG_C2_LP_VAL;
   +    uint32_t pllst = MCG_S_PLLST_VAL;
    
        /*------------------------------------------------------------------
                               Mode and Registers
   -    ____________________________________________________________________
   -
   -      Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   -    ____________________________________________________________________
   -
   -      FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -      PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   -    ____________________________________________________________________
   -
   -      PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -    ----------------------------------------------------------------------*/
   -
   -    if (clkst == (uint32_t)kMCG_ClkOutStatFll)
   -    {
   -        if ((uint32_t)kMCG_FllSrcExternal == irefst)
   -        {
   +       ____________________________________________________________________
   +
   +       Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   +       ____________________________________________________________________
   +
   +       FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   +       ____________________________________________________________________
   +
   +       PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       ----------------------------------------------------------------------*/
   +
   +    if (clkst == (uint32_t)kMCG_ClkOutStatFll) {
   +        if ((uint32_t)kMCG_FllSrcExternal == irefst) {
                mode = kMCG_ModeFEE;
   -        }
   -        else
   -        {
   +        } else   {
                mode = kMCG_ModeFEI;
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatInt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatInt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPI;
   -        }
   -        else
   -        {
   +        } else   {
                {
                    mode = kMCG_ModeFBI;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatExt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatExt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPE;
   -        }
   -        else
   -        {
   -            if ((uint32_t)kMCG_PllstPll == pllst)
   -            {
   +        } else   {
   +            if ((uint32_t)kMCG_PllstPll == pllst) {
                    mode = kMCG_ModePBE;
   -            }
   -            else
   -            {
   +            } else   {
                    mode = kMCG_ModeFBE;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatPll)
   -    {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatPll)   {
            {
                mode = kMCG_ModePEE;
            }
   -    }
   -    else
   -    {
   +    } else   {
            /*do nothing*/
        }
    
   @@ -1490,15 +1404,15 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to a frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode)))
   -    {
   +    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1510,8 +1424,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1523,13 +1436,11 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1538,13 +1449,11 @@
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1566,15 +1475,15 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode)))
   -    {
   +    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1586,8 +1495,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1600,45 +1508,37 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
        /* Set DRS and DMX32. */
   -    mcg_c4  = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
   +    mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
        MCG->C4 = mcg_c4;
    
        /* Wait for DRST_DRS update. */
   -    while (MCG->C4 != mcg_c4)
   -    {
   +    while (MCG->C4 != mcg_c4) {
        }
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1661,7 +1561,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1670,9 +1571,7 @@
        mcg_mode_t mode = CLOCK_GetMode();
    
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModeBLPI == mode)))
   -
   -    {
   +          (kMCG_ModeBLPI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1687,8 +1586,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1700,26 +1598,22 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   -    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) {
        }
    
        MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1741,7 +1635,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1749,16 +1644,14 @@
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode)))
   -    {
   +          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
    
        /* Change to FLL mode. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Set LP bit to enable the FLL */
   @@ -1772,8 +1665,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1786,24 +1678,19 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for Reference clock Status bit to clear */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1812,13 +1699,11 @@
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for clock status bits to show clock source is ext ref clk */
   -    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for fll stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1834,11 +1719,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpiMode(void)
   +status_t
   +CLOCK_SetBlpiMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1858,11 +1743,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpeMode(void)
   +status_t
   +CLOCK_SetBlpeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1892,7 +1777,8 @@
     * configuration structure not necessary. In this case, pass in NULL.
     * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
     */
   -status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1907,14 +1793,12 @@
    
        /* Wait for CLKST clock status bits to show clock source is ext ref clk */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* Disable PLL first, then configure PLL. */
        MCG->C6 &= (uint8_t)(~MCG_C6_PLLS_MASK);
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Configure the PLL. */
   @@ -1926,8 +1810,7 @@
        MCG->C6 |= MCG_C6_PLLS_MASK;
    
        /* Wait for PLL mode changed. */
   -    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U) {
        }
    
        return kStatus_Success;
   @@ -1945,12 +1828,12 @@
     *       PRDIV/VDIV are different than in the PBE mode, set them up
     *       in PBE mode and wait. When the clock is stable, switch to PEE mode.
     */
   -status_t CLOCK_SetPeeMode(void)
   +status_t
   +CLOCK_SetPeeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (kMCG_ModePBE != mode)
   -    {
   +    if (kMCG_ModePBE != mode) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1959,8 +1842,7 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
    
        /* Wait for clock status bits to update */
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -1982,11 +1864,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
     */
   -status_t CLOCK_ExternalModeToFbeModeQuick(void)
   +status_t
   +CLOCK_ExternalModeToFbeModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) != 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) != 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1995,14 +1877,12 @@
        MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK);
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
        }
    
        /* Disable PLL. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        return kStatus_Success;
   @@ -2024,11 +1904,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
     */
   -status_t CLOCK_InternalModeToFbiModeQuick(void)
   +status_t
   +CLOCK_InternalModeToFbiModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) == 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) == 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif
   @@ -2037,8 +1917,7 @@
        MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        return kStatus_Success;
   @@ -2059,7 +1938,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
    }
   @@ -2079,8 +1959,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToFeeMode(
   -    mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeeMode(mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2100,15 +1980,15 @@
     * retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
   +status_t
   +CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
    {
        /* If reset mode is FEI mode, set MCGIRCLK and always success. */
        (void)CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
    
        /* If reset mode is not BLPI, first enter FBI mode. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        /* Enter BLPI mode. */
   @@ -2128,7 +2008,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2138,20 +2019,16 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* In FBE now, start to enter BLPE. */
   @@ -2173,7 +2050,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -2183,8 +2061,7 @@
    
        /* Change to use PLL output clock. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -2233,7 +2110,8 @@
     * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
     * function.
     */
   -status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
   +status_t
   +CLOCK_SetMcgConfig(const mcg_config_t *config)
    {
        mcg_mode_t next_mode;
        status_t status = kStatus_Success;
   @@ -2241,11 +2119,9 @@
        mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0;
    
        /* If need to change external clock, MCG_C7[OSCSEL]. */
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel))
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel)) {
            /* If external clock is in use, change to FEI first. */
   -        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -        {
   +        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
                (void)CLOCK_ExternalModeToFbeModeQuick();
                (void)CLOCK_SetFeiMode(config->dmx32, config->drs, NULL);
            }
   @@ -2254,8 +2130,7 @@
        }
    
        /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
   -    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt) {
            MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */
    
            {
   @@ -2268,67 +2143,56 @@
    
        next_mode = CLOCK_GetMode();
    
   -    do
   -    {
   +    do{
            next_mode = mcgModeMatrix[next_mode][config->mcgMode];
    
   -        switch (next_mode)
   -        {
   -            case kMCG_ModeFEI:
   -                status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFEE:
   -                status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFBI:
   -                status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeFBE:
   -                status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeBLPI:
   -                status = CLOCK_SetBlpiMode();
   -                break;
   -            case kMCG_ModeBLPE:
   -                status = CLOCK_SetBlpeMode();
   -                break;
   -            case kMCG_ModePBE:
   -                /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   -                if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode))
   +        switch (next_mode) {
   +        case kMCG_ModeFEI:
   +            status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFEE:
   +            status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFBI:
   +            status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeFBE:
   +            status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeBLPI:
   +            status = CLOCK_SetBlpiMode();
   +            break;
   +        case kMCG_ModeBLPE:
   +            status = CLOCK_SetBlpeMode();
   +            break;
   +        case kMCG_ModePBE:
   +            /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   +            if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) {
                    {
   -                    {
   -                        status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
   -                    }
   +                    status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
                    }
   -                else
   -                {
   -                    MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -                    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -                    {
   -                    }
   +            } else   {
   +                MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   +                while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
                    }
   -                break;
   -            case kMCG_ModePEE:
   -                status = CLOCK_SetPeeMode();
   -                break;
   -            default:
   -                assert(false);
   -                break;
   -        }
   -        if (kStatus_Success != status)
   -        {
   +            }
                break;
   +        case kMCG_ModePEE:
   +            status = CLOCK_SetPeeMode();
   +            break;
   +        default:
   +            assert(false);
   +            break;
   +        }
   +        if (kStatus_Success != status) {
   +            break;
            }
        } while (next_mode != config->mcgMode);
    
   -    if (status == kStatus_Success)
   -    {
   -        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U)
   -        {
   +    if (status == kStatus_Success) {
   +        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U) {
                CLOCK_EnablePll0(&config->pll0Config);
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_flash.c
   <details>
   
   ```diff
   @@ -6,7 +6,7 @@
     * to you under the Apache License, Version 2.0 (the
     * "License"); you may not use this file except in compliance
     * with the License.  You may obtain a copy of the License at
   -*
   + *
     *  http://www.apache.org/licenses/LICENSE-2.0
     *
     * Unless required by applicable law or agreed to in writing,
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_lpuart.c
   <details>
   
   ```diff
   @@ -59,10 +59,10 @@
        hal_uart_tx_char u_tx_func;
        hal_uart_tx_done u_tx_done;
        void *u_func_arg;
   -    uint8_t u_configured:1;
   -    uint8_t u_open:1;
   -    uint8_t u_tx_started:1;
   -    uint8_t u_rx_stall:1;
   +    uint8_t u_configured : 1;
   +    uint8_t u_open : 1;
   +    uint8_t u_tx_started : 1;
   +    uint8_t u_rx_stall : 1;
        struct uart_ring ur_tx;
        uint8_t tx_buffer[TX_BUF_SZ];
        struct uart_ring ur_rx;
   @@ -465,8 +465,7 @@
                uarts[port].ur_rx.ur_head = 0;
                uarts[port].ur_rx.ur_tail = 0;
                uarts[port].u_configured = 1;
   -        }
   -        else {
   +        } else   {
                uarts[port].u_configured = 0;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_qspi.c
   <details>
   
   ```diff
   @@ -84,7 +84,8 @@
        [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
    
        /* Match MISRA rule */
   -    [63] = 0};
   +    [63] = 0
   +};
    
    qspi_flash_config_t g_qspi_flash_cfg = {
        .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
   @@ -109,15 +110,12 @@
    {
        uint32_t val = 0;
        /* Check WIP bit */
   -    do
   -    {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +    do{
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
            QSPI_ExecuteIPCommand(QuadSPI0, 12U);
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            val = QuadSPI0->RBDR[0];
            /* Clear ARDB area */
   @@ -128,19 +126,17 @@
    static void
    cmd_write_enable()
    {
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ExecuteIPCommand(QuadSPI0, 4U);
    }
    
    static void
   -read_page(uint32_t address, uint32_t* dst)
   +read_page(uint32_t address, uint32_t * dst)
    {
        int i;
   -    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
   -    {
   -        dst[i] = ((uint32_t*)address)[i];
   +    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++) {
   +        dst[i] = ((uint32_t *)address)[i];
        }
    }
    
   @@ -172,15 +168,13 @@
    {
        uint32_t leftLongWords = 0;
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
    
        QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
        cmd_write_enable();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
    
        /* First write some data into TXFIFO to prevent from underrun */
   @@ -196,8 +190,7 @@
    
        /* Wait until flash finished program */
        check_if_finished();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess)) {
        }
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   @@ -221,7 +214,7 @@
    
        npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        while (npages) {
   -        write_page(address, (uint32_t*) src);
   +        write_page(address, (uint32_t *) src);
            npages--;
            address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        }
   @@ -230,13 +223,12 @@
    
    static int
    nxp_qspi_erase_sector(const struct hal_flash *dev,
   -                         uint32_t sector_address)
   +                      uint32_t sector_address)
    {
        sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
        sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
        QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
   @@ -263,8 +255,7 @@
        nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
        while (nsects) {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
            QSPI_SetIPCommandAddress(QuadSPI0, address);
   @@ -273,7 +264,7 @@
            check_if_finished();
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
   -    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   +        (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
            QSPI_ClearCache(QuadSPI0);
    #endif
            nsects--;
   @@ -300,8 +291,7 @@
    {
        uint32_t val[4] = {0x40U, 0, 0, 0};
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
    
   ```
   
   </details>


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[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot removed a comment on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-773628578


   
   <!-- style-bot -->
   
   ## Style check summary
   
   #### No suggestions at this time!
   


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[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot commented on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-772985567


   
   <!-- style-bot -->
   
   ## Style check summary
   
   ### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
   
   
   #### hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c
   <details>
   
   ```diff
   @@ -187,15 +187,15 @@
     ******************************************************************************/
    
    #ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
   -static void CLOCK_FllStableDelay(void)
   +static void
   +CLOCK_FllStableDelay(void)
    {
        /*
           Should wait at least 1ms. Because in these modes, the core clock is 100MHz
           at most, so this function could obtain the 1ms delay.
         */
        volatile uint32_t i = 30000U;
   -    while (0U != (i--))
   -    {
   +    while (0U != (i--)) {
            __NOP();
        }
    }
   @@ -207,34 +207,35 @@
    extern void CLOCK_FllStableDelay(void);
    #endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */
    
   -static uint32_t CLOCK_GetMcgExtClkFreq(void)
   +static uint32_t
   +CLOCK_GetMcgExtClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (MCG_C7_OSCSEL_VAL)
   -    {
   -        case 0U:
   -            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   -            assert(0U != g_xtal0Freq);
   -            freq = g_xtal0Freq;
   -            break;
   -        case 1U:
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(0U != g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 2U:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (MCG_C7_OSCSEL_VAL) {
   +    case 0U:
   +        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   +        assert(0U != g_xtal0Freq);
   +        freq = g_xtal0Freq;
   +        break;
   +    case 1U:
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(0U != g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 2U:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllExtRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllExtRefClkFreq(void)
    {
        /* FllExtRef = McgExtRef / FllExtRefDiv */
        uint8_t frdiv;
   @@ -246,54 +247,50 @@
        frdiv = MCG_C1_FRDIV_VAL;
        freq >>= frdiv;
    
   -    range  = MCG_C2_RANGE_VAL;
   +    range = MCG_C2_RANGE_VAL;
        oscsel = MCG_C7_OSCSEL_VAL;
    
        /*
           When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536.
           1. MCG_C7[OSCSEL] selects IRC48M.
           2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0.
   -    */
   -    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel))
   -    {
   -        switch (frdiv)
   -        {
   -            case 0:
   -            case 1:
   -            case 2:
   -            case 3:
   -            case 4:
   -            case 5:
   -                freq >>= 5u;
   -                break;
   -            case 6:
   -                /* 64*20=1280 */
   -                freq /= 20u;
   -                break;
   -            case 7:
   -                /* 128*12=1536 */
   -                freq /= 12u;
   -                break;
   -            default:
   -                freq = 0u;
   -                break;
   +     */
   +    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel)) {
   +        switch (frdiv) {
   +        case 0:
   +        case 1:
   +        case 2:
   +        case 3:
   +        case 4:
   +        case 5:
   +            freq >>= 5u;
   +            break;
   +        case 6:
   +            /* 64*20=1280 */
   +            freq /= 20u;
   +            break;
   +        case 7:
   +            /* 128*12=1536 */
   +            freq /= 12u;
   +            break;
   +        default:
   +            freq = 0u;
   +            break;
            }
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetInternalRefClkSelectFreq(void)
   +static uint32_t
   +CLOCK_GetInternalRefClkSelectFreq(void)
    {
        uint32_t freq;
    
   -    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL)
   -    {
   +    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL) {
            /* Slow internal reference clock selected*/
            freq = s_slowIrcFreq;
   -    }
   -    else
   -    {
   +    } else   {
            /* Fast internal reference clock selected*/
            freq = s_fastIrcFreq >> MCG_SC_FCRDIV_VAL;
        }
   @@ -301,44 +298,40 @@
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If use external reference clock. */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            freq = CLOCK_GetFllExtRefClkFreq();
        }
        /* If use internal reference clock. */
   -    else
   -    {
   +    else {
            freq = s_slowIrcFreq;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetPll0RefFreq(void)
   +static uint32_t
   +CLOCK_GetPll0RefFreq(void)
    {
        /* MCG external reference clock. */
        return CLOCK_GetMcgExtClkFreq();
    }
    
   -static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
   +static uint8_t
   +CLOCK_GetOscRangeFromFreq(uint32_t freq)
    {
        uint8_t range;
    
   -    if (freq <= 39063U)
   -    {
   +    if (freq <= 39063U) {
            range = 0U;
   -    }
   -    else if (freq <= 8000000U)
   -    {
   +    } else if (freq <= 8000000U)   {
            range = 1U;
   -    }
   -    else
   -    {
   +    } else   {
            range = 2U;
        }
    
   @@ -350,17 +343,15 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetOsc0ErClkFreq(void)
   +uint32_t
   +CLOCK_GetOsc0ErClkFreq(void)
    {
        uint32_t freq;
   -    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)
   -    {
   +    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U) {
            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
            assert(g_xtal0Freq);
            freq = g_xtal0Freq;
   -    }
   -    else
   -    {
   +    } else   {
            freq = 0U;
        }
    
   @@ -372,26 +363,26 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetEr32kClkFreq(void)
   +uint32_t
   +CLOCK_GetEr32kClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT1_OSC32KSEL_VAL)
   -    {
   -        case 0U: /* OSC 32k clock  */
   -            freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   -            break;
   -        case 2U: /* RTC 32k clock  */
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 3U: /* LPO clock      */
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT1_OSC32KSEL_VAL) {
   +    case 0U:     /* OSC 32k clock  */
   +        freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   +        break;
   +    case 2U:     /* RTC 32k clock  */
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 3U:     /* LPO clock      */
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
        return freq;
    }
   @@ -401,24 +392,24 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPllFllSelClkFreq(void)
   +uint32_t
   +CLOCK_GetPllFllSelClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT2_PLLFLLSEL_VAL)
   -    {
   -        case 0U: /* FLL. */
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case 1U: /* PLL. */
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case 3U: /* MCG IRC48M. */
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT2_PLLFLLSEL_VAL) {
   +    case 0U:     /* FLL. */
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case 1U:     /* PLL. */
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case 3U:     /* MCG IRC48M. */
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -429,7 +420,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPlatClkFreq(void)
   +uint32_t
   +CLOCK_GetPlatClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -439,7 +431,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlashClkFreq(void)
   +uint32_t
   +CLOCK_GetFlashClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
    }
   @@ -449,7 +442,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlexBusClkFreq(void)
   +uint32_t
   +CLOCK_GetFlexBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
    }
   @@ -459,7 +453,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetBusClkFreq(void)
   +uint32_t
   +CLOCK_GetBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
    }
   @@ -469,7 +464,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetCoreSysClkFreq(void)
   +uint32_t
   +CLOCK_GetCoreSysClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -484,55 +480,55 @@
     * param clockName Clock names defined in clock_name_t
     * return Clock frequency value in Hertz
     */
   -uint32_t CLOCK_GetFreq(clock_name_t clockName)
   +uint32_t
   +CLOCK_GetFreq(clock_name_t clockName)
    {
        uint32_t freq;
    
   -    switch (clockName)
   -    {
   -        case kCLOCK_CoreSysClk:
   -        case kCLOCK_PlatClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   -            break;
   -        case kCLOCK_BusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlexBusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlashClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   -            break;
   -        case kCLOCK_PllFllSelClk:
   -            freq = CLOCK_GetPllFllSelClkFreq();
   -            break;
   -        case kCLOCK_Er32kClk:
   -            freq = CLOCK_GetEr32kClkFreq();
   -            break;
   -        case kCLOCK_Osc0ErClk:
   -            freq = CLOCK_GetOsc0ErClkFreq();
   -            break;
   -        case kCLOCK_McgFixedFreqClk:
   -            freq = CLOCK_GetFixedFreqClkFreq();
   -            break;
   -        case kCLOCK_McgInternalRefClk:
   -            freq = CLOCK_GetInternalRefClkFreq();
   -            break;
   -        case kCLOCK_McgFllClk:
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case kCLOCK_McgPll0Clk:
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case kCLOCK_McgIrc48MClk:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        case kCLOCK_LpoClk:
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (clockName) {
   +    case kCLOCK_CoreSysClk:
   +    case kCLOCK_PlatClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   +        break;
   +    case kCLOCK_BusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlexBusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlashClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   +        break;
   +    case kCLOCK_PllFllSelClk:
   +        freq = CLOCK_GetPllFllSelClkFreq();
   +        break;
   +    case kCLOCK_Er32kClk:
   +        freq = CLOCK_GetEr32kClkFreq();
   +        break;
   +    case kCLOCK_Osc0ErClk:
   +        freq = CLOCK_GetOsc0ErClkFreq();
   +        break;
   +    case kCLOCK_McgFixedFreqClk:
   +        freq = CLOCK_GetFixedFreqClkFreq();
   +        break;
   +    case kCLOCK_McgInternalRefClk:
   +        freq = CLOCK_GetInternalRefClkFreq();
   +        break;
   +    case kCLOCK_McgFllClk:
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case kCLOCK_McgPll0Clk:
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case kCLOCK_McgIrc48MClk:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    case kCLOCK_LpoClk:
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -545,7 +541,8 @@
     *
     * param config Pointer to the configure structure.
     */
   -void CLOCK_SetSimConfig(sim_clock_config_t const *config)
   +void
   +CLOCK_SetSimConfig(sim_clock_config_t const *config)
    {
        SIM->CLKDIV1 = config->clkdiv1;
        CLOCK_SetPllFllSelClock(config->pllFllSel);
   @@ -559,35 +556,32 @@
     * retval true The clock is set successfully.
     * retval false The clock source is invalid to get proper USB FS clock.
     */
   -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
   +bool
   +CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
    {
        bool ret = true;
    
        CLOCK_DisableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcExt == src)
   -    {
   +    if (kCLOCK_UsbSrcExt == src) {
            SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
   -    }
   -    else
   -    {
   -        switch (freq)
   -        {
   -            case 120000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 96000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            case 72000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 48000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            default:
   -                ret = false;
   -                break;
   +    } else   {
   +        switch (freq) {
   +        case 120000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 96000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        case 72000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 48000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        default:
   +            ret = false;
   +            break;
            }
    
            SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src);
   @@ -595,8 +589,7 @@
    
        CLOCK_EnableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcIrc48M == src)
   -    {
   +    if (kCLOCK_UsbSrcIrc48M == src) {
            USB0->CLK_RECOVER_IRC_EN = 0x03U;
            USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
        }
   @@ -611,28 +604,28 @@
     *
     * return The frequency of MCGOUTCLK.
     */
   -uint32_t CLOCK_GetOutClkFreq(void)
   +uint32_t
   +CLOCK_GetOutClkFreq(void)
    {
        uint32_t mcgoutclk;
        uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
    
   -    switch (clkst)
   -    {
   -        case (uint32_t)kMCG_ClkOutStatPll:
   -            mcgoutclk = CLOCK_GetPll0Freq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatFll:
   -            mcgoutclk = CLOCK_GetFllFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatInt:
   -            mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatExt:
   -            mcgoutclk = CLOCK_GetMcgExtClkFreq();
   -            break;
   -        default:
   -            mcgoutclk = 0U;
   -            break;
   +    switch (clkst) {
   +    case (uint32_t)kMCG_ClkOutStatPll:
   +        mcgoutclk = CLOCK_GetPll0Freq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatFll:
   +        mcgoutclk = CLOCK_GetFllFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatInt:
   +        mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatExt:
   +        mcgoutclk = CLOCK_GetMcgExtClkFreq();
   +        break;
   +    default:
   +        mcgoutclk = 0U;
   +        break;
        }
    
        return mcgoutclk;
   @@ -647,7 +640,8 @@
     *
     * return The frequency of MCGFLLCLK.
     */
   -uint32_t CLOCK_GetFllFreq(void)
   +uint32_t
   +CLOCK_GetFllFreq(void)
    {
        static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}};
    
   @@ -656,23 +650,17 @@
        uint32_t ret;
    
        /* If FLL is not enabled currently, then return 0U. */
   -    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U)))
   -    {
   +    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) {
            ret = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            /* Get FLL reference clock frequency. */
            freq = CLOCK_GetFllRefClkFreq();
   -        if (0U == freq)
   -        {
   +        if (0U == freq) {
                ret = freq;
   -        }
   -        else
   -        {
   -            drs   = MCG_C4_DRST_DRS_VAL;
   +        } else   {
   +            drs = MCG_C4_DRST_DRS_VAL;
                dmx32 = MCG_C4_DMX32_VAL;
   -            ret   = freq * fllFactorTable[drs][dmx32];
   +            ret = freq * fllFactorTable[drs][dmx32];
            }
        }
    
   @@ -687,17 +675,15 @@
     *
     * return The frequency of MCGIRCLK.
     */
   -uint32_t CLOCK_GetInternalRefClkFreq(void)
   +uint32_t
   +CLOCK_GetInternalRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If MCGIRCLK is gated. */
   -    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK))
   -    {
   +    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            freq = CLOCK_GetInternalRefClkSelectFreq();
        }
    
   @@ -712,18 +698,16 @@
     *
     * return The frequency of MCGFFCLK.
     */
   -uint32_t CLOCK_GetFixedFreqClkFreq(void)
   +uint32_t
   +CLOCK_GetFixedFreqClkFreq(void)
    {
        uint32_t freq = CLOCK_GetFllRefClkFreq();
        uint32_t ret;
    
        /* MCGFFCLK must be no more than MCGOUTCLK/8. */
   -    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq))
   -    {
   +    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq)) {
            ret = freq;
   -    }
   -    else
   -    {
   +    } else   {
            ret = 0U;
        }
    
   @@ -738,7 +722,8 @@
     *
     * return The frequency of MCGPLL0CLK.
     */
   -uint32_t CLOCK_GetPll0Freq(void)
   +uint32_t
   +CLOCK_GetPll0Freq(void)
    {
        uint32_t mcgpll0clk;
        uint32_t freq;
   @@ -746,12 +731,9 @@
        uint8_t mcgpll0prdiv;
        uint8_t mcgpll0vdiv;
        /* If PLL0 is not enabled, return 0. */
   -    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            mcgpll0clk = CLOCK_GetPll0RefFreq();
    
            /*
   @@ -783,36 +765,31 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success External reference clock set successfully.
     */
   -status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
    {
        bool needDelay;
        uint32_t i;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */
   -    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK)))
   -    {
   +    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) {
            return kStatus_MCG_SourceUsed;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
    
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel)
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel) {
            /* If change OSCSEL, need to delay, ERR009878. */
            needDelay = true;
   -    }
   -    else
   -    {
   +    } else   {
            needDelay = false;
        }
    
        MCG->C7 = (uint8_t)(MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
   -    if (needDelay)
   -    {
   +    if (needDelay) {
            /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
            i = 1500U;
   -        while (0U != (i--))
   -        {
   +        while (0U != (i--)) {
                __NOP();
            }
        }
   @@ -836,34 +813,30 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success MCGIRCLK configuration finished successfully.
     */
   -status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
   +status_t
   +CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
    {
        uint32_t mcgOutClkState = (uint32_t)MCG_S_CLKST_VAL;
   -    mcg_irc_mode_t curIrcs  = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   -    uint8_t curFcrdiv       = MCG_SC_FCRDIV_VAL;
   +    mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   +    uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If MCGIRCLK is used as system clock source. */
   -    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState)
   -    {
   +    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState) {
            /* If need to change MCGIRCLK source or driver, return error. */
   -        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs))
   -        {
   +        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) {
                return kStatus_MCG_SourceUsed;
            }
        }
    #endif
    
        /* If need to update the FCRDIV. */
   -    if (fcrdiv != curFcrdiv)
   -    {
   +    if (fcrdiv != curFcrdiv) {
            /* If fast IRC is in use currently, change to slow IRC. */
            if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) &&
   -            (kMCG_IrcFast == curIrcs))
   -        {
   +            (kMCG_IrcFast == curIrcs)) {
                MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
   -            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow)
   -            {
   +            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow) {
                }
            }
            /* Update FCRDIV. */
   @@ -876,10 +849,8 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode);
    
        /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
   -    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable)))
   -    {
   -        while (MCG_S_IRCST_VAL != (uint8_t)ircs)
   -        {
   +    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable))) {
   +        while (MCG_S_IRCST_VAL != (uint8_t)ircs) {
            }
        }
    
   @@ -901,7 +872,8 @@
     * param vdiv       VDIV value to generate desired PLL frequency.
     * return Closest frequency match that the PLL was able generate.
     */
   -uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
   +uint32_t
   +CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
    {
        uint8_t ret_prdiv;               /* PRDIV to return. */
        uint8_t ret_vdiv;                /* VDIV to return.  */
   @@ -910,7 +882,7 @@
        uint8_t prdiv_cur;               /* PRDIV value for iteration.    */
        uint8_t vdiv_cur;                /* VDIV value for iteration.     */
        uint32_t ret_freq = 0U;          /* PLL output frequency to return. */
   -    uint32_t diff     = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */
   +    uint32_t diff = 0xFFFFFFFFU;     /* Difference between desireFreq and return frequency. */
        uint32_t ref_div;                /* Reference frequency after PRDIV. */
    
        /*
   @@ -929,8 +901,7 @@
        /* Reference frequency is out of range. */
        if ((refFreq < (uint32_t)FSL_FEATURE_MCG_PLL_REF_MIN) ||
            (refFreq > ((uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX *
   -                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE))))
   -    {
   +                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) {
            return 0U;
        }
    
   @@ -940,62 +911,52 @@
            (uint8_t)((refFreq + (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX);
    
        /* PRDIV traversal. */
   -    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--)
   -    {
   +    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) {
            /* Reference frequency after PRDIV. */
            ref_div = refFreq / prdiv_cur;
    
            vdiv_cur = (uint8_t)(desireFreq / ref_div);
    
            if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) ||
   -            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                /* No VDIV is available with this PRDIV. */
                continue;
            }
    
            ret_freq = vdiv_cur * ref_div;
    
   -        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE)
   -        {
   -            if (ret_freq == desireFreq) /* If desire frequency is got. */
   -            {
   +        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) {
   +            if (ret_freq == desireFreq) { /* If desire frequency is got. */
                    *prdiv = prdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -                *vdiv  = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +                *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
                    return ret_freq;
                }
                /* New PRDIV/VDIV is closer. */
   -            if (diff > desireFreq - ret_freq)
   -            {
   -                diff      = desireFreq - ret_freq;
   +            if (diff > desireFreq - ret_freq) {
   +                diff = desireFreq - ret_freq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
            vdiv_cur++;
   -        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                ret_freq += ref_div;
                /* New PRDIV/VDIV is closer. */
   -            if (diff > ret_freq - desireFreq)
   -            {
   -                diff      = ret_freq - desireFreq;
   +            if (diff > ret_freq - desireFreq) {
   +                diff = ret_freq - desireFreq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
        }
    
   -    if (0xFFFFFFFFU != diff)
   -    {
   +    if (0xFFFFFFFFU != diff) {
            /* PRDIV/VDIV found. */
   -        *prdiv   = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -        *vdiv    = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +        *prdiv = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   +        *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
            ret_freq = (refFreq / ret_prdiv) * ret_vdiv;
            return ret_freq;
   -    }
   -    else
   -    {
   +    } else   {
            /* No proper PRDIV/VDIV found. */
            return 0U;
        }
   @@ -1012,7 +973,8 @@
     *
     * param config Pointer to the configuration structure.
     */
   -void CLOCK_EnablePll0(mcg_pll_config_t const *config)
   +void
   +CLOCK_EnablePll0(mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1027,8 +989,7 @@
        MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode);
    
        /* Wait for PLL lock. */
   -    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
        }
    }
    
   @@ -1039,23 +1000,18 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
    {
        /* Clear the previous flag, MCG_SC[LOCS0]. */
        MCG->SC &= ~(uint8_t)MCG_SC_ATMF_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= ~(uint8_t)MCG_C6_CME0_MASK;
   -    }
   -    else
   -    {
   -        if (kMCG_MonitorInt == mode)
   -        {
   +    } else   {
   +        if (kMCG_MonitorInt == mode) {
                MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK;
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C2 |= MCG_C2_LOCRE0_MASK;
            }
            MCG->C6 |= MCG_C6_CME0_MASK;
   @@ -1069,16 +1025,15 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8 = MCG->C8;
    
        mcg_c8 &= ~(uint8_t)(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK);
    
   -    if (kMCG_MonitorNone != mode)
   -    {
   -        if (kMCG_MonitorReset == mode)
   -        {
   +    if (kMCG_MonitorNone != mode) {
   +        if (kMCG_MonitorReset == mode) {
                mcg_c8 |= MCG_C8_LOCRE1_MASK;
            }
            mcg_c8 |= MCG_C8_CME1_MASK;
   @@ -1093,29 +1048,24 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8;
    
        /* Clear previous flag. */
        MCG->S = MCG_S_LOLS0_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= (uint8_t)(~MCG_C6_LOLIE0_MASK);
   -    }
   -    else
   -    {
   +    } else   {
            mcg_c8 = MCG->C8;
    
            mcg_c8 &= (uint8_t)(~MCG_C8_LOCS1_MASK);
    
   -        if (kMCG_MonitorInt == mode)
   -        {
   +        if (kMCG_MonitorInt == mode) {
                mcg_c8 &= (uint8_t)(~MCG_C8_LOLRE_MASK);
   -        }
   -        else
   -        {
   +        } else   {
                mcg_c8 |= MCG_C8_LOLRE_MASK;
            }
            MCG->C8 = mcg_c8;
   @@ -1149,29 +1099,25 @@
     *
     * return  Logical OR value of the ref _mcg_status_flags_t.
     */
   -uint32_t CLOCK_GetStatusFlags(void)
   -{
   -    uint32_t ret  = 0U;
   +uint32_t
   +CLOCK_GetStatusFlags(void)
   +{
   +    uint32_t ret = 0U;
        uint8_t mcg_s = MCG->S;
    
   -    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U)
   -    {
   +    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0LostFlag;
        }
   -    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0InitFlag;
        }
   -    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK))
   -    {
   +    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK)) {
            ret |= (uint32_t)kMCG_RtcOscLostFlag;
        }
   -    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LostFlag;
        }
   -    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LockFlag;
        }
        return ret;
   @@ -1193,21 +1139,19 @@
     * param mask The status flags to clear. This is a logical OR of members of the
     *             enumeration ref _mcg_status_flags_t.
     */
   -void CLOCK_ClearStatusFlags(uint32_t mask)
   +void
   +CLOCK_ClearStatusFlags(uint32_t mask)
    {
        uint8_t reg;
    
   -    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL) {
            MCG->SC &= (uint8_t)(~MCG_SC_ATMF_MASK);
        }
   -    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag))
   -    {
   -        reg     = MCG->C8;
   +    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag)) {
   +        reg = MCG->C8;
            MCG->C8 = reg;
        }
   -    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL) {
            MCG->S = MCG_S_LOLS0_MASK;
        }
    }
   @@ -1219,7 +1163,8 @@
     *
     * param  config Pointer to the OSC0 configuration structure.
     */
   -void CLOCK_InitOsc0(osc_config_t const *config)
   +void
   +CLOCK_InitOsc0(osc_config_t const *config)
    {
        uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq);
    
   @@ -1228,11 +1173,9 @@
        MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode);
        OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
    
   -    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U))
   -    {
   +    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)) {
            /* Wait for stable. */
   -        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -        {
   +        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
            }
        }
    }
   @@ -1242,7 +1185,8 @@
     *
     * This function deinitializes the OSC0.
     */
   -void CLOCK_DeinitOsc0(void)
   +void
   +CLOCK_DeinitOsc0(void)
    {
        OSC0->CR = 0U;
        MCG->C2 &= ~(uint8_t)OSC_MODE_MASK;
   @@ -1253,7 +1197,8 @@
     *
     * param freq The Slow IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetSlowIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetSlowIrcFreq(uint32_t freq)
    {
        s_slowIrcFreq = freq;
    }
   @@ -1263,7 +1208,8 @@
     *
     * param freq The Fast IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetFastIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetFastIrcFreq(uint32_t freq)
    {
        s_fastIrcFreq = freq;
    }
   @@ -1286,7 +1232,8 @@
     * retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
     * retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
     */
   -status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
   +status_t
   +CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
    {
        uint32_t multi; /* extFreq / desireFreq */
        uint32_t actv;  /* Auto trim value. */
   @@ -1299,30 +1246,24 @@
            {TRIM_FIRC_MIN, TRIM_FIRC_MAX}  /* Fast IRC. */
        };
    
   -    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN))
   -    {
   +    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) {
            status = kStatus_MCG_AtmBusClockInvalid;
        }
        /* Check desired frequency range. */
   -    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1]))
   -    {
   +    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) {
            status = kStatus_MCG_AtmDesiredFreqInvalid;
        }
        /*
           Make sure internal reference clock is not used to generate bus clock.
           Here only need to check (MCG_S_IREFST == 1).
         */
   -    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK))
   -    {
   +    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) {
            status = kStatus_MCG_AtmIrcUsed;
   -    }
   -    else
   -    {
   +    } else   {
            multi = extFreq / desireFreq;
   -        actv  = multi * 21U;
   -
   -        if (kMCG_AtmSel4m == atms)
   -        {
   +        actv = multi * 21U;
   +
   +        if (kMCG_AtmSel4m == atms) {
                actv *= 128U;
            }
    
   @@ -1336,27 +1277,20 @@
            MCG->SC = (mcg_sc | MCG_SC_ATME_MASK);
    
            /* Wait for MCG finished. */
   -        while (0U != (MCG->SC & MCG_SC_ATME_MASK))
   -        {
   +        while (0U != (MCG->SC & MCG_SC_ATME_MASK)) {
            }
    
            /* Error occurs? */
   -        if (0U != (MCG->SC & MCG_SC_ATMF_MASK))
   -        {
   +        if (0U != (MCG->SC & MCG_SC_ATMF_MASK)) {
                /* Clear the failed flag. */
                MCG->SC = mcg_sc;
   -            status  = kStatus_MCG_AtmHardwareFail;
   -        }
   -        else
   -        {
   +            status = kStatus_MCG_AtmHardwareFail;
   +        } else   {
                *actualFreq = extFreq / multi;
    
   -            if (kMCG_AtmSel4m == atms)
   -            {
   +            if (kMCG_AtmSel4m == atms) {
                    s_fastIrcFreq = *actualFreq;
   -            }
   -            else
   -            {
   +            } else   {
                    s_slowIrcFreq = *actualFreq;
                }
            }
   @@ -1372,103 +1306,83 @@
     *
     * return Current MCG mode or error code; See ref mcg_mode_t.
     */
   -mcg_mode_t CLOCK_GetMode(void)
   +mcg_mode_t
   +CLOCK_GetMode(void)
    {
        mcg_mode_t mode = kMCG_ModeError;
   -    uint32_t clkst  = (uint32_t)MCG_S_CLKST_VAL;
   +    uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
        uint32_t irefst = (uint32_t)MCG_S_IREFST_VAL;
   -    uint32_t lp     = (uint32_t)MCG_C2_LP_VAL;
   -    uint32_t pllst  = MCG_S_PLLST_VAL;
   +    uint32_t lp = (uint32_t)MCG_C2_LP_VAL;
   +    uint32_t pllst = MCG_S_PLLST_VAL;
    
        /*------------------------------------------------------------------
                               Mode and Registers
   -    ____________________________________________________________________
   -
   -      Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   -    ____________________________________________________________________
   -
   -      FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -      PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   -    ____________________________________________________________________
   -
   -      PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -    ----------------------------------------------------------------------*/
   -
   -    if (clkst == (uint32_t)kMCG_ClkOutStatFll)
   -    {
   -        if ((uint32_t)kMCG_FllSrcExternal == irefst)
   -        {
   +       ____________________________________________________________________
   +
   +       Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   +       ____________________________________________________________________
   +
   +       FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   +       ____________________________________________________________________
   +
   +       PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       ----------------------------------------------------------------------*/
   +
   +    if (clkst == (uint32_t)kMCG_ClkOutStatFll) {
   +        if ((uint32_t)kMCG_FllSrcExternal == irefst) {
                mode = kMCG_ModeFEE;
   -        }
   -        else
   -        {
   +        } else   {
                mode = kMCG_ModeFEI;
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatInt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatInt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPI;
   -        }
   -        else
   -        {
   +        } else   {
                {
                    mode = kMCG_ModeFBI;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatExt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatExt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPE;
   -        }
   -        else
   -        {
   -            if ((uint32_t)kMCG_PllstPll == pllst)
   -            {
   +        } else   {
   +            if ((uint32_t)kMCG_PllstPll == pllst) {
                    mode = kMCG_ModePBE;
   -            }
   -            else
   -            {
   +            } else   {
                    mode = kMCG_ModeFBE;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatPll)
   -    {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatPll)   {
            {
                mode = kMCG_ModePEE;
            }
   -    }
   -    else
   -    {
   +    } else   {
            /*do nothing*/
        }
    
   @@ -1490,15 +1404,15 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to a frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode)))
   -    {
   +    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1510,8 +1424,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1523,13 +1436,11 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1538,13 +1449,11 @@
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1566,15 +1475,15 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode)))
   -    {
   +    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1586,8 +1495,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1600,45 +1508,37 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
        /* Set DRS and DMX32. */
   -    mcg_c4  = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
   +    mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
        MCG->C4 = mcg_c4;
    
        /* Wait for DRST_DRS update. */
   -    while (MCG->C4 != mcg_c4)
   -    {
   +    while (MCG->C4 != mcg_c4) {
        }
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1661,7 +1561,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1670,9 +1571,7 @@
        mcg_mode_t mode = CLOCK_GetMode();
    
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModeBLPI == mode)))
   -
   -    {
   +          (kMCG_ModeBLPI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1687,8 +1586,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1700,26 +1598,22 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   -    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) {
        }
    
        MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1741,7 +1635,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1749,16 +1644,14 @@
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode)))
   -    {
   +          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
    
        /* Change to FLL mode. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Set LP bit to enable the FLL */
   @@ -1772,8 +1665,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1786,24 +1678,19 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for Reference clock Status bit to clear */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1812,13 +1699,11 @@
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for clock status bits to show clock source is ext ref clk */
   -    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for fll stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1834,11 +1719,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpiMode(void)
   +status_t
   +CLOCK_SetBlpiMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1858,11 +1743,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpeMode(void)
   +status_t
   +CLOCK_SetBlpeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1892,7 +1777,8 @@
     * configuration structure not necessary. In this case, pass in NULL.
     * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
     */
   -status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1907,14 +1793,12 @@
    
        /* Wait for CLKST clock status bits to show clock source is ext ref clk */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* Disable PLL first, then configure PLL. */
        MCG->C6 &= (uint8_t)(~MCG_C6_PLLS_MASK);
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Configure the PLL. */
   @@ -1926,8 +1810,7 @@
        MCG->C6 |= MCG_C6_PLLS_MASK;
    
        /* Wait for PLL mode changed. */
   -    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U) {
        }
    
        return kStatus_Success;
   @@ -1945,12 +1828,12 @@
     *       PRDIV/VDIV are different than in the PBE mode, set them up
     *       in PBE mode and wait. When the clock is stable, switch to PEE mode.
     */
   -status_t CLOCK_SetPeeMode(void)
   +status_t
   +CLOCK_SetPeeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (kMCG_ModePBE != mode)
   -    {
   +    if (kMCG_ModePBE != mode) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1959,8 +1842,7 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
    
        /* Wait for clock status bits to update */
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -1982,11 +1864,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
     */
   -status_t CLOCK_ExternalModeToFbeModeQuick(void)
   +status_t
   +CLOCK_ExternalModeToFbeModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) != 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) != 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1995,14 +1877,12 @@
        MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK);
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
        }
    
        /* Disable PLL. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        return kStatus_Success;
   @@ -2024,11 +1904,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
     */
   -status_t CLOCK_InternalModeToFbiModeQuick(void)
   +status_t
   +CLOCK_InternalModeToFbiModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) == 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) == 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif
   @@ -2037,8 +1917,7 @@
        MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        return kStatus_Success;
   @@ -2059,7 +1938,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
    }
   @@ -2079,8 +1959,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToFeeMode(
   -    mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeeMode(mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2100,15 +1980,15 @@
     * retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
   +status_t
   +CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
    {
        /* If reset mode is FEI mode, set MCGIRCLK and always success. */
        (void)CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
    
        /* If reset mode is not BLPI, first enter FBI mode. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        /* Enter BLPI mode. */
   @@ -2128,7 +2008,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2138,20 +2019,16 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* In FBE now, start to enter BLPE. */
   @@ -2173,7 +2050,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -2183,8 +2061,7 @@
    
        /* Change to use PLL output clock. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -2233,7 +2110,8 @@
     * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
     * function.
     */
   -status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
   +status_t
   +CLOCK_SetMcgConfig(const mcg_config_t *config)
    {
        mcg_mode_t next_mode;
        status_t status = kStatus_Success;
   @@ -2241,11 +2119,9 @@
        mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0;
    
        /* If need to change external clock, MCG_C7[OSCSEL]. */
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel))
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel)) {
            /* If external clock is in use, change to FEI first. */
   -        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -        {
   +        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
                (void)CLOCK_ExternalModeToFbeModeQuick();
                (void)CLOCK_SetFeiMode(config->dmx32, config->drs, NULL);
            }
   @@ -2254,8 +2130,7 @@
        }
    
        /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
   -    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt) {
            MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */
    
            {
   @@ -2268,67 +2143,56 @@
    
        next_mode = CLOCK_GetMode();
    
   -    do
   -    {
   +    do{
            next_mode = mcgModeMatrix[next_mode][config->mcgMode];
    
   -        switch (next_mode)
   -        {
   -            case kMCG_ModeFEI:
   -                status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFEE:
   -                status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFBI:
   -                status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeFBE:
   -                status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeBLPI:
   -                status = CLOCK_SetBlpiMode();
   -                break;
   -            case kMCG_ModeBLPE:
   -                status = CLOCK_SetBlpeMode();
   -                break;
   -            case kMCG_ModePBE:
   -                /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   -                if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode))
   +        switch (next_mode) {
   +        case kMCG_ModeFEI:
   +            status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFEE:
   +            status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFBI:
   +            status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeFBE:
   +            status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeBLPI:
   +            status = CLOCK_SetBlpiMode();
   +            break;
   +        case kMCG_ModeBLPE:
   +            status = CLOCK_SetBlpeMode();
   +            break;
   +        case kMCG_ModePBE:
   +            /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   +            if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) {
                    {
   -                    {
   -                        status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
   -                    }
   +                    status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
                    }
   -                else
   -                {
   -                    MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -                    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -                    {
   -                    }
   +            } else   {
   +                MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   +                while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
                    }
   -                break;
   -            case kMCG_ModePEE:
   -                status = CLOCK_SetPeeMode();
   -                break;
   -            default:
   -                assert(false);
   -                break;
   -        }
   -        if (kStatus_Success != status)
   -        {
   +            }
                break;
   +        case kMCG_ModePEE:
   +            status = CLOCK_SetPeeMode();
   +            break;
   +        default:
   +            assert(false);
   +            break;
   +        }
   +        if (kStatus_Success != status) {
   +            break;
            }
        } while (next_mode != config->mcgMode);
    
   -    if (status == kStatus_Success)
   -    {
   -        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U)
   -        {
   +    if (status == kStatus_Success) {
   +        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U) {
                CLOCK_EnablePll0(&config->pll0Config);
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/include/hal_lpuart_nxp.h
   <details>
   
   ```diff
   @@ -21,7 +21,7 @@
    #define __MCU_K8XF_HAL_UART_H_
    
    #ifdef __cplusplus
   - extern "C" {
   +extern "C" {
    #endif
    
    #define NXP_UART_EXISTS      { 1, \
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/include/mcu/kinetis_common.h
   <details>
   
   ```diff
   @@ -21,7 +21,7 @@
    #define __KINETIS_COMMON_H_
    
    #ifdef __cplusplus
   - extern "C" {
   +extern "C" {
    #endif
    
    #if MYNEWT_VAL(BSP_MK64F12)
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/include/mcu/kinetis_hal.h
   <details>
   
   ```diff
   @@ -21,7 +21,7 @@
    #define __KINETIS_HAL_H_
    
    #ifdef __cplusplus
   - extern "C" {
   +extern "C" {
    #endif
    
    struct nxp_hal_i2c_cfg {
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_flash.c
   <details>
   
   ```diff
   @@ -6,7 +6,7 @@
     * to you under the Apache License, Version 2.0 (the
     * "License"); you may not use this file except in compliance
     * with the License.  You may obtain a copy of the License at
   -*
   + *
     *  http://www.apache.org/licenses/LICENSE-2.0
     *
     * Unless required by applicable law or agreed to in writing,
   @@ -40,13 +40,13 @@
    #define KINETIS_FLASH_ALIGN MYNEWT_VAL(MCU_FLASH_MIN_WRITE_SIZE)
    
    static int kinetis_flash_read(const struct hal_flash *dev, uint32_t address,
   -        void *dst, uint32_t num_bytes);
   +                              void *dst, uint32_t num_bytes);
    static int kinetis_flash_write(const struct hal_flash *dev, uint32_t address,
   -        const void *src, uint32_t num_bytes);
   +                               const void *src, uint32_t num_bytes);
    static int kinetis_flash_erase_sector(const struct hal_flash *dev,
   -        uint32_t sector_address);
   +                                      uint32_t sector_address);
    static int kinetis_flash_sector_info(const struct hal_flash *dev, int idx,
   -        uint32_t *addr, uint32_t *sz);
   +                                     uint32_t *addr, uint32_t *sz);
    static int kinetis_flash_init(const struct hal_flash *dev);
    
    static const struct hal_flash_funcs kinetis_flash_funcs = {
   @@ -68,9 +68,9 @@
    
    static int
    kinetis_flash_read(const struct hal_flash *dev,
   -                 uint32_t address,
   -                 void *dst,
   -                 uint32_t num_bytes)
   +                   uint32_t address,
   +                   void *dst,
   +                   uint32_t num_bytes)
    {
        memcpy(dst, (void *)address, num_bytes);
        return 0;
   @@ -78,9 +78,9 @@
    
    static int
    kinetis_flash_write(const struct hal_flash *dev,
   -                  uint32_t address,
   -                  const void *src,
   -                  uint32_t len)
   +                    uint32_t address,
   +                    const void *src,
   +                    uint32_t len)
    {
        uint8_t padded[KINETIS_FLASH_ALIGN];
        uint8_t pad_len;
   @@ -142,9 +142,9 @@
    
    static int
    kinetis_flash_sector_info(const struct hal_flash *dev,
   -                        int idx,
   -                        uint32_t *addr,
   -                        uint32_t *sz)
   +                          int idx,
   +                          uint32_t *addr,
   +                          uint32_t *sz)
    {
        uint32_t sector_size;
        FLASH_GetProperty(&kinetis_config,
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_gpio.c
   <details>
   
   ```diff
   @@ -53,8 +53,7 @@
    uint16_t
    hal_to_fsl_pull(hal_gpio_pull_t pull)
    {
   -    switch ((int)pull)
   -    {
   +    switch ((int)pull) {
        case HAL_GPIO_PULL_UP:
            return kPORT_PullUp;
        case HAL_GPIO_PULL_DOWN:
   @@ -304,9 +303,9 @@
    #endif
            memset(&hal_gpio_irqs[entry], 0, sizeof(struct hal_gpio_irq));
            if (hal_gpio_find_port(GPIO_PORT(pin)) < 0) {
   -                NVIC_ClearPendingIRQ(GPIO_PORT(pin));
   -                NVIC_DisableIRQ(GPIO_PORT(pin));
   -            }
   +            NVIC_ClearPendingIRQ(GPIO_PORT(pin));
   +            NVIC_DisableIRQ(GPIO_PORT(pin));
   +        }
        }
    }
    
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_i2c.c
   <details>
   
   ```diff
   @@ -33,10 +33,10 @@
    #define NXP_HAL_I2C_MAX 4
    
    struct nxp_hal_i2c {
   -    I2C_Type* dev;
   +    I2C_Type * dev;
        uint32_t scl_pin;
        uint32_t sda_pin;
   -    PORT_Type *port; 
   +    PORT_Type *port;
        port_mux_t mux;
        IRQn_Type irqn;
        void (*irq_handler)(void);
   @@ -170,7 +170,7 @@
        os_sem_release(&i2c->sync);
    }
    
   -static struct nxp_hal_i2c*
   +static struct nxp_hal_i2c *
    hal_i2c_resolve(uint8_t i2c_num)
    {
        if (i2c_num >= NXP_HAL_I2C_MAX) {
   @@ -289,7 +289,7 @@
    
        i2c = hal_i2c_resolve(i2c_num);
        if (!i2c) {
   -       return HAL_I2C_ERR_INVAL;
   +        return HAL_I2C_ERR_INVAL;
        }
    
        return i2c_config(i2c, cfg->frequency);
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_lpuart.c
   <details>
   
   ```diff
   @@ -50,22 +50,22 @@
    };
    
    struct hal_uart {
   -    LPUART_Type      *u_base;
   -    clock_name_t     clk_src;
   -    uint32_t         u_irq;
   -    PORT_Type       *p_base;
   -    clock_ip_name_t  p_clock;
   -    int  u_pin_rx;
   -    int  u_pin_tx;
   +    LPUART_Type *u_base;
   +    clock_name_t clk_src;
   +    uint32_t u_irq;
   +    PORT_Type *p_base;
   +    clock_ip_name_t p_clock;
   +    int u_pin_rx;
   +    int u_pin_tx;
        /* TODO: support flow control pins */
        hal_uart_rx_char u_rx_func;
        hal_uart_tx_char u_tx_func;
        hal_uart_tx_done u_tx_done;
        void *u_func_arg;
   -    uint8_t u_configured:1;
   -    uint8_t u_open:1;
   -    uint8_t u_tx_started:1;
   -    uint8_t u_rx_stall:1;
   +    uint8_t u_configured : 1;
   +    uint8_t u_open : 1;
   +    uint8_t u_tx_started : 1;
   +    uint8_t u_rx_stall : 1;
        struct uart_ring ur_tx;
        uint8_t tx_buffer[TX_BUF_SZ];
        struct uart_ring ur_rx;
   @@ -98,17 +98,20 @@
     * RING BUFFER FUNCTIONS
     */
    
   -static uint8_t ur_is_empty(struct uart_ring *ur)
   +static uint8_t
   +ur_is_empty(struct uart_ring *ur)
    {
        return (ur->ur_head == ur->ur_tail);
    }
    
   -static uint8_t ur_is_full(struct uart_ring *ur)
   +static uint8_t
   +ur_is_full(struct uart_ring *ur)
    {
        return (((ur->ur_tail + 1) % ur->ur_size) == ur->ur_head);
    }
    
   -static void ur_bump(struct uart_ring *ur)
   +static void
   +ur_bump(struct uart_ring *ur)
    {
        if (!ur_is_empty(ur)) {
            ur->ur_head++;
   @@ -117,12 +120,14 @@
        }
    }
    
   -static uint8_t ur_read(struct uart_ring *ur)
   +static uint8_t
   +ur_read(struct uart_ring *ur)
    {
        return ur->ur_buf[ur->ur_head];
    }
    
   -static int ur_queue(struct uart_ring *ur, uint8_t data)
   +static int
   +ur_queue(struct uart_ring *ur, uint8_t data)
    {
        if (!ur_is_full(ur)) {
            ur->ur_buf[ur->ur_tail] = data;
   @@ -137,11 +142,12 @@
     * END RING BUFFER FUNCTIONS
     */
    
   -int hal_uart_init_cbs(int port,
   -                      hal_uart_tx_char tx_func,
   -                      hal_uart_tx_done tx_done,
   -                      hal_uart_rx_char rx_func,
   -                      void *arg)
   +int
   +hal_uart_init_cbs(int port,
   +                  hal_uart_tx_char tx_func,
   +                  hal_uart_tx_done tx_done,
   +                  hal_uart_rx_char rx_func,
   +                  void *arg)
    {
        struct hal_uart *u;
    
   @@ -157,7 +163,8 @@
        return 0;
    }
    
   -void hal_uart_blocking_tx(int port, uint8_t byte)
   +void
   +hal_uart_blocking_tx(int port, uint8_t byte)
    {
        struct hal_uart *u;
    
   @@ -194,7 +201,8 @@
        return i;
    }
    
   -void hal_uart_start_tx(int port)
   +void
   +hal_uart_start_tx(int port)
    {
        struct hal_uart *u;
        int data = -1;
   @@ -209,8 +217,7 @@
        }
    
        /* main loop */
   -    while (true)
   -    {
   +    while (true) {
            /* add data to TX ring buffer */
            if (u->u_tx_started == 0) {
                rc = hal_uart_tx_fill_buf(u);
   @@ -293,8 +300,9 @@
            if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base)) {
                if (u->u_tx_started) {
                    u->u_tx_started = 0;
   -                if (u->u_tx_done)
   +                if (u->u_tx_done) {
                        u->u_tx_done(u->u_func_arg);
   +                }
                }
            }
        }
   @@ -434,24 +442,23 @@
    {
        if (s_uartExists[port]) {
            if (s_uartEnabled[port]) {
   -            uarts[port].u_base        = s_uartBases[port];
   -            uarts[port].clk_src       = s_uartClocks[port];
   -            uarts[port].u_irq         = s_uartIRQ[port];
   -            uarts[port].p_base        = s_uartPort[port];
   -            uarts[port].p_clock       = s_uartPortClocks[port];
   -            uarts[port].u_pin_rx      = s_uartPIN_RX[port];
   -            uarts[port].u_pin_tx      = s_uartPIN_TX[port];
   -            uarts[port].ur_tx.ur_buf  = uarts[port].tx_buffer;
   +            uarts[port].u_base = s_uartBases[port];
   +            uarts[port].clk_src = s_uartClocks[port];
   +            uarts[port].u_irq = s_uartIRQ[port];
   +            uarts[port].p_base = s_uartPort[port];
   +            uarts[port].p_clock = s_uartPortClocks[port];
   +            uarts[port].u_pin_rx = s_uartPIN_RX[port];
   +            uarts[port].u_pin_tx = s_uartPIN_TX[port];
   +            uarts[port].ur_tx.ur_buf = uarts[port].tx_buffer;
                uarts[port].ur_tx.ur_size = TX_BUF_SZ;
                uarts[port].ur_tx.ur_head = 0;
                uarts[port].ur_tx.ur_tail = 0;
   -            uarts[port].ur_rx.ur_buf  = uarts[port].rx_buffer;
   +            uarts[port].ur_rx.ur_buf = uarts[port].rx_buffer;
                uarts[port].ur_rx.ur_size = RX_BUF_SZ;
                uarts[port].ur_rx.ur_head = 0;
                uarts[port].ur_rx.ur_tail = 0;
   -            uarts[port].u_configured  = 1;
   -        }
   -        else {
   +            uarts[port].u_configured = 1;
   +        } else   {
                uarts[port].u_configured = 0;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_qspi.c
   <details>
   
   ```diff
   @@ -107,7 +107,8 @@
        [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
    
        /* Match MISRA rule */
   -    [63] = 0};
   +    [63] = 0
   +};
    
    qspi_flash_config_t g_qspi_flash_cfg = {
        .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
   @@ -132,15 +133,12 @@
    {
        uint32_t val = 0;
        /* Check WIP bit */
   -    do
   -    {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +    do{
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
            QSPI_ExecuteIPCommand(QuadSPI0, 12U);
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            val = QuadSPI0->RBDR[0];
            /* Clear ARDB area */
   @@ -151,19 +149,17 @@
    static void
    cmd_write_enable()
    {
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ExecuteIPCommand(QuadSPI0, 4U);
    }
    
    static void
   -read_page(uint32_t address, uint32_t* dst)
   +read_page(uint32_t address, uint32_t * dst)
    {
        int i;
   -    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
   -    {
   -        dst[i] = ((uint32_t*)address)[i];
   +    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++) {
   +        dst[i] = ((uint32_t *)address)[i];
        }
    }
    
   @@ -195,15 +191,13 @@
    {
        uint32_t leftLongWords = 0;
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
    
        QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
        cmd_write_enable();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
    
        /* First write some data into TXFIFO to prevent from underrun */
   @@ -219,8 +213,7 @@
    
        /* Wait until flash finished program */
        check_if_finished();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess)) {
        }
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   @@ -244,7 +237,7 @@
    
        npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        while (npages) {
   -        write_page(address, (uint32_t*) src);
   +        write_page(address, (uint32_t *) src);
            npages--;
            address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        }
   @@ -253,13 +246,12 @@
    
    static int
    nxp_qspi_erase_sector(const struct hal_flash *dev,
   -                         uint32_t sector_address)
   +                      uint32_t sector_address)
    {
        sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
        sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
        QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
   @@ -286,8 +278,7 @@
        nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
        while (nsects) {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
            QSPI_SetIPCommandAddress(QuadSPI0, address);
   @@ -296,7 +287,7 @@
            check_if_finished();
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
   -    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   +        (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
            QSPI_ClearCache(QuadSPI0);
    #endif
            nsects--;
   @@ -323,8 +314,7 @@
    {
        uint32_t val[4] = {0x40U, 0, 0, 0};
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
    
   @@ -373,7 +363,7 @@
        PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB2), MYNEWT_VAL(QSPIB_MUX));
        PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOBA), MYNEWT_VAL(QSPIB_MUX));
    
   -    //Configure the baudrate too.
   +    /*Configure the baudrate too. */
    
        QSPI_Init(QuadSPI0, &qspi_cfg, CLOCK_GetFreq(kCLOCK_McgPll0Clk));
    
   @@ -390,21 +380,21 @@
    }
    
    static const struct hal_flash_funcs nxp_qspi_funcs = {
   -        .hff_read = nxp_qspi_read,
   -        .hff_write = nxp_qspi_write,
   -        .hff_erase_sector = nxp_qspi_erase_sector,
   -        .hff_sector_info = nxp_qspi_sector_info,
   -        .hff_init = nxp_qspi_init,
   -        .hff_erase = nxp_qspi_erase
   -    };
   +    .hff_read = nxp_qspi_read,
   +    .hff_write = nxp_qspi_write,
   +    .hff_erase_sector = nxp_qspi_erase_sector,
   +    .hff_sector_info = nxp_qspi_sector_info,
   +    .hff_init = nxp_qspi_init,
   +    .hff_erase = nxp_qspi_erase
   +};
    
    const struct hal_flash nxp_qspi_dev = {
   -        .hf_itf = &nxp_qspi_funcs,
   -        .hf_base_addr = FSL_FEATURE_QSPI_AMBA_BASE,
   -        .hf_size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE),
   -        .hf_sector_cnt = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT),
   -        .hf_align = 8,
   -        .hf_erased_val = 0xff,
   -    };
   -
   -#endif
   +    .hf_itf = &nxp_qspi_funcs,
   +    .hf_base_addr = FSL_FEATURE_QSPI_AMBA_BASE,
   +    .hf_size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE),
   +    .hf_sector_cnt = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT),
   +    .hf_align = 8,
   +    .hf_erased_val = 0xff,
   +};
   +
   +#endif
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_spi.c
   <details>
   
   ```diff
   @@ -38,7 +38,7 @@
    };
    
    struct nxp_hal_spi {
   -    SPI_Type* dev;
   +    SPI_Type * dev;
        uint32_t clk_pin;
        uint32_t pcs_pin;
        uint32_t sout_pin;
   @@ -48,7 +48,7 @@
        IRQn_Type irqn;
        void (*irq_handler)(void);
        hal_spi_txrx_cb txrx_cb;
   -    void* txrx_cb_arg;
   +    void * txrx_cb_arg;
        bool enabled;
        enum spi_type_t type;
    };
   @@ -265,7 +265,7 @@
    static void
    hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
    {
   -    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
   +    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
    
        if (status == kStatus_Success) {
            if (spi->txrx_cb) {
   @@ -277,7 +277,7 @@
    static void
    hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
    {
   -    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
   +    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
    
        if (status == kStatus_Success) {
            if (spi->txrx_cb) {
   @@ -293,7 +293,7 @@
        struct nxp_spi_master *master;
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   +        master = (struct nxp_spi_master *) spi;
            PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
   @@ -311,7 +311,7 @@
        struct nxp_spi_slave *slave;
    
        if (spi->type == HAL_SPI_TYPE_SLAVE) {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
   @@ -406,7 +406,7 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   +        master = (struct nxp_spi_master *) spi;
    
            master->config.ctarConfig.baudRate = settings->baudrate;
            master->config.ctarConfig.pcsToSckDelayInNanoSec =
   @@ -424,7 +424,7 @@
            master->config.ctarConfig.cpol = cpol;
            master->config.ctarConfig.cpha = cpha;
        } else {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            slave->config.ctarConfig.bitsPerFrame =
                (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
            slave->config.ctarConfig.cpol = cpol;
   @@ -448,13 +448,13 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -    master = (struct nxp_spi_master*) spi;
   -    DSPI_MasterInit(spi->dev,
   +        master = (struct nxp_spi_master *) spi;
   +        DSPI_MasterInit(spi->dev,
                        &master->config,
                        CLOCK_GetFreq(kCLOCK_BusClk));
        } else {
   -    slave = (struct nxp_spi_slave*) spi;
   -    DSPI_SlaveInit(spi->dev, &slave->config);
   +        slave = (struct nxp_spi_slave *) spi;
   +        DSPI_SlaveInit(spi->dev, &slave->config);
        }
    
        spi->enabled = true;
   @@ -496,8 +496,8 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        xfer.txData = (uint8_t*) &val;
   -        xfer.rxData = (uint8_t*) &retval;
   +        xfer.txData = (uint8_t *) &val;
   +        xfer.rxData = (uint8_t *) &retval;
            xfer.dataSize = 1;
            xfer.configFlags = kDSPI_MasterCtar0;
            DSPI_MasterTransferBlocking(spi->dev, &xfer);
   @@ -518,8 +518,8 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        xfer.txData = (uint8_t*) txbuf;
   -        xfer.rxData = (uint8_t*) rxbuf;
   +        xfer.txData = (uint8_t *) txbuf;
   +        xfer.rxData = (uint8_t *) rxbuf;
            xfer.dataSize = len;
            xfer.configFlags = kDSPI_MasterCtar0;
            rc = DSPI_MasterTransferBlocking(spi->dev, &xfer);
   @@ -556,26 +556,26 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   -        //master->handle
   +        master = (struct nxp_spi_master *) spi;
   +        /*master->handle */
            DSPI_MasterTransferCreateHandle(spi->dev,
                                            &master->handle,
                                            hal_spi_master_xfer_cb,
                                            spi);
            xfer.configFlags = kDSPI_MasterCtar0;
   -        xfer.txData = (uint8_t*) txbuf;
   -        xfer.rxData = (uint8_t*) rxbuf;
   +        xfer.txData = (uint8_t *) txbuf;
   +        xfer.rxData = (uint8_t *) rxbuf;
            xfer.dataSize = len;
            rc = DSPI_MasterTransferNonBlocking(spi->dev, &master->handle, &xfer);
        } else {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            DSPI_SlaveTransferCreateHandle(spi->dev,
                                           &slave->handle,
                                           hal_spi_slave_xfer_cb,
                                           spi);
            xfer.configFlags = kDSPI_SlaveCtar0;
   -        xfer.txData = (uint8_t*) txbuf;
   -        xfer.rxData = (uint8_t*) rxbuf;
   +        xfer.txData = (uint8_t *) txbuf;
   +        xfer.rxData = (uint8_t *) rxbuf;
            xfer.dataSize = len;
            rc = DSPI_SlaveTransferNonBlocking(spi->dev, &slave->handle, &xfer);
    
   @@ -614,10 +614,10 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   +        master = (struct nxp_spi_master *) spi;
            DSPI_MasterTransferAbort(spi->dev, &master->handle);
        } else {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            DSPI_SlaveTransferAbort(spi->dev, &slave->handle);
        }
        return 0;
   ```
   
   </details>
   
   #### hw/bsp/frdm-k64f/src/hal_bsp.c
   <details>
   
   ```diff
   @@ -98,7 +98,8 @@
        }
    };
    
   -static void init_hardware(void)
   +static void
   +init_hardware(void)
    {
        /* Disable the MPU otherwise USB cannot access the bus */
        SYSMPU->CESR = 0;
   ```
   
   </details>


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   <!-- style-bot -->
   
   ## Style check summary
   
   ### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
   
   
   #### hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c
   <details>
   
   ```diff
   @@ -187,15 +187,15 @@
     ******************************************************************************/
    
    #ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
   -static void CLOCK_FllStableDelay(void)
   +static void
   +CLOCK_FllStableDelay(void)
    {
        /*
           Should wait at least 1ms. Because in these modes, the core clock is 100MHz
           at most, so this function could obtain the 1ms delay.
         */
        volatile uint32_t i = 30000U;
   -    while (0U != (i--))
   -    {
   +    while (0U != (i--)) {
            __NOP();
        }
    }
   @@ -207,34 +207,35 @@
    extern void CLOCK_FllStableDelay(void);
    #endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */
    
   -static uint32_t CLOCK_GetMcgExtClkFreq(void)
   +static uint32_t
   +CLOCK_GetMcgExtClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (MCG_C7_OSCSEL_VAL)
   -    {
   -        case 0U:
   -            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   -            assert(0U != g_xtal0Freq);
   -            freq = g_xtal0Freq;
   -            break;
   -        case 1U:
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(0U != g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 2U:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (MCG_C7_OSCSEL_VAL) {
   +    case 0U:
   +        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   +        assert(0U != g_xtal0Freq);
   +        freq = g_xtal0Freq;
   +        break;
   +    case 1U:
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(0U != g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 2U:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllExtRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllExtRefClkFreq(void)
    {
        /* FllExtRef = McgExtRef / FllExtRefDiv */
        uint8_t frdiv;
   @@ -246,54 +247,50 @@
        frdiv = MCG_C1_FRDIV_VAL;
        freq >>= frdiv;
    
   -    range  = MCG_C2_RANGE_VAL;
   +    range = MCG_C2_RANGE_VAL;
        oscsel = MCG_C7_OSCSEL_VAL;
    
        /*
           When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536.
           1. MCG_C7[OSCSEL] selects IRC48M.
           2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0.
   -    */
   -    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel))
   -    {
   -        switch (frdiv)
   -        {
   -            case 0:
   -            case 1:
   -            case 2:
   -            case 3:
   -            case 4:
   -            case 5:
   -                freq >>= 5u;
   -                break;
   -            case 6:
   -                /* 64*20=1280 */
   -                freq /= 20u;
   -                break;
   -            case 7:
   -                /* 128*12=1536 */
   -                freq /= 12u;
   -                break;
   -            default:
   -                freq = 0u;
   -                break;
   +     */
   +    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel)) {
   +        switch (frdiv) {
   +        case 0:
   +        case 1:
   +        case 2:
   +        case 3:
   +        case 4:
   +        case 5:
   +            freq >>= 5u;
   +            break;
   +        case 6:
   +            /* 64*20=1280 */
   +            freq /= 20u;
   +            break;
   +        case 7:
   +            /* 128*12=1536 */
   +            freq /= 12u;
   +            break;
   +        default:
   +            freq = 0u;
   +            break;
            }
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetInternalRefClkSelectFreq(void)
   +static uint32_t
   +CLOCK_GetInternalRefClkSelectFreq(void)
    {
        uint32_t freq;
    
   -    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL)
   -    {
   +    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL) {
            /* Slow internal reference clock selected*/
            freq = s_slowIrcFreq;
   -    }
   -    else
   -    {
   +    } else   {
            /* Fast internal reference clock selected*/
            freq = s_fastIrcFreq >> MCG_SC_FCRDIV_VAL;
        }
   @@ -301,44 +298,40 @@
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If use external reference clock. */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            freq = CLOCK_GetFllExtRefClkFreq();
        }
        /* If use internal reference clock. */
   -    else
   -    {
   +    else {
            freq = s_slowIrcFreq;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetPll0RefFreq(void)
   +static uint32_t
   +CLOCK_GetPll0RefFreq(void)
    {
        /* MCG external reference clock. */
        return CLOCK_GetMcgExtClkFreq();
    }
    
   -static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
   +static uint8_t
   +CLOCK_GetOscRangeFromFreq(uint32_t freq)
    {
        uint8_t range;
    
   -    if (freq <= 39063U)
   -    {
   +    if (freq <= 39063U) {
            range = 0U;
   -    }
   -    else if (freq <= 8000000U)
   -    {
   +    } else if (freq <= 8000000U)   {
            range = 1U;
   -    }
   -    else
   -    {
   +    } else   {
            range = 2U;
        }
    
   @@ -350,17 +343,15 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetOsc0ErClkFreq(void)
   +uint32_t
   +CLOCK_GetOsc0ErClkFreq(void)
    {
        uint32_t freq;
   -    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)
   -    {
   +    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U) {
            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
            assert(g_xtal0Freq);
            freq = g_xtal0Freq;
   -    }
   -    else
   -    {
   +    } else   {
            freq = 0U;
        }
    
   @@ -372,26 +363,26 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetEr32kClkFreq(void)
   +uint32_t
   +CLOCK_GetEr32kClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT1_OSC32KSEL_VAL)
   -    {
   -        case 0U: /* OSC 32k clock  */
   -            freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   -            break;
   -        case 2U: /* RTC 32k clock  */
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 3U: /* LPO clock      */
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT1_OSC32KSEL_VAL) {
   +    case 0U:     /* OSC 32k clock  */
   +        freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   +        break;
   +    case 2U:     /* RTC 32k clock  */
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 3U:     /* LPO clock      */
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
        return freq;
    }
   @@ -401,24 +392,24 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPllFllSelClkFreq(void)
   +uint32_t
   +CLOCK_GetPllFllSelClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT2_PLLFLLSEL_VAL)
   -    {
   -        case 0U: /* FLL. */
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case 1U: /* PLL. */
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case 3U: /* MCG IRC48M. */
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT2_PLLFLLSEL_VAL) {
   +    case 0U:     /* FLL. */
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case 1U:     /* PLL. */
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case 3U:     /* MCG IRC48M. */
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -429,7 +420,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPlatClkFreq(void)
   +uint32_t
   +CLOCK_GetPlatClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -439,7 +431,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlashClkFreq(void)
   +uint32_t
   +CLOCK_GetFlashClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
    }
   @@ -449,7 +442,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlexBusClkFreq(void)
   +uint32_t
   +CLOCK_GetFlexBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
    }
   @@ -459,7 +453,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetBusClkFreq(void)
   +uint32_t
   +CLOCK_GetBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
    }
   @@ -469,7 +464,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetCoreSysClkFreq(void)
   +uint32_t
   +CLOCK_GetCoreSysClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -484,55 +480,55 @@
     * param clockName Clock names defined in clock_name_t
     * return Clock frequency value in Hertz
     */
   -uint32_t CLOCK_GetFreq(clock_name_t clockName)
   +uint32_t
   +CLOCK_GetFreq(clock_name_t clockName)
    {
        uint32_t freq;
    
   -    switch (clockName)
   -    {
   -        case kCLOCK_CoreSysClk:
   -        case kCLOCK_PlatClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   -            break;
   -        case kCLOCK_BusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlexBusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlashClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   -            break;
   -        case kCLOCK_PllFllSelClk:
   -            freq = CLOCK_GetPllFllSelClkFreq();
   -            break;
   -        case kCLOCK_Er32kClk:
   -            freq = CLOCK_GetEr32kClkFreq();
   -            break;
   -        case kCLOCK_Osc0ErClk:
   -            freq = CLOCK_GetOsc0ErClkFreq();
   -            break;
   -        case kCLOCK_McgFixedFreqClk:
   -            freq = CLOCK_GetFixedFreqClkFreq();
   -            break;
   -        case kCLOCK_McgInternalRefClk:
   -            freq = CLOCK_GetInternalRefClkFreq();
   -            break;
   -        case kCLOCK_McgFllClk:
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case kCLOCK_McgPll0Clk:
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case kCLOCK_McgIrc48MClk:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        case kCLOCK_LpoClk:
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (clockName) {
   +    case kCLOCK_CoreSysClk:
   +    case kCLOCK_PlatClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   +        break;
   +    case kCLOCK_BusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlexBusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlashClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   +        break;
   +    case kCLOCK_PllFllSelClk:
   +        freq = CLOCK_GetPllFllSelClkFreq();
   +        break;
   +    case kCLOCK_Er32kClk:
   +        freq = CLOCK_GetEr32kClkFreq();
   +        break;
   +    case kCLOCK_Osc0ErClk:
   +        freq = CLOCK_GetOsc0ErClkFreq();
   +        break;
   +    case kCLOCK_McgFixedFreqClk:
   +        freq = CLOCK_GetFixedFreqClkFreq();
   +        break;
   +    case kCLOCK_McgInternalRefClk:
   +        freq = CLOCK_GetInternalRefClkFreq();
   +        break;
   +    case kCLOCK_McgFllClk:
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case kCLOCK_McgPll0Clk:
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case kCLOCK_McgIrc48MClk:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    case kCLOCK_LpoClk:
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -545,7 +541,8 @@
     *
     * param config Pointer to the configure structure.
     */
   -void CLOCK_SetSimConfig(sim_clock_config_t const *config)
   +void
   +CLOCK_SetSimConfig(sim_clock_config_t const *config)
    {
        SIM->CLKDIV1 = config->clkdiv1;
        CLOCK_SetPllFllSelClock(config->pllFllSel);
   @@ -559,35 +556,32 @@
     * retval true The clock is set successfully.
     * retval false The clock source is invalid to get proper USB FS clock.
     */
   -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
   +bool
   +CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
    {
        bool ret = true;
    
        CLOCK_DisableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcExt == src)
   -    {
   +    if (kCLOCK_UsbSrcExt == src) {
            SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
   -    }
   -    else
   -    {
   -        switch (freq)
   -        {
   -            case 120000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 96000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            case 72000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 48000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            default:
   -                ret = false;
   -                break;
   +    } else   {
   +        switch (freq) {
   +        case 120000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 96000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        case 72000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 48000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        default:
   +            ret = false;
   +            break;
            }
    
            SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src);
   @@ -595,8 +589,7 @@
    
        CLOCK_EnableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcIrc48M == src)
   -    {
   +    if (kCLOCK_UsbSrcIrc48M == src) {
            USB0->CLK_RECOVER_IRC_EN = 0x03U;
            USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
        }
   @@ -611,28 +604,28 @@
     *
     * return The frequency of MCGOUTCLK.
     */
   -uint32_t CLOCK_GetOutClkFreq(void)
   +uint32_t
   +CLOCK_GetOutClkFreq(void)
    {
        uint32_t mcgoutclk;
        uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
    
   -    switch (clkst)
   -    {
   -        case (uint32_t)kMCG_ClkOutStatPll:
   -            mcgoutclk = CLOCK_GetPll0Freq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatFll:
   -            mcgoutclk = CLOCK_GetFllFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatInt:
   -            mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatExt:
   -            mcgoutclk = CLOCK_GetMcgExtClkFreq();
   -            break;
   -        default:
   -            mcgoutclk = 0U;
   -            break;
   +    switch (clkst) {
   +    case (uint32_t)kMCG_ClkOutStatPll:
   +        mcgoutclk = CLOCK_GetPll0Freq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatFll:
   +        mcgoutclk = CLOCK_GetFllFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatInt:
   +        mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatExt:
   +        mcgoutclk = CLOCK_GetMcgExtClkFreq();
   +        break;
   +    default:
   +        mcgoutclk = 0U;
   +        break;
        }
    
        return mcgoutclk;
   @@ -647,7 +640,8 @@
     *
     * return The frequency of MCGFLLCLK.
     */
   -uint32_t CLOCK_GetFllFreq(void)
   +uint32_t
   +CLOCK_GetFllFreq(void)
    {
        static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}};
    
   @@ -656,23 +650,17 @@
        uint32_t ret;
    
        /* If FLL is not enabled currently, then return 0U. */
   -    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U)))
   -    {
   +    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) {
            ret = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            /* Get FLL reference clock frequency. */
            freq = CLOCK_GetFllRefClkFreq();
   -        if (0U == freq)
   -        {
   +        if (0U == freq) {
                ret = freq;
   -        }
   -        else
   -        {
   -            drs   = MCG_C4_DRST_DRS_VAL;
   +        } else   {
   +            drs = MCG_C4_DRST_DRS_VAL;
                dmx32 = MCG_C4_DMX32_VAL;
   -            ret   = freq * fllFactorTable[drs][dmx32];
   +            ret = freq * fllFactorTable[drs][dmx32];
            }
        }
    
   @@ -687,17 +675,15 @@
     *
     * return The frequency of MCGIRCLK.
     */
   -uint32_t CLOCK_GetInternalRefClkFreq(void)
   +uint32_t
   +CLOCK_GetInternalRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If MCGIRCLK is gated. */
   -    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK))
   -    {
   +    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            freq = CLOCK_GetInternalRefClkSelectFreq();
        }
    
   @@ -712,18 +698,16 @@
     *
     * return The frequency of MCGFFCLK.
     */
   -uint32_t CLOCK_GetFixedFreqClkFreq(void)
   +uint32_t
   +CLOCK_GetFixedFreqClkFreq(void)
    {
        uint32_t freq = CLOCK_GetFllRefClkFreq();
        uint32_t ret;
    
        /* MCGFFCLK must be no more than MCGOUTCLK/8. */
   -    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq))
   -    {
   +    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq)) {
            ret = freq;
   -    }
   -    else
   -    {
   +    } else   {
            ret = 0U;
        }
    
   @@ -738,7 +722,8 @@
     *
     * return The frequency of MCGPLL0CLK.
     */
   -uint32_t CLOCK_GetPll0Freq(void)
   +uint32_t
   +CLOCK_GetPll0Freq(void)
    {
        uint32_t mcgpll0clk;
        uint32_t freq;
   @@ -746,12 +731,9 @@
        uint8_t mcgpll0prdiv;
        uint8_t mcgpll0vdiv;
        /* If PLL0 is not enabled, return 0. */
   -    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            mcgpll0clk = CLOCK_GetPll0RefFreq();
    
            /*
   @@ -783,36 +765,31 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success External reference clock set successfully.
     */
   -status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
    {
        bool needDelay;
        uint32_t i;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */
   -    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK)))
   -    {
   +    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) {
            return kStatus_MCG_SourceUsed;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
    
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel)
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel) {
            /* If change OSCSEL, need to delay, ERR009878. */
            needDelay = true;
   -    }
   -    else
   -    {
   +    } else   {
            needDelay = false;
        }
    
        MCG->C7 = (uint8_t)(MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
   -    if (needDelay)
   -    {
   +    if (needDelay) {
            /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
            i = 1500U;
   -        while (0U != (i--))
   -        {
   +        while (0U != (i--)) {
                __NOP();
            }
        }
   @@ -836,34 +813,30 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success MCGIRCLK configuration finished successfully.
     */
   -status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
   +status_t
   +CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
    {
        uint32_t mcgOutClkState = (uint32_t)MCG_S_CLKST_VAL;
   -    mcg_irc_mode_t curIrcs  = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   -    uint8_t curFcrdiv       = MCG_SC_FCRDIV_VAL;
   +    mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   +    uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If MCGIRCLK is used as system clock source. */
   -    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState)
   -    {
   +    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState) {
            /* If need to change MCGIRCLK source or driver, return error. */
   -        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs))
   -        {
   +        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) {
                return kStatus_MCG_SourceUsed;
            }
        }
    #endif
    
        /* If need to update the FCRDIV. */
   -    if (fcrdiv != curFcrdiv)
   -    {
   +    if (fcrdiv != curFcrdiv) {
            /* If fast IRC is in use currently, change to slow IRC. */
            if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) &&
   -            (kMCG_IrcFast == curIrcs))
   -        {
   +            (kMCG_IrcFast == curIrcs)) {
                MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
   -            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow)
   -            {
   +            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow) {
                }
            }
            /* Update FCRDIV. */
   @@ -876,10 +849,8 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode);
    
        /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
   -    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable)))
   -    {
   -        while (MCG_S_IRCST_VAL != (uint8_t)ircs)
   -        {
   +    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable))) {
   +        while (MCG_S_IRCST_VAL != (uint8_t)ircs) {
            }
        }
    
   @@ -901,7 +872,8 @@
     * param vdiv       VDIV value to generate desired PLL frequency.
     * return Closest frequency match that the PLL was able generate.
     */
   -uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
   +uint32_t
   +CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
    {
        uint8_t ret_prdiv;               /* PRDIV to return. */
        uint8_t ret_vdiv;                /* VDIV to return.  */
   @@ -910,7 +882,7 @@
        uint8_t prdiv_cur;               /* PRDIV value for iteration.    */
        uint8_t vdiv_cur;                /* VDIV value for iteration.     */
        uint32_t ret_freq = 0U;          /* PLL output frequency to return. */
   -    uint32_t diff     = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */
   +    uint32_t diff = 0xFFFFFFFFU;     /* Difference between desireFreq and return frequency. */
        uint32_t ref_div;                /* Reference frequency after PRDIV. */
    
        /*
   @@ -929,8 +901,7 @@
        /* Reference frequency is out of range. */
        if ((refFreq < (uint32_t)FSL_FEATURE_MCG_PLL_REF_MIN) ||
            (refFreq > ((uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX *
   -                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE))))
   -    {
   +                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) {
            return 0U;
        }
    
   @@ -940,62 +911,52 @@
            (uint8_t)((refFreq + (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX);
    
        /* PRDIV traversal. */
   -    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--)
   -    {
   +    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) {
            /* Reference frequency after PRDIV. */
            ref_div = refFreq / prdiv_cur;
    
            vdiv_cur = (uint8_t)(desireFreq / ref_div);
    
            if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) ||
   -            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                /* No VDIV is available with this PRDIV. */
                continue;
            }
    
            ret_freq = vdiv_cur * ref_div;
    
   -        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE)
   -        {
   -            if (ret_freq == desireFreq) /* If desire frequency is got. */
   -            {
   +        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) {
   +            if (ret_freq == desireFreq) { /* If desire frequency is got. */
                    *prdiv = prdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -                *vdiv  = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +                *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
                    return ret_freq;
                }
                /* New PRDIV/VDIV is closer. */
   -            if (diff > desireFreq - ret_freq)
   -            {
   -                diff      = desireFreq - ret_freq;
   +            if (diff > desireFreq - ret_freq) {
   +                diff = desireFreq - ret_freq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
            vdiv_cur++;
   -        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                ret_freq += ref_div;
                /* New PRDIV/VDIV is closer. */
   -            if (diff > ret_freq - desireFreq)
   -            {
   -                diff      = ret_freq - desireFreq;
   +            if (diff > ret_freq - desireFreq) {
   +                diff = ret_freq - desireFreq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
        }
    
   -    if (0xFFFFFFFFU != diff)
   -    {
   +    if (0xFFFFFFFFU != diff) {
            /* PRDIV/VDIV found. */
   -        *prdiv   = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -        *vdiv    = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +        *prdiv = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   +        *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
            ret_freq = (refFreq / ret_prdiv) * ret_vdiv;
            return ret_freq;
   -    }
   -    else
   -    {
   +    } else   {
            /* No proper PRDIV/VDIV found. */
            return 0U;
        }
   @@ -1012,7 +973,8 @@
     *
     * param config Pointer to the configuration structure.
     */
   -void CLOCK_EnablePll0(mcg_pll_config_t const *config)
   +void
   +CLOCK_EnablePll0(mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1027,8 +989,7 @@
        MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode);
    
        /* Wait for PLL lock. */
   -    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
        }
    }
    
   @@ -1039,23 +1000,18 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
    {
        /* Clear the previous flag, MCG_SC[LOCS0]. */
        MCG->SC &= ~(uint8_t)MCG_SC_ATMF_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= ~(uint8_t)MCG_C6_CME0_MASK;
   -    }
   -    else
   -    {
   -        if (kMCG_MonitorInt == mode)
   -        {
   +    } else   {
   +        if (kMCG_MonitorInt == mode) {
                MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK;
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C2 |= MCG_C2_LOCRE0_MASK;
            }
            MCG->C6 |= MCG_C6_CME0_MASK;
   @@ -1069,16 +1025,15 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8 = MCG->C8;
    
        mcg_c8 &= ~(uint8_t)(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK);
    
   -    if (kMCG_MonitorNone != mode)
   -    {
   -        if (kMCG_MonitorReset == mode)
   -        {
   +    if (kMCG_MonitorNone != mode) {
   +        if (kMCG_MonitorReset == mode) {
                mcg_c8 |= MCG_C8_LOCRE1_MASK;
            }
            mcg_c8 |= MCG_C8_CME1_MASK;
   @@ -1093,29 +1048,24 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8;
    
        /* Clear previous flag. */
        MCG->S = MCG_S_LOLS0_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= (uint8_t)(~MCG_C6_LOLIE0_MASK);
   -    }
   -    else
   -    {
   +    } else   {
            mcg_c8 = MCG->C8;
    
            mcg_c8 &= (uint8_t)(~MCG_C8_LOCS1_MASK);
    
   -        if (kMCG_MonitorInt == mode)
   -        {
   +        if (kMCG_MonitorInt == mode) {
                mcg_c8 &= (uint8_t)(~MCG_C8_LOLRE_MASK);
   -        }
   -        else
   -        {
   +        } else   {
                mcg_c8 |= MCG_C8_LOLRE_MASK;
            }
            MCG->C8 = mcg_c8;
   @@ -1149,29 +1099,25 @@
     *
     * return  Logical OR value of the ref _mcg_status_flags_t.
     */
   -uint32_t CLOCK_GetStatusFlags(void)
   -{
   -    uint32_t ret  = 0U;
   +uint32_t
   +CLOCK_GetStatusFlags(void)
   +{
   +    uint32_t ret = 0U;
        uint8_t mcg_s = MCG->S;
    
   -    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U)
   -    {
   +    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0LostFlag;
        }
   -    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0InitFlag;
        }
   -    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK))
   -    {
   +    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK)) {
            ret |= (uint32_t)kMCG_RtcOscLostFlag;
        }
   -    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LostFlag;
        }
   -    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LockFlag;
        }
        return ret;
   @@ -1193,21 +1139,19 @@
     * param mask The status flags to clear. This is a logical OR of members of the
     *             enumeration ref _mcg_status_flags_t.
     */
   -void CLOCK_ClearStatusFlags(uint32_t mask)
   +void
   +CLOCK_ClearStatusFlags(uint32_t mask)
    {
        uint8_t reg;
    
   -    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL) {
            MCG->SC &= (uint8_t)(~MCG_SC_ATMF_MASK);
        }
   -    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag))
   -    {
   -        reg     = MCG->C8;
   +    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag)) {
   +        reg = MCG->C8;
            MCG->C8 = reg;
        }
   -    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL) {
            MCG->S = MCG_S_LOLS0_MASK;
        }
    }
   @@ -1219,7 +1163,8 @@
     *
     * param  config Pointer to the OSC0 configuration structure.
     */
   -void CLOCK_InitOsc0(osc_config_t const *config)
   +void
   +CLOCK_InitOsc0(osc_config_t const *config)
    {
        uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq);
    
   @@ -1228,11 +1173,9 @@
        MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode);
        OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
    
   -    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U))
   -    {
   +    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)) {
            /* Wait for stable. */
   -        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -        {
   +        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
            }
        }
    }
   @@ -1242,7 +1185,8 @@
     *
     * This function deinitializes the OSC0.
     */
   -void CLOCK_DeinitOsc0(void)
   +void
   +CLOCK_DeinitOsc0(void)
    {
        OSC0->CR = 0U;
        MCG->C2 &= ~(uint8_t)OSC_MODE_MASK;
   @@ -1253,7 +1197,8 @@
     *
     * param freq The Slow IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetSlowIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetSlowIrcFreq(uint32_t freq)
    {
        s_slowIrcFreq = freq;
    }
   @@ -1263,7 +1208,8 @@
     *
     * param freq The Fast IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetFastIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetFastIrcFreq(uint32_t freq)
    {
        s_fastIrcFreq = freq;
    }
   @@ -1286,7 +1232,8 @@
     * retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
     * retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
     */
   -status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
   +status_t
   +CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
    {
        uint32_t multi; /* extFreq / desireFreq */
        uint32_t actv;  /* Auto trim value. */
   @@ -1299,30 +1246,24 @@
            {TRIM_FIRC_MIN, TRIM_FIRC_MAX}  /* Fast IRC. */
        };
    
   -    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN))
   -    {
   +    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) {
            status = kStatus_MCG_AtmBusClockInvalid;
        }
        /* Check desired frequency range. */
   -    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1]))
   -    {
   +    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) {
            status = kStatus_MCG_AtmDesiredFreqInvalid;
        }
        /*
           Make sure internal reference clock is not used to generate bus clock.
           Here only need to check (MCG_S_IREFST == 1).
         */
   -    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK))
   -    {
   +    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) {
            status = kStatus_MCG_AtmIrcUsed;
   -    }
   -    else
   -    {
   +    } else   {
            multi = extFreq / desireFreq;
   -        actv  = multi * 21U;
   -
   -        if (kMCG_AtmSel4m == atms)
   -        {
   +        actv = multi * 21U;
   +
   +        if (kMCG_AtmSel4m == atms) {
                actv *= 128U;
            }
    
   @@ -1336,27 +1277,20 @@
            MCG->SC = (mcg_sc | MCG_SC_ATME_MASK);
    
            /* Wait for MCG finished. */
   -        while (0U != (MCG->SC & MCG_SC_ATME_MASK))
   -        {
   +        while (0U != (MCG->SC & MCG_SC_ATME_MASK)) {
            }
    
            /* Error occurs? */
   -        if (0U != (MCG->SC & MCG_SC_ATMF_MASK))
   -        {
   +        if (0U != (MCG->SC & MCG_SC_ATMF_MASK)) {
                /* Clear the failed flag. */
                MCG->SC = mcg_sc;
   -            status  = kStatus_MCG_AtmHardwareFail;
   -        }
   -        else
   -        {
   +            status = kStatus_MCG_AtmHardwareFail;
   +        } else   {
                *actualFreq = extFreq / multi;
    
   -            if (kMCG_AtmSel4m == atms)
   -            {
   +            if (kMCG_AtmSel4m == atms) {
                    s_fastIrcFreq = *actualFreq;
   -            }
   -            else
   -            {
   +            } else   {
                    s_slowIrcFreq = *actualFreq;
                }
            }
   @@ -1372,103 +1306,83 @@
     *
     * return Current MCG mode or error code; See ref mcg_mode_t.
     */
   -mcg_mode_t CLOCK_GetMode(void)
   +mcg_mode_t
   +CLOCK_GetMode(void)
    {
        mcg_mode_t mode = kMCG_ModeError;
   -    uint32_t clkst  = (uint32_t)MCG_S_CLKST_VAL;
   +    uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
        uint32_t irefst = (uint32_t)MCG_S_IREFST_VAL;
   -    uint32_t lp     = (uint32_t)MCG_C2_LP_VAL;
   -    uint32_t pllst  = MCG_S_PLLST_VAL;
   +    uint32_t lp = (uint32_t)MCG_C2_LP_VAL;
   +    uint32_t pllst = MCG_S_PLLST_VAL;
    
        /*------------------------------------------------------------------
                               Mode and Registers
   -    ____________________________________________________________________
   -
   -      Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   -    ____________________________________________________________________
   -
   -      FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -      PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   -    ____________________________________________________________________
   -
   -      PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -    ----------------------------------------------------------------------*/
   -
   -    if (clkst == (uint32_t)kMCG_ClkOutStatFll)
   -    {
   -        if ((uint32_t)kMCG_FllSrcExternal == irefst)
   -        {
   +       ____________________________________________________________________
   +
   +       Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   +       ____________________________________________________________________
   +
   +       FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   +       ____________________________________________________________________
   +
   +       PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       ----------------------------------------------------------------------*/
   +
   +    if (clkst == (uint32_t)kMCG_ClkOutStatFll) {
   +        if ((uint32_t)kMCG_FllSrcExternal == irefst) {
                mode = kMCG_ModeFEE;
   -        }
   -        else
   -        {
   +        } else   {
                mode = kMCG_ModeFEI;
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatInt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatInt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPI;
   -        }
   -        else
   -        {
   +        } else   {
                {
                    mode = kMCG_ModeFBI;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatExt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatExt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPE;
   -        }
   -        else
   -        {
   -            if ((uint32_t)kMCG_PllstPll == pllst)
   -            {
   +        } else   {
   +            if ((uint32_t)kMCG_PllstPll == pllst) {
                    mode = kMCG_ModePBE;
   -            }
   -            else
   -            {
   +            } else   {
                    mode = kMCG_ModeFBE;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatPll)
   -    {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatPll)   {
            {
                mode = kMCG_ModePEE;
            }
   -    }
   -    else
   -    {
   +    } else   {
            /*do nothing*/
        }
    
   @@ -1490,15 +1404,15 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to a frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode)))
   -    {
   +    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1510,8 +1424,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1523,13 +1436,11 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1538,13 +1449,11 @@
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1566,15 +1475,15 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode)))
   -    {
   +    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1586,8 +1495,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1600,45 +1508,37 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
        /* Set DRS and DMX32. */
   -    mcg_c4  = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
   +    mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
        MCG->C4 = mcg_c4;
    
        /* Wait for DRST_DRS update. */
   -    while (MCG->C4 != mcg_c4)
   -    {
   +    while (MCG->C4 != mcg_c4) {
        }
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1661,7 +1561,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1670,9 +1571,7 @@
        mcg_mode_t mode = CLOCK_GetMode();
    
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModeBLPI == mode)))
   -
   -    {
   +          (kMCG_ModeBLPI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1687,8 +1586,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1700,26 +1598,22 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   -    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) {
        }
    
        MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1741,7 +1635,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1749,16 +1644,14 @@
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode)))
   -    {
   +          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
    
        /* Change to FLL mode. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Set LP bit to enable the FLL */
   @@ -1772,8 +1665,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1786,24 +1678,19 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for Reference clock Status bit to clear */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1812,13 +1699,11 @@
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for clock status bits to show clock source is ext ref clk */
   -    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for fll stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1834,11 +1719,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpiMode(void)
   +status_t
   +CLOCK_SetBlpiMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1858,11 +1743,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpeMode(void)
   +status_t
   +CLOCK_SetBlpeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1892,7 +1777,8 @@
     * configuration structure not necessary. In this case, pass in NULL.
     * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
     */
   -status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1907,14 +1793,12 @@
    
        /* Wait for CLKST clock status bits to show clock source is ext ref clk */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* Disable PLL first, then configure PLL. */
        MCG->C6 &= (uint8_t)(~MCG_C6_PLLS_MASK);
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Configure the PLL. */
   @@ -1926,8 +1810,7 @@
        MCG->C6 |= MCG_C6_PLLS_MASK;
    
        /* Wait for PLL mode changed. */
   -    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U) {
        }
    
        return kStatus_Success;
   @@ -1945,12 +1828,12 @@
     *       PRDIV/VDIV are different than in the PBE mode, set them up
     *       in PBE mode and wait. When the clock is stable, switch to PEE mode.
     */
   -status_t CLOCK_SetPeeMode(void)
   +status_t
   +CLOCK_SetPeeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (kMCG_ModePBE != mode)
   -    {
   +    if (kMCG_ModePBE != mode) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1959,8 +1842,7 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
    
        /* Wait for clock status bits to update */
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -1982,11 +1864,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
     */
   -status_t CLOCK_ExternalModeToFbeModeQuick(void)
   +status_t
   +CLOCK_ExternalModeToFbeModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) != 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) != 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1995,14 +1877,12 @@
        MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK);
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
        }
    
        /* Disable PLL. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        return kStatus_Success;
   @@ -2024,11 +1904,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
     */
   -status_t CLOCK_InternalModeToFbiModeQuick(void)
   +status_t
   +CLOCK_InternalModeToFbiModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) == 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) == 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif
   @@ -2037,8 +1917,7 @@
        MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        return kStatus_Success;
   @@ -2059,7 +1938,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
    }
   @@ -2079,8 +1959,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToFeeMode(
   -    mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeeMode(mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2100,15 +1980,15 @@
     * retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
   +status_t
   +CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
    {
        /* If reset mode is FEI mode, set MCGIRCLK and always success. */
        (void)CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
    
        /* If reset mode is not BLPI, first enter FBI mode. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        /* Enter BLPI mode. */
   @@ -2128,7 +2008,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2138,20 +2019,16 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* In FBE now, start to enter BLPE. */
   @@ -2173,7 +2050,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -2183,8 +2061,7 @@
    
        /* Change to use PLL output clock. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -2233,7 +2110,8 @@
     * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
     * function.
     */
   -status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
   +status_t
   +CLOCK_SetMcgConfig(const mcg_config_t *config)
    {
        mcg_mode_t next_mode;
        status_t status = kStatus_Success;
   @@ -2241,11 +2119,9 @@
        mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0;
    
        /* If need to change external clock, MCG_C7[OSCSEL]. */
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel))
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel)) {
            /* If external clock is in use, change to FEI first. */
   -        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -        {
   +        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
                (void)CLOCK_ExternalModeToFbeModeQuick();
                (void)CLOCK_SetFeiMode(config->dmx32, config->drs, NULL);
            }
   @@ -2254,8 +2130,7 @@
        }
    
        /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
   -    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt) {
            MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */
    
            {
   @@ -2268,67 +2143,56 @@
    
        next_mode = CLOCK_GetMode();
    
   -    do
   -    {
   +    do{
            next_mode = mcgModeMatrix[next_mode][config->mcgMode];
    
   -        switch (next_mode)
   -        {
   -            case kMCG_ModeFEI:
   -                status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFEE:
   -                status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFBI:
   -                status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeFBE:
   -                status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeBLPI:
   -                status = CLOCK_SetBlpiMode();
   -                break;
   -            case kMCG_ModeBLPE:
   -                status = CLOCK_SetBlpeMode();
   -                break;
   -            case kMCG_ModePBE:
   -                /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   -                if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode))
   +        switch (next_mode) {
   +        case kMCG_ModeFEI:
   +            status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFEE:
   +            status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFBI:
   +            status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeFBE:
   +            status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeBLPI:
   +            status = CLOCK_SetBlpiMode();
   +            break;
   +        case kMCG_ModeBLPE:
   +            status = CLOCK_SetBlpeMode();
   +            break;
   +        case kMCG_ModePBE:
   +            /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   +            if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) {
                    {
   -                    {
   -                        status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
   -                    }
   +                    status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
                    }
   -                else
   -                {
   -                    MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -                    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -                    {
   -                    }
   +            } else   {
   +                MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   +                while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
                    }
   -                break;
   -            case kMCG_ModePEE:
   -                status = CLOCK_SetPeeMode();
   -                break;
   -            default:
   -                assert(false);
   -                break;
   -        }
   -        if (kStatus_Success != status)
   -        {
   +            }
                break;
   +        case kMCG_ModePEE:
   +            status = CLOCK_SetPeeMode();
   +            break;
   +        default:
   +            assert(false);
   +            break;
   +        }
   +        if (kStatus_Success != status) {
   +            break;
            }
        } while (next_mode != config->mcgMode);
    
   -    if (status == kStatus_Success)
   -    {
   -        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U)
   -        {
   +    if (status == kStatus_Success) {
   +        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U) {
                CLOCK_EnablePll0(&config->pll0Config);
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_qspi.c
   <details>
   
   ```diff
   @@ -133,7 +133,7 @@
    {
        int i;
        for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++) {
   -        dst[i] = ((uint32_t*)address)[i];
   +        dst[i] = ((uint32_t *)address)[i];
        }
    }
    
   ```
   
   </details>


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[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

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URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-773567186






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   <!-- style-bot -->
   
   ## Style check summary
   
   #### No suggestions at this time!
   


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[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

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apache-mynewt-bot removed a comment on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-773577569


   
   <!-- style-bot -->
   
   ## Style check summary
   
   ### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
   
   
   #### hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c
   <details>
   
   ```diff
   @@ -187,15 +187,15 @@
     ******************************************************************************/
    
    #ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
   -static void CLOCK_FllStableDelay(void)
   +static void
   +CLOCK_FllStableDelay(void)
    {
        /*
           Should wait at least 1ms. Because in these modes, the core clock is 100MHz
           at most, so this function could obtain the 1ms delay.
         */
        volatile uint32_t i = 30000U;
   -    while (0U != (i--))
   -    {
   +    while (0U != (i--)) {
            __NOP();
        }
    }
   @@ -207,34 +207,35 @@
    extern void CLOCK_FllStableDelay(void);
    #endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */
    
   -static uint32_t CLOCK_GetMcgExtClkFreq(void)
   +static uint32_t
   +CLOCK_GetMcgExtClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (MCG_C7_OSCSEL_VAL)
   -    {
   -        case 0U:
   -            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   -            assert(0U != g_xtal0Freq);
   -            freq = g_xtal0Freq;
   -            break;
   -        case 1U:
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(0U != g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 2U:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (MCG_C7_OSCSEL_VAL) {
   +    case 0U:
   +        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   +        assert(0U != g_xtal0Freq);
   +        freq = g_xtal0Freq;
   +        break;
   +    case 1U:
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(0U != g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 2U:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllExtRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllExtRefClkFreq(void)
    {
        /* FllExtRef = McgExtRef / FllExtRefDiv */
        uint8_t frdiv;
   @@ -246,54 +247,50 @@
        frdiv = MCG_C1_FRDIV_VAL;
        freq >>= frdiv;
    
   -    range  = MCG_C2_RANGE_VAL;
   +    range = MCG_C2_RANGE_VAL;
        oscsel = MCG_C7_OSCSEL_VAL;
    
        /*
           When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536.
           1. MCG_C7[OSCSEL] selects IRC48M.
           2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0.
   -    */
   -    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel))
   -    {
   -        switch (frdiv)
   -        {
   -            case 0:
   -            case 1:
   -            case 2:
   -            case 3:
   -            case 4:
   -            case 5:
   -                freq >>= 5u;
   -                break;
   -            case 6:
   -                /* 64*20=1280 */
   -                freq /= 20u;
   -                break;
   -            case 7:
   -                /* 128*12=1536 */
   -                freq /= 12u;
   -                break;
   -            default:
   -                freq = 0u;
   -                break;
   +     */
   +    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel)) {
   +        switch (frdiv) {
   +        case 0:
   +        case 1:
   +        case 2:
   +        case 3:
   +        case 4:
   +        case 5:
   +            freq >>= 5u;
   +            break;
   +        case 6:
   +            /* 64*20=1280 */
   +            freq /= 20u;
   +            break;
   +        case 7:
   +            /* 128*12=1536 */
   +            freq /= 12u;
   +            break;
   +        default:
   +            freq = 0u;
   +            break;
            }
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetInternalRefClkSelectFreq(void)
   +static uint32_t
   +CLOCK_GetInternalRefClkSelectFreq(void)
    {
        uint32_t freq;
    
   -    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL)
   -    {
   +    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL) {
            /* Slow internal reference clock selected*/
            freq = s_slowIrcFreq;
   -    }
   -    else
   -    {
   +    } else   {
            /* Fast internal reference clock selected*/
            freq = s_fastIrcFreq >> MCG_SC_FCRDIV_VAL;
        }
   @@ -301,44 +298,40 @@
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If use external reference clock. */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            freq = CLOCK_GetFllExtRefClkFreq();
        }
        /* If use internal reference clock. */
   -    else
   -    {
   +    else {
            freq = s_slowIrcFreq;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetPll0RefFreq(void)
   +static uint32_t
   +CLOCK_GetPll0RefFreq(void)
    {
        /* MCG external reference clock. */
        return CLOCK_GetMcgExtClkFreq();
    }
    
   -static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
   +static uint8_t
   +CLOCK_GetOscRangeFromFreq(uint32_t freq)
    {
        uint8_t range;
    
   -    if (freq <= 39063U)
   -    {
   +    if (freq <= 39063U) {
            range = 0U;
   -    }
   -    else if (freq <= 8000000U)
   -    {
   +    } else if (freq <= 8000000U)   {
            range = 1U;
   -    }
   -    else
   -    {
   +    } else   {
            range = 2U;
        }
    
   @@ -350,17 +343,15 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetOsc0ErClkFreq(void)
   +uint32_t
   +CLOCK_GetOsc0ErClkFreq(void)
    {
        uint32_t freq;
   -    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)
   -    {
   +    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U) {
            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
            assert(g_xtal0Freq);
            freq = g_xtal0Freq;
   -    }
   -    else
   -    {
   +    } else   {
            freq = 0U;
        }
    
   @@ -372,26 +363,26 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetEr32kClkFreq(void)
   +uint32_t
   +CLOCK_GetEr32kClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT1_OSC32KSEL_VAL)
   -    {
   -        case 0U: /* OSC 32k clock  */
   -            freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   -            break;
   -        case 2U: /* RTC 32k clock  */
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 3U: /* LPO clock      */
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT1_OSC32KSEL_VAL) {
   +    case 0U:     /* OSC 32k clock  */
   +        freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   +        break;
   +    case 2U:     /* RTC 32k clock  */
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 3U:     /* LPO clock      */
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
        return freq;
    }
   @@ -401,24 +392,24 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPllFllSelClkFreq(void)
   +uint32_t
   +CLOCK_GetPllFllSelClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT2_PLLFLLSEL_VAL)
   -    {
   -        case 0U: /* FLL. */
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case 1U: /* PLL. */
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case 3U: /* MCG IRC48M. */
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT2_PLLFLLSEL_VAL) {
   +    case 0U:     /* FLL. */
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case 1U:     /* PLL. */
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case 3U:     /* MCG IRC48M. */
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -429,7 +420,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPlatClkFreq(void)
   +uint32_t
   +CLOCK_GetPlatClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -439,7 +431,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlashClkFreq(void)
   +uint32_t
   +CLOCK_GetFlashClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
    }
   @@ -449,7 +442,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlexBusClkFreq(void)
   +uint32_t
   +CLOCK_GetFlexBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
    }
   @@ -459,7 +453,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetBusClkFreq(void)
   +uint32_t
   +CLOCK_GetBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
    }
   @@ -469,7 +464,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetCoreSysClkFreq(void)
   +uint32_t
   +CLOCK_GetCoreSysClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -484,55 +480,55 @@
     * param clockName Clock names defined in clock_name_t
     * return Clock frequency value in Hertz
     */
   -uint32_t CLOCK_GetFreq(clock_name_t clockName)
   +uint32_t
   +CLOCK_GetFreq(clock_name_t clockName)
    {
        uint32_t freq;
    
   -    switch (clockName)
   -    {
   -        case kCLOCK_CoreSysClk:
   -        case kCLOCK_PlatClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   -            break;
   -        case kCLOCK_BusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlexBusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlashClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   -            break;
   -        case kCLOCK_PllFllSelClk:
   -            freq = CLOCK_GetPllFllSelClkFreq();
   -            break;
   -        case kCLOCK_Er32kClk:
   -            freq = CLOCK_GetEr32kClkFreq();
   -            break;
   -        case kCLOCK_Osc0ErClk:
   -            freq = CLOCK_GetOsc0ErClkFreq();
   -            break;
   -        case kCLOCK_McgFixedFreqClk:
   -            freq = CLOCK_GetFixedFreqClkFreq();
   -            break;
   -        case kCLOCK_McgInternalRefClk:
   -            freq = CLOCK_GetInternalRefClkFreq();
   -            break;
   -        case kCLOCK_McgFllClk:
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case kCLOCK_McgPll0Clk:
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case kCLOCK_McgIrc48MClk:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        case kCLOCK_LpoClk:
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (clockName) {
   +    case kCLOCK_CoreSysClk:
   +    case kCLOCK_PlatClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   +        break;
   +    case kCLOCK_BusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlexBusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlashClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   +        break;
   +    case kCLOCK_PllFllSelClk:
   +        freq = CLOCK_GetPllFllSelClkFreq();
   +        break;
   +    case kCLOCK_Er32kClk:
   +        freq = CLOCK_GetEr32kClkFreq();
   +        break;
   +    case kCLOCK_Osc0ErClk:
   +        freq = CLOCK_GetOsc0ErClkFreq();
   +        break;
   +    case kCLOCK_McgFixedFreqClk:
   +        freq = CLOCK_GetFixedFreqClkFreq();
   +        break;
   +    case kCLOCK_McgInternalRefClk:
   +        freq = CLOCK_GetInternalRefClkFreq();
   +        break;
   +    case kCLOCK_McgFllClk:
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case kCLOCK_McgPll0Clk:
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case kCLOCK_McgIrc48MClk:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    case kCLOCK_LpoClk:
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -545,7 +541,8 @@
     *
     * param config Pointer to the configure structure.
     */
   -void CLOCK_SetSimConfig(sim_clock_config_t const *config)
   +void
   +CLOCK_SetSimConfig(sim_clock_config_t const *config)
    {
        SIM->CLKDIV1 = config->clkdiv1;
        CLOCK_SetPllFllSelClock(config->pllFllSel);
   @@ -559,35 +556,32 @@
     * retval true The clock is set successfully.
     * retval false The clock source is invalid to get proper USB FS clock.
     */
   -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
   +bool
   +CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
    {
        bool ret = true;
    
        CLOCK_DisableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcExt == src)
   -    {
   +    if (kCLOCK_UsbSrcExt == src) {
            SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
   -    }
   -    else
   -    {
   -        switch (freq)
   -        {
   -            case 120000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 96000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            case 72000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 48000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            default:
   -                ret = false;
   -                break;
   +    } else   {
   +        switch (freq) {
   +        case 120000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 96000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        case 72000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 48000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        default:
   +            ret = false;
   +            break;
            }
    
            SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src);
   @@ -595,8 +589,7 @@
    
        CLOCK_EnableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcIrc48M == src)
   -    {
   +    if (kCLOCK_UsbSrcIrc48M == src) {
            USB0->CLK_RECOVER_IRC_EN = 0x03U;
            USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
        }
   @@ -611,28 +604,28 @@
     *
     * return The frequency of MCGOUTCLK.
     */
   -uint32_t CLOCK_GetOutClkFreq(void)
   +uint32_t
   +CLOCK_GetOutClkFreq(void)
    {
        uint32_t mcgoutclk;
        uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
    
   -    switch (clkst)
   -    {
   -        case (uint32_t)kMCG_ClkOutStatPll:
   -            mcgoutclk = CLOCK_GetPll0Freq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatFll:
   -            mcgoutclk = CLOCK_GetFllFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatInt:
   -            mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatExt:
   -            mcgoutclk = CLOCK_GetMcgExtClkFreq();
   -            break;
   -        default:
   -            mcgoutclk = 0U;
   -            break;
   +    switch (clkst) {
   +    case (uint32_t)kMCG_ClkOutStatPll:
   +        mcgoutclk = CLOCK_GetPll0Freq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatFll:
   +        mcgoutclk = CLOCK_GetFllFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatInt:
   +        mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatExt:
   +        mcgoutclk = CLOCK_GetMcgExtClkFreq();
   +        break;
   +    default:
   +        mcgoutclk = 0U;
   +        break;
        }
    
        return mcgoutclk;
   @@ -647,7 +640,8 @@
     *
     * return The frequency of MCGFLLCLK.
     */
   -uint32_t CLOCK_GetFllFreq(void)
   +uint32_t
   +CLOCK_GetFllFreq(void)
    {
        static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}};
    
   @@ -656,23 +650,17 @@
        uint32_t ret;
    
        /* If FLL is not enabled currently, then return 0U. */
   -    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U)))
   -    {
   +    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) {
            ret = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            /* Get FLL reference clock frequency. */
            freq = CLOCK_GetFllRefClkFreq();
   -        if (0U == freq)
   -        {
   +        if (0U == freq) {
                ret = freq;
   -        }
   -        else
   -        {
   -            drs   = MCG_C4_DRST_DRS_VAL;
   +        } else   {
   +            drs = MCG_C4_DRST_DRS_VAL;
                dmx32 = MCG_C4_DMX32_VAL;
   -            ret   = freq * fllFactorTable[drs][dmx32];
   +            ret = freq * fllFactorTable[drs][dmx32];
            }
        }
    
   @@ -687,17 +675,15 @@
     *
     * return The frequency of MCGIRCLK.
     */
   -uint32_t CLOCK_GetInternalRefClkFreq(void)
   +uint32_t
   +CLOCK_GetInternalRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If MCGIRCLK is gated. */
   -    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK))
   -    {
   +    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            freq = CLOCK_GetInternalRefClkSelectFreq();
        }
    
   @@ -712,18 +698,16 @@
     *
     * return The frequency of MCGFFCLK.
     */
   -uint32_t CLOCK_GetFixedFreqClkFreq(void)
   +uint32_t
   +CLOCK_GetFixedFreqClkFreq(void)
    {
        uint32_t freq = CLOCK_GetFllRefClkFreq();
        uint32_t ret;
    
        /* MCGFFCLK must be no more than MCGOUTCLK/8. */
   -    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq))
   -    {
   +    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq)) {
            ret = freq;
   -    }
   -    else
   -    {
   +    } else   {
            ret = 0U;
        }
    
   @@ -738,7 +722,8 @@
     *
     * return The frequency of MCGPLL0CLK.
     */
   -uint32_t CLOCK_GetPll0Freq(void)
   +uint32_t
   +CLOCK_GetPll0Freq(void)
    {
        uint32_t mcgpll0clk;
        uint32_t freq;
   @@ -746,12 +731,9 @@
        uint8_t mcgpll0prdiv;
        uint8_t mcgpll0vdiv;
        /* If PLL0 is not enabled, return 0. */
   -    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            mcgpll0clk = CLOCK_GetPll0RefFreq();
    
            /*
   @@ -783,36 +765,31 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success External reference clock set successfully.
     */
   -status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
    {
        bool needDelay;
        uint32_t i;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */
   -    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK)))
   -    {
   +    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) {
            return kStatus_MCG_SourceUsed;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
    
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel)
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel) {
            /* If change OSCSEL, need to delay, ERR009878. */
            needDelay = true;
   -    }
   -    else
   -    {
   +    } else   {
            needDelay = false;
        }
    
        MCG->C7 = (uint8_t)(MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
   -    if (needDelay)
   -    {
   +    if (needDelay) {
            /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
            i = 1500U;
   -        while (0U != (i--))
   -        {
   +        while (0U != (i--)) {
                __NOP();
            }
        }
   @@ -836,34 +813,30 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success MCGIRCLK configuration finished successfully.
     */
   -status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
   +status_t
   +CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
    {
        uint32_t mcgOutClkState = (uint32_t)MCG_S_CLKST_VAL;
   -    mcg_irc_mode_t curIrcs  = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   -    uint8_t curFcrdiv       = MCG_SC_FCRDIV_VAL;
   +    mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   +    uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If MCGIRCLK is used as system clock source. */
   -    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState)
   -    {
   +    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState) {
            /* If need to change MCGIRCLK source or driver, return error. */
   -        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs))
   -        {
   +        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) {
                return kStatus_MCG_SourceUsed;
            }
        }
    #endif
    
        /* If need to update the FCRDIV. */
   -    if (fcrdiv != curFcrdiv)
   -    {
   +    if (fcrdiv != curFcrdiv) {
            /* If fast IRC is in use currently, change to slow IRC. */
            if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) &&
   -            (kMCG_IrcFast == curIrcs))
   -        {
   +            (kMCG_IrcFast == curIrcs)) {
                MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
   -            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow)
   -            {
   +            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow) {
                }
            }
            /* Update FCRDIV. */
   @@ -876,10 +849,8 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode);
    
        /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
   -    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable)))
   -    {
   -        while (MCG_S_IRCST_VAL != (uint8_t)ircs)
   -        {
   +    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable))) {
   +        while (MCG_S_IRCST_VAL != (uint8_t)ircs) {
            }
        }
    
   @@ -901,7 +872,8 @@
     * param vdiv       VDIV value to generate desired PLL frequency.
     * return Closest frequency match that the PLL was able generate.
     */
   -uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
   +uint32_t
   +CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
    {
        uint8_t ret_prdiv;               /* PRDIV to return. */
        uint8_t ret_vdiv;                /* VDIV to return.  */
   @@ -910,7 +882,7 @@
        uint8_t prdiv_cur;               /* PRDIV value for iteration.    */
        uint8_t vdiv_cur;                /* VDIV value for iteration.     */
        uint32_t ret_freq = 0U;          /* PLL output frequency to return. */
   -    uint32_t diff     = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */
   +    uint32_t diff = 0xFFFFFFFFU;     /* Difference between desireFreq and return frequency. */
        uint32_t ref_div;                /* Reference frequency after PRDIV. */
    
        /*
   @@ -929,8 +901,7 @@
        /* Reference frequency is out of range. */
        if ((refFreq < (uint32_t)FSL_FEATURE_MCG_PLL_REF_MIN) ||
            (refFreq > ((uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX *
   -                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE))))
   -    {
   +                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) {
            return 0U;
        }
    
   @@ -940,62 +911,52 @@
            (uint8_t)((refFreq + (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX);
    
        /* PRDIV traversal. */
   -    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--)
   -    {
   +    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) {
            /* Reference frequency after PRDIV. */
            ref_div = refFreq / prdiv_cur;
    
            vdiv_cur = (uint8_t)(desireFreq / ref_div);
    
            if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) ||
   -            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                /* No VDIV is available with this PRDIV. */
                continue;
            }
    
            ret_freq = vdiv_cur * ref_div;
    
   -        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE)
   -        {
   -            if (ret_freq == desireFreq) /* If desire frequency is got. */
   -            {
   +        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) {
   +            if (ret_freq == desireFreq) { /* If desire frequency is got. */
                    *prdiv = prdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -                *vdiv  = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +                *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
                    return ret_freq;
                }
                /* New PRDIV/VDIV is closer. */
   -            if (diff > desireFreq - ret_freq)
   -            {
   -                diff      = desireFreq - ret_freq;
   +            if (diff > desireFreq - ret_freq) {
   +                diff = desireFreq - ret_freq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
            vdiv_cur++;
   -        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                ret_freq += ref_div;
                /* New PRDIV/VDIV is closer. */
   -            if (diff > ret_freq - desireFreq)
   -            {
   -                diff      = ret_freq - desireFreq;
   +            if (diff > ret_freq - desireFreq) {
   +                diff = ret_freq - desireFreq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
        }
    
   -    if (0xFFFFFFFFU != diff)
   -    {
   +    if (0xFFFFFFFFU != diff) {
            /* PRDIV/VDIV found. */
   -        *prdiv   = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -        *vdiv    = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +        *prdiv = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   +        *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
            ret_freq = (refFreq / ret_prdiv) * ret_vdiv;
            return ret_freq;
   -    }
   -    else
   -    {
   +    } else   {
            /* No proper PRDIV/VDIV found. */
            return 0U;
        }
   @@ -1012,7 +973,8 @@
     *
     * param config Pointer to the configuration structure.
     */
   -void CLOCK_EnablePll0(mcg_pll_config_t const *config)
   +void
   +CLOCK_EnablePll0(mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1027,8 +989,7 @@
        MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode);
    
        /* Wait for PLL lock. */
   -    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
        }
    }
    
   @@ -1039,23 +1000,18 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
    {
        /* Clear the previous flag, MCG_SC[LOCS0]. */
        MCG->SC &= ~(uint8_t)MCG_SC_ATMF_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= ~(uint8_t)MCG_C6_CME0_MASK;
   -    }
   -    else
   -    {
   -        if (kMCG_MonitorInt == mode)
   -        {
   +    } else   {
   +        if (kMCG_MonitorInt == mode) {
                MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK;
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C2 |= MCG_C2_LOCRE0_MASK;
            }
            MCG->C6 |= MCG_C6_CME0_MASK;
   @@ -1069,16 +1025,15 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8 = MCG->C8;
    
        mcg_c8 &= ~(uint8_t)(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK);
    
   -    if (kMCG_MonitorNone != mode)
   -    {
   -        if (kMCG_MonitorReset == mode)
   -        {
   +    if (kMCG_MonitorNone != mode) {
   +        if (kMCG_MonitorReset == mode) {
                mcg_c8 |= MCG_C8_LOCRE1_MASK;
            }
            mcg_c8 |= MCG_C8_CME1_MASK;
   @@ -1093,29 +1048,24 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8;
    
        /* Clear previous flag. */
        MCG->S = MCG_S_LOLS0_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= (uint8_t)(~MCG_C6_LOLIE0_MASK);
   -    }
   -    else
   -    {
   +    } else   {
            mcg_c8 = MCG->C8;
    
            mcg_c8 &= (uint8_t)(~MCG_C8_LOCS1_MASK);
    
   -        if (kMCG_MonitorInt == mode)
   -        {
   +        if (kMCG_MonitorInt == mode) {
                mcg_c8 &= (uint8_t)(~MCG_C8_LOLRE_MASK);
   -        }
   -        else
   -        {
   +        } else   {
                mcg_c8 |= MCG_C8_LOLRE_MASK;
            }
            MCG->C8 = mcg_c8;
   @@ -1149,29 +1099,25 @@
     *
     * return  Logical OR value of the ref _mcg_status_flags_t.
     */
   -uint32_t CLOCK_GetStatusFlags(void)
   -{
   -    uint32_t ret  = 0U;
   +uint32_t
   +CLOCK_GetStatusFlags(void)
   +{
   +    uint32_t ret = 0U;
        uint8_t mcg_s = MCG->S;
    
   -    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U)
   -    {
   +    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0LostFlag;
        }
   -    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0InitFlag;
        }
   -    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK))
   -    {
   +    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK)) {
            ret |= (uint32_t)kMCG_RtcOscLostFlag;
        }
   -    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LostFlag;
        }
   -    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LockFlag;
        }
        return ret;
   @@ -1193,21 +1139,19 @@
     * param mask The status flags to clear. This is a logical OR of members of the
     *             enumeration ref _mcg_status_flags_t.
     */
   -void CLOCK_ClearStatusFlags(uint32_t mask)
   +void
   +CLOCK_ClearStatusFlags(uint32_t mask)
    {
        uint8_t reg;
    
   -    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL) {
            MCG->SC &= (uint8_t)(~MCG_SC_ATMF_MASK);
        }
   -    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag))
   -    {
   -        reg     = MCG->C8;
   +    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag)) {
   +        reg = MCG->C8;
            MCG->C8 = reg;
        }
   -    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL) {
            MCG->S = MCG_S_LOLS0_MASK;
        }
    }
   @@ -1219,7 +1163,8 @@
     *
     * param  config Pointer to the OSC0 configuration structure.
     */
   -void CLOCK_InitOsc0(osc_config_t const *config)
   +void
   +CLOCK_InitOsc0(osc_config_t const *config)
    {
        uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq);
    
   @@ -1228,11 +1173,9 @@
        MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode);
        OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
    
   -    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U))
   -    {
   +    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)) {
            /* Wait for stable. */
   -        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -        {
   +        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
            }
        }
    }
   @@ -1242,7 +1185,8 @@
     *
     * This function deinitializes the OSC0.
     */
   -void CLOCK_DeinitOsc0(void)
   +void
   +CLOCK_DeinitOsc0(void)
    {
        OSC0->CR = 0U;
        MCG->C2 &= ~(uint8_t)OSC_MODE_MASK;
   @@ -1253,7 +1197,8 @@
     *
     * param freq The Slow IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetSlowIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetSlowIrcFreq(uint32_t freq)
    {
        s_slowIrcFreq = freq;
    }
   @@ -1263,7 +1208,8 @@
     *
     * param freq The Fast IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetFastIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetFastIrcFreq(uint32_t freq)
    {
        s_fastIrcFreq = freq;
    }
   @@ -1286,7 +1232,8 @@
     * retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
     * retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
     */
   -status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
   +status_t
   +CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
    {
        uint32_t multi; /* extFreq / desireFreq */
        uint32_t actv;  /* Auto trim value. */
   @@ -1299,30 +1246,24 @@
            {TRIM_FIRC_MIN, TRIM_FIRC_MAX}  /* Fast IRC. */
        };
    
   -    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN))
   -    {
   +    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) {
            status = kStatus_MCG_AtmBusClockInvalid;
        }
        /* Check desired frequency range. */
   -    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1]))
   -    {
   +    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) {
            status = kStatus_MCG_AtmDesiredFreqInvalid;
        }
        /*
           Make sure internal reference clock is not used to generate bus clock.
           Here only need to check (MCG_S_IREFST == 1).
         */
   -    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK))
   -    {
   +    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) {
            status = kStatus_MCG_AtmIrcUsed;
   -    }
   -    else
   -    {
   +    } else   {
            multi = extFreq / desireFreq;
   -        actv  = multi * 21U;
   -
   -        if (kMCG_AtmSel4m == atms)
   -        {
   +        actv = multi * 21U;
   +
   +        if (kMCG_AtmSel4m == atms) {
                actv *= 128U;
            }
    
   @@ -1336,27 +1277,20 @@
            MCG->SC = (mcg_sc | MCG_SC_ATME_MASK);
    
            /* Wait for MCG finished. */
   -        while (0U != (MCG->SC & MCG_SC_ATME_MASK))
   -        {
   +        while (0U != (MCG->SC & MCG_SC_ATME_MASK)) {
            }
    
            /* Error occurs? */
   -        if (0U != (MCG->SC & MCG_SC_ATMF_MASK))
   -        {
   +        if (0U != (MCG->SC & MCG_SC_ATMF_MASK)) {
                /* Clear the failed flag. */
                MCG->SC = mcg_sc;
   -            status  = kStatus_MCG_AtmHardwareFail;
   -        }
   -        else
   -        {
   +            status = kStatus_MCG_AtmHardwareFail;
   +        } else   {
                *actualFreq = extFreq / multi;
    
   -            if (kMCG_AtmSel4m == atms)
   -            {
   +            if (kMCG_AtmSel4m == atms) {
                    s_fastIrcFreq = *actualFreq;
   -            }
   -            else
   -            {
   +            } else   {
                    s_slowIrcFreq = *actualFreq;
                }
            }
   @@ -1372,103 +1306,83 @@
     *
     * return Current MCG mode or error code; See ref mcg_mode_t.
     */
   -mcg_mode_t CLOCK_GetMode(void)
   +mcg_mode_t
   +CLOCK_GetMode(void)
    {
        mcg_mode_t mode = kMCG_ModeError;
   -    uint32_t clkst  = (uint32_t)MCG_S_CLKST_VAL;
   +    uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
        uint32_t irefst = (uint32_t)MCG_S_IREFST_VAL;
   -    uint32_t lp     = (uint32_t)MCG_C2_LP_VAL;
   -    uint32_t pllst  = MCG_S_PLLST_VAL;
   +    uint32_t lp = (uint32_t)MCG_C2_LP_VAL;
   +    uint32_t pllst = MCG_S_PLLST_VAL;
    
        /*------------------------------------------------------------------
                               Mode and Registers
   -    ____________________________________________________________________
   -
   -      Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   -    ____________________________________________________________________
   -
   -      FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -      PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   -    ____________________________________________________________________
   -
   -      PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -    ----------------------------------------------------------------------*/
   -
   -    if (clkst == (uint32_t)kMCG_ClkOutStatFll)
   -    {
   -        if ((uint32_t)kMCG_FllSrcExternal == irefst)
   -        {
   +       ____________________________________________________________________
   +
   +       Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   +       ____________________________________________________________________
   +
   +       FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   +       ____________________________________________________________________
   +
   +       PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       ----------------------------------------------------------------------*/
   +
   +    if (clkst == (uint32_t)kMCG_ClkOutStatFll) {
   +        if ((uint32_t)kMCG_FllSrcExternal == irefst) {
                mode = kMCG_ModeFEE;
   -        }
   -        else
   -        {
   +        } else   {
                mode = kMCG_ModeFEI;
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatInt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatInt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPI;
   -        }
   -        else
   -        {
   +        } else   {
                {
                    mode = kMCG_ModeFBI;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatExt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatExt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPE;
   -        }
   -        else
   -        {
   -            if ((uint32_t)kMCG_PllstPll == pllst)
   -            {
   +        } else   {
   +            if ((uint32_t)kMCG_PllstPll == pllst) {
                    mode = kMCG_ModePBE;
   -            }
   -            else
   -            {
   +            } else   {
                    mode = kMCG_ModeFBE;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatPll)
   -    {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatPll)   {
            {
                mode = kMCG_ModePEE;
            }
   -    }
   -    else
   -    {
   +    } else   {
            /*do nothing*/
        }
    
   @@ -1490,15 +1404,15 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to a frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode)))
   -    {
   +    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1510,8 +1424,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1523,13 +1436,11 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1538,13 +1449,11 @@
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1566,15 +1475,15 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode)))
   -    {
   +    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1586,8 +1495,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1600,45 +1508,37 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
        /* Set DRS and DMX32. */
   -    mcg_c4  = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
   +    mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
        MCG->C4 = mcg_c4;
    
        /* Wait for DRST_DRS update. */
   -    while (MCG->C4 != mcg_c4)
   -    {
   +    while (MCG->C4 != mcg_c4) {
        }
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1661,7 +1561,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1670,9 +1571,7 @@
        mcg_mode_t mode = CLOCK_GetMode();
    
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModeBLPI == mode)))
   -
   -    {
   +          (kMCG_ModeBLPI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1687,8 +1586,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1700,26 +1598,22 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   -    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) {
        }
    
        MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1741,7 +1635,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1749,16 +1644,14 @@
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode)))
   -    {
   +          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
    
        /* Change to FLL mode. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Set LP bit to enable the FLL */
   @@ -1772,8 +1665,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1786,24 +1678,19 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for Reference clock Status bit to clear */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1812,13 +1699,11 @@
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for clock status bits to show clock source is ext ref clk */
   -    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for fll stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1834,11 +1719,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpiMode(void)
   +status_t
   +CLOCK_SetBlpiMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1858,11 +1743,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpeMode(void)
   +status_t
   +CLOCK_SetBlpeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1892,7 +1777,8 @@
     * configuration structure not necessary. In this case, pass in NULL.
     * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
     */
   -status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1907,14 +1793,12 @@
    
        /* Wait for CLKST clock status bits to show clock source is ext ref clk */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* Disable PLL first, then configure PLL. */
        MCG->C6 &= (uint8_t)(~MCG_C6_PLLS_MASK);
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Configure the PLL. */
   @@ -1926,8 +1810,7 @@
        MCG->C6 |= MCG_C6_PLLS_MASK;
    
        /* Wait for PLL mode changed. */
   -    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U) {
        }
    
        return kStatus_Success;
   @@ -1945,12 +1828,12 @@
     *       PRDIV/VDIV are different than in the PBE mode, set them up
     *       in PBE mode and wait. When the clock is stable, switch to PEE mode.
     */
   -status_t CLOCK_SetPeeMode(void)
   +status_t
   +CLOCK_SetPeeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (kMCG_ModePBE != mode)
   -    {
   +    if (kMCG_ModePBE != mode) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1959,8 +1842,7 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
    
        /* Wait for clock status bits to update */
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -1982,11 +1864,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
     */
   -status_t CLOCK_ExternalModeToFbeModeQuick(void)
   +status_t
   +CLOCK_ExternalModeToFbeModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) != 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) != 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1995,14 +1877,12 @@
        MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK);
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
        }
    
        /* Disable PLL. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        return kStatus_Success;
   @@ -2024,11 +1904,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
     */
   -status_t CLOCK_InternalModeToFbiModeQuick(void)
   +status_t
   +CLOCK_InternalModeToFbiModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) == 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) == 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif
   @@ -2037,8 +1917,7 @@
        MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        return kStatus_Success;
   @@ -2059,7 +1938,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
    }
   @@ -2079,8 +1959,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToFeeMode(
   -    mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeeMode(mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2100,15 +1980,15 @@
     * retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
   +status_t
   +CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
    {
        /* If reset mode is FEI mode, set MCGIRCLK and always success. */
        (void)CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
    
        /* If reset mode is not BLPI, first enter FBI mode. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        /* Enter BLPI mode. */
   @@ -2128,7 +2008,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2138,20 +2019,16 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* In FBE now, start to enter BLPE. */
   @@ -2173,7 +2050,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -2183,8 +2061,7 @@
    
        /* Change to use PLL output clock. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -2233,7 +2110,8 @@
     * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
     * function.
     */
   -status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
   +status_t
   +CLOCK_SetMcgConfig(const mcg_config_t *config)
    {
        mcg_mode_t next_mode;
        status_t status = kStatus_Success;
   @@ -2241,11 +2119,9 @@
        mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0;
    
        /* If need to change external clock, MCG_C7[OSCSEL]. */
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel))
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel)) {
            /* If external clock is in use, change to FEI first. */
   -        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -        {
   +        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
                (void)CLOCK_ExternalModeToFbeModeQuick();
                (void)CLOCK_SetFeiMode(config->dmx32, config->drs, NULL);
            }
   @@ -2254,8 +2130,7 @@
        }
    
        /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
   -    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt) {
            MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */
    
            {
   @@ -2268,67 +2143,56 @@
    
        next_mode = CLOCK_GetMode();
    
   -    do
   -    {
   +    do{
            next_mode = mcgModeMatrix[next_mode][config->mcgMode];
    
   -        switch (next_mode)
   -        {
   -            case kMCG_ModeFEI:
   -                status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFEE:
   -                status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFBI:
   -                status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeFBE:
   -                status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeBLPI:
   -                status = CLOCK_SetBlpiMode();
   -                break;
   -            case kMCG_ModeBLPE:
   -                status = CLOCK_SetBlpeMode();
   -                break;
   -            case kMCG_ModePBE:
   -                /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   -                if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode))
   +        switch (next_mode) {
   +        case kMCG_ModeFEI:
   +            status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFEE:
   +            status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFBI:
   +            status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeFBE:
   +            status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeBLPI:
   +            status = CLOCK_SetBlpiMode();
   +            break;
   +        case kMCG_ModeBLPE:
   +            status = CLOCK_SetBlpeMode();
   +            break;
   +        case kMCG_ModePBE:
   +            /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   +            if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) {
                    {
   -                    {
   -                        status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
   -                    }
   +                    status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
                    }
   -                else
   -                {
   -                    MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -                    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -                    {
   -                    }
   +            } else   {
   +                MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   +                while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
                    }
   -                break;
   -            case kMCG_ModePEE:
   -                status = CLOCK_SetPeeMode();
   -                break;
   -            default:
   -                assert(false);
   -                break;
   -        }
   -        if (kStatus_Success != status)
   -        {
   +            }
                break;
   +        case kMCG_ModePEE:
   +            status = CLOCK_SetPeeMode();
   +            break;
   +        default:
   +            assert(false);
   +            break;
   +        }
   +        if (kStatus_Success != status) {
   +            break;
            }
        } while (next_mode != config->mcgMode);
    
   -    if (status == kStatus_Success)
   -    {
   -        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U)
   -        {
   +    if (status == kStatus_Success) {
   +        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U) {
                CLOCK_EnablePll0(&config->pll0Config);
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_flash.c
   <details>
   
   ```diff
   @@ -6,7 +6,7 @@
     * to you under the Apache License, Version 2.0 (the
     * "License"); you may not use this file except in compliance
     * with the License.  You may obtain a copy of the License at
   -*
   + *
     *  http://www.apache.org/licenses/LICENSE-2.0
     *
     * Unless required by applicable law or agreed to in writing,
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_lpuart.c
   <details>
   
   ```diff
   @@ -59,10 +59,10 @@
        hal_uart_tx_char u_tx_func;
        hal_uart_tx_done u_tx_done;
        void *u_func_arg;
   -    uint8_t u_configured:1;
   -    uint8_t u_open:1;
   -    uint8_t u_tx_started:1;
   -    uint8_t u_rx_stall:1;
   +    uint8_t u_configured : 1;
   +    uint8_t u_open : 1;
   +    uint8_t u_tx_started : 1;
   +    uint8_t u_rx_stall : 1;
        struct uart_ring ur_tx;
        uint8_t tx_buffer[TX_BUF_SZ];
        struct uart_ring ur_rx;
   @@ -465,8 +465,7 @@
                uarts[port].ur_rx.ur_head = 0;
                uarts[port].ur_rx.ur_tail = 0;
                uarts[port].u_configured = 1;
   -        }
   -        else {
   +        } else   {
                uarts[port].u_configured = 0;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_qspi.c
   <details>
   
   ```diff
   @@ -84,7 +84,8 @@
        [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
    
        /* Match MISRA rule */
   -    [63] = 0};
   +    [63] = 0
   +};
    
    qspi_flash_config_t g_qspi_flash_cfg = {
        .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
   @@ -109,15 +110,12 @@
    {
        uint32_t val = 0;
        /* Check WIP bit */
   -    do
   -    {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +    do{
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
            QSPI_ExecuteIPCommand(QuadSPI0, 12U);
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            val = QuadSPI0->RBDR[0];
            /* Clear ARDB area */
   @@ -128,19 +126,17 @@
    static void
    cmd_write_enable()
    {
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ExecuteIPCommand(QuadSPI0, 4U);
    }
    
    static void
   -read_page(uint32_t address, uint32_t* dst)
   +read_page(uint32_t address, uint32_t * dst)
    {
        int i;
   -    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
   -    {
   -        dst[i] = ((uint32_t*)address)[i];
   +    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++) {
   +        dst[i] = ((uint32_t *)address)[i];
        }
    }
    
   @@ -172,15 +168,13 @@
    {
        uint32_t leftLongWords = 0;
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
    
        QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
        cmd_write_enable();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
    
        /* First write some data into TXFIFO to prevent from underrun */
   @@ -196,8 +190,7 @@
    
        /* Wait until flash finished program */
        check_if_finished();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess)) {
        }
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   @@ -221,7 +214,7 @@
    
        npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        while (npages) {
   -        write_page(address, (uint32_t*) src);
   +        write_page(address, (uint32_t *) src);
            npages--;
            address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        }
   @@ -230,13 +223,12 @@
    
    static int
    nxp_qspi_erase_sector(const struct hal_flash *dev,
   -                         uint32_t sector_address)
   +                      uint32_t sector_address)
    {
        sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
        sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
        QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
   @@ -263,8 +255,7 @@
        nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
        while (nsects) {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
            QSPI_SetIPCommandAddress(QuadSPI0, address);
   @@ -273,7 +264,7 @@
            check_if_finished();
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
   -    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   +        (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
            QSPI_ClearCache(QuadSPI0);
    #endif
            nsects--;
   @@ -300,8 +291,7 @@
    {
        uint32_t val[4] = {0x40U, 0, 0, 0};
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
    
   ```
   
   </details>


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[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot commented on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-772981003


   
   <!-- license-bot -->
   
   ## RAT Report (2021-02-04 02:38:07)
   
   ## New files with unknown licenses
   
   * <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c">hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c</a>
   * <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c</a>
   
   ## 122 new files were excluded from check (.rat-excludes)
   
   <details>
     <summary>Detailed analysis</summary>
   
   ## New files in this PR
   
   | License | File |
   |---------|------|
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/syscfg.yml">hw/mcu/nxp/kinetis/syscfg.yml</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/MK64F12/syscfg.yml">hw/mcu/nxp/kinetis/MK64F12/syscfg.yml</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c">hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/include/hal_lpuart_nxp.h">hw/mcu/nxp/kinetis/include/hal_lpuart_nxp.h</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/include/mcu/kinetis_common.h">hw/mcu/nxp/kinetis/include/mcu/kinetis_common.h</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/include/mcu/kinetis_hal.h">hw/mcu/nxp/kinetis/include/mcu/kinetis_hal.h</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/src/hal_flash.c">hw/mcu/nxp/kinetis/src/hal_flash.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/src/hal_gpio.c">hw/mcu/nxp/kinetis/src/hal_gpio.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/src/hal_i2c.c">hw/mcu/nxp/kinetis/src/hal_i2c.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/src/hal_lpuart.c">hw/mcu/nxp/kinetis/src/hal_lpuart.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/src/hal_qspi.c">hw/mcu/nxp/kinetis/src/hal_qspi.c</a> |
   | AL     | <a href="https://github.com/apache/mynewt-core/blob/f6f51c9b0beb48dbf993fb0a1895d4ffdc4a2ec7/hw/mcu/nxp/kinetis/src/hal_spi.c">hw/mcu/nxp/kinetis/src/hal_spi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/COPYING-BSD-3</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_adc16.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cache.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmp.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_cmt.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_common.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dac.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dmamux.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_enet.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ewm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flash.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexbus.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexcan.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_camera_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2c_master.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_i2s_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_spi_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_flexio_uart_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_adapter.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_cache.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_controller.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_features.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flash.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_flexnvm.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftfx_utilities.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ftm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_gpio.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_i2c_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lmem_cache.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lptmr.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_lpuart_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_dpa.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_ltc_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pdb.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pit.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_pmc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_port.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_qspi_edma.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rcm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_rtc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sai_edma.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdhc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sdramc.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sim.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_emvsim.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_emvsim.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smartcard_phy_tda8035.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_smc.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_sysmpu.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tpm.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_trng.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_tsi_v4.h</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_uart.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_vref.c</a> |
   | ?????  | <a href="https://github.com/apache/mynewt-core/blob/acb97e0e64c79d41dea861c139e3983c20982553/hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c">hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_wdog.c</a> |
   </details>
   
   


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[GitHub] [mynewt-core] utzig commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
utzig commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570630077



##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,408 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type *dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *user_data)
+{
+    struct nxp_hal_i2c *i2c = userData;

Review comment:
       I belive you also have to fix this one! :-)




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[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot removed a comment on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-773567186


   
   <!-- style-bot -->
   
   ## Style check summary
   
   ### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
   
   
   #### hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c
   <details>
   
   ```diff
   @@ -187,15 +187,15 @@
     ******************************************************************************/
    
    #ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
   -static void CLOCK_FllStableDelay(void)
   +static void
   +CLOCK_FllStableDelay(void)
    {
        /*
           Should wait at least 1ms. Because in these modes, the core clock is 100MHz
           at most, so this function could obtain the 1ms delay.
         */
        volatile uint32_t i = 30000U;
   -    while (0U != (i--))
   -    {
   +    while (0U != (i--)) {
            __NOP();
        }
    }
   @@ -207,34 +207,35 @@
    extern void CLOCK_FllStableDelay(void);
    #endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */
    
   -static uint32_t CLOCK_GetMcgExtClkFreq(void)
   +static uint32_t
   +CLOCK_GetMcgExtClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (MCG_C7_OSCSEL_VAL)
   -    {
   -        case 0U:
   -            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   -            assert(0U != g_xtal0Freq);
   -            freq = g_xtal0Freq;
   -            break;
   -        case 1U:
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(0U != g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 2U:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (MCG_C7_OSCSEL_VAL) {
   +    case 0U:
   +        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   +        assert(0U != g_xtal0Freq);
   +        freq = g_xtal0Freq;
   +        break;
   +    case 1U:
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(0U != g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 2U:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllExtRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllExtRefClkFreq(void)
    {
        /* FllExtRef = McgExtRef / FllExtRefDiv */
        uint8_t frdiv;
   @@ -246,54 +247,50 @@
        frdiv = MCG_C1_FRDIV_VAL;
        freq >>= frdiv;
    
   -    range  = MCG_C2_RANGE_VAL;
   +    range = MCG_C2_RANGE_VAL;
        oscsel = MCG_C7_OSCSEL_VAL;
    
        /*
           When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536.
           1. MCG_C7[OSCSEL] selects IRC48M.
           2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0.
   -    */
   -    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel))
   -    {
   -        switch (frdiv)
   -        {
   -            case 0:
   -            case 1:
   -            case 2:
   -            case 3:
   -            case 4:
   -            case 5:
   -                freq >>= 5u;
   -                break;
   -            case 6:
   -                /* 64*20=1280 */
   -                freq /= 20u;
   -                break;
   -            case 7:
   -                /* 128*12=1536 */
   -                freq /= 12u;
   -                break;
   -            default:
   -                freq = 0u;
   -                break;
   +     */
   +    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel)) {
   +        switch (frdiv) {
   +        case 0:
   +        case 1:
   +        case 2:
   +        case 3:
   +        case 4:
   +        case 5:
   +            freq >>= 5u;
   +            break;
   +        case 6:
   +            /* 64*20=1280 */
   +            freq /= 20u;
   +            break;
   +        case 7:
   +            /* 128*12=1536 */
   +            freq /= 12u;
   +            break;
   +        default:
   +            freq = 0u;
   +            break;
            }
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetInternalRefClkSelectFreq(void)
   +static uint32_t
   +CLOCK_GetInternalRefClkSelectFreq(void)
    {
        uint32_t freq;
    
   -    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL)
   -    {
   +    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL) {
            /* Slow internal reference clock selected*/
            freq = s_slowIrcFreq;
   -    }
   -    else
   -    {
   +    } else   {
            /* Fast internal reference clock selected*/
            freq = s_fastIrcFreq >> MCG_SC_FCRDIV_VAL;
        }
   @@ -301,44 +298,40 @@
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If use external reference clock. */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            freq = CLOCK_GetFllExtRefClkFreq();
        }
        /* If use internal reference clock. */
   -    else
   -    {
   +    else {
            freq = s_slowIrcFreq;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetPll0RefFreq(void)
   +static uint32_t
   +CLOCK_GetPll0RefFreq(void)
    {
        /* MCG external reference clock. */
        return CLOCK_GetMcgExtClkFreq();
    }
    
   -static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
   +static uint8_t
   +CLOCK_GetOscRangeFromFreq(uint32_t freq)
    {
        uint8_t range;
    
   -    if (freq <= 39063U)
   -    {
   +    if (freq <= 39063U) {
            range = 0U;
   -    }
   -    else if (freq <= 8000000U)
   -    {
   +    } else if (freq <= 8000000U)   {
            range = 1U;
   -    }
   -    else
   -    {
   +    } else   {
            range = 2U;
        }
    
   @@ -350,17 +343,15 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetOsc0ErClkFreq(void)
   +uint32_t
   +CLOCK_GetOsc0ErClkFreq(void)
    {
        uint32_t freq;
   -    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)
   -    {
   +    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U) {
            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
            assert(g_xtal0Freq);
            freq = g_xtal0Freq;
   -    }
   -    else
   -    {
   +    } else   {
            freq = 0U;
        }
    
   @@ -372,26 +363,26 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetEr32kClkFreq(void)
   +uint32_t
   +CLOCK_GetEr32kClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT1_OSC32KSEL_VAL)
   -    {
   -        case 0U: /* OSC 32k clock  */
   -            freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   -            break;
   -        case 2U: /* RTC 32k clock  */
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 3U: /* LPO clock      */
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT1_OSC32KSEL_VAL) {
   +    case 0U:     /* OSC 32k clock  */
   +        freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   +        break;
   +    case 2U:     /* RTC 32k clock  */
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 3U:     /* LPO clock      */
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
        return freq;
    }
   @@ -401,24 +392,24 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPllFllSelClkFreq(void)
   +uint32_t
   +CLOCK_GetPllFllSelClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT2_PLLFLLSEL_VAL)
   -    {
   -        case 0U: /* FLL. */
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case 1U: /* PLL. */
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case 3U: /* MCG IRC48M. */
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT2_PLLFLLSEL_VAL) {
   +    case 0U:     /* FLL. */
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case 1U:     /* PLL. */
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case 3U:     /* MCG IRC48M. */
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -429,7 +420,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPlatClkFreq(void)
   +uint32_t
   +CLOCK_GetPlatClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -439,7 +431,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlashClkFreq(void)
   +uint32_t
   +CLOCK_GetFlashClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
    }
   @@ -449,7 +442,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlexBusClkFreq(void)
   +uint32_t
   +CLOCK_GetFlexBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
    }
   @@ -459,7 +453,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetBusClkFreq(void)
   +uint32_t
   +CLOCK_GetBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
    }
   @@ -469,7 +464,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetCoreSysClkFreq(void)
   +uint32_t
   +CLOCK_GetCoreSysClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -484,55 +480,55 @@
     * param clockName Clock names defined in clock_name_t
     * return Clock frequency value in Hertz
     */
   -uint32_t CLOCK_GetFreq(clock_name_t clockName)
   +uint32_t
   +CLOCK_GetFreq(clock_name_t clockName)
    {
        uint32_t freq;
    
   -    switch (clockName)
   -    {
   -        case kCLOCK_CoreSysClk:
   -        case kCLOCK_PlatClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   -            break;
   -        case kCLOCK_BusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlexBusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlashClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   -            break;
   -        case kCLOCK_PllFllSelClk:
   -            freq = CLOCK_GetPllFllSelClkFreq();
   -            break;
   -        case kCLOCK_Er32kClk:
   -            freq = CLOCK_GetEr32kClkFreq();
   -            break;
   -        case kCLOCK_Osc0ErClk:
   -            freq = CLOCK_GetOsc0ErClkFreq();
   -            break;
   -        case kCLOCK_McgFixedFreqClk:
   -            freq = CLOCK_GetFixedFreqClkFreq();
   -            break;
   -        case kCLOCK_McgInternalRefClk:
   -            freq = CLOCK_GetInternalRefClkFreq();
   -            break;
   -        case kCLOCK_McgFllClk:
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case kCLOCK_McgPll0Clk:
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case kCLOCK_McgIrc48MClk:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        case kCLOCK_LpoClk:
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (clockName) {
   +    case kCLOCK_CoreSysClk:
   +    case kCLOCK_PlatClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   +        break;
   +    case kCLOCK_BusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlexBusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlashClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   +        break;
   +    case kCLOCK_PllFllSelClk:
   +        freq = CLOCK_GetPllFllSelClkFreq();
   +        break;
   +    case kCLOCK_Er32kClk:
   +        freq = CLOCK_GetEr32kClkFreq();
   +        break;
   +    case kCLOCK_Osc0ErClk:
   +        freq = CLOCK_GetOsc0ErClkFreq();
   +        break;
   +    case kCLOCK_McgFixedFreqClk:
   +        freq = CLOCK_GetFixedFreqClkFreq();
   +        break;
   +    case kCLOCK_McgInternalRefClk:
   +        freq = CLOCK_GetInternalRefClkFreq();
   +        break;
   +    case kCLOCK_McgFllClk:
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case kCLOCK_McgPll0Clk:
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case kCLOCK_McgIrc48MClk:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    case kCLOCK_LpoClk:
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -545,7 +541,8 @@
     *
     * param config Pointer to the configure structure.
     */
   -void CLOCK_SetSimConfig(sim_clock_config_t const *config)
   +void
   +CLOCK_SetSimConfig(sim_clock_config_t const *config)
    {
        SIM->CLKDIV1 = config->clkdiv1;
        CLOCK_SetPllFllSelClock(config->pllFllSel);
   @@ -559,35 +556,32 @@
     * retval true The clock is set successfully.
     * retval false The clock source is invalid to get proper USB FS clock.
     */
   -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
   +bool
   +CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
    {
        bool ret = true;
    
        CLOCK_DisableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcExt == src)
   -    {
   +    if (kCLOCK_UsbSrcExt == src) {
            SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
   -    }
   -    else
   -    {
   -        switch (freq)
   -        {
   -            case 120000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 96000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            case 72000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 48000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            default:
   -                ret = false;
   -                break;
   +    } else   {
   +        switch (freq) {
   +        case 120000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 96000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        case 72000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 48000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        default:
   +            ret = false;
   +            break;
            }
    
            SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src);
   @@ -595,8 +589,7 @@
    
        CLOCK_EnableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcIrc48M == src)
   -    {
   +    if (kCLOCK_UsbSrcIrc48M == src) {
            USB0->CLK_RECOVER_IRC_EN = 0x03U;
            USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
        }
   @@ -611,28 +604,28 @@
     *
     * return The frequency of MCGOUTCLK.
     */
   -uint32_t CLOCK_GetOutClkFreq(void)
   +uint32_t
   +CLOCK_GetOutClkFreq(void)
    {
        uint32_t mcgoutclk;
        uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
    
   -    switch (clkst)
   -    {
   -        case (uint32_t)kMCG_ClkOutStatPll:
   -            mcgoutclk = CLOCK_GetPll0Freq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatFll:
   -            mcgoutclk = CLOCK_GetFllFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatInt:
   -            mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatExt:
   -            mcgoutclk = CLOCK_GetMcgExtClkFreq();
   -            break;
   -        default:
   -            mcgoutclk = 0U;
   -            break;
   +    switch (clkst) {
   +    case (uint32_t)kMCG_ClkOutStatPll:
   +        mcgoutclk = CLOCK_GetPll0Freq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatFll:
   +        mcgoutclk = CLOCK_GetFllFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatInt:
   +        mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatExt:
   +        mcgoutclk = CLOCK_GetMcgExtClkFreq();
   +        break;
   +    default:
   +        mcgoutclk = 0U;
   +        break;
        }
    
        return mcgoutclk;
   @@ -647,7 +640,8 @@
     *
     * return The frequency of MCGFLLCLK.
     */
   -uint32_t CLOCK_GetFllFreq(void)
   +uint32_t
   +CLOCK_GetFllFreq(void)
    {
        static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}};
    
   @@ -656,23 +650,17 @@
        uint32_t ret;
    
        /* If FLL is not enabled currently, then return 0U. */
   -    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U)))
   -    {
   +    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) {
            ret = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            /* Get FLL reference clock frequency. */
            freq = CLOCK_GetFllRefClkFreq();
   -        if (0U == freq)
   -        {
   +        if (0U == freq) {
                ret = freq;
   -        }
   -        else
   -        {
   -            drs   = MCG_C4_DRST_DRS_VAL;
   +        } else   {
   +            drs = MCG_C4_DRST_DRS_VAL;
                dmx32 = MCG_C4_DMX32_VAL;
   -            ret   = freq * fllFactorTable[drs][dmx32];
   +            ret = freq * fllFactorTable[drs][dmx32];
            }
        }
    
   @@ -687,17 +675,15 @@
     *
     * return The frequency of MCGIRCLK.
     */
   -uint32_t CLOCK_GetInternalRefClkFreq(void)
   +uint32_t
   +CLOCK_GetInternalRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If MCGIRCLK is gated. */
   -    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK))
   -    {
   +    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            freq = CLOCK_GetInternalRefClkSelectFreq();
        }
    
   @@ -712,18 +698,16 @@
     *
     * return The frequency of MCGFFCLK.
     */
   -uint32_t CLOCK_GetFixedFreqClkFreq(void)
   +uint32_t
   +CLOCK_GetFixedFreqClkFreq(void)
    {
        uint32_t freq = CLOCK_GetFllRefClkFreq();
        uint32_t ret;
    
        /* MCGFFCLK must be no more than MCGOUTCLK/8. */
   -    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq))
   -    {
   +    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq)) {
            ret = freq;
   -    }
   -    else
   -    {
   +    } else   {
            ret = 0U;
        }
    
   @@ -738,7 +722,8 @@
     *
     * return The frequency of MCGPLL0CLK.
     */
   -uint32_t CLOCK_GetPll0Freq(void)
   +uint32_t
   +CLOCK_GetPll0Freq(void)
    {
        uint32_t mcgpll0clk;
        uint32_t freq;
   @@ -746,12 +731,9 @@
        uint8_t mcgpll0prdiv;
        uint8_t mcgpll0vdiv;
        /* If PLL0 is not enabled, return 0. */
   -    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            mcgpll0clk = CLOCK_GetPll0RefFreq();
    
            /*
   @@ -783,36 +765,31 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success External reference clock set successfully.
     */
   -status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
    {
        bool needDelay;
        uint32_t i;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */
   -    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK)))
   -    {
   +    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) {
            return kStatus_MCG_SourceUsed;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
    
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel)
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel) {
            /* If change OSCSEL, need to delay, ERR009878. */
            needDelay = true;
   -    }
   -    else
   -    {
   +    } else   {
            needDelay = false;
        }
    
        MCG->C7 = (uint8_t)(MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
   -    if (needDelay)
   -    {
   +    if (needDelay) {
            /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
            i = 1500U;
   -        while (0U != (i--))
   -        {
   +        while (0U != (i--)) {
                __NOP();
            }
        }
   @@ -836,34 +813,30 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success MCGIRCLK configuration finished successfully.
     */
   -status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
   +status_t
   +CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
    {
        uint32_t mcgOutClkState = (uint32_t)MCG_S_CLKST_VAL;
   -    mcg_irc_mode_t curIrcs  = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   -    uint8_t curFcrdiv       = MCG_SC_FCRDIV_VAL;
   +    mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   +    uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If MCGIRCLK is used as system clock source. */
   -    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState)
   -    {
   +    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState) {
            /* If need to change MCGIRCLK source or driver, return error. */
   -        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs))
   -        {
   +        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) {
                return kStatus_MCG_SourceUsed;
            }
        }
    #endif
    
        /* If need to update the FCRDIV. */
   -    if (fcrdiv != curFcrdiv)
   -    {
   +    if (fcrdiv != curFcrdiv) {
            /* If fast IRC is in use currently, change to slow IRC. */
            if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) &&
   -            (kMCG_IrcFast == curIrcs))
   -        {
   +            (kMCG_IrcFast == curIrcs)) {
                MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
   -            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow)
   -            {
   +            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow) {
                }
            }
            /* Update FCRDIV. */
   @@ -876,10 +849,8 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode);
    
        /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
   -    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable)))
   -    {
   -        while (MCG_S_IRCST_VAL != (uint8_t)ircs)
   -        {
   +    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable))) {
   +        while (MCG_S_IRCST_VAL != (uint8_t)ircs) {
            }
        }
    
   @@ -901,7 +872,8 @@
     * param vdiv       VDIV value to generate desired PLL frequency.
     * return Closest frequency match that the PLL was able generate.
     */
   -uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
   +uint32_t
   +CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
    {
        uint8_t ret_prdiv;               /* PRDIV to return. */
        uint8_t ret_vdiv;                /* VDIV to return.  */
   @@ -910,7 +882,7 @@
        uint8_t prdiv_cur;               /* PRDIV value for iteration.    */
        uint8_t vdiv_cur;                /* VDIV value for iteration.     */
        uint32_t ret_freq = 0U;          /* PLL output frequency to return. */
   -    uint32_t diff     = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */
   +    uint32_t diff = 0xFFFFFFFFU;     /* Difference between desireFreq and return frequency. */
        uint32_t ref_div;                /* Reference frequency after PRDIV. */
    
        /*
   @@ -929,8 +901,7 @@
        /* Reference frequency is out of range. */
        if ((refFreq < (uint32_t)FSL_FEATURE_MCG_PLL_REF_MIN) ||
            (refFreq > ((uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX *
   -                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE))))
   -    {
   +                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) {
            return 0U;
        }
    
   @@ -940,62 +911,52 @@
            (uint8_t)((refFreq + (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX);
    
        /* PRDIV traversal. */
   -    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--)
   -    {
   +    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) {
            /* Reference frequency after PRDIV. */
            ref_div = refFreq / prdiv_cur;
    
            vdiv_cur = (uint8_t)(desireFreq / ref_div);
    
            if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) ||
   -            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                /* No VDIV is available with this PRDIV. */
                continue;
            }
    
            ret_freq = vdiv_cur * ref_div;
    
   -        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE)
   -        {
   -            if (ret_freq == desireFreq) /* If desire frequency is got. */
   -            {
   +        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) {
   +            if (ret_freq == desireFreq) { /* If desire frequency is got. */
                    *prdiv = prdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -                *vdiv  = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +                *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
                    return ret_freq;
                }
                /* New PRDIV/VDIV is closer. */
   -            if (diff > desireFreq - ret_freq)
   -            {
   -                diff      = desireFreq - ret_freq;
   +            if (diff > desireFreq - ret_freq) {
   +                diff = desireFreq - ret_freq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
            vdiv_cur++;
   -        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                ret_freq += ref_div;
                /* New PRDIV/VDIV is closer. */
   -            if (diff > ret_freq - desireFreq)
   -            {
   -                diff      = ret_freq - desireFreq;
   +            if (diff > ret_freq - desireFreq) {
   +                diff = ret_freq - desireFreq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
        }
    
   -    if (0xFFFFFFFFU != diff)
   -    {
   +    if (0xFFFFFFFFU != diff) {
            /* PRDIV/VDIV found. */
   -        *prdiv   = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -        *vdiv    = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +        *prdiv = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   +        *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
            ret_freq = (refFreq / ret_prdiv) * ret_vdiv;
            return ret_freq;
   -    }
   -    else
   -    {
   +    } else   {
            /* No proper PRDIV/VDIV found. */
            return 0U;
        }
   @@ -1012,7 +973,8 @@
     *
     * param config Pointer to the configuration structure.
     */
   -void CLOCK_EnablePll0(mcg_pll_config_t const *config)
   +void
   +CLOCK_EnablePll0(mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1027,8 +989,7 @@
        MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode);
    
        /* Wait for PLL lock. */
   -    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
        }
    }
    
   @@ -1039,23 +1000,18 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
    {
        /* Clear the previous flag, MCG_SC[LOCS0]. */
        MCG->SC &= ~(uint8_t)MCG_SC_ATMF_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= ~(uint8_t)MCG_C6_CME0_MASK;
   -    }
   -    else
   -    {
   -        if (kMCG_MonitorInt == mode)
   -        {
   +    } else   {
   +        if (kMCG_MonitorInt == mode) {
                MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK;
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C2 |= MCG_C2_LOCRE0_MASK;
            }
            MCG->C6 |= MCG_C6_CME0_MASK;
   @@ -1069,16 +1025,15 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8 = MCG->C8;
    
        mcg_c8 &= ~(uint8_t)(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK);
    
   -    if (kMCG_MonitorNone != mode)
   -    {
   -        if (kMCG_MonitorReset == mode)
   -        {
   +    if (kMCG_MonitorNone != mode) {
   +        if (kMCG_MonitorReset == mode) {
                mcg_c8 |= MCG_C8_LOCRE1_MASK;
            }
            mcg_c8 |= MCG_C8_CME1_MASK;
   @@ -1093,29 +1048,24 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8;
    
        /* Clear previous flag. */
        MCG->S = MCG_S_LOLS0_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= (uint8_t)(~MCG_C6_LOLIE0_MASK);
   -    }
   -    else
   -    {
   +    } else   {
            mcg_c8 = MCG->C8;
    
            mcg_c8 &= (uint8_t)(~MCG_C8_LOCS1_MASK);
    
   -        if (kMCG_MonitorInt == mode)
   -        {
   +        if (kMCG_MonitorInt == mode) {
                mcg_c8 &= (uint8_t)(~MCG_C8_LOLRE_MASK);
   -        }
   -        else
   -        {
   +        } else   {
                mcg_c8 |= MCG_C8_LOLRE_MASK;
            }
            MCG->C8 = mcg_c8;
   @@ -1149,29 +1099,25 @@
     *
     * return  Logical OR value of the ref _mcg_status_flags_t.
     */
   -uint32_t CLOCK_GetStatusFlags(void)
   -{
   -    uint32_t ret  = 0U;
   +uint32_t
   +CLOCK_GetStatusFlags(void)
   +{
   +    uint32_t ret = 0U;
        uint8_t mcg_s = MCG->S;
    
   -    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U)
   -    {
   +    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0LostFlag;
        }
   -    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0InitFlag;
        }
   -    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK))
   -    {
   +    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK)) {
            ret |= (uint32_t)kMCG_RtcOscLostFlag;
        }
   -    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LostFlag;
        }
   -    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LockFlag;
        }
        return ret;
   @@ -1193,21 +1139,19 @@
     * param mask The status flags to clear. This is a logical OR of members of the
     *             enumeration ref _mcg_status_flags_t.
     */
   -void CLOCK_ClearStatusFlags(uint32_t mask)
   +void
   +CLOCK_ClearStatusFlags(uint32_t mask)
    {
        uint8_t reg;
    
   -    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL) {
            MCG->SC &= (uint8_t)(~MCG_SC_ATMF_MASK);
        }
   -    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag))
   -    {
   -        reg     = MCG->C8;
   +    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag)) {
   +        reg = MCG->C8;
            MCG->C8 = reg;
        }
   -    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL) {
            MCG->S = MCG_S_LOLS0_MASK;
        }
    }
   @@ -1219,7 +1163,8 @@
     *
     * param  config Pointer to the OSC0 configuration structure.
     */
   -void CLOCK_InitOsc0(osc_config_t const *config)
   +void
   +CLOCK_InitOsc0(osc_config_t const *config)
    {
        uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq);
    
   @@ -1228,11 +1173,9 @@
        MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode);
        OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
    
   -    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U))
   -    {
   +    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)) {
            /* Wait for stable. */
   -        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -        {
   +        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
            }
        }
    }
   @@ -1242,7 +1185,8 @@
     *
     * This function deinitializes the OSC0.
     */
   -void CLOCK_DeinitOsc0(void)
   +void
   +CLOCK_DeinitOsc0(void)
    {
        OSC0->CR = 0U;
        MCG->C2 &= ~(uint8_t)OSC_MODE_MASK;
   @@ -1253,7 +1197,8 @@
     *
     * param freq The Slow IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetSlowIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetSlowIrcFreq(uint32_t freq)
    {
        s_slowIrcFreq = freq;
    }
   @@ -1263,7 +1208,8 @@
     *
     * param freq The Fast IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetFastIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetFastIrcFreq(uint32_t freq)
    {
        s_fastIrcFreq = freq;
    }
   @@ -1286,7 +1232,8 @@
     * retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
     * retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
     */
   -status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
   +status_t
   +CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
    {
        uint32_t multi; /* extFreq / desireFreq */
        uint32_t actv;  /* Auto trim value. */
   @@ -1299,30 +1246,24 @@
            {TRIM_FIRC_MIN, TRIM_FIRC_MAX}  /* Fast IRC. */
        };
    
   -    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN))
   -    {
   +    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) {
            status = kStatus_MCG_AtmBusClockInvalid;
        }
        /* Check desired frequency range. */
   -    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1]))
   -    {
   +    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) {
            status = kStatus_MCG_AtmDesiredFreqInvalid;
        }
        /*
           Make sure internal reference clock is not used to generate bus clock.
           Here only need to check (MCG_S_IREFST == 1).
         */
   -    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK))
   -    {
   +    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) {
            status = kStatus_MCG_AtmIrcUsed;
   -    }
   -    else
   -    {
   +    } else   {
            multi = extFreq / desireFreq;
   -        actv  = multi * 21U;
   -
   -        if (kMCG_AtmSel4m == atms)
   -        {
   +        actv = multi * 21U;
   +
   +        if (kMCG_AtmSel4m == atms) {
                actv *= 128U;
            }
    
   @@ -1336,27 +1277,20 @@
            MCG->SC = (mcg_sc | MCG_SC_ATME_MASK);
    
            /* Wait for MCG finished. */
   -        while (0U != (MCG->SC & MCG_SC_ATME_MASK))
   -        {
   +        while (0U != (MCG->SC & MCG_SC_ATME_MASK)) {
            }
    
            /* Error occurs? */
   -        if (0U != (MCG->SC & MCG_SC_ATMF_MASK))
   -        {
   +        if (0U != (MCG->SC & MCG_SC_ATMF_MASK)) {
                /* Clear the failed flag. */
                MCG->SC = mcg_sc;
   -            status  = kStatus_MCG_AtmHardwareFail;
   -        }
   -        else
   -        {
   +            status = kStatus_MCG_AtmHardwareFail;
   +        } else   {
                *actualFreq = extFreq / multi;
    
   -            if (kMCG_AtmSel4m == atms)
   -            {
   +            if (kMCG_AtmSel4m == atms) {
                    s_fastIrcFreq = *actualFreq;
   -            }
   -            else
   -            {
   +            } else   {
                    s_slowIrcFreq = *actualFreq;
                }
            }
   @@ -1372,103 +1306,83 @@
     *
     * return Current MCG mode or error code; See ref mcg_mode_t.
     */
   -mcg_mode_t CLOCK_GetMode(void)
   +mcg_mode_t
   +CLOCK_GetMode(void)
    {
        mcg_mode_t mode = kMCG_ModeError;
   -    uint32_t clkst  = (uint32_t)MCG_S_CLKST_VAL;
   +    uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
        uint32_t irefst = (uint32_t)MCG_S_IREFST_VAL;
   -    uint32_t lp     = (uint32_t)MCG_C2_LP_VAL;
   -    uint32_t pllst  = MCG_S_PLLST_VAL;
   +    uint32_t lp = (uint32_t)MCG_C2_LP_VAL;
   +    uint32_t pllst = MCG_S_PLLST_VAL;
    
        /*------------------------------------------------------------------
                               Mode and Registers
   -    ____________________________________________________________________
   -
   -      Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   -    ____________________________________________________________________
   -
   -      FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -      PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   -    ____________________________________________________________________
   -
   -      PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -    ----------------------------------------------------------------------*/
   -
   -    if (clkst == (uint32_t)kMCG_ClkOutStatFll)
   -    {
   -        if ((uint32_t)kMCG_FllSrcExternal == irefst)
   -        {
   +       ____________________________________________________________________
   +
   +       Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   +       ____________________________________________________________________
   +
   +       FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   +       ____________________________________________________________________
   +
   +       PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       ----------------------------------------------------------------------*/
   +
   +    if (clkst == (uint32_t)kMCG_ClkOutStatFll) {
   +        if ((uint32_t)kMCG_FllSrcExternal == irefst) {
                mode = kMCG_ModeFEE;
   -        }
   -        else
   -        {
   +        } else   {
                mode = kMCG_ModeFEI;
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatInt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatInt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPI;
   -        }
   -        else
   -        {
   +        } else   {
                {
                    mode = kMCG_ModeFBI;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatExt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatExt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPE;
   -        }
   -        else
   -        {
   -            if ((uint32_t)kMCG_PllstPll == pllst)
   -            {
   +        } else   {
   +            if ((uint32_t)kMCG_PllstPll == pllst) {
                    mode = kMCG_ModePBE;
   -            }
   -            else
   -            {
   +            } else   {
                    mode = kMCG_ModeFBE;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatPll)
   -    {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatPll)   {
            {
                mode = kMCG_ModePEE;
            }
   -    }
   -    else
   -    {
   +    } else   {
            /*do nothing*/
        }
    
   @@ -1490,15 +1404,15 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to a frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode)))
   -    {
   +    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1510,8 +1424,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1523,13 +1436,11 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1538,13 +1449,11 @@
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1566,15 +1475,15 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode)))
   -    {
   +    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1586,8 +1495,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1600,45 +1508,37 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
        /* Set DRS and DMX32. */
   -    mcg_c4  = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
   +    mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
        MCG->C4 = mcg_c4;
    
        /* Wait for DRST_DRS update. */
   -    while (MCG->C4 != mcg_c4)
   -    {
   +    while (MCG->C4 != mcg_c4) {
        }
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1661,7 +1561,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1670,9 +1571,7 @@
        mcg_mode_t mode = CLOCK_GetMode();
    
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModeBLPI == mode)))
   -
   -    {
   +          (kMCG_ModeBLPI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1687,8 +1586,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1700,26 +1598,22 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   -    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) {
        }
    
        MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1741,7 +1635,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1749,16 +1644,14 @@
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode)))
   -    {
   +          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
    
        /* Change to FLL mode. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Set LP bit to enable the FLL */
   @@ -1772,8 +1665,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1786,24 +1678,19 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for Reference clock Status bit to clear */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1812,13 +1699,11 @@
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for clock status bits to show clock source is ext ref clk */
   -    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for fll stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1834,11 +1719,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpiMode(void)
   +status_t
   +CLOCK_SetBlpiMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1858,11 +1743,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpeMode(void)
   +status_t
   +CLOCK_SetBlpeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1892,7 +1777,8 @@
     * configuration structure not necessary. In this case, pass in NULL.
     * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
     */
   -status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1907,14 +1793,12 @@
    
        /* Wait for CLKST clock status bits to show clock source is ext ref clk */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* Disable PLL first, then configure PLL. */
        MCG->C6 &= (uint8_t)(~MCG_C6_PLLS_MASK);
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Configure the PLL. */
   @@ -1926,8 +1810,7 @@
        MCG->C6 |= MCG_C6_PLLS_MASK;
    
        /* Wait for PLL mode changed. */
   -    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U) {
        }
    
        return kStatus_Success;
   @@ -1945,12 +1828,12 @@
     *       PRDIV/VDIV are different than in the PBE mode, set them up
     *       in PBE mode and wait. When the clock is stable, switch to PEE mode.
     */
   -status_t CLOCK_SetPeeMode(void)
   +status_t
   +CLOCK_SetPeeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (kMCG_ModePBE != mode)
   -    {
   +    if (kMCG_ModePBE != mode) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1959,8 +1842,7 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
    
        /* Wait for clock status bits to update */
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -1982,11 +1864,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
     */
   -status_t CLOCK_ExternalModeToFbeModeQuick(void)
   +status_t
   +CLOCK_ExternalModeToFbeModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) != 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) != 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1995,14 +1877,12 @@
        MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK);
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
        }
    
        /* Disable PLL. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        return kStatus_Success;
   @@ -2024,11 +1904,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
     */
   -status_t CLOCK_InternalModeToFbiModeQuick(void)
   +status_t
   +CLOCK_InternalModeToFbiModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) == 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) == 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif
   @@ -2037,8 +1917,7 @@
        MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        return kStatus_Success;
   @@ -2059,7 +1938,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
    }
   @@ -2079,8 +1959,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToFeeMode(
   -    mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeeMode(mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2100,15 +1980,15 @@
     * retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
   +status_t
   +CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
    {
        /* If reset mode is FEI mode, set MCGIRCLK and always success. */
        (void)CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
    
        /* If reset mode is not BLPI, first enter FBI mode. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        /* Enter BLPI mode. */
   @@ -2128,7 +2008,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2138,20 +2019,16 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* In FBE now, start to enter BLPE. */
   @@ -2173,7 +2050,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -2183,8 +2061,7 @@
    
        /* Change to use PLL output clock. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -2233,7 +2110,8 @@
     * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
     * function.
     */
   -status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
   +status_t
   +CLOCK_SetMcgConfig(const mcg_config_t *config)
    {
        mcg_mode_t next_mode;
        status_t status = kStatus_Success;
   @@ -2241,11 +2119,9 @@
        mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0;
    
        /* If need to change external clock, MCG_C7[OSCSEL]. */
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel))
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel)) {
            /* If external clock is in use, change to FEI first. */
   -        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -        {
   +        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
                (void)CLOCK_ExternalModeToFbeModeQuick();
                (void)CLOCK_SetFeiMode(config->dmx32, config->drs, NULL);
            }
   @@ -2254,8 +2130,7 @@
        }
    
        /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
   -    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt) {
            MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */
    
            {
   @@ -2268,67 +2143,56 @@
    
        next_mode = CLOCK_GetMode();
    
   -    do
   -    {
   +    do{
            next_mode = mcgModeMatrix[next_mode][config->mcgMode];
    
   -        switch (next_mode)
   -        {
   -            case kMCG_ModeFEI:
   -                status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFEE:
   -                status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFBI:
   -                status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeFBE:
   -                status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeBLPI:
   -                status = CLOCK_SetBlpiMode();
   -                break;
   -            case kMCG_ModeBLPE:
   -                status = CLOCK_SetBlpeMode();
   -                break;
   -            case kMCG_ModePBE:
   -                /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   -                if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode))
   +        switch (next_mode) {
   +        case kMCG_ModeFEI:
   +            status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFEE:
   +            status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFBI:
   +            status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeFBE:
   +            status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeBLPI:
   +            status = CLOCK_SetBlpiMode();
   +            break;
   +        case kMCG_ModeBLPE:
   +            status = CLOCK_SetBlpeMode();
   +            break;
   +        case kMCG_ModePBE:
   +            /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   +            if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) {
                    {
   -                    {
   -                        status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
   -                    }
   +                    status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
                    }
   -                else
   -                {
   -                    MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -                    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -                    {
   -                    }
   +            } else   {
   +                MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   +                while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
                    }
   -                break;
   -            case kMCG_ModePEE:
   -                status = CLOCK_SetPeeMode();
   -                break;
   -            default:
   -                assert(false);
   -                break;
   -        }
   -        if (kStatus_Success != status)
   -        {
   +            }
                break;
   +        case kMCG_ModePEE:
   +            status = CLOCK_SetPeeMode();
   +            break;
   +        default:
   +            assert(false);
   +            break;
   +        }
   +        if (kStatus_Success != status) {
   +            break;
            }
        } while (next_mode != config->mcgMode);
    
   -    if (status == kStatus_Success)
   -    {
   -        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U)
   -        {
   +    if (status == kStatus_Success) {
   +        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U) {
                CLOCK_EnablePll0(&config->pll0Config);
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_flash.c
   <details>
   
   ```diff
   @@ -6,7 +6,7 @@
     * to you under the Apache License, Version 2.0 (the
     * "License"); you may not use this file except in compliance
     * with the License.  You may obtain a copy of the License at
   -*
   + *
     *  http://www.apache.org/licenses/LICENSE-2.0
     *
     * Unless required by applicable law or agreed to in writing,
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_lpuart.c
   <details>
   
   ```diff
   @@ -61,10 +61,10 @@
        hal_uart_tx_char u_tx_func;
        hal_uart_tx_done u_tx_done;
        void *u_func_arg;
   -    uint8_t u_configured:1;
   -    uint8_t u_open:1;
   -    uint8_t u_tx_started:1;
   -    uint8_t u_rx_stall:1;
   +    uint8_t u_configured : 1;
   +    uint8_t u_open : 1;
   +    uint8_t u_tx_started : 1;
   +    uint8_t u_rx_stall : 1;
        struct uart_ring ur_tx;
        uint8_t tx_buffer[TX_BUF_SZ];
        struct uart_ring ur_rx;
   @@ -457,8 +457,7 @@
                uarts[port].ur_rx.ur_head = 0;
                uarts[port].ur_rx.ur_tail = 0;
                uarts[port].u_configured = 1;
   -        }
   -        else {
   +        } else   {
                uarts[port].u_configured = 0;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_qspi.c
   <details>
   
   ```diff
   @@ -107,7 +107,8 @@
        [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
    
        /* Match MISRA rule */
   -    [63] = 0};
   +    [63] = 0
   +};
    
    qspi_flash_config_t g_qspi_flash_cfg = {
        .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
   @@ -132,15 +133,12 @@
    {
        uint32_t val = 0;
        /* Check WIP bit */
   -    do
   -    {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +    do{
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
            QSPI_ExecuteIPCommand(QuadSPI0, 12U);
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            val = QuadSPI0->RBDR[0];
            /* Clear ARDB area */
   @@ -151,19 +149,17 @@
    static void
    cmd_write_enable()
    {
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ExecuteIPCommand(QuadSPI0, 4U);
    }
    
    static void
   -read_page(uint32_t address, uint32_t* dst)
   +read_page(uint32_t address, uint32_t * dst)
    {
        int i;
   -    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
   -    {
   -        dst[i] = ((uint32_t*)address)[i];
   +    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++) {
   +        dst[i] = ((uint32_t *)address)[i];
        }
    }
    
   @@ -195,15 +191,13 @@
    {
        uint32_t leftLongWords = 0;
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
    
        QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
        cmd_write_enable();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
    
        /* First write some data into TXFIFO to prevent from underrun */
   @@ -219,8 +213,7 @@
    
        /* Wait until flash finished program */
        check_if_finished();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess)) {
        }
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   @@ -244,7 +237,7 @@
    
        npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        while (npages) {
   -        write_page(address, (uint32_t*) src);
   +        write_page(address, (uint32_t *) src);
            npages--;
            address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        }
   @@ -253,13 +246,12 @@
    
    static int
    nxp_qspi_erase_sector(const struct hal_flash *dev,
   -                         uint32_t sector_address)
   +                      uint32_t sector_address)
    {
        sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
        sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
        QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
   @@ -286,8 +278,7 @@
        nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
        while (nsects) {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
            QSPI_SetIPCommandAddress(QuadSPI0, address);
   @@ -296,7 +287,7 @@
            check_if_finished();
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
   -    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   +        (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
            QSPI_ClearCache(QuadSPI0);
    #endif
            nsects--;
   @@ -323,8 +314,7 @@
    {
        uint32_t val[4] = {0x40U, 0, 0, 0};
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
    
   ```
   
   </details>


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[GitHub] [mynewt-core] utzig edited a comment on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
utzig edited a comment on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-773691606


   @mlaz I am fine with this now, please force-push again to check if no RAT issues remain, for some reason it was no updating the message.


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[GitHub] [mynewt-core] mlaz commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
mlaz commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570633746



##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,408 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type *dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *user_data)
+{
+    struct nxp_hal_i2c *i2c = userData;

Review comment:
       I did!




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[GitHub] [mynewt-core] mlaz commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
mlaz commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570619745



##########
File path: hw/mcu/nxp/kinetis/src/hal_lpuart.c
##########
@@ -0,0 +1,478 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+
+#include "os/mynewt.h"
+#include "hal/hal_uart.h"
+#include "hal/hal_gpio.h"
+#include "hal/hal_system.h"
+#include "mcu/cmsis_nvic.h"
+#include "bsp/bsp.h"
+#include "syscfg/syscfg.h"
+#include "mcu/kinetis_common.h"
+
+#include "fsl_clock.h"
+#include "fsl_port.h"
+#include "fsl_lpuart.h"
+
+#include "hal_lpuart_nxp.h"
+
+/*! @brief Ring buffer size (Unit: Byte). */
+#define TX_BUF_SZ  32
+#define RX_BUF_SZ  128
+
+struct uart_ring {
+    uint16_t ur_head;
+    uint16_t ur_tail;
+    uint16_t ur_size;
+    uint8_t _pad;
+    uint8_t *ur_buf;
+};
+
+struct hal_uart {
+    LPUART_Type *u_base;
+    clock_name_t clk_src;
+    uint32_t u_irq;
+    PORT_Type *p_base;
+    clock_ip_name_t p_clock;
+    int u_pin_rx;
+    int u_pin_tx;
+    hal_uart_rx_char u_rx_func;
+    hal_uart_tx_char u_tx_func;
+    hal_uart_tx_done u_tx_done;
+    void *u_func_arg;
+    uint8_t u_configured : 1;
+    uint8_t u_open : 1;
+    uint8_t u_tx_started : 1;
+    uint8_t u_rx_stall : 1;
+    struct uart_ring ur_tx;
+    uint8_t tx_buffer[TX_BUF_SZ];
+    struct uart_ring ur_rx;
+    uint8_t rx_buffer[RX_BUF_SZ];
+};
+
+/* UART configurations */
+static struct hal_uart uarts[FSL_FEATURE_SOC_LPUART_COUNT];
+
+static uint8_t const s_uartExists[] = NXP_UART_EXISTS;
+static uint8_t const s_uartEnabled[] = NXP_UART_ENABLED;
+static LPUART_Type *const s_uartBases[] = LPUART_BASE_PTRS;
+static clock_name_t s_uartClocks[] = NXP_UART_CLOCKS;
+static uint8_t const s_uartIRQ[] = LPUART_RX_TX_IRQS;
+static PORT_Type *const s_uartPort[] = NXP_UART_PORTS;
+static clock_ip_name_t const s_uartPortClocks[] = NXP_UART_PORT_CLOCKS;
+static uint8_t const s_uartPIN_RX[] = NXP_UART_PIN_RX;
+static uint8_t const s_uartPIN_TX[] = NXP_UART_PIN_TX;
+
+static void uart_irq0(void);
+static void uart_irq1(void);
+static void uart_irq2(void);
+static void uart_irq3(void);
+static void uart_irq4(void);
+static void (*s_uartirqs[])(void) = {
+    uart_irq0, uart_irq1, uart_irq2, uart_irq3, uart_irq4
+};
+
+/*
+ * RING BUFFER FUNCTIONS
+ */
+
+static uint8_t
+ur_is_empty(struct uart_ring *ur)
+{
+    return (ur->ur_head == ur->ur_tail);
+}
+
+static uint8_t
+ur_is_full(struct uart_ring *ur)
+{
+    return (((ur->ur_tail + 1) % ur->ur_size) == ur->ur_head);
+}
+
+static void
+ur_bump(struct uart_ring *ur)
+{
+    if (!ur_is_empty(ur)) {
+        ur->ur_head++;
+        ur->ur_head %= ur->ur_size;
+        return;
+    }
+}
+
+static uint8_t
+ur_read(struct uart_ring *ur)
+{
+    return ur->ur_buf[ur->ur_head];
+}
+
+static int
+ur_queue(struct uart_ring *ur, uint8_t data)
+{
+    if (!ur_is_full(ur)) {
+        ur->ur_buf[ur->ur_tail] = data;
+        ur->ur_tail++;
+        ur->ur_tail %= ur->ur_size;
+        return 0;
+    }
+    return -1;
+}
+
+/*
+ * END RING BUFFER FUNCTIONS
+ */
+
+int
+hal_uart_init_cbs(int port,
+                  hal_uart_tx_char tx_func,
+                  hal_uart_tx_done tx_done,
+                  hal_uart_rx_char rx_func,
+                  void *arg)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    u->u_rx_func = rx_func;
+    u->u_tx_func = tx_func;
+    u->u_tx_done = tx_done;
+    u->u_func_arg = arg;
+
+    return 0;
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t byte)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    LPUART_WriteBlocking(u->u_base, &byte, 1);
+}
+
+static int
+hal_uart_tx_fill_buf(struct hal_uart *u)
+{
+    int data = 0;
+    int i = 0;
+    os_sr_t sr;
+
+    OS_ENTER_CRITICAL(sr);
+    while (!ur_is_full(&u->ur_tx)) {
+        if (u->u_tx_func) {
+            data = u->u_tx_func(u->u_func_arg);
+        }
+        if (data <= 0) {
+            break;
+        }
+        i++;
+        ur_queue(&u->ur_tx, data);
+    }
+    OS_EXIT_CRITICAL(sr);
+    return i;
+}
+
+void
+hal_uart_start_tx(int port)
+{
+    struct hal_uart *u;
+    int data = -1;
+    int rc;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    /* main loop */
+    while (true) {
+        /* add data to TX ring buffer */
+        if (u->u_tx_started == 0) {
+            rc = hal_uart_tx_fill_buf(u);
+            if (rc > 0) {
+                u->u_tx_started = 1;
+            }
+        }
+
+        /* Send data only when UART TX register is empty and TX ring buffer has data to send out. */
+        while (!ur_is_empty(&u->ur_tx) &&
+               (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base))) {
+            data = ur_read(&u->ur_tx);
+            LPUART_WriteByte(u->u_base, data);
+            ur_bump(&u->ur_tx);
+        }
+
+        if (ur_is_empty(&u->ur_tx)) {
+            if (u->u_tx_done) {
+                u->u_tx_done(u->u_func_arg);
+            }
+            u->u_tx_started = 0;
+            break;
+        }
+    }
+}
+
+void
+hal_uart_start_rx(int port)
+{
+    struct hal_uart *u;
+    os_sr_t sr;
+    int rc = 0;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    u->u_rx_stall = 0;
+
+    /* Send back what's in the RX ring buffer until it's empty or we get an
+     * error */
+    while ((rc >= 0) && !ur_is_empty(&u->ur_rx)) {
+        OS_ENTER_CRITICAL(sr);
+        rc = u->u_rx_func(u->u_func_arg, ur_read(&u->ur_rx));
+        if (rc >= 0) {
+            ur_bump(&u->ur_rx);
+        } else {
+            u->u_rx_stall = 1;
+        }
+        OS_EXIT_CRITICAL(sr);
+    }
+}
+
+static void
+uart_irq_handler(int port)
+{
+    struct hal_uart *u;
+    uint32_t status;
+    uint8_t data;
+
+    u = &uarts[port];
+    if (u->u_configured && u->u_open) {
+        status = LPUART_GetStatusFlags(u->u_base);
+        /* Check for RX data */
+        if (status & (kLPUART_RxDataRegFullFlag | kLPUART_RxOverrunFlag)) {
+            data = LPUART_ReadByte(u->u_base);
+            if (u->u_rx_stall || u->u_rx_func(u->u_func_arg, data) < 0) {
+                /*
+                 * RX queue full.
+                 */
+                u->u_rx_stall = 1;
+                ur_queue(&u->ur_rx, data);
+            }
+        }
+        /* Check for TX complete */
+        if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base)) {
+            if (u->u_tx_started) {
+                u->u_tx_started = 0;
+                if (u->u_tx_done) {
+                    u->u_tx_done(u->u_func_arg);
+                }
+            }
+        }
+    }
+}
+
+static void
+uart_irq0(void)
+{
+    uart_irq_handler(0);
+}
+
+static void
+uart_irq1(void)
+{
+    uart_irq_handler(1);
+}
+
+static void
+uart_irq2(void)
+{
+    uart_irq_handler(2);
+}
+
+static void
+uart_irq3(void)
+{
+    uart_irq_handler(3);
+}
+
+static void
+uart_irq4(void)
+{
+    uart_irq_handler(4);
+}
+
+int
+hal_uart_config(int port,
+                int32_t speed,
+                uint8_t databits,
+                uint8_t stopbits,
+                enum hal_uart_parity parity,
+                enum hal_uart_flow_ctl flow_ctl)
+{
+    struct hal_uart *u;
+    lpuart_config_t uconfig;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || u->u_open) {
+        return -1;
+    }
+
+    /* PIN config (all UARTs use kPORT_MuxAlt3) */
+    CLOCK_EnableClock(u->p_clock);
+    PORT_SetPinMux(u->p_base, u->u_pin_rx, kPORT_MuxAlt3);
+    PORT_SetPinMux(u->p_base, u->u_pin_tx, kPORT_MuxAlt3);
+
+    /* UART CONFIG */
+    CLOCK_SetLpuartClock(2U);
+
+    LPUART_GetDefaultConfig(&uconfig);
+    uconfig.baudRate_Bps = speed;
+
+    switch (databits) {
+    case 8:
+        uconfig.dataBitsCount = kLPUART_EightDataBits;
+        break;
+    case 7:
+#if FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        uconfig.dataBitsCount = kLPUART_SevenDataBits;
+        break;
+#endif /* Fallthrought */
+    default:
+        uconfig.parityMode = kLPUART_ParityEven;
+        return -1;

Review comment:
       hah good catch!




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[GitHub] [mynewt-core] mlaz commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
mlaz commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570624452



##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,408 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type *dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *userData)

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_lpuart.c
##########
@@ -0,0 +1,478 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+
+#include "os/mynewt.h"
+#include "hal/hal_uart.h"
+#include "hal/hal_gpio.h"
+#include "hal/hal_system.h"
+#include "mcu/cmsis_nvic.h"
+#include "bsp/bsp.h"
+#include "syscfg/syscfg.h"
+#include "mcu/kinetis_common.h"
+
+#include "fsl_clock.h"
+#include "fsl_port.h"
+#include "fsl_lpuart.h"
+
+#include "hal_lpuart_nxp.h"
+
+/*! @brief Ring buffer size (Unit: Byte). */
+#define TX_BUF_SZ  32
+#define RX_BUF_SZ  128
+
+struct uart_ring {
+    uint16_t ur_head;
+    uint16_t ur_tail;
+    uint16_t ur_size;
+    uint8_t _pad;
+    uint8_t *ur_buf;
+};
+
+struct hal_uart {
+    LPUART_Type *u_base;
+    clock_name_t clk_src;
+    uint32_t u_irq;
+    PORT_Type *p_base;
+    clock_ip_name_t p_clock;
+    int u_pin_rx;
+    int u_pin_tx;
+    hal_uart_rx_char u_rx_func;
+    hal_uart_tx_char u_tx_func;
+    hal_uart_tx_done u_tx_done;
+    void *u_func_arg;
+    uint8_t u_configured : 1;
+    uint8_t u_open : 1;
+    uint8_t u_tx_started : 1;
+    uint8_t u_rx_stall : 1;
+    struct uart_ring ur_tx;
+    uint8_t tx_buffer[TX_BUF_SZ];
+    struct uart_ring ur_rx;
+    uint8_t rx_buffer[RX_BUF_SZ];
+};
+
+/* UART configurations */
+static struct hal_uart uarts[FSL_FEATURE_SOC_LPUART_COUNT];
+
+static uint8_t const s_uartExists[] = NXP_UART_EXISTS;
+static uint8_t const s_uartEnabled[] = NXP_UART_ENABLED;
+static LPUART_Type *const s_uartBases[] = LPUART_BASE_PTRS;
+static clock_name_t s_uartClocks[] = NXP_UART_CLOCKS;
+static uint8_t const s_uartIRQ[] = LPUART_RX_TX_IRQS;
+static PORT_Type *const s_uartPort[] = NXP_UART_PORTS;
+static clock_ip_name_t const s_uartPortClocks[] = NXP_UART_PORT_CLOCKS;
+static uint8_t const s_uartPIN_RX[] = NXP_UART_PIN_RX;
+static uint8_t const s_uartPIN_TX[] = NXP_UART_PIN_TX;
+
+static void uart_irq0(void);
+static void uart_irq1(void);
+static void uart_irq2(void);
+static void uart_irq3(void);
+static void uart_irq4(void);
+static void (*s_uartirqs[])(void) = {
+    uart_irq0, uart_irq1, uart_irq2, uart_irq3, uart_irq4
+};
+
+/*
+ * RING BUFFER FUNCTIONS
+ */
+
+static uint8_t
+ur_is_empty(struct uart_ring *ur)
+{
+    return (ur->ur_head == ur->ur_tail);
+}
+
+static uint8_t
+ur_is_full(struct uart_ring *ur)
+{
+    return (((ur->ur_tail + 1) % ur->ur_size) == ur->ur_head);
+}
+
+static void
+ur_bump(struct uart_ring *ur)
+{
+    if (!ur_is_empty(ur)) {
+        ur->ur_head++;
+        ur->ur_head %= ur->ur_size;
+        return;
+    }
+}
+
+static uint8_t
+ur_read(struct uart_ring *ur)
+{
+    return ur->ur_buf[ur->ur_head];
+}
+
+static int
+ur_queue(struct uart_ring *ur, uint8_t data)
+{
+    if (!ur_is_full(ur)) {
+        ur->ur_buf[ur->ur_tail] = data;
+        ur->ur_tail++;
+        ur->ur_tail %= ur->ur_size;
+        return 0;
+    }
+    return -1;
+}
+
+/*
+ * END RING BUFFER FUNCTIONS
+ */
+
+int
+hal_uart_init_cbs(int port,
+                  hal_uart_tx_char tx_func,
+                  hal_uart_tx_done tx_done,
+                  hal_uart_rx_char rx_func,
+                  void *arg)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    u->u_rx_func = rx_func;
+    u->u_tx_func = tx_func;
+    u->u_tx_done = tx_done;
+    u->u_func_arg = arg;
+
+    return 0;
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t byte)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    LPUART_WriteBlocking(u->u_base, &byte, 1);
+}
+
+static int
+hal_uart_tx_fill_buf(struct hal_uart *u)
+{
+    int data = 0;
+    int i = 0;
+    os_sr_t sr;
+
+    OS_ENTER_CRITICAL(sr);
+    while (!ur_is_full(&u->ur_tx)) {
+        if (u->u_tx_func) {
+            data = u->u_tx_func(u->u_func_arg);
+        }
+        if (data <= 0) {
+            break;
+        }
+        i++;
+        ur_queue(&u->ur_tx, data);
+    }
+    OS_EXIT_CRITICAL(sr);
+    return i;
+}
+
+void
+hal_uart_start_tx(int port)
+{
+    struct hal_uart *u;
+    int data = -1;
+    int rc;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    /* main loop */
+    while (true) {
+        /* add data to TX ring buffer */
+        if (u->u_tx_started == 0) {
+            rc = hal_uart_tx_fill_buf(u);
+            if (rc > 0) {
+                u->u_tx_started = 1;
+            }
+        }
+
+        /* Send data only when UART TX register is empty and TX ring buffer has data to send out. */
+        while (!ur_is_empty(&u->ur_tx) &&
+               (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base))) {
+            data = ur_read(&u->ur_tx);
+            LPUART_WriteByte(u->u_base, data);
+            ur_bump(&u->ur_tx);
+        }
+
+        if (ur_is_empty(&u->ur_tx)) {
+            if (u->u_tx_done) {
+                u->u_tx_done(u->u_func_arg);
+            }
+            u->u_tx_started = 0;
+            break;
+        }
+    }
+}
+
+void
+hal_uart_start_rx(int port)
+{
+    struct hal_uart *u;
+    os_sr_t sr;
+    int rc = 0;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    u->u_rx_stall = 0;
+
+    /* Send back what's in the RX ring buffer until it's empty or we get an
+     * error */
+    while ((rc >= 0) && !ur_is_empty(&u->ur_rx)) {
+        OS_ENTER_CRITICAL(sr);
+        rc = u->u_rx_func(u->u_func_arg, ur_read(&u->ur_rx));
+        if (rc >= 0) {
+            ur_bump(&u->ur_rx);
+        } else {
+            u->u_rx_stall = 1;
+        }
+        OS_EXIT_CRITICAL(sr);
+    }
+}
+
+static void
+uart_irq_handler(int port)
+{
+    struct hal_uart *u;
+    uint32_t status;
+    uint8_t data;
+
+    u = &uarts[port];
+    if (u->u_configured && u->u_open) {
+        status = LPUART_GetStatusFlags(u->u_base);
+        /* Check for RX data */
+        if (status & (kLPUART_RxDataRegFullFlag | kLPUART_RxOverrunFlag)) {
+            data = LPUART_ReadByte(u->u_base);
+            if (u->u_rx_stall || u->u_rx_func(u->u_func_arg, data) < 0) {
+                /*
+                 * RX queue full.
+                 */
+                u->u_rx_stall = 1;
+                ur_queue(&u->ur_rx, data);
+            }
+        }
+        /* Check for TX complete */
+        if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base)) {
+            if (u->u_tx_started) {
+                u->u_tx_started = 0;
+                if (u->u_tx_done) {
+                    u->u_tx_done(u->u_func_arg);
+                }
+            }
+        }
+    }
+}
+
+static void
+uart_irq0(void)
+{
+    uart_irq_handler(0);
+}
+
+static void
+uart_irq1(void)
+{
+    uart_irq_handler(1);
+}
+
+static void
+uart_irq2(void)
+{
+    uart_irq_handler(2);
+}
+
+static void
+uart_irq3(void)
+{
+    uart_irq_handler(3);
+}
+
+static void
+uart_irq4(void)
+{
+    uart_irq_handler(4);
+}
+
+int
+hal_uart_config(int port,
+                int32_t speed,
+                uint8_t databits,
+                uint8_t stopbits,
+                enum hal_uart_parity parity,
+                enum hal_uart_flow_ctl flow_ctl)
+{
+    struct hal_uart *u;
+    lpuart_config_t uconfig;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || u->u_open) {
+        return -1;
+    }
+
+    /* PIN config (all UARTs use kPORT_MuxAlt3) */
+    CLOCK_EnableClock(u->p_clock);
+    PORT_SetPinMux(u->p_base, u->u_pin_rx, kPORT_MuxAlt3);
+    PORT_SetPinMux(u->p_base, u->u_pin_tx, kPORT_MuxAlt3);
+
+    /* UART CONFIG */
+    CLOCK_SetLpuartClock(2U);
+
+    LPUART_GetDefaultConfig(&uconfig);
+    uconfig.baudRate_Bps = speed;
+
+    switch (databits) {
+    case 8:
+        uconfig.dataBitsCount = kLPUART_EightDataBits;
+        break;
+    case 7:
+#if FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        uconfig.dataBitsCount = kLPUART_SevenDataBits;
+        break;
+#endif /* Fallthrought */
+    default:
+        uconfig.parityMode = kLPUART_ParityEven;
+        return -1;

Review comment:
       Addressed.




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[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot removed a comment on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-772981680


   
   <!-- style-bot -->
   
   ## Style check summary
   
   ### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
   
   
   #### hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c
   <details>
   
   ```diff
   @@ -187,15 +187,15 @@
     ******************************************************************************/
    
    #ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
   -static void CLOCK_FllStableDelay(void)
   +static void
   +CLOCK_FllStableDelay(void)
    {
        /*
           Should wait at least 1ms. Because in these modes, the core clock is 100MHz
           at most, so this function could obtain the 1ms delay.
         */
        volatile uint32_t i = 30000U;
   -    while (0U != (i--))
   -    {
   +    while (0U != (i--)) {
            __NOP();
        }
    }
   @@ -207,34 +207,35 @@
    extern void CLOCK_FllStableDelay(void);
    #endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */
    
   -static uint32_t CLOCK_GetMcgExtClkFreq(void)
   +static uint32_t
   +CLOCK_GetMcgExtClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (MCG_C7_OSCSEL_VAL)
   -    {
   -        case 0U:
   -            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   -            assert(0U != g_xtal0Freq);
   -            freq = g_xtal0Freq;
   -            break;
   -        case 1U:
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(0U != g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 2U:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (MCG_C7_OSCSEL_VAL) {
   +    case 0U:
   +        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   +        assert(0U != g_xtal0Freq);
   +        freq = g_xtal0Freq;
   +        break;
   +    case 1U:
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(0U != g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 2U:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllExtRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllExtRefClkFreq(void)
    {
        /* FllExtRef = McgExtRef / FllExtRefDiv */
        uint8_t frdiv;
   @@ -246,54 +247,50 @@
        frdiv = MCG_C1_FRDIV_VAL;
        freq >>= frdiv;
    
   -    range  = MCG_C2_RANGE_VAL;
   +    range = MCG_C2_RANGE_VAL;
        oscsel = MCG_C7_OSCSEL_VAL;
    
        /*
           When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536.
           1. MCG_C7[OSCSEL] selects IRC48M.
           2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0.
   -    */
   -    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel))
   -    {
   -        switch (frdiv)
   -        {
   -            case 0:
   -            case 1:
   -            case 2:
   -            case 3:
   -            case 4:
   -            case 5:
   -                freq >>= 5u;
   -                break;
   -            case 6:
   -                /* 64*20=1280 */
   -                freq /= 20u;
   -                break;
   -            case 7:
   -                /* 128*12=1536 */
   -                freq /= 12u;
   -                break;
   -            default:
   -                freq = 0u;
   -                break;
   +     */
   +    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel)) {
   +        switch (frdiv) {
   +        case 0:
   +        case 1:
   +        case 2:
   +        case 3:
   +        case 4:
   +        case 5:
   +            freq >>= 5u;
   +            break;
   +        case 6:
   +            /* 64*20=1280 */
   +            freq /= 20u;
   +            break;
   +        case 7:
   +            /* 128*12=1536 */
   +            freq /= 12u;
   +            break;
   +        default:
   +            freq = 0u;
   +            break;
            }
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetInternalRefClkSelectFreq(void)
   +static uint32_t
   +CLOCK_GetInternalRefClkSelectFreq(void)
    {
        uint32_t freq;
    
   -    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL)
   -    {
   +    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL) {
            /* Slow internal reference clock selected*/
            freq = s_slowIrcFreq;
   -    }
   -    else
   -    {
   +    } else   {
            /* Fast internal reference clock selected*/
            freq = s_fastIrcFreq >> MCG_SC_FCRDIV_VAL;
        }
   @@ -301,44 +298,40 @@
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If use external reference clock. */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            freq = CLOCK_GetFllExtRefClkFreq();
        }
        /* If use internal reference clock. */
   -    else
   -    {
   +    else {
            freq = s_slowIrcFreq;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetPll0RefFreq(void)
   +static uint32_t
   +CLOCK_GetPll0RefFreq(void)
    {
        /* MCG external reference clock. */
        return CLOCK_GetMcgExtClkFreq();
    }
    
   -static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
   +static uint8_t
   +CLOCK_GetOscRangeFromFreq(uint32_t freq)
    {
        uint8_t range;
    
   -    if (freq <= 39063U)
   -    {
   +    if (freq <= 39063U) {
            range = 0U;
   -    }
   -    else if (freq <= 8000000U)
   -    {
   +    } else if (freq <= 8000000U)   {
            range = 1U;
   -    }
   -    else
   -    {
   +    } else   {
            range = 2U;
        }
    
   @@ -350,17 +343,15 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetOsc0ErClkFreq(void)
   +uint32_t
   +CLOCK_GetOsc0ErClkFreq(void)
    {
        uint32_t freq;
   -    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)
   -    {
   +    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U) {
            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
            assert(g_xtal0Freq);
            freq = g_xtal0Freq;
   -    }
   -    else
   -    {
   +    } else   {
            freq = 0U;
        }
    
   @@ -372,26 +363,26 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetEr32kClkFreq(void)
   +uint32_t
   +CLOCK_GetEr32kClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT1_OSC32KSEL_VAL)
   -    {
   -        case 0U: /* OSC 32k clock  */
   -            freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   -            break;
   -        case 2U: /* RTC 32k clock  */
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 3U: /* LPO clock      */
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT1_OSC32KSEL_VAL) {
   +    case 0U:     /* OSC 32k clock  */
   +        freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   +        break;
   +    case 2U:     /* RTC 32k clock  */
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 3U:     /* LPO clock      */
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
        return freq;
    }
   @@ -401,24 +392,24 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPllFllSelClkFreq(void)
   +uint32_t
   +CLOCK_GetPllFllSelClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT2_PLLFLLSEL_VAL)
   -    {
   -        case 0U: /* FLL. */
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case 1U: /* PLL. */
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case 3U: /* MCG IRC48M. */
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT2_PLLFLLSEL_VAL) {
   +    case 0U:     /* FLL. */
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case 1U:     /* PLL. */
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case 3U:     /* MCG IRC48M. */
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -429,7 +420,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPlatClkFreq(void)
   +uint32_t
   +CLOCK_GetPlatClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -439,7 +431,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlashClkFreq(void)
   +uint32_t
   +CLOCK_GetFlashClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
    }
   @@ -449,7 +442,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlexBusClkFreq(void)
   +uint32_t
   +CLOCK_GetFlexBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
    }
   @@ -459,7 +453,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetBusClkFreq(void)
   +uint32_t
   +CLOCK_GetBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
    }
   @@ -469,7 +464,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetCoreSysClkFreq(void)
   +uint32_t
   +CLOCK_GetCoreSysClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -484,55 +480,55 @@
     * param clockName Clock names defined in clock_name_t
     * return Clock frequency value in Hertz
     */
   -uint32_t CLOCK_GetFreq(clock_name_t clockName)
   +uint32_t
   +CLOCK_GetFreq(clock_name_t clockName)
    {
        uint32_t freq;
    
   -    switch (clockName)
   -    {
   -        case kCLOCK_CoreSysClk:
   -        case kCLOCK_PlatClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   -            break;
   -        case kCLOCK_BusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlexBusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlashClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   -            break;
   -        case kCLOCK_PllFllSelClk:
   -            freq = CLOCK_GetPllFllSelClkFreq();
   -            break;
   -        case kCLOCK_Er32kClk:
   -            freq = CLOCK_GetEr32kClkFreq();
   -            break;
   -        case kCLOCK_Osc0ErClk:
   -            freq = CLOCK_GetOsc0ErClkFreq();
   -            break;
   -        case kCLOCK_McgFixedFreqClk:
   -            freq = CLOCK_GetFixedFreqClkFreq();
   -            break;
   -        case kCLOCK_McgInternalRefClk:
   -            freq = CLOCK_GetInternalRefClkFreq();
   -            break;
   -        case kCLOCK_McgFllClk:
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case kCLOCK_McgPll0Clk:
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case kCLOCK_McgIrc48MClk:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        case kCLOCK_LpoClk:
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (clockName) {
   +    case kCLOCK_CoreSysClk:
   +    case kCLOCK_PlatClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   +        break;
   +    case kCLOCK_BusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlexBusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlashClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   +        break;
   +    case kCLOCK_PllFllSelClk:
   +        freq = CLOCK_GetPllFllSelClkFreq();
   +        break;
   +    case kCLOCK_Er32kClk:
   +        freq = CLOCK_GetEr32kClkFreq();
   +        break;
   +    case kCLOCK_Osc0ErClk:
   +        freq = CLOCK_GetOsc0ErClkFreq();
   +        break;
   +    case kCLOCK_McgFixedFreqClk:
   +        freq = CLOCK_GetFixedFreqClkFreq();
   +        break;
   +    case kCLOCK_McgInternalRefClk:
   +        freq = CLOCK_GetInternalRefClkFreq();
   +        break;
   +    case kCLOCK_McgFllClk:
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case kCLOCK_McgPll0Clk:
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case kCLOCK_McgIrc48MClk:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    case kCLOCK_LpoClk:
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -545,7 +541,8 @@
     *
     * param config Pointer to the configure structure.
     */
   -void CLOCK_SetSimConfig(sim_clock_config_t const *config)
   +void
   +CLOCK_SetSimConfig(sim_clock_config_t const *config)
    {
        SIM->CLKDIV1 = config->clkdiv1;
        CLOCK_SetPllFllSelClock(config->pllFllSel);
   @@ -559,35 +556,32 @@
     * retval true The clock is set successfully.
     * retval false The clock source is invalid to get proper USB FS clock.
     */
   -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
   +bool
   +CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
    {
        bool ret = true;
    
        CLOCK_DisableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcExt == src)
   -    {
   +    if (kCLOCK_UsbSrcExt == src) {
            SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
   -    }
   -    else
   -    {
   -        switch (freq)
   -        {
   -            case 120000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 96000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            case 72000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 48000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            default:
   -                ret = false;
   -                break;
   +    } else   {
   +        switch (freq) {
   +        case 120000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 96000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        case 72000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 48000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        default:
   +            ret = false;
   +            break;
            }
    
            SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src);
   @@ -595,8 +589,7 @@
    
        CLOCK_EnableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcIrc48M == src)
   -    {
   +    if (kCLOCK_UsbSrcIrc48M == src) {
            USB0->CLK_RECOVER_IRC_EN = 0x03U;
            USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
        }
   @@ -611,28 +604,28 @@
     *
     * return The frequency of MCGOUTCLK.
     */
   -uint32_t CLOCK_GetOutClkFreq(void)
   +uint32_t
   +CLOCK_GetOutClkFreq(void)
    {
        uint32_t mcgoutclk;
        uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
    
   -    switch (clkst)
   -    {
   -        case (uint32_t)kMCG_ClkOutStatPll:
   -            mcgoutclk = CLOCK_GetPll0Freq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatFll:
   -            mcgoutclk = CLOCK_GetFllFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatInt:
   -            mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatExt:
   -            mcgoutclk = CLOCK_GetMcgExtClkFreq();
   -            break;
   -        default:
   -            mcgoutclk = 0U;
   -            break;
   +    switch (clkst) {
   +    case (uint32_t)kMCG_ClkOutStatPll:
   +        mcgoutclk = CLOCK_GetPll0Freq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatFll:
   +        mcgoutclk = CLOCK_GetFllFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatInt:
   +        mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatExt:
   +        mcgoutclk = CLOCK_GetMcgExtClkFreq();
   +        break;
   +    default:
   +        mcgoutclk = 0U;
   +        break;
        }
    
        return mcgoutclk;
   @@ -647,7 +640,8 @@
     *
     * return The frequency of MCGFLLCLK.
     */
   -uint32_t CLOCK_GetFllFreq(void)
   +uint32_t
   +CLOCK_GetFllFreq(void)
    {
        static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}};
    
   @@ -656,23 +650,17 @@
        uint32_t ret;
    
        /* If FLL is not enabled currently, then return 0U. */
   -    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U)))
   -    {
   +    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) {
            ret = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            /* Get FLL reference clock frequency. */
            freq = CLOCK_GetFllRefClkFreq();
   -        if (0U == freq)
   -        {
   +        if (0U == freq) {
                ret = freq;
   -        }
   -        else
   -        {
   -            drs   = MCG_C4_DRST_DRS_VAL;
   +        } else   {
   +            drs = MCG_C4_DRST_DRS_VAL;
                dmx32 = MCG_C4_DMX32_VAL;
   -            ret   = freq * fllFactorTable[drs][dmx32];
   +            ret = freq * fllFactorTable[drs][dmx32];
            }
        }
    
   @@ -687,17 +675,15 @@
     *
     * return The frequency of MCGIRCLK.
     */
   -uint32_t CLOCK_GetInternalRefClkFreq(void)
   +uint32_t
   +CLOCK_GetInternalRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If MCGIRCLK is gated. */
   -    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK))
   -    {
   +    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            freq = CLOCK_GetInternalRefClkSelectFreq();
        }
    
   @@ -712,18 +698,16 @@
     *
     * return The frequency of MCGFFCLK.
     */
   -uint32_t CLOCK_GetFixedFreqClkFreq(void)
   +uint32_t
   +CLOCK_GetFixedFreqClkFreq(void)
    {
        uint32_t freq = CLOCK_GetFllRefClkFreq();
        uint32_t ret;
    
        /* MCGFFCLK must be no more than MCGOUTCLK/8. */
   -    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq))
   -    {
   +    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq)) {
            ret = freq;
   -    }
   -    else
   -    {
   +    } else   {
            ret = 0U;
        }
    
   @@ -738,7 +722,8 @@
     *
     * return The frequency of MCGPLL0CLK.
     */
   -uint32_t CLOCK_GetPll0Freq(void)
   +uint32_t
   +CLOCK_GetPll0Freq(void)
    {
        uint32_t mcgpll0clk;
        uint32_t freq;
   @@ -746,12 +731,9 @@
        uint8_t mcgpll0prdiv;
        uint8_t mcgpll0vdiv;
        /* If PLL0 is not enabled, return 0. */
   -    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            mcgpll0clk = CLOCK_GetPll0RefFreq();
    
            /*
   @@ -783,36 +765,31 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success External reference clock set successfully.
     */
   -status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
    {
        bool needDelay;
        uint32_t i;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */
   -    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK)))
   -    {
   +    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) {
            return kStatus_MCG_SourceUsed;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
    
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel)
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel) {
            /* If change OSCSEL, need to delay, ERR009878. */
            needDelay = true;
   -    }
   -    else
   -    {
   +    } else   {
            needDelay = false;
        }
    
        MCG->C7 = (uint8_t)(MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
   -    if (needDelay)
   -    {
   +    if (needDelay) {
            /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
            i = 1500U;
   -        while (0U != (i--))
   -        {
   +        while (0U != (i--)) {
                __NOP();
            }
        }
   @@ -836,34 +813,30 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success MCGIRCLK configuration finished successfully.
     */
   -status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
   +status_t
   +CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
    {
        uint32_t mcgOutClkState = (uint32_t)MCG_S_CLKST_VAL;
   -    mcg_irc_mode_t curIrcs  = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   -    uint8_t curFcrdiv       = MCG_SC_FCRDIV_VAL;
   +    mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   +    uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If MCGIRCLK is used as system clock source. */
   -    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState)
   -    {
   +    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState) {
            /* If need to change MCGIRCLK source or driver, return error. */
   -        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs))
   -        {
   +        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) {
                return kStatus_MCG_SourceUsed;
            }
        }
    #endif
    
        /* If need to update the FCRDIV. */
   -    if (fcrdiv != curFcrdiv)
   -    {
   +    if (fcrdiv != curFcrdiv) {
            /* If fast IRC is in use currently, change to slow IRC. */
            if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) &&
   -            (kMCG_IrcFast == curIrcs))
   -        {
   +            (kMCG_IrcFast == curIrcs)) {
                MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
   -            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow)
   -            {
   +            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow) {
                }
            }
            /* Update FCRDIV. */
   @@ -876,10 +849,8 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode);
    
        /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
   -    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable)))
   -    {
   -        while (MCG_S_IRCST_VAL != (uint8_t)ircs)
   -        {
   +    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable))) {
   +        while (MCG_S_IRCST_VAL != (uint8_t)ircs) {
            }
        }
    
   @@ -901,7 +872,8 @@
     * param vdiv       VDIV value to generate desired PLL frequency.
     * return Closest frequency match that the PLL was able generate.
     */
   -uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
   +uint32_t
   +CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
    {
        uint8_t ret_prdiv;               /* PRDIV to return. */
        uint8_t ret_vdiv;                /* VDIV to return.  */
   @@ -910,7 +882,7 @@
        uint8_t prdiv_cur;               /* PRDIV value for iteration.    */
        uint8_t vdiv_cur;                /* VDIV value for iteration.     */
        uint32_t ret_freq = 0U;          /* PLL output frequency to return. */
   -    uint32_t diff     = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */
   +    uint32_t diff = 0xFFFFFFFFU;     /* Difference between desireFreq and return frequency. */
        uint32_t ref_div;                /* Reference frequency after PRDIV. */
    
        /*
   @@ -929,8 +901,7 @@
        /* Reference frequency is out of range. */
        if ((refFreq < (uint32_t)FSL_FEATURE_MCG_PLL_REF_MIN) ||
            (refFreq > ((uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX *
   -                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE))))
   -    {
   +                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) {
            return 0U;
        }
    
   @@ -940,62 +911,52 @@
            (uint8_t)((refFreq + (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX);
    
        /* PRDIV traversal. */
   -    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--)
   -    {
   +    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) {
            /* Reference frequency after PRDIV. */
            ref_div = refFreq / prdiv_cur;
    
            vdiv_cur = (uint8_t)(desireFreq / ref_div);
    
            if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) ||
   -            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                /* No VDIV is available with this PRDIV. */
                continue;
            }
    
            ret_freq = vdiv_cur * ref_div;
    
   -        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE)
   -        {
   -            if (ret_freq == desireFreq) /* If desire frequency is got. */
   -            {
   +        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) {
   +            if (ret_freq == desireFreq) { /* If desire frequency is got. */
                    *prdiv = prdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -                *vdiv  = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +                *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
                    return ret_freq;
                }
                /* New PRDIV/VDIV is closer. */
   -            if (diff > desireFreq - ret_freq)
   -            {
   -                diff      = desireFreq - ret_freq;
   +            if (diff > desireFreq - ret_freq) {
   +                diff = desireFreq - ret_freq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
            vdiv_cur++;
   -        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                ret_freq += ref_div;
                /* New PRDIV/VDIV is closer. */
   -            if (diff > ret_freq - desireFreq)
   -            {
   -                diff      = ret_freq - desireFreq;
   +            if (diff > ret_freq - desireFreq) {
   +                diff = ret_freq - desireFreq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
        }
    
   -    if (0xFFFFFFFFU != diff)
   -    {
   +    if (0xFFFFFFFFU != diff) {
            /* PRDIV/VDIV found. */
   -        *prdiv   = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -        *vdiv    = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +        *prdiv = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   +        *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
            ret_freq = (refFreq / ret_prdiv) * ret_vdiv;
            return ret_freq;
   -    }
   -    else
   -    {
   +    } else   {
            /* No proper PRDIV/VDIV found. */
            return 0U;
        }
   @@ -1012,7 +973,8 @@
     *
     * param config Pointer to the configuration structure.
     */
   -void CLOCK_EnablePll0(mcg_pll_config_t const *config)
   +void
   +CLOCK_EnablePll0(mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1027,8 +989,7 @@
        MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode);
    
        /* Wait for PLL lock. */
   -    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
        }
    }
    
   @@ -1039,23 +1000,18 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
    {
        /* Clear the previous flag, MCG_SC[LOCS0]. */
        MCG->SC &= ~(uint8_t)MCG_SC_ATMF_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= ~(uint8_t)MCG_C6_CME0_MASK;
   -    }
   -    else
   -    {
   -        if (kMCG_MonitorInt == mode)
   -        {
   +    } else   {
   +        if (kMCG_MonitorInt == mode) {
                MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK;
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C2 |= MCG_C2_LOCRE0_MASK;
            }
            MCG->C6 |= MCG_C6_CME0_MASK;
   @@ -1069,16 +1025,15 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8 = MCG->C8;
    
        mcg_c8 &= ~(uint8_t)(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK);
    
   -    if (kMCG_MonitorNone != mode)
   -    {
   -        if (kMCG_MonitorReset == mode)
   -        {
   +    if (kMCG_MonitorNone != mode) {
   +        if (kMCG_MonitorReset == mode) {
                mcg_c8 |= MCG_C8_LOCRE1_MASK;
            }
            mcg_c8 |= MCG_C8_CME1_MASK;
   @@ -1093,29 +1048,24 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8;
    
        /* Clear previous flag. */
        MCG->S = MCG_S_LOLS0_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= (uint8_t)(~MCG_C6_LOLIE0_MASK);
   -    }
   -    else
   -    {
   +    } else   {
            mcg_c8 = MCG->C8;
    
            mcg_c8 &= (uint8_t)(~MCG_C8_LOCS1_MASK);
    
   -        if (kMCG_MonitorInt == mode)
   -        {
   +        if (kMCG_MonitorInt == mode) {
                mcg_c8 &= (uint8_t)(~MCG_C8_LOLRE_MASK);
   -        }
   -        else
   -        {
   +        } else   {
                mcg_c8 |= MCG_C8_LOLRE_MASK;
            }
            MCG->C8 = mcg_c8;
   @@ -1149,29 +1099,25 @@
     *
     * return  Logical OR value of the ref _mcg_status_flags_t.
     */
   -uint32_t CLOCK_GetStatusFlags(void)
   -{
   -    uint32_t ret  = 0U;
   +uint32_t
   +CLOCK_GetStatusFlags(void)
   +{
   +    uint32_t ret = 0U;
        uint8_t mcg_s = MCG->S;
    
   -    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U)
   -    {
   +    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0LostFlag;
        }
   -    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0InitFlag;
        }
   -    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK))
   -    {
   +    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK)) {
            ret |= (uint32_t)kMCG_RtcOscLostFlag;
        }
   -    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LostFlag;
        }
   -    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LockFlag;
        }
        return ret;
   @@ -1193,21 +1139,19 @@
     * param mask The status flags to clear. This is a logical OR of members of the
     *             enumeration ref _mcg_status_flags_t.
     */
   -void CLOCK_ClearStatusFlags(uint32_t mask)
   +void
   +CLOCK_ClearStatusFlags(uint32_t mask)
    {
        uint8_t reg;
    
   -    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL) {
            MCG->SC &= (uint8_t)(~MCG_SC_ATMF_MASK);
        }
   -    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag))
   -    {
   -        reg     = MCG->C8;
   +    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag)) {
   +        reg = MCG->C8;
            MCG->C8 = reg;
        }
   -    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL) {
            MCG->S = MCG_S_LOLS0_MASK;
        }
    }
   @@ -1219,7 +1163,8 @@
     *
     * param  config Pointer to the OSC0 configuration structure.
     */
   -void CLOCK_InitOsc0(osc_config_t const *config)
   +void
   +CLOCK_InitOsc0(osc_config_t const *config)
    {
        uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq);
    
   @@ -1228,11 +1173,9 @@
        MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode);
        OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
    
   -    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U))
   -    {
   +    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)) {
            /* Wait for stable. */
   -        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -        {
   +        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
            }
        }
    }
   @@ -1242,7 +1185,8 @@
     *
     * This function deinitializes the OSC0.
     */
   -void CLOCK_DeinitOsc0(void)
   +void
   +CLOCK_DeinitOsc0(void)
    {
        OSC0->CR = 0U;
        MCG->C2 &= ~(uint8_t)OSC_MODE_MASK;
   @@ -1253,7 +1197,8 @@
     *
     * param freq The Slow IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetSlowIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetSlowIrcFreq(uint32_t freq)
    {
        s_slowIrcFreq = freq;
    }
   @@ -1263,7 +1208,8 @@
     *
     * param freq The Fast IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetFastIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetFastIrcFreq(uint32_t freq)
    {
        s_fastIrcFreq = freq;
    }
   @@ -1286,7 +1232,8 @@
     * retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
     * retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
     */
   -status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
   +status_t
   +CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
    {
        uint32_t multi; /* extFreq / desireFreq */
        uint32_t actv;  /* Auto trim value. */
   @@ -1299,30 +1246,24 @@
            {TRIM_FIRC_MIN, TRIM_FIRC_MAX}  /* Fast IRC. */
        };
    
   -    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN))
   -    {
   +    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) {
            status = kStatus_MCG_AtmBusClockInvalid;
        }
        /* Check desired frequency range. */
   -    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1]))
   -    {
   +    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) {
            status = kStatus_MCG_AtmDesiredFreqInvalid;
        }
        /*
           Make sure internal reference clock is not used to generate bus clock.
           Here only need to check (MCG_S_IREFST == 1).
         */
   -    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK))
   -    {
   +    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) {
            status = kStatus_MCG_AtmIrcUsed;
   -    }
   -    else
   -    {
   +    } else   {
            multi = extFreq / desireFreq;
   -        actv  = multi * 21U;
   -
   -        if (kMCG_AtmSel4m == atms)
   -        {
   +        actv = multi * 21U;
   +
   +        if (kMCG_AtmSel4m == atms) {
                actv *= 128U;
            }
    
   @@ -1336,27 +1277,20 @@
            MCG->SC = (mcg_sc | MCG_SC_ATME_MASK);
    
            /* Wait for MCG finished. */
   -        while (0U != (MCG->SC & MCG_SC_ATME_MASK))
   -        {
   +        while (0U != (MCG->SC & MCG_SC_ATME_MASK)) {
            }
    
            /* Error occurs? */
   -        if (0U != (MCG->SC & MCG_SC_ATMF_MASK))
   -        {
   +        if (0U != (MCG->SC & MCG_SC_ATMF_MASK)) {
                /* Clear the failed flag. */
                MCG->SC = mcg_sc;
   -            status  = kStatus_MCG_AtmHardwareFail;
   -        }
   -        else
   -        {
   +            status = kStatus_MCG_AtmHardwareFail;
   +        } else   {
                *actualFreq = extFreq / multi;
    
   -            if (kMCG_AtmSel4m == atms)
   -            {
   +            if (kMCG_AtmSel4m == atms) {
                    s_fastIrcFreq = *actualFreq;
   -            }
   -            else
   -            {
   +            } else   {
                    s_slowIrcFreq = *actualFreq;
                }
            }
   @@ -1372,103 +1306,83 @@
     *
     * return Current MCG mode or error code; See ref mcg_mode_t.
     */
   -mcg_mode_t CLOCK_GetMode(void)
   +mcg_mode_t
   +CLOCK_GetMode(void)
    {
        mcg_mode_t mode = kMCG_ModeError;
   -    uint32_t clkst  = (uint32_t)MCG_S_CLKST_VAL;
   +    uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
        uint32_t irefst = (uint32_t)MCG_S_IREFST_VAL;
   -    uint32_t lp     = (uint32_t)MCG_C2_LP_VAL;
   -    uint32_t pllst  = MCG_S_PLLST_VAL;
   +    uint32_t lp = (uint32_t)MCG_C2_LP_VAL;
   +    uint32_t pllst = MCG_S_PLLST_VAL;
    
        /*------------------------------------------------------------------
                               Mode and Registers
   -    ____________________________________________________________________
   -
   -      Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   -    ____________________________________________________________________
   -
   -      FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -      PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   -    ____________________________________________________________________
   -
   -      PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -    ----------------------------------------------------------------------*/
   -
   -    if (clkst == (uint32_t)kMCG_ClkOutStatFll)
   -    {
   -        if ((uint32_t)kMCG_FllSrcExternal == irefst)
   -        {
   +       ____________________________________________________________________
   +
   +       Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   +       ____________________________________________________________________
   +
   +       FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   +       ____________________________________________________________________
   +
   +       PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       ----------------------------------------------------------------------*/
   +
   +    if (clkst == (uint32_t)kMCG_ClkOutStatFll) {
   +        if ((uint32_t)kMCG_FllSrcExternal == irefst) {
                mode = kMCG_ModeFEE;
   -        }
   -        else
   -        {
   +        } else   {
                mode = kMCG_ModeFEI;
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatInt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatInt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPI;
   -        }
   -        else
   -        {
   +        } else   {
                {
                    mode = kMCG_ModeFBI;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatExt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatExt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPE;
   -        }
   -        else
   -        {
   -            if ((uint32_t)kMCG_PllstPll == pllst)
   -            {
   +        } else   {
   +            if ((uint32_t)kMCG_PllstPll == pllst) {
                    mode = kMCG_ModePBE;
   -            }
   -            else
   -            {
   +            } else   {
                    mode = kMCG_ModeFBE;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatPll)
   -    {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatPll)   {
            {
                mode = kMCG_ModePEE;
            }
   -    }
   -    else
   -    {
   +    } else   {
            /*do nothing*/
        }
    
   @@ -1490,15 +1404,15 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to a frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode)))
   -    {
   +    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1510,8 +1424,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1523,13 +1436,11 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1538,13 +1449,11 @@
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1566,15 +1475,15 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode)))
   -    {
   +    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1586,8 +1495,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1600,45 +1508,37 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
        /* Set DRS and DMX32. */
   -    mcg_c4  = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
   +    mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
        MCG->C4 = mcg_c4;
    
        /* Wait for DRST_DRS update. */
   -    while (MCG->C4 != mcg_c4)
   -    {
   +    while (MCG->C4 != mcg_c4) {
        }
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1661,7 +1561,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1670,9 +1571,7 @@
        mcg_mode_t mode = CLOCK_GetMode();
    
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModeBLPI == mode)))
   -
   -    {
   +          (kMCG_ModeBLPI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1687,8 +1586,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1700,26 +1598,22 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   -    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) {
        }
    
        MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1741,7 +1635,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1749,16 +1644,14 @@
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode)))
   -    {
   +          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
    
        /* Change to FLL mode. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Set LP bit to enable the FLL */
   @@ -1772,8 +1665,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1786,24 +1678,19 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for Reference clock Status bit to clear */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1812,13 +1699,11 @@
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for clock status bits to show clock source is ext ref clk */
   -    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for fll stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1834,11 +1719,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpiMode(void)
   +status_t
   +CLOCK_SetBlpiMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1858,11 +1743,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpeMode(void)
   +status_t
   +CLOCK_SetBlpeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1892,7 +1777,8 @@
     * configuration structure not necessary. In this case, pass in NULL.
     * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
     */
   -status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1907,14 +1793,12 @@
    
        /* Wait for CLKST clock status bits to show clock source is ext ref clk */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* Disable PLL first, then configure PLL. */
        MCG->C6 &= (uint8_t)(~MCG_C6_PLLS_MASK);
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Configure the PLL. */
   @@ -1926,8 +1810,7 @@
        MCG->C6 |= MCG_C6_PLLS_MASK;
    
        /* Wait for PLL mode changed. */
   -    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U) {
        }
    
        return kStatus_Success;
   @@ -1945,12 +1828,12 @@
     *       PRDIV/VDIV are different than in the PBE mode, set them up
     *       in PBE mode and wait. When the clock is stable, switch to PEE mode.
     */
   -status_t CLOCK_SetPeeMode(void)
   +status_t
   +CLOCK_SetPeeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (kMCG_ModePBE != mode)
   -    {
   +    if (kMCG_ModePBE != mode) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1959,8 +1842,7 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
    
        /* Wait for clock status bits to update */
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -1982,11 +1864,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
     */
   -status_t CLOCK_ExternalModeToFbeModeQuick(void)
   +status_t
   +CLOCK_ExternalModeToFbeModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) != 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) != 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1995,14 +1877,12 @@
        MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK);
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
        }
    
        /* Disable PLL. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        return kStatus_Success;
   @@ -2024,11 +1904,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
     */
   -status_t CLOCK_InternalModeToFbiModeQuick(void)
   +status_t
   +CLOCK_InternalModeToFbiModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) == 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) == 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif
   @@ -2037,8 +1917,7 @@
        MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        return kStatus_Success;
   @@ -2059,7 +1938,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
    }
   @@ -2079,8 +1959,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToFeeMode(
   -    mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeeMode(mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2100,15 +1980,15 @@
     * retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
   +status_t
   +CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
    {
        /* If reset mode is FEI mode, set MCGIRCLK and always success. */
        (void)CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
    
        /* If reset mode is not BLPI, first enter FBI mode. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        /* Enter BLPI mode. */
   @@ -2128,7 +2008,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2138,20 +2019,16 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* In FBE now, start to enter BLPE. */
   @@ -2173,7 +2050,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -2183,8 +2061,7 @@
    
        /* Change to use PLL output clock. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -2233,7 +2110,8 @@
     * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
     * function.
     */
   -status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
   +status_t
   +CLOCK_SetMcgConfig(const mcg_config_t *config)
    {
        mcg_mode_t next_mode;
        status_t status = kStatus_Success;
   @@ -2241,11 +2119,9 @@
        mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0;
    
        /* If need to change external clock, MCG_C7[OSCSEL]. */
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel))
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel)) {
            /* If external clock is in use, change to FEI first. */
   -        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -        {
   +        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
                (void)CLOCK_ExternalModeToFbeModeQuick();
                (void)CLOCK_SetFeiMode(config->dmx32, config->drs, NULL);
            }
   @@ -2254,8 +2130,7 @@
        }
    
        /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
   -    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt) {
            MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */
    
            {
   @@ -2268,67 +2143,56 @@
    
        next_mode = CLOCK_GetMode();
    
   -    do
   -    {
   +    do{
            next_mode = mcgModeMatrix[next_mode][config->mcgMode];
    
   -        switch (next_mode)
   -        {
   -            case kMCG_ModeFEI:
   -                status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFEE:
   -                status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFBI:
   -                status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeFBE:
   -                status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeBLPI:
   -                status = CLOCK_SetBlpiMode();
   -                break;
   -            case kMCG_ModeBLPE:
   -                status = CLOCK_SetBlpeMode();
   -                break;
   -            case kMCG_ModePBE:
   -                /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   -                if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode))
   +        switch (next_mode) {
   +        case kMCG_ModeFEI:
   +            status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFEE:
   +            status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFBI:
   +            status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeFBE:
   +            status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeBLPI:
   +            status = CLOCK_SetBlpiMode();
   +            break;
   +        case kMCG_ModeBLPE:
   +            status = CLOCK_SetBlpeMode();
   +            break;
   +        case kMCG_ModePBE:
   +            /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   +            if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) {
                    {
   -                    {
   -                        status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
   -                    }
   +                    status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
                    }
   -                else
   -                {
   -                    MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -                    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -                    {
   -                    }
   +            } else   {
   +                MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   +                while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
                    }
   -                break;
   -            case kMCG_ModePEE:
   -                status = CLOCK_SetPeeMode();
   -                break;
   -            default:
   -                assert(false);
   -                break;
   -        }
   -        if (kStatus_Success != status)
   -        {
   +            }
                break;
   +        case kMCG_ModePEE:
   +            status = CLOCK_SetPeeMode();
   +            break;
   +        default:
   +            assert(false);
   +            break;
   +        }
   +        if (kStatus_Success != status) {
   +            break;
            }
        } while (next_mode != config->mcgMode);
    
   -    if (status == kStatus_Success)
   -    {
   -        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U)
   -        {
   +    if (status == kStatus_Success) {
   +        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U) {
                CLOCK_EnablePll0(&config->pll0Config);
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/include/hal_lpuart_nxp.h
   <details>
   
   ```diff
   @@ -21,7 +21,7 @@
    #define __MCU_K8XF_HAL_UART_H_
    
    #ifdef __cplusplus
   - extern "C" {
   +extern "C" {
    #endif
    
    #define NXP_UART_EXISTS      { 1, \
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/include/mcu/kinetis_common.h
   <details>
   
   ```diff
   @@ -21,7 +21,7 @@
    #define __KINETIS_COMMON_H_
    
    #ifdef __cplusplus
   - extern "C" {
   +extern "C" {
    #endif
    
    #if MYNEWT_VAL(BSP_MK64F12)
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/include/mcu/kinetis_hal.h
   <details>
   
   ```diff
   @@ -21,7 +21,7 @@
    #define __KINETIS_HAL_H_
    
    #ifdef __cplusplus
   - extern "C" {
   +extern "C" {
    #endif
    
    struct nxp_hal_i2c_cfg {
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_flash.c
   <details>
   
   ```diff
   @@ -6,7 +6,7 @@
     * to you under the Apache License, Version 2.0 (the
     * "License"); you may not use this file except in compliance
     * with the License.  You may obtain a copy of the License at
   -*
   + *
     *  http://www.apache.org/licenses/LICENSE-2.0
     *
     * Unless required by applicable law or agreed to in writing,
   @@ -40,13 +40,13 @@
    #define KINETIS_FLASH_ALIGN MYNEWT_VAL(MCU_FLASH_MIN_WRITE_SIZE)
    
    static int kinetis_flash_read(const struct hal_flash *dev, uint32_t address,
   -        void *dst, uint32_t num_bytes);
   +                              void *dst, uint32_t num_bytes);
    static int kinetis_flash_write(const struct hal_flash *dev, uint32_t address,
   -        const void *src, uint32_t num_bytes);
   +                               const void *src, uint32_t num_bytes);
    static int kinetis_flash_erase_sector(const struct hal_flash *dev,
   -        uint32_t sector_address);
   +                                      uint32_t sector_address);
    static int kinetis_flash_sector_info(const struct hal_flash *dev, int idx,
   -        uint32_t *addr, uint32_t *sz);
   +                                     uint32_t *addr, uint32_t *sz);
    static int kinetis_flash_init(const struct hal_flash *dev);
    
    static const struct hal_flash_funcs kinetis_flash_funcs = {
   @@ -68,9 +68,9 @@
    
    static int
    kinetis_flash_read(const struct hal_flash *dev,
   -                 uint32_t address,
   -                 void *dst,
   -                 uint32_t num_bytes)
   +                   uint32_t address,
   +                   void *dst,
   +                   uint32_t num_bytes)
    {
        memcpy(dst, (void *)address, num_bytes);
        return 0;
   @@ -78,9 +78,9 @@
    
    static int
    kinetis_flash_write(const struct hal_flash *dev,
   -                  uint32_t address,
   -                  const void *src,
   -                  uint32_t len)
   +                    uint32_t address,
   +                    const void *src,
   +                    uint32_t len)
    {
        uint8_t padded[KINETIS_FLASH_ALIGN];
        uint8_t pad_len;
   @@ -142,9 +142,9 @@
    
    static int
    kinetis_flash_sector_info(const struct hal_flash *dev,
   -                        int idx,
   -                        uint32_t *addr,
   -                        uint32_t *sz)
   +                          int idx,
   +                          uint32_t *addr,
   +                          uint32_t *sz)
    {
        uint32_t sector_size;
        FLASH_GetProperty(&kinetis_config,
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_gpio.c
   <details>
   
   ```diff
   @@ -53,8 +53,7 @@
    uint16_t
    hal_to_fsl_pull(hal_gpio_pull_t pull)
    {
   -    switch ((int)pull)
   -    {
   +    switch ((int)pull) {
        case HAL_GPIO_PULL_UP:
            return kPORT_PullUp;
        case HAL_GPIO_PULL_DOWN:
   @@ -304,9 +303,9 @@
    #endif
            memset(&hal_gpio_irqs[entry], 0, sizeof(struct hal_gpio_irq));
            if (hal_gpio_find_port(GPIO_PORT(pin)) < 0) {
   -                NVIC_ClearPendingIRQ(GPIO_PORT(pin));
   -                NVIC_DisableIRQ(GPIO_PORT(pin));
   -            }
   +            NVIC_ClearPendingIRQ(GPIO_PORT(pin));
   +            NVIC_DisableIRQ(GPIO_PORT(pin));
   +        }
        }
    }
    
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_i2c.c
   <details>
   
   ```diff
   @@ -33,10 +33,10 @@
    #define NXP_HAL_I2C_MAX 4
    
    struct nxp_hal_i2c {
   -    I2C_Type* dev;
   +    I2C_Type * dev;
        uint32_t scl_pin;
        uint32_t sda_pin;
   -    PORT_Type *port; 
   +    PORT_Type *port;
        port_mux_t mux;
        IRQn_Type irqn;
        void (*irq_handler)(void);
   @@ -170,7 +170,7 @@
        os_sem_release(&i2c->sync);
    }
    
   -static struct nxp_hal_i2c*
   +static struct nxp_hal_i2c *
    hal_i2c_resolve(uint8_t i2c_num)
    {
        if (i2c_num >= NXP_HAL_I2C_MAX) {
   @@ -289,7 +289,7 @@
    
        i2c = hal_i2c_resolve(i2c_num);
        if (!i2c) {
   -       return HAL_I2C_ERR_INVAL;
   +        return HAL_I2C_ERR_INVAL;
        }
    
        return i2c_config(i2c, cfg->frequency);
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_lpuart.c
   <details>
   
   ```diff
   @@ -50,22 +50,22 @@
    };
    
    struct hal_uart {
   -    LPUART_Type      *u_base;
   -    clock_name_t     clk_src;
   -    uint32_t         u_irq;
   -    PORT_Type       *p_base;
   -    clock_ip_name_t  p_clock;
   -    int  u_pin_rx;
   -    int  u_pin_tx;
   +    LPUART_Type *u_base;
   +    clock_name_t clk_src;
   +    uint32_t u_irq;
   +    PORT_Type *p_base;
   +    clock_ip_name_t p_clock;
   +    int u_pin_rx;
   +    int u_pin_tx;
        /* TODO: support flow control pins */
        hal_uart_rx_char u_rx_func;
        hal_uart_tx_char u_tx_func;
        hal_uart_tx_done u_tx_done;
        void *u_func_arg;
   -    uint8_t u_configured:1;
   -    uint8_t u_open:1;
   -    uint8_t u_tx_started:1;
   -    uint8_t u_rx_stall:1;
   +    uint8_t u_configured : 1;
   +    uint8_t u_open : 1;
   +    uint8_t u_tx_started : 1;
   +    uint8_t u_rx_stall : 1;
        struct uart_ring ur_tx;
        uint8_t tx_buffer[TX_BUF_SZ];
        struct uart_ring ur_rx;
   @@ -98,17 +98,20 @@
     * RING BUFFER FUNCTIONS
     */
    
   -static uint8_t ur_is_empty(struct uart_ring *ur)
   +static uint8_t
   +ur_is_empty(struct uart_ring *ur)
    {
        return (ur->ur_head == ur->ur_tail);
    }
    
   -static uint8_t ur_is_full(struct uart_ring *ur)
   +static uint8_t
   +ur_is_full(struct uart_ring *ur)
    {
        return (((ur->ur_tail + 1) % ur->ur_size) == ur->ur_head);
    }
    
   -static void ur_bump(struct uart_ring *ur)
   +static void
   +ur_bump(struct uart_ring *ur)
    {
        if (!ur_is_empty(ur)) {
            ur->ur_head++;
   @@ -117,12 +120,14 @@
        }
    }
    
   -static uint8_t ur_read(struct uart_ring *ur)
   +static uint8_t
   +ur_read(struct uart_ring *ur)
    {
        return ur->ur_buf[ur->ur_head];
    }
    
   -static int ur_queue(struct uart_ring *ur, uint8_t data)
   +static int
   +ur_queue(struct uart_ring *ur, uint8_t data)
    {
        if (!ur_is_full(ur)) {
            ur->ur_buf[ur->ur_tail] = data;
   @@ -137,11 +142,12 @@
     * END RING BUFFER FUNCTIONS
     */
    
   -int hal_uart_init_cbs(int port,
   -                      hal_uart_tx_char tx_func,
   -                      hal_uart_tx_done tx_done,
   -                      hal_uart_rx_char rx_func,
   -                      void *arg)
   +int
   +hal_uart_init_cbs(int port,
   +                  hal_uart_tx_char tx_func,
   +                  hal_uart_tx_done tx_done,
   +                  hal_uart_rx_char rx_func,
   +                  void *arg)
    {
        struct hal_uart *u;
    
   @@ -157,7 +163,8 @@
        return 0;
    }
    
   -void hal_uart_blocking_tx(int port, uint8_t byte)
   +void
   +hal_uart_blocking_tx(int port, uint8_t byte)
    {
        struct hal_uart *u;
    
   @@ -194,7 +201,8 @@
        return i;
    }
    
   -void hal_uart_start_tx(int port)
   +void
   +hal_uart_start_tx(int port)
    {
        struct hal_uart *u;
        int data = -1;
   @@ -209,8 +217,7 @@
        }
    
        /* main loop */
   -    while (true)
   -    {
   +    while (true) {
            /* add data to TX ring buffer */
            if (u->u_tx_started == 0) {
                rc = hal_uart_tx_fill_buf(u);
   @@ -293,8 +300,9 @@
            if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base)) {
                if (u->u_tx_started) {
                    u->u_tx_started = 0;
   -                if (u->u_tx_done)
   +                if (u->u_tx_done) {
                        u->u_tx_done(u->u_func_arg);
   +                }
                }
            }
        }
   @@ -434,24 +442,23 @@
    {
        if (s_uartExists[port]) {
            if (s_uartEnabled[port]) {
   -            uarts[port].u_base        = s_uartBases[port];
   -            uarts[port].clk_src       = s_uartClocks[port];
   -            uarts[port].u_irq         = s_uartIRQ[port];
   -            uarts[port].p_base        = s_uartPort[port];
   -            uarts[port].p_clock       = s_uartPortClocks[port];
   -            uarts[port].u_pin_rx      = s_uartPIN_RX[port];
   -            uarts[port].u_pin_tx      = s_uartPIN_TX[port];
   -            uarts[port].ur_tx.ur_buf  = uarts[port].tx_buffer;
   +            uarts[port].u_base = s_uartBases[port];
   +            uarts[port].clk_src = s_uartClocks[port];
   +            uarts[port].u_irq = s_uartIRQ[port];
   +            uarts[port].p_base = s_uartPort[port];
   +            uarts[port].p_clock = s_uartPortClocks[port];
   +            uarts[port].u_pin_rx = s_uartPIN_RX[port];
   +            uarts[port].u_pin_tx = s_uartPIN_TX[port];
   +            uarts[port].ur_tx.ur_buf = uarts[port].tx_buffer;
                uarts[port].ur_tx.ur_size = TX_BUF_SZ;
                uarts[port].ur_tx.ur_head = 0;
                uarts[port].ur_tx.ur_tail = 0;
   -            uarts[port].ur_rx.ur_buf  = uarts[port].rx_buffer;
   +            uarts[port].ur_rx.ur_buf = uarts[port].rx_buffer;
                uarts[port].ur_rx.ur_size = RX_BUF_SZ;
                uarts[port].ur_rx.ur_head = 0;
                uarts[port].ur_rx.ur_tail = 0;
   -            uarts[port].u_configured  = 1;
   -        }
   -        else {
   +            uarts[port].u_configured = 1;
   +        } else   {
                uarts[port].u_configured = 0;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_qspi.c
   <details>
   
   ```diff
   @@ -107,7 +107,8 @@
        [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
    
        /* Match MISRA rule */
   -    [63] = 0};
   +    [63] = 0
   +};
    
    qspi_flash_config_t g_qspi_flash_cfg = {
        .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
   @@ -132,15 +133,12 @@
    {
        uint32_t val = 0;
        /* Check WIP bit */
   -    do
   -    {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +    do{
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
            QSPI_ExecuteIPCommand(QuadSPI0, 12U);
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            val = QuadSPI0->RBDR[0];
            /* Clear ARDB area */
   @@ -151,19 +149,17 @@
    static void
    cmd_write_enable()
    {
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ExecuteIPCommand(QuadSPI0, 4U);
    }
    
    static void
   -read_page(uint32_t address, uint32_t* dst)
   +read_page(uint32_t address, uint32_t * dst)
    {
        int i;
   -    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
   -    {
   -        dst[i] = ((uint32_t*)address)[i];
   +    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++) {
   +        dst[i] = ((uint32_t *)address)[i];
        }
    }
    
   @@ -195,15 +191,13 @@
    {
        uint32_t leftLongWords = 0;
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
    
        QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
        cmd_write_enable();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
    
        /* First write some data into TXFIFO to prevent from underrun */
   @@ -219,8 +213,7 @@
    
        /* Wait until flash finished program */
        check_if_finished();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess)) {
        }
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   @@ -244,7 +237,7 @@
    
        npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        while (npages) {
   -        write_page(address, (uint32_t*) src);
   +        write_page(address, (uint32_t *) src);
            npages--;
            address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        }
   @@ -253,13 +246,12 @@
    
    static int
    nxp_qspi_erase_sector(const struct hal_flash *dev,
   -                         uint32_t sector_address)
   +                      uint32_t sector_address)
    {
        sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
        sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
        QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
   @@ -286,8 +278,7 @@
        nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
        while (nsects) {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
            QSPI_SetIPCommandAddress(QuadSPI0, address);
   @@ -296,7 +287,7 @@
            check_if_finished();
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
   -    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   +        (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
            QSPI_ClearCache(QuadSPI0);
    #endif
            nsects--;
   @@ -323,8 +314,7 @@
    {
        uint32_t val[4] = {0x40U, 0, 0, 0};
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
    
   @@ -373,7 +363,7 @@
        PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB2), MYNEWT_VAL(QSPIB_MUX));
        PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOBA), MYNEWT_VAL(QSPIB_MUX));
    
   -    //Configure the baudrate too.
   +    /*Configure the baudrate too. */
    
        QSPI_Init(QuadSPI0, &qspi_cfg, CLOCK_GetFreq(kCLOCK_McgPll0Clk));
    
   @@ -390,21 +380,21 @@
    }
    
    static const struct hal_flash_funcs nxp_qspi_funcs = {
   -        .hff_read = nxp_qspi_read,
   -        .hff_write = nxp_qspi_write,
   -        .hff_erase_sector = nxp_qspi_erase_sector,
   -        .hff_sector_info = nxp_qspi_sector_info,
   -        .hff_init = nxp_qspi_init,
   -        .hff_erase = nxp_qspi_erase
   -    };
   +    .hff_read = nxp_qspi_read,
   +    .hff_write = nxp_qspi_write,
   +    .hff_erase_sector = nxp_qspi_erase_sector,
   +    .hff_sector_info = nxp_qspi_sector_info,
   +    .hff_init = nxp_qspi_init,
   +    .hff_erase = nxp_qspi_erase
   +};
    
    const struct hal_flash nxp_qspi_dev = {
   -        .hf_itf = &nxp_qspi_funcs,
   -        .hf_base_addr = FSL_FEATURE_QSPI_AMBA_BASE,
   -        .hf_size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE),
   -        .hf_sector_cnt = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT),
   -        .hf_align = 8,
   -        .hf_erased_val = 0xff,
   -    };
   -
   -#endif
   +    .hf_itf = &nxp_qspi_funcs,
   +    .hf_base_addr = FSL_FEATURE_QSPI_AMBA_BASE,
   +    .hf_size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE),
   +    .hf_sector_cnt = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT),
   +    .hf_align = 8,
   +    .hf_erased_val = 0xff,
   +};
   +
   +#endif
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_spi.c
   <details>
   
   ```diff
   @@ -38,7 +38,7 @@
    };
    
    struct nxp_hal_spi {
   -    SPI_Type* dev;
   +    SPI_Type * dev;
        uint32_t clk_pin;
        uint32_t pcs_pin;
        uint32_t sout_pin;
   @@ -48,7 +48,7 @@
        IRQn_Type irqn;
        void (*irq_handler)(void);
        hal_spi_txrx_cb txrx_cb;
   -    void* txrx_cb_arg;
   +    void * txrx_cb_arg;
        bool enabled;
        enum spi_type_t type;
    };
   @@ -265,7 +265,7 @@
    static void
    hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
    {
   -    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
   +    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
    
        if (status == kStatus_Success) {
            if (spi->txrx_cb) {
   @@ -277,7 +277,7 @@
    static void
    hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
    {
   -    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
   +    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
    
        if (status == kStatus_Success) {
            if (spi->txrx_cb) {
   @@ -293,7 +293,7 @@
        struct nxp_spi_master *master;
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   +        master = (struct nxp_spi_master *) spi;
            PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
   @@ -311,7 +311,7 @@
        struct nxp_spi_slave *slave;
    
        if (spi->type == HAL_SPI_TYPE_SLAVE) {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
   @@ -406,7 +406,7 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   +        master = (struct nxp_spi_master *) spi;
    
            master->config.ctarConfig.baudRate = settings->baudrate;
            master->config.ctarConfig.pcsToSckDelayInNanoSec =
   @@ -424,7 +424,7 @@
            master->config.ctarConfig.cpol = cpol;
            master->config.ctarConfig.cpha = cpha;
        } else {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            slave->config.ctarConfig.bitsPerFrame =
                (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
            slave->config.ctarConfig.cpol = cpol;
   @@ -448,13 +448,13 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -    master = (struct nxp_spi_master*) spi;
   -    DSPI_MasterInit(spi->dev,
   +        master = (struct nxp_spi_master *) spi;
   +        DSPI_MasterInit(spi->dev,
                        &master->config,
                        CLOCK_GetFreq(kCLOCK_BusClk));
        } else {
   -    slave = (struct nxp_spi_slave*) spi;
   -    DSPI_SlaveInit(spi->dev, &slave->config);
   +        slave = (struct nxp_spi_slave *) spi;
   +        DSPI_SlaveInit(spi->dev, &slave->config);
        }
    
        spi->enabled = true;
   @@ -496,8 +496,8 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        xfer.txData = (uint8_t*) &val;
   -        xfer.rxData = (uint8_t*) &retval;
   +        xfer.txData = (uint8_t *) &val;
   +        xfer.rxData = (uint8_t *) &retval;
            xfer.dataSize = 1;
            xfer.configFlags = kDSPI_MasterCtar0;
            DSPI_MasterTransferBlocking(spi->dev, &xfer);
   @@ -518,8 +518,8 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        xfer.txData = (uint8_t*) txbuf;
   -        xfer.rxData = (uint8_t*) rxbuf;
   +        xfer.txData = (uint8_t *) txbuf;
   +        xfer.rxData = (uint8_t *) rxbuf;
            xfer.dataSize = len;
            xfer.configFlags = kDSPI_MasterCtar0;
            rc = DSPI_MasterTransferBlocking(spi->dev, &xfer);
   @@ -556,26 +556,26 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   -        //master->handle
   +        master = (struct nxp_spi_master *) spi;
   +        /*master->handle */
            DSPI_MasterTransferCreateHandle(spi->dev,
                                            &master->handle,
                                            hal_spi_master_xfer_cb,
                                            spi);
            xfer.configFlags = kDSPI_MasterCtar0;
   -        xfer.txData = (uint8_t*) txbuf;
   -        xfer.rxData = (uint8_t*) rxbuf;
   +        xfer.txData = (uint8_t *) txbuf;
   +        xfer.rxData = (uint8_t *) rxbuf;
            xfer.dataSize = len;
            rc = DSPI_MasterTransferNonBlocking(spi->dev, &master->handle, &xfer);
        } else {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            DSPI_SlaveTransferCreateHandle(spi->dev,
                                           &slave->handle,
                                           hal_spi_slave_xfer_cb,
                                           spi);
            xfer.configFlags = kDSPI_SlaveCtar0;
   -        xfer.txData = (uint8_t*) txbuf;
   -        xfer.rxData = (uint8_t*) rxbuf;
   +        xfer.txData = (uint8_t *) txbuf;
   +        xfer.rxData = (uint8_t *) rxbuf;
            xfer.dataSize = len;
            rc = DSPI_SlaveTransferNonBlocking(spi->dev, &slave->handle, &xfer);
    
   @@ -614,10 +614,10 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   +        master = (struct nxp_spi_master *) spi;
            DSPI_MasterTransferAbort(spi->dev, &master->handle);
        } else {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            DSPI_SlaveTransferAbort(spi->dev, &slave->handle);
        }
        return 0;
   ```
   
   </details>
   
   #### hw/bsp/frdm-k64f/src/hal_bsp.c
   <details>
   
   ```diff
   @@ -98,7 +98,8 @@
        }
    };
    
   -static void init_hardware(void)
   +static void
   +init_hardware(void)
    {
        /* Disable the MPU otherwise USB cannot access the bus */
        SYSMPU->CESR = 0;
   ```
   
   </details>


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[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot removed a comment on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-773584274


   
   <!-- style-bot -->
   
   ## Style check summary
   
   ### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
   
   
   #### hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c
   <details>
   
   ```diff
   @@ -187,15 +187,15 @@
     ******************************************************************************/
    
    #ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
   -static void CLOCK_FllStableDelay(void)
   +static void
   +CLOCK_FllStableDelay(void)
    {
        /*
           Should wait at least 1ms. Because in these modes, the core clock is 100MHz
           at most, so this function could obtain the 1ms delay.
         */
        volatile uint32_t i = 30000U;
   -    while (0U != (i--))
   -    {
   +    while (0U != (i--)) {
            __NOP();
        }
    }
   @@ -207,34 +207,35 @@
    extern void CLOCK_FllStableDelay(void);
    #endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */
    
   -static uint32_t CLOCK_GetMcgExtClkFreq(void)
   +static uint32_t
   +CLOCK_GetMcgExtClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (MCG_C7_OSCSEL_VAL)
   -    {
   -        case 0U:
   -            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   -            assert(0U != g_xtal0Freq);
   -            freq = g_xtal0Freq;
   -            break;
   -        case 1U:
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(0U != g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 2U:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (MCG_C7_OSCSEL_VAL) {
   +    case 0U:
   +        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   +        assert(0U != g_xtal0Freq);
   +        freq = g_xtal0Freq;
   +        break;
   +    case 1U:
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(0U != g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 2U:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllExtRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllExtRefClkFreq(void)
    {
        /* FllExtRef = McgExtRef / FllExtRefDiv */
        uint8_t frdiv;
   @@ -246,54 +247,50 @@
        frdiv = MCG_C1_FRDIV_VAL;
        freq >>= frdiv;
    
   -    range  = MCG_C2_RANGE_VAL;
   +    range = MCG_C2_RANGE_VAL;
        oscsel = MCG_C7_OSCSEL_VAL;
    
        /*
           When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536.
           1. MCG_C7[OSCSEL] selects IRC48M.
           2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0.
   -    */
   -    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel))
   -    {
   -        switch (frdiv)
   -        {
   -            case 0:
   -            case 1:
   -            case 2:
   -            case 3:
   -            case 4:
   -            case 5:
   -                freq >>= 5u;
   -                break;
   -            case 6:
   -                /* 64*20=1280 */
   -                freq /= 20u;
   -                break;
   -            case 7:
   -                /* 128*12=1536 */
   -                freq /= 12u;
   -                break;
   -            default:
   -                freq = 0u;
   -                break;
   +     */
   +    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel)) {
   +        switch (frdiv) {
   +        case 0:
   +        case 1:
   +        case 2:
   +        case 3:
   +        case 4:
   +        case 5:
   +            freq >>= 5u;
   +            break;
   +        case 6:
   +            /* 64*20=1280 */
   +            freq /= 20u;
   +            break;
   +        case 7:
   +            /* 128*12=1536 */
   +            freq /= 12u;
   +            break;
   +        default:
   +            freq = 0u;
   +            break;
            }
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetInternalRefClkSelectFreq(void)
   +static uint32_t
   +CLOCK_GetInternalRefClkSelectFreq(void)
    {
        uint32_t freq;
    
   -    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL)
   -    {
   +    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL) {
            /* Slow internal reference clock selected*/
            freq = s_slowIrcFreq;
   -    }
   -    else
   -    {
   +    } else   {
            /* Fast internal reference clock selected*/
            freq = s_fastIrcFreq >> MCG_SC_FCRDIV_VAL;
        }
   @@ -301,44 +298,40 @@
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If use external reference clock. */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            freq = CLOCK_GetFllExtRefClkFreq();
        }
        /* If use internal reference clock. */
   -    else
   -    {
   +    else {
            freq = s_slowIrcFreq;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetPll0RefFreq(void)
   +static uint32_t
   +CLOCK_GetPll0RefFreq(void)
    {
        /* MCG external reference clock. */
        return CLOCK_GetMcgExtClkFreq();
    }
    
   -static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
   +static uint8_t
   +CLOCK_GetOscRangeFromFreq(uint32_t freq)
    {
        uint8_t range;
    
   -    if (freq <= 39063U)
   -    {
   +    if (freq <= 39063U) {
            range = 0U;
   -    }
   -    else if (freq <= 8000000U)
   -    {
   +    } else if (freq <= 8000000U)   {
            range = 1U;
   -    }
   -    else
   -    {
   +    } else   {
            range = 2U;
        }
    
   @@ -350,17 +343,15 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetOsc0ErClkFreq(void)
   +uint32_t
   +CLOCK_GetOsc0ErClkFreq(void)
    {
        uint32_t freq;
   -    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)
   -    {
   +    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U) {
            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
            assert(g_xtal0Freq);
            freq = g_xtal0Freq;
   -    }
   -    else
   -    {
   +    } else   {
            freq = 0U;
        }
    
   @@ -372,26 +363,26 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetEr32kClkFreq(void)
   +uint32_t
   +CLOCK_GetEr32kClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT1_OSC32KSEL_VAL)
   -    {
   -        case 0U: /* OSC 32k clock  */
   -            freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   -            break;
   -        case 2U: /* RTC 32k clock  */
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 3U: /* LPO clock      */
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT1_OSC32KSEL_VAL) {
   +    case 0U:     /* OSC 32k clock  */
   +        freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   +        break;
   +    case 2U:     /* RTC 32k clock  */
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 3U:     /* LPO clock      */
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
        return freq;
    }
   @@ -401,24 +392,24 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPllFllSelClkFreq(void)
   +uint32_t
   +CLOCK_GetPllFllSelClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT2_PLLFLLSEL_VAL)
   -    {
   -        case 0U: /* FLL. */
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case 1U: /* PLL. */
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case 3U: /* MCG IRC48M. */
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT2_PLLFLLSEL_VAL) {
   +    case 0U:     /* FLL. */
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case 1U:     /* PLL. */
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case 3U:     /* MCG IRC48M. */
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -429,7 +420,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPlatClkFreq(void)
   +uint32_t
   +CLOCK_GetPlatClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -439,7 +431,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlashClkFreq(void)
   +uint32_t
   +CLOCK_GetFlashClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
    }
   @@ -449,7 +442,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlexBusClkFreq(void)
   +uint32_t
   +CLOCK_GetFlexBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
    }
   @@ -459,7 +453,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetBusClkFreq(void)
   +uint32_t
   +CLOCK_GetBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
    }
   @@ -469,7 +464,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetCoreSysClkFreq(void)
   +uint32_t
   +CLOCK_GetCoreSysClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -484,55 +480,55 @@
     * param clockName Clock names defined in clock_name_t
     * return Clock frequency value in Hertz
     */
   -uint32_t CLOCK_GetFreq(clock_name_t clockName)
   +uint32_t
   +CLOCK_GetFreq(clock_name_t clockName)
    {
        uint32_t freq;
    
   -    switch (clockName)
   -    {
   -        case kCLOCK_CoreSysClk:
   -        case kCLOCK_PlatClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   -            break;
   -        case kCLOCK_BusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlexBusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlashClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   -            break;
   -        case kCLOCK_PllFllSelClk:
   -            freq = CLOCK_GetPllFllSelClkFreq();
   -            break;
   -        case kCLOCK_Er32kClk:
   -            freq = CLOCK_GetEr32kClkFreq();
   -            break;
   -        case kCLOCK_Osc0ErClk:
   -            freq = CLOCK_GetOsc0ErClkFreq();
   -            break;
   -        case kCLOCK_McgFixedFreqClk:
   -            freq = CLOCK_GetFixedFreqClkFreq();
   -            break;
   -        case kCLOCK_McgInternalRefClk:
   -            freq = CLOCK_GetInternalRefClkFreq();
   -            break;
   -        case kCLOCK_McgFllClk:
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case kCLOCK_McgPll0Clk:
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case kCLOCK_McgIrc48MClk:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        case kCLOCK_LpoClk:
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (clockName) {
   +    case kCLOCK_CoreSysClk:
   +    case kCLOCK_PlatClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   +        break;
   +    case kCLOCK_BusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlexBusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlashClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   +        break;
   +    case kCLOCK_PllFllSelClk:
   +        freq = CLOCK_GetPllFllSelClkFreq();
   +        break;
   +    case kCLOCK_Er32kClk:
   +        freq = CLOCK_GetEr32kClkFreq();
   +        break;
   +    case kCLOCK_Osc0ErClk:
   +        freq = CLOCK_GetOsc0ErClkFreq();
   +        break;
   +    case kCLOCK_McgFixedFreqClk:
   +        freq = CLOCK_GetFixedFreqClkFreq();
   +        break;
   +    case kCLOCK_McgInternalRefClk:
   +        freq = CLOCK_GetInternalRefClkFreq();
   +        break;
   +    case kCLOCK_McgFllClk:
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case kCLOCK_McgPll0Clk:
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case kCLOCK_McgIrc48MClk:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    case kCLOCK_LpoClk:
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -545,7 +541,8 @@
     *
     * param config Pointer to the configure structure.
     */
   -void CLOCK_SetSimConfig(sim_clock_config_t const *config)
   +void
   +CLOCK_SetSimConfig(sim_clock_config_t const *config)
    {
        SIM->CLKDIV1 = config->clkdiv1;
        CLOCK_SetPllFllSelClock(config->pllFllSel);
   @@ -559,35 +556,32 @@
     * retval true The clock is set successfully.
     * retval false The clock source is invalid to get proper USB FS clock.
     */
   -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
   +bool
   +CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
    {
        bool ret = true;
    
        CLOCK_DisableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcExt == src)
   -    {
   +    if (kCLOCK_UsbSrcExt == src) {
            SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
   -    }
   -    else
   -    {
   -        switch (freq)
   -        {
   -            case 120000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 96000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            case 72000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 48000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            default:
   -                ret = false;
   -                break;
   +    } else   {
   +        switch (freq) {
   +        case 120000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 96000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        case 72000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 48000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        default:
   +            ret = false;
   +            break;
            }
    
            SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src);
   @@ -595,8 +589,7 @@
    
        CLOCK_EnableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcIrc48M == src)
   -    {
   +    if (kCLOCK_UsbSrcIrc48M == src) {
            USB0->CLK_RECOVER_IRC_EN = 0x03U;
            USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
        }
   @@ -611,28 +604,28 @@
     *
     * return The frequency of MCGOUTCLK.
     */
   -uint32_t CLOCK_GetOutClkFreq(void)
   +uint32_t
   +CLOCK_GetOutClkFreq(void)
    {
        uint32_t mcgoutclk;
        uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
    
   -    switch (clkst)
   -    {
   -        case (uint32_t)kMCG_ClkOutStatPll:
   -            mcgoutclk = CLOCK_GetPll0Freq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatFll:
   -            mcgoutclk = CLOCK_GetFllFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatInt:
   -            mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatExt:
   -            mcgoutclk = CLOCK_GetMcgExtClkFreq();
   -            break;
   -        default:
   -            mcgoutclk = 0U;
   -            break;
   +    switch (clkst) {
   +    case (uint32_t)kMCG_ClkOutStatPll:
   +        mcgoutclk = CLOCK_GetPll0Freq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatFll:
   +        mcgoutclk = CLOCK_GetFllFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatInt:
   +        mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatExt:
   +        mcgoutclk = CLOCK_GetMcgExtClkFreq();
   +        break;
   +    default:
   +        mcgoutclk = 0U;
   +        break;
        }
    
        return mcgoutclk;
   @@ -647,7 +640,8 @@
     *
     * return The frequency of MCGFLLCLK.
     */
   -uint32_t CLOCK_GetFllFreq(void)
   +uint32_t
   +CLOCK_GetFllFreq(void)
    {
        static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}};
    
   @@ -656,23 +650,17 @@
        uint32_t ret;
    
        /* If FLL is not enabled currently, then return 0U. */
   -    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U)))
   -    {
   +    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) {
            ret = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            /* Get FLL reference clock frequency. */
            freq = CLOCK_GetFllRefClkFreq();
   -        if (0U == freq)
   -        {
   +        if (0U == freq) {
                ret = freq;
   -        }
   -        else
   -        {
   -            drs   = MCG_C4_DRST_DRS_VAL;
   +        } else   {
   +            drs = MCG_C4_DRST_DRS_VAL;
                dmx32 = MCG_C4_DMX32_VAL;
   -            ret   = freq * fllFactorTable[drs][dmx32];
   +            ret = freq * fllFactorTable[drs][dmx32];
            }
        }
    
   @@ -687,17 +675,15 @@
     *
     * return The frequency of MCGIRCLK.
     */
   -uint32_t CLOCK_GetInternalRefClkFreq(void)
   +uint32_t
   +CLOCK_GetInternalRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If MCGIRCLK is gated. */
   -    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK))
   -    {
   +    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            freq = CLOCK_GetInternalRefClkSelectFreq();
        }
    
   @@ -712,18 +698,16 @@
     *
     * return The frequency of MCGFFCLK.
     */
   -uint32_t CLOCK_GetFixedFreqClkFreq(void)
   +uint32_t
   +CLOCK_GetFixedFreqClkFreq(void)
    {
        uint32_t freq = CLOCK_GetFllRefClkFreq();
        uint32_t ret;
    
        /* MCGFFCLK must be no more than MCGOUTCLK/8. */
   -    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq))
   -    {
   +    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq)) {
            ret = freq;
   -    }
   -    else
   -    {
   +    } else   {
            ret = 0U;
        }
    
   @@ -738,7 +722,8 @@
     *
     * return The frequency of MCGPLL0CLK.
     */
   -uint32_t CLOCK_GetPll0Freq(void)
   +uint32_t
   +CLOCK_GetPll0Freq(void)
    {
        uint32_t mcgpll0clk;
        uint32_t freq;
   @@ -746,12 +731,9 @@
        uint8_t mcgpll0prdiv;
        uint8_t mcgpll0vdiv;
        /* If PLL0 is not enabled, return 0. */
   -    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            mcgpll0clk = CLOCK_GetPll0RefFreq();
    
            /*
   @@ -783,36 +765,31 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success External reference clock set successfully.
     */
   -status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
    {
        bool needDelay;
        uint32_t i;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */
   -    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK)))
   -    {
   +    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) {
            return kStatus_MCG_SourceUsed;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
    
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel)
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel) {
            /* If change OSCSEL, need to delay, ERR009878. */
            needDelay = true;
   -    }
   -    else
   -    {
   +    } else   {
            needDelay = false;
        }
    
        MCG->C7 = (uint8_t)(MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
   -    if (needDelay)
   -    {
   +    if (needDelay) {
            /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
            i = 1500U;
   -        while (0U != (i--))
   -        {
   +        while (0U != (i--)) {
                __NOP();
            }
        }
   @@ -836,34 +813,30 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success MCGIRCLK configuration finished successfully.
     */
   -status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
   +status_t
   +CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
    {
        uint32_t mcgOutClkState = (uint32_t)MCG_S_CLKST_VAL;
   -    mcg_irc_mode_t curIrcs  = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   -    uint8_t curFcrdiv       = MCG_SC_FCRDIV_VAL;
   +    mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   +    uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If MCGIRCLK is used as system clock source. */
   -    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState)
   -    {
   +    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState) {
            /* If need to change MCGIRCLK source or driver, return error. */
   -        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs))
   -        {
   +        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) {
                return kStatus_MCG_SourceUsed;
            }
        }
    #endif
    
        /* If need to update the FCRDIV. */
   -    if (fcrdiv != curFcrdiv)
   -    {
   +    if (fcrdiv != curFcrdiv) {
            /* If fast IRC is in use currently, change to slow IRC. */
            if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) &&
   -            (kMCG_IrcFast == curIrcs))
   -        {
   +            (kMCG_IrcFast == curIrcs)) {
                MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
   -            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow)
   -            {
   +            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow) {
                }
            }
            /* Update FCRDIV. */
   @@ -876,10 +849,8 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode);
    
        /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
   -    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable)))
   -    {
   -        while (MCG_S_IRCST_VAL != (uint8_t)ircs)
   -        {
   +    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable))) {
   +        while (MCG_S_IRCST_VAL != (uint8_t)ircs) {
            }
        }
    
   @@ -901,7 +872,8 @@
     * param vdiv       VDIV value to generate desired PLL frequency.
     * return Closest frequency match that the PLL was able generate.
     */
   -uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
   +uint32_t
   +CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
    {
        uint8_t ret_prdiv;               /* PRDIV to return. */
        uint8_t ret_vdiv;                /* VDIV to return.  */
   @@ -910,7 +882,7 @@
        uint8_t prdiv_cur;               /* PRDIV value for iteration.    */
        uint8_t vdiv_cur;                /* VDIV value for iteration.     */
        uint32_t ret_freq = 0U;          /* PLL output frequency to return. */
   -    uint32_t diff     = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */
   +    uint32_t diff = 0xFFFFFFFFU;     /* Difference between desireFreq and return frequency. */
        uint32_t ref_div;                /* Reference frequency after PRDIV. */
    
        /*
   @@ -929,8 +901,7 @@
        /* Reference frequency is out of range. */
        if ((refFreq < (uint32_t)FSL_FEATURE_MCG_PLL_REF_MIN) ||
            (refFreq > ((uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX *
   -                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE))))
   -    {
   +                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) {
            return 0U;
        }
    
   @@ -940,62 +911,52 @@
            (uint8_t)((refFreq + (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX);
    
        /* PRDIV traversal. */
   -    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--)
   -    {
   +    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) {
            /* Reference frequency after PRDIV. */
            ref_div = refFreq / prdiv_cur;
    
            vdiv_cur = (uint8_t)(desireFreq / ref_div);
    
            if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) ||
   -            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                /* No VDIV is available with this PRDIV. */
                continue;
            }
    
            ret_freq = vdiv_cur * ref_div;
    
   -        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE)
   -        {
   -            if (ret_freq == desireFreq) /* If desire frequency is got. */
   -            {
   +        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) {
   +            if (ret_freq == desireFreq) { /* If desire frequency is got. */
                    *prdiv = prdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -                *vdiv  = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +                *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
                    return ret_freq;
                }
                /* New PRDIV/VDIV is closer. */
   -            if (diff > desireFreq - ret_freq)
   -            {
   -                diff      = desireFreq - ret_freq;
   +            if (diff > desireFreq - ret_freq) {
   +                diff = desireFreq - ret_freq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
            vdiv_cur++;
   -        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                ret_freq += ref_div;
                /* New PRDIV/VDIV is closer. */
   -            if (diff > ret_freq - desireFreq)
   -            {
   -                diff      = ret_freq - desireFreq;
   +            if (diff > ret_freq - desireFreq) {
   +                diff = ret_freq - desireFreq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
        }
    
   -    if (0xFFFFFFFFU != diff)
   -    {
   +    if (0xFFFFFFFFU != diff) {
            /* PRDIV/VDIV found. */
   -        *prdiv   = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -        *vdiv    = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +        *prdiv = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   +        *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
            ret_freq = (refFreq / ret_prdiv) * ret_vdiv;
            return ret_freq;
   -    }
   -    else
   -    {
   +    } else   {
            /* No proper PRDIV/VDIV found. */
            return 0U;
        }
   @@ -1012,7 +973,8 @@
     *
     * param config Pointer to the configuration structure.
     */
   -void CLOCK_EnablePll0(mcg_pll_config_t const *config)
   +void
   +CLOCK_EnablePll0(mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1027,8 +989,7 @@
        MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode);
    
        /* Wait for PLL lock. */
   -    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
        }
    }
    
   @@ -1039,23 +1000,18 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
    {
        /* Clear the previous flag, MCG_SC[LOCS0]. */
        MCG->SC &= ~(uint8_t)MCG_SC_ATMF_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= ~(uint8_t)MCG_C6_CME0_MASK;
   -    }
   -    else
   -    {
   -        if (kMCG_MonitorInt == mode)
   -        {
   +    } else   {
   +        if (kMCG_MonitorInt == mode) {
                MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK;
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C2 |= MCG_C2_LOCRE0_MASK;
            }
            MCG->C6 |= MCG_C6_CME0_MASK;
   @@ -1069,16 +1025,15 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8 = MCG->C8;
    
        mcg_c8 &= ~(uint8_t)(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK);
    
   -    if (kMCG_MonitorNone != mode)
   -    {
   -        if (kMCG_MonitorReset == mode)
   -        {
   +    if (kMCG_MonitorNone != mode) {
   +        if (kMCG_MonitorReset == mode) {
                mcg_c8 |= MCG_C8_LOCRE1_MASK;
            }
            mcg_c8 |= MCG_C8_CME1_MASK;
   @@ -1093,29 +1048,24 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8;
    
        /* Clear previous flag. */
        MCG->S = MCG_S_LOLS0_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= (uint8_t)(~MCG_C6_LOLIE0_MASK);
   -    }
   -    else
   -    {
   +    } else   {
            mcg_c8 = MCG->C8;
    
            mcg_c8 &= (uint8_t)(~MCG_C8_LOCS1_MASK);
    
   -        if (kMCG_MonitorInt == mode)
   -        {
   +        if (kMCG_MonitorInt == mode) {
                mcg_c8 &= (uint8_t)(~MCG_C8_LOLRE_MASK);
   -        }
   -        else
   -        {
   +        } else   {
                mcg_c8 |= MCG_C8_LOLRE_MASK;
            }
            MCG->C8 = mcg_c8;
   @@ -1149,29 +1099,25 @@
     *
     * return  Logical OR value of the ref _mcg_status_flags_t.
     */
   -uint32_t CLOCK_GetStatusFlags(void)
   -{
   -    uint32_t ret  = 0U;
   +uint32_t
   +CLOCK_GetStatusFlags(void)
   +{
   +    uint32_t ret = 0U;
        uint8_t mcg_s = MCG->S;
    
   -    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U)
   -    {
   +    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0LostFlag;
        }
   -    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0InitFlag;
        }
   -    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK))
   -    {
   +    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK)) {
            ret |= (uint32_t)kMCG_RtcOscLostFlag;
        }
   -    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LostFlag;
        }
   -    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LockFlag;
        }
        return ret;
   @@ -1193,21 +1139,19 @@
     * param mask The status flags to clear. This is a logical OR of members of the
     *             enumeration ref _mcg_status_flags_t.
     */
   -void CLOCK_ClearStatusFlags(uint32_t mask)
   +void
   +CLOCK_ClearStatusFlags(uint32_t mask)
    {
        uint8_t reg;
    
   -    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL) {
            MCG->SC &= (uint8_t)(~MCG_SC_ATMF_MASK);
        }
   -    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag))
   -    {
   -        reg     = MCG->C8;
   +    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag)) {
   +        reg = MCG->C8;
            MCG->C8 = reg;
        }
   -    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL) {
            MCG->S = MCG_S_LOLS0_MASK;
        }
    }
   @@ -1219,7 +1163,8 @@
     *
     * param  config Pointer to the OSC0 configuration structure.
     */
   -void CLOCK_InitOsc0(osc_config_t const *config)
   +void
   +CLOCK_InitOsc0(osc_config_t const *config)
    {
        uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq);
    
   @@ -1228,11 +1173,9 @@
        MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode);
        OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
    
   -    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U))
   -    {
   +    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)) {
            /* Wait for stable. */
   -        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -        {
   +        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
            }
        }
    }
   @@ -1242,7 +1185,8 @@
     *
     * This function deinitializes the OSC0.
     */
   -void CLOCK_DeinitOsc0(void)
   +void
   +CLOCK_DeinitOsc0(void)
    {
        OSC0->CR = 0U;
        MCG->C2 &= ~(uint8_t)OSC_MODE_MASK;
   @@ -1253,7 +1197,8 @@
     *
     * param freq The Slow IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetSlowIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetSlowIrcFreq(uint32_t freq)
    {
        s_slowIrcFreq = freq;
    }
   @@ -1263,7 +1208,8 @@
     *
     * param freq The Fast IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetFastIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetFastIrcFreq(uint32_t freq)
    {
        s_fastIrcFreq = freq;
    }
   @@ -1286,7 +1232,8 @@
     * retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
     * retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
     */
   -status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
   +status_t
   +CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
    {
        uint32_t multi; /* extFreq / desireFreq */
        uint32_t actv;  /* Auto trim value. */
   @@ -1299,30 +1246,24 @@
            {TRIM_FIRC_MIN, TRIM_FIRC_MAX}  /* Fast IRC. */
        };
    
   -    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN))
   -    {
   +    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) {
            status = kStatus_MCG_AtmBusClockInvalid;
        }
        /* Check desired frequency range. */
   -    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1]))
   -    {
   +    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) {
            status = kStatus_MCG_AtmDesiredFreqInvalid;
        }
        /*
           Make sure internal reference clock is not used to generate bus clock.
           Here only need to check (MCG_S_IREFST == 1).
         */
   -    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK))
   -    {
   +    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) {
            status = kStatus_MCG_AtmIrcUsed;
   -    }
   -    else
   -    {
   +    } else   {
            multi = extFreq / desireFreq;
   -        actv  = multi * 21U;
   -
   -        if (kMCG_AtmSel4m == atms)
   -        {
   +        actv = multi * 21U;
   +
   +        if (kMCG_AtmSel4m == atms) {
                actv *= 128U;
            }
    
   @@ -1336,27 +1277,20 @@
            MCG->SC = (mcg_sc | MCG_SC_ATME_MASK);
    
            /* Wait for MCG finished. */
   -        while (0U != (MCG->SC & MCG_SC_ATME_MASK))
   -        {
   +        while (0U != (MCG->SC & MCG_SC_ATME_MASK)) {
            }
    
            /* Error occurs? */
   -        if (0U != (MCG->SC & MCG_SC_ATMF_MASK))
   -        {
   +        if (0U != (MCG->SC & MCG_SC_ATMF_MASK)) {
                /* Clear the failed flag. */
                MCG->SC = mcg_sc;
   -            status  = kStatus_MCG_AtmHardwareFail;
   -        }
   -        else
   -        {
   +            status = kStatus_MCG_AtmHardwareFail;
   +        } else   {
                *actualFreq = extFreq / multi;
    
   -            if (kMCG_AtmSel4m == atms)
   -            {
   +            if (kMCG_AtmSel4m == atms) {
                    s_fastIrcFreq = *actualFreq;
   -            }
   -            else
   -            {
   +            } else   {
                    s_slowIrcFreq = *actualFreq;
                }
            }
   @@ -1372,103 +1306,83 @@
     *
     * return Current MCG mode or error code; See ref mcg_mode_t.
     */
   -mcg_mode_t CLOCK_GetMode(void)
   +mcg_mode_t
   +CLOCK_GetMode(void)
    {
        mcg_mode_t mode = kMCG_ModeError;
   -    uint32_t clkst  = (uint32_t)MCG_S_CLKST_VAL;
   +    uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
        uint32_t irefst = (uint32_t)MCG_S_IREFST_VAL;
   -    uint32_t lp     = (uint32_t)MCG_C2_LP_VAL;
   -    uint32_t pllst  = MCG_S_PLLST_VAL;
   +    uint32_t lp = (uint32_t)MCG_C2_LP_VAL;
   +    uint32_t pllst = MCG_S_PLLST_VAL;
    
        /*------------------------------------------------------------------
                               Mode and Registers
   -    ____________________________________________________________________
   -
   -      Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   -    ____________________________________________________________________
   -
   -      FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -      PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   -    ____________________________________________________________________
   -
   -      PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -    ----------------------------------------------------------------------*/
   -
   -    if (clkst == (uint32_t)kMCG_ClkOutStatFll)
   -    {
   -        if ((uint32_t)kMCG_FllSrcExternal == irefst)
   -        {
   +       ____________________________________________________________________
   +
   +       Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   +       ____________________________________________________________________
   +
   +       FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   +       ____________________________________________________________________
   +
   +       PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       ----------------------------------------------------------------------*/
   +
   +    if (clkst == (uint32_t)kMCG_ClkOutStatFll) {
   +        if ((uint32_t)kMCG_FllSrcExternal == irefst) {
                mode = kMCG_ModeFEE;
   -        }
   -        else
   -        {
   +        } else   {
                mode = kMCG_ModeFEI;
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatInt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatInt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPI;
   -        }
   -        else
   -        {
   +        } else   {
                {
                    mode = kMCG_ModeFBI;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatExt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatExt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPE;
   -        }
   -        else
   -        {
   -            if ((uint32_t)kMCG_PllstPll == pllst)
   -            {
   +        } else   {
   +            if ((uint32_t)kMCG_PllstPll == pllst) {
                    mode = kMCG_ModePBE;
   -            }
   -            else
   -            {
   +            } else   {
                    mode = kMCG_ModeFBE;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatPll)
   -    {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatPll)   {
            {
                mode = kMCG_ModePEE;
            }
   -    }
   -    else
   -    {
   +    } else   {
            /*do nothing*/
        }
    
   @@ -1490,15 +1404,15 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to a frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode)))
   -    {
   +    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1510,8 +1424,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1523,13 +1436,11 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1538,13 +1449,11 @@
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1566,15 +1475,15 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode)))
   -    {
   +    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1586,8 +1495,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1600,45 +1508,37 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
        /* Set DRS and DMX32. */
   -    mcg_c4  = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
   +    mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
        MCG->C4 = mcg_c4;
    
        /* Wait for DRST_DRS update. */
   -    while (MCG->C4 != mcg_c4)
   -    {
   +    while (MCG->C4 != mcg_c4) {
        }
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1661,7 +1561,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1670,9 +1571,7 @@
        mcg_mode_t mode = CLOCK_GetMode();
    
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModeBLPI == mode)))
   -
   -    {
   +          (kMCG_ModeBLPI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1687,8 +1586,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1700,26 +1598,22 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   -    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) {
        }
    
        MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1741,7 +1635,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1749,16 +1644,14 @@
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode)))
   -    {
   +          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
    
        /* Change to FLL mode. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Set LP bit to enable the FLL */
   @@ -1772,8 +1665,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1786,24 +1678,19 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for Reference clock Status bit to clear */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1812,13 +1699,11 @@
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for clock status bits to show clock source is ext ref clk */
   -    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for fll stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1834,11 +1719,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpiMode(void)
   +status_t
   +CLOCK_SetBlpiMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1858,11 +1743,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpeMode(void)
   +status_t
   +CLOCK_SetBlpeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1892,7 +1777,8 @@
     * configuration structure not necessary. In this case, pass in NULL.
     * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
     */
   -status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1907,14 +1793,12 @@
    
        /* Wait for CLKST clock status bits to show clock source is ext ref clk */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* Disable PLL first, then configure PLL. */
        MCG->C6 &= (uint8_t)(~MCG_C6_PLLS_MASK);
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Configure the PLL. */
   @@ -1926,8 +1810,7 @@
        MCG->C6 |= MCG_C6_PLLS_MASK;
    
        /* Wait for PLL mode changed. */
   -    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U) {
        }
    
        return kStatus_Success;
   @@ -1945,12 +1828,12 @@
     *       PRDIV/VDIV are different than in the PBE mode, set them up
     *       in PBE mode and wait. When the clock is stable, switch to PEE mode.
     */
   -status_t CLOCK_SetPeeMode(void)
   +status_t
   +CLOCK_SetPeeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (kMCG_ModePBE != mode)
   -    {
   +    if (kMCG_ModePBE != mode) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1959,8 +1842,7 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
    
        /* Wait for clock status bits to update */
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -1982,11 +1864,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
     */
   -status_t CLOCK_ExternalModeToFbeModeQuick(void)
   +status_t
   +CLOCK_ExternalModeToFbeModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) != 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) != 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1995,14 +1877,12 @@
        MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK);
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
        }
    
        /* Disable PLL. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        return kStatus_Success;
   @@ -2024,11 +1904,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
     */
   -status_t CLOCK_InternalModeToFbiModeQuick(void)
   +status_t
   +CLOCK_InternalModeToFbiModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) == 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) == 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif
   @@ -2037,8 +1917,7 @@
        MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        return kStatus_Success;
   @@ -2059,7 +1938,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
    }
   @@ -2079,8 +1959,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToFeeMode(
   -    mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeeMode(mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2100,15 +1980,15 @@
     * retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
   +status_t
   +CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
    {
        /* If reset mode is FEI mode, set MCGIRCLK and always success. */
        (void)CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
    
        /* If reset mode is not BLPI, first enter FBI mode. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        /* Enter BLPI mode. */
   @@ -2128,7 +2008,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2138,20 +2019,16 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* In FBE now, start to enter BLPE. */
   @@ -2173,7 +2050,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -2183,8 +2061,7 @@
    
        /* Change to use PLL output clock. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -2233,7 +2110,8 @@
     * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
     * function.
     */
   -status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
   +status_t
   +CLOCK_SetMcgConfig(const mcg_config_t *config)
    {
        mcg_mode_t next_mode;
        status_t status = kStatus_Success;
   @@ -2241,11 +2119,9 @@
        mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0;
    
        /* If need to change external clock, MCG_C7[OSCSEL]. */
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel))
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel)) {
            /* If external clock is in use, change to FEI first. */
   -        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -        {
   +        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
                (void)CLOCK_ExternalModeToFbeModeQuick();
                (void)CLOCK_SetFeiMode(config->dmx32, config->drs, NULL);
            }
   @@ -2254,8 +2130,7 @@
        }
    
        /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
   -    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt) {
            MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */
    
            {
   @@ -2268,67 +2143,56 @@
    
        next_mode = CLOCK_GetMode();
    
   -    do
   -    {
   +    do{
            next_mode = mcgModeMatrix[next_mode][config->mcgMode];
    
   -        switch (next_mode)
   -        {
   -            case kMCG_ModeFEI:
   -                status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFEE:
   -                status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFBI:
   -                status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeFBE:
   -                status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeBLPI:
   -                status = CLOCK_SetBlpiMode();
   -                break;
   -            case kMCG_ModeBLPE:
   -                status = CLOCK_SetBlpeMode();
   -                break;
   -            case kMCG_ModePBE:
   -                /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   -                if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode))
   +        switch (next_mode) {
   +        case kMCG_ModeFEI:
   +            status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFEE:
   +            status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFBI:
   +            status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeFBE:
   +            status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeBLPI:
   +            status = CLOCK_SetBlpiMode();
   +            break;
   +        case kMCG_ModeBLPE:
   +            status = CLOCK_SetBlpeMode();
   +            break;
   +        case kMCG_ModePBE:
   +            /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   +            if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) {
                    {
   -                    {
   -                        status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
   -                    }
   +                    status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
                    }
   -                else
   -                {
   -                    MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -                    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -                    {
   -                    }
   +            } else   {
   +                MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   +                while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
                    }
   -                break;
   -            case kMCG_ModePEE:
   -                status = CLOCK_SetPeeMode();
   -                break;
   -            default:
   -                assert(false);
   -                break;
   -        }
   -        if (kStatus_Success != status)
   -        {
   +            }
                break;
   +        case kMCG_ModePEE:
   +            status = CLOCK_SetPeeMode();
   +            break;
   +        default:
   +            assert(false);
   +            break;
   +        }
   +        if (kStatus_Success != status) {
   +            break;
            }
        } while (next_mode != config->mcgMode);
    
   -    if (status == kStatus_Success)
   -    {
   -        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U)
   -        {
   +    if (status == kStatus_Success) {
   +        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U) {
                CLOCK_EnablePll0(&config->pll0Config);
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_qspi.c
   <details>
   
   ```diff
   @@ -133,7 +133,7 @@
    {
        int i;
        for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++) {
   -        dst[i] = ((uint32_t*)address)[i];
   +        dst[i] = ((uint32_t *)address)[i];
        }
    }
    
   ```
   
   </details>


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[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
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[GitHub] [mynewt-core] utzig commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
utzig commented on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-773691606


   @mlaz I am fine with this now, please force-push again to check if not RAT issues remain, for some reason it was no updating the message.


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[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

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   ## Style check summary
   
   ### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
   
   
   #### hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c
   <details>
   
   ```diff
   @@ -187,15 +187,15 @@
     ******************************************************************************/
    
    #ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
   -static void CLOCK_FllStableDelay(void)
   +static void
   +CLOCK_FllStableDelay(void)
    {
        /*
           Should wait at least 1ms. Because in these modes, the core clock is 100MHz
           at most, so this function could obtain the 1ms delay.
         */
        volatile uint32_t i = 30000U;
   -    while (0U != (i--))
   -    {
   +    while (0U != (i--)) {
            __NOP();
        }
    }
   @@ -207,34 +207,35 @@
    extern void CLOCK_FllStableDelay(void);
    #endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */
    
   -static uint32_t CLOCK_GetMcgExtClkFreq(void)
   +static uint32_t
   +CLOCK_GetMcgExtClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (MCG_C7_OSCSEL_VAL)
   -    {
   -        case 0U:
   -            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   -            assert(0U != g_xtal0Freq);
   -            freq = g_xtal0Freq;
   -            break;
   -        case 1U:
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(0U != g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 2U:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (MCG_C7_OSCSEL_VAL) {
   +    case 0U:
   +        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   +        assert(0U != g_xtal0Freq);
   +        freq = g_xtal0Freq;
   +        break;
   +    case 1U:
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(0U != g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 2U:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllExtRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllExtRefClkFreq(void)
    {
        /* FllExtRef = McgExtRef / FllExtRefDiv */
        uint8_t frdiv;
   @@ -246,54 +247,50 @@
        frdiv = MCG_C1_FRDIV_VAL;
        freq >>= frdiv;
    
   -    range  = MCG_C2_RANGE_VAL;
   +    range = MCG_C2_RANGE_VAL;
        oscsel = MCG_C7_OSCSEL_VAL;
    
        /*
           When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536.
           1. MCG_C7[OSCSEL] selects IRC48M.
           2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0.
   -    */
   -    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel))
   -    {
   -        switch (frdiv)
   -        {
   -            case 0:
   -            case 1:
   -            case 2:
   -            case 3:
   -            case 4:
   -            case 5:
   -                freq >>= 5u;
   -                break;
   -            case 6:
   -                /* 64*20=1280 */
   -                freq /= 20u;
   -                break;
   -            case 7:
   -                /* 128*12=1536 */
   -                freq /= 12u;
   -                break;
   -            default:
   -                freq = 0u;
   -                break;
   +     */
   +    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel)) {
   +        switch (frdiv) {
   +        case 0:
   +        case 1:
   +        case 2:
   +        case 3:
   +        case 4:
   +        case 5:
   +            freq >>= 5u;
   +            break;
   +        case 6:
   +            /* 64*20=1280 */
   +            freq /= 20u;
   +            break;
   +        case 7:
   +            /* 128*12=1536 */
   +            freq /= 12u;
   +            break;
   +        default:
   +            freq = 0u;
   +            break;
            }
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetInternalRefClkSelectFreq(void)
   +static uint32_t
   +CLOCK_GetInternalRefClkSelectFreq(void)
    {
        uint32_t freq;
    
   -    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL)
   -    {
   +    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL) {
            /* Slow internal reference clock selected*/
            freq = s_slowIrcFreq;
   -    }
   -    else
   -    {
   +    } else   {
            /* Fast internal reference clock selected*/
            freq = s_fastIrcFreq >> MCG_SC_FCRDIV_VAL;
        }
   @@ -301,44 +298,40 @@
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If use external reference clock. */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            freq = CLOCK_GetFllExtRefClkFreq();
        }
        /* If use internal reference clock. */
   -    else
   -    {
   +    else {
            freq = s_slowIrcFreq;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetPll0RefFreq(void)
   +static uint32_t
   +CLOCK_GetPll0RefFreq(void)
    {
        /* MCG external reference clock. */
        return CLOCK_GetMcgExtClkFreq();
    }
    
   -static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
   +static uint8_t
   +CLOCK_GetOscRangeFromFreq(uint32_t freq)
    {
        uint8_t range;
    
   -    if (freq <= 39063U)
   -    {
   +    if (freq <= 39063U) {
            range = 0U;
   -    }
   -    else if (freq <= 8000000U)
   -    {
   +    } else if (freq <= 8000000U)   {
            range = 1U;
   -    }
   -    else
   -    {
   +    } else   {
            range = 2U;
        }
    
   @@ -350,17 +343,15 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetOsc0ErClkFreq(void)
   +uint32_t
   +CLOCK_GetOsc0ErClkFreq(void)
    {
        uint32_t freq;
   -    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)
   -    {
   +    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U) {
            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
            assert(g_xtal0Freq);
            freq = g_xtal0Freq;
   -    }
   -    else
   -    {
   +    } else   {
            freq = 0U;
        }
    
   @@ -372,26 +363,26 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetEr32kClkFreq(void)
   +uint32_t
   +CLOCK_GetEr32kClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT1_OSC32KSEL_VAL)
   -    {
   -        case 0U: /* OSC 32k clock  */
   -            freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   -            break;
   -        case 2U: /* RTC 32k clock  */
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 3U: /* LPO clock      */
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT1_OSC32KSEL_VAL) {
   +    case 0U:     /* OSC 32k clock  */
   +        freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   +        break;
   +    case 2U:     /* RTC 32k clock  */
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 3U:     /* LPO clock      */
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
        return freq;
    }
   @@ -401,24 +392,24 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPllFllSelClkFreq(void)
   +uint32_t
   +CLOCK_GetPllFllSelClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT2_PLLFLLSEL_VAL)
   -    {
   -        case 0U: /* FLL. */
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case 1U: /* PLL. */
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case 3U: /* MCG IRC48M. */
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT2_PLLFLLSEL_VAL) {
   +    case 0U:     /* FLL. */
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case 1U:     /* PLL. */
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case 3U:     /* MCG IRC48M. */
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -429,7 +420,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPlatClkFreq(void)
   +uint32_t
   +CLOCK_GetPlatClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -439,7 +431,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlashClkFreq(void)
   +uint32_t
   +CLOCK_GetFlashClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
    }
   @@ -449,7 +442,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlexBusClkFreq(void)
   +uint32_t
   +CLOCK_GetFlexBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
    }
   @@ -459,7 +453,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetBusClkFreq(void)
   +uint32_t
   +CLOCK_GetBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
    }
   @@ -469,7 +464,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetCoreSysClkFreq(void)
   +uint32_t
   +CLOCK_GetCoreSysClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -484,55 +480,55 @@
     * param clockName Clock names defined in clock_name_t
     * return Clock frequency value in Hertz
     */
   -uint32_t CLOCK_GetFreq(clock_name_t clockName)
   +uint32_t
   +CLOCK_GetFreq(clock_name_t clockName)
    {
        uint32_t freq;
    
   -    switch (clockName)
   -    {
   -        case kCLOCK_CoreSysClk:
   -        case kCLOCK_PlatClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   -            break;
   -        case kCLOCK_BusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlexBusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlashClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   -            break;
   -        case kCLOCK_PllFllSelClk:
   -            freq = CLOCK_GetPllFllSelClkFreq();
   -            break;
   -        case kCLOCK_Er32kClk:
   -            freq = CLOCK_GetEr32kClkFreq();
   -            break;
   -        case kCLOCK_Osc0ErClk:
   -            freq = CLOCK_GetOsc0ErClkFreq();
   -            break;
   -        case kCLOCK_McgFixedFreqClk:
   -            freq = CLOCK_GetFixedFreqClkFreq();
   -            break;
   -        case kCLOCK_McgInternalRefClk:
   -            freq = CLOCK_GetInternalRefClkFreq();
   -            break;
   -        case kCLOCK_McgFllClk:
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case kCLOCK_McgPll0Clk:
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case kCLOCK_McgIrc48MClk:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        case kCLOCK_LpoClk:
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (clockName) {
   +    case kCLOCK_CoreSysClk:
   +    case kCLOCK_PlatClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   +        break;
   +    case kCLOCK_BusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlexBusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlashClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   +        break;
   +    case kCLOCK_PllFllSelClk:
   +        freq = CLOCK_GetPllFllSelClkFreq();
   +        break;
   +    case kCLOCK_Er32kClk:
   +        freq = CLOCK_GetEr32kClkFreq();
   +        break;
   +    case kCLOCK_Osc0ErClk:
   +        freq = CLOCK_GetOsc0ErClkFreq();
   +        break;
   +    case kCLOCK_McgFixedFreqClk:
   +        freq = CLOCK_GetFixedFreqClkFreq();
   +        break;
   +    case kCLOCK_McgInternalRefClk:
   +        freq = CLOCK_GetInternalRefClkFreq();
   +        break;
   +    case kCLOCK_McgFllClk:
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case kCLOCK_McgPll0Clk:
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case kCLOCK_McgIrc48MClk:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    case kCLOCK_LpoClk:
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -545,7 +541,8 @@
     *
     * param config Pointer to the configure structure.
     */
   -void CLOCK_SetSimConfig(sim_clock_config_t const *config)
   +void
   +CLOCK_SetSimConfig(sim_clock_config_t const *config)
    {
        SIM->CLKDIV1 = config->clkdiv1;
        CLOCK_SetPllFllSelClock(config->pllFllSel);
   @@ -559,35 +556,32 @@
     * retval true The clock is set successfully.
     * retval false The clock source is invalid to get proper USB FS clock.
     */
   -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
   +bool
   +CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
    {
        bool ret = true;
    
        CLOCK_DisableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcExt == src)
   -    {
   +    if (kCLOCK_UsbSrcExt == src) {
            SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
   -    }
   -    else
   -    {
   -        switch (freq)
   -        {
   -            case 120000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 96000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            case 72000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 48000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            default:
   -                ret = false;
   -                break;
   +    } else   {
   +        switch (freq) {
   +        case 120000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 96000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        case 72000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 48000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        default:
   +            ret = false;
   +            break;
            }
    
            SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src);
   @@ -595,8 +589,7 @@
    
        CLOCK_EnableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcIrc48M == src)
   -    {
   +    if (kCLOCK_UsbSrcIrc48M == src) {
            USB0->CLK_RECOVER_IRC_EN = 0x03U;
            USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
        }
   @@ -611,28 +604,28 @@
     *
     * return The frequency of MCGOUTCLK.
     */
   -uint32_t CLOCK_GetOutClkFreq(void)
   +uint32_t
   +CLOCK_GetOutClkFreq(void)
    {
        uint32_t mcgoutclk;
        uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
    
   -    switch (clkst)
   -    {
   -        case (uint32_t)kMCG_ClkOutStatPll:
   -            mcgoutclk = CLOCK_GetPll0Freq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatFll:
   -            mcgoutclk = CLOCK_GetFllFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatInt:
   -            mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatExt:
   -            mcgoutclk = CLOCK_GetMcgExtClkFreq();
   -            break;
   -        default:
   -            mcgoutclk = 0U;
   -            break;
   +    switch (clkst) {
   +    case (uint32_t)kMCG_ClkOutStatPll:
   +        mcgoutclk = CLOCK_GetPll0Freq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatFll:
   +        mcgoutclk = CLOCK_GetFllFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatInt:
   +        mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatExt:
   +        mcgoutclk = CLOCK_GetMcgExtClkFreq();
   +        break;
   +    default:
   +        mcgoutclk = 0U;
   +        break;
        }
    
        return mcgoutclk;
   @@ -647,7 +640,8 @@
     *
     * return The frequency of MCGFLLCLK.
     */
   -uint32_t CLOCK_GetFllFreq(void)
   +uint32_t
   +CLOCK_GetFllFreq(void)
    {
        static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}};
    
   @@ -656,23 +650,17 @@
        uint32_t ret;
    
        /* If FLL is not enabled currently, then return 0U. */
   -    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U)))
   -    {
   +    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) {
            ret = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            /* Get FLL reference clock frequency. */
            freq = CLOCK_GetFllRefClkFreq();
   -        if (0U == freq)
   -        {
   +        if (0U == freq) {
                ret = freq;
   -        }
   -        else
   -        {
   -            drs   = MCG_C4_DRST_DRS_VAL;
   +        } else   {
   +            drs = MCG_C4_DRST_DRS_VAL;
                dmx32 = MCG_C4_DMX32_VAL;
   -            ret   = freq * fllFactorTable[drs][dmx32];
   +            ret = freq * fllFactorTable[drs][dmx32];
            }
        }
    
   @@ -687,17 +675,15 @@
     *
     * return The frequency of MCGIRCLK.
     */
   -uint32_t CLOCK_GetInternalRefClkFreq(void)
   +uint32_t
   +CLOCK_GetInternalRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If MCGIRCLK is gated. */
   -    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK))
   -    {
   +    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            freq = CLOCK_GetInternalRefClkSelectFreq();
        }
    
   @@ -712,18 +698,16 @@
     *
     * return The frequency of MCGFFCLK.
     */
   -uint32_t CLOCK_GetFixedFreqClkFreq(void)
   +uint32_t
   +CLOCK_GetFixedFreqClkFreq(void)
    {
        uint32_t freq = CLOCK_GetFllRefClkFreq();
        uint32_t ret;
    
        /* MCGFFCLK must be no more than MCGOUTCLK/8. */
   -    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq))
   -    {
   +    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq)) {
            ret = freq;
   -    }
   -    else
   -    {
   +    } else   {
            ret = 0U;
        }
    
   @@ -738,7 +722,8 @@
     *
     * return The frequency of MCGPLL0CLK.
     */
   -uint32_t CLOCK_GetPll0Freq(void)
   +uint32_t
   +CLOCK_GetPll0Freq(void)
    {
        uint32_t mcgpll0clk;
        uint32_t freq;
   @@ -746,12 +731,9 @@
        uint8_t mcgpll0prdiv;
        uint8_t mcgpll0vdiv;
        /* If PLL0 is not enabled, return 0. */
   -    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            mcgpll0clk = CLOCK_GetPll0RefFreq();
    
            /*
   @@ -783,36 +765,31 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success External reference clock set successfully.
     */
   -status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
    {
        bool needDelay;
        uint32_t i;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */
   -    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK)))
   -    {
   +    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) {
            return kStatus_MCG_SourceUsed;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
    
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel)
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel) {
            /* If change OSCSEL, need to delay, ERR009878. */
            needDelay = true;
   -    }
   -    else
   -    {
   +    } else   {
            needDelay = false;
        }
    
        MCG->C7 = (uint8_t)(MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
   -    if (needDelay)
   -    {
   +    if (needDelay) {
            /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
            i = 1500U;
   -        while (0U != (i--))
   -        {
   +        while (0U != (i--)) {
                __NOP();
            }
        }
   @@ -836,34 +813,30 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success MCGIRCLK configuration finished successfully.
     */
   -status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
   +status_t
   +CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
    {
        uint32_t mcgOutClkState = (uint32_t)MCG_S_CLKST_VAL;
   -    mcg_irc_mode_t curIrcs  = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   -    uint8_t curFcrdiv       = MCG_SC_FCRDIV_VAL;
   +    mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   +    uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If MCGIRCLK is used as system clock source. */
   -    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState)
   -    {
   +    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState) {
            /* If need to change MCGIRCLK source or driver, return error. */
   -        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs))
   -        {
   +        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) {
                return kStatus_MCG_SourceUsed;
            }
        }
    #endif
    
        /* If need to update the FCRDIV. */
   -    if (fcrdiv != curFcrdiv)
   -    {
   +    if (fcrdiv != curFcrdiv) {
            /* If fast IRC is in use currently, change to slow IRC. */
            if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) &&
   -            (kMCG_IrcFast == curIrcs))
   -        {
   +            (kMCG_IrcFast == curIrcs)) {
                MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
   -            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow)
   -            {
   +            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow) {
                }
            }
            /* Update FCRDIV. */
   @@ -876,10 +849,8 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode);
    
        /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
   -    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable)))
   -    {
   -        while (MCG_S_IRCST_VAL != (uint8_t)ircs)
   -        {
   +    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable))) {
   +        while (MCG_S_IRCST_VAL != (uint8_t)ircs) {
            }
        }
    
   @@ -901,7 +872,8 @@
     * param vdiv       VDIV value to generate desired PLL frequency.
     * return Closest frequency match that the PLL was able generate.
     */
   -uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
   +uint32_t
   +CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
    {
        uint8_t ret_prdiv;               /* PRDIV to return. */
        uint8_t ret_vdiv;                /* VDIV to return.  */
   @@ -910,7 +882,7 @@
        uint8_t prdiv_cur;               /* PRDIV value for iteration.    */
        uint8_t vdiv_cur;                /* VDIV value for iteration.     */
        uint32_t ret_freq = 0U;          /* PLL output frequency to return. */
   -    uint32_t diff     = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */
   +    uint32_t diff = 0xFFFFFFFFU;     /* Difference between desireFreq and return frequency. */
        uint32_t ref_div;                /* Reference frequency after PRDIV. */
    
        /*
   @@ -929,8 +901,7 @@
        /* Reference frequency is out of range. */
        if ((refFreq < (uint32_t)FSL_FEATURE_MCG_PLL_REF_MIN) ||
            (refFreq > ((uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX *
   -                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE))))
   -    {
   +                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) {
            return 0U;
        }
    
   @@ -940,62 +911,52 @@
            (uint8_t)((refFreq + (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX);
    
        /* PRDIV traversal. */
   -    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--)
   -    {
   +    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) {
            /* Reference frequency after PRDIV. */
            ref_div = refFreq / prdiv_cur;
    
            vdiv_cur = (uint8_t)(desireFreq / ref_div);
    
            if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) ||
   -            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                /* No VDIV is available with this PRDIV. */
                continue;
            }
    
            ret_freq = vdiv_cur * ref_div;
    
   -        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE)
   -        {
   -            if (ret_freq == desireFreq) /* If desire frequency is got. */
   -            {
   +        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) {
   +            if (ret_freq == desireFreq) { /* If desire frequency is got. */
                    *prdiv = prdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -                *vdiv  = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +                *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
                    return ret_freq;
                }
                /* New PRDIV/VDIV is closer. */
   -            if (diff > desireFreq - ret_freq)
   -            {
   -                diff      = desireFreq - ret_freq;
   +            if (diff > desireFreq - ret_freq) {
   +                diff = desireFreq - ret_freq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
            vdiv_cur++;
   -        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                ret_freq += ref_div;
                /* New PRDIV/VDIV is closer. */
   -            if (diff > ret_freq - desireFreq)
   -            {
   -                diff      = ret_freq - desireFreq;
   +            if (diff > ret_freq - desireFreq) {
   +                diff = ret_freq - desireFreq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
        }
    
   -    if (0xFFFFFFFFU != diff)
   -    {
   +    if (0xFFFFFFFFU != diff) {
            /* PRDIV/VDIV found. */
   -        *prdiv   = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -        *vdiv    = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +        *prdiv = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   +        *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
            ret_freq = (refFreq / ret_prdiv) * ret_vdiv;
            return ret_freq;
   -    }
   -    else
   -    {
   +    } else   {
            /* No proper PRDIV/VDIV found. */
            return 0U;
        }
   @@ -1012,7 +973,8 @@
     *
     * param config Pointer to the configuration structure.
     */
   -void CLOCK_EnablePll0(mcg_pll_config_t const *config)
   +void
   +CLOCK_EnablePll0(mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1027,8 +989,7 @@
        MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode);
    
        /* Wait for PLL lock. */
   -    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
        }
    }
    
   @@ -1039,23 +1000,18 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
    {
        /* Clear the previous flag, MCG_SC[LOCS0]. */
        MCG->SC &= ~(uint8_t)MCG_SC_ATMF_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= ~(uint8_t)MCG_C6_CME0_MASK;
   -    }
   -    else
   -    {
   -        if (kMCG_MonitorInt == mode)
   -        {
   +    } else   {
   +        if (kMCG_MonitorInt == mode) {
                MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK;
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C2 |= MCG_C2_LOCRE0_MASK;
            }
            MCG->C6 |= MCG_C6_CME0_MASK;
   @@ -1069,16 +1025,15 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8 = MCG->C8;
    
        mcg_c8 &= ~(uint8_t)(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK);
    
   -    if (kMCG_MonitorNone != mode)
   -    {
   -        if (kMCG_MonitorReset == mode)
   -        {
   +    if (kMCG_MonitorNone != mode) {
   +        if (kMCG_MonitorReset == mode) {
                mcg_c8 |= MCG_C8_LOCRE1_MASK;
            }
            mcg_c8 |= MCG_C8_CME1_MASK;
   @@ -1093,29 +1048,24 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8;
    
        /* Clear previous flag. */
        MCG->S = MCG_S_LOLS0_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= (uint8_t)(~MCG_C6_LOLIE0_MASK);
   -    }
   -    else
   -    {
   +    } else   {
            mcg_c8 = MCG->C8;
    
            mcg_c8 &= (uint8_t)(~MCG_C8_LOCS1_MASK);
    
   -        if (kMCG_MonitorInt == mode)
   -        {
   +        if (kMCG_MonitorInt == mode) {
                mcg_c8 &= (uint8_t)(~MCG_C8_LOLRE_MASK);
   -        }
   -        else
   -        {
   +        } else   {
                mcg_c8 |= MCG_C8_LOLRE_MASK;
            }
            MCG->C8 = mcg_c8;
   @@ -1149,29 +1099,25 @@
     *
     * return  Logical OR value of the ref _mcg_status_flags_t.
     */
   -uint32_t CLOCK_GetStatusFlags(void)
   -{
   -    uint32_t ret  = 0U;
   +uint32_t
   +CLOCK_GetStatusFlags(void)
   +{
   +    uint32_t ret = 0U;
        uint8_t mcg_s = MCG->S;
    
   -    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U)
   -    {
   +    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0LostFlag;
        }
   -    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0InitFlag;
        }
   -    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK))
   -    {
   +    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK)) {
            ret |= (uint32_t)kMCG_RtcOscLostFlag;
        }
   -    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LostFlag;
        }
   -    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LockFlag;
        }
        return ret;
   @@ -1193,21 +1139,19 @@
     * param mask The status flags to clear. This is a logical OR of members of the
     *             enumeration ref _mcg_status_flags_t.
     */
   -void CLOCK_ClearStatusFlags(uint32_t mask)
   +void
   +CLOCK_ClearStatusFlags(uint32_t mask)
    {
        uint8_t reg;
    
   -    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL) {
            MCG->SC &= (uint8_t)(~MCG_SC_ATMF_MASK);
        }
   -    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag))
   -    {
   -        reg     = MCG->C8;
   +    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag)) {
   +        reg = MCG->C8;
            MCG->C8 = reg;
        }
   -    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL) {
            MCG->S = MCG_S_LOLS0_MASK;
        }
    }
   @@ -1219,7 +1163,8 @@
     *
     * param  config Pointer to the OSC0 configuration structure.
     */
   -void CLOCK_InitOsc0(osc_config_t const *config)
   +void
   +CLOCK_InitOsc0(osc_config_t const *config)
    {
        uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq);
    
   @@ -1228,11 +1173,9 @@
        MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode);
        OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
    
   -    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U))
   -    {
   +    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)) {
            /* Wait for stable. */
   -        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -        {
   +        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
            }
        }
    }
   @@ -1242,7 +1185,8 @@
     *
     * This function deinitializes the OSC0.
     */
   -void CLOCK_DeinitOsc0(void)
   +void
   +CLOCK_DeinitOsc0(void)
    {
        OSC0->CR = 0U;
        MCG->C2 &= ~(uint8_t)OSC_MODE_MASK;
   @@ -1253,7 +1197,8 @@
     *
     * param freq The Slow IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetSlowIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetSlowIrcFreq(uint32_t freq)
    {
        s_slowIrcFreq = freq;
    }
   @@ -1263,7 +1208,8 @@
     *
     * param freq The Fast IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetFastIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetFastIrcFreq(uint32_t freq)
    {
        s_fastIrcFreq = freq;
    }
   @@ -1286,7 +1232,8 @@
     * retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
     * retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
     */
   -status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
   +status_t
   +CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
    {
        uint32_t multi; /* extFreq / desireFreq */
        uint32_t actv;  /* Auto trim value. */
   @@ -1299,30 +1246,24 @@
            {TRIM_FIRC_MIN, TRIM_FIRC_MAX}  /* Fast IRC. */
        };
    
   -    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN))
   -    {
   +    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) {
            status = kStatus_MCG_AtmBusClockInvalid;
        }
        /* Check desired frequency range. */
   -    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1]))
   -    {
   +    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) {
            status = kStatus_MCG_AtmDesiredFreqInvalid;
        }
        /*
           Make sure internal reference clock is not used to generate bus clock.
           Here only need to check (MCG_S_IREFST == 1).
         */
   -    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK))
   -    {
   +    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) {
            status = kStatus_MCG_AtmIrcUsed;
   -    }
   -    else
   -    {
   +    } else   {
            multi = extFreq / desireFreq;
   -        actv  = multi * 21U;
   -
   -        if (kMCG_AtmSel4m == atms)
   -        {
   +        actv = multi * 21U;
   +
   +        if (kMCG_AtmSel4m == atms) {
                actv *= 128U;
            }
    
   @@ -1336,27 +1277,20 @@
            MCG->SC = (mcg_sc | MCG_SC_ATME_MASK);
    
            /* Wait for MCG finished. */
   -        while (0U != (MCG->SC & MCG_SC_ATME_MASK))
   -        {
   +        while (0U != (MCG->SC & MCG_SC_ATME_MASK)) {
            }
    
            /* Error occurs? */
   -        if (0U != (MCG->SC & MCG_SC_ATMF_MASK))
   -        {
   +        if (0U != (MCG->SC & MCG_SC_ATMF_MASK)) {
                /* Clear the failed flag. */
                MCG->SC = mcg_sc;
   -            status  = kStatus_MCG_AtmHardwareFail;
   -        }
   -        else
   -        {
   +            status = kStatus_MCG_AtmHardwareFail;
   +        } else   {
                *actualFreq = extFreq / multi;
    
   -            if (kMCG_AtmSel4m == atms)
   -            {
   +            if (kMCG_AtmSel4m == atms) {
                    s_fastIrcFreq = *actualFreq;
   -            }
   -            else
   -            {
   +            } else   {
                    s_slowIrcFreq = *actualFreq;
                }
            }
   @@ -1372,103 +1306,83 @@
     *
     * return Current MCG mode or error code; See ref mcg_mode_t.
     */
   -mcg_mode_t CLOCK_GetMode(void)
   +mcg_mode_t
   +CLOCK_GetMode(void)
    {
        mcg_mode_t mode = kMCG_ModeError;
   -    uint32_t clkst  = (uint32_t)MCG_S_CLKST_VAL;
   +    uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
        uint32_t irefst = (uint32_t)MCG_S_IREFST_VAL;
   -    uint32_t lp     = (uint32_t)MCG_C2_LP_VAL;
   -    uint32_t pllst  = MCG_S_PLLST_VAL;
   +    uint32_t lp = (uint32_t)MCG_C2_LP_VAL;
   +    uint32_t pllst = MCG_S_PLLST_VAL;
    
        /*------------------------------------------------------------------
                               Mode and Registers
   -    ____________________________________________________________________
   -
   -      Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   -    ____________________________________________________________________
   -
   -      FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -      PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   -    ____________________________________________________________________
   -
   -      PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -    ----------------------------------------------------------------------*/
   -
   -    if (clkst == (uint32_t)kMCG_ClkOutStatFll)
   -    {
   -        if ((uint32_t)kMCG_FllSrcExternal == irefst)
   -        {
   +       ____________________________________________________________________
   +
   +       Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   +       ____________________________________________________________________
   +
   +       FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   +       ____________________________________________________________________
   +
   +       PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       ----------------------------------------------------------------------*/
   +
   +    if (clkst == (uint32_t)kMCG_ClkOutStatFll) {
   +        if ((uint32_t)kMCG_FllSrcExternal == irefst) {
                mode = kMCG_ModeFEE;
   -        }
   -        else
   -        {
   +        } else   {
                mode = kMCG_ModeFEI;
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatInt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatInt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPI;
   -        }
   -        else
   -        {
   +        } else   {
                {
                    mode = kMCG_ModeFBI;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatExt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatExt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPE;
   -        }
   -        else
   -        {
   -            if ((uint32_t)kMCG_PllstPll == pllst)
   -            {
   +        } else   {
   +            if ((uint32_t)kMCG_PllstPll == pllst) {
                    mode = kMCG_ModePBE;
   -            }
   -            else
   -            {
   +            } else   {
                    mode = kMCG_ModeFBE;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatPll)
   -    {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatPll)   {
            {
                mode = kMCG_ModePEE;
            }
   -    }
   -    else
   -    {
   +    } else   {
            /*do nothing*/
        }
    
   @@ -1490,15 +1404,15 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to a frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode)))
   -    {
   +    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1510,8 +1424,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1523,13 +1436,11 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1538,13 +1449,11 @@
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1566,15 +1475,15 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode)))
   -    {
   +    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1586,8 +1495,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1600,45 +1508,37 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
        /* Set DRS and DMX32. */
   -    mcg_c4  = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
   +    mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
        MCG->C4 = mcg_c4;
    
        /* Wait for DRST_DRS update. */
   -    while (MCG->C4 != mcg_c4)
   -    {
   +    while (MCG->C4 != mcg_c4) {
        }
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1661,7 +1561,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1670,9 +1571,7 @@
        mcg_mode_t mode = CLOCK_GetMode();
    
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModeBLPI == mode)))
   -
   -    {
   +          (kMCG_ModeBLPI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1687,8 +1586,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1700,26 +1598,22 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   -    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) {
        }
    
        MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1741,7 +1635,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1749,16 +1644,14 @@
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode)))
   -    {
   +          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
    
        /* Change to FLL mode. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Set LP bit to enable the FLL */
   @@ -1772,8 +1665,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1786,24 +1678,19 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for Reference clock Status bit to clear */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1812,13 +1699,11 @@
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for clock status bits to show clock source is ext ref clk */
   -    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for fll stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1834,11 +1719,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpiMode(void)
   +status_t
   +CLOCK_SetBlpiMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1858,11 +1743,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpeMode(void)
   +status_t
   +CLOCK_SetBlpeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1892,7 +1777,8 @@
     * configuration structure not necessary. In this case, pass in NULL.
     * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
     */
   -status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1907,14 +1793,12 @@
    
        /* Wait for CLKST clock status bits to show clock source is ext ref clk */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* Disable PLL first, then configure PLL. */
        MCG->C6 &= (uint8_t)(~MCG_C6_PLLS_MASK);
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Configure the PLL. */
   @@ -1926,8 +1810,7 @@
        MCG->C6 |= MCG_C6_PLLS_MASK;
    
        /* Wait for PLL mode changed. */
   -    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U) {
        }
    
        return kStatus_Success;
   @@ -1945,12 +1828,12 @@
     *       PRDIV/VDIV are different than in the PBE mode, set them up
     *       in PBE mode and wait. When the clock is stable, switch to PEE mode.
     */
   -status_t CLOCK_SetPeeMode(void)
   +status_t
   +CLOCK_SetPeeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (kMCG_ModePBE != mode)
   -    {
   +    if (kMCG_ModePBE != mode) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1959,8 +1842,7 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
    
        /* Wait for clock status bits to update */
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -1982,11 +1864,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
     */
   -status_t CLOCK_ExternalModeToFbeModeQuick(void)
   +status_t
   +CLOCK_ExternalModeToFbeModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) != 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) != 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1995,14 +1877,12 @@
        MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK);
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
        }
    
        /* Disable PLL. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        return kStatus_Success;
   @@ -2024,11 +1904,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
     */
   -status_t CLOCK_InternalModeToFbiModeQuick(void)
   +status_t
   +CLOCK_InternalModeToFbiModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) == 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) == 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif
   @@ -2037,8 +1917,7 @@
        MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        return kStatus_Success;
   @@ -2059,7 +1938,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
    }
   @@ -2079,8 +1959,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToFeeMode(
   -    mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeeMode(mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2100,15 +1980,15 @@
     * retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
   +status_t
   +CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
    {
        /* If reset mode is FEI mode, set MCGIRCLK and always success. */
        (void)CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
    
        /* If reset mode is not BLPI, first enter FBI mode. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        /* Enter BLPI mode. */
   @@ -2128,7 +2008,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2138,20 +2019,16 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* In FBE now, start to enter BLPE. */
   @@ -2173,7 +2050,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -2183,8 +2061,7 @@
    
        /* Change to use PLL output clock. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -2233,7 +2110,8 @@
     * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
     * function.
     */
   -status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
   +status_t
   +CLOCK_SetMcgConfig(const mcg_config_t *config)
    {
        mcg_mode_t next_mode;
        status_t status = kStatus_Success;
   @@ -2241,11 +2119,9 @@
        mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0;
    
        /* If need to change external clock, MCG_C7[OSCSEL]. */
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel))
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel)) {
            /* If external clock is in use, change to FEI first. */
   -        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -        {
   +        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
                (void)CLOCK_ExternalModeToFbeModeQuick();
                (void)CLOCK_SetFeiMode(config->dmx32, config->drs, NULL);
            }
   @@ -2254,8 +2130,7 @@
        }
    
        /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
   -    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt) {
            MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */
    
            {
   @@ -2268,67 +2143,56 @@
    
        next_mode = CLOCK_GetMode();
    
   -    do
   -    {
   +    do{
            next_mode = mcgModeMatrix[next_mode][config->mcgMode];
    
   -        switch (next_mode)
   -        {
   -            case kMCG_ModeFEI:
   -                status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFEE:
   -                status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFBI:
   -                status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeFBE:
   -                status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeBLPI:
   -                status = CLOCK_SetBlpiMode();
   -                break;
   -            case kMCG_ModeBLPE:
   -                status = CLOCK_SetBlpeMode();
   -                break;
   -            case kMCG_ModePBE:
   -                /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   -                if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode))
   +        switch (next_mode) {
   +        case kMCG_ModeFEI:
   +            status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFEE:
   +            status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFBI:
   +            status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeFBE:
   +            status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeBLPI:
   +            status = CLOCK_SetBlpiMode();
   +            break;
   +        case kMCG_ModeBLPE:
   +            status = CLOCK_SetBlpeMode();
   +            break;
   +        case kMCG_ModePBE:
   +            /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   +            if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) {
                    {
   -                    {
   -                        status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
   -                    }
   +                    status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
                    }
   -                else
   -                {
   -                    MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -                    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -                    {
   -                    }
   +            } else   {
   +                MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   +                while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
                    }
   -                break;
   -            case kMCG_ModePEE:
   -                status = CLOCK_SetPeeMode();
   -                break;
   -            default:
   -                assert(false);
   -                break;
   -        }
   -        if (kStatus_Success != status)
   -        {
   +            }
                break;
   +        case kMCG_ModePEE:
   +            status = CLOCK_SetPeeMode();
   +            break;
   +        default:
   +            assert(false);
   +            break;
   +        }
   +        if (kStatus_Success != status) {
   +            break;
            }
        } while (next_mode != config->mcgMode);
    
   -    if (status == kStatus_Success)
   -    {
   -        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U)
   -        {
   +    if (status == kStatus_Success) {
   +        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U) {
                CLOCK_EnablePll0(&config->pll0Config);
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_flash.c
   <details>
   
   ```diff
   @@ -6,7 +6,7 @@
     * to you under the Apache License, Version 2.0 (the
     * "License"); you may not use this file except in compliance
     * with the License.  You may obtain a copy of the License at
   -*
   + *
     *  http://www.apache.org/licenses/LICENSE-2.0
     *
     * Unless required by applicable law or agreed to in writing,
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_lpuart.c
   <details>
   
   ```diff
   @@ -61,10 +61,10 @@
        hal_uart_tx_char u_tx_func;
        hal_uart_tx_done u_tx_done;
        void *u_func_arg;
   -    uint8_t u_configured:1;
   -    uint8_t u_open:1;
   -    uint8_t u_tx_started:1;
   -    uint8_t u_rx_stall:1;
   +    uint8_t u_configured : 1;
   +    uint8_t u_open : 1;
   +    uint8_t u_tx_started : 1;
   +    uint8_t u_rx_stall : 1;
        struct uart_ring ur_tx;
        uint8_t tx_buffer[TX_BUF_SZ];
        struct uart_ring ur_rx;
   @@ -457,8 +457,7 @@
                uarts[port].ur_rx.ur_head = 0;
                uarts[port].ur_rx.ur_tail = 0;
                uarts[port].u_configured = 1;
   -        }
   -        else {
   +        } else   {
                uarts[port].u_configured = 0;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_qspi.c
   <details>
   
   ```diff
   @@ -107,7 +107,8 @@
        [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
    
        /* Match MISRA rule */
   -    [63] = 0};
   +    [63] = 0
   +};
    
    qspi_flash_config_t g_qspi_flash_cfg = {
        .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
   @@ -132,15 +133,12 @@
    {
        uint32_t val = 0;
        /* Check WIP bit */
   -    do
   -    {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +    do{
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
            QSPI_ExecuteIPCommand(QuadSPI0, 12U);
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            val = QuadSPI0->RBDR[0];
            /* Clear ARDB area */
   @@ -151,19 +149,17 @@
    static void
    cmd_write_enable()
    {
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ExecuteIPCommand(QuadSPI0, 4U);
    }
    
    static void
   -read_page(uint32_t address, uint32_t* dst)
   +read_page(uint32_t address, uint32_t * dst)
    {
        int i;
   -    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
   -    {
   -        dst[i] = ((uint32_t*)address)[i];
   +    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++) {
   +        dst[i] = ((uint32_t *)address)[i];
        }
    }
    
   @@ -195,15 +191,13 @@
    {
        uint32_t leftLongWords = 0;
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
    
        QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
        cmd_write_enable();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
    
        /* First write some data into TXFIFO to prevent from underrun */
   @@ -219,8 +213,7 @@
    
        /* Wait until flash finished program */
        check_if_finished();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess)) {
        }
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   @@ -244,7 +237,7 @@
    
        npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        while (npages) {
   -        write_page(address, (uint32_t*) src);
   +        write_page(address, (uint32_t *) src);
            npages--;
            address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        }
   @@ -253,13 +246,12 @@
    
    static int
    nxp_qspi_erase_sector(const struct hal_flash *dev,
   -                         uint32_t sector_address)
   +                      uint32_t sector_address)
    {
        sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
        sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
        QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
   @@ -286,8 +278,7 @@
        nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
        while (nsects) {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
            QSPI_SetIPCommandAddress(QuadSPI0, address);
   @@ -296,7 +287,7 @@
            check_if_finished();
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
   -    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   +        (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
            QSPI_ClearCache(QuadSPI0);
    #endif
            nsects--;
   @@ -323,8 +314,7 @@
    {
        uint32_t val[4] = {0x40U, 0, 0, 0};
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
    
   ```
   
   </details>


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[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot commented on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-773684122


   
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[GitHub] [mynewt-core] mlaz merged pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
mlaz merged pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466


   


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[GitHub] [mynewt-core] mlaz commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
mlaz commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570633746



##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,408 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type *dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *user_data)
+{
+    struct nxp_hal_i2c *i2c = userData;

Review comment:
       I did! You are too fast!




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[GitHub] [mynewt-core] mlaz commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
mlaz commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570624651



##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,623 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type *dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void *txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);

Review comment:
       Addressed, good catch.




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[GitHub] [mynewt-core] mlaz commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
mlaz commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570624710



##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,623 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type *dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void *txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave *) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }
+    return 0;
+}
+
+int
+hal_spi_enable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (spi->enabled) {
+        return 0;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        DSPI_MasterInit(spi->dev,
+                        &master->config,
+                        CLOCK_GetFreq(kCLOCK_BusClk));
+    } else {
+        slave = (struct nxp_spi_slave *) spi;
+        DSPI_SlaveInit(spi->dev, &slave->config);
+    }
+
+    spi->enabled = true;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_SetVector(spi->irqn, (uint32_t) spi->irq_handler);
+    NVIC_EnableIRQ(spi->irqn);
+    return 0;
+}
+
+int
+hal_spi_disable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (!spi->enabled) {
+        return 0;
+    }
+
+    DSPI_Deinit(spi->dev);
+
+    spi->enabled = false;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_DisableIRQ(spi->irqn);
+    return 0;
+}
+
+uint16_t
+hal_spi_tx_val(int spi_num, uint16_t val)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    uint16_t retval = 0;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t *) &val;
+        xfer.rxData = (uint8_t *) &retval;
+        xfer.dataSize = 1;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return retval;
+    }
+    return 0xFFFF; /* Invalid API. */
+}
+
+int
+hal_spi_txrx(int spi_num, void *txbuf, void *rxbuf, int len)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    status_t rc;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t *) txbuf;
+        xfer.rxData = (uint8_t *) rxbuf;
+        xfer.dataSize = len;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        rc = DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return (rc == kStatus_Success) ? 0 : rc;

Review comment:
       Addressed, good catch!




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[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

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   <!-- style-bot -->
   
   ## Style check summary
   
   ### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
   
   
   #### hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c
   <details>
   
   ```diff
   @@ -187,15 +187,15 @@
     ******************************************************************************/
    
    #ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
   -static void CLOCK_FllStableDelay(void)
   +static void
   +CLOCK_FllStableDelay(void)
    {
        /*
           Should wait at least 1ms. Because in these modes, the core clock is 100MHz
           at most, so this function could obtain the 1ms delay.
         */
        volatile uint32_t i = 30000U;
   -    while (0U != (i--))
   -    {
   +    while (0U != (i--)) {
            __NOP();
        }
    }
   @@ -207,34 +207,35 @@
    extern void CLOCK_FllStableDelay(void);
    #endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */
    
   -static uint32_t CLOCK_GetMcgExtClkFreq(void)
   +static uint32_t
   +CLOCK_GetMcgExtClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (MCG_C7_OSCSEL_VAL)
   -    {
   -        case 0U:
   -            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   -            assert(0U != g_xtal0Freq);
   -            freq = g_xtal0Freq;
   -            break;
   -        case 1U:
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(0U != g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 2U:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (MCG_C7_OSCSEL_VAL) {
   +    case 0U:
   +        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
   +        assert(0U != g_xtal0Freq);
   +        freq = g_xtal0Freq;
   +        break;
   +    case 1U:
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(0U != g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 2U:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllExtRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllExtRefClkFreq(void)
    {
        /* FllExtRef = McgExtRef / FllExtRefDiv */
        uint8_t frdiv;
   @@ -246,54 +247,50 @@
        frdiv = MCG_C1_FRDIV_VAL;
        freq >>= frdiv;
    
   -    range  = MCG_C2_RANGE_VAL;
   +    range = MCG_C2_RANGE_VAL;
        oscsel = MCG_C7_OSCSEL_VAL;
    
        /*
           When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536.
           1. MCG_C7[OSCSEL] selects IRC48M.
           2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0.
   -    */
   -    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel))
   -    {
   -        switch (frdiv)
   -        {
   -            case 0:
   -            case 1:
   -            case 2:
   -            case 3:
   -            case 4:
   -            case 5:
   -                freq >>= 5u;
   -                break;
   -            case 6:
   -                /* 64*20=1280 */
   -                freq /= 20u;
   -                break;
   -            case 7:
   -                /* 128*12=1536 */
   -                freq /= 12u;
   -                break;
   -            default:
   -                freq = 0u;
   -                break;
   +     */
   +    if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel)) {
   +        switch (frdiv) {
   +        case 0:
   +        case 1:
   +        case 2:
   +        case 3:
   +        case 4:
   +        case 5:
   +            freq >>= 5u;
   +            break;
   +        case 6:
   +            /* 64*20=1280 */
   +            freq /= 20u;
   +            break;
   +        case 7:
   +            /* 128*12=1536 */
   +            freq /= 12u;
   +            break;
   +        default:
   +            freq = 0u;
   +            break;
            }
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetInternalRefClkSelectFreq(void)
   +static uint32_t
   +CLOCK_GetInternalRefClkSelectFreq(void)
    {
        uint32_t freq;
    
   -    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL)
   -    {
   +    if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL) {
            /* Slow internal reference clock selected*/
            freq = s_slowIrcFreq;
   -    }
   -    else
   -    {
   +    } else   {
            /* Fast internal reference clock selected*/
            freq = s_fastIrcFreq >> MCG_SC_FCRDIV_VAL;
        }
   @@ -301,44 +298,40 @@
        return freq;
    }
    
   -static uint32_t CLOCK_GetFllRefClkFreq(void)
   +static uint32_t
   +CLOCK_GetFllRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If use external reference clock. */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            freq = CLOCK_GetFllExtRefClkFreq();
        }
        /* If use internal reference clock. */
   -    else
   -    {
   +    else {
            freq = s_slowIrcFreq;
        }
    
        return freq;
    }
    
   -static uint32_t CLOCK_GetPll0RefFreq(void)
   +static uint32_t
   +CLOCK_GetPll0RefFreq(void)
    {
        /* MCG external reference clock. */
        return CLOCK_GetMcgExtClkFreq();
    }
    
   -static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
   +static uint8_t
   +CLOCK_GetOscRangeFromFreq(uint32_t freq)
    {
        uint8_t range;
    
   -    if (freq <= 39063U)
   -    {
   +    if (freq <= 39063U) {
            range = 0U;
   -    }
   -    else if (freq <= 8000000U)
   -    {
   +    } else if (freq <= 8000000U)   {
            range = 1U;
   -    }
   -    else
   -    {
   +    } else   {
            range = 2U;
        }
    
   @@ -350,17 +343,15 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetOsc0ErClkFreq(void)
   +uint32_t
   +CLOCK_GetOsc0ErClkFreq(void)
    {
        uint32_t freq;
   -    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)
   -    {
   +    if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U) {
            /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
            assert(g_xtal0Freq);
            freq = g_xtal0Freq;
   -    }
   -    else
   -    {
   +    } else   {
            freq = 0U;
        }
    
   @@ -372,26 +363,26 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetEr32kClkFreq(void)
   +uint32_t
   +CLOCK_GetEr32kClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT1_OSC32KSEL_VAL)
   -    {
   -        case 0U: /* OSC 32k clock  */
   -            freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   -            break;
   -        case 2U: /* RTC 32k clock  */
   -            /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   -            assert(g_xtal32Freq);
   -            freq = g_xtal32Freq;
   -            break;
   -        case 3U: /* LPO clock      */
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT1_OSC32KSEL_VAL) {
   +    case 0U:     /* OSC 32k clock  */
   +        freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U;
   +        break;
   +    case 2U:     /* RTC 32k clock  */
   +        /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */
   +        assert(g_xtal32Freq);
   +        freq = g_xtal32Freq;
   +        break;
   +    case 3U:     /* LPO clock      */
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
        return freq;
    }
   @@ -401,24 +392,24 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPllFllSelClkFreq(void)
   +uint32_t
   +CLOCK_GetPllFllSelClkFreq(void)
    {
        uint32_t freq;
    
   -    switch (SIM_SOPT2_PLLFLLSEL_VAL)
   -    {
   -        case 0U: /* FLL. */
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case 1U: /* PLL. */
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case 3U: /* MCG IRC48M. */
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (SIM_SOPT2_PLLFLLSEL_VAL) {
   +    case 0U:     /* FLL. */
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case 1U:     /* PLL. */
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case 3U:     /* MCG IRC48M. */
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -429,7 +420,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetPlatClkFreq(void)
   +uint32_t
   +CLOCK_GetPlatClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -439,7 +431,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlashClkFreq(void)
   +uint32_t
   +CLOCK_GetFlashClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
    }
   @@ -449,7 +442,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetFlexBusClkFreq(void)
   +uint32_t
   +CLOCK_GetFlexBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
    }
   @@ -459,7 +453,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetBusClkFreq(void)
   +uint32_t
   +CLOCK_GetBusClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
    }
   @@ -469,7 +464,8 @@
     *
     * return Clock frequency in Hz.
     */
   -uint32_t CLOCK_GetCoreSysClkFreq(void)
   +uint32_t
   +CLOCK_GetCoreSysClkFreq(void)
    {
        return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
    }
   @@ -484,55 +480,55 @@
     * param clockName Clock names defined in clock_name_t
     * return Clock frequency value in Hertz
     */
   -uint32_t CLOCK_GetFreq(clock_name_t clockName)
   +uint32_t
   +CLOCK_GetFreq(clock_name_t clockName)
    {
        uint32_t freq;
    
   -    switch (clockName)
   -    {
   -        case kCLOCK_CoreSysClk:
   -        case kCLOCK_PlatClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   -            break;
   -        case kCLOCK_BusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlexBusClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   -            break;
   -        case kCLOCK_FlashClk:
   -            freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   -            break;
   -        case kCLOCK_PllFllSelClk:
   -            freq = CLOCK_GetPllFllSelClkFreq();
   -            break;
   -        case kCLOCK_Er32kClk:
   -            freq = CLOCK_GetEr32kClkFreq();
   -            break;
   -        case kCLOCK_Osc0ErClk:
   -            freq = CLOCK_GetOsc0ErClkFreq();
   -            break;
   -        case kCLOCK_McgFixedFreqClk:
   -            freq = CLOCK_GetFixedFreqClkFreq();
   -            break;
   -        case kCLOCK_McgInternalRefClk:
   -            freq = CLOCK_GetInternalRefClkFreq();
   -            break;
   -        case kCLOCK_McgFllClk:
   -            freq = CLOCK_GetFllFreq();
   -            break;
   -        case kCLOCK_McgPll0Clk:
   -            freq = CLOCK_GetPll0Freq();
   -            break;
   -        case kCLOCK_McgIrc48MClk:
   -            freq = MCG_INTERNAL_IRC_48M;
   -            break;
   -        case kCLOCK_LpoClk:
   -            freq = LPO_CLK_FREQ;
   -            break;
   -        default:
   -            freq = 0U;
   -            break;
   +    switch (clockName) {
   +    case kCLOCK_CoreSysClk:
   +    case kCLOCK_PlatClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL);
   +        break;
   +    case kCLOCK_BusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlexBusClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL);
   +        break;
   +    case kCLOCK_FlashClk:
   +        freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL);
   +        break;
   +    case kCLOCK_PllFllSelClk:
   +        freq = CLOCK_GetPllFllSelClkFreq();
   +        break;
   +    case kCLOCK_Er32kClk:
   +        freq = CLOCK_GetEr32kClkFreq();
   +        break;
   +    case kCLOCK_Osc0ErClk:
   +        freq = CLOCK_GetOsc0ErClkFreq();
   +        break;
   +    case kCLOCK_McgFixedFreqClk:
   +        freq = CLOCK_GetFixedFreqClkFreq();
   +        break;
   +    case kCLOCK_McgInternalRefClk:
   +        freq = CLOCK_GetInternalRefClkFreq();
   +        break;
   +    case kCLOCK_McgFllClk:
   +        freq = CLOCK_GetFllFreq();
   +        break;
   +    case kCLOCK_McgPll0Clk:
   +        freq = CLOCK_GetPll0Freq();
   +        break;
   +    case kCLOCK_McgIrc48MClk:
   +        freq = MCG_INTERNAL_IRC_48M;
   +        break;
   +    case kCLOCK_LpoClk:
   +        freq = LPO_CLK_FREQ;
   +        break;
   +    default:
   +        freq = 0U;
   +        break;
        }
    
        return freq;
   @@ -545,7 +541,8 @@
     *
     * param config Pointer to the configure structure.
     */
   -void CLOCK_SetSimConfig(sim_clock_config_t const *config)
   +void
   +CLOCK_SetSimConfig(sim_clock_config_t const *config)
    {
        SIM->CLKDIV1 = config->clkdiv1;
        CLOCK_SetPllFllSelClock(config->pllFllSel);
   @@ -559,35 +556,32 @@
     * retval true The clock is set successfully.
     * retval false The clock source is invalid to get proper USB FS clock.
     */
   -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
   +bool
   +CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
    {
        bool ret = true;
    
        CLOCK_DisableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcExt == src)
   -    {
   +    if (kCLOCK_UsbSrcExt == src) {
            SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
   -    }
   -    else
   -    {
   -        switch (freq)
   -        {
   -            case 120000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 96000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            case 72000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   -                break;
   -            case 48000000U:
   -                SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   -                break;
   -            default:
   -                ret = false;
   -                break;
   +    } else   {
   +        switch (freq) {
   +        case 120000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 96000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        case 72000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
   +            break;
   +        case 48000000U:
   +            SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
   +            break;
   +        default:
   +            ret = false;
   +            break;
            }
    
            SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src);
   @@ -595,8 +589,7 @@
    
        CLOCK_EnableClock(kCLOCK_Usbfs0);
    
   -    if (kCLOCK_UsbSrcIrc48M == src)
   -    {
   +    if (kCLOCK_UsbSrcIrc48M == src) {
            USB0->CLK_RECOVER_IRC_EN = 0x03U;
            USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
        }
   @@ -611,28 +604,28 @@
     *
     * return The frequency of MCGOUTCLK.
     */
   -uint32_t CLOCK_GetOutClkFreq(void)
   +uint32_t
   +CLOCK_GetOutClkFreq(void)
    {
        uint32_t mcgoutclk;
        uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
    
   -    switch (clkst)
   -    {
   -        case (uint32_t)kMCG_ClkOutStatPll:
   -            mcgoutclk = CLOCK_GetPll0Freq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatFll:
   -            mcgoutclk = CLOCK_GetFllFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatInt:
   -            mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   -            break;
   -        case (uint32_t)kMCG_ClkOutStatExt:
   -            mcgoutclk = CLOCK_GetMcgExtClkFreq();
   -            break;
   -        default:
   -            mcgoutclk = 0U;
   -            break;
   +    switch (clkst) {
   +    case (uint32_t)kMCG_ClkOutStatPll:
   +        mcgoutclk = CLOCK_GetPll0Freq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatFll:
   +        mcgoutclk = CLOCK_GetFllFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatInt:
   +        mcgoutclk = CLOCK_GetInternalRefClkSelectFreq();
   +        break;
   +    case (uint32_t)kMCG_ClkOutStatExt:
   +        mcgoutclk = CLOCK_GetMcgExtClkFreq();
   +        break;
   +    default:
   +        mcgoutclk = 0U;
   +        break;
        }
    
        return mcgoutclk;
   @@ -647,7 +640,8 @@
     *
     * return The frequency of MCGFLLCLK.
     */
   -uint32_t CLOCK_GetFllFreq(void)
   +uint32_t
   +CLOCK_GetFllFreq(void)
    {
        static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}};
    
   @@ -656,23 +650,17 @@
        uint32_t ret;
    
        /* If FLL is not enabled currently, then return 0U. */
   -    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U)))
   -    {
   +    if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) {
            ret = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            /* Get FLL reference clock frequency. */
            freq = CLOCK_GetFllRefClkFreq();
   -        if (0U == freq)
   -        {
   +        if (0U == freq) {
                ret = freq;
   -        }
   -        else
   -        {
   -            drs   = MCG_C4_DRST_DRS_VAL;
   +        } else   {
   +            drs = MCG_C4_DRST_DRS_VAL;
                dmx32 = MCG_C4_DMX32_VAL;
   -            ret   = freq * fllFactorTable[drs][dmx32];
   +            ret = freq * fllFactorTable[drs][dmx32];
            }
        }
    
   @@ -687,17 +675,15 @@
     *
     * return The frequency of MCGIRCLK.
     */
   -uint32_t CLOCK_GetInternalRefClkFreq(void)
   +uint32_t
   +CLOCK_GetInternalRefClkFreq(void)
    {
        uint32_t freq;
    
        /* If MCGIRCLK is gated. */
   -    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK))
   -    {
   +    if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            freq = CLOCK_GetInternalRefClkSelectFreq();
        }
    
   @@ -712,18 +698,16 @@
     *
     * return The frequency of MCGFFCLK.
     */
   -uint32_t CLOCK_GetFixedFreqClkFreq(void)
   +uint32_t
   +CLOCK_GetFixedFreqClkFreq(void)
    {
        uint32_t freq = CLOCK_GetFllRefClkFreq();
        uint32_t ret;
    
        /* MCGFFCLK must be no more than MCGOUTCLK/8. */
   -    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq))
   -    {
   +    if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq)) {
            ret = freq;
   -    }
   -    else
   -    {
   +    } else   {
            ret = 0U;
        }
    
   @@ -738,7 +722,8 @@
     *
     * return The frequency of MCGPLL0CLK.
     */
   -uint32_t CLOCK_GetPll0Freq(void)
   +uint32_t
   +CLOCK_GetPll0Freq(void)
    {
        uint32_t mcgpll0clk;
        uint32_t freq;
   @@ -746,12 +731,9 @@
        uint8_t mcgpll0prdiv;
        uint8_t mcgpll0vdiv;
        /* If PLL0 is not enabled, return 0. */
   -    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
            freq = 0U;
   -    }
   -    else
   -    {
   +    } else   {
            mcgpll0clk = CLOCK_GetPll0RefFreq();
    
            /*
   @@ -783,36 +765,31 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success External reference clock set successfully.
     */
   -status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
    {
        bool needDelay;
        uint32_t i;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */
   -    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK)))
   -    {
   +    if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) {
            return kStatus_MCG_SourceUsed;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
    
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel)
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel) {
            /* If change OSCSEL, need to delay, ERR009878. */
            needDelay = true;
   -    }
   -    else
   -    {
   +    } else   {
            needDelay = false;
        }
    
        MCG->C7 = (uint8_t)(MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
   -    if (needDelay)
   -    {
   +    if (needDelay) {
            /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
            i = 1500U;
   -        while (0U != (i--))
   -        {
   +        while (0U != (i--)) {
                __NOP();
            }
        }
   @@ -836,34 +813,30 @@
     * the configuration should not be changed. Otherwise, a glitch occurs.
     * retval kStatus_Success MCGIRCLK configuration finished successfully.
     */
   -status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
   +status_t
   +CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv)
    {
        uint32_t mcgOutClkState = (uint32_t)MCG_S_CLKST_VAL;
   -    mcg_irc_mode_t curIrcs  = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   -    uint8_t curFcrdiv       = MCG_SC_FCRDIV_VAL;
   +    mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL);
   +    uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        /* If MCGIRCLK is used as system clock source. */
   -    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState)
   -    {
   +    if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState) {
            /* If need to change MCGIRCLK source or driver, return error. */
   -        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs))
   -        {
   +        if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) {
                return kStatus_MCG_SourceUsed;
            }
        }
    #endif
    
        /* If need to update the FCRDIV. */
   -    if (fcrdiv != curFcrdiv)
   -    {
   +    if (fcrdiv != curFcrdiv) {
            /* If fast IRC is in use currently, change to slow IRC. */
            if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) &&
   -            (kMCG_IrcFast == curIrcs))
   -        {
   +            (kMCG_IrcFast == curIrcs)) {
                MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
   -            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow)
   -            {
   +            while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow) {
                }
            }
            /* Update FCRDIV. */
   @@ -876,10 +849,8 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode);
    
        /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
   -    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable)))
   -    {
   -        while (MCG_S_IRCST_VAL != (uint8_t)ircs)
   -        {
   +    if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable))) {
   +        while (MCG_S_IRCST_VAL != (uint8_t)ircs) {
            }
        }
    
   @@ -901,7 +872,8 @@
     * param vdiv       VDIV value to generate desired PLL frequency.
     * return Closest frequency match that the PLL was able generate.
     */
   -uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
   +uint32_t
   +CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv)
    {
        uint8_t ret_prdiv;               /* PRDIV to return. */
        uint8_t ret_vdiv;                /* VDIV to return.  */
   @@ -910,7 +882,7 @@
        uint8_t prdiv_cur;               /* PRDIV value for iteration.    */
        uint8_t vdiv_cur;                /* VDIV value for iteration.     */
        uint32_t ret_freq = 0U;          /* PLL output frequency to return. */
   -    uint32_t diff     = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */
   +    uint32_t diff = 0xFFFFFFFFU;     /* Difference between desireFreq and return frequency. */
        uint32_t ref_div;                /* Reference frequency after PRDIV. */
    
        /*
   @@ -929,8 +901,7 @@
        /* Reference frequency is out of range. */
        if ((refFreq < (uint32_t)FSL_FEATURE_MCG_PLL_REF_MIN) ||
            (refFreq > ((uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX *
   -                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE))))
   -    {
   +                    ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) {
            return 0U;
        }
    
   @@ -940,62 +911,52 @@
            (uint8_t)((refFreq + (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX);
    
        /* PRDIV traversal. */
   -    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--)
   -    {
   +    for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) {
            /* Reference frequency after PRDIV. */
            ref_div = refFreq / prdiv_cur;
    
            vdiv_cur = (uint8_t)(desireFreq / ref_div);
    
            if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) ||
   -            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +            (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                /* No VDIV is available with this PRDIV. */
                continue;
            }
    
            ret_freq = vdiv_cur * ref_div;
    
   -        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE)
   -        {
   -            if (ret_freq == desireFreq) /* If desire frequency is got. */
   -            {
   +        if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) {
   +            if (ret_freq == desireFreq) { /* If desire frequency is got. */
                    *prdiv = prdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -                *vdiv  = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +                *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
                    return ret_freq;
                }
                /* New PRDIV/VDIV is closer. */
   -            if (diff > desireFreq - ret_freq)
   -            {
   -                diff      = desireFreq - ret_freq;
   +            if (diff > desireFreq - ret_freq) {
   +                diff = desireFreq - ret_freq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
            vdiv_cur++;
   -        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U))
   -        {
   +        if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) {
                ret_freq += ref_div;
                /* New PRDIV/VDIV is closer. */
   -            if (diff > ret_freq - desireFreq)
   -            {
   -                diff      = ret_freq - desireFreq;
   +            if (diff > ret_freq - desireFreq) {
   +                diff = ret_freq - desireFreq;
                    ret_prdiv = prdiv_cur;
   -                ret_vdiv  = vdiv_cur;
   +                ret_vdiv = vdiv_cur;
                }
            }
        }
    
   -    if (0xFFFFFFFFU != diff)
   -    {
   +    if (0xFFFFFFFFU != diff) {
            /* PRDIV/VDIV found. */
   -        *prdiv   = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   -        *vdiv    = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
   +        *prdiv = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE;
   +        *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE;
            ret_freq = (refFreq / ret_prdiv) * ret_vdiv;
            return ret_freq;
   -    }
   -    else
   -    {
   +    } else   {
            /* No proper PRDIV/VDIV found. */
            return 0U;
        }
   @@ -1012,7 +973,8 @@
     *
     * param config Pointer to the configuration structure.
     */
   -void CLOCK_EnablePll0(mcg_pll_config_t const *config)
   +void
   +CLOCK_EnablePll0(mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1027,8 +989,7 @@
        MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode);
    
        /* Wait for PLL lock. */
   -    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) {
        }
    }
    
   @@ -1039,23 +1000,18 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
    {
        /* Clear the previous flag, MCG_SC[LOCS0]. */
        MCG->SC &= ~(uint8_t)MCG_SC_ATMF_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= ~(uint8_t)MCG_C6_CME0_MASK;
   -    }
   -    else
   -    {
   -        if (kMCG_MonitorInt == mode)
   -        {
   +    } else   {
   +        if (kMCG_MonitorInt == mode) {
                MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK;
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C2 |= MCG_C2_LOCRE0_MASK;
            }
            MCG->C6 |= MCG_C6_CME0_MASK;
   @@ -1069,16 +1025,15 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8 = MCG->C8;
    
        mcg_c8 &= ~(uint8_t)(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK);
    
   -    if (kMCG_MonitorNone != mode)
   -    {
   -        if (kMCG_MonitorReset == mode)
   -        {
   +    if (kMCG_MonitorNone != mode) {
   +        if (kMCG_MonitorReset == mode) {
                mcg_c8 |= MCG_C8_LOCRE1_MASK;
            }
            mcg_c8 |= MCG_C8_CME1_MASK;
   @@ -1093,29 +1048,24 @@
     *
     * param mode Monitor mode to set.
     */
   -void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
   +void
   +CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
    {
        uint8_t mcg_c8;
    
        /* Clear previous flag. */
        MCG->S = MCG_S_LOLS0_MASK;
    
   -    if (kMCG_MonitorNone == mode)
   -    {
   +    if (kMCG_MonitorNone == mode) {
            MCG->C6 &= (uint8_t)(~MCG_C6_LOLIE0_MASK);
   -    }
   -    else
   -    {
   +    } else   {
            mcg_c8 = MCG->C8;
    
            mcg_c8 &= (uint8_t)(~MCG_C8_LOCS1_MASK);
    
   -        if (kMCG_MonitorInt == mode)
   -        {
   +        if (kMCG_MonitorInt == mode) {
                mcg_c8 &= (uint8_t)(~MCG_C8_LOLRE_MASK);
   -        }
   -        else
   -        {
   +        } else   {
                mcg_c8 |= MCG_C8_LOLRE_MASK;
            }
            MCG->C8 = mcg_c8;
   @@ -1149,29 +1099,25 @@
     *
     * return  Logical OR value of the ref _mcg_status_flags_t.
     */
   -uint32_t CLOCK_GetStatusFlags(void)
   -{
   -    uint32_t ret  = 0U;
   +uint32_t
   +CLOCK_GetStatusFlags(void)
   +{
   +    uint32_t ret = 0U;
        uint8_t mcg_s = MCG->S;
    
   -    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U)
   -    {
   +    if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0LostFlag;
        }
   -    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Osc0InitFlag;
        }
   -    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK))
   -    {
   +    if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK)) {
            ret |= (uint32_t)kMCG_RtcOscLostFlag;
        }
   -    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOLS0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LostFlag;
        }
   -    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U)
   -    {
   +    if ((mcg_s & MCG_S_LOCK0_MASK) != 0U) {
            ret |= (uint32_t)kMCG_Pll0LockFlag;
        }
        return ret;
   @@ -1193,21 +1139,19 @@
     * param mask The status flags to clear. This is a logical OR of members of the
     *             enumeration ref _mcg_status_flags_t.
     */
   -void CLOCK_ClearStatusFlags(uint32_t mask)
   +void
   +CLOCK_ClearStatusFlags(uint32_t mask)
    {
        uint8_t reg;
    
   -    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL) {
            MCG->SC &= (uint8_t)(~MCG_SC_ATMF_MASK);
        }
   -    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag))
   -    {
   -        reg     = MCG->C8;
   +    if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag)) {
   +        reg = MCG->C8;
            MCG->C8 = reg;
        }
   -    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL)
   -    {
   +    if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL) {
            MCG->S = MCG_S_LOLS0_MASK;
        }
    }
   @@ -1219,7 +1163,8 @@
     *
     * param  config Pointer to the OSC0 configuration structure.
     */
   -void CLOCK_InitOsc0(osc_config_t const *config)
   +void
   +CLOCK_InitOsc0(osc_config_t const *config)
    {
        uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq);
    
   @@ -1228,11 +1173,9 @@
        MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode);
        OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
    
   -    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U))
   -    {
   +    if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)) {
            /* Wait for stable. */
   -        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -        {
   +        while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
            }
        }
    }
   @@ -1242,7 +1185,8 @@
     *
     * This function deinitializes the OSC0.
     */
   -void CLOCK_DeinitOsc0(void)
   +void
   +CLOCK_DeinitOsc0(void)
    {
        OSC0->CR = 0U;
        MCG->C2 &= ~(uint8_t)OSC_MODE_MASK;
   @@ -1253,7 +1197,8 @@
     *
     * param freq The Slow IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetSlowIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetSlowIrcFreq(uint32_t freq)
    {
        s_slowIrcFreq = freq;
    }
   @@ -1263,7 +1208,8 @@
     *
     * param freq The Fast IRC frequency input clock frequency in Hz.
     */
   -void CLOCK_SetFastIrcFreq(uint32_t freq)
   +void
   +CLOCK_SetFastIrcFreq(uint32_t freq)
    {
        s_fastIrcFreq = freq;
    }
   @@ -1286,7 +1232,8 @@
     * retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
     * retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
     */
   -status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
   +status_t
   +CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
    {
        uint32_t multi; /* extFreq / desireFreq */
        uint32_t actv;  /* Auto trim value. */
   @@ -1299,30 +1246,24 @@
            {TRIM_FIRC_MIN, TRIM_FIRC_MAX}  /* Fast IRC. */
        };
    
   -    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN))
   -    {
   +    if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) {
            status = kStatus_MCG_AtmBusClockInvalid;
        }
        /* Check desired frequency range. */
   -    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1]))
   -    {
   +    else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) {
            status = kStatus_MCG_AtmDesiredFreqInvalid;
        }
        /*
           Make sure internal reference clock is not used to generate bus clock.
           Here only need to check (MCG_S_IREFST == 1).
         */
   -    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK))
   -    {
   +    else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) {
            status = kStatus_MCG_AtmIrcUsed;
   -    }
   -    else
   -    {
   +    } else   {
            multi = extFreq / desireFreq;
   -        actv  = multi * 21U;
   -
   -        if (kMCG_AtmSel4m == atms)
   -        {
   +        actv = multi * 21U;
   +
   +        if (kMCG_AtmSel4m == atms) {
                actv *= 128U;
            }
    
   @@ -1336,27 +1277,20 @@
            MCG->SC = (mcg_sc | MCG_SC_ATME_MASK);
    
            /* Wait for MCG finished. */
   -        while (0U != (MCG->SC & MCG_SC_ATME_MASK))
   -        {
   +        while (0U != (MCG->SC & MCG_SC_ATME_MASK)) {
            }
    
            /* Error occurs? */
   -        if (0U != (MCG->SC & MCG_SC_ATMF_MASK))
   -        {
   +        if (0U != (MCG->SC & MCG_SC_ATMF_MASK)) {
                /* Clear the failed flag. */
                MCG->SC = mcg_sc;
   -            status  = kStatus_MCG_AtmHardwareFail;
   -        }
   -        else
   -        {
   +            status = kStatus_MCG_AtmHardwareFail;
   +        } else   {
                *actualFreq = extFreq / multi;
    
   -            if (kMCG_AtmSel4m == atms)
   -            {
   +            if (kMCG_AtmSel4m == atms) {
                    s_fastIrcFreq = *actualFreq;
   -            }
   -            else
   -            {
   +            } else   {
                    s_slowIrcFreq = *actualFreq;
                }
            }
   @@ -1372,103 +1306,83 @@
     *
     * return Current MCG mode or error code; See ref mcg_mode_t.
     */
   -mcg_mode_t CLOCK_GetMode(void)
   +mcg_mode_t
   +CLOCK_GetMode(void)
    {
        mcg_mode_t mode = kMCG_ModeError;
   -    uint32_t clkst  = (uint32_t)MCG_S_CLKST_VAL;
   +    uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL;
        uint32_t irefst = (uint32_t)MCG_S_IREFST_VAL;
   -    uint32_t lp     = (uint32_t)MCG_C2_LP_VAL;
   -    uint32_t pllst  = MCG_S_PLLST_VAL;
   +    uint32_t lp = (uint32_t)MCG_C2_LP_VAL;
   +    uint32_t pllst = MCG_S_PLLST_VAL;
    
        /*------------------------------------------------------------------
                               Mode and Registers
   -    ____________________________________________________________________
   -
   -      Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   -    ____________________________________________________________________
   -
   -      FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   -    ____________________________________________________________________
   -
   -      FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   -    ____________________________________________________________________
   -
   -      PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -      PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   -    ____________________________________________________________________
   -
   -      PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   -    ____________________________________________________________________
   -
   -      PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   -    ____________________________________________________________________
   -
   -    ----------------------------------------------------------------------*/
   -
   -    if (clkst == (uint32_t)kMCG_ClkOutStatFll)
   -    {
   -        if ((uint32_t)kMCG_FllSrcExternal == irefst)
   -        {
   +       ____________________________________________________________________
   +
   +       Mode   |   CLKST    |   IREFST   |   PLLST   |      LP
   +       ____________________________________________________________________
   +
   +       FEI    |  00(FLL)   |   1(INT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FEE    |  00(FLL)   |   0(EXT)   |   0(FLL)  |      X
   +       ____________________________________________________________________
   +
   +       FBE    |  10(EXT)   |   0(EXT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       FBI    |  01(INT)   |   1(INT)   |   0(FLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       BLPI   |  01(INT)   |   1(INT)   |   0(FLL)  |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       BLPE   |  10(EXT)   |   0(EXT)   |     X     |   1(LOW POWER)
   +       ____________________________________________________________________
   +
   +       PEE    |  11(PLL)   |   0(EXT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       PBE    |  10(EXT)   |   0(EXT)   |   1(PLL)  |   O(NORMAL)
   +       ____________________________________________________________________
   +
   +       PBI    |  01(INT)   |   1(INT)   |   1(PLL)  |   0(NORMAL)
   +       ____________________________________________________________________
   +
   +       PEI    |  11(PLL)   |   1(INT)   |   1(PLL)  |      X
   +       ____________________________________________________________________
   +
   +       ----------------------------------------------------------------------*/
   +
   +    if (clkst == (uint32_t)kMCG_ClkOutStatFll) {
   +        if ((uint32_t)kMCG_FllSrcExternal == irefst) {
                mode = kMCG_ModeFEE;
   -        }
   -        else
   -        {
   +        } else   {
                mode = kMCG_ModeFEI;
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatInt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatInt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPI;
   -        }
   -        else
   -        {
   +        } else   {
                {
                    mode = kMCG_ModeFBI;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatExt)
   -    {
   -        if (0U != lp)
   -        {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatExt)   {
   +        if (0U != lp) {
                mode = kMCG_ModeBLPE;
   -        }
   -        else
   -        {
   -            if ((uint32_t)kMCG_PllstPll == pllst)
   -            {
   +        } else   {
   +            if ((uint32_t)kMCG_PllstPll == pllst) {
                    mode = kMCG_ModePBE;
   -            }
   -            else
   -            {
   +            } else   {
                    mode = kMCG_ModeFBE;
                }
            }
   -    }
   -    else if (clkst == (uint32_t)kMCG_ClkOutStatPll)
   -    {
   +    } else if (clkst == (uint32_t)kMCG_ClkOutStatPll)   {
            {
                mode = kMCG_ModePEE;
            }
   -    }
   -    else
   -    {
   +    } else   {
            /*do nothing*/
        }
    
   @@ -1490,15 +1404,15 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to a frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode)))
   -    {
   +    if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1510,8 +1424,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1523,13 +1436,11 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1538,13 +1449,11 @@
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1566,15 +1475,15 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
    
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode)))
   -    {
   +    if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1586,8 +1495,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1600,45 +1508,37 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
        /* Set DRS and DMX32. */
   -    mcg_c4  = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
   +    mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
        MCG->C4 = mcg_c4;
    
        /* Wait for DRST_DRS update. */
   -    while (MCG->C4 != mcg_c4)
   -    {
   +    while (MCG->C4 != mcg_c4) {
        }
    
        /* Check MCG_S[CLKST] */
   -    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1661,7 +1561,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1670,9 +1571,7 @@
        mcg_mode_t mode = CLOCK_GetMode();
    
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModeBLPI == mode)))
   -
   -    {
   +          (kMCG_ModeBLPI == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1687,8 +1586,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1700,26 +1598,22 @@
                             | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
    
        /* Wait and check status. */
   -    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   -    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) {
        }
    
        MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) |
                            (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for FLL stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1741,7 +1635,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        uint8_t mcg_c4;
        bool change_drs = false;
   @@ -1749,16 +1644,14 @@
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
        if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
   -          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode)))
   -    {
   +          (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
    
        /* Change to FLL mode. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Set LP bit to enable the FLL */
   @@ -1772,8 +1665,7 @@
           reference clock source changes, then reset to previous value after
           reference clock changes.
         */
   -    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
   -    {
   +    if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) {
            change_drs = true;
            /* Change the LSB of DRST_DRS. */
            MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
   @@ -1786,24 +1678,19 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for Reference clock Status bit to clear */
   -    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
   -    {
   +    while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) {
        }
    
        /* Errata: ERR007993 */
   -    if (change_drs)
   -    {
   +    if (change_drs) {
            MCG->C4 = mcg_c4;
        }
    
   @@ -1812,13 +1699,11 @@
                           (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
    
        /* Wait for clock status bits to show clock source is ext ref clk */
   -    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
   -    {
   +    while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) {
        }
    
        /* Wait for fll stable time. */
   -    if (NULL != fllStableDelay)
   -    {
   +    if (NULL != fllStableDelay) {
            fllStableDelay();
        }
    
   @@ -1834,11 +1719,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpiMode(void)
   +status_t
   +CLOCK_SetBlpiMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1858,11 +1743,11 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_SetBlpeMode(void)
   +status_t
   +CLOCK_SetBlpeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1892,7 +1777,8 @@
     * configuration structure not necessary. In this case, pass in NULL.
     * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
     */
   -status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -1907,14 +1793,12 @@
    
        /* Wait for CLKST clock status bits to show clock source is ext ref clk */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* Disable PLL first, then configure PLL. */
        MCG->C6 &= (uint8_t)(~MCG_C6_PLLS_MASK);
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        /* Configure the PLL. */
   @@ -1926,8 +1810,7 @@
        MCG->C6 |= MCG_C6_PLLS_MASK;
    
        /* Wait for PLL mode changed. */
   -    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U)
   -    {
   +    while (((MCG->S & MCG_S_PLLST_MASK)) == 0U) {
        }
    
        return kStatus_Success;
   @@ -1945,12 +1828,12 @@
     *       PRDIV/VDIV are different than in the PBE mode, set them up
     *       in PBE mode and wait. When the clock is stable, switch to PEE mode.
     */
   -status_t CLOCK_SetPeeMode(void)
   +status_t
   +CLOCK_SetPeeMode(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
        mcg_mode_t mode = CLOCK_GetMode();
   -    if (kMCG_ModePBE != mode)
   -    {
   +    if (kMCG_ModePBE != mode) {
            return kStatus_MCG_ModeUnreachable;
        }
    #endif
   @@ -1959,8 +1842,7 @@
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
    
        /* Wait for clock status bits to update */
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -1982,11 +1864,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
     */
   -status_t CLOCK_ExternalModeToFbeModeQuick(void)
   +status_t
   +CLOCK_ExternalModeToFbeModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) != 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) != 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif /* MCG_CONFIG_CHECK_PARAM */
   @@ -1995,14 +1877,12 @@
        MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK);
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
        }
    
        /* Disable PLL. */
        MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK;
   -    while ((MCG->S & MCG_S_PLLST_MASK) != 0U)
   -    {
   +    while ((MCG->S & MCG_S_PLLST_MASK) != 0U) {
        }
    
        return kStatus_Success;
   @@ -2024,11 +1904,11 @@
     * retval kStatus_Success Switched successfully.
     * retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
     */
   -status_t CLOCK_InternalModeToFbiModeQuick(void)
   +status_t
   +CLOCK_InternalModeToFbiModeQuick(void)
    {
    #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
   -    if ((MCG->S & MCG_S_IREFST_MASK) == 0U)
   -    {
   +    if ((MCG->S & MCG_S_IREFST_MASK) == 0U) {
            return kStatus_MCG_ModeInvalid;
        }
    #endif
   @@ -2037,8 +1917,7 @@
        MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
    
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        return kStatus_Success;
   @@ -2059,7 +1938,8 @@
     * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
     * to frequency above 32768 Hz.
     */
   -status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
    }
   @@ -2079,8 +1959,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToFeeMode(
   -    mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
   +status_t
   +CLOCK_BootToFeeMode(mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2100,15 +1980,15 @@
     * retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
   +status_t
   +CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode)
    {
        /* If reset mode is FEI mode, set MCGIRCLK and always success. */
        (void)CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
    
        /* If reset mode is not BLPI, first enter FBI mode. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) {
        }
    
        /* Enter BLPI mode. */
   @@ -2128,7 +2008,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
   +status_t
   +CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
    {
        (void)CLOCK_SetExternalRefClkConfig(oscsel);
    
   @@ -2138,20 +2019,16 @@
                             | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
    
        /* If use external crystal as clock source, wait for it stable. */
   -    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
   -    {
   -        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK))
   -        {
   -            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK))
   -            {
   +    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) {
   +        if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) {
   +            while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) {
                }
            }
        }
    
        /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
        while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
   -           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
   -    {
   +           (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) {
        }
    
        /* In FBE now, start to enter BLPE. */
   @@ -2173,7 +2050,8 @@
     * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
     * retval kStatus_Success Switched to the target mode successfully.
     */
   -status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
   +status_t
   +CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
    {
        assert(config);
    
   @@ -2183,8 +2061,7 @@
    
        /* Change to use PLL output clock. */
        MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut));
   -    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll)
   -    {
   +    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) {
        }
    
        return kStatus_Success;
   @@ -2233,7 +2110,8 @@
     * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
     * function.
     */
   -status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
   +status_t
   +CLOCK_SetMcgConfig(const mcg_config_t *config)
    {
        mcg_mode_t next_mode;
        status_t status = kStatus_Success;
   @@ -2241,11 +2119,9 @@
        mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0;
    
        /* If need to change external clock, MCG_C7[OSCSEL]. */
   -    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel))
   -    {
   +    if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel)) {
            /* If external clock is in use, change to FEI first. */
   -        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
   -        {
   +        if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) {
                (void)CLOCK_ExternalModeToFbeModeQuick();
                (void)CLOCK_SetFeiMode(config->dmx32, config->drs, NULL);
            }
   @@ -2254,8 +2130,7 @@
        }
    
        /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
   -    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt)
   -    {
   +    if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt) {
            MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */
    
            {
   @@ -2268,67 +2143,56 @@
    
        next_mode = CLOCK_GetMode();
    
   -    do
   -    {
   +    do{
            next_mode = mcgModeMatrix[next_mode][config->mcgMode];
    
   -        switch (next_mode)
   -        {
   -            case kMCG_ModeFEI:
   -                status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFEE:
   -                status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   -                break;
   -            case kMCG_ModeFBI:
   -                status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeFBE:
   -                status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   -                break;
   -            case kMCG_ModeBLPI:
   -                status = CLOCK_SetBlpiMode();
   -                break;
   -            case kMCG_ModeBLPE:
   -                status = CLOCK_SetBlpeMode();
   -                break;
   -            case kMCG_ModePBE:
   -                /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   -                if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode))
   +        switch (next_mode) {
   +        case kMCG_ModeFEI:
   +            status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFEE:
   +            status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
   +            break;
   +        case kMCG_ModeFBI:
   +            status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeFBE:
   +            status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL);
   +            break;
   +        case kMCG_ModeBLPI:
   +            status = CLOCK_SetBlpiMode();
   +            break;
   +        case kMCG_ModeBLPE:
   +            status = CLOCK_SetBlpeMode();
   +            break;
   +        case kMCG_ModePBE:
   +            /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
   +            if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) {
                    {
   -                    {
   -                        status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
   -                    }
   +                    status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
                    }
   -                else
   -                {
   -                    MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   -                    while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt)
   -                    {
   -                    }
   +            } else   {
   +                MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
   +                while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) {
                    }
   -                break;
   -            case kMCG_ModePEE:
   -                status = CLOCK_SetPeeMode();
   -                break;
   -            default:
   -                assert(false);
   -                break;
   -        }
   -        if (kStatus_Success != status)
   -        {
   +            }
                break;
   +        case kMCG_ModePEE:
   +            status = CLOCK_SetPeeMode();
   +            break;
   +        default:
   +            assert(false);
   +            break;
   +        }
   +        if (kStatus_Success != status) {
   +            break;
            }
        } while (next_mode != config->mcgMode);
    
   -    if (status == kStatus_Success)
   -    {
   -        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U)
   -        {
   +    if (status == kStatus_Success) {
   +        if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U) {
                CLOCK_EnablePll0(&config->pll0Config);
   -        }
   -        else
   -        {
   +        } else   {
                MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/include/hal_lpuart_nxp.h
   <details>
   
   ```diff
   @@ -21,7 +21,7 @@
    #define __MCU_K8XF_HAL_UART_H_
    
    #ifdef __cplusplus
   - extern "C" {
   +extern "C" {
    #endif
    
    #define NXP_UART_EXISTS      { 1, \
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/include/mcu/kinetis_common.h
   <details>
   
   ```diff
   @@ -21,7 +21,7 @@
    #define __KINETIS_COMMON_H_
    
    #ifdef __cplusplus
   - extern "C" {
   +extern "C" {
    #endif
    
    #if MYNEWT_VAL(BSP_MK64F12)
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/include/mcu/kinetis_hal.h
   <details>
   
   ```diff
   @@ -21,7 +21,7 @@
    #define __KINETIS_HAL_H_
    
    #ifdef __cplusplus
   - extern "C" {
   +extern "C" {
    #endif
    
    struct nxp_hal_i2c_cfg {
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_flash.c
   <details>
   
   ```diff
   @@ -6,7 +6,7 @@
     * to you under the Apache License, Version 2.0 (the
     * "License"); you may not use this file except in compliance
     * with the License.  You may obtain a copy of the License at
   -*
   + *
     *  http://www.apache.org/licenses/LICENSE-2.0
     *
     * Unless required by applicable law or agreed to in writing,
   @@ -40,13 +40,13 @@
    #define KINETIS_FLASH_ALIGN MYNEWT_VAL(MCU_FLASH_MIN_WRITE_SIZE)
    
    static int kinetis_flash_read(const struct hal_flash *dev, uint32_t address,
   -        void *dst, uint32_t num_bytes);
   +                              void *dst, uint32_t num_bytes);
    static int kinetis_flash_write(const struct hal_flash *dev, uint32_t address,
   -        const void *src, uint32_t num_bytes);
   +                               const void *src, uint32_t num_bytes);
    static int kinetis_flash_erase_sector(const struct hal_flash *dev,
   -        uint32_t sector_address);
   +                                      uint32_t sector_address);
    static int kinetis_flash_sector_info(const struct hal_flash *dev, int idx,
   -        uint32_t *addr, uint32_t *sz);
   +                                     uint32_t *addr, uint32_t *sz);
    static int kinetis_flash_init(const struct hal_flash *dev);
    
    static const struct hal_flash_funcs kinetis_flash_funcs = {
   @@ -68,9 +68,9 @@
    
    static int
    kinetis_flash_read(const struct hal_flash *dev,
   -                 uint32_t address,
   -                 void *dst,
   -                 uint32_t num_bytes)
   +                   uint32_t address,
   +                   void *dst,
   +                   uint32_t num_bytes)
    {
        memcpy(dst, (void *)address, num_bytes);
        return 0;
   @@ -78,9 +78,9 @@
    
    static int
    kinetis_flash_write(const struct hal_flash *dev,
   -                  uint32_t address,
   -                  const void *src,
   -                  uint32_t len)
   +                    uint32_t address,
   +                    const void *src,
   +                    uint32_t len)
    {
        uint8_t padded[KINETIS_FLASH_ALIGN];
        uint8_t pad_len;
   @@ -142,9 +142,9 @@
    
    static int
    kinetis_flash_sector_info(const struct hal_flash *dev,
   -                        int idx,
   -                        uint32_t *addr,
   -                        uint32_t *sz)
   +                          int idx,
   +                          uint32_t *addr,
   +                          uint32_t *sz)
    {
        uint32_t sector_size;
        FLASH_GetProperty(&kinetis_config,
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_gpio.c
   <details>
   
   ```diff
   @@ -53,8 +53,7 @@
    uint16_t
    hal_to_fsl_pull(hal_gpio_pull_t pull)
    {
   -    switch ((int)pull)
   -    {
   +    switch ((int)pull) {
        case HAL_GPIO_PULL_UP:
            return kPORT_PullUp;
        case HAL_GPIO_PULL_DOWN:
   @@ -304,9 +303,9 @@
    #endif
            memset(&hal_gpio_irqs[entry], 0, sizeof(struct hal_gpio_irq));
            if (hal_gpio_find_port(GPIO_PORT(pin)) < 0) {
   -                NVIC_ClearPendingIRQ(GPIO_PORT(pin));
   -                NVIC_DisableIRQ(GPIO_PORT(pin));
   -            }
   +            NVIC_ClearPendingIRQ(GPIO_PORT(pin));
   +            NVIC_DisableIRQ(GPIO_PORT(pin));
   +        }
        }
    }
    
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_i2c.c
   <details>
   
   ```diff
   @@ -33,10 +33,10 @@
    #define NXP_HAL_I2C_MAX 4
    
    struct nxp_hal_i2c {
   -    I2C_Type* dev;
   +    I2C_Type * dev;
        uint32_t scl_pin;
        uint32_t sda_pin;
   -    PORT_Type *port; 
   +    PORT_Type *port;
        port_mux_t mux;
        IRQn_Type irqn;
        void (*irq_handler)(void);
   @@ -170,7 +170,7 @@
        os_sem_release(&i2c->sync);
    }
    
   -static struct nxp_hal_i2c*
   +static struct nxp_hal_i2c *
    hal_i2c_resolve(uint8_t i2c_num)
    {
        if (i2c_num >= NXP_HAL_I2C_MAX) {
   @@ -289,7 +289,7 @@
    
        i2c = hal_i2c_resolve(i2c_num);
        if (!i2c) {
   -       return HAL_I2C_ERR_INVAL;
   +        return HAL_I2C_ERR_INVAL;
        }
    
        return i2c_config(i2c, cfg->frequency);
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_lpuart.c
   <details>
   
   ```diff
   @@ -50,22 +50,22 @@
    };
    
    struct hal_uart {
   -    LPUART_Type      *u_base;
   -    clock_name_t     clk_src;
   -    uint32_t         u_irq;
   -    PORT_Type       *p_base;
   -    clock_ip_name_t  p_clock;
   -    int  u_pin_rx;
   -    int  u_pin_tx;
   +    LPUART_Type *u_base;
   +    clock_name_t clk_src;
   +    uint32_t u_irq;
   +    PORT_Type *p_base;
   +    clock_ip_name_t p_clock;
   +    int u_pin_rx;
   +    int u_pin_tx;
        /* TODO: support flow control pins */
        hal_uart_rx_char u_rx_func;
        hal_uart_tx_char u_tx_func;
        hal_uart_tx_done u_tx_done;
        void *u_func_arg;
   -    uint8_t u_configured:1;
   -    uint8_t u_open:1;
   -    uint8_t u_tx_started:1;
   -    uint8_t u_rx_stall:1;
   +    uint8_t u_configured : 1;
   +    uint8_t u_open : 1;
   +    uint8_t u_tx_started : 1;
   +    uint8_t u_rx_stall : 1;
        struct uart_ring ur_tx;
        uint8_t tx_buffer[TX_BUF_SZ];
        struct uart_ring ur_rx;
   @@ -98,17 +98,20 @@
     * RING BUFFER FUNCTIONS
     */
    
   -static uint8_t ur_is_empty(struct uart_ring *ur)
   +static uint8_t
   +ur_is_empty(struct uart_ring *ur)
    {
        return (ur->ur_head == ur->ur_tail);
    }
    
   -static uint8_t ur_is_full(struct uart_ring *ur)
   +static uint8_t
   +ur_is_full(struct uart_ring *ur)
    {
        return (((ur->ur_tail + 1) % ur->ur_size) == ur->ur_head);
    }
    
   -static void ur_bump(struct uart_ring *ur)
   +static void
   +ur_bump(struct uart_ring *ur)
    {
        if (!ur_is_empty(ur)) {
            ur->ur_head++;
   @@ -117,12 +120,14 @@
        }
    }
    
   -static uint8_t ur_read(struct uart_ring *ur)
   +static uint8_t
   +ur_read(struct uart_ring *ur)
    {
        return ur->ur_buf[ur->ur_head];
    }
    
   -static int ur_queue(struct uart_ring *ur, uint8_t data)
   +static int
   +ur_queue(struct uart_ring *ur, uint8_t data)
    {
        if (!ur_is_full(ur)) {
            ur->ur_buf[ur->ur_tail] = data;
   @@ -137,11 +142,12 @@
     * END RING BUFFER FUNCTIONS
     */
    
   -int hal_uart_init_cbs(int port,
   -                      hal_uart_tx_char tx_func,
   -                      hal_uart_tx_done tx_done,
   -                      hal_uart_rx_char rx_func,
   -                      void *arg)
   +int
   +hal_uart_init_cbs(int port,
   +                  hal_uart_tx_char tx_func,
   +                  hal_uart_tx_done tx_done,
   +                  hal_uart_rx_char rx_func,
   +                  void *arg)
    {
        struct hal_uart *u;
    
   @@ -157,7 +163,8 @@
        return 0;
    }
    
   -void hal_uart_blocking_tx(int port, uint8_t byte)
   +void
   +hal_uart_blocking_tx(int port, uint8_t byte)
    {
        struct hal_uart *u;
    
   @@ -194,7 +201,8 @@
        return i;
    }
    
   -void hal_uart_start_tx(int port)
   +void
   +hal_uart_start_tx(int port)
    {
        struct hal_uart *u;
        int data = -1;
   @@ -209,8 +217,7 @@
        }
    
        /* main loop */
   -    while (true)
   -    {
   +    while (true) {
            /* add data to TX ring buffer */
            if (u->u_tx_started == 0) {
                rc = hal_uart_tx_fill_buf(u);
   @@ -293,8 +300,9 @@
            if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base)) {
                if (u->u_tx_started) {
                    u->u_tx_started = 0;
   -                if (u->u_tx_done)
   +                if (u->u_tx_done) {
                        u->u_tx_done(u->u_func_arg);
   +                }
                }
            }
        }
   @@ -434,24 +442,23 @@
    {
        if (s_uartExists[port]) {
            if (s_uartEnabled[port]) {
   -            uarts[port].u_base        = s_uartBases[port];
   -            uarts[port].clk_src       = s_uartClocks[port];
   -            uarts[port].u_irq         = s_uartIRQ[port];
   -            uarts[port].p_base        = s_uartPort[port];
   -            uarts[port].p_clock       = s_uartPortClocks[port];
   -            uarts[port].u_pin_rx      = s_uartPIN_RX[port];
   -            uarts[port].u_pin_tx      = s_uartPIN_TX[port];
   -            uarts[port].ur_tx.ur_buf  = uarts[port].tx_buffer;
   +            uarts[port].u_base = s_uartBases[port];
   +            uarts[port].clk_src = s_uartClocks[port];
   +            uarts[port].u_irq = s_uartIRQ[port];
   +            uarts[port].p_base = s_uartPort[port];
   +            uarts[port].p_clock = s_uartPortClocks[port];
   +            uarts[port].u_pin_rx = s_uartPIN_RX[port];
   +            uarts[port].u_pin_tx = s_uartPIN_TX[port];
   +            uarts[port].ur_tx.ur_buf = uarts[port].tx_buffer;
                uarts[port].ur_tx.ur_size = TX_BUF_SZ;
                uarts[port].ur_tx.ur_head = 0;
                uarts[port].ur_tx.ur_tail = 0;
   -            uarts[port].ur_rx.ur_buf  = uarts[port].rx_buffer;
   +            uarts[port].ur_rx.ur_buf = uarts[port].rx_buffer;
                uarts[port].ur_rx.ur_size = RX_BUF_SZ;
                uarts[port].ur_rx.ur_head = 0;
                uarts[port].ur_rx.ur_tail = 0;
   -            uarts[port].u_configured  = 1;
   -        }
   -        else {
   +            uarts[port].u_configured = 1;
   +        } else   {
                uarts[port].u_configured = 0;
            }
        }
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_qspi.c
   <details>
   
   ```diff
   @@ -107,7 +107,8 @@
        [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
    
        /* Match MISRA rule */
   -    [63] = 0};
   +    [63] = 0
   +};
    
    qspi_flash_config_t g_qspi_flash_cfg = {
        .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
   @@ -132,15 +133,12 @@
    {
        uint32_t val = 0;
        /* Check WIP bit */
   -    do
   -    {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +    do{
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
            QSPI_ExecuteIPCommand(QuadSPI0, 12U);
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            val = QuadSPI0->RBDR[0];
            /* Clear ARDB area */
   @@ -151,19 +149,17 @@
    static void
    cmd_write_enable()
    {
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ExecuteIPCommand(QuadSPI0, 4U);
    }
    
    static void
   -read_page(uint32_t address, uint32_t* dst)
   +read_page(uint32_t address, uint32_t * dst)
    {
        int i;
   -    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
   -    {
   -        dst[i] = ((uint32_t*)address)[i];
   +    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++) {
   +        dst[i] = ((uint32_t *)address)[i];
        }
    }
    
   @@ -195,15 +191,13 @@
    {
        uint32_t leftLongWords = 0;
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
    
        QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
        cmd_write_enable();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
    
        /* First write some data into TXFIFO to prevent from underrun */
   @@ -219,8 +213,7 @@
    
        /* Wait until flash finished program */
        check_if_finished();
   -    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess)) {
        }
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   @@ -244,7 +237,7 @@
    
        npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        while (npages) {
   -        write_page(address, (uint32_t*) src);
   +        write_page(address, (uint32_t *) src);
            npages--;
            address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
        }
   @@ -253,13 +246,12 @@
    
    static int
    nxp_qspi_erase_sector(const struct hal_flash *dev,
   -                         uint32_t sector_address)
   +                      uint32_t sector_address)
    {
        sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
        sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
        QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
   @@ -286,8 +278,7 @@
        nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
    
        while (nsects) {
   -        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -        {
   +        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
            }
            QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
            QSPI_SetIPCommandAddress(QuadSPI0, address);
   @@ -296,7 +287,7 @@
            check_if_finished();
    
    #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
   -    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
   +        (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
            QSPI_ClearCache(QuadSPI0);
    #endif
            nsects--;
   @@ -323,8 +314,7 @@
    {
        uint32_t val[4] = {0x40U, 0, 0, 0};
    
   -    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
   -    {
   +    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) {
        }
        QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
    
   @@ -373,7 +363,7 @@
        PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB2), MYNEWT_VAL(QSPIB_MUX));
        PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOBA), MYNEWT_VAL(QSPIB_MUX));
    
   -    //Configure the baudrate too.
   +    /*Configure the baudrate too. */
    
        QSPI_Init(QuadSPI0, &qspi_cfg, CLOCK_GetFreq(kCLOCK_McgPll0Clk));
    
   @@ -390,21 +380,21 @@
    }
    
    static const struct hal_flash_funcs nxp_qspi_funcs = {
   -        .hff_read = nxp_qspi_read,
   -        .hff_write = nxp_qspi_write,
   -        .hff_erase_sector = nxp_qspi_erase_sector,
   -        .hff_sector_info = nxp_qspi_sector_info,
   -        .hff_init = nxp_qspi_init,
   -        .hff_erase = nxp_qspi_erase
   -    };
   +    .hff_read = nxp_qspi_read,
   +    .hff_write = nxp_qspi_write,
   +    .hff_erase_sector = nxp_qspi_erase_sector,
   +    .hff_sector_info = nxp_qspi_sector_info,
   +    .hff_init = nxp_qspi_init,
   +    .hff_erase = nxp_qspi_erase
   +};
    
    const struct hal_flash nxp_qspi_dev = {
   -        .hf_itf = &nxp_qspi_funcs,
   -        .hf_base_addr = FSL_FEATURE_QSPI_AMBA_BASE,
   -        .hf_size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE),
   -        .hf_sector_cnt = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT),
   -        .hf_align = 8,
   -        .hf_erased_val = 0xff,
   -    };
   -
   -#endif
   +    .hf_itf = &nxp_qspi_funcs,
   +    .hf_base_addr = FSL_FEATURE_QSPI_AMBA_BASE,
   +    .hf_size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE),
   +    .hf_sector_cnt = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT),
   +    .hf_align = 8,
   +    .hf_erased_val = 0xff,
   +};
   +
   +#endif
   ```
   
   </details>
   
   #### hw/mcu/nxp/kinetis/src/hal_spi.c
   <details>
   
   ```diff
   @@ -38,7 +38,7 @@
    };
    
    struct nxp_hal_spi {
   -    SPI_Type* dev;
   +    SPI_Type * dev;
        uint32_t clk_pin;
        uint32_t pcs_pin;
        uint32_t sout_pin;
   @@ -48,7 +48,7 @@
        IRQn_Type irqn;
        void (*irq_handler)(void);
        hal_spi_txrx_cb txrx_cb;
   -    void* txrx_cb_arg;
   +    void * txrx_cb_arg;
        bool enabled;
        enum spi_type_t type;
    };
   @@ -265,7 +265,7 @@
    static void
    hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
    {
   -    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
   +    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
    
        if (status == kStatus_Success) {
            if (spi->txrx_cb) {
   @@ -277,7 +277,7 @@
    static void
    hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
    {
   -    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
   +    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
    
        if (status == kStatus_Success) {
            if (spi->txrx_cb) {
   @@ -293,7 +293,7 @@
        struct nxp_spi_master *master;
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   +        master = (struct nxp_spi_master *) spi;
            PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
   @@ -311,7 +311,7 @@
        struct nxp_spi_slave *slave;
    
        if (spi->type == HAL_SPI_TYPE_SLAVE) {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
            PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
   @@ -406,7 +406,7 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   +        master = (struct nxp_spi_master *) spi;
    
            master->config.ctarConfig.baudRate = settings->baudrate;
            master->config.ctarConfig.pcsToSckDelayInNanoSec =
   @@ -424,7 +424,7 @@
            master->config.ctarConfig.cpol = cpol;
            master->config.ctarConfig.cpha = cpha;
        } else {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            slave->config.ctarConfig.bitsPerFrame =
                (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
            slave->config.ctarConfig.cpol = cpol;
   @@ -448,13 +448,13 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -    master = (struct nxp_spi_master*) spi;
   -    DSPI_MasterInit(spi->dev,
   +        master = (struct nxp_spi_master *) spi;
   +        DSPI_MasterInit(spi->dev,
                        &master->config,
                        CLOCK_GetFreq(kCLOCK_BusClk));
        } else {
   -    slave = (struct nxp_spi_slave*) spi;
   -    DSPI_SlaveInit(spi->dev, &slave->config);
   +        slave = (struct nxp_spi_slave *) spi;
   +        DSPI_SlaveInit(spi->dev, &slave->config);
        }
    
        spi->enabled = true;
   @@ -496,8 +496,8 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        xfer.txData = (uint8_t*) &val;
   -        xfer.rxData = (uint8_t*) &retval;
   +        xfer.txData = (uint8_t *) &val;
   +        xfer.rxData = (uint8_t *) &retval;
            xfer.dataSize = 1;
            xfer.configFlags = kDSPI_MasterCtar0;
            DSPI_MasterTransferBlocking(spi->dev, &xfer);
   @@ -518,8 +518,8 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        xfer.txData = (uint8_t*) txbuf;
   -        xfer.rxData = (uint8_t*) rxbuf;
   +        xfer.txData = (uint8_t *) txbuf;
   +        xfer.rxData = (uint8_t *) rxbuf;
            xfer.dataSize = len;
            xfer.configFlags = kDSPI_MasterCtar0;
            rc = DSPI_MasterTransferBlocking(spi->dev, &xfer);
   @@ -556,26 +556,26 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   -        //master->handle
   +        master = (struct nxp_spi_master *) spi;
   +        /*master->handle */
            DSPI_MasterTransferCreateHandle(spi->dev,
                                            &master->handle,
                                            hal_spi_master_xfer_cb,
                                            spi);
            xfer.configFlags = kDSPI_MasterCtar0;
   -        xfer.txData = (uint8_t*) txbuf;
   -        xfer.rxData = (uint8_t*) rxbuf;
   +        xfer.txData = (uint8_t *) txbuf;
   +        xfer.rxData = (uint8_t *) rxbuf;
            xfer.dataSize = len;
            rc = DSPI_MasterTransferNonBlocking(spi->dev, &master->handle, &xfer);
        } else {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            DSPI_SlaveTransferCreateHandle(spi->dev,
                                           &slave->handle,
                                           hal_spi_slave_xfer_cb,
                                           spi);
            xfer.configFlags = kDSPI_SlaveCtar0;
   -        xfer.txData = (uint8_t*) txbuf;
   -        xfer.rxData = (uint8_t*) rxbuf;
   +        xfer.txData = (uint8_t *) txbuf;
   +        xfer.rxData = (uint8_t *) rxbuf;
            xfer.dataSize = len;
            rc = DSPI_SlaveTransferNonBlocking(spi->dev, &slave->handle, &xfer);
    
   @@ -614,10 +614,10 @@
        }
    
        if (spi->type == HAL_SPI_TYPE_MASTER) {
   -        master = (struct nxp_spi_master*) spi;
   +        master = (struct nxp_spi_master *) spi;
            DSPI_MasterTransferAbort(spi->dev, &master->handle);
        } else {
   -        slave = (struct nxp_spi_slave*) spi;
   +        slave = (struct nxp_spi_slave *) spi;
            DSPI_SlaveTransferAbort(spi->dev, &slave->handle);
        }
        return 0;
   ```
   
   </details>
   
   #### hw/bsp/frdm-k64f/src/hal_bsp.c
   <details>
   
   ```diff
   @@ -98,7 +98,8 @@
        }
    };
    
   -static void init_hardware(void)
   +static void
   +init_hardware(void)
    {
        /* Disable the MPU otherwise USB cannot access the bus */
        SYSMPU->CESR = 0;
   ```
   
   </details>


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[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
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[GitHub] [mynewt-core] utzig commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
utzig commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570142953



##########
File path: hw/mcu/nxp/kinetis/src/hal_hw_id.c
##########
@@ -22,26 +22,27 @@
 
 #include <hal/hal_bsp.h>
 
-#include "MK64F12.h"
+#include "fsl_sim.h"
 
 #ifndef min
 #define min(a, b) ((a)<(b)?(a):(b))
 #endif
 
-#define MK64F12_HW_ID_LEN     7
+#define MK8xF_HW_ID_LEN sizeof(sim_uid_t)

Review comment:
       Should be called `KINETIS_HW_ID_LEN` or some similar family name.

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,624 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type* dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void* txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave*) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }
+    return 0;
+}
+
+int
+hal_spi_enable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (spi->enabled) {
+        return 0;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+    master = (struct nxp_spi_master*) spi;
+    DSPI_MasterInit(spi->dev,
+                    &master->config,
+                    CLOCK_GetFreq(kCLOCK_BusClk));
+    } else {
+    slave = (struct nxp_spi_slave*) spi;
+    DSPI_SlaveInit(spi->dev, &slave->config);
+    }

Review comment:
       `if` and `else` blocks are indented incorrectly.

##########
File path: hw/mcu/nxp/kinetis/src/hal_lpuart.c
##########
@@ -0,0 +1,460 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+
+#include "os/mynewt.h"
+#include "hal/hal_uart.h"
+#include "hal/hal_gpio.h"
+#include "hal/hal_system.h"
+#include "mcu/cmsis_nvic.h"
+#include "bsp/bsp.h"
+
+#include "mcu/frdm-k8xf_hal.h"

Review comment:
       Don't other Kinetis MCU families also support LP-UARTS?

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
+
+    /* Clear Tx FIFO */
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    /* Write enable */
+    cmd_write_enable();
+
+    /* Write data into TX FIFO, needs to write at least 16 bytes of data */
+    QSPI_WriteBlocking(QuadSPI0, val, 16U);
+
+    /* Set seq id, write register */
+    QSPI_ExecuteIPCommand(QuadSPI0, 20);
+
+    /* Wait until finished */
+    check_if_finished();
+}
+
+static int
+nxp_qspi_init(const struct hal_flash *dev)
+{
+    qspi_config_t qspi_cfg = {0};
+
+    /*Get QSPI default settings and configure the qspi */
+    QSPI_GetDefaultQspiConfig(&qspi_cfg);
+
+    /*Set AHB buffer size for reading data through AHB bus */
+/* #if MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) <= FSL_FEATURE_QSPI_AHB_BUFFER_SIZE */
+    qspi_cfg.AHBbufferSize[3] = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+/* #else */
+/*     qspi_cfg.AHBbufferSize[3] = FSL_FEATURE_QSPI_AHB_BUFFER_SIZE; */
+/* #endif */
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SCKA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SSA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA0), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA1), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA2), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIO3A), MYNEWT_VAL(QSPIA_MUX));
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SCKB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SSB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB0), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB1), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB2), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOBA), MYNEWT_VAL(QSPIB_MUX));
+
+    //Configure the baudrate too.
+
+    QSPI_Init(QuadSPI0, &qspi_cfg, CLOCK_GetFreq(kCLOCK_McgPll0Clk));
+
+    memcpy(g_qspi_flash_cfg.lookuptable, lut, sizeof(lut));
+    /*According to serial flash feature to configure flash settings */
+    QSPI_SetFlashConfig(QuadSPI0, &g_qspi_flash_cfg);
+
+#if FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC
+    QSPI_ClearCache(QuadSPI0);
+#endif
+
+    enable_quad_mode();
+    return 0;
+}
+
+static const struct hal_flash_funcs nxp_qspi_funcs = {
+        .hff_read = nxp_qspi_read,
+        .hff_write = nxp_qspi_write,
+        .hff_erase_sector = nxp_qspi_erase_sector,
+        .hff_sector_info = nxp_qspi_sector_info,
+        .hff_init = nxp_qspi_init,
+        .hff_erase = nxp_qspi_erase
+    };
+
+const struct hal_flash nxp_qspi_dev = {
+        .hf_itf = &nxp_qspi_funcs,
+        .hf_base_addr = FSL_FEATURE_QSPI_AMBA_BASE,
+        .hf_size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE),
+        .hf_sector_cnt = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT),
+        .hf_align = 8,
+        .hf_erased_val = 0xff,
+    };

Review comment:
       Both structs need to be dedented.

##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,412 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type* dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port; 
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *userData)
+{
+    struct nxp_hal_i2c *i2c = userData;
+    i2c->stat = status;
+    os_sem_release(&i2c->sync);
+}
+
+static struct nxp_hal_i2c*
+hal_i2c_resolve(uint8_t i2c_num)
+{
+    if (i2c_num >= NXP_HAL_I2C_MAX) {
+        return NULL;
+    }
+
+    return i2c_modules[i2c_num];
+}
+
+static void
+i2c_init_hw(struct nxp_hal_i2c *i2c, int pin_scl, int pin_sda)
+{
+    uint32_t clock_freq;
+    i2c_master_config_t master_cfg;
+
+    const port_pin_config_t pincfg = {
+        kPORT_PullUp,
+        kPORT_FastSlewRate,
+        kPORT_PassiveFilterDisable,
+        kPORT_OpenDrainEnable,
+        kPORT_LowDriveStrength,
+        i2c->mux,
+        kPORT_UnlockRegister
+    };
+    PORT_SetPinConfig(i2c->port, i2c->scl_pin, &pincfg);
+    PORT_SetPinConfig(i2c->port, i2c->sda_pin, &pincfg);
+
+    clock_freq = CLOCK_GetFreq(kCLOCK_BusClk);
+    I2C_MasterGetDefaultConfig(&master_cfg);
+    I2C_MasterInit(i2c->dev, &master_cfg, clock_freq);
+
+    I2C_MasterTransferCreateHandle(i2c->dev, &i2c->handle, master_xfer_cb, i2c);
+    NVIC_ClearPendingIRQ(i2c->irqn);
+    NVIC_SetVector(i2c->irqn, (uint32_t) i2c->irq_handler);
+    NVIC_EnableIRQ(i2c->irqn);
+}
+
+static int
+i2c_config(struct nxp_hal_i2c *i2c, uint32_t frequency)
+{
+    uint32_t clock_freq;
+    uint32_t baudrate;
+
+    switch (frequency) {
+    case 100:
+        baudrate = 100000U;
+        break;
+    case 400:
+        baudrate = 400000U;
+        break;
+    case 1000:
+        baudrate = 1000000U;
+        break;
+    default:

Review comment:
       Could also be:
   
   ```
       case 100: /* fallthrough */
       case 400: /* fallthrough */
       case 1000:
           baudrate = frequency * 1000;
           break;
   ```

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,624 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type* dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void* txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave*) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }
+    return 0;
+}
+
+int
+hal_spi_enable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (spi->enabled) {
+        return 0;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+    master = (struct nxp_spi_master*) spi;
+    DSPI_MasterInit(spi->dev,
+                    &master->config,
+                    CLOCK_GetFreq(kCLOCK_BusClk));
+    } else {
+    slave = (struct nxp_spi_slave*) spi;
+    DSPI_SlaveInit(spi->dev, &slave->config);
+    }
+
+    spi->enabled = true;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_SetVector(spi->irqn, (uint32_t) spi->irq_handler);
+    NVIC_EnableIRQ(spi->irqn);
+    return 0;
+}
+
+int
+hal_spi_disable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (!spi->enabled) {
+        return 0;
+    }
+
+    DSPI_Deinit(spi->dev);
+
+    spi->enabled = false;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_DisableIRQ(spi->irqn);
+    return 0;
+}
+
+uint16_t
+hal_spi_tx_val(int spi_num, uint16_t val)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    uint16_t retval = 0;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t*) &val;
+        xfer.rxData = (uint8_t*) &retval;
+        xfer.dataSize = 1;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return retval;
+    }
+    return 0xFFFF; /* Invalid API. */
+}
+
+int
+hal_spi_txrx(int spi_num, void *txbuf, void *rxbuf, int len)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    status_t rc;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t*) txbuf;
+        xfer.rxData = (uint8_t*) rxbuf;
+        xfer.dataSize = len;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        rc = DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return (rc == kStatus_Success) ? 0 : rc;
+    }
+    return -1;
+}
+
+int
+hal_spi_set_txrx_cb(int spi_num, hal_spi_txrx_cb txrx_cb, void *arg)
+{
+    struct nxp_hal_spi *spi;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    spi->txrx_cb = txrx_cb;
+    spi->txrx_cb_arg = arg;
+    return 0;
+}
+
+int
+hal_spi_txrx_noblock(int spi_num, void *txbuf, void *rxbuf, int len)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_transfer_t xfer;
+    status_t rc;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+        //master->handle

Review comment:
       Remove the comment.

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
+
+    /* Clear Tx FIFO */
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    /* Write enable */
+    cmd_write_enable();
+
+    /* Write data into TX FIFO, needs to write at least 16 bytes of data */
+    QSPI_WriteBlocking(QuadSPI0, val, 16U);
+
+    /* Set seq id, write register */
+    QSPI_ExecuteIPCommand(QuadSPI0, 20);
+
+    /* Wait until finished */
+    check_if_finished();
+}
+
+static int
+nxp_qspi_init(const struct hal_flash *dev)
+{
+    qspi_config_t qspi_cfg = {0};
+
+    /*Get QSPI default settings and configure the qspi */
+    QSPI_GetDefaultQspiConfig(&qspi_cfg);
+
+    /*Set AHB buffer size for reading data through AHB bus */
+/* #if MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) <= FSL_FEATURE_QSPI_AHB_BUFFER_SIZE */
+    qspi_cfg.AHBbufferSize[3] = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+/* #else */
+/*     qspi_cfg.AHBbufferSize[3] = FSL_FEATURE_QSPI_AHB_BUFFER_SIZE; */
+/* #endif */

Review comment:
       Commented out code should be removed?

##########
File path: hw/mcu/nxp/kinetis/src/hal_lpuart.c
##########
@@ -0,0 +1,460 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+
+#include "os/mynewt.h"
+#include "hal/hal_uart.h"
+#include "hal/hal_gpio.h"
+#include "hal/hal_system.h"
+#include "mcu/cmsis_nvic.h"
+#include "bsp/bsp.h"
+
+#include "mcu/frdm-k8xf_hal.h"
+#include "syscfg/syscfg.h"
+#include "mcu/kinetis_common.h"
+
+#include "fsl_clock.h"
+#include "fsl_port.h"
+#include "fsl_lpuart.h"
+
+#include "hal_lpuart_nxp.h"
+
+/*! @brief Ring buffer size (Unit: Byte). */
+#define TX_BUF_SZ  32
+#define RX_BUF_SZ  128
+
+struct uart_ring {
+    uint16_t ur_head;
+    uint16_t ur_tail;
+    uint16_t ur_size;
+    uint8_t _pad;
+    uint8_t *ur_buf;
+};
+
+struct hal_uart {
+    LPUART_Type      *u_base;
+    clock_name_t     clk_src;
+    uint32_t         u_irq;
+    PORT_Type       *p_base;
+    clock_ip_name_t  p_clock;
+    int  u_pin_rx;
+    int  u_pin_tx;
+    /* TODO: support flow control pins */
+    hal_uart_rx_char u_rx_func;
+    hal_uart_tx_char u_tx_func;
+    hal_uart_tx_done u_tx_done;
+    void *u_func_arg;
+    uint8_t u_configured:1;
+    uint8_t u_open:1;
+    uint8_t u_tx_started:1;
+    uint8_t u_rx_stall:1;
+    struct uart_ring ur_tx;
+    uint8_t tx_buffer[TX_BUF_SZ];
+    struct uart_ring ur_rx;
+    uint8_t rx_buffer[RX_BUF_SZ];
+};
+
+/* UART configurations */
+static struct hal_uart uarts[FSL_FEATURE_SOC_LPUART_COUNT];
+
+static uint8_t const s_uartExists[] = NXP_UART_EXISTS;
+static uint8_t const s_uartEnabled[] = NXP_UART_ENABLED;
+static LPUART_Type *const s_uartBases[] = LPUART_BASE_PTRS;
+static clock_name_t s_uartClocks[] = NXP_UART_CLOCKS;
+static uint8_t const s_uartIRQ[] = LPUART_RX_TX_IRQS;
+static PORT_Type *const s_uartPort[] = NXP_UART_PORTS;
+static clock_ip_name_t const s_uartPortClocks[] = NXP_UART_PORT_CLOCKS;
+static uint8_t const s_uartPIN_RX[] = NXP_UART_PIN_RX;
+static uint8_t const s_uartPIN_TX[] = NXP_UART_PIN_TX;
+
+static void uart_irq0(void);
+static void uart_irq1(void);
+static void uart_irq2(void);
+static void uart_irq3(void);
+static void uart_irq4(void);
+static void (*s_uartirqs[])(void) = {
+    uart_irq0, uart_irq1, uart_irq2, uart_irq3, uart_irq4
+};
+
+/*
+ * RING BUFFER FUNCTIONS
+ */
+
+static uint8_t ur_is_empty(struct uart_ring *ur)
+{
+    return (ur->ur_head == ur->ur_tail);
+}
+
+static uint8_t ur_is_full(struct uart_ring *ur)
+{
+    return (((ur->ur_tail + 1) % ur->ur_size) == ur->ur_head);
+}
+
+static void ur_bump(struct uart_ring *ur)
+{
+    if (!ur_is_empty(ur)) {
+        ur->ur_head++;
+        ur->ur_head %= ur->ur_size;
+        return;
+    }
+}
+
+static uint8_t ur_read(struct uart_ring *ur)
+{
+    return ur->ur_buf[ur->ur_head];
+}
+
+static int ur_queue(struct uart_ring *ur, uint8_t data)
+{
+    if (!ur_is_full(ur)) {
+        ur->ur_buf[ur->ur_tail] = data;
+        ur->ur_tail++;
+        ur->ur_tail %= ur->ur_size;
+        return 0;
+    }
+    return -1;
+}
+
+/*
+ * END RING BUFFER FUNCTIONS
+ */
+
+int hal_uart_init_cbs(int port,
+                      hal_uart_tx_char tx_func,
+                      hal_uart_tx_done tx_done,
+                      hal_uart_rx_char rx_func,
+                      void *arg)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    u->u_rx_func = rx_func;
+    u->u_tx_func = tx_func;
+    u->u_tx_done = tx_done;
+    u->u_func_arg = arg;
+
+    return 0;
+}
+
+void hal_uart_blocking_tx(int port, uint8_t byte)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    LPUART_WriteBlocking(u->u_base, &byte, 1);
+}
+
+static int
+hal_uart_tx_fill_buf(struct hal_uart *u)
+{
+    int data = 0;
+    int i = 0;
+    os_sr_t sr;
+
+    OS_ENTER_CRITICAL(sr);
+    while (!ur_is_full(&u->ur_tx)) {
+        if (u->u_tx_func) {
+            data = u->u_tx_func(u->u_func_arg);
+        }
+        if (data <= 0) {
+            break;
+        }
+        i++;
+        ur_queue(&u->ur_tx, data);
+    }
+    OS_EXIT_CRITICAL(sr);
+    return i;
+}
+
+void hal_uart_start_tx(int port)
+{
+    struct hal_uart *u;
+    int data = -1;
+    int rc;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    /* main loop */
+    while (true)
+    {
+        /* add data to TX ring buffer */
+        if (u->u_tx_started == 0) {
+            rc = hal_uart_tx_fill_buf(u);
+            if (rc > 0) {
+                u->u_tx_started = 1;
+            }
+        }
+
+        /* Send data only when UART TX register is empty and TX ring buffer has data to send out. */
+        while (!ur_is_empty(&u->ur_tx) &&
+               (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base))) {
+            data = ur_read(&u->ur_tx);
+            LPUART_WriteByte(u->u_base, data);
+            ur_bump(&u->ur_tx);
+        }
+
+        if (ur_is_empty(&u->ur_tx)) {
+            if (u->u_tx_done) {
+                u->u_tx_done(u->u_func_arg);
+            }
+            u->u_tx_started = 0;
+            break;
+        }
+    }
+}
+
+void
+hal_uart_start_rx(int port)
+{
+    struct hal_uart *u;
+    os_sr_t sr;
+    int rc = 0;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    u->u_rx_stall = 0;
+
+    /* Send back what's in the RX ring buffer until it's empty or we get an
+     * error */
+    while ((rc >= 0) && !ur_is_empty(&u->ur_rx)) {
+        OS_ENTER_CRITICAL(sr);
+        rc = u->u_rx_func(u->u_func_arg, ur_read(&u->ur_rx));
+        if (rc >= 0) {
+            ur_bump(&u->ur_rx);
+        } else {
+            u->u_rx_stall = 1;
+        }
+        OS_EXIT_CRITICAL(sr);
+    }
+}
+
+static void
+uart_irq_handler(int port)
+{
+    struct hal_uart *u;
+    uint32_t status;
+    uint8_t data;
+
+    u = &uarts[port];
+    if (u->u_configured && u->u_open) {
+        status = LPUART_GetStatusFlags(u->u_base);
+        /* Check for RX data */
+        if (status & (kLPUART_RxDataRegFullFlag | kLPUART_RxOverrunFlag)) {
+            data = LPUART_ReadByte(u->u_base);
+            if (u->u_rx_stall || u->u_rx_func(u->u_func_arg, data) < 0) {
+                /*
+                 * RX queue full.
+                 */
+                u->u_rx_stall = 1;
+                ur_queue(&u->ur_rx, data);
+            }
+        }
+        /* Check for TX complete */
+        if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base)) {
+            if (u->u_tx_started) {
+                u->u_tx_started = 0;
+                if (u->u_tx_done)
+                    u->u_tx_done(u->u_func_arg);
+            }
+        }
+    }
+}
+
+static void
+uart_irq0(void)
+{
+    uart_irq_handler(0);
+}
+
+static void
+uart_irq1(void)
+{
+    uart_irq_handler(1);
+}
+
+static void
+uart_irq2(void)
+{
+    uart_irq_handler(2);
+}
+
+static void
+uart_irq3(void)
+{
+    uart_irq_handler(3);
+}
+
+static void
+uart_irq4(void)
+{
+    uart_irq_handler(4);
+}
+
+int
+hal_uart_config(int port,
+                int32_t speed,
+                uint8_t databits,
+                uint8_t stopbits,
+                enum hal_uart_parity parity,
+                enum hal_uart_flow_ctl flow_ctl)
+{
+    struct hal_uart *u;
+    lpuart_config_t uconfig;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || u->u_open) {
+        return -1;
+    }
+
+    /* PIN config (all UARTs use kPORT_MuxAlt3) */
+    CLOCK_EnableClock(u->p_clock);
+    PORT_SetPinMux(u->p_base, u->u_pin_rx, kPORT_MuxAlt3);
+    PORT_SetPinMux(u->p_base, u->u_pin_tx, kPORT_MuxAlt3);
+
+    /* UART CONFIG */
+    CLOCK_SetLpuartClock(2U);
+
+    LPUART_GetDefaultConfig(&uconfig);
+    uconfig.baudRate_Bps = speed;
+
+    /* TODO: only handles 8 databits currently */
+    switch (stopbits) {
+    case 1:
+        uconfig.stopBitCount = kLPUART_OneStopBit;
+        break;
+    case 2:
+        uconfig.stopBitCount = kLPUART_TwoStopBit;
+        break;
+    default:
+        return -1;
+    }
+
+    switch (parity) {
+    case HAL_UART_PARITY_NONE:
+        uconfig.parityMode = kLPUART_ParityDisabled;
+        break;
+    case HAL_UART_PARITY_ODD:
+        uconfig.parityMode = kLPUART_ParityOdd;
+        break;
+    case HAL_UART_PARITY_EVEN:
+        uconfig.parityMode = kLPUART_ParityEven;
+        break;
+    }
+
+    /* TODO: HW flow control not supported */
+    assert(flow_ctl == HAL_UART_FLOW_CTL_NONE);

Review comment:
       Maybe `return -1`?

##########
File path: hw/mcu/nxp/kinetis/src/hal_flash.c
##########
@@ -0,0 +1,178 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+*
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * Internal flash for MK82F25615.

Review comment:
       Not just `MK82F25615` but the `Kinetis family`

##########
File path: hw/mcu/nxp/kinetis/src/hal_watchdog.c
##########
@@ -25,7 +25,7 @@
 #include "fsl_wdog.h"
 #include "fsl_rcm.h"
 
-/* #define WATCHDOG_STUB */
+//#define WATCHDOG_STUB

Review comment:
       You can just remove this line.

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
+
+    /* Clear Tx FIFO */
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    /* Write enable */
+    cmd_write_enable();
+
+    /* Write data into TX FIFO, needs to write at least 16 bytes of data */
+    QSPI_WriteBlocking(QuadSPI0, val, 16U);
+
+    /* Set seq id, write register */
+    QSPI_ExecuteIPCommand(QuadSPI0, 20);
+
+    /* Wait until finished */
+    check_if_finished();
+}
+
+static int
+nxp_qspi_init(const struct hal_flash *dev)
+{
+    qspi_config_t qspi_cfg = {0};
+
+    /*Get QSPI default settings and configure the qspi */
+    QSPI_GetDefaultQspiConfig(&qspi_cfg);
+
+    /*Set AHB buffer size for reading data through AHB bus */
+/* #if MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) <= FSL_FEATURE_QSPI_AHB_BUFFER_SIZE */
+    qspi_cfg.AHBbufferSize[3] = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+/* #else */
+/*     qspi_cfg.AHBbufferSize[3] = FSL_FEATURE_QSPI_AHB_BUFFER_SIZE; */
+/* #endif */
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SCKA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SSA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA0), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA1), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA2), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIO3A), MYNEWT_VAL(QSPIA_MUX));
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SCKB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SSB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB0), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB1), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB2), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOBA), MYNEWT_VAL(QSPIB_MUX));
+
+    //Configure the baudrate too.

Review comment:
       A `TODO`?

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */

Review comment:
       Should all those commented out lines be removed?

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }

Review comment:
       Can be all on the same line?

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,623 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type *dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void *txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);

Review comment:
       Can also `return EINVAL`

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,623 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type *dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void *txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave *) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }

Review comment:
       Since `nxp_spi_master` and `nxp_spi_slave` contain the `nxp_hal_spi` as the first element you could probably just do `master` specific configuration inside the `if` and move the generic after the `if` block:
   
   ```
   spi->config.ctarConfig.bitsPerFrame =
       (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
   spi->config.ctarConfig.cpol = cpol;
   spi->config.ctarConfig.cpha = cpha;
   ```
   
   And get rid of the `slave` variable. Not entirely sure, disregard if you think it won't work.

##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,408 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type *dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *userData)

Review comment:
       Naming convention: should be `user_data`

##########
File path: hw/mcu/nxp/kinetis/src/hal_lpuart.c
##########
@@ -0,0 +1,478 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+
+#include "os/mynewt.h"
+#include "hal/hal_uart.h"
+#include "hal/hal_gpio.h"
+#include "hal/hal_system.h"
+#include "mcu/cmsis_nvic.h"
+#include "bsp/bsp.h"
+#include "syscfg/syscfg.h"
+#include "mcu/kinetis_common.h"
+
+#include "fsl_clock.h"
+#include "fsl_port.h"
+#include "fsl_lpuart.h"
+
+#include "hal_lpuart_nxp.h"
+
+/*! @brief Ring buffer size (Unit: Byte). */
+#define TX_BUF_SZ  32
+#define RX_BUF_SZ  128
+
+struct uart_ring {
+    uint16_t ur_head;
+    uint16_t ur_tail;
+    uint16_t ur_size;
+    uint8_t _pad;
+    uint8_t *ur_buf;
+};
+
+struct hal_uart {
+    LPUART_Type *u_base;
+    clock_name_t clk_src;
+    uint32_t u_irq;
+    PORT_Type *p_base;
+    clock_ip_name_t p_clock;
+    int u_pin_rx;
+    int u_pin_tx;
+    hal_uart_rx_char u_rx_func;
+    hal_uart_tx_char u_tx_func;
+    hal_uart_tx_done u_tx_done;
+    void *u_func_arg;
+    uint8_t u_configured : 1;
+    uint8_t u_open : 1;
+    uint8_t u_tx_started : 1;
+    uint8_t u_rx_stall : 1;
+    struct uart_ring ur_tx;
+    uint8_t tx_buffer[TX_BUF_SZ];
+    struct uart_ring ur_rx;
+    uint8_t rx_buffer[RX_BUF_SZ];
+};
+
+/* UART configurations */
+static struct hal_uart uarts[FSL_FEATURE_SOC_LPUART_COUNT];
+
+static uint8_t const s_uartExists[] = NXP_UART_EXISTS;
+static uint8_t const s_uartEnabled[] = NXP_UART_ENABLED;
+static LPUART_Type *const s_uartBases[] = LPUART_BASE_PTRS;
+static clock_name_t s_uartClocks[] = NXP_UART_CLOCKS;
+static uint8_t const s_uartIRQ[] = LPUART_RX_TX_IRQS;
+static PORT_Type *const s_uartPort[] = NXP_UART_PORTS;
+static clock_ip_name_t const s_uartPortClocks[] = NXP_UART_PORT_CLOCKS;
+static uint8_t const s_uartPIN_RX[] = NXP_UART_PIN_RX;
+static uint8_t const s_uartPIN_TX[] = NXP_UART_PIN_TX;
+
+static void uart_irq0(void);
+static void uart_irq1(void);
+static void uart_irq2(void);
+static void uart_irq3(void);
+static void uart_irq4(void);
+static void (*s_uartirqs[])(void) = {
+    uart_irq0, uart_irq1, uart_irq2, uart_irq3, uart_irq4
+};
+
+/*
+ * RING BUFFER FUNCTIONS
+ */
+
+static uint8_t
+ur_is_empty(struct uart_ring *ur)
+{
+    return (ur->ur_head == ur->ur_tail);
+}
+
+static uint8_t
+ur_is_full(struct uart_ring *ur)
+{
+    return (((ur->ur_tail + 1) % ur->ur_size) == ur->ur_head);
+}
+
+static void
+ur_bump(struct uart_ring *ur)
+{
+    if (!ur_is_empty(ur)) {
+        ur->ur_head++;
+        ur->ur_head %= ur->ur_size;
+        return;
+    }
+}
+
+static uint8_t
+ur_read(struct uart_ring *ur)
+{
+    return ur->ur_buf[ur->ur_head];
+}
+
+static int
+ur_queue(struct uart_ring *ur, uint8_t data)
+{
+    if (!ur_is_full(ur)) {
+        ur->ur_buf[ur->ur_tail] = data;
+        ur->ur_tail++;
+        ur->ur_tail %= ur->ur_size;
+        return 0;
+    }
+    return -1;
+}
+
+/*
+ * END RING BUFFER FUNCTIONS
+ */
+
+int
+hal_uart_init_cbs(int port,
+                  hal_uart_tx_char tx_func,
+                  hal_uart_tx_done tx_done,
+                  hal_uart_rx_char rx_func,
+                  void *arg)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    u->u_rx_func = rx_func;
+    u->u_tx_func = tx_func;
+    u->u_tx_done = tx_done;
+    u->u_func_arg = arg;
+
+    return 0;
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t byte)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    LPUART_WriteBlocking(u->u_base, &byte, 1);
+}
+
+static int
+hal_uart_tx_fill_buf(struct hal_uart *u)
+{
+    int data = 0;
+    int i = 0;
+    os_sr_t sr;
+
+    OS_ENTER_CRITICAL(sr);
+    while (!ur_is_full(&u->ur_tx)) {
+        if (u->u_tx_func) {
+            data = u->u_tx_func(u->u_func_arg);
+        }
+        if (data <= 0) {
+            break;
+        }
+        i++;
+        ur_queue(&u->ur_tx, data);
+    }
+    OS_EXIT_CRITICAL(sr);
+    return i;
+}
+
+void
+hal_uart_start_tx(int port)
+{
+    struct hal_uart *u;
+    int data = -1;
+    int rc;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    /* main loop */
+    while (true) {
+        /* add data to TX ring buffer */
+        if (u->u_tx_started == 0) {
+            rc = hal_uart_tx_fill_buf(u);
+            if (rc > 0) {
+                u->u_tx_started = 1;
+            }
+        }
+
+        /* Send data only when UART TX register is empty and TX ring buffer has data to send out. */
+        while (!ur_is_empty(&u->ur_tx) &&
+               (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base))) {
+            data = ur_read(&u->ur_tx);
+            LPUART_WriteByte(u->u_base, data);
+            ur_bump(&u->ur_tx);
+        }
+
+        if (ur_is_empty(&u->ur_tx)) {
+            if (u->u_tx_done) {
+                u->u_tx_done(u->u_func_arg);
+            }
+            u->u_tx_started = 0;
+            break;
+        }
+    }
+}
+
+void
+hal_uart_start_rx(int port)
+{
+    struct hal_uart *u;
+    os_sr_t sr;
+    int rc = 0;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    u->u_rx_stall = 0;
+
+    /* Send back what's in the RX ring buffer until it's empty or we get an
+     * error */
+    while ((rc >= 0) && !ur_is_empty(&u->ur_rx)) {
+        OS_ENTER_CRITICAL(sr);
+        rc = u->u_rx_func(u->u_func_arg, ur_read(&u->ur_rx));
+        if (rc >= 0) {
+            ur_bump(&u->ur_rx);
+        } else {
+            u->u_rx_stall = 1;
+        }
+        OS_EXIT_CRITICAL(sr);
+    }
+}
+
+static void
+uart_irq_handler(int port)
+{
+    struct hal_uart *u;
+    uint32_t status;
+    uint8_t data;
+
+    u = &uarts[port];
+    if (u->u_configured && u->u_open) {
+        status = LPUART_GetStatusFlags(u->u_base);
+        /* Check for RX data */
+        if (status & (kLPUART_RxDataRegFullFlag | kLPUART_RxOverrunFlag)) {
+            data = LPUART_ReadByte(u->u_base);
+            if (u->u_rx_stall || u->u_rx_func(u->u_func_arg, data) < 0) {
+                /*
+                 * RX queue full.
+                 */
+                u->u_rx_stall = 1;
+                ur_queue(&u->ur_rx, data);
+            }
+        }
+        /* Check for TX complete */
+        if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base)) {
+            if (u->u_tx_started) {
+                u->u_tx_started = 0;
+                if (u->u_tx_done) {
+                    u->u_tx_done(u->u_func_arg);
+                }
+            }
+        }
+    }
+}
+
+static void
+uart_irq0(void)
+{
+    uart_irq_handler(0);
+}
+
+static void
+uart_irq1(void)
+{
+    uart_irq_handler(1);
+}
+
+static void
+uart_irq2(void)
+{
+    uart_irq_handler(2);
+}
+
+static void
+uart_irq3(void)
+{
+    uart_irq_handler(3);
+}
+
+static void
+uart_irq4(void)
+{
+    uart_irq_handler(4);
+}
+
+int
+hal_uart_config(int port,
+                int32_t speed,
+                uint8_t databits,
+                uint8_t stopbits,
+                enum hal_uart_parity parity,
+                enum hal_uart_flow_ctl flow_ctl)
+{
+    struct hal_uart *u;
+    lpuart_config_t uconfig;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || u->u_open) {
+        return -1;
+    }
+
+    /* PIN config (all UARTs use kPORT_MuxAlt3) */
+    CLOCK_EnableClock(u->p_clock);
+    PORT_SetPinMux(u->p_base, u->u_pin_rx, kPORT_MuxAlt3);
+    PORT_SetPinMux(u->p_base, u->u_pin_tx, kPORT_MuxAlt3);
+
+    /* UART CONFIG */
+    CLOCK_SetLpuartClock(2U);
+
+    LPUART_GetDefaultConfig(&uconfig);
+    uconfig.baudRate_Bps = speed;
+
+    switch (databits) {
+    case 8:
+        uconfig.dataBitsCount = kLPUART_EightDataBits;
+        break;
+    case 7:
+#if FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        uconfig.dataBitsCount = kLPUART_SevenDataBits;
+        break;
+#endif /* Fallthrought */
+    default:
+        uconfig.parityMode = kLPUART_ParityEven;
+        return -1;

Review comment:
       No reason to set `partityMode` if you're going to leave early right?

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,623 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type *dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void *txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave *) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }
+    return 0;
+}
+
+int
+hal_spi_enable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (spi->enabled) {
+        return 0;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        DSPI_MasterInit(spi->dev,
+                        &master->config,
+                        CLOCK_GetFreq(kCLOCK_BusClk));
+    } else {
+        slave = (struct nxp_spi_slave *) spi;
+        DSPI_SlaveInit(spi->dev, &slave->config);
+    }
+
+    spi->enabled = true;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_SetVector(spi->irqn, (uint32_t) spi->irq_handler);
+    NVIC_EnableIRQ(spi->irqn);
+    return 0;
+}
+
+int
+hal_spi_disable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (!spi->enabled) {
+        return 0;
+    }
+
+    DSPI_Deinit(spi->dev);
+
+    spi->enabled = false;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_DisableIRQ(spi->irqn);
+    return 0;
+}
+
+uint16_t
+hal_spi_tx_val(int spi_num, uint16_t val)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    uint16_t retval = 0;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t *) &val;
+        xfer.rxData = (uint8_t *) &retval;
+        xfer.dataSize = 1;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return retval;
+    }
+    return 0xFFFF; /* Invalid API. */
+}
+
+int
+hal_spi_txrx(int spi_num, void *txbuf, void *rxbuf, int len)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    status_t rc;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t *) txbuf;
+        xfer.rxData = (uint8_t *) rxbuf;
+        xfer.dataSize = len;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        rc = DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return (rc == kStatus_Success) ? 0 : rc;

Review comment:
       If you initialize `rc` to `-1` you can move this `return` after the `if` block.

##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,408 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type *dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *user_data)
+{
+    struct nxp_hal_i2c *i2c = userData;

Review comment:
       I belive you also have to fix this one! :-)

##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,408 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type *dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *user_data)
+{
+    struct nxp_hal_i2c *i2c = userData;

Review comment:
       I believe you also have to fix this one! :-)




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[GitHub] [mynewt-core] mlaz commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
mlaz commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570522918



##########
File path: hw/mcu/nxp/kinetis/src/hal_flash.c
##########
@@ -0,0 +1,178 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+*
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * Internal flash for MK82F25615.

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_hw_id.c
##########
@@ -22,26 +22,27 @@
 
 #include <hal/hal_bsp.h>
 
-#include "MK64F12.h"
+#include "fsl_sim.h"
 
 #ifndef min
 #define min(a, b) ((a)<(b)?(a):(b))
 #endif
 
-#define MK64F12_HW_ID_LEN     7
+#define MK8xF_HW_ID_LEN sizeof(sim_uid_t)

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_watchdog.c
##########
@@ -25,7 +25,7 @@
 #include "fsl_wdog.h"
 #include "fsl_rcm.h"
 
-/* #define WATCHDOG_STUB */
+//#define WATCHDOG_STUB

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,412 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type* dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port; 
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *userData)
+{
+    struct nxp_hal_i2c *i2c = userData;
+    i2c->stat = status;
+    os_sem_release(&i2c->sync);
+}
+
+static struct nxp_hal_i2c*
+hal_i2c_resolve(uint8_t i2c_num)
+{
+    if (i2c_num >= NXP_HAL_I2C_MAX) {
+        return NULL;
+    }
+
+    return i2c_modules[i2c_num];
+}
+
+static void
+i2c_init_hw(struct nxp_hal_i2c *i2c, int pin_scl, int pin_sda)
+{
+    uint32_t clock_freq;
+    i2c_master_config_t master_cfg;
+
+    const port_pin_config_t pincfg = {
+        kPORT_PullUp,
+        kPORT_FastSlewRate,
+        kPORT_PassiveFilterDisable,
+        kPORT_OpenDrainEnable,
+        kPORT_LowDriveStrength,
+        i2c->mux,
+        kPORT_UnlockRegister
+    };
+    PORT_SetPinConfig(i2c->port, i2c->scl_pin, &pincfg);
+    PORT_SetPinConfig(i2c->port, i2c->sda_pin, &pincfg);
+
+    clock_freq = CLOCK_GetFreq(kCLOCK_BusClk);
+    I2C_MasterGetDefaultConfig(&master_cfg);
+    I2C_MasterInit(i2c->dev, &master_cfg, clock_freq);
+
+    I2C_MasterTransferCreateHandle(i2c->dev, &i2c->handle, master_xfer_cb, i2c);
+    NVIC_ClearPendingIRQ(i2c->irqn);
+    NVIC_SetVector(i2c->irqn, (uint32_t) i2c->irq_handler);
+    NVIC_EnableIRQ(i2c->irqn);
+}
+
+static int
+i2c_config(struct nxp_hal_i2c *i2c, uint32_t frequency)
+{
+    uint32_t clock_freq;
+    uint32_t baudrate;
+
+    switch (frequency) {
+    case 100:
+        baudrate = 100000U;
+        break;
+    case 400:
+        baudrate = 400000U;
+        break;
+    case 1000:
+        baudrate = 1000000U;
+        break;
+    default:

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,624 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type* dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void* txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave*) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }
+    return 0;
+}
+
+int
+hal_spi_enable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (spi->enabled) {
+        return 0;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+    master = (struct nxp_spi_master*) spi;
+    DSPI_MasterInit(spi->dev,
+                    &master->config,
+                    CLOCK_GetFreq(kCLOCK_BusClk));
+    } else {
+    slave = (struct nxp_spi_slave*) spi;
+    DSPI_SlaveInit(spi->dev, &slave->config);
+    }

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
+
+    /* Clear Tx FIFO */
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    /* Write enable */
+    cmd_write_enable();
+
+    /* Write data into TX FIFO, needs to write at least 16 bytes of data */
+    QSPI_WriteBlocking(QuadSPI0, val, 16U);
+
+    /* Set seq id, write register */
+    QSPI_ExecuteIPCommand(QuadSPI0, 20);
+
+    /* Wait until finished */
+    check_if_finished();
+}
+
+static int
+nxp_qspi_init(const struct hal_flash *dev)
+{
+    qspi_config_t qspi_cfg = {0};
+
+    /*Get QSPI default settings and configure the qspi */
+    QSPI_GetDefaultQspiConfig(&qspi_cfg);
+
+    /*Set AHB buffer size for reading data through AHB bus */
+/* #if MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) <= FSL_FEATURE_QSPI_AHB_BUFFER_SIZE */
+    qspi_cfg.AHBbufferSize[3] = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+/* #else */
+/*     qspi_cfg.AHBbufferSize[3] = FSL_FEATURE_QSPI_AHB_BUFFER_SIZE; */
+/* #endif */

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,624 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type* dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void* txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave*) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave*) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }
+    return 0;
+}
+
+int
+hal_spi_enable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (spi->enabled) {
+        return 0;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+    master = (struct nxp_spi_master*) spi;
+    DSPI_MasterInit(spi->dev,
+                    &master->config,
+                    CLOCK_GetFreq(kCLOCK_BusClk));
+    } else {
+    slave = (struct nxp_spi_slave*) spi;
+    DSPI_SlaveInit(spi->dev, &slave->config);
+    }
+
+    spi->enabled = true;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_SetVector(spi->irqn, (uint32_t) spi->irq_handler);
+    NVIC_EnableIRQ(spi->irqn);
+    return 0;
+}
+
+int
+hal_spi_disable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (!spi->enabled) {
+        return 0;
+    }
+
+    DSPI_Deinit(spi->dev);
+
+    spi->enabled = false;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_DisableIRQ(spi->irqn);
+    return 0;
+}
+
+uint16_t
+hal_spi_tx_val(int spi_num, uint16_t val)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    uint16_t retval = 0;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t*) &val;
+        xfer.rxData = (uint8_t*) &retval;
+        xfer.dataSize = 1;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return retval;
+    }
+    return 0xFFFF; /* Invalid API. */
+}
+
+int
+hal_spi_txrx(int spi_num, void *txbuf, void *rxbuf, int len)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    status_t rc;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t*) txbuf;
+        xfer.rxData = (uint8_t*) rxbuf;
+        xfer.dataSize = len;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        rc = DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return (rc == kStatus_Success) ? 0 : rc;
+    }
+    return -1;
+}
+
+int
+hal_spi_set_txrx_cb(int spi_num, hal_spi_txrx_cb txrx_cb, void *arg)
+{
+    struct nxp_hal_spi *spi;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    spi->txrx_cb = txrx_cb;
+    spi->txrx_cb_arg = arg;
+    return 0;
+}
+
+int
+hal_spi_txrx_noblock(int spi_num, void *txbuf, void *rxbuf, int len)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_transfer_t xfer;
+    status_t rc;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master*) spi;
+        //master->handle

Review comment:
       Done




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[GitHub] [mynewt-core] mlaz commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
mlaz commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570523381



##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
+
+    /* Clear Tx FIFO */
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    /* Write enable */
+    cmd_write_enable();
+
+    /* Write data into TX FIFO, needs to write at least 16 bytes of data */
+    QSPI_WriteBlocking(QuadSPI0, val, 16U);
+
+    /* Set seq id, write register */
+    QSPI_ExecuteIPCommand(QuadSPI0, 20);
+
+    /* Wait until finished */
+    check_if_finished();
+}
+
+static int
+nxp_qspi_init(const struct hal_flash *dev)
+{
+    qspi_config_t qspi_cfg = {0};
+
+    /*Get QSPI default settings and configure the qspi */
+    QSPI_GetDefaultQspiConfig(&qspi_cfg);
+
+    /*Set AHB buffer size for reading data through AHB bus */
+/* #if MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) <= FSL_FEATURE_QSPI_AHB_BUFFER_SIZE */
+    qspi_cfg.AHBbufferSize[3] = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+/* #else */
+/*     qspi_cfg.AHBbufferSize[3] = FSL_FEATURE_QSPI_AHB_BUFFER_SIZE; */
+/* #endif */
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SCKA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SSA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA0), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA1), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA2), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIO3A), MYNEWT_VAL(QSPIA_MUX));
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SCKB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SSB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB0), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB1), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB2), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOBA), MYNEWT_VAL(QSPIB_MUX));
+
+    //Configure the baudrate too.
+
+    QSPI_Init(QuadSPI0, &qspi_cfg, CLOCK_GetFreq(kCLOCK_McgPll0Clk));
+
+    memcpy(g_qspi_flash_cfg.lookuptable, lut, sizeof(lut));
+    /*According to serial flash feature to configure flash settings */
+    QSPI_SetFlashConfig(QuadSPI0, &g_qspi_flash_cfg);
+
+#if FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC
+    QSPI_ClearCache(QuadSPI0);
+#endif
+
+    enable_quad_mode();
+    return 0;
+}
+
+static const struct hal_flash_funcs nxp_qspi_funcs = {
+        .hff_read = nxp_qspi_read,
+        .hff_write = nxp_qspi_write,
+        .hff_erase_sector = nxp_qspi_erase_sector,
+        .hff_sector_info = nxp_qspi_sector_info,
+        .hff_init = nxp_qspi_init,
+        .hff_erase = nxp_qspi_erase
+    };
+
+const struct hal_flash nxp_qspi_dev = {
+        .hf_itf = &nxp_qspi_funcs,
+        .hf_base_addr = FSL_FEATURE_QSPI_AMBA_BASE,
+        .hf_size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE),
+        .hf_sector_cnt = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT),
+        .hf_align = 8,
+        .hf_erased_val = 0xff,
+    };

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
+
+    /* Clear Tx FIFO */
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    /* Write enable */
+    cmd_write_enable();
+
+    /* Write data into TX FIFO, needs to write at least 16 bytes of data */
+    QSPI_WriteBlocking(QuadSPI0, val, 16U);
+
+    /* Set seq id, write register */
+    QSPI_ExecuteIPCommand(QuadSPI0, 20);
+
+    /* Wait until finished */
+    check_if_finished();
+}
+
+static int
+nxp_qspi_init(const struct hal_flash *dev)
+{
+    qspi_config_t qspi_cfg = {0};
+
+    /*Get QSPI default settings and configure the qspi */
+    QSPI_GetDefaultQspiConfig(&qspi_cfg);
+
+    /*Set AHB buffer size for reading data through AHB bus */
+/* #if MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) <= FSL_FEATURE_QSPI_AHB_BUFFER_SIZE */
+    qspi_cfg.AHBbufferSize[3] = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+/* #else */
+/*     qspi_cfg.AHBbufferSize[3] = FSL_FEATURE_QSPI_AHB_BUFFER_SIZE; */
+/* #endif */
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SCKA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_SSA), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA0), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA1), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIOA2), MYNEWT_VAL(QSPIA_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIA_PORT), MYNEWT_VAL(QSPI_PIN_DIO3A), MYNEWT_VAL(QSPIA_MUX));
+
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SCKB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_SSB), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB0), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB1), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOB2), MYNEWT_VAL(QSPIB_MUX));
+    PORT_SetPinMux(MYNEWT_VAL(QSPIB_PORT), MYNEWT_VAL(QSPI_PIN_DIOBA), MYNEWT_VAL(QSPIB_MUX));
+
+    //Configure the baudrate too.

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+    /* Seq0 :Quad Read */
+    /* CMD:        0xEB - Quad Read, Single pad */
+    /* ADDR:       0x18 - 24bit address, Quad pads */
+    /* DUMMY:      0x06 - 6 clock cyles, Quad pads */
+    /* READ:       0x80 - Read 128 bytes, Quad pads */
+    /* JUMP_ON_CS: 0 */
+    [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+    [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+    [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+    /* Seq1: Write Enable */
+    /* CMD:      0x06 - Write Enable, Single pad */
+    [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+    /* Seq2: Erase All */
+    /* CMD:    0x60 - Erase All chip, Single pad */
+    [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+    /* Seq3: Read Status */
+    /* CMD:    0x05 - Read Status, single pad */
+    /* READ:   0x01 - Read 1 byte */
+    [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq4: Page Program */
+    /* CMD:    0x02 - Page Program, Single pad */
+    /* ADDR:   0x18 - 24bit address, Single pad */
+    /* WRITE:  0x80 - Write 128 bytes at one pass, Single pad */
+    [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+    [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+    /* Seq5: Write Register */
+    /* CMD:    0x01 - Write Status Register, single pad */
+    /* WRITE:  0x01 - Write 1 byte of data, single pad */
+    [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+    /* Seq6: Read Config Register */
+    /* CMD:  0x15 - Read Config register, single pad */
+    /* READ: 0x01 - Read 1 byte */
+    [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+    /* Seq7: Erase Sector */
+    /* CMD:  0x20 - Sector Erase, single pad */
+    /* ADDR: 0x18 - 24 bit address, single pad */
+    [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+    /* Match MISRA rule */
+    [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+    .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+    .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+    .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+    .dataHoldTime = 0,
+#endif
+    .CSHoldTime = 0,
+    .CSSetupTime = 0,
+    .cloumnspace = 0,
+    .dataLearnValue = 0,
+    .endian = kQSPI_64LittleEndian,
+    .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+    uint32_t val = 0;
+    /* Check WIP bit */
+    do
+    {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+        QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        val = QuadSPI0->RBDR[0];
+        /* Clear ARDB area */
+        QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+    } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+    int i;
+    for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+    {
+        dst[i] = ((uint32_t*)address)[i];
+    }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+              uint32_t address,
+              void *dst,
+              uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        read_page(address,  dst);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+    uint32_t leftLongWords = 0;
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+    QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+    cmd_write_enable();
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+
+    /* First write some data into TXFIFO to prevent from underrun */
+    QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+    src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+    /* Start the program */
+    QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+    QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+    leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+    QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+    /* Wait until flash finished program */
+    check_if_finished();
+    while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+    {
+    }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+               uint32_t address,
+               const void *src,
+               uint32_t num_bytes)
+{
+    uint32_t npages;
+    if ((address % dev->hf_align) != 0) {
+        return OS_EINVAL;
+    }
+    if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+        return OS_EINVAL;
+    }
+
+    npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    while (npages) {
+        write_page(address, (uint32_t*) src);
+        npages--;
+        address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+                         uint32_t sector_address)
+{
+    sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }
+    QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+    QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+    cmd_write_enable();
+    QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+    check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+    QSPI_ClearCache(QuadSPI0);
+#endif
+    return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+               uint32_t address,
+               uint32_t size)
+{
+    uint32_t nsects;
+
+    address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    while (nsects) {
+        while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+        {
+        }
+        QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+        QSPI_SetIPCommandAddress(QuadSPI0, address);
+        cmd_write_enable();
+        QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+        check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) &&  \
+    (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+        QSPI_ClearCache(QuadSPI0);
+#endif
+        nsects--;
+        address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    }
+    return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+                     int idx,
+                     uint32_t *address,
+                     uint32_t *sz)
+{
+    *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+    *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+    return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+    uint32_t val[4] = {0x40U, 0, 0, 0};
+
+    while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+    {
+    }

Review comment:
       Addressed.

##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */

Review comment:
       Addressed.




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[GitHub] [mynewt-core] utzig commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
utzig commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570608431



##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,623 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type *dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void *txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);

Review comment:
       Can also `return EINVAL`

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,623 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type *dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void *txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave *) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }

Review comment:
       Since `nxp_spi_master` and `nxp_spi_slave` contain the `nxp_hal_spi` as the first element you could probably just do `master` specific configuration inside the `if` and move the generic after the `if` block:
   
   ```
   spi->config.ctarConfig.bitsPerFrame =
       (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
   spi->config.ctarConfig.cpol = cpol;
   spi->config.ctarConfig.cpha = cpha;
   ```
   
   And get rid of the `slave` variable. Not entirely sure, disregard if you think it won't work.

##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,408 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+    I2C_Type *dev;
+    uint32_t scl_pin;
+    uint32_t sda_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    i2c_master_handle_t handle;
+    struct os_sem sync;
+    status_t stat;
+    bool enabled;
+    bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+    .dev = I2C0,
+    .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_0_PORT),
+    .mux = MYNEWT_VAL(I2C_0_MUX),
+    .irqn = I2C0_IRQn,
+    .irq_handler = i2c0_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+    .dev = I2C1,
+    .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_1_PORT),
+    .mux = MYNEWT_VAL(I2C_1_MUX),
+    .irqn = I2C1_IRQn,
+    .irq_handler = i2c1_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+    .dev = I2C2,
+    .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_2_PORT),
+    .mux = MYNEWT_VAL(I2C_2_MUX),
+    .irqn = I2C2_IRQn,
+    .irq_handler = i2c2_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+    .dev = I2C3,
+    .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+    .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+    .port = MYNEWT_VAL(I2C_3_PORT),
+    .mux = MYNEWT_VAL(I2C_3_MUX),
+    .irqn = I2C3_IRQn,
+    .irq_handler = i2c3_irq,
+    .stat = 0,
+    .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+    &hal_i2c0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+    &hal_i2c1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+    &hal_i2c2,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+    &hal_i2c3,
+#else
+    NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+    I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+               i2c_master_handle_t *handle,
+               status_t status,
+               void *userData)

Review comment:
       Naming convention: should be `user_data`

##########
File path: hw/mcu/nxp/kinetis/src/hal_lpuart.c
##########
@@ -0,0 +1,478 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+
+#include "os/mynewt.h"
+#include "hal/hal_uart.h"
+#include "hal/hal_gpio.h"
+#include "hal/hal_system.h"
+#include "mcu/cmsis_nvic.h"
+#include "bsp/bsp.h"
+#include "syscfg/syscfg.h"
+#include "mcu/kinetis_common.h"
+
+#include "fsl_clock.h"
+#include "fsl_port.h"
+#include "fsl_lpuart.h"
+
+#include "hal_lpuart_nxp.h"
+
+/*! @brief Ring buffer size (Unit: Byte). */
+#define TX_BUF_SZ  32
+#define RX_BUF_SZ  128
+
+struct uart_ring {
+    uint16_t ur_head;
+    uint16_t ur_tail;
+    uint16_t ur_size;
+    uint8_t _pad;
+    uint8_t *ur_buf;
+};
+
+struct hal_uart {
+    LPUART_Type *u_base;
+    clock_name_t clk_src;
+    uint32_t u_irq;
+    PORT_Type *p_base;
+    clock_ip_name_t p_clock;
+    int u_pin_rx;
+    int u_pin_tx;
+    hal_uart_rx_char u_rx_func;
+    hal_uart_tx_char u_tx_func;
+    hal_uart_tx_done u_tx_done;
+    void *u_func_arg;
+    uint8_t u_configured : 1;
+    uint8_t u_open : 1;
+    uint8_t u_tx_started : 1;
+    uint8_t u_rx_stall : 1;
+    struct uart_ring ur_tx;
+    uint8_t tx_buffer[TX_BUF_SZ];
+    struct uart_ring ur_rx;
+    uint8_t rx_buffer[RX_BUF_SZ];
+};
+
+/* UART configurations */
+static struct hal_uart uarts[FSL_FEATURE_SOC_LPUART_COUNT];
+
+static uint8_t const s_uartExists[] = NXP_UART_EXISTS;
+static uint8_t const s_uartEnabled[] = NXP_UART_ENABLED;
+static LPUART_Type *const s_uartBases[] = LPUART_BASE_PTRS;
+static clock_name_t s_uartClocks[] = NXP_UART_CLOCKS;
+static uint8_t const s_uartIRQ[] = LPUART_RX_TX_IRQS;
+static PORT_Type *const s_uartPort[] = NXP_UART_PORTS;
+static clock_ip_name_t const s_uartPortClocks[] = NXP_UART_PORT_CLOCKS;
+static uint8_t const s_uartPIN_RX[] = NXP_UART_PIN_RX;
+static uint8_t const s_uartPIN_TX[] = NXP_UART_PIN_TX;
+
+static void uart_irq0(void);
+static void uart_irq1(void);
+static void uart_irq2(void);
+static void uart_irq3(void);
+static void uart_irq4(void);
+static void (*s_uartirqs[])(void) = {
+    uart_irq0, uart_irq1, uart_irq2, uart_irq3, uart_irq4
+};
+
+/*
+ * RING BUFFER FUNCTIONS
+ */
+
+static uint8_t
+ur_is_empty(struct uart_ring *ur)
+{
+    return (ur->ur_head == ur->ur_tail);
+}
+
+static uint8_t
+ur_is_full(struct uart_ring *ur)
+{
+    return (((ur->ur_tail + 1) % ur->ur_size) == ur->ur_head);
+}
+
+static void
+ur_bump(struct uart_ring *ur)
+{
+    if (!ur_is_empty(ur)) {
+        ur->ur_head++;
+        ur->ur_head %= ur->ur_size;
+        return;
+    }
+}
+
+static uint8_t
+ur_read(struct uart_ring *ur)
+{
+    return ur->ur_buf[ur->ur_head];
+}
+
+static int
+ur_queue(struct uart_ring *ur, uint8_t data)
+{
+    if (!ur_is_full(ur)) {
+        ur->ur_buf[ur->ur_tail] = data;
+        ur->ur_tail++;
+        ur->ur_tail %= ur->ur_size;
+        return 0;
+    }
+    return -1;
+}
+
+/*
+ * END RING BUFFER FUNCTIONS
+ */
+
+int
+hal_uart_init_cbs(int port,
+                  hal_uart_tx_char tx_func,
+                  hal_uart_tx_done tx_done,
+                  hal_uart_rx_char rx_func,
+                  void *arg)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    u->u_rx_func = rx_func;
+    u->u_tx_func = tx_func;
+    u->u_tx_done = tx_done;
+    u->u_func_arg = arg;
+
+    return 0;
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t byte)
+{
+    struct hal_uart *u;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    LPUART_WriteBlocking(u->u_base, &byte, 1);
+}
+
+static int
+hal_uart_tx_fill_buf(struct hal_uart *u)
+{
+    int data = 0;
+    int i = 0;
+    os_sr_t sr;
+
+    OS_ENTER_CRITICAL(sr);
+    while (!ur_is_full(&u->ur_tx)) {
+        if (u->u_tx_func) {
+            data = u->u_tx_func(u->u_func_arg);
+        }
+        if (data <= 0) {
+            break;
+        }
+        i++;
+        ur_queue(&u->ur_tx, data);
+    }
+    OS_EXIT_CRITICAL(sr);
+    return i;
+}
+
+void
+hal_uart_start_tx(int port)
+{
+    struct hal_uart *u;
+    int data = -1;
+    int rc;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    /* main loop */
+    while (true) {
+        /* add data to TX ring buffer */
+        if (u->u_tx_started == 0) {
+            rc = hal_uart_tx_fill_buf(u);
+            if (rc > 0) {
+                u->u_tx_started = 1;
+            }
+        }
+
+        /* Send data only when UART TX register is empty and TX ring buffer has data to send out. */
+        while (!ur_is_empty(&u->ur_tx) &&
+               (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base))) {
+            data = ur_read(&u->ur_tx);
+            LPUART_WriteByte(u->u_base, data);
+            ur_bump(&u->ur_tx);
+        }
+
+        if (ur_is_empty(&u->ur_tx)) {
+            if (u->u_tx_done) {
+                u->u_tx_done(u->u_func_arg);
+            }
+            u->u_tx_started = 0;
+            break;
+        }
+    }
+}
+
+void
+hal_uart_start_rx(int port)
+{
+    struct hal_uart *u;
+    os_sr_t sr;
+    int rc = 0;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || !u->u_open) {
+        return;
+    }
+
+    u->u_rx_stall = 0;
+
+    /* Send back what's in the RX ring buffer until it's empty or we get an
+     * error */
+    while ((rc >= 0) && !ur_is_empty(&u->ur_rx)) {
+        OS_ENTER_CRITICAL(sr);
+        rc = u->u_rx_func(u->u_func_arg, ur_read(&u->ur_rx));
+        if (rc >= 0) {
+            ur_bump(&u->ur_rx);
+        } else {
+            u->u_rx_stall = 1;
+        }
+        OS_EXIT_CRITICAL(sr);
+    }
+}
+
+static void
+uart_irq_handler(int port)
+{
+    struct hal_uart *u;
+    uint32_t status;
+    uint8_t data;
+
+    u = &uarts[port];
+    if (u->u_configured && u->u_open) {
+        status = LPUART_GetStatusFlags(u->u_base);
+        /* Check for RX data */
+        if (status & (kLPUART_RxDataRegFullFlag | kLPUART_RxOverrunFlag)) {
+            data = LPUART_ReadByte(u->u_base);
+            if (u->u_rx_stall || u->u_rx_func(u->u_func_arg, data) < 0) {
+                /*
+                 * RX queue full.
+                 */
+                u->u_rx_stall = 1;
+                ur_queue(&u->ur_rx, data);
+            }
+        }
+        /* Check for TX complete */
+        if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base)) {
+            if (u->u_tx_started) {
+                u->u_tx_started = 0;
+                if (u->u_tx_done) {
+                    u->u_tx_done(u->u_func_arg);
+                }
+            }
+        }
+    }
+}
+
+static void
+uart_irq0(void)
+{
+    uart_irq_handler(0);
+}
+
+static void
+uart_irq1(void)
+{
+    uart_irq_handler(1);
+}
+
+static void
+uart_irq2(void)
+{
+    uart_irq_handler(2);
+}
+
+static void
+uart_irq3(void)
+{
+    uart_irq_handler(3);
+}
+
+static void
+uart_irq4(void)
+{
+    uart_irq_handler(4);
+}
+
+int
+hal_uart_config(int port,
+                int32_t speed,
+                uint8_t databits,
+                uint8_t stopbits,
+                enum hal_uart_parity parity,
+                enum hal_uart_flow_ctl flow_ctl)
+{
+    struct hal_uart *u;
+    lpuart_config_t uconfig;
+
+    if (port >= FSL_FEATURE_SOC_LPUART_COUNT) {
+        return -1;
+    }
+    u = &uarts[port];
+    if (!u->u_configured || u->u_open) {
+        return -1;
+    }
+
+    /* PIN config (all UARTs use kPORT_MuxAlt3) */
+    CLOCK_EnableClock(u->p_clock);
+    PORT_SetPinMux(u->p_base, u->u_pin_rx, kPORT_MuxAlt3);
+    PORT_SetPinMux(u->p_base, u->u_pin_tx, kPORT_MuxAlt3);
+
+    /* UART CONFIG */
+    CLOCK_SetLpuartClock(2U);
+
+    LPUART_GetDefaultConfig(&uconfig);
+    uconfig.baudRate_Bps = speed;
+
+    switch (databits) {
+    case 8:
+        uconfig.dataBitsCount = kLPUART_EightDataBits;
+        break;
+    case 7:
+#if FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        uconfig.dataBitsCount = kLPUART_SevenDataBits;
+        break;
+#endif /* Fallthrought */
+    default:
+        uconfig.parityMode = kLPUART_ParityEven;
+        return -1;

Review comment:
       No reason to set `partityMode` if you're going to leave early right?

##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,623 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+    TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+    TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+    SPI_Type *dev;
+    uint32_t clk_pin;
+    uint32_t pcs_pin;
+    uint32_t sout_pin;
+    uint32_t sin_pin;
+    PORT_Type *port;
+    port_mux_t mux;
+    IRQn_Type irqn;
+    void (*irq_handler)(void);
+    hal_spi_txrx_cb txrx_cb;
+    void *txrx_cb_arg;
+    bool enabled;
+    enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+    struct nxp_hal_spi hal_spi;
+    dspi_master_config_t config;
+    dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+    struct nxp_hal_spi hal_spi;
+    dspi_slave_config_t config;
+    dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+    .hal_spi = {
+        .dev = SPI0,
+        .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+        .irqn = SPI0_IRQn,
+        .irq_handler = spi0_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+    .hal_spi = {
+        .dev = SPI1,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI1_IRQn,
+        .irq_handler = spi1_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+        .pcs_pin = 0, /* unused */
+        .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+        .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+        .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+        .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_MASTER,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+    .hal_spi = {
+        .dev = SPI2,
+        .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+        .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+        .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+        .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+        .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+        .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+        .irqn = SPI2_IRQn,
+        .irq_handler = spi2_irq,
+        .txrx_cb = NULL,
+        .txrx_cb_arg = NULL,
+        .enabled = false,
+        .type = HAL_SPI_TYPE_SLAVE,
+    },
+    .config = {0},
+    .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi0,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi1,
+#else
+    NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+    (struct nxp_hal_spi *) &hal_spi2
+#else
+    NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+    if (spi_num >= NXP_HAL_SPI_MAX) {
+        return NULL;
+    }
+    return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+    DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+    DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+    struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData;
+
+    if (status == kStatus_Success) {
+        if (spi->txrx_cb) {
+            spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+        }
+    }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+                    const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_master *master;
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        DSPI_MasterGetDefaultConfig(&master->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+                   const struct nxp_hal_spi_cfg *cfg)
+{
+    struct nxp_spi_slave *slave;
+
+    if (spi->type == HAL_SPI_TYPE_SLAVE) {
+        slave = (struct nxp_spi_slave *) spi;
+        PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+        PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+        DSPI_SlaveGetDefaultConfig(&slave->config);
+        return 0;
+    }
+
+    return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+    struct nxp_hal_spi *spi;
+
+    /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi_type != spi->type) {
+        return EINVAL;
+    }
+
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        return hal_spi_init_master(spi, cfg);
+    } else {
+        return hal_spi_init_slave(spi, cfg);
+    }
+    return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+                uint8_t spi_type,
+                const struct hal_spi_hw_settings *cfg)
+{
+    struct nxp_hal_spi_cfg hal_cfg;
+    hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+    if (spi_type == HAL_SPI_TYPE_MASTER) {
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+    } else {
+        hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+        hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+    }
+    hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+    return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    dspi_clock_polarity_t cpol;
+    dspi_clock_phase_t cpha;
+
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (!settings) {
+        return EINVAL;
+    }
+
+    switch (settings->data_mode) {
+    case HAL_SPI_MODE0:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE1:
+        cpol = kDSPI_ClockPolarityActiveHigh;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    case HAL_SPI_MODE2:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseFirstEdge;
+        break;
+    case HAL_SPI_MODE3:
+        cpol = kDSPI_ClockPolarityActiveLow;
+        cpha = kDSPI_ClockPhaseSecondEdge;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+
+        master->config.ctarConfig.baudRate = settings->baudrate;
+        master->config.ctarConfig.pcsToSckDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.betweenTransferDelayInNanoSec =
+            1000000000U / master->config.ctarConfig.baudRate;
+        master->config.ctarConfig.direction =
+            (settings->data_order == HAL_SPI_MSB_FIRST) ?
+            kDSPI_MsbFirst :
+            kDSPI_LsbFirst;
+        master->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        master->config.ctarConfig.cpol = cpol;
+        master->config.ctarConfig.cpha = cpha;
+    } else {
+        slave = (struct nxp_spi_slave *) spi;
+        slave->config.ctarConfig.bitsPerFrame =
+            (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+        slave->config.ctarConfig.cpol = cpol;
+        slave->config.ctarConfig.cpha = cpha;
+    }
+    return 0;
+}
+
+int
+hal_spi_enable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    struct nxp_spi_master *master;
+    struct nxp_spi_slave *slave;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (spi->enabled) {
+        return 0;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        master = (struct nxp_spi_master *) spi;
+        DSPI_MasterInit(spi->dev,
+                        &master->config,
+                        CLOCK_GetFreq(kCLOCK_BusClk));
+    } else {
+        slave = (struct nxp_spi_slave *) spi;
+        DSPI_SlaveInit(spi->dev, &slave->config);
+    }
+
+    spi->enabled = true;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_SetVector(spi->irqn, (uint32_t) spi->irq_handler);
+    NVIC_EnableIRQ(spi->irqn);
+    return 0;
+}
+
+int
+hal_spi_disable(int spi_num)
+{
+    struct nxp_hal_spi *spi;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+    if (!spi->enabled) {
+        return 0;
+    }
+
+    DSPI_Deinit(spi->dev);
+
+    spi->enabled = false;
+    NVIC_ClearPendingIRQ(spi->irqn);
+    NVIC_DisableIRQ(spi->irqn);
+    return 0;
+}
+
+uint16_t
+hal_spi_tx_val(int spi_num, uint16_t val)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    uint16_t retval = 0;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t *) &val;
+        xfer.rxData = (uint8_t *) &retval;
+        xfer.dataSize = 1;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return retval;
+    }
+    return 0xFFFF; /* Invalid API. */
+}
+
+int
+hal_spi_txrx(int spi_num, void *txbuf, void *rxbuf, int len)
+{
+    struct nxp_hal_spi *spi;
+    dspi_transfer_t xfer;
+    status_t rc;
+    spi = hal_spi_resolve(spi_num);
+    if (!spi) {
+        return EINVAL;
+    }
+
+    if (spi->type == HAL_SPI_TYPE_MASTER) {
+        xfer.txData = (uint8_t *) txbuf;
+        xfer.rxData = (uint8_t *) rxbuf;
+        xfer.dataSize = len;
+        xfer.configFlags = kDSPI_MasterCtar0;
+        rc = DSPI_MasterTransferBlocking(spi->dev, &xfer);
+        return (rc == kStatus_Success) ? 0 : rc;

Review comment:
       If you initialize `rc` to `-1` you can move this `return` after the `if` block.




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[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot commented on pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-773628578


   
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[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.

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