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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/11/24 20:36:52 UTC
[GitHub] [incubator-nuttx] TimJTi opened a new pull request, #7691: GD25Q 4 byte read status issue
TimJTi opened a new pull request, #7691:
URL: https://github.com/apache/incubator-nuttx/pull/7691
## Summary
Attempt 3.
GG25Q devices have the 4 byte read mode in bit 0 not bit 3 of the status register. This change allows for both types, depending on the JEDEC DEVICE ID that is read back.
## Impact
None
## Testing
Custom ATSAMA5D27-D1M board with GG25Q256EFIRR device fitted which now works.
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[GitHub] [incubator-nuttx] TimJTi commented on a diff in pull request #7691: GD25Q 4 byte read status issue
Posted by GitBox <gi...@apache.org>.
TimJTi commented on code in PR #7691:
URL: https://github.com/apache/incubator-nuttx/pull/7691#discussion_r1031866158
##########
drivers/mtd/gd25.c:
##########
@@ -107,6 +107,7 @@
#define GD25_SR_WIP (1 << 0) /* Bit 0: Write in Progress */
#define GD25_SR_WEL (1 << 1) /* Bit 1: Write Enable Latch */
#define GD25_SR1_EN4B (1 << 3) /* Bit 3: Enable 4byte address */
+#define GD25Q_SR1_EN4B (1 << 0) /* Bit 0: Enable 4byte address GD25Q memories */
Review Comment:
This isn't about the WIP bit, it's the 4 byte read bit, which is only relevant to memories with >128mbit.
It's in the second status register, which has different names dependent on the device, and either bit 0 or 3.
The driver will only attempt to read or write this if the size is >128Mbit
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[GitHub] [incubator-nuttx] acassis commented on a diff in pull request #7691: GD25Q 4 byte read status issue
Posted by GitBox <gi...@apache.org>.
acassis commented on code in PR #7691:
URL: https://github.com/apache/incubator-nuttx/pull/7691#discussion_r1031848011
##########
drivers/mtd/gd25.c:
##########
@@ -107,6 +107,7 @@
#define GD25_SR_WIP (1 << 0) /* Bit 0: Write in Progress */
#define GD25_SR_WEL (1 << 1) /* Bit 1: Write Enable Latch */
#define GD25_SR1_EN4B (1 << 3) /* Bit 3: Enable 4byte address */
+#define GD25Q_SR1_EN4B (1 << 0) /* Bit 0: Enable 4byte address GD25Q memories */
Review Comment:
It is not correct for all GD25Q devices GD25Q32 has WIP as bit 0: https://www.elm-tech.com/en/products/spi-flash-memory/gd25q32/gd25q32.pdf
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[GitHub] [nuttx] acassis merged pull request #7691: GD25Q 4 byte read status issue
Posted by GitBox <gi...@apache.org>.
acassis merged PR #7691:
URL: https://github.com/apache/nuttx/pull/7691
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[GitHub] [nuttx] acassis commented on a diff in pull request #7691: GD25Q 4 byte read status issue
Posted by GitBox <gi...@apache.org>.
acassis commented on code in PR #7691:
URL: https://github.com/apache/nuttx/pull/7691#discussion_r1032381233
##########
drivers/mtd/gd25.c:
##########
@@ -107,6 +107,7 @@
#define GD25_SR_WIP (1 << 0) /* Bit 0: Write in Progress */
#define GD25_SR_WEL (1 << 1) /* Bit 1: Write Enable Latch */
#define GD25_SR1_EN4B (1 << 3) /* Bit 3: Enable 4byte address */
+#define GD25Q_SR1_EN4B (1 << 0) /* Bit 0: Enable 4byte address GD25Q memories */
Review Comment:
So, you cannot assume that all GD25Q devices will have EN4B at bit 0 position.
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[GitHub] [nuttx] acassis commented on a diff in pull request #7691: GD25Q 4 byte read status issue
Posted by GitBox <gi...@apache.org>.
acassis commented on code in PR #7691:
URL: https://github.com/apache/nuttx/pull/7691#discussion_r1032380362
##########
drivers/mtd/gd25.c:
##########
@@ -107,6 +107,7 @@
#define GD25_SR_WIP (1 << 0) /* Bit 0: Write in Progress */
#define GD25_SR_WEL (1 << 1) /* Bit 1: Write Enable Latch */
#define GD25_SR1_EN4B (1 << 3) /* Bit 3: Enable 4byte address */
+#define GD25Q_SR1_EN4B (1 << 0) /* Bit 0: Enable 4byte address GD25Q memories */
Review Comment:
Yes, I know it is not WIP, what I said is: in GD25G32 the bit 0 is not EN4B, but WIP:
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[GitHub] [nuttx] acassis commented on a diff in pull request #7691: GD25Q 4 byte read status issue
Posted by GitBox <gi...@apache.org>.
acassis commented on code in PR #7691:
URL: https://github.com/apache/nuttx/pull/7691#discussion_r1032441603
##########
drivers/mtd/gd25.c:
##########
@@ -107,6 +107,7 @@
#define GD25_SR_WIP (1 << 0) /* Bit 0: Write in Progress */
#define GD25_SR_WEL (1 << 1) /* Bit 1: Write Enable Latch */
#define GD25_SR1_EN4B (1 << 3) /* Bit 3: Enable 4byte address */
+#define GD25Q_SR1_EN4B (1 << 0) /* Bit 0: Enable 4byte address GD25Q memories */
Review Comment:
Thank you @TimJTi understood the issue!
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[GitHub] [nuttx] TimJTi commented on a diff in pull request #7691: GD25Q 4 byte read status issue
Posted by GitBox <gi...@apache.org>.
TimJTi commented on code in PR #7691:
URL: https://github.com/apache/nuttx/pull/7691#discussion_r1032386682
##########
drivers/mtd/gd25.c:
##########
@@ -107,6 +107,7 @@
#define GD25_SR_WIP (1 << 0) /* Bit 0: Write in Progress */
#define GD25_SR_WEL (1 << 1) /* Bit 1: Write Enable Latch */
#define GD25_SR1_EN4B (1 << 3) /* Bit 3: Enable 4byte address */
+#define GD25Q_SR1_EN4B (1 << 0) /* Bit 0: Enable 4byte address GD25Q memories */
Review Comment:
Apologies, perhaps what you wrote was ambiguous and I misunderstood - but that is not the bit that is read (it reads the second status reg to get S11 - or S8 with this change) BUT it will not be read for a 32Mbit device anyway. The driver will never attempt to place this device into 4 byte read mode, so it is not a problem:
if (priv->nsectors > GD25_NSECTORS_128MBIT)
{
if (!gd25_4ben(priv))
{
ferr("ERROR: capacity %02x: Can't enable 4-byte mode!\n", capacity);
... etc
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