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Posted to commits@mynewt.apache.org by we...@apache.org on 2016/10/11 00:43:42 UTC
[2/3] incubator-mynewt-core git commit: MYNEWT-433: Add RedBear nano2
bsp.
MYNEWT-433: Add RedBear nano2 bsp.
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/c117b7b2
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/c117b7b2
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/c117b7b2
Branch: refs/heads/develop
Commit: c117b7b27d1f01a2d1a3a8313f7979115b8ad4bc
Parents: b3b452c
Author: William San Filippo <wi...@runtime.io>
Authored: Mon Oct 10 17:42:35 2016 -0700
Committer: William San Filippo <wi...@runtime.io>
Committed: Mon Oct 10 17:43:33 2016 -0700
----------------------------------------------------------------------
hw/bsp/rb-nano2/boot-rb-nano2.ld | 191 ++++++++
hw/bsp/rb-nano2/bsp.yml | 58 +++
hw/bsp/rb-nano2/cmsis-dap.cfg | 12 +
hw/bsp/rb-nano2/include/bsp/boards.h | 0
hw/bsp/rb-nano2/include/bsp/bsp.h | 53 +++
hw/bsp/rb-nano2/include/bsp/bsp_sysid.h | 37 ++
hw/bsp/rb-nano2/include/bsp/cmsis_nvic.h | 29 ++
hw/bsp/rb-nano2/include/bsp/nrf_drv_config.h | 471 +++++++++++++++++++
hw/bsp/rb-nano2/nrf52.cfg | 41 ++
hw/bsp/rb-nano2/pkg.yml | 48 ++
hw/bsp/rb-nano2/rb-nano2.ld | 202 ++++++++
hw/bsp/rb-nano2/rb-nano2_debug.sh | 56 +++
hw/bsp/rb-nano2/rb-nano2_download.sh | 120 +++++
hw/bsp/rb-nano2/rb-nano2_no_boot.ld | 191 ++++++++
hw/bsp/rb-nano2/split-rb-nano2.ld | 208 ++++++++
.../src/arch/cortex_m4/gcc_startup_nrf52.s | 294 ++++++++++++
.../arch/cortex_m4/gcc_startup_nrf52_split.s | 152 ++++++
hw/bsp/rb-nano2/src/hal_bsp.c | 65 +++
hw/bsp/rb-nano2/src/libc_stubs.c | 84 ++++
hw/bsp/rb-nano2/src/os_bsp.c | 72 +++
hw/bsp/rb-nano2/src/sbrk.c | 59 +++
hw/bsp/rb-nano2/src/system_nrf52.c | 183 +++++++
hw/bsp/rb-nano2/syscfg.yml | 90 ++++
23 files changed, 2716 insertions(+)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/boot-rb-nano2.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/boot-rb-nano2.ld b/hw/bsp/rb-nano2/boot-rb-nano2.ld
new file mode 100755
index 0000000..5bb2099
--- /dev/null
+++ b/hw/bsp/rb-nano2/boot-rb-nano2.ld
@@ -0,0 +1,191 @@
+/* Linker script for Nordic Semiconductor nRF5 devices
+ *
+ * Version: Sourcery G++ 4.5-1
+ * Support: https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x4000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __bssnz_start__
+ * __bssnz_end__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ __isr_vector_start = .;
+ KEEP(*(.isr_vector))
+ __isr_vector_end = .;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ *(.eh_frame*)
+ . = ALIGN(4);
+ } > FLASH
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ . = ALIGN(4);
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .vector_relocation :
+ {
+ . = ALIGN(4);
+ __vector_tbl_reloc__ = .;
+ . = . + (__isr_vector_end - __isr_vector_start);
+ . = ALIGN(4);
+ } > RAM
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ *(.preinit_array)
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ *(SORT(.init_array.*))
+ *(.init_array)
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ *(SORT(.fini_array.*))
+ *(.fini_array)
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ *(.jcr)
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ } > RAM
+
+ /* Non-zeroed BSS. This section is similar to BSS, with the following
+ * caveat:
+ * 1. It does not get zeroed at init-time.
+ */
+ .bssnz :
+ {
+ . = ALIGN(4);
+ __bssnz_start__ = .;
+ *(.bss.core.nz*)
+ . = ALIGN(4);
+ __bssnz_end__ = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ /* Heap starts after BSS */
+ __HeapBase = .;
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Top of head is the bottom of the stack */
+ __HeapLimit = __StackLimit;
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack")
+}
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/bsp.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/bsp.yml b/hw/bsp/rb-nano2/bsp.yml
new file mode 100644
index 0000000..bc9ef54
--- /dev/null
+++ b/hw/bsp/rb-nano2/bsp.yml
@@ -0,0 +1,58 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+bsp.arch: cortex_m4
+bsp.compiler: compiler/arm-none-eabi-m4
+bsp.linkerscript: "rb-nano2.ld"
+bsp.linkerscript.BOOT_LOADER.OVERWRITE: "boot-rb-nano2.ld"
+bsp.part2linkerscript: "split-rb-nano2.ld"
+bsp.downloadscript: rb-nano2_download.sh
+bsp.debugscript: rb-nano2_debug.sh
+
+bsp.flash_map:
+ areas:
+ # System areas.
+ FLASH_AREA_BOOTLOADER:
+ device: 0
+ offset: 0x00000000
+ size: 16kB
+ FLASH_AREA_IMAGE_0:
+ device: 0
+ offset: 0x00008000
+ size: 232kB
+ FLASH_AREA_IMAGE_1:
+ device: 0
+ offset: 0x00042000
+ size: 232kB
+ FLASH_AREA_IMAGE_SCRATCH:
+ device: 0
+ offset: 0x0007c000
+ size: 4kB
+
+ # User areas.
+ FLASH_AREA_REBOOT_LOG:
+ user_id: 0
+ device: 0
+ offset: 0x00004000
+ size: 16kB
+ FLASH_AREA_NFFS:
+ user_id: 1
+ device: 0
+ offset: 0x0007d000
+ size: 12kB
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/cmsis-dap.cfg
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/cmsis-dap.cfg b/hw/bsp/rb-nano2/cmsis-dap.cfg
new file mode 100644
index 0000000..7251280
--- /dev/null
+++ b/hw/bsp/rb-nano2/cmsis-dap.cfg
@@ -0,0 +1,12 @@
+#
+# ARM CMSIS-DAP compliant adapter
+#
+# http://www.keil.com/support/man/docs/dapdebug/
+#
+
+interface cmsis-dap
+
+#set WORKAREASIZE 0x2000
+
+# Optionally specify the serial number of CMSIS-DAP usb device.
+#cmsis_dap_serial 02200201E6661E601B98E3B9
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/include/bsp/boards.h
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/include/bsp/boards.h b/hw/bsp/rb-nano2/include/bsp/boards.h
new file mode 100644
index 0000000..e69de29
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/include/bsp/bsp.h
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/include/bsp/bsp.h b/hw/bsp/rb-nano2/include/bsp/bsp.h
new file mode 100644
index 0000000..a1a7455
--- /dev/null
+++ b/hw/bsp/rb-nano2/include/bsp/bsp.h
@@ -0,0 +1,53 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef H_BSP_H
+#define H_BSP_H
+
+#include <inttypes.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define special stackos sections */
+#define sec_data_core __attribute__((section(".data.core")))
+#define sec_bss_core __attribute__((section(".bss.core")))
+#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+/* More convenient section placement macros. */
+#define bssnz_t sec_bss_nz_core
+
+extern uint8_t _ram_start;
+#define RAM_SIZE 0x10000
+
+/* LED */
+#define LED_BLINK_PIN (11)
+
+/* UART info */
+#define CONSOLE_UART "uart0"
+#define CONSOLE_UART_SPEED 115200
+
+#define NFFS_AREA_MAX (8)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_BSP_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/include/bsp/bsp_sysid.h
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/include/bsp/bsp_sysid.h b/hw/bsp/rb-nano2/include/bsp/bsp_sysid.h
new file mode 100644
index 0000000..63959e5
--- /dev/null
+++ b/hw/bsp/rb-nano2/include/bsp/bsp_sysid.h
@@ -0,0 +1,37 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef BSP_SYSID_H
+#define BSP_SYSID_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* stub until this BSP gets new HAL */
+enum system_device_id
+{
+ RESERVED,
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BSP_SYSID_H */
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/include/bsp/cmsis_nvic.h
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/include/bsp/cmsis_nvic.h b/hw/bsp/rb-nano2/include/bsp/cmsis_nvic.h
new file mode 100644
index 0000000..856f7d0
--- /dev/null
+++ b/hw/bsp/rb-nano2/include/bsp/cmsis_nvic.h
@@ -0,0 +1,29 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include <stdint.h>
+
+#define NVIC_NUM_VECTORS (16 + 38) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "nrf52.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_Relocate(void);
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/include/bsp/nrf_drv_config.h
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/include/bsp/nrf_drv_config.h b/hw/bsp/rb-nano2/include/bsp/nrf_drv_config.h
new file mode 100644
index 0000000..b5c7806
--- /dev/null
+++ b/hw/bsp/rb-nano2/include/bsp/nrf_drv_config.h
@@ -0,0 +1,471 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+#ifndef NRF_DRV_CONFIG_H
+#define NRF_DRV_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Provide a non-zero value here in applications that need to use several
+ * peripherals with the same ID that are sharing certain resources
+ * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used
+ * simultaneously. Therefore, this definition allows to initialize the driver
+ * for another peripheral from a given group only after the previously used one
+ * is uninitialized. Normally, this is not possible, because interrupt handlers
+ * are implemented in individual drivers.
+ * This functionality requires a more complicated interrupt handling and driver
+ * initialization, hence it is not always desirable to use it.
+ */
+#define PERIPHERAL_RESOURCE_SHARING_ENABLED 1
+
+/* CLOCK */
+#define CLOCK_ENABLED 1
+
+#if (CLOCK_ENABLED == 1)
+#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
+#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal
+#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* GPIOTE */
+#define GPIOTE_ENABLED 1
+
+#if (GPIOTE_ENABLED == 1)
+#define GPIOTE_CONFIG_USE_SWI_EGU false
+#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
+#endif
+
+/* TIMER */
+#define TIMER0_ENABLED 1
+
+#if (TIMER0_ENABLED == 1)
+#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
+#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER0_INSTANCE_INDEX 0
+#endif
+
+#define TIMER1_ENABLED 0
+
+#if (TIMER1_ENABLED == 1)
+#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
+#endif
+
+#define TIMER2_ENABLED 0
+
+#if (TIMER2_ENABLED == 1)
+#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER3_ENABLED 0
+
+#if (TIMER3_ENABLED == 1)
+#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER4_ENABLED 0
+
+#if (TIMER4_ENABLED == 1)
+#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+
+#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
+
+/* RTC */
+#define RTC0_ENABLED 0
+
+#if (RTC0_ENABLED == 1)
+#define RTC0_CONFIG_FREQUENCY 32678
+#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC0_CONFIG_RELIABLE false
+
+#define RTC0_INSTANCE_INDEX 0
+#endif
+
+#define RTC1_ENABLED 0
+
+#if (RTC1_ENABLED == 1)
+#define RTC1_CONFIG_FREQUENCY 32768
+#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC1_CONFIG_RELIABLE false
+
+#define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
+#endif
+
+#define RTC2_ENABLED 0
+
+#if (RTC2_ENABLED == 1)
+#define RTC2_CONFIG_FREQUENCY 32768
+#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC2_CONFIG_RELIABLE false
+
+#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED)
+#endif
+
+
+#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED)
+
+#define NRF_MAXIMUM_LATENCY_US 2000
+
+/* RNG */
+#define RNG_ENABLED 1
+
+#if (RNG_ENABLED == 1)
+#define RNG_CONFIG_ERROR_CORRECTION true
+#define RNG_CONFIG_POOL_SIZE 8
+#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PWM */
+
+#define PWM0_ENABLED 1
+
+#if (PWM0_ENABLED == 1)
+#define PWM0_CONFIG_OUT0_PIN 2
+#define PWM0_CONFIG_OUT1_PIN 3
+#define PWM0_CONFIG_OUT2_PIN 4
+#define PWM0_CONFIG_OUT3_PIN 5
+#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM0_CONFIG_TOP_VALUE 1000
+#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM0_INSTANCE_INDEX 0
+#endif
+
+#define PWM1_ENABLED 0
+
+#if (PWM1_ENABLED == 1)
+#define PWM1_CONFIG_OUT0_PIN 2
+#define PWM1_CONFIG_OUT1_PIN 3
+#define PWM1_CONFIG_OUT2_PIN 4
+#define PWM1_CONFIG_OUT3_PIN 5
+#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM1_CONFIG_TOP_VALUE 1000
+#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM1_INSTANCE_INDEX (PWM0_ENABLED)
+#endif
+
+#define PWM2_ENABLED 0
+
+#if (PWM2_ENABLED == 1)
+#define PWM2_CONFIG_OUT0_PIN 2
+#define PWM2_CONFIG_OUT1_PIN 3
+#define PWM2_CONFIG_OUT2_PIN 4
+#define PWM2_CONFIG_OUT3_PIN 5
+#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM2_CONFIG_TOP_VALUE 1000
+#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED)
+#endif
+
+#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED)
+
+/* SPI */
+#define SPI0_ENABLED 1
+
+#if (SPI0_ENABLED == 1)
+#define SPI0_USE_EASY_DMA 1
+#define SPI0_CONFIG_SCK_PIN 2
+#define SPI0_CONFIG_MOSI_PIN 3
+#define SPI0_CONFIG_MISO_PIN 4
+#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI0_INSTANCE_INDEX 0
+#endif
+
+#define SPI1_ENABLED 0
+
+#if (SPI1_ENABLED == 1)
+#define SPI1_USE_EASY_DMA 0
+
+#define SPI1_CONFIG_SCK_PIN 2
+#define SPI1_CONFIG_MOSI_PIN 3
+#define SPI1_CONFIG_MISO_PIN 4
+#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
+#endif
+
+#define SPI2_ENABLED 0
+
+#if (SPI2_ENABLED == 1)
+#define SPI2_USE_EASY_DMA 0
+
+#define SPI2_CONFIG_SCK_PIN 2
+#define SPI2_CONFIG_MOSI_PIN 3
+#define SPI2_CONFIG_MISO_PIN 4
+#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
+#endif
+
+#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
+
+/* SPIS */
+#define SPIS0_ENABLED 1
+
+#if (SPIS0_ENABLED == 1)
+#define SPIS0_CONFIG_SCK_PIN 23
+#define SPIS0_CONFIG_MOSI_PIN 24
+#define SPIS0_CONFIG_MISO_PIN 25
+#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS0_INSTANCE_INDEX 0
+#endif
+
+#define SPIS1_ENABLED 0
+
+#if (SPIS1_ENABLED == 1)
+#define SPIS1_CONFIG_SCK_PIN 2
+#define SPIS1_CONFIG_MOSI_PIN 3
+#define SPIS1_CONFIG_MISO_PIN 4
+#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
+#endif
+
+#define SPIS2_ENABLED 0
+
+#if (SPIS2_ENABLED == 1)
+#define SPIS2_CONFIG_SCK_PIN 2
+#define SPIS2_CONFIG_MOSI_PIN 3
+#define SPIS2_CONFIG_MISO_PIN 4
+#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
+#endif
+
+#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED)
+
+/* UART */
+#define UART0_ENABLED 1
+
+#if (UART0_ENABLED == 1)
+#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED
+#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED
+#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200
+#define UART0_CONFIG_PSEL_TXD 0
+#define UART0_CONFIG_PSEL_RXD 0
+#define UART0_CONFIG_PSEL_CTS 0
+#define UART0_CONFIG_PSEL_RTS 0
+#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#ifdef NRF52
+#define UART0_CONFIG_USE_EASY_DMA false
+//Compile time flag
+#define UART_EASY_DMA_SUPPORT 1
+#define UART_LEGACY_SUPPORT 1
+#endif //NRF52
+#endif
+
+#define TWI0_ENABLED 1
+
+#if (TWI0_ENABLED == 1)
+#define TWI0_USE_EASY_DMA 0
+
+#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
+#define TWI0_CONFIG_SCL 0
+#define TWI0_CONFIG_SDA 1
+#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI0_INSTANCE_INDEX 0
+#endif
+
+#define TWI1_ENABLED 1
+
+#if (TWI1_ENABLED == 1)
+#define TWI1_USE_EASY_DMA 0
+
+#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
+#define TWI1_CONFIG_SCL 0
+#define TWI1_CONFIG_SDA 1
+#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
+#endif
+
+#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED)
+
+/* TWIS */
+#define TWIS0_ENABLED 1
+
+#if (TWIS0_ENABLED == 1)
+ #define TWIS0_CONFIG_ADDR0 0
+ #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
+ #define TWIS0_CONFIG_SCL 0
+ #define TWIS0_CONFIG_SDA 1
+ #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+ #define TWIS0_INSTANCE_INDEX 0
+#endif
+
+#define TWIS1_ENABLED 0
+
+#if (TWIS1_ENABLED == 1)
+ #define TWIS1_CONFIG_ADDR0 0
+ #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
+ #define TWIS1_CONFIG_SCL 0
+ #define TWIS1_CONFIG_SDA 1
+ #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+ #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
+#endif
+
+#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_NO_SYNC_MODE 0
+
+/* QDEC */
+#define QDEC_ENABLED 1
+
+#if (QDEC_ENABLED == 1)
+#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10
+#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us
+#define QDEC_CONFIG_PIO_A 1
+#define QDEC_CONFIG_PIO_B 2
+#define QDEC_CONFIG_PIO_LED 3
+#define QDEC_CONFIG_LEDPRE 511
+#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
+#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define QDEC_CONFIG_DBFEN false
+#define QDEC_CONFIG_SAMPLE_INTEN false
+#endif
+
+/* ADC */
+#define ADC_ENABLED 0
+
+#if (ADC_ENABLED == 1)
+#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+
+/* SAADC */
+#define SAADC_ENABLED 1
+
+#if (SAADC_ENABLED == 1)
+#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
+#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
+#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PDM */
+#define PDM_ENABLED 0
+
+#if (PDM_ENABLED == 1)
+#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO
+#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING
+#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K
+#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* COMP */
+#define COMP_ENABLED 1
+
+#if (COMP_ENABLED == 1)
+#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8
+#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE
+#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High
+#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst
+#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off
+#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0
+#endif
+
+/* LPCOMP */
+#define LPCOMP_ENABLED 1
+
+#if (LPCOMP_ENABLED == 1)
+#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
+#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
+#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
+#endif
+
+/* WDT */
+#define WDT_ENABLED 1
+
+#if (WDT_ENABLED == 1)
+#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP
+#define WDT_CONFIG_RELOAD_VALUE 2000
+#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#endif
+
+/* SWI EGU */
+#ifdef NRF52
+ #define EGU_ENABLED 0
+#endif
+
+/* I2S */
+#define I2S_ENABLED 1
+
+#if (I2S_ENABLED == 1)
+#define I2S_CONFIG_SCK_PIN 22
+#define I2S_CONFIG_LRCK_PIN 23
+#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED
+#define I2S_CONFIG_SDOUT_PIN 24
+#define I2S_CONFIG_SDIN_PIN 25
+#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER
+#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S
+#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT
+#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT
+#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO
+#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8
+#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X
+#endif
+
+#include "nrf_drv_config_validation.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_DRV_CONFIG_H
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/nrf52.cfg
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/nrf52.cfg b/hw/bsp/rb-nano2/nrf52.cfg
new file mode 100644
index 0000000..c4ba167
--- /dev/null
+++ b/hw/bsp/rb-nano2/nrf52.cfg
@@ -0,0 +1,41 @@
+#
+# Nordic nRF52 series: ARM Cortex-M4 @ 64 MHz
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME nrf52
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x2ba01477
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x4000
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash nrf52 0x00000000 0 1 1 $_TARGETNAME
+flash bank $_CHIPNAME.uicr nrf52 0x10001000 0 1 1 $_TARGETNAME
+
+adapter_khz 10000
+
+if { ![using_hla] } {
+ cortex_m reset_config sysresetreq
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/pkg.yml b/hw/bsp/rb-nano2/pkg.yml
new file mode 100644
index 0000000..1b6f68b
--- /dev/null
+++ b/hw/bsp/rb-nano2/pkg.yml
@@ -0,0 +1,48 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/rb-nano2
+pkg.type: bsp
+pkg.description: BSP definition for the Red Bear Labs nano2 module.
+pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - nrf52
+ - nano2
+ - RedBearLabs
+
+pkg.cflags:
+ # Nordic SDK files require these defines.
+ - '-DNRF52'
+ - '-DSPI_MASTER_0_ENABLE'
+
+pkg.deps:
+ - boot/bootutil
+ - hw/mcu/nordic/nrf52xxx
+ - libc/baselibc
+ - sys/flash_map
+
+pkg.deps.BLE_DEVICE:
+ - hw/drivers/nimble/nrf52
+
+pkg.deps.ADC_0:
+ - hw/drivers/adc/adc_nrf52
+
+pkg.deps.UART_0:
+ - hw/drivers/uart/uart_hal
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/rb-nano2.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/rb-nano2.ld b/hw/bsp/rb-nano2/rb-nano2.ld
new file mode 100755
index 0000000..e131176
--- /dev/null
+++ b/hw/bsp/rb-nano2/rb-nano2.ld
@@ -0,0 +1,202 @@
+/* Linker script for Nordic Semiconductor nRF5 devices
+ *
+ * Version: Sourcery G++ 4.5-1
+ * Support: https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00008000, LENGTH = 0x3a000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __bssnz_start__
+ * __bssnz_end__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .imghdr (NOLOAD):
+ {
+ . = . + 0x20;
+ } > FLASH
+
+ .text :
+ {
+ __isr_vector_start = .;
+ KEEP(*(.isr_vector))
+ __isr_vector_end = .;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ *(.eh_frame*)
+ . = ALIGN(4);
+ } > FLASH
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ . = ALIGN(4);
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .vector_relocation :
+ {
+ . = ALIGN(4);
+ __vector_tbl_reloc__ = .;
+ . = . + (__isr_vector_end - __isr_vector_start);
+ . = ALIGN(4);
+ } > RAM
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ *(.preinit_array)
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ *(SORT(.init_array.*))
+ *(.init_array)
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ *(SORT(.fini_array.*))
+ *(.fini_array)
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ *(.jcr)
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ } > RAM
+
+ /* Non-zeroed BSS. This section is similar to BSS, with the following two
+ * caveats:
+ * 1. It does not get zeroed at init-time.
+ * 2. You cannot use it as source memory for EasyDMA.
+ *
+ * This section exists because of a hardware defect; see errata 33 and 34
+ * in nrf52 errata sheet.
+ */
+ .bssnz :
+ {
+ . = ALIGN(4);
+ __bssnz_start__ = .;
+ *(.bss.core.nz*)
+ . = ALIGN(4);
+ __bssnz_end__ = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ /* Heap starts after BSS */
+ __HeapBase = .;
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ _ram_start = ORIGIN(RAM);
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Top of head is the bottom of the stack */
+ __HeapLimit = __StackLimit;
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack")
+}
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/rb-nano2_debug.sh
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/rb-nano2_debug.sh b/hw/bsp/rb-nano2/rb-nano2_debug.sh
new file mode 100755
index 0000000..ccaf5fd
--- /dev/null
+++ b/hw/bsp/rb-nano2/rb-nano2_debug.sh
@@ -0,0 +1,56 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - RESET set if target should be reset when attaching
+#
+if [ -z "$BIN_BASENAME" ]; then
+ echo "Need binary to debug"
+ exit 1
+fi
+
+if [ -z "$BSP_PATH" ]; then
+ echo "Need BSP path for openocd script location"
+ exit 1
+fi
+
+FILE_NAME=$BIN_BASENAME.elf
+GDB_CMD_FILE=.gdb_cmds
+
+echo "Debugging" $FILE_NAME
+
+set -m
+openocd -s $BSP_PATH -f cmsis-dap.cfg -f nrf52.cfg -c "nrf52.cpu configure -event gdb-detach {resume;shutdown}" -c "$EXTRA_JTAG_CMD" -c init -c halt &
+set +m
+
+echo "target remote localhost:3333" > $GDB_CMD_FILE
+# Whether target should be reset or not
+if [ ! -z "$RESET" ]; then
+ echo "mon reset" >> $GDB_CMD_FILE
+fi
+
+arm-none-eabi-gdb -x $GDB_CMD_FILE $FILE_NAME
+
+rm $GDB_CMD_FILE
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/rb-nano2_download.sh
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/rb-nano2_download.sh b/hw/bsp/rb-nano2/rb-nano2_download.sh
new file mode 100755
index 0000000..d461450
--- /dev/null
+++ b/hw/bsp/rb-nano2/rb-nano2_download.sh
@@ -0,0 +1,120 @@
+#!/bin/bash
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+#
+
+if [ -z "$BIN_BASENAME" ]; then
+ echo "Need binary to download"
+ exit 1
+fi
+
+if [ -z "$IMAGE_SLOT" ]; then
+ echo "Need image slot to download"
+ exit 1
+fi
+
+IS_BOOTLOADER=0
+#JLINK_SCRIPT=.download.jlink
+GDB_CMD_FILE=.gdb_cmds
+
+# Look for 'bootloader' in FEATURES
+for feature in $FEATURES; do
+ if [ $feature == "BOOT_LOADER" ]; then
+ IS_BOOTLOADER=1
+ fi
+done
+
+if [ $IS_BOOTLOADER -eq 1 ]; then
+ FLASH_OFFSET=0x0
+ FILE_NAME=$BIN_BASENAME.elf.bin
+elif [ $IMAGE_SLOT -eq 0 ]; then
+ FLASH_OFFSET=0x8000
+ FILE_NAME=$BIN_BASENAME.img
+elif [ $IMAGE_SLOT -eq 1 ]; then
+ FLASH_OFFSET=0x23800
+ FILE_NAME=$BIN_BASENAME.img
+else
+ echo "Invalid Image Slot Number: $IMAGE_SLOT"
+ exit 1
+fi
+
+echo "Downloading" $FILE_NAME "to" $FLASH_OFFSET
+
+if [ ! -f $FILE_NAME ]; then
+ echo "File " $FILE_NAME "not found"
+ exit 1
+fi
+
+# XXX for some reason JLinkExe overwrites flash at offset 0 when
+# downloading somewhere in the flash. So need to figure out how to tell it
+# not to do that, or report failure if gdb fails to write this file
+#
+echo "shell /bin/sh -c 'trap \"\" 2;openocd -s $BSP_PATH -f cmsis-dap.cfg -c \"$EXTRA_JTAG_CMD\" -f nrf52.cfg' &" > $GDB_CMD_FILE
+echo "target remote localhost:3333" >> $GDB_CMD_FILE
+echo "monitor reset halt" >> $GDB_CMD_FILE
+echo "monitor flash write_image erase $FILE_NAME $FLASH_OFFSET" >> $GDB_CMD_FILE
+echo "monitor reset run" >> $GDB_CMD_FILE
+echo "monitor shutdown" >> $GDB_CMD_FILE
+echo "quit" >> $GDB_CMD_FILE
+
+msgs=`arm-none-eabi-gdb -x $GDB_CMD_FILE 2>&1`
+echo $msgs > .gdb_out
+
+rm $GDB_CMD_FILE
+
+#cat > $JLINK_SCRIPT <<EOF
+#w 4001e504 1
+#loadbin $FILE_NAME,$FLASH_OFFSET
+#q
+#EOF
+
+#msgs=`JLinkExe -device nRF52 -speed 4000 -if SWD $JLINK_SCRIPT`
+
+# Echo output from script run, so newt can show it if things go wrong.
+echo $msgs
+#rm $JLINK_SCRIPT
+
+error=`echo $msgs | grep error | grep -v Ignoring`
+if [ -n "$error" ]; then
+ exit 1
+fi
+
+error=`echo $msgs | grep -i failed`
+if [ -n "$error" ]; then
+ exit 1
+fi
+
+error=`echo $msgs | grep -i "unknown / supported"`
+if [ -n "$error" ]; then
+ exit 1
+fi
+
+error=`echo $msgs | grep -i "not found"`
+if [ -n "$error" ]; then
+ exit 1
+fi
+
+exit 0
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/rb-nano2_no_boot.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/rb-nano2_no_boot.ld b/hw/bsp/rb-nano2/rb-nano2_no_boot.ld
new file mode 100755
index 0000000..e2fb5a8
--- /dev/null
+++ b/hw/bsp/rb-nano2/rb-nano2_no_boot.ld
@@ -0,0 +1,191 @@
+/* Linker script for Nordic Semiconductor nRF5 devices
+ *
+ * Version: Sourcery G++ 4.5-1
+ * Support: https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __bssnz_start__
+ * __bssnz_end__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ __isr_vector_start = .;
+ KEEP(*(.isr_vector))
+ __isr_vector_end = .;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ *(.eh_frame*)
+ . = ALIGN(4);
+ } > FLASH
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ . = ALIGN(4);
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .vector_relocation :
+ {
+ . = ALIGN(4);
+ __vector_tbl_reloc__ = .;
+ . = . + (__isr_vector_end - __isr_vector_start);
+ . = ALIGN(4);
+ } > RAM
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ *(.preinit_array)
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ *(SORT(.init_array.*))
+ *(.init_array)
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ *(SORT(.fini_array.*))
+ *(.fini_array)
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ *(.jcr)
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ } > RAM
+
+ /* Non-zeroed BSS. This section is similar to BSS, with the following
+ * caveat:
+ * 1. It does not get zeroed at init-time.
+ */
+ .bssnz :
+ {
+ . = ALIGN(4);
+ __bssnz_start__ = .;
+ *(.bss.core.nz*)
+ . = ALIGN(4);
+ __bssnz_end__ = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ /* Heap starts after BSS */
+ __HeapBase = .;
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Top of head is the bottom of the stack */
+ __HeapLimit = __StackLimit;
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack")
+}
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/split-rb-nano2.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/split-rb-nano2.ld b/hw/bsp/rb-nano2/split-rb-nano2.ld
new file mode 100755
index 0000000..ebfac21
--- /dev/null
+++ b/hw/bsp/rb-nano2/split-rb-nano2.ld
@@ -0,0 +1,208 @@
+/* Linker script for Nordic Semiconductor nRF5 devices
+ *
+ * Version: Sourcery G++ 4.5-1
+ * Support: https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00042000, LENGTH = 0x3a000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __bssnz_start__
+ * __bssnz_end__
+ */
+ENTRY(Reset_Handler_split)
+
+SECTIONS
+{
+ .imghdr (NOLOAD):
+ {
+ . = . + 0x20;
+ } > FLASH
+
+ .text :
+ {
+ __split_isr_vector_start = .;
+ KEEP(*(.isr_vector_split))
+ __split_isr_vector_end = .;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ *(.eh_frame*)
+ . = ALIGN(4);
+ } > FLASH
+
+
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ . = ALIGN(4);
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ /* save RAM used by the split image. This assumes that
+ * the loader uses all the RAM up to its HeapBase */
+ .loader_ram_contents :
+ {
+ _loader_ram_start = .;
+
+ /* this symbol comes from the loader linker */
+ . = . + (ABSOLUTE(__HeapBase_loader) - _loader_ram_start);
+ _loader_ram_end = .;
+ } > RAM
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ *(.preinit_array)
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ *(SORT(.init_array.*))
+ *(.init_array)
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ *(SORT(.fini_array.*))
+ *(.fini_array)
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ *(.jcr)
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ } > RAM
+
+ /* Non-zeroed BSS. This section is similar to BSS, with the following two
+ * caveats:
+ * 1. It does not get zeroed at init-time.
+ * 2. You cannot use it as source memory for EasyDMA.
+ *
+ * This section exists because of a hardware defect; see errata 33 and 34
+ * in nrf52 errata sheet.
+ */
+ .bssnz :
+ {
+ . = ALIGN(4);
+ __bssnz_start__ = .;
+ *(.bss.core.nz*)
+ . = ALIGN(4);
+ __bssnz_end__ = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ /* Heap starts after BSS */
+ __HeapBase = .;
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ _ram_start = ORIGIN(RAM);
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Top of head is the bottom of the stack */
+ __HeapLimit = __StackLimit;
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack")
+}
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52.s
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52.s b/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52.s
new file mode 100755
index 0000000..54b76ad
--- /dev/null
+++ b/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52.s
@@ -0,0 +1,294 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long POWER_CLOCK_IRQHandler
+ .long RADIO_IRQHandler
+ .long UARTE0_UART0_IRQHandler
+ .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ .long NFCT_IRQHandler
+ .long GPIOTE_IRQHandler
+ .long SAADC_IRQHandler
+ .long TIMER0_IRQHandler
+ .long TIMER1_IRQHandler
+ .long TIMER2_IRQHandler
+ .long RTC0_IRQHandler
+ .long TEMP_IRQHandler
+ .long RNG_IRQHandler
+ .long ECB_IRQHandler
+ .long CCM_AAR_IRQHandler
+ .long WDT_IRQHandler
+ .long RTC1_IRQHandler
+ .long QDEC_IRQHandler
+ .long COMP_LPCOMP_IRQHandler
+ .long SWI0_EGU0_IRQHandler
+ .long SWI1_EGU1_IRQHandler
+ .long SWI2_EGU2_IRQHandler
+ .long SWI3_EGU3_IRQHandler
+ .long SWI4_EGU4_IRQHandler
+ .long SWI5_EGU5_IRQHandler
+ .long TIMER3_IRQHandler
+ .long TIMER4_IRQHandler
+ .long PWM0_IRQHandler
+ .long PDM_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long MWU_IRQHandler
+ .long PWM1_IRQHandler
+ .long PWM2_IRQHandler
+ .long SPIM2_SPIS2_SPI2_IRQHandler
+ .long RTC2_IRQHandler
+ .long I2S_IRQHandler
+
+ .size __isr_vector, . - __isr_vector
+
+/* Reset Handler */
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ .fnstart
+
+ /* This is called but current_slot is in the data section so it is
+ * overwritten. its only called here to ensure that the global and this
+ * function are linked into the loader */
+ BL boot_set_image_slot_split
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+
+.LC0:
+
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler,.-Reset_Handler
+
+ .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+
+ .weak MemoryManagement_Handler
+ .type MemoryManagement_Handler, %function
+MemoryManagement_Handler:
+ B .
+ .size MemoryManagement_Handler, . - MemoryManagement_Handler
+
+
+ .weak BusFault_Handler
+ .type BusFault_Handler, %function
+BusFault_Handler:
+ B .
+ .size BusFault_Handler, . - BusFault_Handler
+
+
+ .weak UsageFault_Handler
+ .type UsageFault_Handler, %function
+UsageFault_Handler:
+ B .
+ .size UsageFault_Handler, . - UsageFault_Handler
+
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ POWER_CLOCK_IRQHandler
+ IRQ RADIO_IRQHandler
+ IRQ UARTE0_UART0_IRQHandler
+ IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ IRQ NFCT_IRQHandler
+ IRQ GPIOTE_IRQHandler
+ IRQ SAADC_IRQHandler
+ IRQ TIMER0_IRQHandler
+ IRQ TIMER1_IRQHandler
+ IRQ TIMER2_IRQHandler
+ IRQ RTC0_IRQHandler
+ IRQ TEMP_IRQHandler
+ IRQ RNG_IRQHandler
+ IRQ ECB_IRQHandler
+ IRQ CCM_AAR_IRQHandler
+ IRQ WDT_IRQHandler
+ IRQ RTC1_IRQHandler
+ IRQ QDEC_IRQHandler
+ IRQ COMP_LPCOMP_IRQHandler
+ IRQ SWI0_EGU0_IRQHandler
+ IRQ SWI1_EGU1_IRQHandler
+ IRQ SWI2_EGU2_IRQHandler
+ IRQ SWI3_EGU3_IRQHandler
+ IRQ SWI4_EGU4_IRQHandler
+ IRQ SWI5_EGU5_IRQHandler
+ IRQ TIMER3_IRQHandler
+ IRQ TIMER4_IRQHandler
+ IRQ PWM0_IRQHandler
+ IRQ PDM_IRQHandler
+ IRQ MWU_IRQHandler
+ IRQ PWM1_IRQHandler
+ IRQ PWM2_IRQHandler
+ IRQ SPIM2_SPIS2_SPI2_IRQHandler
+ IRQ RTC2_IRQHandler
+ IRQ I2S_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52_split.s
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52_split.s b/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52_split.s
new file mode 100755
index 0000000..26bb3a8
--- /dev/null
+++ b/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52_split.s
@@ -0,0 +1,152 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv7-m
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector_split
+ .align 2
+ .globl __isr_vector_split
+__isr_vector_split:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler_split /* Reset Handler */
+
+ .size __isr_vector_split, . - __isr_vector_split
+
+/* Reset Handler */
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler_split
+ .type Reset_Handler_split, %function
+Reset_Handler_split:
+ .fnstart
+
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+
+.LC0:
+ ldr r1, =__etext_loader
+ ldr r2, =__data_start___loader
+ ldr r3, =__data_end___loader
+
+ subs r3, r2
+ ble .LC2
+
+.LC3:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC3
+.LC2:
+
+ subs r0, r0
+ ldr r2, =__bss_start___loader
+ ldr r3, =__bss_end___loader
+
+ subs r3, r2
+ ble .LC4
+
+.LC5:
+ subs r3, 4
+ str r0, [r2,r3]
+ bgt .LC5
+.LC4:
+
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ BL boot_set_image_slot_split
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler_split,.-Reset_Handler_split
+
+ .section ".text"
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/src/hal_bsp.c b/hw/bsp/rb-nano2/src/hal_bsp.c
new file mode 100644
index 0000000..242c862
--- /dev/null
+++ b/hw/bsp/rb-nano2/src/hal_bsp.c
@@ -0,0 +1,65 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <stdint.h>
+#include <stddef.h>
+
+#include "bsp/bsp.h"
+#include <hal/hal_bsp.h>
+#include "mcu/nrf52_hal.h"
+
+/*
+ * What memory to include in coredump.
+ */
+static const struct bsp_mem_dump dump_cfg[] = {
+ [0] = {
+ .bmd_start = &_ram_start,
+ .bmd_size = RAM_SIZE
+ }
+};
+
+const struct hal_flash *
+bsp_flash_dev(uint8_t id)
+{
+ /*
+ * Internal flash mapped to id 0.
+ */
+ if (id != 0) {
+ return NULL;
+ }
+ return &nrf52k_flash_dev;
+}
+
+const struct bsp_mem_dump *
+bsp_core_dump(int *area_cnt)
+{
+ *area_cnt = sizeof(dump_cfg) / sizeof(dump_cfg[0]);
+ return dump_cfg;
+}
+
+uint16_t
+bsp_get_refmv(void *cfgdata)
+{
+ return (2800);
+}
+
+int
+hal_bsp_power_state(int state)
+{
+ return (0);
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/src/libc_stubs.c
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/src/libc_stubs.c b/hw/bsp/rb-nano2/src/libc_stubs.c
new file mode 100644
index 0000000..b1b6b8b
--- /dev/null
+++ b/hw/bsp/rb-nano2/src/libc_stubs.c
@@ -0,0 +1,84 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <hal/hal_system.h>
+#include <hal/hal_bsp.h>
+
+int _close(int fd);
+int _fstat(int fd, void *s);
+void _exit(int s);
+int _kill(int pid, int sig);
+int _write(int fd, void *b, int nb);
+int _isatty(int c);
+int _lseek(int fd, int off, int w);
+int _read(int fd, void *b, int nb);
+int _getpid(void);
+
+int
+_close(int fd)
+{
+ return -1;
+}
+
+int
+_fstat(int fd, void *s)
+{
+ return -1;
+}
+
+
+void
+_exit(int s)
+{
+ system_reset();
+}
+
+int
+_kill(int pid, int sig)
+{
+ return -1;
+}
+
+int
+_write(int fd, void *b, int nb)
+{
+ return -1;
+}
+
+int
+_isatty(int c)
+{
+ return -1;
+}
+
+int
+_lseek(int fd, int off, int w)
+{
+ return -1;
+}
+
+int
+_read(int fd, void *b, int nb)
+{
+ return -1;
+}
+
+int
+_getpid(void) {
+ return -1;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/src/os_bsp.c b/hw/bsp/rb-nano2/src/os_bsp.c
new file mode 100644
index 0000000..1395116
--- /dev/null
+++ b/hw/bsp/rb-nano2/src/os_bsp.c
@@ -0,0 +1,72 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdint.h>
+#include "os/os_cputime.h"
+#include "syscfg/syscfg.h"
+#include "sysflash/sysflash.h"
+#include "flash_map/flash_map.h"
+#include "hal/hal_bsp.h"
+#include "hal/hal_flash.h"
+#include "hal/hal_spi.h"
+#include "hal/hal_watchdog.h"
+#include "mcu/nrf52_hal.h"
+#include "uart/uart.h"
+#include "uart_hal/uart_hal.h"
+#include "os/os_dev.h"
+#include "bsp.h"
+
+#if MYNEWT_VAL(SPI_MASTER)
+#include "nrf_drv_spi.h"
+#endif
+#if MYNEWT_VAL(SPI_SLAVE)
+#include "nrf_drv_spis.h"
+#endif
+#include "nrf_drv_config.h"
+#include "app_util_platform.h"
+#include "nrf.h"
+#include "app_error.h"
+#include "nrf_drv_saadc.h"
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+static const struct nrf52_uart_cfg os_bsp_uart0_cfg = {
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+};
+#endif
+
+void
+bsp_init(void)
+{
+ int rc;
+
+ /* Set cputime to count at 1 usec increments */
+ rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
+ assert(rc == 0);
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
+ assert(rc == 0);
+#endif
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/src/sbrk.c
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/src/sbrk.c b/hw/bsp/rb-nano2/src/sbrk.c
new file mode 100644
index 0000000..242f11b
--- /dev/null
+++ b/hw/bsp/rb-nano2/src/sbrk.c
@@ -0,0 +1,59 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <hal/hal_bsp.h>
+
+/* put these in the data section so they are not cleared by _start */
+static char *sbrkBase __attribute__ ((section (".data")));
+static char *sbrkLimit __attribute__ ((section (".data")));
+static char *brk __attribute__ ((section (".data")));
+
+void
+_sbrkInit(char *base, char *limit) {
+ sbrkBase = base;
+ sbrkLimit = limit;
+ brk = base;
+}
+
+void *
+_sbrk(int incr)
+{
+ void *prev_brk;
+
+ if (incr < 0) {
+ /* Returning memory to the heap. */
+ incr = -incr;
+ if (brk - incr < sbrkBase) {
+ prev_brk = (void *)-1;
+ } else {
+ prev_brk = brk;
+ brk -= incr;
+ }
+ } else {
+ /* Allocating memory from the heap. */
+ if (sbrkLimit - brk >= incr) {
+ prev_brk = brk;
+ brk += incr;
+ } else {
+ prev_brk = (void *)-1;
+ }
+ }
+
+ return prev_brk;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/src/system_nrf52.c
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/src/system_nrf52.c b/hw/bsp/rb-nano2/src/system_nrf52.c
new file mode 100644
index 0000000..86af900
--- /dev/null
+++ b/hw/bsp/rb-nano2/src/system_nrf52.c
@@ -0,0 +1,183 @@
+/* Copyright (c) 2015, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "bsp/cmsis_nvic.h"
+#include "nrf.h"
+#include "system_nrf52.h"
+
+/*lint ++flb "Enter library region" */
+
+#define __SYSTEM_CLOCK_16M (16000000UL)
+#define __SYSTEM_CLOCK_64M (64000000UL)
+
+static bool ftpan_32(void);
+static bool ftpan_37(void);
+static bool ftpan_36(void);
+
+
+#if defined ( __CC_ARM )
+ uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
+#elif defined ( __ICCARM__ )
+ __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
+#elif defined ( __GNUC__ )
+ uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
+#endif
+
+void SystemCoreClockUpdate(void)
+{
+ SystemCoreClock = __SYSTEM_CLOCK_64M;
+}
+
+void SystemInit(void)
+{
+ /* Workaround for FTPAN-32 "DIF: Debug session automatically enables TracePort pins" found at Product Anomaly document
+ for your device located at https://www.nordicsemi.com/ */
+ if (ftpan_32()){
+ CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
+ }
+
+ /* Workaround for FTPAN-37 "AMLI: EasyDMA is slow with Radio, ECB, AAR and CCM." found at Product Anomaly document
+ for your device located at https://www.nordicsemi.com/ */
+ if (ftpan_37()){
+ *(volatile uint32_t *)0x400005A0 = 0x3;
+ }
+
+ /* Workaround for FTPAN-36 "CLOCK: Some registers are not reset when expected." found at Product Anomaly document
+ for your device located at https://www.nordicsemi.com/ */
+ if (ftpan_36()){
+ NRF_CLOCK->EVENTS_DONE = 0;
+ NRF_CLOCK->EVENTS_CTTO = 0;
+ }
+
+ /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
+ * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
+ * operations are not used in your code. */
+ #if (__FPU_USED == 1)
+ SCB->CPACR |= (3UL << 20) | (3UL << 22);
+ __DSB();
+ __ISB();
+ #endif
+
+ /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
+ two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
+ normal GPIOs. */
+ #if defined (CONFIG_NFCT_PINS_AS_GPIOS)
+ if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NVIC_SystemReset();
+ }
+ #endif
+
+ /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
+ defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
+ reserved for PinReset and not available as normal GPIO. */
+ #if defined (CONFIG_GPIO_AS_PINRESET)
+ if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+ ((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_UICR->PSELRESET[0] = 21;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_UICR->PSELRESET[1] = 21;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NVIC_SystemReset();
+ }
+ #endif
+
+ /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
+ Specification to see which one). */
+ #if defined (ENABLE_SWO)
+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+ NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+ #endif
+
+ /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
+ Specification to see which ones). */
+ #if defined (ENABLE_TRACE)
+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+ NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+ #endif
+
+ SystemCoreClockUpdate();
+
+ NVIC_Relocate();
+}
+
+static bool ftpan_32(void)
+{
+ if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+ {
+ if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+ {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static bool ftpan_37(void)
+{
+ if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+ {
+ if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+ {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static bool ftpan_36(void)
+{
+ if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+ {
+ if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+ {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+
+
+/*lint --flb "Leave library region" */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c117b7b2/hw/bsp/rb-nano2/syscfg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/syscfg.yml b/hw/bsp/rb-nano2/syscfg.yml
new file mode 100644
index 0000000..f79771e
--- /dev/null
+++ b/hw/bsp/rb-nano2/syscfg.yml
@@ -0,0 +1,90 @@
+# Package: hw/bsp/rb-nano2
+
+syscfg.defs:
+ BSP_NRF52:
+ description: 'TBD'
+ value: 1
+
+ CLOCK_FREQ:
+ description: 'TBD'
+ value: 1000000
+
+ OS_CPUTIME_TIMER_NUM:
+ description: 'Timer to use for cputime'
+ value: 0
+
+ XTAL_32768:
+ description: 'TBD'
+ value: 1
+ ADC_0:
+ description: 'TBD'
+ value: 0
+ ADC_0_RESOLUTION:
+ description: 'TBD'
+ value: 'SAADC_CONFIG_RESOLUTION'
+ ADC_0_OVERSAMPLE:
+ description: 'TBD'
+ value: 'SAADC_CONFIG_OVERSAMPLE'
+ ADC_0_INTERRUPT_PRIORITY:
+ description: 'TBD'
+ value: 'SAADC_CONFIG_IRQ_PRIORITY'
+
+ UART_0:
+ description: 'TBD'
+ value: 1
+ UART_0_PIN_TX:
+ description: 'TBD'
+ value: 29
+ UART_0_PIN_RX:
+ description: 'TBD'
+ value: 30
+ UART_0_PIN_RTS:
+ description: 'TBD'
+ value: 2
+ UART_0_PIN_CTS:
+ description: 'TBD'
+ value: 28
+
+ SPI_MASTER:
+ description: 'TBD'
+ value: 0
+ SPI_SLAVE:
+ description: 'TBD'
+ value: 0
+
+ TIMER_0:
+ description: 'NRF52 Timer 0'
+ value: 1
+ TIMER_0_INTERRUPT_PRIORITY:
+ description: 'TBD'
+ value: '((1 << __NVIC_PRIO_BITS) - 1)'
+ TIMER_1:
+ description: 'NRF52 Timer 1'
+ value: 0
+ TIMER_1_INTERRUPT_PRIORITY:
+ description: 'TBD'
+ value: '((1 << __NVIC_PRIO_BITS) - 1)'
+ TIMER_2:
+ description: 'NRF52 Timer 2'
+ value: 0
+ TIMER_2_INTERRUPT_PRIORITY:
+ description: 'TBD'
+ value: '((1 << __NVIC_PRIO_BITS) - 1)'
+ TIMER_3:
+ description: 'NRF52 Timer 3'
+ value: 0
+ TIMER_3_INTERRUPT_PRIORITY:
+ description: 'TBD'
+ value: '((1 << __NVIC_PRIO_BITS) - 1)'
+ TIMER_4:
+ description: 'NRF52 Timer 4'
+ value: 0
+ TIMER_4_INTERRUPT_PRIORITY:
+ description: 'TBD'
+ value: '((1 << __NVIC_PRIO_BITS) - 1)'
+
+syscfg.vals:
+ CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
+ REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG
+ NFFS_FLASH_AREA: FLASH_AREA_REBOOT_LOG
+ COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1