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Posted to commits@nuttx.apache.org by ag...@apache.org on 2020/07/15 10:25:41 UTC
[incubator-nuttx] branch master updated: Add initial support for
the QuickLogic EOS S3
This is an automated email from the ASF dual-hosted git repository.
aguettouche pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new aef6f4a Add initial support for the QuickLogic EOS S3
aef6f4a is described below
commit aef6f4ae09029907b587cb7961baf01d5228d932
Author: Brennan Ashton <ba...@brennanashton.com>
AuthorDate: Wed Jun 24 22:22:08 2020 -0700
Add initial support for the QuickLogic EOS S3
The QuickFeather board added as an initial target.
These featrues are minimally implemented:
* Clock Configuration -- All clocking registers are defined and
configuration is used to setup the HSO, M4 Core, and M4 Perif
clocks. Additionally some clock debugging is stubbed for
bringing out clock paths to IO pins.
* UART -- The lowputc as well as the serial driver is implemnted
for the single UART device. Currently the configuration is
hard coded, but uses the proper interfaces to later fill in.
* SysTick -- The system tick timer is implemented and clocking
properly. Tickless mode is not yet implemented.
* Interrupts -- The interrupt system is implemented and verified
using the UART and SysTick systems.
* GPIO -- GPIO and IOMUX systems are defined and implemented.
This is verified using the UART as well as the Arch LED
system. The GPIO interupt system is stubbed out but not
implemented.
* Arch LEDS -- The blue LED as part of the RGB LED is configured
and attached to the Arch LED system. This indicates the device
coming online as well as when a hardfault is triggered.
Applications and Testing:
* There is a nsh configuration implemented that includes debug
features as well as the ostest, getprime, and mem test.
All of these have been run and verified.
Signed-off-by: Brennan Ashton <ba...@brennanashton.com>
---
arch/arm/Kconfig | 13 +
arch/arm/include/eoss3/chip.h | 43 ++
arch/arm/include/eoss3/irq.h | 141 +++++
arch/arm/src/eoss3/Kconfig | 16 +
arch/arm/src/eoss3/Make.defs | 70 +++
arch/arm/src/eoss3/chip.h | 35 ++
arch/arm/src/eoss3/eoss3.h | 41 ++
arch/arm/src/eoss3/eoss3_clockconfig.c | 130 +++++
arch/arm/src/eoss3/eoss3_clockconfig.h | 64 +++
arch/arm/src/eoss3/eoss3_gpio.c | 191 +++++++
arch/arm/src/eoss3/eoss3_gpio.h | 275 +++++++++
arch/arm/src/eoss3/eoss3_idle.c | 73 +++
arch/arm/src/eoss3/eoss3_irq.c | 559 ++++++++++++++++++
arch/arm/src/eoss3/eoss3_lowputc.c | 130 +++++
arch/arm/src/eoss3/eoss3_lowputc.h | 63 ++
arch/arm/src/eoss3/eoss3_serial.c | 636 +++++++++++++++++++++
arch/arm/src/eoss3/eoss3_start.c | 350 ++++++++++++
arch/arm/src/eoss3/eoss3_start.h | 62 ++
arch/arm/src/eoss3/eoss3_timerisr.c | 129 +++++
arch/arm/src/eoss3/hardware/eoss3_clock.h | 173 ++++++
arch/arm/src/eoss3/hardware/eoss3_intr.h | 182 ++++++
arch/arm/src/eoss3/hardware/eoss3_iomux.h | 321 +++++++++++
arch/arm/src/eoss3/hardware/eoss3_memorymap.h | 73 +++
arch/arm/src/eoss3/hardware/eoss3_uart.h | 169 ++++++
boards/Kconfig | 11 +
boards/arm/eoss3/quickfeather/Kconfig | 8 +
boards/arm/eoss3/quickfeather/README.txt | 0
.../arm/eoss3/quickfeather/configs/nsh/defconfig | 48 ++
boards/arm/eoss3/quickfeather/include/board.h | 66 +++
boards/arm/eoss3/quickfeather/scripts/Make.defs | 95 +++
boards/arm/eoss3/quickfeather/scripts/ld.script | 105 ++++
.../arm/eoss3/quickfeather/scripts/quicknuttx.resc | 20 +
boards/arm/eoss3/quickfeather/src/Makefile | 31 +
boards/arm/eoss3/quickfeather/src/eoss3_appinit.c | 66 +++
boards/arm/eoss3/quickfeather/src/eoss3_autoleds.c | 143 +++++
boards/arm/eoss3/quickfeather/src/eoss3_boot.c | 83 +++
boards/arm/eoss3/quickfeather/src/eoss3_bringup.c | 59 ++
boards/arm/eoss3/quickfeather/src/quickfeather.h | 79 +++
38 files changed, 4753 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c43f252..b7a5e28 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -60,6 +60,15 @@ config ARCH_CHIP_EFM32
---help---
Energy Micro EFM32 microcontrollers (ARM Cortex-M).
+config ARCH_CHIP_EOSS3
+ bool "QuickLogic EOS S3"
+ select ARCH_CORTEXM4
+ select ARCH_HAVE_MPU
+ select ARM_HAVE_MPU_UNIFIED
+ select ARCH_HAVE_FPU
+ ---help---
+ QuickLogic EOS S3 (ARM Cortex-M4)
+
config ARCH_CHIP_IMX1
bool "NXP/Freescale iMX.1"
select ARCH_ARM920T
@@ -703,6 +712,7 @@ config ARCH_CHIP
default "c5471" if ARCH_CHIP_C5471
default "dm320" if ARCH_CHIP_DM320
default "efm32" if ARCH_CHIP_EFM32
+ default "eoss3" if ARCH_CHIP_EOSS3
default "imx1" if ARCH_CHIP_IMX1
default "imx6" if ARCH_CHIP_IMX6
default "imxrt" if ARCH_CHIP_IMXRT
@@ -906,6 +916,9 @@ endif
if ARCH_CHIP_EFM32
source arch/arm/src/efm32/Kconfig
endif
+if ARCH_CHIP_EOSS3
+source arch/arm/src/eoss3/Kconfig
+endif
if ARCH_CHIP_IMX1
source arch/arm/src/imx1/Kconfig
endif
diff --git a/arch/arm/include/eoss3/chip.h b/arch/arm/include/eoss3/chip.h
new file mode 100644
index 0000000..d159613
--- /dev/null
+++ b/arch/arm/include/eoss3/chip.h
@@ -0,0 +1,43 @@
+/****************************************************************************
+ * arch/arm/src/eoss3/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_EFM32_CHIP_H
+#define __ARCH_ARM_INCLUDE_EFM32_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* EOS S3 Support 8 Levels of priority.
+ * May need to revisit the masking here
+ */
+
+#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* Bits [7:5] set in min priority */
+#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
+#define NVIC_SYSH_PRIORITY_STEP 0x20 /* Three bits of interrupt pri used */
+
+#endif /* __ARCH_ARM_INCLUDE_EFM32_CHIP_H */
\ No newline at end of file
diff --git a/arch/arm/include/eoss3/irq.h b/arch/arm/include/eoss3/irq.h
new file mode 100644
index 0000000..133ab48
--- /dev/null
+++ b/arch/arm/include/eoss3/irq.h
@@ -0,0 +1,141 @@
+/****************************************************************************
+ * arch/arm/include/eoss3/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_EOSS3_IRQ_H
+#define __ARCH_ARM_INCLUDE_EOSS3_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/eoss3/chip.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Common Processor Exceptions (vectors 0-15) */
+
+#define EOSS3_IRQ_RESERVED (0) /* Reserved vector */
+ /* Vector 0: Reset stack pointer val */
+ /* Vector 1: Reset (unused) */
+#define EOSS3_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt */
+#define EOSS3_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
+#define EOSS3_IRQ_MEMFAULT (4) /* Vector 4: Memory management */
+#define EOSS3_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
+#define EOSS3_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
+ /* Vectors 7-10: Reserved */
+#define EOSS3_IRQ_SVCALL (11) /* Vector 11: SVC call */
+#define EOSS3_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
+ /* Vector 13: Reserved */
+#define EOSS3_IRQ_PENDSV (14) /* Vector 14: Pendable sys srv req */
+#define EOSS3_IRQ_SYSTICK (15) /* Vector 15: System tick */
+#define EOSS3_IRQ_EXTINT (16) /* Vector num of first ext interrupt */
+
+/* Chip-Specific External interrupts */
+
+#define EOSS3_IRQ_SW2 (EOSS3_IRQ_EXTINT + 0)
+#define EOSS3_IRQ_SW1 (EOSS3_IRQ_EXTINT + 1)
+#define EOSS3_IRQ_RSV1 (EOSS3_IRQ_EXTINT + 2)
+#define EOSS3_IRQ_FFE0MSG (EOSS3_IRQ_EXTINT + 3)
+#define EOSS3_IRQ_FBMSG (EOSS3_IRQ_EXTINT + 4)
+#define EOSS3_IRQ_GPIO (EOSS3_IRQ_EXTINT + 5)
+#define EOSS3_IRQ_SRAM_SLEEP (EOSS3_IRQ_EXTINT + 6)
+#define EOSS3_IRQ_UART (EOSS3_IRQ_EXTINT + 7)
+#define EOSS3_IRQ_TIMER (EOSS3_IRQ_EXTINT + 8)
+#define EOSS3_IRQ_CPUWD_INT (EOSS3_IRQ_EXTINT + 9)
+#define EOSS3_IRQ_CPUWD_RST (EOSS3_IRQ_EXTINT + 0)
+#define EOSS3_IRQ_BUS_TIMEOUT (EOSS3_IRQ_EXTINT + 11)
+#define EOSS3_IRQ_FPU (EOSS3_IRQ_EXTINT + 12)
+#define EOSS3_IRQ_PKFB (EOSS3_IRQ_EXTINT + 13)
+#define EOSS3_IRQ_RSV_I2S (EOSS3_IRQ_EXTINT + 14)
+#define EOSS3_IRQ_RSV_AUDIO (EOSS3_IRQ_EXTINT + 15)
+#define EOSS3_IRQ_SPI_MS (EOSS3_IRQ_EXTINT + 16)
+#define EOSS3_IRQ_CFG_DMA (EOSS3_IRQ_EXTINT + 17)
+#define EOSS3_IRQ_PMU_TIMER (EOSS3_IRQ_EXTINT + 18)
+#define EOSS3_IRQ_ADC_DONE (EOSS3_IRQ_EXTINT + 19)
+#define EOSS3_IRQ_RTC_ALARM (EOSS3_IRQ_EXTINT + 20)
+#define EOSS3_IRQ_RESET_INT (EOSS3_IRQ_EXTINT + 21)
+#define EOSS3_IRQ_FFE0 (EOSS3_IRQ_EXTINT + 22)
+#define EOSS3_IRQ_FFE_WDT (EOSS3_IRQ_EXTINT + 23)
+#define EOSS3_IRQ_AP_BOOT (EOSS3_IRQ_EXTINT + 24)
+#define EOSS3_IRQ_LDO30_PG (EOSS3_IRQ_EXTINT + 25)
+#define EOSS3_IRQ_LDO50_PG (EOSS3_IRQ_EXTINT + 26)
+#define EOSS3_IRQ_SRAM_TO (EOSS3_IRQ_EXTINT + 27)
+#define EOSS3_IRQ_LPSD (EOSS3_IRQ_EXTINT + 28)
+#define EOSS3_IRQ_DMIC (EOSS3_IRQ_EXTINT + 29)
+#define EOSS3_IRQ_RSV2 (EOSS3_IRQ_EXTINT + 20)
+#define EOSS3_IRQ_SDMA_DONE1 (EOSS3_IRQ_EXTINT + 31)
+#define EOSS3_IRQ_SDMA_DONE2 (EOSS3_IRQ_EXTINT + 32)
+#define EOSS3_IRQ_SDMA_DONE3 (EOSS3_IRQ_EXTINT + 33)
+#define EOSS3_IRQ_SDMA_DONE4 (EOSS3_IRQ_EXTINT + 34)
+#define EOSS3_IRQ_SDMA_DONE5 (EOSS3_IRQ_EXTINT + 35)
+#define EOSS3_IRQ_SDMA_DONE6 (EOSS3_IRQ_EXTINT + 36)
+#define EOSS3_IRQ_SDMA_DONE7 (EOSS3_IRQ_EXTINT + 37)
+#define EOSS3_IRQ_SDMA_DONE8 (EOSS3_IRQ_EXTINT + 38)
+#define EOSS3_IRQ_SDMA_DONE9 (EOSS3_IRQ_EXTINT + 39)
+#define EOSS3_IRQ_SDMA_DONE10 (EOSS3_IRQ_EXTINT + 40)
+#define EOSS3_IRQ_SDMA_DONE11 (EOSS3_IRQ_EXTINT + 41)
+#define EOSS3_IRQ_AP_PDM_CLK_ON (EOSS3_IRQ_EXTINT + 42)
+#define EOSS3_IRQ_AP_PDM_CLK_OFF (EOSS3_IRQ_EXTINT + 43)
+#define EOSS3_IRQ_DMAC0_BLK_DONE (EOSS3_IRQ_EXTINT + 44)
+#define EOSS3_IRQ_DMAC0_BUF_DONE (EOSS3_IRQ_EXTINT + 45)
+#define EOSS3_IRQ_DMAC1_BLK_DONE (EOSS3_IRQ_EXTINT + 46)
+#define EOSS3_IRQ_DMAC1_BUF_DONE (EOSS3_IRQ_EXTINT + 47)
+#define EOSS3_IRQ_SDMA_DONE0 (EOSS3_IRQ_EXTINT + 48)
+#define EOSS3_IRQ_SDMA_ERR (EOSS3_IRQ_EXTINT + 49)
+#define EOSS3_IRQ_I2S_SLV (EOSS3_IRQ_EXTINT + 50)
+#define EOSS3_IRQ_LPSD_VOICE_OFF (EOSS3_IRQ_EXTINT + 51)
+#define EOSS3_IRQ_DMIC_VOICE_OFF (EOSS3_IRQ_EXTINT + 52)
+
+#define EOSS3_NEXTINT (53)
+#define EOSS3_IRQ_NVECTORS (EOSS3_IRQ_EXTINT + EOSS3_NEXTINT)
+#define EOSS3_IRQ_INTERRUPTS EOSS3_IRQ_EXTINT
+#define NR_IRQS EOSS3_IRQ_NVECTORS
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* #define __ARCH_ARM_INCLUDE_EOSS3_IRQ_H */
diff --git a/arch/arm/src/eoss3/Kconfig b/arch/arm/src/eoss3/Kconfig
new file mode 100644
index 0000000..800e020
--- /dev/null
+++ b/arch/arm/src/eoss3/Kconfig
@@ -0,0 +1,16 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+comment "EOS S3 Configuration Options"
+
+menu "EOS S3 Peripheral Support"
+
+config EOSS3_UART
+ bool "UART"
+ default n
+ select UART_SERIALDRIVER
+ select SCHED_HPWORK
+
+endmenu
diff --git a/arch/arm/src/eoss3/Make.defs b/arch/arm/src/eoss3/Make.defs
new file mode 100644
index 0000000..c87c37f
--- /dev/null
+++ b/arch/arm/src/eoss3/Make.defs
@@ -0,0 +1,70 @@
+############################################################################
+# arch/arm/src/eoss3/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S arm_switchcontext.S
+CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S
+
+ifeq ($(CONFIG_ARCH_SETJMP_H),y)
+ifeq ($(CONFIG_ARCH_TOOLCHAIN_GNU),y)
+CMN_ASRCS += arm_setjmp.S
+endif
+endif
+
+CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c arm_copyfullstate.c
+CMN_CSRCS += arm_createstack.c arm_doirq.c arm_exit.c arm_hardfault.c
+CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
+CMN_CSRCS += arm_itm.c arm_mdelay.c arm_memfault.c arm_modifyreg8.c
+CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasepending.c
+CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_schedulesigaction.c
+CMN_CSRCS += arm_sigdeliver.c arm_stackframe.c arm_svcall.c arm_systemreset.c
+CMN_CSRCS += arm_trigger_irq.c arm_udelay.c arm_unblocktask.c arm_usestack.c arm_vfork.c
+
+ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
+CMN_ASRCS += arm_lazyexception.S
+else
+CMN_ASRCS += arm_exception.S
+endif
+CMN_CSRCS += arm_vectors.c
+
+ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
+CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
+endif
+
+ifeq ($(CONFIG_BUILD_PROTECTED),y)
+CMN_CSRCS += arm_task_start.c arm_pthread_start.c
+CMN_CSRCS += arm_signal_dispatch.c
+CMN_UASRCS += arm_signal_handler.S
+endif
+
+ifeq ($(CONFIG_STACK_COLORATION),y)
+CMN_CSRCS += arm_checkstack.c
+endif
+
+CHIP_CSRCS = eoss3_start.c eoss3_gpio.c eoss3_lowputc.c eoss3_clockconfig.c
+CHIP_CSRCS += eoss3_irq.c
+CHIP_CSRCS += eoss3_serial.c
+
+ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
+CHIP_CSRCS += eoss3_idle.c
+endif
+
+ifneq ($(CONFIG_SCHED_TICKLESS),y)
+CHIP_CSRCS += eoss3_timerisr.c
+endif
diff --git a/arch/arm/src/eoss3/chip.h b/arch/arm/src/eoss3/chip.h
new file mode 100644
index 0000000..6e5cbc6
--- /dev/null
+++ b/arch/arm/src/eoss3/chip.h
@@ -0,0 +1,35 @@
+/****************************************************************************
+ * arch/arm/src/eoss3/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_EOSS3_CHIP_H
+#define __ARCH_ARM_SRC_EOSS3_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/eoss3/chip.h>
+
+#define ARMV7M_PERIPHERAL_INTERRUPTS 64
+
+#include "hardware/eoss3_memorymap.h"
+
+#endif /* __ARCH_ARM_SRC_EOSS3_CHIP_H */
diff --git a/arch/arm/src/eoss3/eoss3.h b/arch/arm/src/eoss3/eoss3.h
new file mode 100644
index 0000000..d141ac7
--- /dev/null
+++ b/arch/arm/src/eoss3/eoss3.h
@@ -0,0 +1,41 @@
+/****************************************************************************
+ * arch/arm/src/eoss3/eoss3.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_EOSS3_EOSS3_H
+#define __ARCH_ARM_SRC_EOSS3_EOSS3_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "arm_internal.h"
+
+/* Peripherals **************************************************************/
+
+#include "chip.h"
+#include "eoss3_lowputc.h"
+#include "eoss3_clockconfig.h"
+
+#endif /* __ARCH_ARM_SRC_EOSS3_EOSS3_H */
diff --git a/arch/arm/src/eoss3/eoss3_clockconfig.c b/arch/arm/src/eoss3/eoss3_clockconfig.c
new file mode 100644
index 0000000..b4ad8eb
--- /dev/null
+++ b/arch/arm/src/eoss3/eoss3_clockconfig.c
@@ -0,0 +1,130 @@
+/****************************************************************************
+ * arch/arm/src/eoss3/eoss3_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <arch/board/board.h>
+
+#include "arm_internal.h"
+#include "arm_arch.h"
+
+#include "chip.h"
+
+#include "eoss3.h"
+#include "hardware/eoss3_clock.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: eoss3_clockconfig
+ *
+ * Description:
+ * Called to initialize the EOS S3. This does whatever setup is needed to
+ * put the SoC in a usable state. This includes the initialization of
+ * clocking using the settings in board.h.
+ *
+ ****************************************************************************/
+
+void eoss3_clockconfig(void)
+{
+ uint32_t clk_cfg;
+ uint8_t check_cnt;
+
+ /* Enable the OSC clock source */
+
+ putreg32(AIP_OSC_CTRL_0_EN, EOSS3_AIP_OSC_CTRL_0);
+
+ /* Set the frequency 79.79MHz (Update to use BOARD clock define */
+
+ clk_cfg = getreg32(EOSS3_AIP_OSC_CTRL_1);
+ clk_cfg &= ~AIP_OSC_CTRL_1_PROG_MASK;
+ clk_cfg |= 0x980 << AIP_OSC_CTRL_1_PROG_SHIFT; /* (prog + 3) ∗ 32,768Hz */
+ putreg32(clk_cfg, EOSS3_AIP_OSC_CTRL_1);
+
+ /* Wait for the lock, we need to wait for lock twice
+ * This can be disabled for the emulator to function since it does not
+ * implement the lock register and it will forever spin here.
+ */
+
+#if 1
+ for (check_cnt = 0; check_cnt < 2; check_cnt++)
+ {
+ while ((getreg32(EOSS3_AIP_OSC_STA_0) & AIP_OSC_STA_0_LOCK) == 0);
+ }
+#endif
+
+ /* Configure the M4 Clock. Directly connect to HFCLK for 79.79MHz */
+
+ putreg32(0, EOSS3_CLK_CONTROL_A_1); /* Use OSC */
+ putreg32(0, EOSS3_CLK_CONTROL_A_0); /* Disable, Output Directly */
+ putreg32(0x5f, EOSS3_CLK_C10_GATE); /* Enable Gates [6, 4:0] */
+
+ /* Need to setup M4 peripheral clocks (UART, Timer, Watchdog)
+ * CLK_SWITCH_FOR_D = 0
+ * CLK_Control_D_0 = 0x206 (divide 8 [8-2=6] + enable)
+ * MISC_LOCK_KEY_CTRL = 0x1acce551 (re-lock by writing any other val)
+ * C11_CLK_GATE = 1
+ */
+
+ putreg32(0, EOSS3_CLK_SWITCH_FOR_D);
+ putreg32((8 - 2) | (1 << 9), EOSS3_CLK_CONTROL_D_0);
+ putreg32(MISC_LOCK_KEY_CTRL_UNLOCK, MISC_LOCK_KEY_CTRL);
+ putreg32(1, EOSS3_CLK_C11_GATE);
+
+#if 0
+ /* Enable clock debug logic C11 is brought out to pad 13 */
+
+ putreg32(0, 0x40005004);
+ putreg32(1, 0x40005008);
+ putreg32(2, 0x40004c34);
+ putreg32(8, 0x40004108);
+#endif
+}
diff --git a/arch/arm/src/eoss3/eoss3_clockconfig.h b/arch/arm/src/eoss3/eoss3_clockconfig.h
new file mode 100644
index 0000000..0bc6245
--- /dev/null
+++ b/arch/arm/src/eoss3/eoss3_clockconfig.h
@@ -0,0 +1,64 @@
+/****************************************************************************
+ * arch/arm/src/eoss3/eoss3_lowputc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_EOSS3_EOSS3_CLOCKCONFIG_H
+#define __ARCH_ARM_SRC_EOSS3_EOSS3_CLOCKCONFIG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: eoss3_clockconfig
+ *
+ * Description:
+ * Called to initialize the EOS S3. This does whatever setup is needed to
+ * put the SoC in a usable state. This includes the initialization of
+ * clocking using the settings in board.h.
+ *
+ ****************************************************************************/
+
+void eoss3_clockconfig(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_EOSS3_EOSS3_CLOCKCONFIG_H */
diff --git a/arch/arm/src/eoss3/eoss3_gpio.c b/arch/arm/src/eoss3/eoss3_gpio.c
new file mode 100644
index 0000000..cb25c72
--- /dev/null
+++ b/arch/arm/src/eoss3/eoss3_gpio.c
@@ -0,0 +1,191 @@
+/****************************************************************************
+ * arch/arm/src/eoss3/eoss3_gpio.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <arch/board/board.h>
+#include <nuttx/irq.h>
+
+#include "arm_internal.h"
+#include "arm_arch.h"
+
+#include "chip.h"
+
+#include "eoss3.h"
+#include "eoss3_gpio.h"
+#include "hardware/eoss3_iomux.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: eoss3_configgpio
+ *
+ * Description:
+ * Configure a PIO pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+int eoss3_configgpio(gpio_pinset_t cfgset)
+{
+ uint16_t pad = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
+ uint16_t ctrl = (cfgset & GPIO_CTRL_MASK) >> GPIO_CTRL_SHIFT;
+ uint16_t input = (cfgset & GPIO_INPUT_SEL_MASK) >> GPIO_INPUT_SEL_SHIFT;
+ uint8_t sel = input & EOSS3_PAD_SEL_VAL_MASK;
+ uint16_t sel_idx = \
+ (input & EOSS3_PAD_SEL_IDX_MASK) >> EOSS3_PAD_SEL_IDX_SHIFT;
+
+ irqstate_t flags = enter_critical_section();
+
+ /* Check select index, if it is 0 we are not working with an input */
+
+ if (sel_idx != 0)
+ {
+ putreg32(sel, EOSS3_PAD_SEL(sel_idx));
+ }
+
+ /* Check if we are enabling GPIO Register access */
+
+ if (cfgset & GPIO_REG_EN_MASK)
+ {
+ uint8_t iobit = (cfgset & GPIO_REG_BIT_MASK) >> GPIO_REG_BIT_SHIFT;
+ if (pad >= IO_REG_START_HI_PAD)
+ {
+ putreg32(
+ getreg32(EOSS3_IO_REG_SEL) | (1 << iobit),
+ EOSS3_IO_REG_SEL);
+ }
+ else
+ {
+ putreg32(
+ getreg32(EOSS3_IO_REG_SEL) & ~(1 << iobit),
+ EOSS3_IO_REG_SEL);
+ }
+ }
+
+ putreg32(ctrl, EOSS3_PAD_X_CTRL(pad));
+ leave_critical_section(flags);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: eoss3_unconfiggpio
+ *
+ * Description:
+ * unConfigure a PIO pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+int eoss3_unconfiggpio(gpio_pinset_t cfgset)
+{
+ return OK;
+}
+
+/****************************************************************************
+ * Name: eoss3_gpiowrite
+ *
+ * Description:
+ * Write one or zero to the selected PIO pin
+ *
+ ****************************************************************************/
+
+void eoss3_gpiowrite(gpio_pinset_t cfgset, bool value)
+{
+ uint8_t iobit = (cfgset & GPIO_REG_BIT_MASK) >> GPIO_REG_BIT_SHIFT;
+ if (cfgset & GPIO_REG_EN_MASK)
+ {
+ irqstate_t flags = enter_critical_section();
+ if (value)
+ {
+ putreg32(
+ getreg32(EOSS3_MISC_IO_OUTPUT) | (1 << iobit),
+ EOSS3_MISC_IO_OUTPUT);
+ }
+ else
+ {
+ putreg32(
+ getreg32(EOSS3_MISC_IO_OUTPUT) & ~(1 << iobit),
+ EOSS3_MISC_IO_OUTPUT);
+ }
+
+ leave_critical_section(flags);
+ }
+}
+
+/****************************************************************************
+ * Name: eoss3_gpioread
+ *
+ * Description:
+ * Read one or zero from the selected PIO pin
+ *
+ ****************************************************************************/
+
+bool eoss3_gpioread(gpio_pinset_t cfgset)
+{
+ uint8_t iobit = (cfgset & GPIO_REG_BIT_MASK) >> GPIO_REG_BIT_SHIFT;
+ return ((getreg32(EOSS3_MISC_IO_INPUT) & (1 << iobit)) != 0);
+}
+
+/****************************************************************************
+ * Function: eoss3_dumpgpio
+ *
+ * Description:
+ * Dump all PIO registers associated with the base address of the provided
+ * pinset.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_GPIO_INFO
+int eoss3_dumpgpio(uint32_t pinset, const char *msg)
+{
+#warning Missing logic
+ return -ENOSYS;
+}
+#endif
diff --git a/arch/arm/src/eoss3/eoss3_gpio.h b/arch/arm/src/eoss3/eoss3_gpio.h
new file mode 100644
index 0000000..d822cde
--- /dev/null
+++ b/arch/arm/src/eoss3/eoss3_gpio.h
@@ -0,0 +1,275 @@
+/****************************************************************************
+ * arch/arm/src/eoss3/eoss3_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_EOSS3_EOSS3_GPIO_H
+#define __ARCH_ARM_SRC_EOSS3_EOSS3_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "chip.h"
+#include "hardware/eoss3_iomux.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* pinset encoding
+ * 3322 2222 2222 1111 1111 1100 0000 0000
+ * 1098 7654 3210 9876 5432 1098 7654 3210
+ * GGGE SSSS SSII ICCC CCCC CCCC CCPP PPPP
+ *
+ * G - GPIO Reg Bit
+ * E - GPIO Reg Enable
+ * S - Maps to input select
+ * I - Input Select Register
+ * C - Maps to packed PAD CTRL
+ * P - PAD Number
+ */
+
+#define GPIO_PIN_SHIFT (0) /* Bits 0-5: Pin number: 0-45 */
+#define GPIO_PIN_MASK (0x3f << GPIO_PIN_SHIFT)
+# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
+# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
+# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
+# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
+# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
+# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
+# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
+# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
+# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
+# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
+# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
+# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
+# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
+# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
+# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
+# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
+# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT)
+# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT)
+# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT)
+# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT)
+# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT)
+# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT)
+# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT)
+# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT)
+# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT)
+# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT)
+# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT)
+# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT)
+# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT)
+# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT)
+# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
+# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
+# define GPIO_PIN32 (32 << GPIO_PIN_SHIFT)
+# define GPIO_PIN33 (33 << GPIO_PIN_SHIFT)
+# define GPIO_PIN34 (34 << GPIO_PIN_SHIFT)
+# define GPIO_PIN35 (35 << GPIO_PIN_SHIFT)
+# define GPIO_PIN36 (36 << GPIO_PIN_SHIFT)
+# define GPIO_PIN37 (37 << GPIO_PIN_SHIFT)
+# define GPIO_PIN38 (38 << GPIO_PIN_SHIFT)
+# define GPIO_PIN39 (39 << GPIO_PIN_SHIFT)
+# define GPIO_PIN40 (40 << GPIO_PIN_SHIFT)
+# define GPIO_PIN41 (41 << GPIO_PIN_SHIFT)
+# define GPIO_PIN42 (42 << GPIO_PIN_SHIFT)
+# define GPIO_PIN43 (43 << GPIO_PIN_SHIFT)
+# define GPIO_PIN44 (44 << GPIO_PIN_SHIFT)
+# define GPIO_PIN45 (45 << GPIO_PIN_SHIFT)
+
+#define GPIO_CTRL_SHIFT (6) /* Bits 6-18 */
+#define GPIO_CTRL_MASK (0x1fff << GPIO_CTRL_SHIFT)
+#define GPIO_INPUT_SEL_SHIFT (19) /* Bits 19-27 */
+#define GPIO_INPUT_SEL_MASK (0x1ff << GPIO_INPUT_SEL_SHIFT)
+
+#define GPIO_REG_EN_SHIFT (28)
+#define GPIO_REG_EN_MASK (1 << GPIO_REG_EN_SHIFT)
+
+#define GPIO_REG_BIT_SHIFT (29)
+#define GPIO_REG_BIT_MASK (0x7 << GPIO_REG_BIT_SHIFT)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* Must be big enough to hold the 20-bit encoding */
+
+typedef uint32_t gpio_pinset_t;
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: eoss3_gpioirqinitialize
+ *
+ * Description:
+ * Initialize logic to support a second level of interrupt decoding for
+ * PIO pins.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_EOSS3_GPIO_IRQ
+void eoss3_gpioirqinitialize(void);
+#else
+# define eoss3_gpioirqinitialize()
+#endif
+
+/****************************************************************************
+ * Name: eoss3_configgpio
+ *
+ * Description:
+ * Configure a PIO pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+int eoss3_configgpio(gpio_pinset_t cfgset);
+
+/****************************************************************************
+
+ * Name: eoss3_unconfiggpio
+ *
+ * Description:
+ * UnConfigure a PIO pin based on bit-encoded description of the pin.
+ *
+ ****************************************************************************/
+
+int eoss3_unconfiggpio(gpio_pinset_t cfgset);
+
+/****************************************************************************
+ * Name: eoss3_gpiowrite
+ *
+ * Description:
+ * Write one or zero to the selected PIO pin
+ *
+ ****************************************************************************/
+
+void eoss3_gpiowrite(gpio_pinset_t pinset, bool value);
+
+/****************************************************************************
+ * Name: eoss3_gpioread
+ *
+ * Description:
+ * Read one or zero from the selected PIO pin
+ *
+ ****************************************************************************/
+
+bool eoss3_gpioread(gpio_pinset_t pinset);
+
+/****************************************************************************
+ * Name: eoss3_gpioirq
+ *
+ * Description:
+ * Configure an interrupt for the specified PIO pin.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_EFM32_GPIO_IRQ
+void eoss3_gpioirq(gpio_pinset_t pinset);
+#else
+# define eoss3_gpioirq(pinset)
+#endif
+
+/****************************************************************************
+ * Name: eoss3_gpioirqenable
+ *
+ * Description:
+ * Enable the interrupt for specified PIO IRQ
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_EFM32_GPIO_IRQ
+void eoss3_gpioirqenable(int irq);
+#else
+# define eoss3_gpioirqenable(irq)
+#endif
+
+/****************************************************************************
+ * Name: eoss3_gpioirqdisable
+ *
+ * Description:
+ * Disable the interrupt for specified PIO IRQ
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_EFM32_GPIO_IRQ
+void eoss3_gpioirqdisable(int irq);
+#else
+# define eoss3_gpioirqdisable(irq)
+#endif
+
+/****************************************************************************
+ * Name: eoss3_gpioirqclear
+ *
+ * Description:
+ * clear the interrupt for specified PIO IRQ
+ *
+ ****************************************************************************/
+#ifdef CONFIG_EOSS3_GPIO_IRQ
+void eoss3_gpioirqclear(int irq);
+#else
+# define eoss3_gpioirqclear(irq)
+#endif
+
+/****************************************************************************
+ * Function: eoss3_dumpgpio
+ *
+ * Description:
+ * Dump all PIO registers associated with the base address of the provided
+ * pinset.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_GPIO_INFO
+int eoss3_dumpgpio(uint32_t pinset, const char *msg);
+#else
+# define eoss3_dumpgpio(p,m)
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_EOSS3_EOSS3_GPIO_H */
diff --git a/arch/arm/src/eoss3/eoss3_idle.c b/arch/arm/src/eoss3/eoss3_idle.c
new file mode 100644
index 0000000..6c99bb4
--- /dev/null
+++ b/arch/arm/src/eoss3/eoss3_idle.c
@@ -0,0 +1,73 @@
+/****************************************************************************
+ * arch/arm/eoss3/src/eoss3_idle.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <arch/board/board.h>
+#include <nuttx/config.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/power/pm.h>
+
+#include <nuttx/irq.h>
+
+#include "chip.h"
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_idle
+ *
+ * Description:
+ * up_idle() is the logic that will be executed when their is no other
+ * ready-to-run task. This is processor idle time and will continue until
+ * some interrupt occurs to cause a context switch from the idle task.
+ *
+ * Processing in this state may be processor-specific. e.g., this is where
+ * power management operations might be performed.
+ *
+ ****************************************************************************/
+
+void up_idle(void)
+{
+#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
+ /* If the system is idle and there are no timer interrupts, then process
+ * "fake" timer interrupts. Hopefully, something will wake up.
+ */
+
+ nxsched_process_timer();
+#else
+ asm("WFI");
+#endif
+}
diff --git a/arch/arm/src/eoss3/eoss3_irq.c b/arch/arm/src/eoss3/eoss3_irq.c
new file mode 100644
index 0000000..430a8b4
--- /dev/null
+++ b/arch/arm/src/eoss3/eoss3_irq.c
@@ -0,0 +1,559 @@
+/****************************************************************************
+ * arch/arm/src/eoss3/eoss3_irq.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <arch/armv7-m/nvicpri.h>
+
+#include "nvic.h"
+#include "ram_vectors.h"
+#include "arm_arch.h"
+#include "sched/sched.h"
+#include "arm_internal.h"
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Get a 32-bit version of the default priority */
+
+#define DEFPRIORITY32 \
+ (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
+ NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
+ NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
+ NVIC_SYSH_PRIORITY_DEFAULT)
+
+/* Given the address of a NVIC ENABLE register, this is the offset to
+ * the corresponding CLEAR ENABLE register.
+ */
+
+#define NVIC_ENA_OFFSET (0)
+#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+volatile uint32_t *g_current_regs[1];
+
+/* This is the address of the exception vector table (determined by the
+ * linker script).
+ */
+
+extern uint32_t _vectors[];
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: eoss3_dumpnvic
+ *
+ * Description:
+ * Dump some interesting NVIC registers
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_DEBUG_IRQ_INFO)
+static void eoss3_dumpnvic(const char *msg, int irq)
+{
+ irqstate_t flags;
+
+ flags = enter_critical_section();
+
+ irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
+ irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
+ getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
+ irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x "
+ "SYSTICK: %08x\n",
+ getreg32(NVIC_SYSHCON_MEMFAULTENA),
+ getreg32(NVIC_SYSHCON_BUSFAULTENA),
+ getreg32(NVIC_SYSHCON_USGFAULTENA),
+ getreg32(NVIC_SYSTICK_CTRL_ENABLE));
+ irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
+ getreg32(NVIC_IRQ0_31_ENABLE),
+ getreg32(NVIC_IRQ32_63_ENABLE),
+ getreg32(NVIC_IRQ64_95_ENABLE));
+ irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
+ getreg32(NVIC_SYSH4_7_PRIORITY),
+ getreg32(NVIC_SYSH8_11_PRIORITY),
+ getreg32(NVIC_SYSH12_15_PRIORITY));
+ irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ0_3_PRIORITY),
+ getreg32(NVIC_IRQ4_7_PRIORITY),
+ getreg32(NVIC_IRQ8_11_PRIORITY),
+ getreg32(NVIC_IRQ12_15_PRIORITY));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(NVIC_IRQ16_19_PRIORITY),
+ getreg32(NVIC_IRQ20_23_PRIORITY),
+ getreg32(NVIC_IRQ24_27_PRIORITY),
+ getreg32(NVIC_IRQ28_31_PRIORITY));
+
+ leave_critical_section(flags);
+}
+#else
+# define eoss3_dumpnvic(msg, irq)
+#endif
+
+/****************************************************************************
+ * Name: eoss3_nmi, eoss3_busfault, eoss3_usagefault, eoss3_pendsv,
+ * eoss3_dbgmonitor, eoss3_pendsv, eoss3_reserved
+ *
+ * Description:
+ * Handlers for various exceptions. None are handled and all are fatal
+ * error conditions. The only advantage these provided over the default
+ * unexpected interrupt handler is that they provide a diagnostic output.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_FEATURES
+static int eoss3_nmi(int irq, FAR void *context, FAR void *arg)
+{
+ up_irq_save();
+ _err("PANIC!!! NMI received\n");
+ PANIC();
+ return 0;
+}
+
+static int eoss3_busfault(int irq, FAR void *context, FAR void *arg)
+{
+ up_irq_save();
+ _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
+ PANIC();
+ return 0;
+}
+
+static int eoss3_usagefault(int irq, FAR void *context, FAR void *arg)
+{
+ up_irq_save();
+ _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
+ PANIC();
+ return 0;
+}
+
+static int eoss3_pendsv(int irq, FAR void *context, FAR void *arg)
+{
+ up_irq_save();
+ _err("PANIC!!! PendSV received\n");
+ PANIC();
+ return 0;
+}
+
+static int eoss3_dbgmonitor(int irq, FAR void *context, FAR void *arg)
+{
+ up_irq_save();
+ _err("PANIC!!! Debug Monitor received\n");
+ PANIC();
+ return 0;
+}
+
+static int eoss3_reserved(int irq, FAR void *context, FAR void *arg)
+{
+ up_irq_save();
+ _err("PANIC!!! Reserved interrupt\n");
+ PANIC();
+ return 0;
+}
+#endif
+
+/****************************************************************************
+ * Name: eoss3_prioritize_syscall
+ *
+ * Description:
+ * Set the priority of an exception. This function may be needed
+ * internally even if support for prioritized interrupts is not enabled.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+static inline void eoss3_prioritize_syscall(int priority)
+{
+ uint32_t regval;
+
+ /* SVCALL is system handler 11 */
+
+ regval = getreg32(NVIC_SYSH8_11_PRIORITY);
+ regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
+ regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
+ putreg32(regval, NVIC_SYSH8_11_PRIORITY);
+}
+#endif
+
+/****************************************************************************
+ * Name: eoss3_irqinfo
+ *
+ * Description:
+ * Given an IRQ number, provide the register and bit setting to enable or
+ * disable the irq.
+ *
+ ****************************************************************************/
+
+static int eoss3_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
+ uintptr_t offset)
+{
+ int n;
+
+ DEBUGASSERT(irq >= EOSS3_IRQ_NMI && irq < NR_IRQS);
+
+ /* Check for external interrupt or a second level GPIO interrupt */
+
+ if (irq >= EOSS3_IRQ_INTERRUPTS)
+ {
+ if (irq < EOSS3_IRQ_NVECTORS)
+ {
+ n = irq - EOSS3_IRQ_INTERRUPTS;
+ *regaddr = NVIC_IRQ_ENABLE(n) + offset;
+ *bit = (uint32_t)1 << (n & 0x1f);
+ }
+ else
+ {
+ return -EINVAL; /* Invalid interrupt */
+ }
+ }
+
+ /* Handle processor exceptions. Only a few can be disabled */
+
+ else
+ {
+ *regaddr = NVIC_SYSHCON;
+ if (irq == EOSS3_IRQ_MEMFAULT)
+ {
+ *bit = NVIC_SYSHCON_MEMFAULTENA;
+ }
+ else if (irq == EOSS3_IRQ_BUSFAULT)
+ {
+ *bit = NVIC_SYSHCON_BUSFAULTENA;
+ }
+ else if (irq == EOSS3_IRQ_USAGEFAULT)
+ {
+ *bit = NVIC_SYSHCON_USGFAULTENA;
+ }
+ else if (irq == EOSS3_IRQ_SYSTICK)
+ {
+ *regaddr = NVIC_SYSTICK_CTRL;
+ *bit = NVIC_SYSTICK_CTRL_ENABLE;
+ }
+ else
+ {
+ return -EINVAL; /* Invalid or unsupported exception */
+ }
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+ uint32_t regaddr;
+ int num_priority_registers;
+ int i;
+
+ /* Disable all interrupts */
+
+ for (i = 0; i < EOSS3_IRQ_NVECTORS - EOSS3_IRQ_INTERRUPTS; i += 32)
+ {
+ putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
+ }
+
+ /* Make sure that we are using the correct vector table. The default
+ * vector address is 0x0000:0000 but if we are executing code that is
+ * positioned in SRAM or in external FLASH, then we may need to reset
+ * the interrupt vector so that it refers to the table in SRAM or in
+ * external FLASH.
+ */
+
+ putreg32((uint32_t)_vectors, NVIC_VECTAB);
+
+#ifdef CONFIG_ARCH_RAMVECTORS
+ /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
+ * vector table that requires special initialization.
+ */
+
+ arm_ramvec_initialize();
+#endif
+
+ /* Set all interrupts (and exceptions) to the default priority */
+
+ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
+ putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
+ putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
+
+ /* The NVIC ICTR register (bits 0-4) holds the number of interrupt
+ * lines that the NVIC supports:
+ *
+ * 0 -> 32 interrupt lines, 8 priority registers
+ * 1 -> 64 " " " ", 16 priority registers
+ * 2 -> 96 " " " ", 32 priority registers
+ * ...
+ */
+
+ num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8;
+
+ /* Now set all of the interrupt lines to the default priority */
+
+ regaddr = NVIC_IRQ0_3_PRIORITY;
+ while (num_priority_registers--)
+ {
+ putreg32(DEFPRIORITY32, regaddr);
+ regaddr += 4;
+ }
+
+ /* currents_regs is non-NULL only while processing an interrupt */
+
+ CURRENT_REGS = NULL;
+
+ /* Attach the SVCall and Hard Fault exception handlers. The SVCall
+ * exception is used for performing context switches; The Hard Fault
+ * must also be caught because a SVCall may show up as a Hard Fault
+ * under certain conditions.
+ */
+
+ irq_attach(EOSS3_IRQ_SVCALL, arm_svcall, NULL);
+ irq_attach(EOSS3_IRQ_HARDFAULT, arm_hardfault, NULL);
+
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+ /* Set the priority of the SVCall interrupt */
+
+ eoss3_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
+#endif
+
+ /* If the MPU is enabled, then attach and enable the Memory Management
+ * Fault handler.
+ */
+
+#ifdef CONFIG_ARM_MPU
+ irq_attach(EOSS3_IRQ_MEMFAULT, arm_memfault, NULL);
+ up_enable_irq(EOSS3_IRQ_MEMFAULT);
+#endif
+
+ /* Attach all other processor exceptions (except reset and sys tick) */
+
+#ifdef CONFIG_DEBUG_FEATURES
+ irq_attach(EOSS3_IRQ_NMI, eoss3_nmi, NULL);
+#ifndef CONFIG_ARM_MPU
+ irq_attach(EOSS3_IRQ_MEMFAULT, arm_memfault, NULL);
+#endif
+ irq_attach(EOSS3_IRQ_BUSFAULT, eoss3_busfault, NULL);
+ irq_attach(EOSS3_IRQ_USAGEFAULT, eoss3_usagefault, NULL);
+ irq_attach(EOSS3_IRQ_PENDSV, eoss3_pendsv, NULL);
+ irq_attach(EOSS3_IRQ_DBGMONITOR, eoss3_dbgmonitor, NULL);
+ irq_attach(EOSS3_IRQ_RESERVED, eoss3_reserved, NULL);
+#endif
+
+ eoss3_dumpnvic("initial", EOSS3_IRQ_NVECTORS);
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+#ifdef CONFIG_EOSS3_GPIO_IRQ
+ /* Initialize logic to support a second level of interrupt decoding for
+ * GPIO pins.
+ */
+
+ eoss3_gpioirqinitialize();
+#endif
+
+ /* And finally, enable interrupts */
+
+ up_irq_enable();
+#endif
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ * Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+ uintptr_t regaddr;
+ uint32_t regval;
+ uint32_t bit;
+
+ if (eoss3_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0)
+ {
+ /* Modify the appropriate bit in the register to disable the interrupt.
+ * For normal interrupts, we need to set the bit in the associated
+ * Interrupt Clear Enable register. For other exceptions, we need to
+ * clear the bit in the System Handler Control and State Register.
+ */
+
+ if (irq >= EOSS3_IRQ_INTERRUPTS)
+ {
+ putreg32(bit, regaddr);
+ }
+ else
+ {
+ regval = getreg32(regaddr);
+ regval &= ~bit;
+ putreg32(regval, regaddr);
+ }
+ }
+#ifdef CONFIG_EOSS3_GPIO_IRQ
+ else
+ {
+ /* Maybe it is a (derived) GPIO IRQ */
+
+ eoss3_gpioirqdisable(irq);
+ }
+#endif
+
+ eoss3_dumpnvic("disable", irq);
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ * Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+ uintptr_t regaddr;
+ uint32_t regval;
+ uint32_t bit;
+
+ if (eoss3_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0)
+ {
+ /* Modify the appropriate bit in the register to enable the interrupt.
+ * For normal interrupts, we need to set the bit in the associated
+ * Interrupt Set Enable register. For other exceptions, we need to
+ * set the bit in the System Handler Control and State Register.
+ */
+
+ if (irq >= EOSS3_IRQ_INTERRUPTS)
+ {
+ putreg32(bit, regaddr);
+ }
+ else
+ {
+ regval = getreg32(regaddr);
+ regval |= bit;
+ putreg32(regval, regaddr);
+ }
+ }
+#ifdef CONFIG_EOSS3_GPIO_IRQ
+ else
+ {
+ /* Maybe it is a (derived) PIO IRQ */
+
+ eoss3_gpioirqenable(irq);
+ }
+#endif
+
+ eoss3_dumpnvic("enable", irq);
+}
+
+/****************************************************************************
+ * Name: arm_ack_irq
+ *
+ * Description:
+ * Acknowledge the IRQ
+ *
+ ****************************************************************************/
+
+void arm_ack_irq(int irq)
+{
+}
+
+/****************************************************************************
+ * Name: up_prioritize_irq
+ *
+ * Description:
+ * Set the priority of an IRQ.
+ *
+ * Since this API is not supported on all architectures, it should be
+ * avoided in common implementations where possible.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_IRQPRIO
+int up_prioritize_irq(int irq, int priority)
+{
+ uint32_t regaddr;
+ uint32_t regval;
+ int shift;
+
+ DEBUGASSERT(irq >= EOSS3_IRQ_MEMFAULT && irq < EOSS3_IRQ_NVECTORS &&
+ (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
+
+ if (irq < EOSS3_IRQ_INTERRUPTS)
+ {
+ /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
+ * registers (0-3 are invalid)
+ */
+
+ regaddr = NVIC_SYSH_PRIORITY(irq);
+ irq -= 4;
+ }
+ else (irq < EOSS3_IRQ_NVECTORS)
+ {
+ /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
+
+ irq -= EOSS3_IRQ_INTERRUPTS;
+ regaddr = NVIC_IRQ_PRIORITY(irq);
+ }
+ else
+ {
+ /* Must be a GPIO interrupt */
+
+ return -EINVAL;
+ }
+
+ regval = getreg32(regaddr);
+ shift = ((irq & 3) << 3);
+ regval &= ~(0xff << shift);
+ regval |= (priority << shift);
+ putreg32(regval, regaddr);
+
+ eoss3_dumpnvic("prioritize", irq);
+ return OK;
+}
+#endif
diff --git a/arch/arm/src/eoss3/eoss3_lowputc.c b/arch/arm/src/eoss3/eoss3_lowputc.c
new file mode 100644
index 0000000..a99e93c
--- /dev/null
+++ b/arch/arm/src/eoss3/eoss3_lowputc.c
@@ -0,0 +1,130 @@
+/****************************************************************************
+ * arch/arm/src/eoss3/eoss3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <arch/board/board.h>
+
+#include "arm_internal.h"
+#include "arm_arch.h"
+
+#include "chip.h"
+
+#include "eoss3.h"
+#include "eoss3_gpio.h"
+#include "hardware/eoss3_uart.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_lowputc
+ *
+ * Description:
+ * Output one byte on the serial console
+ *
+ ****************************************************************************/
+
+void arm_lowputc(char ch)
+{
+ /* Wait until the TX data register is empty */
+
+ while ((getreg32(EOSS3_UART_TFR) & UART_TFR_BUSY) != 0);
+
+ /* Then send the character */
+
+ putreg32((uint32_t)ch, EOSS3_UART_DR);
+}
+
+/****************************************************************************
+ * Name: eoss3_lowsetup
+ *
+ * Description:
+ * This performs basic initialization of the UART used for the serial
+ * console. Its purpose is to get the console output available as soon
+ * as possible.
+ *
+ ****************************************************************************/
+
+void eoss3_lowsetup(void)
+{
+ /* Configure the Baudrate
+ * At this point we 9973760.0 clock on C11
+ * Lets go ahead and configure the UART Baudrate to be 115200
+ * This clocking configuration should probably be configured via
+ * board settings but we are hard coding it all for now.
+ *
+ * Note there is a fixed divisor of 16 in the front
+ *
+ * 9973760.0 / (16 * 115200) = 5.411111111111111
+ *
+ * int = 5
+ * frac = (5.411111111111111 - 5)*(2^6) = 26
+ *
+ * act_div = 5 + 26 / 2^6 = 86.578125
+ * act_baud = 9973760.0 / 86.578125 = 115303
+ */
+
+ putreg32(5, EOSS3_UART_IBRD);
+ putreg32(26, EOSS3_UART_FBRD);
+
+ /* Configure word length 8 bit */
+
+ putreg32(UART_LCR_H_WLE_8, EOSS3_UART_LCR_H);
+
+ /* Enable Hardware */
+
+ putreg32(UART_CR_UARTEN | UART_CR_TXE | UART_CR_RXE, EOSS3_UART_CR);
+
+ /* Should move these pin configuration definitions to the board */
+
+ eoss3_configgpio(GPIO_UART_RX);
+ eoss3_configgpio(GPIO_UART_TX);
+}
diff --git a/arch/arm/src/eoss3/eoss3_lowputc.h b/arch/arm/src/eoss3/eoss3_lowputc.h
new file mode 100644
index 0000000..4cba397
--- /dev/null
+++ b/arch/arm/src/eoss3/eoss3_lowputc.h
@@ -0,0 +1,63 @@
+/****************************************************************************
+ * arch/arm/src/eoss3/eoss3_lowputc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_EOSS3_EOSS3_LOWPUTC_H
+#define __ARCH_ARM_SRC_EOSS3_EOSS3_LOWPUTC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: eoss3_lowsetup
+ *
+ * Description:
+ * Called at the very beginning of _start. Performs low level
+ * initialization of serial console.
+ *
+ ****************************************************************************/
+
+void eoss3_lowsetup(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_EOSS3_EOSS3_LOWPUTC_H */
diff --git a/arch/arm/src/eoss3/eoss3_serial.c b/arch/arm/src/eoss3/eoss3_serial.c
new file mode 100644
index 0000000..b38bdce
--- /dev/null
+++ b/arch/arm/src/eoss3/eoss3_serial.c
@@ -0,0 +1,636 @@
+/****************************************************************************
+ * arch/arm/eoss3/src/eoss3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/init.h>
+#include <nuttx/power/pm.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/wqueue.h>
+
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "arm_arch.h"
+#include "arm_internal.h"
+
+#include "hardware/eoss3_uart.h"
+#include "hardware/eoss3_intr.h"
+#include "eoss3_lowputc.h"
+
+#ifdef USE_SERIALDRIVER
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct eoss3_uart_s
+{
+ uint32_t ie; /* Saved IE value */
+ struct work_s work;
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static inline void eoss3_disableuartint(struct eoss3_uart_s *priv,
+ uint32_t *ie);
+static inline void eoss3_restoreuartint(struct eoss3_uart_s *priv,
+ uint32_t ie);
+static void eoss3_tx_work(void *arg);
+static int eoss3_setup(struct uart_dev_s *dev);
+static void eoss3_shutdown(struct uart_dev_s *dev);
+static int eoss3_attach(struct uart_dev_s *dev);
+static void eoss3_detach(struct uart_dev_s *dev);
+static int eoss3_interrupt(int irq, void *context, FAR void *arg);
+static int eoss3_ioctl(struct file *filep, int cmd, unsigned long arg);
+static int eoss3_receive(struct uart_dev_s *dev, uint32_t *status);
+static void eoss3_rxint(struct uart_dev_s *dev, bool enable);
+static bool eoss3_rxavailable(struct uart_dev_s *dev);
+static void eoss3_send(struct uart_dev_s *dev, int ch);
+static void eoss3_txint(struct uart_dev_s *dev, bool enable);
+static bool eoss3_txready(struct uart_dev_s *dev);
+static bool eoss3_txempty(struct uart_dev_s *dev);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Serial driver UART operations */
+
+static const struct uart_ops_s g_uart_ops =
+{
+ .setup = eoss3_setup,
+ .shutdown = eoss3_shutdown,
+ .attach = eoss3_attach,
+ .detach = eoss3_detach,
+ .ioctl = eoss3_ioctl,
+ .receive = eoss3_receive,
+ .rxint = eoss3_rxint,
+ .rxavailable = eoss3_rxavailable,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = NULL,
+#endif
+ .send = eoss3_send,
+ .txint = eoss3_txint,
+ .txready = eoss3_txready,
+ .txempty = eoss3_txempty,
+};
+
+/* I/O buffers */
+
+#ifdef CONFIG_EOSS3_UART
+static char g_uartrxbuffer[CONFIG_UART_RXBUFSIZE];
+static char g_uarttxbuffer[CONFIG_UART_TXBUFSIZE];
+#endif
+
+/* This describes the state of the EOSS3 uart port. */
+
+#ifdef CONFIG_EOSS3_UART
+static struct eoss3_uart_s g_uartpriv;
+
+static struct uart_dev_s g_uartport =
+{
+ .recv =
+ {
+ .size = CONFIG_UART_RXBUFSIZE,
+ .buffer = g_uartrxbuffer,
+ },
+ .xmit =
+ {
+ .size = CONFIG_UART_TXBUFSIZE,
+ .buffer = g_uarttxbuffer,
+ },
+ .ops = &g_uart_ops,
+ .priv = &g_uartpriv,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: eoss3_disableuartint
+ ****************************************************************************/
+
+static inline void eoss3_disableuartint(struct eoss3_uart_s *priv,
+ uint32_t *ie)
+{
+ if (ie)
+ {
+ *ie = priv->ie & UART_IMSC_ALLINTS;
+ }
+
+ priv->ie &= ~UART_IMSC_ALLINTS;
+ putreg32(priv->ie, EOSS3_UART_IMSC);
+}
+
+/****************************************************************************
+ * Name: eoss3_restoreuartint
+ ****************************************************************************/
+
+static inline void eoss3_restoreuartint(struct eoss3_uart_s *priv,
+ uint32_t ie)
+{
+ priv->ie |= ie & UART_IMSC_ALLINTS;
+ putreg32(priv->ie, EOSS3_UART_IMSC);
+}
+
+/****************************************************************************
+ * Name: eoss3_tx_work
+ *
+ * Description:
+ * We expect that the TX FIFO should be ready for data again
+ *
+ ****************************************************************************/
+
+static void eoss3_tx_work(void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct eoss3_uart_s *priv = (struct eoss3_uart_s *)dev->priv;
+ irqstate_t flags;
+
+ uart_xmitchars(dev);
+
+ /* Check if there is still data to send, if so reschedule */
+
+ flags = enter_critical_section();
+ if (dev->xmit.head != dev->xmit.tail)
+ {
+ work_queue(HPWORK, &priv->work, eoss3_tx_work,
+ (FAR void *)arg, 0);
+ }
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: eoss3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This
+ * method is called the first time that the serial port is
+ * opened.
+ *
+ ****************************************************************************/
+
+static int eoss3_setup(struct uart_dev_s *dev)
+{
+ struct eoss3_uart_s *priv = (struct eoss3_uart_s *)dev->priv;
+ int ret;
+ uint32_t lcrh;
+
+ /* Grab starting state of interrupts */
+
+ priv->ie = getreg32(EOSS3_UART_IMSC);
+
+#ifndef CONFIG_SUPPRESS_UART_CONFIG
+ /* Enable the FIFO
+ * This is especially important since we are faking tx empty interrupt.
+ */
+
+ lcrh = getreg32(EOSS3_UART_LCR_H);
+ lcrh |= UART_LCR_H_FEN;
+ putreg32(lcrh, EOSS3_UART_LCR_H);
+ ret = OK;
+ return ret;
+#else
+ UNUSED(ret);
+ UNUSED(lcrh);
+ return OK;
+#endif
+}
+
+/****************************************************************************
+ * Name: eoss3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial
+ * port is closed
+ *
+ ****************************************************************************/
+
+static void eoss3_shutdown(struct uart_dev_s *dev)
+{
+ struct eoss3_uart_s *priv = (struct eoss3_uart_s *)dev->priv;
+ eoss3_disableuartint(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: eoss3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the setup() method is called, however, the serial console may operate
+ * in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ ****************************************************************************/
+
+static int eoss3_attach(struct uart_dev_s *dev)
+{
+ int ret;
+ uint32_t m4_intrc;
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(EOSS3_IRQ_UART, eoss3_interrupt, dev);
+ if (ret == OK)
+ {
+ /* Enable the interrupt (RX and TX interrupts are still disabled
+ * in the UART. This also turns on the top level routing. This may
+ * later move into the up_enable_irq logic.
+ */
+
+ putreg32(INTR_UART_DET, EOSS3_INTR_OTHER);
+ putreg32(UART_IMSC_ALLINTS, EOSS3_UART_ICR);
+ m4_intrc = getreg32(EOSS3_INTR_OTHER_EN_M4);
+ m4_intrc |= INTR_UART_EN_M4;
+ putreg32(m4_intrc, EOSS3_INTR_OTHER_EN_M4);
+ up_enable_irq(EOSS3_IRQ_UART);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: eoss3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ ****************************************************************************/
+
+static void eoss3_detach(struct uart_dev_s *dev)
+{
+ up_disable_irq(EOSS3_IRQ_UART);
+ irq_detach(EOSS3_IRQ_UART);
+}
+
+/****************************************************************************
+ * Name: eoss3_interrupt
+ *
+ * Description:
+ * This is the common UART interrupt handler. It should call
+ * uart_transmitchars or uart_receivechar to perform the appropriate data
+ * transfers.
+ *
+ ****************************************************************************/
+
+static int eoss3_interrupt(int irq, void *context, FAR void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ uint32_t status;
+ int passes;
+
+ /* Loop until there are no characters to be transferred or,
+ * until we have been looping for a long time.
+ */
+
+ for (passes = 0; passes < 256; passes++)
+ {
+ /* Get the current UART status and check for loop
+ * termination conditions
+ */
+
+ status = getreg32(EOSS3_UART_MIS);
+
+ /* If no interrupts remaining break */
+
+ if (status == 0)
+ {
+ putreg32(UART_IMSC_ALLINTS, EOSS3_UART_ICR);
+ break;
+ }
+
+ /* Handle incoming, receive bytes */
+
+ if (status & (UART_MIS_RXMIS | UART_MIS_RTMIS))
+ {
+ uart_recvchars(dev);
+ }
+ }
+
+ /* This will clear the pending interrupt flag on the top level */
+
+ putreg32(INTR_UART_DET, EOSS3_INTR_OTHER);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: eoss3_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ *
+ ****************************************************************************/
+
+static int eoss3_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+#if defined(CONFIG_SERIAL_TIOCSERGSTRUCT) || defined(CONFIG_SERIAL_TERMIOS)
+ struct inode *inode = filep->f_inode;
+ struct uart_dev_s *dev = inode->i_private;
+ irqstate_t flags;
+#endif
+ int ret = OK;
+
+ switch (cmd)
+ {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+ case TIOCSERGSTRUCT:
+ {
+ struct eoss3_uart_s *user = (struct eoss3_uart_s *)arg;
+ if (!user)
+ {
+ ret = -EINVAL;
+ }
+ else
+ {
+ memcpy(user, dev, sizeof(struct eoss3_uart_s));
+ }
+ }
+ break;
+#endif
+ default:
+ ret = -ENOTTY;
+ break;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: eoss3_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ****************************************************************************/
+
+static int eoss3_receive(struct uart_dev_s *dev, uint32_t *status)
+{
+ *status = getreg32(EOSS3_UART_RSR_ECR);
+ return (getreg32(EOSS3_UART_DR) & UART_DR_DATA_MASK);
+}
+
+/****************************************************************************
+ * Name: eoss3_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ****************************************************************************/
+
+static void eoss3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct eoss3_uart_s *priv = (struct eoss3_uart_s *)dev->priv;
+
+ /* Enable interrupts for data available at Rx */
+
+ if (enable)
+ {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ priv->ie |= (UART_IMSC_RXIM | UART_IMSC_RTIM);
+#endif
+ }
+ else
+ {
+ priv->ie &= ~(UART_IMSC_RXIM | UART_IMSC_RTIM);
+ }
+
+ putreg32(priv->ie, EOSS3_UART_IMSC);
+}
+
+/****************************************************************************
+ * Name: eoss3_rxavailable
+ *
+ * Description:
+ * Return true if the receive fifo is not empty
+ *
+ ****************************************************************************/
+
+static bool eoss3_rxavailable(struct uart_dev_s *dev)
+{
+ return ((getreg32(EOSS3_UART_TFR) & UART_TFR_RXFE) == 0);
+}
+
+/****************************************************************************
+ * Name: eoss3_send
+ *
+ * Description:
+ * This method will send one byte on the UART
+ *
+ ****************************************************************************/
+
+static void eoss3_send(struct uart_dev_s *dev, int ch)
+{
+ putreg32(ch & UART_DR_DATA_MASK, EOSS3_UART_DR);
+}
+
+/****************************************************************************
+ * Name: eoss3_txint
+ *
+ * Description:
+ * Normally would turn on and off the tx empty interrupt instead we are
+ * enableing a kernel worker because there is no interrupt. This worker
+ * will requeue and dequeue itself as needed.
+ *
+ ****************************************************************************/
+
+static void eoss3_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct eoss3_uart_s *priv = (struct eoss3_uart_s *)dev->priv;
+
+ if (enable)
+ {
+ if (work_available(&priv->work))
+ {
+ work_queue(HPWORK, &priv->work, eoss3_tx_work,
+ (FAR void *)dev, 0);
+ }
+ }
+}
+
+/****************************************************************************
+ * Name: eoss3_txready
+ *
+ * Description:
+ * Return true if the transmit fifo is not full
+ *
+ ****************************************************************************/
+
+static bool eoss3_txready(struct uart_dev_s *dev)
+{
+ return ((getreg32(EOSS3_UART_TFR) & UART_TFR_TXFF) == 0);
+}
+
+/****************************************************************************
+ * Name: eoss3_txempty
+ *
+ * Description:
+ * Return true if the transmit fifo is empty
+ *
+ ****************************************************************************/
+
+static bool eoss3_txempty(struct uart_dev_s *dev)
+{
+ return ((getreg32(EOSS3_UART_TFR) & UART_TFR_TXFE) != 0);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_earlyserialinit
+ *
+ * Description:
+ * Performs the low level UART initialization early in debug so that the
+ * serial console will be available during bootup. This must be called
+ * before arm_serialinit.
+ *
+ ****************************************************************************/
+
+void arm_earlyserialinit(void)
+{
+ /* NOTE: This function assumes that low level hardware configuration
+ * -- including all clocking and pin configuration -- was performed by the
+ * function eoss3_lowsetup() earlier in the boot sequence.
+ */
+
+ /* Enable the console UART. The other UARTs will be initialized if and
+ * when they are first opened.
+ */
+
+#ifdef CONFIG_UART_SERIAL_CONSOLE
+ g_uartport.isconsole = true;
+ eoss3_setup(&g_uartport);
+#endif
+}
+
+/****************************************************************************
+ * Name: arm_serialinit
+ *
+ * Description:
+ * Register serial console and serial ports. This assumes
+ * that eoss3_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+void arm_serialinit(void)
+{
+#ifdef CONFIG_UART_SERIAL_CONSOLE
+ uart_register("/dev/console", &g_uartport);
+#endif
+#ifdef CONFIG_EOSS3_UART
+ uart_register("/dev/ttyS0", &g_uartport);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ * Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef CONFIG_UART_SERIAL_CONSOLE
+ struct eoss3_uart_s *priv = (struct eoss3_uart_s *)g_uartport.priv;
+ uint32_t ie;
+
+ eoss3_disableuartint(priv, &ie);
+
+ /* Check for LF */
+
+ if (ch == '\n')
+ {
+ /* Add CR */
+
+ arm_lowputc('\r');
+ }
+
+ arm_lowputc(ch);
+ eoss3_restoreuartint(priv, ie);
+#endif
+
+ return ch;
+}
+
+#else /* USE_SERIALDRIVER */
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ * Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+ /* Check for LF */
+
+ if (ch == '\n')
+ {
+ /* Add CR */
+
+ arm_lowputc('\r');
+ }
+
+ /* Output the character */
+
+ arm_lowputc(ch);
+ return ch;
+}
+
+#endif /* USE_SERIALDRIVER */
\ No newline at end of file
diff --git a/arch/arm/src/eoss3/eoss3_start.c b/arch/arm/src/eoss3/eoss3_start.c
new file mode 100644
index 0000000..1f1aa3d
--- /dev/null
+++ b/arch/arm/src/eoss3/eoss3_start.c
@@ -0,0 +1,350 @@
+/****************************************************************************
+ * arch/arm/eoss3/src/eoss3_start.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/init.h>
+
+#include "arm_arch.h"
+#include "arm_internal.h"
+#include "nvic.h"
+#include "nuttx/irq.h"
+
+#include "eoss3.h"
+#include "eoss3_start.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* .data is positioned first in the primary RAM followed immediately by .bss.
+ * The IDLE thread stack lies just after .bss and has size give by
+ * CONFIG_IDLETHREAD_STACKSIZE; The heap then begins just after the IDLE.
+ * ARM EABI requires 64 bit stack alignment.
+ */
+
+#define IDLE_STACKSIZE (CONFIG_IDLETHREAD_STACKSIZE & ~7)
+#define IDLE_STACK ((uintptr_t)&_ebss + IDLE_STACKSIZE)
+#define HEAP_BASE ((uintptr_t)&_ebss + IDLE_STACKSIZE)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
+ * linker script. _ebss lies at the end of the BSS region. The idle task
+ * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
+ * The IDLE thread is the thread that the system boots on and, eventually,
+ * becomes the IDLE, do nothing task that runs only when there is nothing
+ * else to run. The heap continues from there until the end of memory.
+ * g_idle_topstack is a read-only variable the provides this computed
+ * address.
+ */
+
+const uintptr_t g_idle_topstack = HEAP_BASE;
+
+/****************************************************************************
+ * Private Function prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_FPU
+static inline void eoss3_fpuconfig(void);
+#endif
+#ifdef CONFIG_STACK_COLORATION
+static void go_nx_start(void *pv, unsigned int nbytes)
+ __attribute__ ((naked, no_instrument_function, noreturn));
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: showprogress
+ *
+ * Description:
+ * Print a character on the UART to show boot status.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_FEATURES
+# define showprogress(c) arm_lowputc(c)
+#else
+# define showprogress(c)
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ARMV7M_STACKCHECK
+/* we need to get r10 set before we can allow instrumentation calls */
+
+void __start(void) __attribute__ ((no_instrument_function));
+#endif
+
+/****************************************************************************
+ * Name: eoss3_fpuconfig
+ *
+ * Description:
+ * Configure the FPU. Relative bit settings:
+ *
+ * CPACR: Enables access to CP10 and CP11
+ * CONTROL.FPCA: Determines whether the FP extension is active in the
+ * current context:
+ * FPCCR.ASPEN: Enables automatic FP state preservation, then the
+ * processor sets this bit to 1 on successful completion of any FP
+ * instruction.
+ * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
+ * done, the processor reserves space on the stack for the FP state,
+ * but does not save that state information to the stack.
+ *
+ * Software must not change the value of the ASPEN bit or LSPEN bit while
+ * either:
+ * - the CPACR permits access to CP10 and CP11, that give access to the FP
+ * extension, or
+ * - the CONTROL.FPCA bit is set to 1
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_FPU
+#ifndef CONFIG_ARMV7M_LAZYFPU
+
+static inline void eoss3_fpuconfig(void)
+{
+ uint32_t regval;
+
+ /* Set CONTROL.FPCA so that we always get the extended context frame
+ * with the volatile FP registers stacked above the basic context.
+ */
+
+ regval = getcontrol();
+ regval |= (1 << 2);
+ setcontrol(regval);
+
+ /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
+ * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
+ * are going to turn on CONTROL.FPCA for all contexts.
+ */
+
+ regval = getreg32(NVIC_FPCCR);
+ regval &= ~((1 << 31) | (1 << 30));
+ putreg32(regval, NVIC_FPCCR);
+
+ /* Enable full access to CP10 and CP11 */
+
+ regval = getreg32(NVIC_CPACR);
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
+ putreg32(regval, NVIC_CPACR);
+}
+
+#else
+
+static inline void eoss3_fpuconfig(void)
+{
+ uint32_t regval;
+
+ /* Clear CONTROL.FPCA so that we do not get the extended context frame
+ * with the volatile FP registers stacked in the saved context.
+ */
+
+ regval = getcontrol();
+ regval &= ~(1 << 2);
+ setcontrol(regval);
+
+ /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
+ * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
+ * are going to keep CONTROL.FPCA off for all contexts.
+ */
+
+ regval = getreg32(NVIC_FPCCR);
+ regval &= ~((1 << 31) | (1 << 30));
+ putreg32(regval, NVIC_FPCCR);
+
+ /* Enable full access to CP10 and CP11 */
+
+ regval = getreg32(NVIC_CPACR);
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
+ putreg32(regval, NVIC_CPACR);
+}
+
+#endif
+
+#else
+# define eoss3_fpuconfig()
+#endif
+
+/****************************************************************************
+ * Name: go_nx_start
+ *
+ * Description:
+ * Set the IDLE stack to the coloration value and jump into nx_start()
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STACK_COLORATION
+static void go_nx_start(void *pv, unsigned int nbytes)
+{
+ /* Set the IDLE stack to the stack coloration value then jump to
+ * nx_start(). We take extreme care here because were currently
+ * executing on this stack.
+ *
+ * We want to avoid sneak stack access generated by the compiler.
+ */
+
+ __asm__ __volatile__
+ (
+ "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */
+ "\tcmp r1, #0\n" /* Check (nwords == 0) */
+ "\tbeq 2f\n" /* (should not happen) */
+
+ "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */
+ "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */
+ "\tmovt r2, #0xdead\n"
+
+ "1:\n" /* Top of the loop */
+ "\tsub r1, r1, #1\n" /* R1 nwords-- */
+ "\tcmp r1, #0\n" /* Check (nwords == 0) */
+ "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */
+ "\tbne 1b\n" /* Bottom of the loop */
+
+ "2:\n"
+ "\tmov r14, #0\n" /* LR = return address (none) */
+ "\tb nx_start\n" /* Branch to nx_start */
+ );
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _start
+ *
+ * Description:
+ * This is the reset entry point.
+ *
+ ****************************************************************************/
+
+void __start(void)
+{
+ const uint32_t *src;
+ uint32_t *dest;
+
+#ifdef CONFIG_ARMV7M_STACKCHECK
+ /* Set the stack limit before we attempt to call any functions */
+
+ __asm__ volatile \
+ ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) :);
+#endif
+
+ /* Configure the UART so that we can get debug output as soon as possible */
+
+ eoss3_clockconfig();
+
+ /* Unclear what needs to happen here to make RENODE happy. */
+#if 1
+ eoss3_fpuconfig();
+#endif
+
+ eoss3_lowsetup();
+
+ showprogress('A');
+
+ /* Clear .bss. We'll do this inline (vs. calling memset) just to be
+ * certain that there are no issues with the state of global variables.
+ */
+
+ for (dest = _START_BSS; dest < _END_BSS; )
+ {
+ *dest++ = 0;
+ }
+
+ showprogress('B');
+
+ /* Move the initialized data section from his temporary holding spot in
+ * FLASH into the correct place in SRAM. The correct place in SRAM is
+ * give by _sdata and _edata. The temporary location is in FLASH at the
+ * end of all of the other read-only data (.text, .rodata) at _eronly.
+ */
+
+ for (src = _DATA_INIT, dest = _START_DATA; dest < _END_DATA; )
+ {
+ *dest++ = *src++;
+ }
+
+ showprogress('C');
+
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
+ /* Perform ARMv7-M ITM SYSLOG initialization */
+
+ itm_syslog_initialize();
+#endif
+
+ /* Perform early serial initialization */
+
+#ifdef USE_EARLYSERIALINIT
+ arm_earlyserialinit();
+#endif
+ showprogress('D');
+
+ /* For the case of the separate user-/kernel-space build, perform whatever
+ * platform specific initialization of the user memory is required.
+ * Normally this just means initializing the user space .data and .bss
+ * segments.
+ */
+
+#ifdef CONFIG_BUILD_PROTECTED
+ eoss3_userspace();
+ showprogress('E');
+#endif
+
+ /* Initialize onboard resources */
+
+ eoss3_boardinitialize();
+ showprogress('F');
+
+ /* Then start NuttX */
+
+ showprogress('\r');
+ showprogress('\n');
+
+#ifdef CONFIG_STACK_COLORATION
+ /* Set the IDLE stack to the coloration value and jump into nx_start() */
+
+ go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE);
+#else
+ /* Call nx_start() */
+
+ nx_start();
+
+ /* Shouldn't get here */
+
+ for (; ; );
+#endif
+}
diff --git a/arch/arm/src/eoss3/eoss3_start.h b/arch/arm/src/eoss3/eoss3_start.h
new file mode 100644
index 0000000..cea0580
--- /dev/null
+++ b/arch/arm/src/eoss3/eoss3_start.h
@@ -0,0 +1,62 @@
+/****************************************************************************
+ * arch/arm/eoss3/src/eoss3_start.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_EOSS3_EOSS3_START_H
+#define __ARCH_ARM_SRC_EOSS3_EOSS3_START_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
+ * linker script. _ebss lies at the end of the BSS region. The idle task
+ * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
+ * The IDLE thread is the thread that the system boots on and, eventually,
+ * becomes the IDLE, do nothing task that runs only when there is nothing
+ * else to run. The heap continues from there until the end of memory.
+ * g_idle_topstack is a read-only variable the provides this computed
+ * address.
+ */
+
+extern const uintptr_t g_idle_topstack;
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: eoss3_boardinitialize
+ *
+ * Description:
+ * All EOS S3 architectures must provide the following entry point. This
+ * entry point is called early in the initialization -- after clocking and
+ * memory have been configured but before caches have been enabled and
+ * before any devices have been initialized.
+ *
+ ****************************************************************************/
+
+void eoss3_boardinitialize(void);
+
+#endif /* __ARCH_ARM_SRC_EOSS3_EOSS3_START_H */
diff --git a/arch/arm/src/eoss3/eoss3_timerisr.c b/arch/arm/src/eoss3/eoss3_timerisr.c
new file mode 100644
index 0000000..273a41f
--- /dev/null
+++ b/arch/arm/src/eoss3/eoss3_timerisr.c
@@ -0,0 +1,129 @@
+/****************************************************************************
+ * arch/arm/eoss3/src/eoss3_timerisr.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <time.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+
+#include <arch/board/board.h>
+
+#include "nvic.h"
+#include "clock/clock.h"
+#include "arm_internal.h"
+#include "arm_arch.h"
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define EOSS3_SYSTICK_CLOCK BOARD_CPU_FREQUENCY
+
+/* The desired timer interrupt frequency is provided by the definition
+ * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
+ * system clock ticks per second. That value is a user configurable setting
+ * that defaults to 100 (100 ticks per second = 10 MS interval).
+ */
+
+#define SYSTICK_RELOAD ((EOSS3_SYSTICK_CLOCK / CLK_TCK) - 1)
+
+/* The size of the reload field is 24 bits. Verify that the reload value
+ * will fit in the reload register.
+ */
+
+#if SYSTICK_RELOAD > 0x00ffffff
+# error SYSTICK_RELOAD exceeds the range of the RELOAD register
+#endif
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int eoss3_timerisr(int irq, uint32_t *regs, void *arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: eoss3_timerisr
+ *
+ * Description:
+ * The timer ISR will perform a variety of services for various portions
+ * of the systems.
+ *
+ ****************************************************************************/
+
+static int eoss3_timerisr(int irq, uint32_t *regs, void *arg)
+{
+ /* Process timer interrupt */
+
+ nxsched_process_timer();
+ return 0;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: up_timer_initialize
+ *
+ * Description:
+ * This function is called during start-up to initialize the timer
+ * interrupt.
+ *
+ ****************************************************************************/
+
+void up_timer_initialize(void)
+{
+ uint32_t regval;
+
+ /* Configure SysTick to interrupt at the requested rate */
+
+ putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
+ putreg32(0, NVIC_SYSTICK_CURRENT);
+
+ /* Attach the timer interrupt vector */
+
+ irq_attach(EOSS3_IRQ_SYSTICK, (xcpt_t)eoss3_timerisr, NULL);
+
+ /* Enable SysTick interrupts */
+
+ regval = (NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
+ NVIC_SYSTICK_CTRL_ENABLE);
+ putreg32(regval, NVIC_SYSTICK_CTRL);
+
+ /* And enable the timer interrupt */
+
+ up_enable_irq(EOSS3_IRQ_SYSTICK);
+}
diff --git a/arch/arm/src/eoss3/hardware/eoss3_clock.h b/arch/arm/src/eoss3/hardware/eoss3_clock.h
new file mode 100644
index 0000000..5b1b297
--- /dev/null
+++ b/arch/arm/src/eoss3/hardware/eoss3_clock.h
@@ -0,0 +1,173 @@
+/*****************************************************************************
+ * arch/arm/src/eoss3/eoss3_clock.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_CLOCK_H
+#define __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_CLOCK_H
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+/*****************************************************************************
+ * Pre-processor Definitions
+ *****************************************************************************/
+
+/* Register Offsets **********************************************************/
+
+#define EOSS3_CLK_CONTROL_A_0_OFFSET 0x0000 /* Clock 10 Divisor */
+#define EOSS3_CLK_CONTROL_A_1_OFFSET 0x0004 /* Clock 10 Clock Src Ctrl */
+#define EOSS3_CLK_CONTROL_B_0_OFFSET 0x0008 /* Clock 2 Divisor */
+#define EOSS3_CLK_CONTROL_C_0_OFFSET 0x0010 /* Clock 8 Divisor */
+#define EOSS3_CLK_CONTROL_D_0_OFFSET 0x0014 /* Clock 11 Divisor */
+#define EOSS3_CLK_CONTROL_E_0_OFFSET 0x0018 /* Clock 12 Divisor */
+#define EOSS3_CLK_CONTROL_F_0_OFFSET 0x0020 /* Clock 16 Divisor */
+#define EOSS3_CLK_CONTROL_F_1_OFFSET 0x0024 /* Clock 16 Clock Src Ctrl */
+#define EOSS3_CLK_CONTROL_G_0_OFFSET 0x0028 /* Clock 30 Divisor */
+#define EOSS3_CLK_CONTROL_H_0_OFFSET 0x002c /* Clock 19 Divisor */
+#define EOSS3_CLK_CONTROL_I_0_OFFSET 0x0034 /* Clock 21 Divisor */
+#define EOSS3_CLK_CONTROL_I_1_OFFSET 0x0038 /* Clock 21 Clock Src Ctrl */
+#define EOSS3_CLK_HS_CLK_SOURCE_OFFSET 0x003c /* HS Clock Selection Pin */
+#define EOSS3_CLK_C01_GATE_OFFSET 0x0040 /* Clock 1 Gating Ctrl */
+#define EOSS3_CLK_C02_GATE_OFFSET 0x0044 /* Clock 2 Gating Ctrl */
+#define EOSS3_CLK_C08_X4_GATE_OFFSET 0x0048 /* Clock 8 X4 Gating Ctrl */
+#define EOSS3_CLK_C08_X1_GATE_OFFSET 0x004c /* Clock 8 X1 Gating Ctrl */
+#define EOSS3_CLK_C10_GATE_OFFSET 0x0050 /* Clock 10 Gating Ctrl */
+#define EOSS3_CLK_C11_GATE_OFFSET 0x0054 /* Clock 111 Gating Ctrl */
+#define EOSS3_CLK_CS_GATE_OFFSET 0x005c /* Clock S Gating Ctrl */
+#define EOSS3_CLK_C16_GATE_OFFSET 0x0064 /* Clock 16 Gating Ctrl */
+#define EOSS3_CLK_C19_GATE_OFFSET 0x006c /* Clock 19 Gating Ctrl */
+#define EOSS3_CLK_C21_GATE_OFFSET 0x0070 /* Clock 21 Gating Ctrl */
+#define EOSS3_CLK_PF_SW_RESET_OFFSET 0x0080 /* Software Rest PF Block */
+#define EOSS3_CLK_FFE_SW_RESET_OFFSET 0x0084 /* Software Reset FFE Block */
+#define EOSS3_CLK_FB_SW_RESET_OFFSET 0x0088 /* Software Reset FB Block */
+#define EOSS3_CLK_A1_SW_RESET_OFFSET 0x008c /* Software Reset A1 Block */
+
+#define EOSS3_CLK_AUDIO_MISC_SW_RESET_OFFSET 0x0090 /* SW Rst Audio MISC */
+#define EOSS3_CLK_FB_MISC_SW_RST_CTL_OFFSET 0x0094 /* SW Rst FB MISC */
+
+#define EOSS3_CLK_CONTROL_PMU_OFFSET 0x0100 /* PMU Clock Gating Ctrl */
+#define EOSS3_CLK_CRU_GENERAL_OFFSET 0x0104 /* SPICLK Always On Ctrl */
+#define EOSS3_CLK_CRU_DEBUG_OFFSET 0x0108 /* Debug Select */
+#define EOSS3_CLK_C01_DIV_OFFSET 0x0110 /* Clock 1 Divider Ctrl */
+#define EOSS3_CLK_C09_DIV_OFFSET 0x0114 /* Clock 9 Divider Ctrl */
+#define EOSS3_CLK_C31_DIV_OFFSET 0x0118 /* Clock 31 Divider Ctrl */
+#define EOSS3_CLK_C09_GATE_OFFSET 0x011c /* Clock 9 Gating Ctrl */
+#define EOSS3_CLK_C30_C31_GATE_OFFSET 0x0120 /* Clock 30/31 Gating Ctrl */
+
+#define EOSS3_CLK_DIVIDER_CLK_GATING_OFFSET 0x0124 /* Clk DIV Clk Gating */
+
+#define EOSS3_CLK_SWITCH_FOR_B_OFFSET 0x0130 /* Clock 2 Source Ctrl */
+#define EOSS3_CLK_SWITCH_FOR_C_OFFSET 0x0134 /* Clock 8 Source Ctrl */
+#define EOSS3_CLK_SWITCH_FOR_D_OFFSET 0x0138 /* Clock 11 Source Ctrl */
+#define EOSS3_CLK_SWITCH_FOR_H_OFFSET 0x013c /* Clock 19 Source Ctrl */
+#define EOSS3_CLK_SWITCH_FOR_J_OFFSET 0x0140 /* Clock 23 Source Ctrl */
+#define EOSS3_CLK_SWITCH_FOR_G_OFFSET 0x0144 /* Clock 30 Source Ctrl */
+
+/* The AIP offsets for clocking */
+
+#define EOSS3_AIP_OSC_CTRL_0_OFFSET 0x0080 /* AIP Oscillator Control 0 */
+#define EOSS3_AIP_OSC_CTRL_1_OFFSET 0x0084 /* AIP Oscillator Control 1 */
+#define EOSS3_AIP_OSC_STA_0_OFFSET 0x00A0 /* AIP OScillator Status 0 */
+
+/* Register Addresses ********************************************************/
+
+#define EOSS3_UART_DR (EOSS3_CLK_BASE + EOSS3_UART_DR_OFFSET)
+#define EOSS3_CLK_CONTROL_A_0 (EOSS3_CLK_BASE + EOSS3_CLK_CONTROL_A_0_OFFSET)
+#define EOSS3_CLK_CONTROL_A_1 (EOSS3_CLK_BASE + EOSS3_CLK_CONTROL_A_1_OFFSET)
+#define EOSS3_CLK_CONTROL_B_0 (EOSS3_CLK_BASE + EOSS3_CLK_CONTROL_B_0_OFFSET)
+#define EOSS3_CLK_CONTROL_C_0 (EOSS3_CLK_BASE + EOSS3_CLK_CONTROL_C_0_OFFSET)
+#define EOSS3_CLK_CONTROL_D_0 (EOSS3_CLK_BASE + EOSS3_CLK_CONTROL_D_0_OFFSET)
+#define EOSS3_CLK_CONTROL_E_0 (EOSS3_CLK_BASE + EOSS3_CLK_CONTROL_E_0_OFFSET)
+#define EOSS3_CLK_CONTROL_F_0 (EOSS3_CLK_BASE + EOSS3_CLK_CONTROL_F_0_OFFSET)
+#define EOSS3_CLK_CONTROL_F_1 (EOSS3_CLK_BASE + EOSS3_CLK_CONTROL_F_1_OFFSET)
+#define EOSS3_CLK_CONTROL_G_0 (EOSS3_CLK_BASE + EOSS3_CLK_CONTROL_G_0_OFFSET)
+#define EOSS3_CLK_CONTROL_H_0 (EOSS3_CLK_BASE + EOSS3_CLK_CONTROL_H_0_OFFSET)
+#define EOSS3_CLK_CONTROL_I_0 (EOSS3_CLK_BASE + EOSS3_CLK_CONTROL_I_0_OFFSET)
+#define EOSS3_CLK_CONTROL_I_1 (EOSS3_CLK_BASE + EOSS3_CLK_CONTROL_I_1_OFFSET)
+#define EOSS3_CLK_HS_CLK_SOURCE (EOSS3_CLK_BASE + EOSS3_CLK_HS_CLK_SOURCE_OFFSET)
+#define EOSS3_CLK_C01_GATE (EOSS3_CLK_BASE + EOSS3_CLK_C01_GATE_OFFSET)
+#define EOSS3_CLK_C02_GATE (EOSS3_CLK_BASE + EOSS3_CLK_C02_GATE_OFFSET)
+#define EOSS3_CLK_C08_X4_GATE (EOSS3_CLK_BASE + EOSS3_CLK_C08_X4_GATE_OFFSET)
+#define EOSS3_CLK_C08_X1_GATE (EOSS3_CLK_BASE + EOSS3_CLK_C08_X1_GATE_OFFSET)
+#define EOSS3_CLK_C10_GATE (EOSS3_CLK_BASE + EOSS3_CLK_C10_GATE_OFFSET)
+#define EOSS3_CLK_C11_GATE (EOSS3_CLK_BASE + EOSS3_CLK_C11_GATE_OFFSET)
+#define EOSS3_CLK_CS_GATE (EOSS3_CLK_BASE + EOSS3_CLK_CS_GATE_OFFSET)
+#define EOSS3_CLK_C16_GATE (EOSS3_CLK_BASE + EOSS3_CLK_C16_GATE_OFFSET)
+#define EOSS3_CLK_C19_GATE (EOSS3_CLK_BASE + EOSS3_CLK_C19_GATE_OFFSET)
+#define EOSS3_CLK_C21_GATE (EOSS3_CLK_BASE + EOSS3_CLK_C21_GATE_OFFSET)
+#define EOSS3_CLK_PF_SW_RESET (EOSS3_CLK_BASE + EOSS3_CLK_PF_SW_RESET_OFFSET)
+#define EOSS3_CLK_FFE_SW_RESET (EOSS3_CLK_BASE + EOSS3_CLK_FFE_SW_RESET_OFFSET)
+#define EOSS3_CLK_FB_SW_RESET (EOSS3_CLK_BASE + EOSS3_CLK_FB_SW_RESET_OFFSET)
+#define EOSS3_CLK_A1_SW_RESET (EOSS3_CLK_BASE + EOSS3_CLK_A1_SW_RESET_OFFSET)
+
+#define EOSS3_CLK_AUDIO_MISC_SW_RESET (EOSS3_CLK_BASE + EOSS3_CLK_AUDIO_MISC_SW_RESET_OFFSET)
+#define EOSS3_CLK_FB_MISC_SW_RST_CTL (EOSS3_CLK_BASE + EOSS3_CLK_FB_MISC_SW_RST_CTL_OFFSET)
+
+#define EOSS3_CLK_CONTROL_PMU (EOSS3_CLK_BASE + EOSS3_CLK_CONTROL_PMU_OFFSET)
+#define EOSS3_CLK_CRU_GENERAL (EOSS3_CLK_BASE + EOSS3_CLK_CRU_GENERAL_OFFSET)
+#define EOSS3_CLK_CRU_DEBUG (EOSS3_CLK_BASE + EOSS3_CLK_CRU_DEBUG_OFFSET)
+#define EOSS3_CLK_C01_DIV (EOSS3_CLK_BASE + EOSS3_CLK_C01_DIV_OFFSET)
+#define EOSS3_CLK_C09_DIV (EOSS3_CLK_BASE + EOSS3_CLK_C09_DIV_OFFSET)
+#define EOSS3_CLK_C31_DIV (EOSS3_CLK_BASE + EOSS3_CLK_C31_DIV_OFFSET)
+#define EOSS3_CLK_C09_GATE (EOSS3_CLK_BASE + EOSS3_CLK_C09_GATE_OFFSET)
+#define EOSS3_CLK_C30_C31_GATE (EOSS3_CLK_BASE + EOSS3_CLK_C30_C31_GATE_OFFSET)
+
+#define EOSS3_CLK_DIVIDER_CLK_GATING (EOSS3_CLK_BASE + EOSS3_CLK_DIVIDER_CLK_GATING_OFFSET)
+
+#define EOSS3_CLK_SWITCH_FOR_B (EOSS3_CLK_BASE + EOSS3_CLK_SWITCH_FOR_B_OFFSET)
+#define EOSS3_CLK_SWITCH_FOR_C (EOSS3_CLK_BASE + EOSS3_CLK_SWITCH_FOR_C_OFFSET)
+#define EOSS3_CLK_SWITCH_FOR_D (EOSS3_CLK_BASE + EOSS3_CLK_SWITCH_FOR_D_OFFSET)
+#define EOSS3_CLK_SWITCH_FOR_H (EOSS3_CLK_BASE + EOSS3_CLK_SWITCH_FOR_H_OFFSET)
+#define EOSS3_CLK_SWITCH_FOR_J (EOSS3_CLK_BASE + EOSS3_CLK_SWITCH_FOR_J_OFFSET)
+#define EOSS3_CLK_SWITCH_FOR_G (EOSS3_CLK_BASE + EOSS3_CLK_SWITCH_FOR_G_OFFSET)
+
+/* AIP Clocking Registers */
+
+#define EOSS3_AIP_OSC_CTRL_0 (EOSS3_AIP_BASE + EOSS3_AIP_OSC_CTRL_0_OFFSET)
+#define EOSS3_AIP_OSC_CTRL_1 (EOSS3_AIP_BASE + EOSS3_AIP_OSC_CTRL_1_OFFSET)
+#define EOSS3_AIP_OSC_STA_0 (EOSS3_AIP_BASE + EOSS3_AIP_OSC_STA_0_OFFSET)
+
+/* MISC_LOCK_KEY_CTRL */
+
+#define MISC_LOCK_KEY_CTRL (0x40005310)
+
+/* Register Bitfield Definitions *********************************************/
+
+/* EOSS3_AIP_OSC_CTRL_0 Register */
+
+#define AIP_OSC_CTRL_0_EN (1 << 0)
+#define AIP_OSC_CTRL_0_FREF16K_SEL (1 << 1)
+
+/* EOSS3_AIP_OSC_CTRL_1 Register */
+
+#define AIP_OSC_CTRL_1_PROG_SHIFT (0)
+#define AIP_OSC_CTRL_1_PROG_MASK (0x1fff << AIP_OSC_CTRL_1_PROG_SHIFT)
+
+/* EOSS3_AIP_OSC_STA_0 Register */
+
+#define AIP_OSC_STA_0_LOCK (1 << 0)
+
+/* MISC_LOCK_KEY_CTRL Register */
+#define MISC_LOCK_KEY_CTRL_UNLOCK (0x1acce551)
+#define MISC_LOCK_KEY_CTRL_LOCK (0x00000000)
+
+#endif /* __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_CLOCK_H */
diff --git a/arch/arm/src/eoss3/hardware/eoss3_intr.h b/arch/arm/src/eoss3/hardware/eoss3_intr.h
new file mode 100644
index 0000000..c8d0415
--- /dev/null
+++ b/arch/arm/src/eoss3/hardware/eoss3_intr.h
@@ -0,0 +1,182 @@
+/****************************************************************************
+ * arch/arm/src/eoss3/eoss3_intr.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_INTR_H
+#define __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_INTR_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define EOSS3_INTR_GPIO_OFFSET 0x0000
+#define EOSS3_INTR_GPIO_RAW_OFFSET 0x0004
+#define EOSS3_INTR_GPIO_TYPE_OFFSET 0x0008
+#define EOSS3_INTR_GPIO_POL_OFFSET 0x000c
+#define EOSS3_INTR_GPIO_EN_AP_OFFSET 0x0010
+#define EOSS3_INTR_GPIO_EN_M4_OFFSET 0x0014
+#define EOSS3_INTR_GPIO_EN_FFE0_OFFSET 0x0018
+#define EOSS3_INTR_GPIO_EN_FFE1_OFFSET 0x001C
+#define EOSS3_INTR_OTHER_OFFSET 0x0030
+#define EOSS3_INTR_OTHER_EN_AP_OFFSET 0x0034
+#define EOSS3_INTR_OTHER_EN_M4_OFFSET 0x0038
+#define EOSS3_INTR_SW_1_OFFSET 0x0040
+#define EOSS3_INTR_SW_1_EN_AP_OFFSET 0x0044
+#define EOSS3_INTR_SW_1_EN_M4_OFFSET 0x0048
+#define EOSS3_INTR_SW_2_OFFSET 0x0050
+#define EOSS3_INTR_SW_2_EN_AP_OFFSET 0x0054
+#define EOSS3_INTR_SW_2_EN_M4_OFFSET 0x0058
+#define EOSS3_INTR_FFE_OFFSET 0x0060
+#define EOSS3_INTR_FFE_EN_AP_OFFSET 0x0064
+#define EOSS3_INTR_FFE_EN_M4_OFFSET 0x0068
+#define EOSS3_INTR_FFE1_FB_OFFSET 0x0070
+#define EOSS3_INTR_FFE1_FB_EN_AP_OFFSET 0x0074
+#define EOSS3_INTR_FFE1_FB_EN_M4_OFFSET 0x0078
+#define EOSS3_INTR_FB_OFFSET 0x0080
+#define EOSS3_INTR_FB_RAW_OFFSET 0x0084
+#define EOSS3_INTR_FB_TYPE_OFFSET 0x0088
+#define EOSS3_INTR_FB_POL_OFFSET 0x008c
+#define EOSS3_INTR_FB_EN_AP_OFFSET 0x0090
+#define EOSS3_INTR_FB_EN_M4_OFFSET 0x0094
+#define EOSS3_INTR_M4_MEM_AON_OFFSET 0x00a0
+#define EOSS3_INTR_M4_MEM_AON_EN_OFFSET 0x00a4
+
+/* Register Addresses *******************************************************/
+
+#define EOSS3_INTR_GPIO (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_GPIO_OFFSET)
+#define EOSS3_INTR_GPIO_RAW (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_GPIO_RAW_OFFSET)
+#define EOSS3_INTR_GPIO_TYPE (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_GPIO_TYPE_OFFSET)
+#define EOSS3_INTR_GPIO_POL (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_GPIO_POL_OFFSET)
+#define EOSS3_INTR_GPIO_EN_AP (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_GPIO_EN_AP_OFFSET)
+#define EOSS3_INTR_GPIO_EN_M4 (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_GPIO_EN_M4_OFFSET)
+#define EOSS3_INTR_GPIO_EN_FFE0 (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_GPIO_EN_FFE0_OFFSET)
+#define EOSS3_INTR_GPIO_EN_FFE1 (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_GPIO_EN_FFE1_OFFSET)
+#define EOSS3_INTR_OTHER (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_OTHER_OFFSET)
+#define EOSS3_INTR_OTHER_EN_AP (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_OTHER_EN_AP_OFFSET)
+#define EOSS3_INTR_OTHER_EN_M4 (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_OTHER_EN_M4_OFFSET)
+#define EOSS3_INTR_SW_1 (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_SW_1_OFFSET)
+#define EOSS3_INTR_SW_1_EN_AP (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_SW_1_EN_AP_OFFSET)
+#define EOSS3_INTR_SW_1_EN_M4 (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_SW_1_EN_M4_OFFSET)
+#define EOSS3_INTR_SW_2 (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_SW_2_OFFSET)
+#define EOSS3_INTR_SW_2_EN_AP (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_SW_2_EN_AP_OFFSET)
+#define EOSS3_INTR_SW_2_EN_M4 (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_SW_2_EN_M4_OFFSET)
+#define EOSS3_INTR_FFE (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_FFE_OFFSET)
+#define EOSS3_INTR_FFE_EN_AP (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_FFE_EN_AP_OFFSET)
+#define EOSS3_INTR_FFE_EN_M4 (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_FFE_EN_M4_OFFSET)
+#define EOSS3_INTR_FFE1_FB (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_FFE1_FB_OFFSET)
+#define EOSS3_INTR_FFE1_FB_EN_AP (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_FFE1_FB_EN_AP_OFFSET)
+#define EOSS3_INTR_FFE1_FB_EN_M4 (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_FFE1_FB_EN_M4_OFFSET)
+#define EOSS3_INTR_FB (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_FB_OFFSET)
+#define EOSS3_INTR_FB_RAW (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_FB_RAW_OFFSET)
+#define EOSS3_INTR_FB_TYPE (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_FB_TYPE_OFFSET)
+#define EOSS3_INTR_FB_POL (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_FB_POL_OFFSET)
+#define EOSS3_INTR_FB_EN_AP (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_FB_EN_AP_OFFSET)
+#define EOSS3_INTR_FB_EN_M4 (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_FB_EN_M4_OFFSET)
+#define EOSS3_INTR_M4_MEM_AON (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_M4_MEM_AON_OFFSET)
+#define EOSS3_INTR_M4_MEM_AON_EN (EOSS3_INTR_CTRL_BASE + EOSS3_INTR_M4_MEM_AON_EN_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* EOSS3_INTR_OTHER Register */
+
+#define INTR_M4_SRAM_DET (1 << 0)
+#define INTR_UART_DET (1 << 1)
+#define INTR_TIMER_DET (1 << 2)
+#define INTR_WDT_DET (1 << 3)
+#define INTR_WDT_RST_DET (1 << 4)
+#define INTR_TIMEOUT_DET (1 << 5)
+#define INTR_FPU_DET (1 << 6)
+#define INTR_PKFB_DET (1 << 7)
+#define INTR_I2S_DET (1 << 8)
+#define INTR_AUD_DET (1 << 9)
+#define INTR_SPI_MS_DET (1 << 10)
+#define INTR_CFG_DMA_DET (1 << 11)
+#define INTR_PMU_TMR_DET (1 << 12)
+#define INTR_ADC_DET (1 << 13)
+#define INTR_RTC_DET (1 << 14)
+#define INTR_RST_DET (1 << 15)
+#define INTR_FFE0_DET (1 << 16)
+#define INTR_WDT_FFE_DET (1 << 17)
+#define INTR_APBOOT_EN_DET (1 << 18)
+#define INTR_LPSD_VOICE_DET (1 << 22)
+#define INTR_DMIC_VOICE_DET (1 << 23)
+
+/* EOSS3_INTR_OTHER_EN_AP Register */
+
+#define INTR_M4_SRAM_EN_AP (1 << 0)
+#define INTR_UART_EN_AP (1 << 1)
+#define INTR_TIMER_EN_AP (1 << 2)
+#define INTR_WDT_EN_AP (1 << 3)
+#define INTR_WDT_RST_EN_AP (1 << 4)
+#define INTR_TIMEOUT_EN_AP (1 << 5)
+#define INTR_FPU_EN_AP (1 << 6)
+#define INTR_PKFB_EN_AP (1 << 7)
+#define INTR_I2S_EN_AP (1 << 8)
+#define INTR_AUD_EN_AP (1 << 9)
+#define INTR_SPI_MS_EN_AP (1 << 10)
+#define INTR_CFG_DMA_EN_AP (1 << 11)
+#define INTR_PMU_TMR_EN_AP (1 << 12)
+#define INTR_ADC_EN_AP (1 << 13)
+#define INTR_RTC_EN_AP (1 << 14)
+#define INTR_RST_EN_AP (1 << 15)
+#define INTR_FFE0_EN_AP (1 << 16)
+#define INTR_WDT_FFE_EN_AP (1 << 17)
+#define INTR_APBOOT_EN_AP (1 << 18)
+#define INTR_LD030_PG_EN_AP (1 << 19)
+#define INTR_LD050_PG_EN_AP (1 << 20)
+#define INTR_SRAM_128KB_EN_AP (1 << 21)
+#define INTR_LPSD_VOICE_EN_AP (1 << 22)
+#define INTR_DMIC_VOICE_EN_AP (1 << 23)
+
+/* EOSS3_INTR_OTHER_EN_M4 Register */
+
+#define INTR_M4_SRAM_EN_M4 (1 << 0)
+#define INTR_UART_EN_M4 (1 << 1)
+#define INTR_TIMER_EN_M4 (1 << 2)
+#define INTR_WDT_EN_M4 (1 << 3)
+#define INTR_WDT_RST_EN_M4 (1 << 4)
+#define INTR_TIMEOUT_EN_M4 (1 << 5)
+#define INTR_FPU_EN_M4 (1 << 6)
+#define INTR_PKFB_EN_M4 (1 << 7)
+#define INTR_I2S_EN_M4 (1 << 8)
+#define INTR_AUD_EN_M4 (1 << 9)
+#define INTR_SPI_MS_EN_M4 (1 << 10)
+#define INTR_CFG_DMA_EN_M4 (1 << 11)
+#define INTR_PMU_TMR_EN_M4 (1 << 12)
+#define INTR_ADC_EN_M4 (1 << 13)
+#define INTR_RTC_EN_M4 (1 << 14)
+#define INTR_RST_EN_M4 (1 << 15)
+#define INTR_FFE0_EN_M4 (1 << 16)
+#define INTR_WDT_FFE_EN_M4 (1 << 17)
+#define INTR_APBOOT_EN_M4 (1 << 18)
+#define INTR_LD030_PG_EN_M4 (1 << 19)
+#define INTR_LD050_PG_EN_M4 (1 << 20)
+#define INTR_SRAM_128KB_EN_M4 (1 << 21)
+#define INTR_LPSD_VOICE_EN_M4 (1 << 22)
+#define INTR_DMIC_VOICE_EN_M4 (1 << 23)
+
+#endif /* __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_INTR_H */
diff --git a/arch/arm/src/eoss3/hardware/eoss3_iomux.h b/arch/arm/src/eoss3/hardware/eoss3_iomux.h
new file mode 100644
index 0000000..2fe6f5d
--- /dev/null
+++ b/arch/arm/src/eoss3/hardware/eoss3_iomux.h
@@ -0,0 +1,321 @@
+/****************************************************************************
+ * arch/arm/src/eoss3/eoss3_iomux.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_IOMUX_H
+#define __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_IOMUX_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Compute PAD Control Register Address */
+
+#define EOSS3_PAD_X_CTRL(pad) (EOSS3_IO_MUX_BASE + (pad << 2))
+#define EOSS3_PAD_SEL(idx) (EOSS3_IO_MUX_BASE + 0x100 + ((idx - 1) << 2))
+
+#define EOSS3_IOMUX_PAD_0_CTRL (EOSS3_PAD_X_CTRL(0))
+#define EOSS3_IOMUX_PAD_1_CTRL (EOSS3_PAD_X_CTRL(1))
+#define EOSS3_IOMUX_PAD_2_CTRL (EOSS3_PAD_X_CTRL(2))
+#define EOSS3_IOMUX_PAD_3_CTRL (EOSS3_PAD_X_CTRL(3))
+#define EOSS3_IOMUX_PAD_4_CTRL (EOSS3_PAD_X_CTRL(4))
+#define EOSS3_IOMUX_PAD_5_CTRL (EOSS3_PAD_X_CTRL(5))
+#define EOSS3_IOMUX_PAD_6_CTRL (EOSS3_PAD_X_CTRL(6))
+#define EOSS3_IOMUX_PAD_7_CTRL (EOSS3_PAD_X_CTRL(7))
+#define EOSS3_IOMUX_PAD_8_CTRL (EOSS3_PAD_X_CTRL(8))
+#define EOSS3_IOMUX_PAD_9_CTRL (EOSS3_PAD_X_CTRL(9))
+#define EOSS3_IOMUX_PAD_10_CTRL (EOSS3_PAD_X_CTRL(10))
+#define EOSS3_IOMUX_PAD_11_CTRL (EOSS3_PAD_X_CTRL(11))
+#define EOSS3_IOMUX_PAD_12_CTRL (EOSS3_PAD_X_CTRL(12))
+#define EOSS3_IOMUX_PAD_13_CTRL (EOSS3_PAD_X_CTRL(13))
+#define EOSS3_IOMUX_PAD_14_CTRL (EOSS3_PAD_X_CTRL(14))
+#define EOSS3_IOMUX_PAD_15_CTRL (EOSS3_PAD_X_CTRL(15))
+#define EOSS3_IOMUX_PAD_16_CTRL (EOSS3_PAD_X_CTRL(16))
+#define EOSS3_IOMUX_PAD_17_CTRL (EOSS3_PAD_X_CTRL(17))
+#define EOSS3_IOMUX_PAD_18_CTRL (EOSS3_PAD_X_CTRL(18))
+#define EOSS3_IOMUX_PAD_19_CTRL (EOSS3_PAD_X_CTRL(19))
+#define EOSS3_IOMUX_PAD_20_CTRL (EOSS3_PAD_X_CTRL(20))
+#define EOSS3_IOMUX_PAD_21_CTRL (EOSS3_PAD_X_CTRL(21))
+#define EOSS3_IOMUX_PAD_22_CTRL (EOSS3_PAD_X_CTRL(22))
+#define EOSS3_IOMUX_PAD_23_CTRL (EOSS3_PAD_X_CTRL(23))
+#define EOSS3_IOMUX_PAD_24_CTRL (EOSS3_PAD_X_CTRL(24))
+#define EOSS3_IOMUX_PAD_25_CTRL (EOSS3_PAD_X_CTRL(25))
+#define EOSS3_IOMUX_PAD_26_CTRL (EOSS3_PAD_X_CTRL(26))
+#define EOSS3_IOMUX_PAD_27_CTRL (EOSS3_PAD_X_CTRL(27))
+#define EOSS3_IOMUX_PAD_28_CTRL (EOSS3_PAD_X_CTRL(28))
+#define EOSS3_IOMUX_PAD_29_CTRL (EOSS3_PAD_X_CTRL(29))
+#define EOSS3_IOMUX_PAD_30_CTRL (EOSS3_PAD_X_CTRL(30))
+#define EOSS3_IOMUX_PAD_31_CTRL (EOSS3_PAD_X_CTRL(31))
+#define EOSS3_IOMUX_PAD_32_CTRL (EOSS3_PAD_X_CTRL(32))
+#define EOSS3_IOMUX_PAD_33_CTRL (EOSS3_PAD_X_CTRL(33))
+#define EOSS3_IOMUX_PAD_34_CTRL (EOSS3_PAD_X_CTRL(34))
+#define EOSS3_IOMUX_PAD_35_CTRL (EOSS3_PAD_X_CTRL(35))
+#define EOSS3_IOMUX_PAD_36_CTRL (EOSS3_PAD_X_CTRL(36))
+#define EOSS3_IOMUX_PAD_37_CTRL (EOSS3_PAD_X_CTRL(37))
+#define EOSS3_IOMUX_PAD_38_CTRL (EOSS3_PAD_X_CTRL(38))
+#define EOSS3_IOMUX_PAD_39_CTRL (EOSS3_PAD_X_CTRL(39))
+#define EOSS3_IOMUX_PAD_40_CTRL (EOSS3_PAD_X_CTRL(40))
+#define EOSS3_IOMUX_PAD_41_CTRL (EOSS3_PAD_X_CTRL(41))
+#define EOSS3_IOMUX_PAD_42_CTRL (EOSS3_PAD_X_CTRL(42))
+#define EOSS3_IOMUX_PAD_43_CTRL (EOSS3_PAD_X_CTRL(43))
+#define EOSS3_IOMUX_PAD_44_CTRL (EOSS3_PAD_X_CTRL(44))
+#define EOSS3_IOMUX_PAD_45_CTRL (EOSS3_PAD_X_CTRL(45))
+
+/* IO_REG Select Register Address */
+
+#define EOSS3_IO_REG_SEL_OFFSET (0x160)
+#define EOSS3_IO_REG_SEL (EOSS3_IO_REG_SEL_OFFSET + EOSS3_IO_MUX_BASE)
+
+/* MISC IO Register Addresses */
+
+#define EOSS3_MISC_IO_INPUT_OFFSET (0x100)
+#define EOSS3_MISC_IO_OUTPUT_OFFSET (0x104)
+
+#define EOSS3_MISC_IO_INPUT (EOSS3_MISC_IO_INPUT_OFFSET + EOSS3_MISC_BASE)
+#define EOSS3_MISC_IO_OUTPUT (EOSS3_MISC_IO_OUTPUT_OFFSET + EOSS3_MISC_BASE)
+
+/* Pad Control Register [13:0] */
+
+#define PAD_CTRL_MASK (0x1fff)
+#define PAD_FUNC_SEL_SHIFT (0)
+#define PAD_FUNC_SEL_MASK (0x3 << PAD_FUNC_SEL_SHIFT)
+#define PAD_CTRL_SEL_SHIFT (3)
+#define PAD_CTRL_SEL_MASK (0x3 << PAD_CTRL_SEL_SHIFT)
+#define PAD_OEN (1 << 5)
+#define PAD_P_SHIFT (1 << 6)
+#define PAD_P_MASK (0x3 << PAD_P_SHIFT)
+#define PAD_E_SHIFT (1 << 8)
+#define PAD_E_MASK (0x3 << PAD_E_SHIFT)
+#define PAD_SR (1 << 10)
+#define PAD_REN (1 << 11)
+#define PAD_SMT (1 << 12)
+
+#define PAD_FUNC_0 (0x0 << PAD_FUNC_SEL_SHIFT)
+#define PAD_FUNC_1 (0x1 << PAD_FUNC_SEL_SHIFT)
+#define PAD_FUNC_2 (0x2 << PAD_FUNC_SEL_SHIFT)
+#define PAD_FUNC_3 (0x3 << PAD_FUNC_SEL_SHIFT)
+
+#define PAD_CTRL_A0 (0x0 << PAD_CTRL_SEL_SHIFT)
+#define PAD_CTRL_OTHER (0x1 << PAD_CTRL_SEL_SHIFT)
+#define PAD_CTRL_FABRIC (0x2 << PAD_CTRL_SEL_SHIFT)
+
+#define PAD_HIGHZ (0)
+#define PAD_PULLUP (0x1 << PAD_P_SHIFT)
+#define PAD_PULLDOWN (0x2 << PAD_P_SHIFT)
+#define PAD_KEEP (0x3 << PAD_P_SHIFT)
+
+#define PAD_SR_SLOW (0)
+#define PAD_SR_FAST (PAD_SR)
+
+/* Input PAD Selection
+ * These vales are packed sel_val[2:0] idx[8:3]
+ * idx can be converted to the SEL address with EOSS3_PAD_SEL(idx)
+ * idx of 0 is used to indicate no PAD_SEL input feature should be configured
+ */
+
+#define EOSS3_PAD_SEL_IDX_SHIFT (3)
+#define EOSS3_PAD_SEL_IDX_MASK (0x3f << EOSS3_PAD_SEL_IDX_SHIFT)
+#define EOSS3_PAD_SEL_VAL_MASK (0x7)
+
+#define SDA0_SEL_1 (0x0 | (1 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SDA0_SEL_P1 (0x1 | (1 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define SDA1_SEL_1 (0x0 | (2 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SDA1_SEL_P15 (0x1 | (2 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SDA1_SEL_P32 (0x2 | (2 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SDA1_SEL_P44 (0x3 | (2 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define SDA2_SEL_1 (0x0 | (3 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SDA2_SEL_P41 (0x1 | (3 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define SCL0_SEL_1 (0x0 | (4 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SCL0_SEL_P0 (0x1 | (4 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define SCL1_SEL_1 (0x0 | (5 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SCL1_SEL_P14 (0x1 | (5 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SCL1_SEL_P33 (0x2 | (5 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SCL1_SEL_P45 (0x3 | (5 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define SCL2_SEL_1 (0x0 | (6 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SCL2_SEL_P40 (0x1 | (6 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define SPIS_CLK_SEL_P16 (0x0 | (7 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SPIS_CLK_SEL_0 (0x1 | (7 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define SPIS_SSN_SEL_P20 (0x0 | (8 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SPIS_SSN_SEL_0 (0x1 | (8 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define SPIS_MOSI_SEL_P19 (0x0 | (9 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SPIS_MOSI_SEL_0 (0x1 | (9 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define SPIM_MISO_SEL_P36 (0x0 | (10 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SPIM_MISO_SEL_0 (0x1 | (10 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define PDM_DATA_SEL_0 (0x0 | (11 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define PDM_DATA_SEL_P10 (0x1 | (11 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define PDM_DATA_SEL_P28 (0x2 | (11 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define I2S_DATA_SEL_0 (0x0 | (12 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define I2S_DATA_SEL_P10 (0x1 | (12 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define I2S_DATA_SEL_P28 (0x2 | (12 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define FCLK_SEL_P2 (0x0 | (13 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define FCLK_SEL_P7 (0x1 | (13 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define FCLK_SEL_P10 (0x2 | (13 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define FCLK_SEL_P26 (0x3 | (13 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define FCLK_SEL_P27 (0x4 | (13 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define FCLK_SEL_L (0x6 | (13 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define FCLK_SEL_H (0x7 | (13 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define UART_RXD_SEL_0 (0x0 | (14 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define UART_RXD_SEL_P14 (0x1 | (14 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define UART_RXD_SEL_P16 (0x2 | (14 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define UART_RXD_SEL_P25 (0x3 | (14 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define UART_RXD_SEL_P45 (0x4 | (14 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define IRDA_DIRIN_SEL_0 (0x0 | (15 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define IRDA_DIRIN_SEL_P6 (0x1 | (15 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define IRDA_DIRIN_SEL_P15 (0x2 | (15 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define IRDA_DIRIN_SEL_P21 (0x3 | (15 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define IRDA_DIRIN_SEL_P24 (0x4 | (15 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define IRDA_DIRIN_SEL_P28 (0x5 | (15 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define IRDA_DIRIN_SEL_P40 (0x6 | (15 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define IRDA_DIRIN_SEL_P44 (0x7 | (15 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define S_INTR_0_SEL_0 (0x0 | (16 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_0_SEL_P3 (0x1 | (16 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define S_INTR_1_SEL_0 (0x0 | (17 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_1_SEL_P2 (0x1 | (17 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_1_SEL_P6 (0x2 | (17 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_1_SEL_P18 (0x3 | (17 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_1_SEL_P24 (0x4 | (17 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_1_SEL_P35 (0x5 | (17 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_1_SEL_P36 (0x6 | (17 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define S_INTR_2_SEL_0 (0x0 | (18 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_2_SEL_P4 (0x1 | (18 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_2_SEL_P8 (0x2 | (18 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_2_SEL_P21 (0x3 | (18 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_2_SEL_P25 (0x4 | (18 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_2_SEL_P37 (0x5 | (18 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_2_SEL_P38 (0x6 | (18 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define S_INTR_3_SEL_0 (0x0 | (19 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_3_SEL_P5 (0x1 | (19 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_3_SEL_P8 (0x2 | (19 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_3_SEL_P22 (0x3 | (19 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_3_SEL_P28 (0x4 | (19 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_3_SEL_P39 (0x5 | (19 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_3_SEL_P40 (0x6 | (19 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define S_INTR_4_SEL_0 (0x0 | (20 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_4_SEL_P7 (0x1 | (20 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_4_SEL_P10 (0x2 | (20 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_4_SEL_P26 (0x3 | (20 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_4_SEL_P29 (0x4 | (20 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_4_SEL_P44 (0x5 | (20 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define S_INTR_5_SEL_0 (0x0 | (21 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_5_SEL_P11 (0x1 | (21 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_5_SEL_P14 (0x2 | (21 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_5_SEL_P27 (0x3 | (21 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_5_SEL_P30 (0x4 | (21 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_5_SEL_P45 (0x5 | (21 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define S_INTR_6_SEL_0 (0x0 | (22 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_6_SEL_P12 (0x1 | (22 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_6_SEL_P15 (0x2 | (22 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_6_SEL_P31 (0x3 | (22 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_6_SEL_P32 (0x4 | (22 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_6_SEL_P41 (0x5 | (22 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define S_INTR_7_SEL_0 (0x0 | (23 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_7_SEL_P13 (0x1 | (23 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_7_SEL_P23 (0x2 | (23 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_7_SEL_P33 (0x3 | (23 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_7_SEL_P34 (0x4 | (23 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define S_INTR_7_SEL_P42 (0x5 | (23 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define NUARTCTS_SEL_0 (0x0 | (24 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define NUARTCTS_SEL_P17 (0x1 | (24 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define NUARTCTS_SEL_P22 (0x2 | (24 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define SW_CLK_SEL_P14_45 (0x0 | (29 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SW_CLK_SEL_0 (0x1 | (29 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define SW_IO_SEL_P15_44 (0x0 | (30 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SW_IO_SEL_0 (0x1 | (30 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define FBIO_SEL_1_0 (0x0 | (33 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define FBIO_SEL_1_PAD (0x1 | (33 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define FBIO_SEL_2_0 (0x0 | (34 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define FBIO_SEL_2_PAD (0x1 | (34 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define SPI_SENS_MISO_SEL_0 (0x0 | (37 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SPI_SENS_MISO_SEL_P8 (0x1 | (37 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SPI_SENS_MISO_SEL_P29 (0x2 | (37 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define SPI_SENS_MOSI_SEL_0 (0x0 | (38 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SPI_SENS_MOSI_SEL_P6 (0x1 | (38 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define SPI_SENS_MOSI_SEL_P28 (0x2 | (38 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define I2S_WD_CLKIN_SEL_0 (0x0 | (41 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define I2S_WD_CLKIN_SEL_P23 (0x1 | (41 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define I2S_CLKIN_SEL_0 (0x0 | (42 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define I2S_CLKIN_SEL_P31 (0x1 | (42 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define PDM_STAT_IN_SEL_0 (0x0 | (43 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define PDM_STAT_IN_SEL_P9 (0x0 | (43 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define PDM_STAT_IN_SEL_P30 (0x0 | (43 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+#define PDM_CLKIN_SEL_0 (0x0 | (44 << EOSS3_PAD_SEL_IDX_SHIFT))
+#define PDM_CLKIN_SEL_P38 (0x0 | (44 << EOSS3_PAD_SEL_IDX_SHIFT))
+
+/* IO_REG Select Register */
+
+#define IO_REG_P6 (0) /* Low Enable */
+#define IO_REG_P24 (0) /* High Enable */
+#define IO_REG_P9 (1) /* Low Enable */
+#define IO_REG_P26 (1) /* High Enable */
+#define IO_REG_P11 (2) /* Low Enable */
+#define IO_REG_P28 (2) /* High Enable */
+#define IO_REG_P14 (3) /* Low Enable */
+#define IO_REG_P30 (3) /* High Enable */
+#define IO_REG_P18 (4) /* Low Enable */
+#define IO_REG_P31 (4) /* High Enable */
+#define IO_REG_P21 (5) /* Low Enable */
+#define IO_REG_P36 (5) /* High Enable */
+#define IO_REG_P22 (6) /* Low Enable */
+#define IO_REG_P38 (6) /* High Enable */
+#define IO_REG_P23 (7) /* Low Enable */
+#define IO_REG_P45 (7) /* High Enable */
+#define IO_REG_MASK (7)
+
+#define IO_REG_START_HI_PAD (24) /* First pad where enable is high */
+
+#endif /* __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_IOMUX_H */
diff --git a/arch/arm/src/eoss3/hardware/eoss3_memorymap.h b/arch/arm/src/eoss3/hardware/eoss3_memorymap.h
new file mode 100644
index 0000000..46a95f5
--- /dev/null
+++ b/arch/arm/src/eoss3/hardware/eoss3_memorymap.h
@@ -0,0 +1,73 @@
+/****************************************************************************
+ * arch/arm/src/eoss3/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_MEMORYMAP_H
+#define __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_MEMORYMAP_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Address Blocks ***********************************************************/
+
+#define EOSS3_CODE_BASE 0x00000000
+#define EOSS3_SRAM_BASE 0x20000000
+#define EOSS3_PERIPH_BASE 0x40000000
+#define EOSS3_CORTEX_BASE 0xe0000000
+
+/* Peripheral Base Addresses ************************************************/
+
+#define EOSS3_PERIPH_BASE 0x40000000
+#define EOSS3_PKT_FIFO_BASE 0x40002000
+#define EOSS3_CLK_BASE 0x40004000
+#define EOSS3_PMU_BASE 0x40004400
+#define EOSS3_INTR_CTRL_BASE 0x40004800
+#define EOSS3_IO_MUX_BASE 0x40004c00
+#define EOSS3_MISC_BASE 0x40005000
+#define EOSS3_AIP_BASE 0x40005400
+#define EOSS3_JTM_BASE 0x40005a00
+#define EOSS3_SPT_BASE 0x40005c00
+#define EOSS3_A1_BASE 0x40006000
+#define EOSS3_SPI_BASE 0x40007000
+#define EOSS3_DMA_SPI_BASE 0x40007400
+#define EOSS3_EFUSE_BASE 0x40008000
+#define EOSS3_I2S_BASE 0x4000b000
+#define EOSS3_SDMA_BASE 0x4000c000
+#define EOSS3_SDMA_BRG_BASE 0x4000d000
+#define EOSS3_SDMA_SRAM_BASE 0x4000f000
+#define EOSS3_UART_BASE 0x40010000
+#define EOSS3_WDT_BASE 0x40012000
+#define EOSS3_TIMER_BASE 0x40013000
+#define EOSS3_PIF_BASE 0x40014000
+#define EOSS3_AUD_BASE 0x40015000
+#define EOSS3_RAMFIFO0_BASE 0x40018000
+#define EOSS3_RAMFIFO1_BASE 0x40019000
+#define EOSS3_RAMFIFO2_BASE 0x4001a000
+#define EOSS3_RAMFIFO3_BASE 0x4001b000
+#define EOSS3_FABRIC_BASE 0x40020000
+#define EOSS3_FFE_BASE 0x40040000
+#define EOSS3_CM_BASE 0x40050000
+#define EOSS3_ITM_BASE 0xe0000000
+#define EOSS3_DWT_BASE 0xe0001000
+#define EOSS3_FBP_BASE 0xe0002000
+#define EOSS3_SCS_BASE 0xe000e000
+#define EOSS3_TPIU_BASE 0xe0040000
+#define EOSS3_DAP_BASE 0xe00ff000
+
+#endif /* __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_MEMORYMAP_H */
diff --git a/arch/arm/src/eoss3/hardware/eoss3_uart.h b/arch/arm/src/eoss3/hardware/eoss3_uart.h
new file mode 100644
index 0000000..61f6903
--- /dev/null
+++ b/arch/arm/src/eoss3/hardware/eoss3_uart.h
@@ -0,0 +1,169 @@
+/****************************************************************************
+ * arch/arm/src/eoss3/eoss3_uart.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_UART_H
+#define __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_UART_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define EOSS3_UART_DR_OFFSET 0x0000 /* Data Register */
+#define EOSS3_UART_RSR_ECR_OFFSET 0x0004 /* Status Reg / Error Clear Reg */
+#define EOSS3_UART_TFR_OFFSET 0x0018 /* Flag Register */
+#define EOSS3_UART_ILPRDIV_OFFSET 0x0020 /* Low Power Divisor */
+#define EOSS3_UART_IBRD_OFFSET 0x0024 /* Integer Baud Rate Divisor */
+#define EOSS3_UART_FBRD_OFFSET 0x0028 /* Fractional Baud Rate Divisor */
+#define EOSS3_UART_LCR_H_OFFSET 0x002c /* UART Line Control Register */
+#define EOSS3_UART_CR_OFFSET 0x0030 /* UART Control Register */
+#define EOSS3_UART_IFLS_OFFSET 0x0034 /* Interrupt FIFO Level Select */
+#define EOSS3_UART_IMSC_OFFSET 0x0038 /* Interrupt Mask Set/Clear */
+#define EOSS3_UART_RIS_OFFSET 0x003c /* Raw Interrupt Status Register */
+#define EOSS3_UART_MIS_OFFSET 0x0040 /* Masked Interrupt Status */
+#define EOSS3_UART_ICR_OFFSET 0x0044 /* Interrupt Clear Register */
+
+/* Register Addresses *******************************************************/
+
+#define EOSS3_UART_DR (EOSS3_UART_BASE + EOSS3_UART_DR_OFFSET)
+#define EOSS3_UART_RSR_ECR (EOSS3_UART_BASE + EOSS3_UART_RSR_ECR_OFFSET)
+#define EOSS3_UART_TFR (EOSS3_UART_BASE + EOSS3_UART_TFR_OFFSET)
+#define EOSS3_UART_ILPRDIV (EOSS3_UART_BASE + EOSS3_UART_ILPRDIV_OFFSET)
+#define EOSS3_UART_IBRD (EOSS3_UART_BASE + EOSS3_UART_IBRD_OFFSET)
+#define EOSS3_UART_FBRD (EOSS3_UART_BASE + EOSS3_UART_FBRD_OFFSET)
+#define EOSS3_UART_LCR_H (EOSS3_UART_BASE + EOSS3_UART_LCR_H_OFFSET)
+#define EOSS3_UART_CR (EOSS3_UART_BASE + EOSS3_UART_CR_OFFSET)
+#define EOSS3_UART_IFLS (EOSS3_UART_BASE + EOSS3_UART_IFLS_OFFSET)
+#define EOSS3_UART_IMSC (EOSS3_UART_BASE + EOSS3_UART_IMSC_OFFSET)
+#define EOSS3_UART_RIS (EOSS3_UART_BASE + EOSS3_UART_RIS_OFFSET)
+#define EOSS3_UART_MIS (EOSS3_UART_BASE + EOSS3_UART_MIS_OFFSET)
+#define EOSS3_UART_ICR (EOSS3_UART_BASE + EOSS3_UART_ICR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* EOSS3_UART_DR Register */
+
+#define UART_DR_DATA_SHIFT (0)
+#define UART_DR_DATA_MASK (0xff << UART_DR_DATA_SHIFT)
+#define UART_DR_FE (1 << 8)
+#define UART_DR_PE (1 << 9)
+#define UART_DR_BE (1 << 10)
+#define UART_DR_OE (1 << 11)
+
+/* EOSS3_UART_RSR_ECR Register */
+
+#define UART_RSR_ECR_FE (1 << 0)
+#define UART_RST_ECR_PE (1 << 1)
+#define UART_RSR_ECR_BE (1 << 2)
+#define UART_RSR_ECR_OE (1 << 3)
+
+/* EOSS3_UART_TFR Register */
+
+#define UART_TFR_CTS (1 << 0)
+#define UART_TFR_DSR (1 << 1)
+#define UART_TFR_DCD (1 << 2)
+#define UART_TFR_BUSY (1 << 3)
+#define UART_TFR_RXFE (1 << 4)
+#define UART_TFR_TXFF (1 << 5)
+#define UART_TFR_RXFF (1 << 6)
+#define UART_TFR_TXFE (1 << 7)
+#define UART_TFR_RI (1 << 8)
+
+/* EOSS3_UART_LCR_H Register */
+
+#define UART_LCR_H_BRK (1 << 0)
+#define UART_LCR_H_PEN (1 << 1)
+#define UART_LCR_H_EPS (1 << 2)
+#define UART_LCR_H_STP2 (1 << 3)
+#define UART_LCR_H_FEN (1 << 4)
+#define UART_LCR_H_WLEN_SHIFT (5)
+#define UART_LCR_H_WLEN_MASK (0x3 << UART_LCR_H_WLEN_SHIFT)
+#define UART_LCR_H_WLE_5 (0x0 << UART_LCR_H_WLEN_SHIFT)
+#define UART_LCR_H_WLE_6 (0x1 << UART_LCR_H_WLEN_SHIFT)
+#define UART_LCR_H_WLE_7 (0x2 << UART_LCR_H_WLEN_SHIFT)
+#define UART_LCR_H_WLE_8 (0x3 << UART_LCR_H_WLEN_SHIFT)
+#define UART_LCR_H_SPS (1 << 7)
+
+/* EOSS3_UART_CR Register */
+
+#define UART_CR_UARTEN (1 << 0)
+#define UART_CR_SIREN (1 << 1)
+#define UART_CR_SIRLP (1 << 2)
+#define UART_CR_LBE (1 << 7)
+#define UART_CR_TXE (1 << 8)
+#define UART_CR_RXE (1 << 9)
+#define UART_CR_DTR (1 << 10)
+#define UART_CR_RTS (1 << 11)
+#define UART_CR_OUT1 (1 << 12)
+#define UART_CR_OUT2 (1 << 13)
+#define UART_CR_RTSEN (1 << 14)
+#define UART_CR_CTSEN (1 << 15)
+
+/* EOSS3_UART_IMSC Register */
+
+#define UART_IMSC_RIMIM (1 << 0)
+#define UART_IMSC_CTSMIM (1 << 1)
+#define UART_IMSC_DCDMIM (1 << 2)
+#define UART_IMSC_DSRMIM (1 << 3)
+#define UART_IMSC_RXIM (1 << 4)
+#define UART_IMSC_TXIM (1 << 5)
+#define UART_IMSC_RTIM (1 << 6)
+#define UART_IMSC_FEIM (1 << 7)
+#define UART_IMSC_PEIM (1 << 8)
+#define UART_IMSC_BEIM (1 << 9)
+#define UART_IMSC_OEIM (1 << 10)
+#define UART_IMSC_ALLINTS (0x7ff)
+
+/* EOSS3_UART_IMSC Register */
+
+#define UART_MIS_RIMMIS (1 << 0)
+#define UART_MIS_CTSMMIS (1 << 1)
+#define UART_MIS_DCDMMIS (1 << 2)
+#define UART_MIS_DSRMMIS (1 << 3)
+#define UART_MIS_RXMIS (1 << 4)
+#define UART_MIS_TXMIS (1 << 5)
+#define UART_MIS_RTMIS (1 << 6)
+#define UART_MIS_FEMIS (1 << 7)
+#define UART_MIS_PEMIS (1 << 8)
+#define UART_MIS_BEMIS (1 << 9)
+#define UART_MIS_OEMIS (1 << 10)
+
+/* EOSS3_UART_ICR Register */
+
+#define UART_ICR_RIMIC (1 << 0)
+#define UART_ICR_CTSMIC (1 << 1)
+#define UART_ICR_DCDMIC (1 << 2)
+#define UART_ICR_DSRMIC (1 << 3)
+#define UART_ICR_RXIC (1 << 4)
+#define UART_ICR_TXIC (1 << 5)
+#define UART_ICR_RTIC (1 << 6)
+#define UART_ICR_FEIC (1 << 7)
+#define UART_ICR_PEIC (1 << 8)
+#define UART_ICR_BEIC (1 << 9)
+#define UART_ICR_OEIC (1 << 10)
+
+#endif /* __ARCH_ARM_SRC_EOSS3_HARDWARE_EOSS3_UART_H */
diff --git a/boards/Kconfig b/boards/Kconfig
index 6692f50..63ad8ec 100644
--- a/boards/Kconfig
+++ b/boards/Kconfig
@@ -178,6 +178,16 @@ config ARCH_BOARD_EKKLM3S9B96
TI/Stellaris EKK-LM3S9B96 board. This board is based on the
an EKK-LM3S9B96 which is a Cortex-M3.
+config ARCH_BOARD_QUICKFEATHER
+ bool "EOS S3 QuickFeather"
+ depends on ARCH_CHIP_EOSS3
+ select ARCH_HAVE_LEDS
+ ---help---
+ QuickLogic EOS S3 QuickFeather board. This is the feather form factor
+ low cost development board. This includes 16-Mbit external flash,
+ MC3635 accelerometer, DPS310 pressure sensor, IM69D130 PDM microphone,
+ internal programmable FPGA fabric.
+
config ARCH_BOARD_ESP32CORE
bool "Espressif ESP32 Core board V2"
depends on ARCH_CHIP_ESP32
@@ -2126,6 +2136,7 @@ config ARCH_BOARD
default "efm32-g8xx-stk" if ARCH_BOARD_EFM32G8XXSTK
default "efm32gg-stk3700" if ARCH_BOARD_EFM32GG_STK3700
default "ekk-lm3s9b96" if ARCH_BOARD_EKKLM3S9B96
+ default "quickfeather" if ARCH_BOARD_QUICKFEATHER
default "esp32-core" if ARCH_BOARD_ESP32CORE
default "ez80f910200kitg" if ARCH_BOARD_EZ80F910200KITG
default "ez80f910200zco" if ARCH_BOARD_EZ80F910200ZCO
diff --git a/boards/arm/eoss3/quickfeather/Kconfig b/boards/arm/eoss3/quickfeather/Kconfig
new file mode 100644
index 0000000..093bd1e
--- /dev/null
+++ b/boards/arm/eoss3/quickfeather/Kconfig
@@ -0,0 +1,8 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_QUICKFEATHER
+
+endif
diff --git a/boards/arm/eoss3/quickfeather/README.txt b/boards/arm/eoss3/quickfeather/README.txt
new file mode 100644
index 0000000..e69de29
diff --git a/boards/arm/eoss3/quickfeather/configs/nsh/defconfig b/boards/arm/eoss3/quickfeather/configs/nsh/defconfig
new file mode 100644
index 0000000..a087320
--- /dev/null
+++ b/boards/arm/eoss3/quickfeather/configs/nsh/defconfig
@@ -0,0 +1,48 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="quickfeather"
+CONFIG_ARCH_BOARD_QUICKFEATHER=y
+CONFIG_ARCH_CHIP="eoss3"
+CONFIG_ARCH_CHIP_EOSS3=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=61440
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_ERROR=y
+CONFIG_DEBUG_FEATURES=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEBUG_WARN=y
+CONFIG_DISABLE_MQUEUE=y
+CONFIG_EOSS3_UART=y
+CONFIG_EXAMPLES_HELLO=y
+CONFIG_FS_PROCFS=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_IFCONFIG=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_MOTD=y
+CONFIG_NSH_MOTD_STRING="Hello from Apache NuttX on QuickFeather"
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_RAM_SIZE=262144
+CONFIG_RAM_START=0x20040000
+CONFIG_RAW_BINARY=y
+CONFIG_STACK_COLORATION=y
+CONFIG_SYSTEM_CLE=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TESTING_GETPRIME=y
+CONFIG_TESTING_MM=y
+CONFIG_TESTING_OSTEST=y
+CONFIG_TESTING_OSTEST_NBARRIER_THREADS=3
+CONFIG_TESTING_OSTEST_STACKSIZE=4096
+CONFIG_UART_SERIAL_CONSOLE=y
+CONFIG_USERMAIN_STACKSIZE=4096
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_WDOG_INTRESERVE=2
diff --git a/boards/arm/eoss3/quickfeather/include/board.h b/boards/arm/eoss3/quickfeather/include/board.h
new file mode 100644
index 0000000..ef0b0f5
--- /dev/null
+++ b/boards/arm/eoss3/quickfeather/include/board.h
@@ -0,0 +1,66 @@
+/****************************************************************************
+ * boards/arm/eoss3/quickfeather/include/board.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM_EOSS3_QUICKFEATHER_INCLUDE_BOARD_H
+#define __BOARDS_ARM_EOSS3_QUICKFEATHER_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "eoss3_gpio.h"
+
+#define BOARD_HCLK_FREQUENCY 79790000
+#define BOARD_CPU_FREQUENCY 79790000
+
+/* LED definitions **********************************************************/
+
+#define LED_STARTED 0 /* LED off */
+#define LED_HEAPALLOCATE 0 /* LED off */
+#define LED_IRQSENABLED 0 /* LED off */
+#define LED_STACKCREATED 1 /* LED on */
+#define LED_INIRQ 2 /* LED no change */
+#define LED_SIGNAL 2 /* LED no change */
+#define LED_ASSERTION 2 /* LED no change */
+#define LED_PANIC 3 /* LED flashing */
+
+#define GPIO_LED_B ((IO_REG_P18 << GPIO_REG_BIT_SHIFT) | \
+ (GPIO_REG_EN_MASK) | \
+ ((PAD_FUNC_3) << GPIO_CTRL_SHIFT) | \
+ GPIO_PIN18)
+#define GPIO_LED_G ((IO_REG_P21 << GPIO_REG_BIT_SHIFT) | \
+ (GPIO_REG_EN_MASK) | \
+ ((PAD_FUNC_3) << GPIO_CTRL_SHIFT) | \
+ GPIO_PIN21)
+#define GPIO_LED_R ((IO_REG_P22 << GPIO_REG_BIT_SHIFT) | \
+ (GPIO_REG_EN_MASK) | \
+ ((PAD_FUNC_3) << GPIO_CTRL_SHIFT) | \
+ GPIO_PIN22)
+
+/* UART definitions *********************************************************/
+
+#define GPIO_UART_RX ((UART_RXD_SEL_P45 << GPIO_INPUT_SEL_SHIFT) | \
+ ((PAD_OEN | PAD_REN) << GPIO_CTRL_SHIFT) | \
+ GPIO_PIN45)
+
+#define GPIO_UART_TX (((PAD_FUNC_3) << GPIO_CTRL_SHIFT) | GPIO_PIN44)
+
+#endif /* __BOARDS_ARM_EOSS3_QUICKFEATHER_INCLUDE_BOARD_H */
diff --git a/boards/arm/eoss3/quickfeather/scripts/Make.defs b/boards/arm/eoss3/quickfeather/scripts/Make.defs
new file mode 100644
index 0000000..802913f
--- /dev/null
+++ b/boards/arm/eoss3/quickfeather/scripts/Make.defs
@@ -0,0 +1,95 @@
+############################################################################
+# boards/arm/stm32/stm32f4discovery/scripts/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/.config
+include $(TOPDIR)/tools/Config.mk
+include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
+
+LDSCRIPT = ld.script
+
+CINCPATH := ${shell $(INCDIR) -s "$(CC)" $(TOPDIR)$(DELIM)include}
+CXXINCPATH := ${shell $(INCDIR) -s "$(CC)" $(TOPDIR)$(DELIM)include$(DELIM)cxx}
+
+ARCHINCLUDES += $(CINCPATH)
+ARCHXXINCLUDES += $(CINCPATH) $(CXXINCPATH)
+
+ifeq ($(CONFIG_CYGWIN_WINTOOL),y)
+ ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}"
+else
+ ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
+endif
+
+LD = $(CROSSDEV)ld
+STRIP = $(CROSSDEV)strip --strip-unneeded
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+ifeq ($(CONFIG_ARMV7M_TOOLCHAIN_CLANGL),y)
+ ARCHCCVERSION = {shell $(CC) -v 2>&1 | sed -n '/clang version/p' | sed -e 's/.* clang version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g'}
+ HOSTCC = clang
+ CC = clang
+ CXX = clang++
+ CPP = clang -E
+ ARCHCFLAGS += -nostdlib -ffreestanding -target arm-none-eabi -march=armv7-m -mcpu=cortex-m4
+ ARCHCXXFLAGS += -nostdlib -ffreestanding -target arm-none-eabi -march=armv7-m -mcpu=cortex-m4 -DCONFIG_WCHAR_BUILTIN
+else
+ ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ HOSTCC = gcc
+ CC = $(CROSSDEV)gcc
+ CXX = $(CROSSDEV)g++
+ CPP = $(CROSSDEV)gcc -E
+ ARCHCFLAGS += -funwind-tables
+ ARCHCXXFLAGS += -fno-rtti -funwind-tables
+ ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += -fno-strength-reduce
+ endif
+
+endif
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
diff --git a/boards/arm/eoss3/quickfeather/scripts/ld.script b/boards/arm/eoss3/quickfeather/scripts/ld.script
new file mode 100644
index 0000000..e973825
--- /dev/null
+++ b/boards/arm/eoss3/quickfeather/scripts/ld.script
@@ -0,0 +1,105 @@
+/****************************************************************************
+ * boards/arm/eoss3/quickfeather/scripts/ld.script
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+/* There are complications here that I don't fully understand. It looks like
+ * the memory region 0x0000_0000 to 0x0000_8000 is ROM/Flash but is mirrored
+ * up to 0x2000_0000 so we need to keep the sram region outside of the
+ * mirrored code or we will run into issues.
+ */
+
+MEMORY
+{
+ /* flash (rx) : ORIGIN = 0x00000000, LENGTH = 2M */
+ /* sram (rwx) : ORIGIN = 0x20000000, LENGTH = 512K */
+ flash (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+ sram (rwx) : ORIGIN = 0x20027000, LENGTH = 512K - 0x00040000
+}
+
+OUTPUT_ARCH(arm)
+ENTRY(_stext)
+EXTERN(_vectors)
+SECTIONS
+{
+ .text : {
+ _stext = ABSOLUTE(.);
+ *(.vectors)
+ *(.text .text.*)
+ *(.fixup)
+ *(.gnu.warning)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.got)
+ *(.gcc_except_table)
+ *(.gnu.linkonce.r.*)
+ _etext = ABSOLUTE(.);
+ } > flash
+
+ .init_section : ALIGN(4) {
+ _sinit = ABSOLUTE(.);
+ KEEP(*(.init_array .init_array.*))
+ _einit = ABSOLUTE(.);
+ } > flash
+
+ .ARM.extab : ALIGN(4) {
+ *(.ARM.extab*)
+ } > flash
+
+ .ARM.exidx : ALIGN(4) {
+ __exidx_start = ABSOLUTE(.);
+ *(.ARM.exidx*)
+ __exidx_end = ABSOLUTE(.);
+ } > flash
+
+ _eronly = ABSOLUTE(.);
+
+ .data : ALIGN(4) {
+ _sdata = ABSOLUTE(.);
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ CONSTRUCTORS
+ . = ALIGN(4);
+ _edata = ABSOLUTE(.);
+ } > sram AT > flash
+
+ .bss : ALIGN(4) {
+ _sbss = ABSOLUTE(.);
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = ABSOLUTE(.);
+ } > sram
+
+ /* Stabs debugging sections. */
+
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/boards/arm/eoss3/quickfeather/scripts/quicknuttx.resc b/boards/arm/eoss3/quickfeather/scripts/quicknuttx.resc
new file mode 100644
index 0000000..80c0baa
--- /dev/null
+++ b/boards/arm/eoss3/quickfeather/scripts/quicknuttx.resc
@@ -0,0 +1,20 @@
+:name: QuickLogic QuickFeather
+:description: This script runs NuttX on a QuickFeather board.
+
+$name?="QuickFeather"
+
+using sysbus
+mach create $name
+machine LoadPlatformDescription @platforms/boards/eos-s3-quickfeather.repl
+
+showAnalyzer uart
+sysbus LogPeripheralAccess sysbus.uart
+logLevel -1 sysbus.uart
+machine StartGdbServer 3333
+
+macro reset
+"""
+ sysbus LoadELF $CWD/nuttx
+"""
+runMacro $reset
+
diff --git a/boards/arm/eoss3/quickfeather/src/Makefile b/boards/arm/eoss3/quickfeather/src/Makefile
new file mode 100644
index 0000000..9a82be4
--- /dev/null
+++ b/boards/arm/eoss3/quickfeather/src/Makefile
@@ -0,0 +1,31 @@
+############################################################################
+# boards/arm/eoss3/quickfeather/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+
+CSRCS = eoss3_boot.c eoss3_bringup.c eoss3_appinit.c
+
+ifeq ($(CONFIG_ARCH_LEDS),y)
+CSRCS += eoss3_autoleds.c
+else
+CSRCS += eoss3_userleds.c
+endif
+
+include $(TOPDIR)/boards/Board.mk
\ No newline at end of file
diff --git a/boards/arm/eoss3/quickfeather/src/eoss3_appinit.c b/boards/arm/eoss3/quickfeather/src/eoss3_appinit.c
new file mode 100644
index 0000000..aa1cfa2
--- /dev/null
+++ b/boards/arm/eoss3/quickfeather/src/eoss3_appinit.c
@@ -0,0 +1,66 @@
+/****************************************************************************
+ * boards/arm/eoss3/quickfeather/src/eoss3_appinit.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+
+#include <nuttx/board.h>
+
+#ifdef CONFIG_LIB_BOARDCTL
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ * Perform application specific initialization. This function is never
+ * called directly from application code, but only indirectly via the
+ * (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ * arg - The boardctl() argument is passed to the board_app_initialize()
+ * implementation without modification. The argument has no
+ * meaning to NuttX; the meaning of the argument is a contract
+ * between the board-specific initialization logic and the
+ * matching application logic. The value could be such things as a
+ * mode enumeration value, a set of DIP switch switch settings, a
+ * pointer to configuration data read from a file or serial FLASH,
+ * or whatever you would like to do with it. Every implementation
+ * should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned on
+ * any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int board_app_initialize(uintptr_t arg)
+{
+ return OK;
+}
+
+#endif /* CONFIG_LIB_BOARDCTL */
diff --git a/boards/arm/eoss3/quickfeather/src/eoss3_autoleds.c b/boards/arm/eoss3/quickfeather/src/eoss3_autoleds.c
new file mode 100644
index 0000000..31309d5
--- /dev/null
+++ b/boards/arm/eoss3/quickfeather/src/eoss3_autoleds.c
@@ -0,0 +1,143 @@
+/****************************************************************************
+ * boards/arm/eoss3/eoss3-quickfeather/src/eoss3_autoleds.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "arm_arch.h"
+#include "arm_internal.h"
+
+#ifdef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: eoss3_autoled_initialize
+ *
+ * Description:
+ * Initialize NuttX-controlled LED logic
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void board_autoled_initialize(void)
+{
+ /* Configure LED GPIO for output */
+
+ eoss3_configgpio(GPIO_LED_B);
+}
+
+/****************************************************************************
+ * Name: board_autoled_on
+ *
+ * Description:
+ * Turn on the "logical" LED state
+ *
+ * Input Parameters:
+ * led - Identifies the "logical" LED state (see definitions in
+ * include/board.h)
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void board_autoled_on(int led)
+{
+ bool ledon = true;
+
+ switch (led)
+ {
+ case 0: /* LED Off */
+ ledon = false;
+ break;
+
+ case 2: /* LED No change */
+ return;
+
+ case 1: /* LED On */
+ case 3: /* LED On */
+ break;
+ }
+
+ eoss3_gpiowrite(GPIO_LED_B, ledon); /* High illuminates */
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ *
+ * Description:
+ * Turn off the "logical" LED state
+ *
+ * Input Parameters:
+ * led - Identifies the "logical" LED state (see definitions in
+ * include/board.h)
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void board_autoled_off(int led)
+{
+ switch (led)
+ {
+ case 0: /* LED Off */
+ case 1: /* LED Off */
+ case 3: /* LED Off */
+ break;
+
+ case 2: /* LED No change */
+ return;
+ }
+
+ eoss3_gpiowrite(GPIO_LED_B, false); /* High illuminates */
+}
+
+#endif /* CONFIG_ARCH_LEDS */
diff --git a/boards/arm/eoss3/quickfeather/src/eoss3_boot.c b/boards/arm/eoss3/quickfeather/src/eoss3_boot.c
new file mode 100644
index 0000000..38160d7
--- /dev/null
+++ b/boards/arm/eoss3/quickfeather/src/eoss3_boot.c
@@ -0,0 +1,83 @@
+/****************************************************************************
+ * boards/arm/eoss3/quickfeather/src/eoss3_boot.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "arm_arch.h"
+#include "nvic.h"
+#include "itm.h"
+
+#include "eoss3.h"
+#include "quickfeather.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: eoss3_boardinitialize
+ *
+ * Description:
+ * All EOS S3 architectures must provide the following entry point. This
+ * entry point is called early in the initialization -- after all memory
+ * has been configured and mapped but before any devices have been
+ * initialized.
+ *
+ ****************************************************************************/
+
+void eoss3_boardinitialize(void)
+{
+#ifdef CONFIG_ARCH_LEDS
+ /* Configure on-board LEDs if LED support has been selected. */
+
+ board_autoled_initialize();
+#endif
+}
+
+/****************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
+ * initialization call will be performed in the boot-up sequence to a
+ * function called board_late_initialize(). board_late_initialize() will
+ * be called immediately after up_initialize() is called and just before
+ * the initial application is started. This additional initialization
+ * phase may be used, for example, to initialize board-specific device
+ * drivers.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+ /* Perform board-specific initialization */
+
+ eoss3_bringup();
+}
+#endif
diff --git a/boards/arm/eoss3/quickfeather/src/eoss3_bringup.c b/boards/arm/eoss3/quickfeather/src/eoss3_bringup.c
new file mode 100644
index 0000000..cfc49bb
--- /dev/null
+++ b/boards/arm/eoss3/quickfeather/src/eoss3_bringup.c
@@ -0,0 +1,59 @@
+/****************************************************************************
+ * boards/arm/eoss3/quickfeather/src/eoss3_bringup.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/mount.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <debug.h>
+#include <errno.h>
+
+#include "eoss3.h"
+
+#include "quickfeather.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: eoss3_bringup
+ *
+ * Description:
+ * Perform architecture-specific initialization
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y :
+ * Called from board_late_initialize().
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
+ * Called from the NSH library
+ *
+ ****************************************************************************/
+
+int eoss3_bringup(void)
+{
+ int ret = OK;
+
+ return ret;
+}
diff --git a/boards/arm/eoss3/quickfeather/src/quickfeather.h b/boards/arm/eoss3/quickfeather/src/quickfeather.h
new file mode 100644
index 0000000..20a5896
--- /dev/null
+++ b/boards/arm/eoss3/quickfeather/src/quickfeather.h
@@ -0,0 +1,79 @@
+/****************************************************************************
+ * boards/arm/eoss3/quickfeather/src/eoss3_boot.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM_EOSS3_QUICKFEATHER_SRC_QUICKFEATHER_H
+#define __BOARDS_ARM_EOSS3_QUICKFEATHER_SRC_QUICKFEATHER_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+#include <stdint.h>
+#include <arch/eoss3/chip.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* procfs File System *******************************************************/
+
+#ifdef CONFIG_FS_PROCFS
+# ifdef CONFIG_NSH_PROC_MOUNTPOINT
+# define EOSS3_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT
+# else
+# define EOSS3_PROCFS_MOUNTPOINT "/proc"
+# endif
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: eoss3_bringup
+ *
+ * Description:
+ * Perform architecture-specific initialization
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y :
+ * Called from board_late_initialize().
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
+ * Called from the NSH library
+ *
+ ****************************************************************************/
+
+int eoss3_bringup(void);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __BOARDS_ARM_EOSS3_QUICKFEATHER_SRC_QUICKFEATHER_H */