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Posted to commits@nuttx.apache.org by xi...@apache.org on 2021/11/06 10:14:14 UTC
[incubator-nuttx] branch master updated (f8832f7 -> 4b96c28)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from f8832f7 mpfs: emmcsd: fix uninitialized value
new 040a042 drivers/spi:Define SPI_~CS~_DELAY_CONTROL to support other delays
new 4b96c28 stm32h7:Support SPI SPI_DELAY_CONTROL
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/arm/src/samv7/sam_spi.c | 15 +++--
arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h | 2 +-
arch/arm/src/stm32h7/stm32_spi.c | 71 ++++++++++++++++++++++
arch/risc-v/src/bl602/bl602_spi.c | 8 ++-
arch/risc-v/src/mpfs/mpfs_spi.c | 2 +-
arch/z80/src/ez80/ez80_spi.c | 2 +-
.../arm/kinetis/freedom-k66f/configs/nsh/defconfig | 2 +-
drivers/spi/Kconfig | 18 ++++--
drivers/spi/spi_transfer.c | 4 +-
include/nuttx/spi/spi.h | 9 +--
include/nuttx/spi/spi_transfer.h | 3 +-
11 files changed, 110 insertions(+), 26 deletions(-)
[incubator-nuttx] 02/02: stm32h7:Support SPI SPI_DELAY_CONTROL
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 4b96c28ed4b3e64ebdb4d0719426ad12d5fb1ee5
Author: David Sidrane <Da...@NscDg.com>
AuthorDate: Fri Nov 5 10:28:23 2021 -0700
stm32h7:Support SPI SPI_DELAY_CONTROL
---
arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h | 2 +-
arch/arm/src/stm32h7/stm32_spi.c | 71 +++++++++++++++++++++++++
2 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h
index edaa379..cc2f8f9 100644
--- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h
@@ -326,7 +326,7 @@
# define SPI_CFG2_MSSI_13CLK (13 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_14CLK (14 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_15CLK (15 << SPI_CFG2_MSSI_SHIFT)
-#define SPI_CFG2_MIDI_SHIFT (0) /* Bits 4-7: master Inter-Data idleness */
+#define SPI_CFG2_MIDI_SHIFT (4) /* Bits 4-7: master Inter-Data idleness */
#define SPI_CFG2_MIDI_MASK (0xf << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_0CLK (0 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_1CLK (1 << SPI_CFG2_MIDI_SHIFT)
diff --git a/arch/arm/src/stm32h7/stm32_spi.c b/arch/arm/src/stm32h7/stm32_spi.c
index be8d968..e67fa5c 100644
--- a/arch/arm/src/stm32h7/stm32_spi.c
+++ b/arch/arm/src/stm32h7/stm32_spi.c
@@ -313,6 +313,11 @@ static inline void spi_dmatxstart(FAR struct stm32_spidev_s *priv);
static int spi_lock(FAR struct spi_dev_s *dev, bool lock);
static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
uint32_t frequency);
+#ifdef CONFIG_SPI_DELAY_CONTROL
+static int spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
+ uint32_t stopdelay, uint32_t csdelay,
+ uint32_t ifdelay);
+#endif
static void spi_setmode(FAR struct spi_dev_s *dev,
enum spi_mode_e mode);
static void spi_setbits(FAR struct spi_dev_s *dev, int nbits);
@@ -355,6 +360,9 @@ static const struct spi_ops_s g_sp1iops =
.lock = spi_lock,
.select = stm32_spi1select,
.setfrequency = spi_setfrequency,
+#ifdef CONFIG_SPI_DELAY_CONTROL
+ .setdelay = spi_setdelay,
+#endif
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
@@ -421,6 +429,9 @@ static const struct spi_ops_s g_sp2iops =
.lock = spi_lock,
.select = stm32_spi2select,
.setfrequency = spi_setfrequency,
+#ifdef CONFIG_SPI_DELAY_CONTROL
+ .setdelay = spi_setdelay,
+#endif
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
@@ -487,6 +498,9 @@ static const struct spi_ops_s g_sp3iops =
.lock = spi_lock,
.select = stm32_spi3select,
.setfrequency = spi_setfrequency,
+#ifdef CONFIG_SPI_DELAY_CONTROL
+ .setdelay = spi_setdelay,
+#endif
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
@@ -553,6 +567,9 @@ static const struct spi_ops_s g_sp4iops =
.lock = spi_lock,
.select = stm32_spi4select,
.setfrequency = spi_setfrequency,
+#ifdef CONFIG_SPI_DELAY_CONTROL
+ .setdelay = spi_setdelay,
+#endif
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
@@ -619,6 +636,9 @@ static const struct spi_ops_s g_sp5iops =
.lock = spi_lock,
.select = stm32_spi5select,
.setfrequency = spi_setfrequency,
+#ifdef CONFIG_SPI_DELAY_CONTROL
+ .setdelay = spi_setdelay,
+#endif
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
@@ -685,6 +705,9 @@ static const struct spi_ops_s g_sp6iops =
.lock = spi_lock,
.select = stm32_spi6select,
.setfrequency = spi_setfrequency,
+#ifdef CONFIG_SPI_DELAY_CONTROL
+ .setdelay = spi_setdelay,
+#endif
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
@@ -1541,6 +1564,54 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
}
/****************************************************************************
+ * Name: spi_setdelay
+ *
+ * Description:
+ * Set the SPI Delays in nanoseconds. Optional.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * startdelay - The delay between CS active and first CLK
+ * stopdelay - The delay between last CLK and CS inactive
+ * csdelay - The delay between CS inactive and CS active again
+ * ifdelay - The delay between frames
+ *
+ * Returned Value:
+ * Returns zero (OK) on success; a negated errno value is return on any
+ * failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_DELAY_CONTROL
+static int spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
+ uint32_t stopdelay, uint32_t csdelay,
+ uint32_t ifdelay)
+{
+ FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev;
+ uint32_t setbits = 0;
+ uint32_t clrbits = SPI_CFG2_MSSI_MASK | SPI_CFG2_MIDI_MASK;
+ uint32_t nsperclk = NSEC_PER_SEC / priv->actual;
+
+ startdelay /= nsperclk;
+ ifdelay /= nsperclk;
+
+ setbits = ((ifdelay << SPI_CFG2_MIDI_SHIFT) & SPI_CFG2_MIDI_MASK) |
+ ((startdelay << SPI_CFG2_MSSI_SHIFT) & SPI_CFG2_MSSI_MASK);
+
+ spi_enable(priv, false);
+
+ /* Change SPI mode */
+
+ spi_modifyreg(priv, STM32_SPI_CFG2_OFFSET, clrbits, setbits);
+
+ /* Re-enable SPI */
+
+ spi_enable(priv, true);
+ return OK;
+}
+#endif
+
+/****************************************************************************
* Name: spi_setmode
*
* Description:
[incubator-nuttx] 01/02: drivers/spi:Define SPI_~CS~_DELAY_CONTROL
to support other delays
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 040a04241e31a404104efca22c87ceaeafb5549f
Author: David Sidrane <Da...@NscDg.com>
AuthorDate: Fri Nov 5 09:54:40 2021 -0700
drivers/spi:Define SPI_~CS~_DELAY_CONTROL to support other delays
---
arch/arm/src/samv7/sam_spi.c | 15 +++++++++------
arch/risc-v/src/bl602/bl602_spi.c | 8 +++++---
arch/risc-v/src/mpfs/mpfs_spi.c | 2 +-
arch/z80/src/ez80/ez80_spi.c | 2 +-
boards/arm/kinetis/freedom-k66f/configs/nsh/defconfig | 2 +-
drivers/spi/Kconfig | 18 ++++++++++++------
drivers/spi/spi_transfer.c | 4 ++--
include/nuttx/spi/spi.h | 9 +++++----
include/nuttx/spi/spi_transfer.h | 3 ++-
9 files changed, 38 insertions(+), 25 deletions(-)
diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c
index 99e05a2..fad6b7e 100644
--- a/arch/arm/src/samv7/sam_spi.c
+++ b/arch/arm/src/samv7/sam_spi.c
@@ -254,9 +254,9 @@ static int spi_lock(struct spi_dev_s *dev, bool lock);
static void spi_select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency);
-#ifdef CONFIG_SPI_CS_DELAY_CONTROL
+#ifdef CONFIG_SPI_DELAY_CONTROL
static int spi_setdelay(struct spi_dev_s *dev, uint32_t a, uint32_t b,
- uint32_t c);
+ uint32_t c, uint32_t i);
#endif
#ifdef CONFIG_SPI_HWFEATURES
static int spi_hwfeatures(struct spi_dev_s *dev, uint8_t features);
@@ -311,7 +311,7 @@ static const struct spi_ops_s g_spi0ops =
.lock = spi_lock,
.select = spi_select,
.setfrequency = spi_setfrequency,
-#ifdef CONFIG_SPI_CS_DELAY_CONTROL
+#ifdef CONFIG_SPI_DELAY_CONTROL
.setdelay = spi_setdelay,
#endif
.setmode = spi_setmode,
@@ -353,7 +353,7 @@ static const struct spi_ops_s g_spi1ops =
.lock = spi_lock,
.select = spi_select,
.setfrequency = spi_setfrequency,
-#ifdef CONFIG_SPI_CS_DELAY_CONTROL
+#ifdef CONFIG_SPI_DELAY_CONTROL
.setdelay = spi_setdelay,
#endif
.setmode = spi_setmode,
@@ -1105,15 +1105,17 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
* startdelay - The delay between CS active and first CLK
* stopdelay - The delay between last CLK and CS inactive
* csdelay - The delay between CS inactive and CS active again
+ * ifdelay - The delay between frames
*
* Returned Value:
* Returns 0 if ok
*
****************************************************************************/
-#ifdef CONFIG_SPI_CS_DELAY_CONTROL
+#ifdef CONFIG_SPI_DELAY_CONTROL
static int spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
- uint32_t stopdelay, uint32_t csdelay)
+ uint32_t stopdelay, uint32_t csdelay,
+ uint32_t ifdelay)
{
struct sam_spics_s *spics = (struct sam_spics_s *)dev;
struct sam_spidev_s *spi = spi_device(spics);
@@ -1126,6 +1128,7 @@ static int spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
spiinfo("cs=%d startdelay=%d\n", spics->cs, startdelay);
spiinfo("cs=%d stopdelay=%d\n", spics->cs, stopdelay);
spiinfo("cs=%d csdelay=%d\n", spics->cs, csdelay);
+ spiinfo("cs=%d ifdelay=%d\n", spics->if, ifdelay);
offset = (unsigned int)g_csroffset[spics->cs];
diff --git a/arch/risc-v/src/bl602/bl602_spi.c b/arch/risc-v/src/bl602/bl602_spi.c
index f4ef650..3f18cdc 100644
--- a/arch/risc-v/src/bl602/bl602_spi.c
+++ b/arch/risc-v/src/bl602/bl602_spi.c
@@ -196,7 +196,7 @@ static const struct spi_ops_s bl602_spi_ops =
.lock = bl602_spi_lock,
.select = bl602_spi_select,
.setfrequency = bl602_spi_setfrequency,
-#ifdef CONFIG_SPI_CS_DELAY_CONTROL
+#ifdef CONFIG_SPI_DELAY_CONTROL
.setdelay = bl602_spi_setdelay,
#endif
.setmode = bl602_spi_setmode,
@@ -518,6 +518,7 @@ static uint32_t bl602_spi_setfrequency(struct spi_dev_s *dev,
* startdelay - The delay between CS active and first CLK
* stopdelay - The delay between last CLK and CS inactive
* csdelay - The delay between CS inactive and CS active again
+ * ifdelay - The delay between frames
*
* Returned Value:
* Returns zero (OK) on success; a negated errno value is return on any
@@ -525,9 +526,10 @@ static uint32_t bl602_spi_setfrequency(struct spi_dev_s *dev,
*
****************************************************************************/
-#ifdef CONFIG_SPI_CS_DELAY_CONTROL
+#ifdef CONFIG_SPI_DELAY_CONTROL
static int bl602_spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
- uint32_t stopdelay, uint32_t csdelay)
+ uint32_t stopdelay, uint32_t csdelay,
+ uint32_t ifdelay)
{
spierr("SPI CS delay control not supported\n");
DEBUGPANIC();
diff --git a/arch/risc-v/src/mpfs/mpfs_spi.c b/arch/risc-v/src/mpfs/mpfs_spi.c
index 6b58016..e5f7ce8 100644
--- a/arch/risc-v/src/mpfs/mpfs_spi.c
+++ b/arch/risc-v/src/mpfs/mpfs_spi.c
@@ -193,7 +193,7 @@ static const struct spi_ops_s mpfs_spi_ops =
.lock = mpfs_spi_lock,
.select = mpfs_spi_select,
.setfrequency = mpfs_spi_setfrequency,
-#ifdef CONFIG_SPI_CS_DELAY_CONTROL
+#ifdef CONFIG_SPI_DELAY_CONTROL
.setdelay = mpfs_spi_setdelay,
#endif
.setmode = mpfs_spi_setmode,
diff --git a/arch/z80/src/ez80/ez80_spi.c b/arch/z80/src/ez80/ez80_spi.c
index 90976cf..b37d025 100644
--- a/arch/z80/src/ez80/ez80_spi.c
+++ b/arch/z80/src/ez80/ez80_spi.c
@@ -95,7 +95,7 @@ static const struct spi_ops_s g_spiops =
spi_lock, /* lock() */
ez80_spiselect, /* select(): Provided externally by board logic */
spi_setfrequency, /* setfrequency() */
-#ifdef CONFIG_SPI_CS_DELAY_CONTROL
+#ifdef CONFIG_SPI_DELAY_CONTROL
NULL, /* setdelay() */
#endif
spi_setmode,
diff --git a/boards/arm/kinetis/freedom-k66f/configs/nsh/defconfig b/boards/arm/kinetis/freedom-k66f/configs/nsh/defconfig
index a3cded4..2576647 100644
--- a/boards/arm/kinetis/freedom-k66f/configs/nsh/defconfig
+++ b/boards/arm/kinetis/freedom-k66f/configs/nsh/defconfig
@@ -92,7 +92,7 @@ CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_SERIAL_TERMIOS=y
-CONFIG_SPI_CS_DELAY_CONTROL=y
+CONFIG_SPI_DELAY_CONTROL=y
CONFIG_STACK_COLORATION=y
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_SYSTEM_NSH=y
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 4743ede..f5c7f64 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -163,14 +163,20 @@ config SPI_BITORDER
Enables capability to select MSB- or LSB-first hardware feature for
data transfers.
-config SPI_CS_DELAY_CONTROL
- bool "SPI CS Delay Control"
+config SPI_DELAY_CONTROL
+ bool "SPI Delay Control"
default n
---help---
- Enables possibilities to define the SPI-ChipSelect-Delays like
- time between ChipSelect assertion and first Data-Bit, the time
- between the last Data-Bit and the de-assertion and the minimum
- delay between two ChipSelects.
+ Enables possibilities to define the SPI Delays such as
+ SPI-ChipSelect-Delays and inter frame delays.
+
+ SPI-ChipSelect-Delays: are the delay between ChipSelect assertion
+ and first Data-Bit, the delay between the last Data-Bit and the
+ de-assertion and the minimum delay between two ChipSelects.
+
+ The inter-frame delays also know as Inter-Data Idleness, controls the
+ delay between frames. (one transaction of nbits as configured with
+ SPI_SETBITS).
This option enables the setdelay() interface method.
diff --git a/drivers/spi/spi_transfer.c b/drivers/spi/spi_transfer.c
index ceaa9ed..82d1e70 100644
--- a/drivers/spi/spi_transfer.c
+++ b/drivers/spi/spi_transfer.c
@@ -72,8 +72,8 @@ int spi_transfer(FAR struct spi_dev_s *spi, FAR struct spi_sequence_s *seq)
SPI_SETFREQUENCY(spi, seq->frequency);
-#ifdef CONFIG_SPI_CS_DELAY_CONTROL
- ret = SPI_SETDELAY(spi, seq->a, seq->b, seq->c);
+#ifdef CONFIG_SPI_DELAY_CONTROL
+ ret = SPI_SETDELAY(spi, seq->a, seq->b, seq->c, seq->i);
if (ret < 0)
{
spierr("ERROR: SPI_SETDELAY failed: %d\n", ret);
diff --git a/include/nuttx/spi/spi.h b/include/nuttx/spi/spi.h
index 3c50ed7..98889d9 100644
--- a/include/nuttx/spi/spi.h
+++ b/include/nuttx/spi/spi.h
@@ -124,6 +124,7 @@
* startdelay - The delay between CS active and first CLK
* stopdelay - The delay between last CLK and CS inactive
* csdelay - The delay between CS inactive and CS active again
+ * ifdelay - The delay between frames
*
* Returned Value:
* Returns zero (OK) on success; a negated errno value is return on any
@@ -131,8 +132,8 @@
*
****************************************************************************/
-#ifdef CONFIG_SPI_CS_DELAY_CONTROL
-# define SPI_SETDELAY(d,a,b,c) ((d)->ops->setdelay(d,a,b,c))
+#ifdef CONFIG_SPI_DELAY_CONTROL
+# define SPI_SETDELAY(d,a,b,c,i) ((d)->ops->setdelay(d,a,b,c,i))
#endif
/****************************************************************************
@@ -543,9 +544,9 @@ struct spi_ops_s
bool selected);
CODE uint32_t (*setfrequency)(FAR struct spi_dev_s *dev,
uint32_t frequency);
-#ifdef CONFIG_SPI_CS_DELAY_CONTROL
+#ifdef CONFIG_SPI_DELAY_CONTROL
CODE int (*setdelay)(FAR struct spi_dev_s *dev, uint32_t a,
- uint32_t b, uint32_t c);
+ uint32_t b, uint32_t c, uint32_t i);
#endif
CODE void (*setmode)(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
CODE void (*setbits)(FAR struct spi_dev_s *dev, int nbits);
diff --git a/include/nuttx/spi/spi_transfer.h b/include/nuttx/spi/spi_transfer.h
index c9f2342..a3ea58e 100644
--- a/include/nuttx/spi/spi_transfer.h
+++ b/include/nuttx/spi/spi_transfer.h
@@ -100,10 +100,11 @@ struct spi_sequence_s
uint8_t nbits; /* Number of bits */
uint8_t ntrans; /* Number of transactions */
uint32_t frequency; /* SPI frequency (Hz) */
-#ifdef CONFIG_SPI_CS_DELAY_CONTROL
+#ifdef CONFIG_SPI_DELAY_CONTROL
uint32_t a; /* Arguments to setdelay() */
uint32_t b;
uint32_t c;
+ uint32_t i;
#endif
/* A pointer to the list of transfers to be be performed. */