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Posted to commits@nuttx.apache.org by "wangtao13 (via GitHub)" <gi...@apache.org> on 2026/06/02 09:55:48 UTC
[I] [HELP] Nuttx porting: Unexpected exception vector in MIPS32 [nuttx]</h1><pre>
wangtao13 opened a new issue, #19017:
URL: https://github.com/apache/nuttx/issues/19017
### Description
I am porting nuttx to a MIPS32 SOC system, where there is 32MB DRAM.
I started porting by referring to the pic32mz.
First of all I want to setup interrupt and exception handlers for it, per MIPS ISA, I clear the BEV in status register and set IV in cause register of CP0, I would use 0x80000180 and 0x80000200 for exception and interrupt handling. So I worked out a board.ld as follows,
```
OUTPUT_FORMAT("elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(__start)
MEMORY
{
ram (rwx) : ORIGIN = 0x80100000, LENGTH = 31M
ramv (rwx) : ORIGIN = 0x80000000, LENGTH = 16K
}
SECTIONS
{
.start : {
*(.start)
} > ram
.vectors_load : {
_vectors_load_start = .;
. = ALIGN(4);
KEEP(*(.reset))
. = _vectors_load_start + 0x180;
. = ALIGN(4);
KEEP(*(.gen_excpt))
. = _vectors_load_start + 0x200;
. = ALIGN(4);
KEEP(*(.ebase_excpt))
. = _vectors_load_start + 0x300;
. = ALIGN(4);
KEEP(*(.cache_excpt))
. = _vectors_load_start + 0x380;
. = ALIGN(4);
KEEP(*(.bev_excpt))
. = _vectors_load_start + 0x400;
. = ALIGN(4);
KEEP(*(.int_excpt))
. = _vectors_load_start + 0x480;
. = ALIGN(4);
KEEP(*(.dbg_excpt))
. = _vectors_load_start + 0x500;
_vectors_load_end = .;
} > ramv
.text : {
_stext = .;
*(.text .text.*)
......
}
```
which defined entry point (__start) is 0x80100000, and the vectors are all in 0x80000N00.
From the following in System.map I think the vectors are in the location specified by board.ld.
```
Memory Configuration
Name Origin Length Attributes
ram 0x0000000080100000 0x0000000001f00000 xrw
ramv 0x0000000080000000 0x0000000000004000 xrw
*default* 0x0000000000000000 0xffffffffffffffff
Linker script and memory map
.start 0x0000000080100000 0x178
*(.start)
.start 0x0000000080100000 0x178 my_head.o
0x0000000080100000 __start
.vectors_load 0x0000000080000000 0x500
0x0000000080000000 _vectors_load_start = .
0x0000000080000000 . = ALIGN (0x4)
*(.reset)
.reset 0x0000000080000000 0x10 my_head.o
0x0000000080000000 __reset
0x0000000080000180 . = (_vectors_load_start + 0x180)
*fill* 0x0000000080000010 0x170
0x0000000080000180 . = ALIGN (0x4)
*(.gen_excpt)
.gen_excpt 0x0000000080000180 0x10 my_head.o
0x0000000080000200 . = (_vectors_load_start + 0x200)
*fill* 0x0000000080000190 0x70
0x0000000080000200 . = ALIGN (0x4)
*(.ebase_excpt)
.ebase_excpt 0x0000000080000200 0x10 my_head.o
0x0000000080000300 . = (_vectors_load_start + 0x300)
*fill* 0x0000000080000210 0xf0
0x0000000080000300 . = ALIGN (0x4)
*(.cache_excpt)
0x0000000080000380 . = (_vectors_load_start + 0x380)
*fill* 0x0000000080000300 0x80
0x0000000080000380 . = ALIGN (0x4)
*(.bev_excpt)
.bev_excpt 0x0000000080000380 0x10 my_head.o
0x0000000080000400 . = (_vectors_load_start + 0x400)
*fill* 0x0000000080000390 0x70
0x0000000080000400 . = ALIGN (0x4)
*(.int_excpt)
.int_excpt 0x0000000080000400 0x10 my_head.o
0x0000000080000480 . = (_vectors_load_start + 0x480)
*fill* 0x0000000080000410 0x70
0x0000000080000480 . = ALIGN (0x4)
*(.dbg_excpt)
0x0000000080000500 . = (_vectors_load_start + 0x500)
*fill* 0x0000000080000480 0x80
0x0000000080000500 _vectors_load_end = .
.text 0x0000000080100180 0x51260
0x0000000080100180 _stext = .
*(.text .text.*)
```
Here is the codes to setup interrupt and exception (there is interrupt controller in SOC, so far I only enabled SW0 in status register).
```
cp0_putebase(0x80000000);
/* Set the INTCTL vector spacing to non-zero */
cp0_putintctl(0x00000020);
/* Set the IV bit in the CAUSE register */
regval = cp0_getcause();
regval |= CP0_CAUSE_IV;
cp0_putcause(regval);
/* Clear the EXL and BEV bits in the STATUS register */
regval = cp0_getstatus();
regval &= ~(CP0_STATUS_EXL | CP0_STATUS_BEV);
cp0_putstatus(regval);
__asm__ volatile(
"sync\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
);
```
With JTAG and GDB, I loaded my image to 0x80000000 (so the vectors are well populated), I started running the image from 0x80100000.
To my surprise, I hit the codes in _bev_exception at 0x80000380 instead of 0x80000200 when the interrupt is enabled through status register, which caused no calling of interrupt handler!
I checked the cause and status registers of CP0, when _bev_exception is called, they are,
status: 00000303; cause: 40808100, there seemed be interrupt but why it is trapped to _bev_exception instead of 0x80000200?
### Verification
- [x] I have verified before submitting the report.
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</pre><hr/>
<h2>Re: [I] [HELP] Nuttx porting: Unexpected exception vector in MIPS32 [nuttx]</h2>
<b>Posted by "ldube (via GitHub)" <gi...@apache.org>.</b><hr/><pre>
ldube commented on issue #19017:
URL: https://github.com/apache/nuttx/issues/19017#issuecomment-4652128558
@wangtao13 Which mips soc is this?
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</pre><hr/>
<h2>Re: [I] [HELP] Nuttx porting: Unexpected exception vector in MIPS32 [nuttx]</h2>
<b>Posted by "wangtao13 (via GitHub)" <gi...@apache.org>.</b><hr/><pre>
wangtao13 commented on issue #19017:
URL: https://github.com/apache/nuttx/issues/19017#issuecomment-5260175495
I am not sure if I fixed the issue, the interrupt and exception are working.
I changed the chip_head.S as follows,
```
.section .bev_excpt,"ax",@progbits
.set noreorder
#ifdef CONFIG_MIPS_MICROMIPS
.set micromips
#endif
.ent _bev_exception
_bev_exception:
/* commented out by wt. la k0, _exception_handler */
la k0, _int_handler
jr k0
nop
.end _bev_exception
```
and
```
.section .int_handler, "ax", @progbits
.set noreorder
#ifdef CONFIG_MIPS_MICROMIPS
.set micromips
#endif
.ent _int_handler
_int_handler:
EXCPT_PROLOGUE t0 /* Save registers on stack, enable nested interrupts */
move a0, sp /* Pass register save structure as the parameter 1 */
USE_INTSTACK t0, t1, t2, t3 /* Switch to the interrupt stack */
la t0, mips_chip_decodeirq /* wt: Call mips_chip_decodeirq(regs) */
jalr ra, t0
nop
#ifdef CONFIG_MIPS_NESTED_INTERRUPTS
di /* Prohibit nested interrupts from here */
#endif
RESTORE_STACK t0, t1 /* Undo the operations of USE_STACK */
EXCPT_EPILOGUE v0 /* Return to the context returned by mips_chip_decodeirq() */
.end _int_handler
```
Here is what I did in my porting of `up_irqinitialize()`.
```
/* Set all interrupts to the default (middle) priority */
/* Set the BEV bit in the STATUS register */
regval = cp0_getstatus();
regval |= CP0_STATUS_BEV;
cp0_putstatus(regval);
cp0_putebase(0x80000000);
/* Set the INTCTL vector spacing to non-zero */
cp0_putintctl(0x00000020);
/* Set the IV bit in the CAUSE register */
regval = cp0_getcause();
/// wt: Cleared IV
regval &= ~CP0_CAUSE_IV;
cp0_putcause(regval);
/* Clear the EXL and BEV bits in the STATUS register */
regval = cp0_getstatus();
regval &= ~(CP0_STATUS_EXL | CP0_STATUS_BEV);
cp0_putstatus(regval);
__asm__ volatile(
"sync\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
);
up_flush_dcache_all();
```
I found there supported a new MIPS SOC in arch/mips/src, I will check if I can refer to its interrupt/exception configuration.
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</pre><hr/>
<h2>Re: [I] [HELP] Nuttx porting: Unexpected exception vector in MIPS32 [nuttx]</h2>
<b>Posted by "wangtao13 (via GitHub)" <gi...@apache.org>.</b><hr/><pre>
wangtao13 commented on issue #19017:
URL: https://github.com/apache/nuttx/issues/19017#issuecomment-4703511267
> [@wangtao13](https://github.com/wangtao13) Which mips soc is this?
This is MIPS SOC which has MIPS32r2 CPU on chip, it also supports FPU.
I checked the SOC's spec about exception vector, but I did NOT find anything special.
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</pre><hr/>
<h2>Re: [I] [HELP] <title> Nuttx porting: Unexpected exception vector in MIPS32 [nuttx]</h2>
<b>Posted by "fatumax (via GitHub)" <gi...@apache.org>.</b><hr/><pre>
fatumax commented on issue #19017:
URL: https://github.com/apache/nuttx/issues/19017#issuecomment-4611413331
@wangtao13
这个 Issue 不只是写给本项目维护者的，更是写给所有正在做开源、或者将来打算做开源的同行们的。
**事实摆在眼前：** 过去 48 小时内新增了约 2845 颗星。全是默认灰色头像，bio 一片空白。
**结果呢？**
- 社区成员已经发现并开始讨论
- 项目的真实信誉遭到严重损害
- 未来每一个新的访问者都会看到这些 Issue
- 维护者的个人声誉也受到牵连
**如果你也曾动过刷星的念头，请想清楚这几件事：**
1. **刷星一定会被发现。** 不是可能，是一定。空壳号的特征太明显了，任何一个有经验的开发者都能在三分钟内看出来。
2. **被发现后的代价远大于收益。** 几千块钱买来的假 Star，可能让你损失掉几年积累的行业声誉和潜在合作机会。
3. **真实的增长虽然慢，但可持续。** 一篇好的技术博客带来的 Star 比你买来的更有价值，因为这些人会真正使用你的项目、给你反馈、帮你传播。
4. **开源社区对造假零容忍。** 你可以犯技术错误，可以写出 bug，但如果你数据造假，社区不会原谅你。
以这个项目为鉴。别走同样的路。
开源的世界不需要虚假的数字，需要真实的代码。
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</pre><hr/>
<h2>Re: [I] [HELP] Nuttx porting: Unexpected exception vector in MIPS32 [nuttx]</h2>
<b>Posted by "ldube (via GitHub)" <gi...@apache.org>.</b><hr/><pre>
ldube commented on issue #19017:
URL: https://github.com/apache/nuttx/issues/19017#issuecomment-5254367660
@wangtao13 Did you resolve this issue?
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</pre><hr/>
<h2>Re: [I] [HELP] <title> Nuttx porting: Unexpected exception vector in MIPS32 [nuttx]</h2>
<b>Posted by "wangtao13 (via GitHub)" <gi...@apache.org>.</b><hr/><pre>
wangtao13 commented on issue #19017:
URL: https://github.com/apache/nuttx/issues/19017#issuecomment-4617531420
> [@wangtao13](https://github.com/wangtao13)
>
> 这个 Issue 不只是写给本项目维护者的，更是写给所有正在做开源、或者将来打算做开源的同行们的。
>
> **事实摆在眼前：** 过去 48 小时内新增了约 2845 颗星。全是默认灰色头像，bio 一片空白。
>
> **结果呢？**
>
> * 社区成员已经发现并开始讨论
> * 项目的真实信誉遭到严重损害
> * 未来每一个新的访问者都会看到这些 Issue
> * 维护者的个人声誉也受到牵连
>
> **如果你也曾动过刷星的念头，请想清楚这几件事：**
>
> 1. **刷星一定会被发现。** 不是可能，是一定。空壳号的特征太明显了，任何一个有经验的开发者都能在三分钟内看出来。
> 2. **被发现后的代价远大于收益。** 几千块钱买来的假 Star，可能让你损失掉几年积累的行业声誉和潜在合作机会。
> 3. **真实的增长虽然慢，但可持续。** 一篇好的技术博客带来的 Star 比你买来的更有价值，因为这些人会真正使用你的项目、给你反馈、帮你传播。
> 4. **开源社区对造假零容忍。** 你可以犯技术错误，可以写出 bug，但如果你数据造假，社区不会原谅你。
>
> 以这个项目为鉴。别走同样的路。
>
> 开源的世界不需要虚假的数字，需要真实的代码。
What on hell is this comment for?
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</pre><hr/>
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