You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@mynewt.apache.org by ja...@apache.org on 2022/12/21 09:26:36 UTC
[mynewt-core] branch master updated (6f024918d -> 06c934d82)
This is an automated email from the ASF dual-hosted git repository.
janc pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
from 6f024918d loramac: fix broken rx1 interval
new fb0086500 mcu/nrf52: Enable instruction cache by default
new 06c934d82 mcu/nrf5340_net: Enable instruction cache by default
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
hw/mcu/nordic/nrf52xxx/syscfg.yml | 2 +-
hw/mcu/nordic/nrf5340_net/syscfg.yml | 3 +--
2 files changed, 2 insertions(+), 3 deletions(-)
[mynewt-core] 02/02: mcu/nrf5340_net: Enable instruction cache by default
Posted by ja...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
janc pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 06c934d8292ecc8fea86680cdadb06623d5884db
Author: Szymon Janc <sz...@codecoup.pl>
AuthorDate: Wed Dec 21 09:04:48 2022 +0100
mcu/nrf5340_net: Enable instruction cache by default
Does not really make sense to have it disabled by default since we are
running from flash.
---
hw/mcu/nordic/nrf5340_net/syscfg.yml | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/mcu/nordic/nrf5340_net/syscfg.yml b/hw/mcu/nordic/nrf5340_net/syscfg.yml
index 86849853d..618beafab 100644
--- a/hw/mcu/nordic/nrf5340_net/syscfg.yml
+++ b/hw/mcu/nordic/nrf5340_net/syscfg.yml
@@ -65,8 +65,7 @@ syscfg.defs:
MCU_ICACHE_ENABLED:
description: >
Enable instruction code cache
- Default value is 0, so disabled.
- value: 0
+ value: 1
MCU_DEFAULT_STARTUP:
description: >
[mynewt-core] 01/02: mcu/nrf52: Enable instruction cache by default
Posted by ja...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
janc pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit fb0086500ed6dd69c219656fe63fb6be91b9c90a
Author: Szymon Janc <sz...@codecoup.pl>
AuthorDate: Wed Dec 21 09:01:35 2022 +0100
mcu/nrf52: Enable instruction cache by default
Does not really make sense to have it disabled by default since we are
running from flash.
Coremark comparison on nRF52840
icache off:
CoreMark Size : 666
Total ticks : 2131
Total time (secs): 16
Iterations/Sec : 125
Iterations : 2000
icache on:
CoreMark Size : 666
Total ticks : 1538
Total time (secs): 12
Iterations/Sec : 166
Iterations : 2000
---
hw/mcu/nordic/nrf52xxx/syscfg.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mcu/nordic/nrf52xxx/syscfg.yml b/hw/mcu/nordic/nrf52xxx/syscfg.yml
index 497865d02..5ad6c62b1 100644
--- a/hw/mcu/nordic/nrf52xxx/syscfg.yml
+++ b/hw/mcu/nordic/nrf52xxx/syscfg.yml
@@ -95,7 +95,7 @@ syscfg.defs:
MCU_ICACHE_ENABLED:
description: >
Enabled Instruction code cache
- value: 0
+ value: 1
MCU_COMMON_STARTUP:
description: >