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Posted to commits@nuttx.apache.org by "michallenc (via GitHub)" <gi...@apache.org> on 2025/11/27 09:48:20 UTC
[PR] arch/arm/src/samv7/sam_qspi_spi.c: add support for SPI_SETDELAY [nuttx]
michallenc opened a new pull request, #17389:
URL: https://github.com/apache/nuttx/pull/17389
## Summary
This commit adds support for `SPI_SETDELAY` operation on SAMv7 QSPI peripheral running in SPI mode. The logic is the same as for standard SPI peripheral, just different registers. The change allows to set custom delays between transfers, chip selects and so on.
## Impact
None on current implementations with `CONFIG_SPI_DELAY_CONTROL` disabled. If enabled, it allows to set SPI delays
based on the device settings.
## Testing
Tested against W25 SPI NOR flash on a custom SAMv7 board. Flash had SmartFS partition and three partitions for NXboot. The update and confirmation process was significantly slower because of default large delay between consecutive transfers. The speed is as expected with the delays set to zero. The needed change in W25 driver is in #17388 17388
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Re: [PR] arch/arm/src/samv7/sam_qspi_spi.c: add support for SPI_SETDELAY [nuttx]
Posted by "michallenc (via GitHub)" <gi...@apache.org>.
michallenc commented on code in PR #17389:
URL: https://github.com/apache/nuttx/pull/17389#discussion_r2568388478
##########
arch/arm/src/samv7/sam_qspi_spi.c:
##########
@@ -398,6 +406,109 @@ static uint32_t qspi_spi_setfrequency(struct spi_dev_s *dev,
return actual;
}
+/****************************************************************************
+ * Name: qspi_spi_setdelay
+ *
+ * Description:
+ * Set the QSPI Delays in nanoseconds. Optional.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * startdelay - The delay between CS active and first CLK
+ * stopdelay - The delay between last CLK and CS inactive
+ * csdelay - The delay between CS inactive and CS active again
+ * ifdelay - The delay between frames
+ *
+ * Returned Value:
+ * Returns 0 if ok
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_DELAY_CONTROL
+static int qspi_spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
+ uint32_t stopdelay, uint32_t csdelay,
+ uint32_t ifdelay)
+{
+ struct sam_spidev_s *spi = &g_spidev;
+ uint64_t dlybs;
+ uint64_t dlybct;
+ uint64_t dlybcs;
+ uint32_t regval;
+
+ spiinfo("startdelay=%" PRIu32 "\n", startdelay);
+ spiinfo("stopdelay=%" PRIu32 "\n", stopdelay);
+ spiinfo("csdelay=%" PRIu32 "\n", csdelay);
+ spiinfo("ifdelay=%" PRIu32 "\n", ifdelay);
+
+ /* startdelay = DLYBS: Delay Before SPCK.
+ * This field defines the delay from NPCS valid to the first valid SPCK
+ * transition. When DLYBS equals zero, the NPCS valid to SPCK transition is
+ * 1/2 the SPCK clock period.
+ * Otherwise, the following equations determine the delay:
+ *
+ * Delay Before SPCK = DLYBS / SPI_CLK
+ *
+ * For a 2uS delay
+ *
+ * DLYBS = SPI_CLK * 0.000002 = SPI_CLK / 500000
+ *
+ * TODO: Check for boundaries!
+ */
+
+ dlybs = SAM_QSPI_CLOCK;
+ dlybs *= startdelay;
+ dlybs /= 1000000000;
Review Comment:
You're right, doesn't make much sense for it to be more verbose. Changed
##########
arch/arm/src/samv7/sam_qspi_spi.c:
##########
@@ -398,6 +406,109 @@ static uint32_t qspi_spi_setfrequency(struct spi_dev_s *dev,
return actual;
}
+/****************************************************************************
+ * Name: qspi_spi_setdelay
+ *
+ * Description:
+ * Set the QSPI Delays in nanoseconds. Optional.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * startdelay - The delay between CS active and first CLK
+ * stopdelay - The delay between last CLK and CS inactive
+ * csdelay - The delay between CS inactive and CS active again
+ * ifdelay - The delay between frames
+ *
+ * Returned Value:
+ * Returns 0 if ok
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_DELAY_CONTROL
+static int qspi_spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
+ uint32_t stopdelay, uint32_t csdelay,
+ uint32_t ifdelay)
+{
+ struct sam_spidev_s *spi = &g_spidev;
+ uint64_t dlybs;
+ uint64_t dlybct;
+ uint64_t dlybcs;
+ uint32_t regval;
+
+ spiinfo("startdelay=%" PRIu32 "\n", startdelay);
+ spiinfo("stopdelay=%" PRIu32 "\n", stopdelay);
+ spiinfo("csdelay=%" PRIu32 "\n", csdelay);
+ spiinfo("ifdelay=%" PRIu32 "\n", ifdelay);
+
+ /* startdelay = DLYBS: Delay Before SPCK.
+ * This field defines the delay from NPCS valid to the first valid SPCK
+ * transition. When DLYBS equals zero, the NPCS valid to SPCK transition is
+ * 1/2 the SPCK clock period.
+ * Otherwise, the following equations determine the delay:
+ *
+ * Delay Before SPCK = DLYBS / SPI_CLK
+ *
+ * For a 2uS delay
+ *
+ * DLYBS = SPI_CLK * 0.000002 = SPI_CLK / 500000
+ *
+ * TODO: Check for boundaries!
+ */
+
+ dlybs = SAM_QSPI_CLOCK;
+ dlybs *= startdelay;
+ dlybs /= 1000000000;
+ regval = qspi_getreg(spi, SAM_QSPI_SCR_OFFSET);
+ regval &= ~QSPI_SCR_DLYBS_MASK;
+ regval |= (uint32_t) dlybs << QSPI_SCR_DLYBS_SHIFT;
+ qspi_putreg(spi, regval, SAM_QSPI_SCR_OFFSET);
+
+ /* ifdelay = DLYBCT: Delay Between Consecutive Transfers.
+ * This field defines the delay between two consecutive transfers with the
+ * same peripheral without removing the chip select. The delay is always
+ * inserted after each transfer and before removing the chip select if
+ * needed.
+ *
+ * Delay Between Consecutive Transfers = (32 x DLYBCT) / SPI_CLK
+ *
+ * For a 5uS delay:
+ *
+ * DLYBCT = SPI_CLK * 0.000005 / 32 = SPI_CLK / 200000 / 32
+ */
+
+ dlybct = SAM_QSPI_CLOCK;
+ dlybct *= ifdelay;
+ dlybct /= 1000000000;
+ dlybct /= 32;
Review Comment:
Changed
##########
arch/arm/src/samv7/sam_qspi_spi.c:
##########
@@ -398,6 +406,109 @@ static uint32_t qspi_spi_setfrequency(struct spi_dev_s *dev,
return actual;
}
+/****************************************************************************
+ * Name: qspi_spi_setdelay
+ *
+ * Description:
+ * Set the QSPI Delays in nanoseconds. Optional.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * startdelay - The delay between CS active and first CLK
+ * stopdelay - The delay between last CLK and CS inactive
+ * csdelay - The delay between CS inactive and CS active again
+ * ifdelay - The delay between frames
+ *
+ * Returned Value:
+ * Returns 0 if ok
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_DELAY_CONTROL
+static int qspi_spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
+ uint32_t stopdelay, uint32_t csdelay,
+ uint32_t ifdelay)
+{
+ struct sam_spidev_s *spi = &g_spidev;
+ uint64_t dlybs;
+ uint64_t dlybct;
+ uint64_t dlybcs;
+ uint32_t regval;
+
+ spiinfo("startdelay=%" PRIu32 "\n", startdelay);
+ spiinfo("stopdelay=%" PRIu32 "\n", stopdelay);
+ spiinfo("csdelay=%" PRIu32 "\n", csdelay);
+ spiinfo("ifdelay=%" PRIu32 "\n", ifdelay);
+
+ /* startdelay = DLYBS: Delay Before SPCK.
+ * This field defines the delay from NPCS valid to the first valid SPCK
+ * transition. When DLYBS equals zero, the NPCS valid to SPCK transition is
+ * 1/2 the SPCK clock period.
+ * Otherwise, the following equations determine the delay:
+ *
+ * Delay Before SPCK = DLYBS / SPI_CLK
+ *
+ * For a 2uS delay
+ *
+ * DLYBS = SPI_CLK * 0.000002 = SPI_CLK / 500000
+ *
+ * TODO: Check for boundaries!
+ */
+
+ dlybs = SAM_QSPI_CLOCK;
+ dlybs *= startdelay;
+ dlybs /= 1000000000;
+ regval = qspi_getreg(spi, SAM_QSPI_SCR_OFFSET);
+ regval &= ~QSPI_SCR_DLYBS_MASK;
+ regval |= (uint32_t) dlybs << QSPI_SCR_DLYBS_SHIFT;
+ qspi_putreg(spi, regval, SAM_QSPI_SCR_OFFSET);
+
+ /* ifdelay = DLYBCT: Delay Between Consecutive Transfers.
+ * This field defines the delay between two consecutive transfers with the
+ * same peripheral without removing the chip select. The delay is always
+ * inserted after each transfer and before removing the chip select if
+ * needed.
+ *
+ * Delay Between Consecutive Transfers = (32 x DLYBCT) / SPI_CLK
+ *
+ * For a 5uS delay:
+ *
+ * DLYBCT = SPI_CLK * 0.000005 / 32 = SPI_CLK / 200000 / 32
+ */
+
+ dlybct = SAM_QSPI_CLOCK;
+ dlybct *= ifdelay;
+ dlybct /= 1000000000;
+ dlybct /= 32;
+ regval = qspi_getreg(spi, SAM_QSPI_MR_OFFSET);
+ regval &= ~(QSPI_MR_DLYBCT_MASK);
+ regval |= (uint32_t) dlybct << QSPI_MR_DLYBCT_SHIFT;
+ qspi_putreg(spi, regval, SAM_QSPI_MR_OFFSET);
+
+ /* csdelay = DLYBCS: Delay Between Chip Selects.
+ * This field defines the delay between the inactivation and the activation
+ * of NPCS. The DLYBCS time guarantees non-overlapping chip selects and
+ * solves bus contentions in case of peripherals having long data float
+ * times. If DLYBCS is lower than 6, six peripheral clock periods are
+ * inserted by default.
+ *
+ * Delay Between Chip Selects = DLYBCS / SPI_CLK
+ *
+ * DLYBCS = SPI_CLK * Delay
+ */
+
+ dlybcs = SAM_QSPI_CLOCK;
+ dlybcs *= csdelay;
+ dlybcs /= 1000000000;
Review Comment:
Changed
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Re: [PR] arch/arm/src/samv7/sam_qspi_spi.c: add support for SPI_SETDELAY [nuttx]
Posted by "acassis (via GitHub)" <gi...@apache.org>.
acassis commented on code in PR #17389:
URL: https://github.com/apache/nuttx/pull/17389#discussion_r2568205587
##########
arch/arm/src/samv7/sam_qspi_spi.c:
##########
@@ -398,6 +406,109 @@ static uint32_t qspi_spi_setfrequency(struct spi_dev_s *dev,
return actual;
}
+/****************************************************************************
+ * Name: qspi_spi_setdelay
+ *
+ * Description:
+ * Set the QSPI Delays in nanoseconds. Optional.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * startdelay - The delay between CS active and first CLK
+ * stopdelay - The delay between last CLK and CS inactive
+ * csdelay - The delay between CS inactive and CS active again
+ * ifdelay - The delay between frames
+ *
+ * Returned Value:
+ * Returns 0 if ok
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_DELAY_CONTROL
+static int qspi_spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
+ uint32_t stopdelay, uint32_t csdelay,
+ uint32_t ifdelay)
+{
+ struct sam_spidev_s *spi = &g_spidev;
+ uint64_t dlybs;
+ uint64_t dlybct;
+ uint64_t dlybcs;
+ uint32_t regval;
+
+ spiinfo("startdelay=%" PRIu32 "\n", startdelay);
+ spiinfo("stopdelay=%" PRIu32 "\n", stopdelay);
+ spiinfo("csdelay=%" PRIu32 "\n", csdelay);
+ spiinfo("ifdelay=%" PRIu32 "\n", ifdelay);
+
+ /* startdelay = DLYBS: Delay Before SPCK.
+ * This field defines the delay from NPCS valid to the first valid SPCK
+ * transition. When DLYBS equals zero, the NPCS valid to SPCK transition is
+ * 1/2 the SPCK clock period.
+ * Otherwise, the following equations determine the delay:
+ *
+ * Delay Before SPCK = DLYBS / SPI_CLK
+ *
+ * For a 2uS delay
+ *
+ * DLYBS = SPI_CLK * 0.000002 = SPI_CLK / 500000
+ *
+ * TODO: Check for boundaries!
+ */
+
+ dlybs = SAM_QSPI_CLOCK;
+ dlybs *= startdelay;
+ dlybs /= 1000000000;
Review Comment:
I'm ok these three lines, but why not just use:
dlybs = (SAM_QSPI_CLOCK * startdelay) / 1000000000;
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Re: [PR] arch/arm/src/samv7/sam_qspi_spi.c: add support for SPI_SETDELAY [nuttx]
Posted by "acassis (via GitHub)" <gi...@apache.org>.
acassis commented on code in PR #17389:
URL: https://github.com/apache/nuttx/pull/17389#discussion_r2568205587
##########
arch/arm/src/samv7/sam_qspi_spi.c:
##########
@@ -398,6 +406,109 @@ static uint32_t qspi_spi_setfrequency(struct spi_dev_s *dev,
return actual;
}
+/****************************************************************************
+ * Name: qspi_spi_setdelay
+ *
+ * Description:
+ * Set the QSPI Delays in nanoseconds. Optional.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * startdelay - The delay between CS active and first CLK
+ * stopdelay - The delay between last CLK and CS inactive
+ * csdelay - The delay between CS inactive and CS active again
+ * ifdelay - The delay between frames
+ *
+ * Returned Value:
+ * Returns 0 if ok
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_DELAY_CONTROL
+static int qspi_spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
+ uint32_t stopdelay, uint32_t csdelay,
+ uint32_t ifdelay)
+{
+ struct sam_spidev_s *spi = &g_spidev;
+ uint64_t dlybs;
+ uint64_t dlybct;
+ uint64_t dlybcs;
+ uint32_t regval;
+
+ spiinfo("startdelay=%" PRIu32 "\n", startdelay);
+ spiinfo("stopdelay=%" PRIu32 "\n", stopdelay);
+ spiinfo("csdelay=%" PRIu32 "\n", csdelay);
+ spiinfo("ifdelay=%" PRIu32 "\n", ifdelay);
+
+ /* startdelay = DLYBS: Delay Before SPCK.
+ * This field defines the delay from NPCS valid to the first valid SPCK
+ * transition. When DLYBS equals zero, the NPCS valid to SPCK transition is
+ * 1/2 the SPCK clock period.
+ * Otherwise, the following equations determine the delay:
+ *
+ * Delay Before SPCK = DLYBS / SPI_CLK
+ *
+ * For a 2uS delay
+ *
+ * DLYBS = SPI_CLK * 0.000002 = SPI_CLK / 500000
+ *
+ * TODO: Check for boundaries!
+ */
+
+ dlybs = SAM_QSPI_CLOCK;
+ dlybs *= startdelay;
+ dlybs /= 1000000000;
Review Comment:
I'm ok this these three lines, but why not just use:
dlybs = (SAM_QSPI_CLOCK * startdelay) / 1000000000;
##########
arch/arm/src/samv7/sam_qspi_spi.c:
##########
@@ -398,6 +406,109 @@ static uint32_t qspi_spi_setfrequency(struct spi_dev_s *dev,
return actual;
}
+/****************************************************************************
+ * Name: qspi_spi_setdelay
+ *
+ * Description:
+ * Set the QSPI Delays in nanoseconds. Optional.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * startdelay - The delay between CS active and first CLK
+ * stopdelay - The delay between last CLK and CS inactive
+ * csdelay - The delay between CS inactive and CS active again
+ * ifdelay - The delay between frames
+ *
+ * Returned Value:
+ * Returns 0 if ok
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_DELAY_CONTROL
+static int qspi_spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
+ uint32_t stopdelay, uint32_t csdelay,
+ uint32_t ifdelay)
+{
+ struct sam_spidev_s *spi = &g_spidev;
+ uint64_t dlybs;
+ uint64_t dlybct;
+ uint64_t dlybcs;
+ uint32_t regval;
+
+ spiinfo("startdelay=%" PRIu32 "\n", startdelay);
+ spiinfo("stopdelay=%" PRIu32 "\n", stopdelay);
+ spiinfo("csdelay=%" PRIu32 "\n", csdelay);
+ spiinfo("ifdelay=%" PRIu32 "\n", ifdelay);
+
+ /* startdelay = DLYBS: Delay Before SPCK.
+ * This field defines the delay from NPCS valid to the first valid SPCK
+ * transition. When DLYBS equals zero, the NPCS valid to SPCK transition is
+ * 1/2 the SPCK clock period.
+ * Otherwise, the following equations determine the delay:
+ *
+ * Delay Before SPCK = DLYBS / SPI_CLK
+ *
+ * For a 2uS delay
+ *
+ * DLYBS = SPI_CLK * 0.000002 = SPI_CLK / 500000
+ *
+ * TODO: Check for boundaries!
+ */
+
+ dlybs = SAM_QSPI_CLOCK;
+ dlybs *= startdelay;
+ dlybs /= 1000000000;
+ regval = qspi_getreg(spi, SAM_QSPI_SCR_OFFSET);
+ regval &= ~QSPI_SCR_DLYBS_MASK;
+ regval |= (uint32_t) dlybs << QSPI_SCR_DLYBS_SHIFT;
+ qspi_putreg(spi, regval, SAM_QSPI_SCR_OFFSET);
+
+ /* ifdelay = DLYBCT: Delay Between Consecutive Transfers.
+ * This field defines the delay between two consecutive transfers with the
+ * same peripheral without removing the chip select. The delay is always
+ * inserted after each transfer and before removing the chip select if
+ * needed.
+ *
+ * Delay Between Consecutive Transfers = (32 x DLYBCT) / SPI_CLK
+ *
+ * For a 5uS delay:
+ *
+ * DLYBCT = SPI_CLK * 0.000005 / 32 = SPI_CLK / 200000 / 32
+ */
+
+ dlybct = SAM_QSPI_CLOCK;
+ dlybct *= ifdelay;
+ dlybct /= 1000000000;
+ dlybct /= 32;
+ regval = qspi_getreg(spi, SAM_QSPI_MR_OFFSET);
+ regval &= ~(QSPI_MR_DLYBCT_MASK);
+ regval |= (uint32_t) dlybct << QSPI_MR_DLYBCT_SHIFT;
+ qspi_putreg(spi, regval, SAM_QSPI_MR_OFFSET);
+
+ /* csdelay = DLYBCS: Delay Between Chip Selects.
+ * This field defines the delay between the inactivation and the activation
+ * of NPCS. The DLYBCS time guarantees non-overlapping chip selects and
+ * solves bus contentions in case of peripherals having long data float
+ * times. If DLYBCS is lower than 6, six peripheral clock periods are
+ * inserted by default.
+ *
+ * Delay Between Chip Selects = DLYBCS / SPI_CLK
+ *
+ * DLYBCS = SPI_CLK * Delay
+ */
+
+ dlybcs = SAM_QSPI_CLOCK;
+ dlybcs *= csdelay;
+ dlybcs /= 1000000000;
Review Comment:
Ditto
##########
arch/arm/src/samv7/sam_qspi_spi.c:
##########
@@ -398,6 +406,109 @@ static uint32_t qspi_spi_setfrequency(struct spi_dev_s *dev,
return actual;
}
+/****************************************************************************
+ * Name: qspi_spi_setdelay
+ *
+ * Description:
+ * Set the QSPI Delays in nanoseconds. Optional.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * startdelay - The delay between CS active and first CLK
+ * stopdelay - The delay between last CLK and CS inactive
+ * csdelay - The delay between CS inactive and CS active again
+ * ifdelay - The delay between frames
+ *
+ * Returned Value:
+ * Returns 0 if ok
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_DELAY_CONTROL
+static int qspi_spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
+ uint32_t stopdelay, uint32_t csdelay,
+ uint32_t ifdelay)
+{
+ struct sam_spidev_s *spi = &g_spidev;
+ uint64_t dlybs;
+ uint64_t dlybct;
+ uint64_t dlybcs;
+ uint32_t regval;
+
+ spiinfo("startdelay=%" PRIu32 "\n", startdelay);
+ spiinfo("stopdelay=%" PRIu32 "\n", stopdelay);
+ spiinfo("csdelay=%" PRIu32 "\n", csdelay);
+ spiinfo("ifdelay=%" PRIu32 "\n", ifdelay);
+
+ /* startdelay = DLYBS: Delay Before SPCK.
+ * This field defines the delay from NPCS valid to the first valid SPCK
+ * transition. When DLYBS equals zero, the NPCS valid to SPCK transition is
+ * 1/2 the SPCK clock period.
+ * Otherwise, the following equations determine the delay:
+ *
+ * Delay Before SPCK = DLYBS / SPI_CLK
+ *
+ * For a 2uS delay
+ *
+ * DLYBS = SPI_CLK * 0.000002 = SPI_CLK / 500000
+ *
+ * TODO: Check for boundaries!
+ */
+
+ dlybs = SAM_QSPI_CLOCK;
+ dlybs *= startdelay;
+ dlybs /= 1000000000;
+ regval = qspi_getreg(spi, SAM_QSPI_SCR_OFFSET);
+ regval &= ~QSPI_SCR_DLYBS_MASK;
+ regval |= (uint32_t) dlybs << QSPI_SCR_DLYBS_SHIFT;
+ qspi_putreg(spi, regval, SAM_QSPI_SCR_OFFSET);
+
+ /* ifdelay = DLYBCT: Delay Between Consecutive Transfers.
+ * This field defines the delay between two consecutive transfers with the
+ * same peripheral without removing the chip select. The delay is always
+ * inserted after each transfer and before removing the chip select if
+ * needed.
+ *
+ * Delay Between Consecutive Transfers = (32 x DLYBCT) / SPI_CLK
+ *
+ * For a 5uS delay:
+ *
+ * DLYBCT = SPI_CLK * 0.000005 / 32 = SPI_CLK / 200000 / 32
+ */
+
+ dlybct = SAM_QSPI_CLOCK;
+ dlybct *= ifdelay;
+ dlybct /= 1000000000;
+ dlybct /= 32;
Review Comment:
Same
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Re: [PR] arch/arm/src/samv7/sam_qspi_spi.c: add support for SPI_SETDELAY [nuttx]
Posted by "simbit18 (via GitHub)" <gi...@apache.org>.
simbit18 commented on PR #17389:
URL: https://github.com/apache/nuttx/pull/17389#issuecomment-3585850363
Hi @acassis, is an error that can occur in this step Docker Login
https://github.com/apache/nuttx/blob/master/.github/workflows/build.yml#L166-L171
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Re: [PR] arch/arm/src/samv7/sam_qspi_spi.c: add support for SPI_SETDELAY [nuttx]
Posted by "xiaoxiang781216 (via GitHub)" <gi...@apache.org>.
xiaoxiang781216 merged PR #17389:
URL: https://github.com/apache/nuttx/pull/17389
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Re: [PR] arch/arm/src/samv7/sam_qspi_spi.c: add support for SPI_SETDELAY [nuttx]
Posted by "acassis (via GitHub)" <gi...@apache.org>.
acassis commented on PR #17389:
URL: https://github.com/apache/nuttx/pull/17389#issuecomment-3585613981
@simbit18 did you know this error:
Logging into ghcr.io...
Error: Error response from daemon: Get "https://ghcr.io/v2/": context deadline exceeded
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