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Posted to commits@mynewt.apache.org by je...@apache.org on 2020/05/11 09:00:31 UTC
[mynewt-core] branch master updated (6c613b9 -> f664e2d)
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git.
from 6c613b9 sys/console/full: Fix semihosting pointer arithmetic
new 1b0dc39 stm32l4xx: Fix clock discrepancies
new f664e2d nucleo-l476rg: Fix PLL configuration
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
hw/bsp/nucleo-l476rg/syscfg.yml | 14 +++++++-------
hw/mcu/stm/stm32l4xx/syscfg.yml | 8 ++++----
2 files changed, 11 insertions(+), 11 deletions(-)
[mynewt-core] 02/02: nucleo-l476rg: Fix PLL configuration
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit f664e2d3cbeabdf27ace346e22ec4a116eda0f1e
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Wed May 6 08:56:06 2020 +0200
nucleo-l476rg: Fix PLL configuration
PLL was configured to produce 64MHz clock, yet PLLM and PLLN
produced fVCO = 16 / 1 * 24 = 384MHz which is outside allowed
range (64-344).
With this change:
- PLLx values are specified according to specification
- System clock is changed to 80MHz
- Flash latency is updated to reflect this higher speed
- MSI is configured to run at 48MHz (instead of 16) and can now
be used directly as USB clock source.
---
hw/bsp/nucleo-l476rg/syscfg.yml | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/bsp/nucleo-l476rg/syscfg.yml b/hw/bsp/nucleo-l476rg/syscfg.yml
index de38f02..406ac42 100644
--- a/hw/bsp/nucleo-l476rg/syscfg.yml
+++ b/hw/bsp/nucleo-l476rg/syscfg.yml
@@ -34,20 +34,20 @@ syscfg.vals:
STM32_CLOCK_LSE_BYPASS: 0
STM32_CLOCK_MSI: 1
STM32_CLOCK_MSI_CALIBRATION: 'RCC_MSICALIBRATION_DEFAULT'
- STM32_CLOCK_MSI_CLOCK_RANGE: 'RCC_MSIRANGE_8' # 16MHz
+ STM32_CLOCK_MSI_CLOCK_RANGE: 'RCC_MSIRANGE_11' # 48MHz
STM32_CLOCK_HSI: 0
STM32_CLOCK_HSI_CALIBRATION: 'RCC_HSICALIBRATION_DEFAULT'
STM32_CLOCK_HSE: 0
STM32_CLOCK_HSE_BYPASS: 0
- STM32_CLOCK_PLL_PLLM: 1 # 16 / 1 = 16MHz
- STM32_CLOCK_PLL_PLLN: 24 # 16 * 24 = 384MHz
- STM32_CLOCK_PLL_PLLP: 7 # 384 / 7 = 54.85MHz
- STM32_CLOCK_PLL_PLLR: 6 # 384 / 6 = 64MHz
- STM32_CLOCK_PLL_PLLQ: 8 # 384 / 8 = 48MHz
+ STM32_CLOCK_PLL_PLLM: 6 # 48 / 6 = 8MHz
+ STM32_CLOCK_PLL_PLLN: 40 # 48 / 6 * 24 = 320MHz
+ STM32_CLOCK_PLL_PLLP: 7 # 320 / 7 = 45.71MHz
+ STM32_CLOCK_PLL_PLLR: 4 # 320 / 4 = 80MHz
+ STM32_CLOCK_PLL_PLLQ: 4 # 320 / 4 = 80MHz
STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV1'
STM32_CLOCK_APB2_DIVIDER: 'RCC_HCLK_DIV1'
- STM32_FLASH_LATENCY: 'FLASH_LATENCY_3' # max 64MHz
+ STM32_FLASH_LATENCY: 'FLASH_LATENCY_4' # max 80MHz
STM32_FLASH_PREFETCH_ENABLE: 0
STM32_INSTRUCTION_CACHE_ENABLE: 1
STM32_DATA_CACHE_ENABLE: 1
[mynewt-core] 01/02: stm32l4xx: Fix clock discrepancies
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 1b0dc396d87d390e82b7d22b330141bc86783b7a
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Wed May 6 08:35:10 2020 +0200
stm32l4xx: Fix clock discrepancies
syscfg default value for MSI clock was using constant
suitable for calibration filed resulting in default
MSI clock speed 100kHz.
AHB, APB1, APB2 dividers descriptions mentioned 64MHz
max frequencies while this MCU has 80MHz limit.
---
hw/mcu/stm/stm32l4xx/syscfg.yml | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/mcu/stm/stm32l4xx/syscfg.yml b/hw/mcu/stm/stm32l4xx/syscfg.yml
index eb778c6..8a92651 100644
--- a/hw/mcu/stm/stm32l4xx/syscfg.yml
+++ b/hw/mcu/stm/stm32l4xx/syscfg.yml
@@ -53,7 +53,7 @@ syscfg.defs:
STM32_CLOCK_MSI_CLOCK_RANGE:
description: MSI clock range
- value: 'RCC_MSICALIBRATION_DEFAULT'
+ value: 'RCC_MSIRANGE_8'
STM32_CLOCK_HSE:
description: Enable high-speed external clock source
@@ -96,15 +96,15 @@ syscfg.defs:
value: 0
STM32_CLOCK_AHB_DIVIDER:
- description: AHB CLK1 prescaler (64MHz max)
+ description: AHB CLK1 prescaler (80MHz max)
value: 0
STM32_CLOCK_APB1_DIVIDER:
- description: APB low-speed prescaler (64MHz max)
+ description: APB low-speed prescaler (80MHz max)
value: 0
STM32_CLOCK_APB2_DIVIDER:
- description: APB high-speed prescaler (64MHz max)
+ description: APB high-speed prescaler (80MHz max)
value: 0
STM32_FLASH_LATENCY: