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Posted to commits@nuttx.apache.org by xi...@apache.org on 2023/12/11 10:10:20 UTC
(nuttx) branch master updated: Extend MMU Flags to 64-bit for T-Head C906 and Svpbmt
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 0bac2efd0e Extend MMU Flags to 64-bit for T-Head C906 and Svpbmt
0bac2efd0e is described below
commit 0bac2efd0e4ca34cd3e9f7b665c2b023de80e887
Author: Lee Lup Yuen <lu...@appkaki.com>
AuthorDate: Sat Dec 9 20:12:52 2023 +0800
Extend MMU Flags to 64-bit for T-Head C906 and Svpbmt
Currently RISC-V NuttX supports 32-bit MMU Flags inside a Page Table Entry. This PR extends the MMU Flags to 64-bit, to support T-Head C906 Core and the new RISC-V Svpbmt Extension.
T-Head C906 uses Bits 59 to 63 in a Leaf Page Table Entry to configure the Memory Type: Cacheable / Bufferable / Strongly-Ordered. For the upcoming port of NuttX to PINE64 Ox64 BL808 SBC, we need to set the Memory Type to Strongly-Ordered for I/O Memory, which requires 64-bit MMU Flags.
Details of C906 MMU: https://lupyuen.github.io/articles/plic3#t-head-errata
Newer RISC-V Cores will use the Svpbmt Extension to configure the Memory Type (Cacheable / Strongly-Ordered). Svpbmt uses Bits 61 to 62 in a Leaf Page Table Entry to define the Memory Type. This also requires 64-bit MMU Flags.
Details of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/main/src/supervisor.adoc#svpbmt
---
arch/risc-v/src/common/riscv_mmu.c | 4 ++--
arch/risc-v/src/common/riscv_mmu.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/risc-v/src/common/riscv_mmu.c b/arch/risc-v/src/common/riscv_mmu.c
index ffb5418760..efe69389d1 100644
--- a/arch/risc-v/src/common/riscv_mmu.c
+++ b/arch/risc-v/src/common/riscv_mmu.c
@@ -60,7 +60,7 @@ static const size_t g_pgt_sizes[] =
****************************************************************************/
void mmu_ln_setentry(uint32_t ptlevel, uintptr_t lnvaddr, uintptr_t paddr,
- uintptr_t vaddr, uint32_t mmuflags)
+ uintptr_t vaddr, uint64_t mmuflags)
{
uintptr_t *lntable = (uintptr_t *)lnvaddr;
uint32_t index;
@@ -136,7 +136,7 @@ void mmu_ln_restore(uint32_t ptlevel, uintptr_t lnvaddr, uintptr_t vaddr,
}
void mmu_ln_map_region(uint32_t ptlevel, uintptr_t lnvaddr, uintptr_t paddr,
- uintptr_t vaddr, size_t size, uint32_t mmuflags)
+ uintptr_t vaddr, size_t size, uint64_t mmuflags)
{
uintptr_t end_paddr = paddr + size;
size_t page_size = g_pgt_sizes[ptlevel - 1];
diff --git a/arch/risc-v/src/common/riscv_mmu.h b/arch/risc-v/src/common/riscv_mmu.h
index 6c9d1baebb..a1d3de36b1 100644
--- a/arch/risc-v/src/common/riscv_mmu.h
+++ b/arch/risc-v/src/common/riscv_mmu.h
@@ -367,7 +367,7 @@ static inline uintptr_t mmu_get_satp_pgbase(void)
****************************************************************************/
void mmu_ln_setentry(uint32_t ptlevel, uintptr_t lnvaddr, uintptr_t paddr,
- uintptr_t vaddr, uint32_t mmuflags);
+ uintptr_t vaddr, uint64_t mmuflags);
/****************************************************************************
* Name: mmu_ln_getentry
@@ -448,7 +448,7 @@ void mmu_ln_restore(uint32_t ptlevel, uintptr_t lnvaddr, uintptr_t vaddr,
****************************************************************************/
void mmu_ln_map_region(uint32_t ptlevel, uintptr_t lnvaddr, uintptr_t paddr,
- uintptr_t vaddr, size_t size, uint32_t mmuflags);
+ uintptr_t vaddr, size_t size, uint64_t mmuflags);
/****************************************************************************
* Name: mmu_ln_map_region