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Posted to commits@nuttx.apache.org by xi...@apache.org on 2020/04/11 05:53:30 UTC
[incubator-nuttx] 01/02: Fixes build issues associated with ARMv7-m
mpu support files. - inline functions within mpu.h converted to macros or
moved to up_mpu.c - mpu.h and up_mpu.c are now conditionally included in
build via CONFIG_ARM_MPU
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit acb16e087a664b185438453d6dea38b7695b9a5b
Author: John Rippetoe <jr...@roboticresearch.com>
AuthorDate: Fri Mar 27 14:43:35 2020 -0400
Fixes build issues associated with ARMv7-m mpu support files.
- inline functions within mpu.h converted to macros or moved to up_mpu.c
- mpu.h and up_mpu.c are now conditionally included in build via CONFIG_ARM_MPU
Chips affected by these changes
- imxrt
- kinetis
- lpc17xx
- lpc43xx
- lpc54xx
- sam34
- stm32
- stm32f7
- stm32h7
- stm32l4
- tiva
- xmc4
---
arch/arm/src/armv7-m/mpu.h | 336 +++++++++++++-------------------
arch/arm/src/armv7-m/up_mpu.c | 87 +++++++++
arch/arm/src/imxrt/Make.defs | 12 +-
arch/arm/src/kinetis/Make.defs | 6 +-
arch/arm/src/lpc17xx_40xx/Make.defs | 6 +-
arch/arm/src/lpc43xx/Make.defs | 6 +-
arch/arm/src/lpc54xx/Make.defs | 6 +-
arch/arm/src/sam34/Make.defs | 6 +-
arch/arm/src/stm32/Make.defs | 6 +-
arch/arm/src/stm32/stm32_allocateheap.c | 8 +-
arch/arm/src/stm32f7/Make.defs | 6 +-
arch/arm/src/stm32h7/Kconfig | 1 +
arch/arm/src/stm32h7/Make.defs | 8 +-
arch/arm/src/stm32l4/Make.defs | 6 +-
arch/arm/src/tiva/Make.defs | 6 +-
arch/arm/src/xmc4/Make.defs | 6 +-
16 files changed, 293 insertions(+), 219 deletions(-)
diff --git a/arch/arm/src/armv7-m/mpu.h b/arch/arm/src/armv7-m/mpu.h
index 0069655..b987e42 100644
--- a/arch/arm/src/armv7-m/mpu.h
+++ b/arch/arm/src/armv7-m/mpu.h
@@ -87,7 +87,7 @@
/* MPU Region Number Register Bit Definitions */
-#if defined(CONFIG_ARM_MPU_NREGIONS)
+#if defined(CONFIG_ARM_MPU_NREGIONS) && defined(CONFIG_ARM_MPU)
# if CONFIG_ARM_MPU_NREGIONS <= 8
# define MPU_RNR_MASK (0x00000007)
# elif CONFIG_ARM_MPU_NREGIONS <= 16
@@ -132,7 +132,7 @@
# define MPU_RASR_TEX_SO (0 << MPU_RASR_TEX_SHIFT) /* Strongly Ordered */
# define MPU_RASR_TEX_NOR (1 << MPU_RASR_TEX_SHIFT) /* Normal */
# define MPU_RASR_TEX_DEV (2 << MPU_RASR_TEX_SHIFT) /* Device */
-# define MPU_RASR_TEX_BB(bb) (4|(bb)) << MPU_RASR_TEX_SHIFT) /* Normal BB AA */
+# define MPU_RASR_TEX_BB(bb) ((4|(bb)) << MPU_RASR_TEX_SHIFT) /* Normal BB AA */
# define MPU_RASR_CP_NC (0) /* Non-cacheable */
# define MPU_RASR_CP_WBRA (1) /* Write back, write and Read- Allocate */
# define MPU_RASR_CP_WT (2) /* Write through, no Write-Allocate */
@@ -147,6 +147,8 @@
# define MPU_RASR_AP_RORO (6 << MPU_RASR_AP_SHIFT) /* P:RO U:RO */
# define MPU_RASR_XN (1 << 28) /* Bit 28: Instruction access disable */
+#ifdef CONFIG_ARM_MPU
+
/*****************************************************************************
* Public Function Prototypes
*****************************************************************************/
@@ -214,114 +216,51 @@ uint8_t mpu_log2regionfloor(size_t size);
uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size);
/*****************************************************************************
- * Inline Functions
- *****************************************************************************/
-
-/*****************************************************************************
- * Name: mpu_showtype
+ * Name: mpu_control
*
* Description:
- * Show the characteristics of the MPU
+ * Configure and enable (or disable) the MPU
*
*****************************************************************************/
-static inline void mpu_showtype(void)
-{
-#ifdef CONFIG_DEBUG_SCHED_INFO
- uint32_t regval = getreg32(MPU_TYPE);
-
- sinfo("%s MPU Regions: data=%d instr=%d\n",
- (regval & MPU_TYPE_SEPARATE) != 0 ? "Separate" : "Unified",
- (regval & MPU_TYPE_DREGION_MASK) >> MPU_TYPE_DREGION_SHIFT,
- (regval & MPU_TYPE_IREGION_MASK) >> MPU_TYPE_IREGION_SHIFT);
-#endif
-}
+void mpu_control(bool enable, bool hfnmiena, bool privdefena);
/*****************************************************************************
- * Name: mpu_control
+ * Name: mpu_configure_region
*
* Description:
- * Configure and enable (or disable) the MPU
+ * Configure a region for privileged, strongly ordered memory
*
*****************************************************************************/
-static inline void mpu_control(bool enable, bool hfnmiena, bool privdefena)
-{
- uint32_t regval = 0;
-
- if (enable)
- {
- regval |= MPU_CTRL_ENABLE; /* Enable the MPU */
+void mpu_configure_region(uintptr_t base, size_t size,
+ uint32_t flags);
- if (hfnmiena)
- {
- regval |= MPU_CTRL_HFNMIENA; /* Enable MPU during hard fault, NMI, and FAULTMAS */
- }
-
- if (privdefena)
- {
- regval |= MPU_CTRL_PRIVDEFENA; /* Enable privileged access to default memory map */
- }
- }
-
- putreg32(regval, MPU_CTRL);
-}
+/*****************************************************************************
+ * Inline Functions
+ *****************************************************************************/
/*****************************************************************************
- * Name: mpu_configure_region
+ * Name: mpu_showtype
*
* Description:
- * Configure a region for privileged, strongly ordered memory
+ * Show the characteristics of the MPU
*
*****************************************************************************/
-static inline void mpu_configure_region(uintptr_t base, size_t size,
- uint32_t flags)
-{
- unsigned int region = mpu_allocregion();
- uint32_t regval;
- uint8_t l2size;
- uint8_t subregions;
- uintptr_t alignedbase;
-
- /* Ensure the base address alignment
- *
- * ARMv7-M Architecture Reference Manual
- * B3.5.8 MPU Region Base Address Register, MPU_RBAR
- * "Software must ensure that the value written to the ADDR field
- * aligns with the size of the selected region."
- */
-
- alignedbase = base & MPU_RBAR_ADDR_MASK;
- l2size = mpu_log2regionceil(size + base - alignedbase);
- alignedbase &= ~((1 << l2size) - 1);
- l2size = mpu_log2regionceil(size + base - alignedbase);
-
- DEBUGASSERT(alignedbase + (1 << l2size) >= base + size);
- DEBUGASSERT(l2size == 5 || alignedbase + (1 << (l2size - 1)) < base + size);
- DEBUGASSERT((alignedbase & MPU_RBAR_ADDR_MASK) == alignedbase);
- DEBUGASSERT((alignedbase & ((1 << l2size) - 1)) == 0);
-
- /* Select the region */
-
- putreg32(region, MPU_RNR);
-
- /* Select the region base address */
-
- putreg32(alignedbase | region | MPU_RBAR_VALID, MPU_RBAR);
-
- /* Select the region size and the sub-region map */
-
- subregions = mpu_subregion(base, size, l2size);
-
- /* The configure the region */
-
- regval = MPU_RASR_ENABLE | /* Enable region */
- MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */
- ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */
- flags;
- putreg32(regval, MPU_RASR);
-}
+#ifdef CONFIG_DEBUG_SCHED_INFO
+# define mpu_showtype() \
+ do \
+ { \
+ uint32_t regval = getreg32(MPU_TYPE); \
+ sinfo("%s MPU Regions: data=%d instr=%d\n", \
+ (regval & MPU_TYPE_SEPARATE) != 0 ? "Separate" : "Unified", \
+ (regval & MPU_TYPE_DREGION_MASK) >> MPU_TYPE_DREGION_SHIFT, \
+ (regval & MPU_TYPE_IREGION_MASK) >> MPU_TYPE_IREGION_SHIFT); \
+ } while (0)
+#else
+# define mpu_showtype() do { } while (0)
+#endif
/*****************************************************************************
* Name: mpu_priv_stronglyordered
@@ -331,18 +270,18 @@ static inline void mpu_configure_region(uintptr_t base, size_t size,
*
*****************************************************************************/
-static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
-{
- /* The configure the region */
-
- mpu_configure_region(base, size,
- MPU_RASR_TEX_SO | /* Ordered */
- /* Not Cacheable */
- /* Not Bufferable */
- MPU_RASR_S | /* Shareable */
- MPU_RASR_AP_RWNO /* P:RW U:None */
- /* Instruction access */);
-}
+#define mpu_priv_stronglyordered(base, size) \
+ do \
+ { \
+ /* The configure the region */ \
+ mpu_configure_region(base, size, \
+ MPU_RASR_TEX_SO | /* Ordered */ \
+ /* Not Cacheable */ \
+ /* Not Bufferable */ \
+ MPU_RASR_S | /* Shareable */ \
+ MPU_RASR_AP_RWNO /* P:RW U:None */ \
+ /* Instruction access */); \
+ } while (0)
/*****************************************************************************
* Name: mpu_user_flash
@@ -352,18 +291,18 @@ static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
*
*****************************************************************************/
-static inline void mpu_user_flash(uintptr_t base, size_t size)
-{
- /* The configure the region */
-
- mpu_configure_region(base, size,
- MPU_RASR_TEX_SO | /* Ordered */
- MPU_RASR_C | /* Cacheable */
- /* Not Bufferable */
- /* Not Shareable */
- MPU_RASR_AP_RORO /* P:RO U:RO */
- /* Instruction access */);
-}
+#define mpu_user_flash(base, size) \
+ do \
+ { \
+ /* The configure the region */ \
+ mpu_configure_region(base, size, \
+ MPU_RASR_TEX_SO | /* Ordered */ \
+ MPU_RASR_C | /* Cacheable */ \
+ /* Not Bufferable */ \
+ /* Not Shareable */ \
+ MPU_RASR_AP_RORO /* P:RO U:RO */ \
+ /* Instruction access */); \
+ } while (0)
/*****************************************************************************
* Name: mpu_priv_flash
@@ -373,18 +312,18 @@ static inline void mpu_user_flash(uintptr_t base, size_t size)
*
*****************************************************************************/
-static inline void mpu_priv_flash(uintptr_t base, size_t size)
-{
- /* The configure the region */
-
-mpu_configure_region(base, size,
- MPU_RASR_TEX_SO | /* Ordered */
- MPU_RASR_C | /* Cacheable */
- /* Not Bufferable */
- /* Not Shareable */
- MPU_RASR_AP_RONO /* P:RO U:None */
- /* Instruction access */);
-}
+#define mpu_priv_flash(base, size) \
+ do \
+ { \
+ /* The configure the region */ \
+ mpu_configure_region(base, size, \
+ MPU_RASR_TEX_SO | /* Ordered */ \
+ MPU_RASR_C | /* Cacheable */ \
+ /* Not Bufferable */ \
+ /* Not Shareable */ \
+ MPU_RASR_AP_RONO /* P:RO U:None */ \
+ /* Instruction access */); \
+ } while (0)
/*****************************************************************************
* Name: mpu_user_intsram
@@ -394,18 +333,18 @@ mpu_configure_region(base, size,
*
*****************************************************************************/
-static inline void mpu_user_intsram(uintptr_t base, size_t size)
-{
- /* The configure the region */
-
- mpu_configure_region(base, size,
- MPU_RASR_TEX_SO | /* Ordered */
- MPU_RASR_C | /* Cacheable */
- /* Not Bufferable */
- MPU_RASR_S | /* Shareable */
- MPU_RASR_AP_RWRW /* P:RW U:RW */
- /* Instruction access */);
-}
+#define mpu_user_intsram(base, size) \
+ do \
+ { \
+ /* The configure the region */ \
+ mpu_configure_region(base, size, \
+ MPU_RASR_TEX_SO | /* Ordered */ \
+ MPU_RASR_C | /* Cacheable */ \
+ /* Not Bufferable */ \
+ MPU_RASR_S | /* Shareable */ \
+ MPU_RASR_AP_RWRW /* P:RW U:RW */ \
+ /* Instruction access */); \
+ } while (0)
/*****************************************************************************
* Name: mpu_priv_intsram
@@ -415,18 +354,18 @@ static inline void mpu_user_intsram(uintptr_t base, size_t size)
*
*****************************************************************************/
-static inline void mpu_priv_intsram(uintptr_t base, size_t size)
-{
- /* The configure the region */
-
- mpu_configure_region(base, size,
- MPU_RASR_TEX_SO | /* Ordered */
- MPU_RASR_C | /* Cacheable */
- /* Not Bufferable */
- MPU_RASR_S | /* Shareable */
- MPU_RASR_AP_RWNO /* P:RW U:None */
- /* Instruction access */);
-}
+#define mpu_priv_intsram(base, size) \
+ do \
+ { \
+ /* The configure the region */ \
+ mpu_configure_region(base, size,\
+ MPU_RASR_TEX_SO | /* Ordered */ \
+ MPU_RASR_C | /* Cacheable */ \
+ /* Not Bufferable */ \
+ MPU_RASR_S | /* Shareable */ \
+ MPU_RASR_AP_RWNO /* P:RW U:None */ \
+ /* Instruction access */); \
+ } while (0)
/*****************************************************************************
* Name: mpu_user_extsram
@@ -436,18 +375,18 @@ static inline void mpu_priv_intsram(uintptr_t base, size_t size)
*
*****************************************************************************/
-static inline void mpu_user_extsram(uintptr_t base, size_t size)
-{
- /* The configure the region */
-
- mpu_configure_region(base, size,
- MPU_RASR_TEX_SO | /* Ordered */
- MPU_RASR_C | /* Cacheable */
- MPU_RASR_B | /* Bufferable */
- MPU_RASR_S | /* Shareable */
- MPU_RASR_AP_RWRW /* P:RW U:RW */
- /* Instruction access */);
-}
+#define mpu_user_extsram(base, size) \
+ do \
+ { \
+ /* The configure the region */ \
+ mpu_configure_region(base, size, \
+ MPU_RASR_TEX_SO | /* Ordered */ \
+ MPU_RASR_C | /* Cacheable */ \
+ MPU_RASR_B | /* Bufferable */ \
+ MPU_RASR_S | /* Shareable */ \
+ MPU_RASR_AP_RWRW /* P:RW U:RW */ \
+ /* Instruction access */); \
+ } while (0)
/*****************************************************************************
* Name: mpu_priv_extsram
@@ -457,18 +396,18 @@ static inline void mpu_user_extsram(uintptr_t base, size_t size)
*
*****************************************************************************/
-static inline void mpu_priv_extsram(uintptr_t base, size_t size)
-{
- /* The configure the region */
-
- mpu_configure_region(base, size,
- MPU_RASR_TEX_SO | /* Ordered */
- MPU_RASR_C | /* Cacheable */
- MPU_RASR_B | /* Bufferable */
- MPU_RASR_S | /* Shareable */
- MPU_RASR_AP_RWNO /* P:RW U:None */
- /* Instruction access */);
-}
+#define mpu_priv_extsram(base, size) \
+ do \
+ { \
+ /* The configure the region */ \
+ mpu_configure_region(base, size, \
+ MPU_RASR_TEX_SO | /* Ordered */ \
+ MPU_RASR_C | /* Cacheable */ \
+ MPU_RASR_B | /* Bufferable */ \
+ MPU_RASR_S | /* Shareable */ \
+ MPU_RASR_AP_RWNO /* P:RW U:None */ \
+ /* Instruction access */); \
+ } while (0)
/*****************************************************************************
* Name: mpu_peripheral
@@ -478,18 +417,18 @@ static inline void mpu_priv_extsram(uintptr_t base, size_t size)
*
*****************************************************************************/
-static inline void mpu_peripheral(uintptr_t base, size_t size)
-{
- /* Then configure the region */
-
- mpu_configure_region(base, size,
- MPU_RASR_TEX_DEV | /* Device */
- /* Not Cacheable */
- MPU_RASR_B | /* Bufferable */
- MPU_RASR_S | /* Shareable */
- MPU_RASR_AP_RWNO | /* P:RW U:None */
- MPU_RASR_XN /* No Instruction access */);
-}
+#define mpu_peripheral(base, size) \
+ do \
+ { \
+ /* Then configure the region */ \
+ mpu_configure_region(base, size, \
+ MPU_RASR_TEX_DEV | /* Device */ \
+ /* Not Cacheable */ \
+ MPU_RASR_B | /* Bufferable */ \
+ MPU_RASR_S | /* Shareable */ \
+ MPU_RASR_AP_RWNO | /* P:RW U:None */ \
+ MPU_RASR_XN /* No Instruction access */); \
+ } while (0)
/*****************************************************************************
* Name: mpu_user_peripheral
@@ -499,18 +438,18 @@ static inline void mpu_peripheral(uintptr_t base, size_t size)
*
*****************************************************************************/
-static inline void mpu_user_peripheral(uintptr_t base, size_t size)
-{
- /* Then configure the region */
-
- mpu_configure_region(base, size,
- MPU_RASR_TEX_DEV | /* Device */
- /* Not Cacheable */
- MPU_RASR_B | /* Bufferable */
- MPU_RASR_S | /* Shareable */
- MPU_RASR_AP_RWRW | /* P:RW U:RW */
- MPU_RASR_XN /* No Instruction access */);
-}
+#define mpu_user_peripheral(base, size) \
+ do \
+ { \
+ /* Then configure the region */ \
+ mpu_configure_region(base, size, \
+ MPU_RASR_TEX_DEV | /* Device */ \
+ /* Not Cacheable */ \
+ MPU_RASR_B | /* Bufferable */ \
+ MPU_RASR_S | /* Shareable */ \
+ MPU_RASR_AP_RWRW | /* P:RW U:RW */ \
+ MPU_RASR_XN /* No Instruction access */); \
+ } while (0)
#undef EXTERN
#if defined(__cplusplus)
@@ -518,4 +457,5 @@ static inline void mpu_user_peripheral(uintptr_t base, size_t size)
#endif
#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_ARM_MPU */
#endif /* __ARCH_ARM_SRC_ARMV7M_MPU_H */
diff --git a/arch/arm/src/armv7-m/up_mpu.c b/arch/arm/src/armv7-m/up_mpu.c
index 3e802fd..94307b7 100644
--- a/arch/arm/src/armv7-m/up_mpu.c
+++ b/arch/arm/src/armv7-m/up_mpu.c
@@ -48,6 +48,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Configuration ************************************************************/
#ifndef CONFIG_ARM_MPU_NREGIONS
@@ -314,3 +315,89 @@ uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size)
ret |= mpu_subregion_ls(offset, l2size);
return ret;
}
+
+/*****************************************************************************
+ * Name: mpu_control
+ *
+ * Description:
+ * Configure and enable (or disable) the MPU
+ *
+ *****************************************************************************/
+
+void mpu_control(bool enable, bool hfnmiena, bool privdefena)
+{
+ uint32_t regval = 0;
+
+ if (enable)
+ {
+ regval |= MPU_CTRL_ENABLE; /* Enable the MPU */
+
+ if (hfnmiena)
+ {
+ regval |= MPU_CTRL_HFNMIENA; /* Enable MPU during hard fault, NMI, and FAULTMAS */
+ }
+
+ if (privdefena)
+ {
+ regval |= MPU_CTRL_PRIVDEFENA; /* Enable privileged access to default memory map */
+ }
+ }
+
+ putreg32(regval, MPU_CTRL);
+}
+
+/*****************************************************************************
+ * Name: mpu_configure_region
+ *
+ * Description:
+ * Configure a region for privileged, strongly ordered memory
+ *
+ *****************************************************************************/
+
+void mpu_configure_region(uintptr_t base, size_t size,
+ uint32_t flags)
+{
+ unsigned int region = mpu_allocregion();
+ uint32_t regval;
+ uint8_t l2size;
+ uint8_t subregions;
+ uintptr_t alignedbase;
+
+ /* Ensure the base address alignment
+ *
+ * ARMv7-M Architecture Reference Manual
+ * B3.5.8 MPU Region Base Address Register, MPU_RBAR
+ * "Software must ensure that the value written to the ADDR field
+ * aligns with the size of the selected region."
+ */
+
+ alignedbase = base & MPU_RBAR_ADDR_MASK;
+ l2size = mpu_log2regionceil(size + base - alignedbase);
+ alignedbase &= ~((1 << l2size) - 1);
+ l2size = mpu_log2regionceil(size + base - alignedbase);
+
+ DEBUGASSERT(alignedbase + (1 << l2size) >= base + size);
+ DEBUGASSERT(l2size == 5 || alignedbase + (1 << (l2size - 1)) < base + size);
+ DEBUGASSERT((alignedbase & MPU_RBAR_ADDR_MASK) == alignedbase);
+ DEBUGASSERT((alignedbase & ((1 << l2size) - 1)) == 0);
+
+ /* Select the region */
+
+ putreg32(region, MPU_RNR);
+
+ /* Select the region base address */
+
+ putreg32(alignedbase | region | MPU_RBAR_VALID, MPU_RBAR);
+
+ /* Select the region size and the sub-region map */
+
+ subregions = mpu_subregion(base, size, l2size);
+
+ /* The configure the region */
+
+ regval = MPU_RASR_ENABLE | /* Enable region */
+ MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */
+ ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */
+ flags;
+ putreg32(regval, MPU_RASR);
+}
diff --git a/arch/arm/src/imxrt/Make.defs b/arch/arm/src/imxrt/Make.defs
index af95ffc..c045b2a 100644
--- a/arch/arm/src/imxrt/Make.defs
+++ b/arch/arm/src/imxrt/Make.defs
@@ -73,8 +73,12 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif
+ifeq ($(CONFIG_ARM_MPU),y)
+CMN_CSRCS += up_mpu.c
+endif
+
ifeq ($(CONFIG_BUILD_PROTECTED),y)
-CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
+CMN_CSRCS += up_task_start.c up_pthread_start.c
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif
@@ -113,14 +117,12 @@ CHIP_CSRCS += imxrt_gpioirq.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
-ifneq ($(CONFIG_BUILD_PROTECTED),y)
-CMN_CSRCS += up_mpu.c
-endif
CHIP_CSRCS += imxrt_mpuinit.c
+endif
+
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += imxrt_userspace.c
endif
-endif
ifeq ($(CONFIG_IMXRT_EDMA),y)
CHIP_CSRCS += imxrt_edma.c
diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs
index 22f13de..0126ba0 100644
--- a/arch/arm/src/kinetis/Make.defs
+++ b/arch/arm/src/kinetis/Make.defs
@@ -71,8 +71,12 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif
+ifeq ($(CONFIG_ARM_MPU),y)
+CMN_CSRCS += up_mpu.c
+endif
+
ifeq ($(CONFIG_BUILD_PROTECTED),y)
-CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
+CMN_CSRCS += up_task_start.c up_pthread_start.c
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif
diff --git a/arch/arm/src/lpc17xx_40xx/Make.defs b/arch/arm/src/lpc17xx_40xx/Make.defs
index eac32bb..e611b3c 100644
--- a/arch/arm/src/lpc17xx_40xx/Make.defs
+++ b/arch/arm/src/lpc17xx_40xx/Make.defs
@@ -76,8 +76,12 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif
+ifeq ($(CONFIG_ARM_MPU),y)
+CMN_CSRCS += up_mpu.c
+endif
+
ifeq ($(CONFIG_BUILD_PROTECTED),y)
-CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
+CMN_CSRCS += up_task_start.c up_pthread_start.c
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif
diff --git a/arch/arm/src/lpc43xx/Make.defs b/arch/arm/src/lpc43xx/Make.defs
index eb62cd2..dc3b383 100644
--- a/arch/arm/src/lpc43xx/Make.defs
+++ b/arch/arm/src/lpc43xx/Make.defs
@@ -64,8 +64,12 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif
+ifeq ($(CONFIG_ARM_MPU),y)
+CMN_CSRCS += up_mpu.c
+endif
+
ifeq ($(CONFIG_BUILD_PROTECTED),y)
-CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
+CMN_CSRCS += up_task_start.c up_pthread_start.c
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif
diff --git a/arch/arm/src/lpc54xx/Make.defs b/arch/arm/src/lpc54xx/Make.defs
index e78516e..e95ad9b 100644
--- a/arch/arm/src/lpc54xx/Make.defs
+++ b/arch/arm/src/lpc54xx/Make.defs
@@ -64,8 +64,12 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif
+ifeq ($(CONFIG_ARM_MPU),y)
+CMN_CSRCS += up_mpu.c
+endif
+
ifeq ($(CONFIG_BUILD_PROTECTED),y)
-CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
+CMN_CSRCS += up_task_start.c up_pthread_start.c
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif
diff --git a/arch/arm/src/sam34/Make.defs b/arch/arm/src/sam34/Make.defs
index 0aee624..0192caf 100644
--- a/arch/arm/src/sam34/Make.defs
+++ b/arch/arm/src/sam34/Make.defs
@@ -80,8 +80,12 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif
+ifeq ($(CONFIG_ARM_MPU),y)
+CMN_CSRCS += up_mpu.c
+endif
+
ifeq ($(CONFIG_BUILD_PROTECTED),y)
-CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
+CMN_CSRCS += up_task_start.c up_pthread_start.c
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif
diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs
index 4656d05..30bb839 100644
--- a/arch/arm/src/stm32/Make.defs
+++ b/arch/arm/src/stm32/Make.defs
@@ -75,8 +75,12 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif
+ifeq ($(CONFIG_ARM_MPU),y)
+CMN_CSRCS += up_mpu.c
+endif
+
ifeq ($(CONFIG_BUILD_PROTECTED),y)
-CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
+CMN_CSRCS += up_task_start.c up_pthread_start.c
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif
diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c
index 2ce15ac..b802f63 100644
--- a/arch/arm/src/stm32/stm32_allocateheap.c
+++ b/arch/arm/src/stm32/stm32_allocateheap.c
@@ -53,13 +53,13 @@
#include <arch/board/board.h>
#include "chip.h"
-#ifdef CONFIG_ARM_MPU
-# include "mpu.h"
-# include "stm32_mpuinit.h"
-#endif
+
+#include "mpu.h"
#include "up_arch.h"
#include "up_internal.h"
+#include "stm32_mpuinit.h"
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs
index edf9115..62a94b5 100644
--- a/arch/arm/src/stm32f7/Make.defs
+++ b/arch/arm/src/stm32f7/Make.defs
@@ -93,8 +93,12 @@ ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
CMN_CSRCS += up_itm_syslog.c
endif
+ifeq ($(CONFIG_ARM_MPU),y)
+CMN_CSRCS += up_mpu.c
+endif
+
ifeq ($(CONFIG_BUILD_PROTECTED),y)
-CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
+CMN_CSRCS += up_task_start.c up_pthread_start.c
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif
diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig
index aa0be80..247876e 100644
--- a/arch/arm/src/stm32h7/Kconfig
+++ b/arch/arm/src/stm32h7/Kconfig
@@ -1186,6 +1186,7 @@ if STM32H7_BKPSRAM
config STM32H7_BBSRAM
bool "BBSRAM File Support"
default n
+ select ARM_MPU
config STM32H7_BBSRAM_FILES
int "Max Files to support in BBSRAM"
diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs
index 4a63041..ee0d871 100644
--- a/arch/arm/src/stm32h7/Make.defs
+++ b/arch/arm/src/stm32h7/Make.defs
@@ -92,8 +92,12 @@ ifeq ($(CONFIG_STM32H7_PROGMEM),y)
CMN_CSRCS += stm32_flash.c
endif
+ifeq ($(CONFIG_ARM_MPU),y)
+CMN_CSRCS += up_mpu.c
+endif
+
ifeq ($(CONFIG_BUILD_PROTECTED),y)
-CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
+CMN_CSRCS += up_task_start.c up_pthread_start.c
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif
@@ -130,7 +134,7 @@ endif
ifeq ($(CONFIG_STM32H7_BBSRAM),y)
ifeq ($(CONFIG_ARMV7M_DCACHE),y)
-ifeq ($(CONFIG_BUILD_PROTECTED),)
+ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += up_mpu.c
endif
endif
diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs
index 7656637..2c8356c 100644
--- a/arch/arm/src/stm32l4/Make.defs
+++ b/arch/arm/src/stm32l4/Make.defs
@@ -84,8 +84,12 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif
+ifeq ($(CONFIG_ARM_MPU),y)
+CMN_CSRCS += up_mpu.c
+endif
+
ifeq ($(CONFIG_BUILD_PROTECTED),y)
-CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
+CMN_CSRCS += up_task_start.c up_pthread_start.c
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif
diff --git a/arch/arm/src/tiva/Make.defs b/arch/arm/src/tiva/Make.defs
index dc23061..ae89ef0 100644
--- a/arch/arm/src/tiva/Make.defs
+++ b/arch/arm/src/tiva/Make.defs
@@ -83,8 +83,12 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c
endif
+ifeq ($(CONFIG_ARM_MPU),y)
+CMN_CSRCS += up_mpu.c
+endif
+
ifeq ($(CONFIG_BUILD_PROTECTED),y)
- CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
+ CMN_CSRCS += up_task_start.c up_pthread_start.c
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
else
diff --git a/arch/arm/src/xmc4/Make.defs b/arch/arm/src/xmc4/Make.defs
index 8e1cab8..f686dc1 100644
--- a/arch/arm/src/xmc4/Make.defs
+++ b/arch/arm/src/xmc4/Make.defs
@@ -71,8 +71,12 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif
+ifeq ($(CONFIG_ARM_MPU),y)
+CMN_CSRCS += up_mpu.c
+endif
+
ifeq ($(CONFIG_BUILD_PROTECTED),y)
-CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
+CMN_CSRCS += up_task_start.c up_pthread_start.c
CMN_CSRCS += up_signal_dispatch.c
CMN_UASRCS += up_signal_handler.S
endif