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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/01/18 10:19:16 UTC
[incubator-nuttx] branch master updated (9551de7 -> 4e1df81)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 9551de7 net: use HTONS, NTOHS, HTONL, NTOHL macro in kernel code
new 72ce934 boards/b-g431b-esc1: add option to select HSI or HSE as PLL source
new d3841eb boards/nucleo-g431rb: add option to select HSI or HSE ass PLL source
new 499c7ce boards/b-g431b-esc1: add CAN example
new 4e1df81 boards/nucleo-g431rb: add CAN example
The 4 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
boards/arm/stm32/b-g431b-esc1/Kconfig | 16 ++++
boards/arm/stm32/b-g431b-esc1/README.txt | 3 +
.../b-g431b-esc1/configs/{nsh => can}/defconfig | 16 +++-
boards/arm/stm32/b-g431b-esc1/include/board.h | 106 ++++++++++++++++++++-
boards/arm/stm32/b-g431b-esc1/src/Make.defs | 4 +
boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h | 17 ++++
boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c | 10 ++
.../src/stm32_can.c | 34 +++----
boards/arm/stm32/nucleo-g431rb/Kconfig | 12 +++
.../configs/{cordic => can}/defconfig | 16 ++--
boards/arm/stm32/nucleo-g431rb/include/board.h | 106 ++++++++++++++++++++-
boards/arm/stm32/nucleo-g431rb/src/Make.defs | 4 +
boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h | 12 +++
boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c | 10 ++
.../src/stm32_can.c | 20 ++--
15 files changed, 344 insertions(+), 42 deletions(-)
copy boards/arm/stm32/b-g431b-esc1/configs/{nsh => can}/defconfig (80%)
copy boards/arm/stm32/{olimex-stm32-p107 => b-g431b-esc1}/src/stm32_can.c (80%)
copy boards/arm/stm32/nucleo-g431rb/configs/{cordic => can}/defconfig (83%)
copy boards/arm/stm32/{stm3210e-eval => nucleo-g431rb}/src/stm32_can.c (88%)
[incubator-nuttx] 04/04: boards/nucleo-g431rb: add CAN example
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 4e1df81fa80b39681dae3507b378b47235714dd3
Author: raiden00pl <ra...@railab.me>
AuthorDate: Sat Jan 15 13:56:50 2022 +0100
boards/nucleo-g431rb: add CAN example
---
.../arm/stm32/nucleo-g431rb/configs/can/defconfig | 58 ++++++++++++++
boards/arm/stm32/nucleo-g431rb/include/board.h | 14 ++++
boards/arm/stm32/nucleo-g431rb/src/Make.defs | 4 +
boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h | 12 +++
boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c | 10 +++
boards/arm/stm32/nucleo-g431rb/src/stm32_can.c | 90 ++++++++++++++++++++++
6 files changed, 188 insertions(+)
diff --git a/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig
new file mode 100644
index 0000000..22c2934
--- /dev/null
+++ b/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig
@@ -0,0 +1,58 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_FPU is not set
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_NSH_CMDPARMS is not set
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+# CONFIG_NSH_DISABLE_PS is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="nucleo-g431rb"
+CONFIG_ARCH_BOARD_NUCLEO_G431RB=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CHIP="stm32"
+CONFIG_ARCH_CHIP_STM32=y
+CONFIG_ARCH_CHIP_STM32G431R=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=8499
+CONFIG_BOARD_NUCLEO_G431RB_USE_HSE=y
+CONFIG_BUILTIN=y
+CONFIG_CAN=y
+CONFIG_CAN_ERRORS=y
+CONFIG_CAN_EXTID=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_EXAMPLES_CAN=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=22528
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_START_DAY=14
+CONFIG_START_MONTH=10
+CONFIG_START_YEAR=2014
+CONFIG_STDIO_BUFFER_SIZE=512
+CONFIG_STM32_FDCAN1=y
+CONFIG_STM32_FDCAN1_BITRATE=250000
+CONFIG_STM32_FDCAN1_NTSEG1=13
+CONFIG_STM32_FDCAN1_NTSEG2=2
+CONFIG_STM32_JTAG_SW_ENABLE=y
+CONFIG_STM32_USART2=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_USART2_SERIAL_CONSOLE=y
diff --git a/boards/arm/stm32/nucleo-g431rb/include/board.h b/boards/arm/stm32/nucleo-g431rb/include/board.h
index ecadfef..a4580b7 100644
--- a/boards/arm/stm32/nucleo-g431rb/include/board.h
+++ b/boards/arm/stm32/nucleo-g431rb/include/board.h
@@ -247,6 +247,15 @@
#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY)
#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY)
+#ifdef CONFIG_STM32_FDCAN
+# ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSE
+# define STM32_CCIPR_FDCANSRC (RCC_CCIPR_FDCANSEL_HSE)
+# define STM32_FDCAN_FREQUENCY (STM32_HSE_FREQUENCY)
+# else
+# error For now FDCAN supported only if HSE enabled
+# endif
+#endif
+
/* LED definitions **********************************************************/
/* The NUCLEO-G431RB has four user LEDs.
@@ -329,6 +338,11 @@
#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3NOUT_1 /* PB1 */
#define GPIO_TIM1_CH4OUT GPIO_TIM1_CH4OUT_2 /* PC3 */
+/* CAN configuration ********************************************************/
+
+#define GPIO_FDCAN1_RX GPIO_FDCAN1_RX_2 /* PB8 */
+#define GPIO_FDCAN1_TX GPIO_FDCAN1_TX_2 /* PB9 */
+
/* DMA channels *************************************************************/
/* ADC */
diff --git a/boards/arm/stm32/nucleo-g431rb/src/Make.defs b/boards/arm/stm32/nucleo-g431rb/src/Make.defs
index bebb998..7d3c428 100644
--- a/boards/arm/stm32/nucleo-g431rb/src/Make.defs
+++ b/boards/arm/stm32/nucleo-g431rb/src/Make.defs
@@ -55,6 +55,10 @@ ifeq ($(CONFIG_MATH_CORDIC),y)
CSRCS += stm32_cordic.c
endif
+ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y)
+CSRCS += stm32_can.c
+endif
+
DEPPATH += --dep-path board
VPATH += :board
CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board)
diff --git a/boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h b/boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h
index 76e151f..26196b9 100644
--- a/boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h
+++ b/boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h
@@ -155,4 +155,16 @@ int stm32_foc_setup(void);
int stm32_cordic_setup(void);
#endif
+/****************************************************************************
+ * Name: stm32_can_setup
+ *
+ * Description:
+ * Initialize CAN and register the CAN device
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32_FDCAN_CHARDRIVER
+int stm32_can_setup(void);
+#endif
+
#endif /* __BOARDS_ARM_STM32_NUCLEO_G431RB_SRC_NUCLEO_G431RB_H */
diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c
index 72ca25a..f204587 100644
--- a/boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c
+++ b/boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c
@@ -149,6 +149,16 @@ int stm32_bringup(void)
}
#endif
+#ifdef CONFIG_STM32_FDCAN_CHARDRIVER
+ /* Initialize CAN and register the CAN driver. */
+
+ ret = stm32_can_setup();
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: stm32_fdcan_setup failed: %d\n", ret);
+ }
+#endif
+
UNUSED(ret);
return OK;
}
diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_can.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_can.c
new file mode 100644
index 0000000..0afb654
--- /dev/null
+++ b/boards/arm/stm32/nucleo-g431rb/src/stm32_can.c
@@ -0,0 +1,90 @@
+/****************************************************************************
+ * boards/arm/stm32/nucleo-g431rb/src/stm32_can.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/can/can.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "arm_arch.h"
+
+#include "stm32.h"
+#include "stm32_fdcan.h"
+#include "nucleo-g431rb.h"
+
+#ifdef CONFIG_CAN
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#if !defined(CONFIG_STM32_FDCAN1)
+# error "No CAN is enable. Please eneable at least one CAN device"
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_can_setup
+ *
+ * Description:
+ * Initialize CAN and register the CAN device
+ *
+ ****************************************************************************/
+
+int stm32_can_setup(void)
+{
+ struct can_dev_s *can;
+ int ret;
+
+ /* Call stm32_fdcaninitialize() to get an instance of the CAN interface */
+
+ can = stm32_fdcaninitialize(1);
+ if (can == NULL)
+ {
+ canerr("ERROR: Failed to get CAN interface\n");
+ return -ENODEV;
+ }
+
+ /* Register the CAN driver at "/dev/can0" */
+
+ ret = can_register("/dev/can0", can);
+ if (ret < 0)
+ {
+ canerr("ERROR: can_register failed: %d\n", ret);
+ return ret;
+ }
+
+ return OK;
+}
+
+#endif /* CONFIG_CAN */
[incubator-nuttx] 03/04: boards/b-g431b-esc1: add CAN example
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 499c7ce4f5509639824444174ca714529cf51592
Author: raiden00pl <ra...@railab.me>
AuthorDate: Sat Jan 15 13:51:58 2022 +0100
boards/b-g431b-esc1: add CAN example
---
boards/arm/stm32/b-g431b-esc1/Kconfig | 4 +
boards/arm/stm32/b-g431b-esc1/README.txt | 3 +
.../arm/stm32/b-g431b-esc1/configs/can/defconfig | 57 +++++++++++
boards/arm/stm32/b-g431b-esc1/include/board.h | 14 +++
boards/arm/stm32/b-g431b-esc1/src/Make.defs | 4 +
boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h | 17 ++++
boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c | 10 ++
boards/arm/stm32/b-g431b-esc1/src/stm32_can.c | 104 +++++++++++++++++++++
8 files changed, 213 insertions(+)
diff --git a/boards/arm/stm32/b-g431b-esc1/Kconfig b/boards/arm/stm32/b-g431b-esc1/Kconfig
index 203c3cf..cc5e7a4 100644
--- a/boards/arm/stm32/b-g431b-esc1/Kconfig
+++ b/boards/arm/stm32/b-g431b-esc1/Kconfig
@@ -29,4 +29,8 @@ config BOARD_STM32_BG431BESC1_FOC_POT
endif # STM32_FOC
+config BOARD_STM32_BG431BESC1_CANTERM
+ bool "B-G431B-ESC1 use on-board CAN terminator resistor"
+ default y
+
endif # ARCH_BOARD_B_G431B_ESC1
diff --git a/boards/arm/stm32/b-g431b-esc1/README.txt b/boards/arm/stm32/b-g431b-esc1/README.txt
index 6dc45e7..f6ecb02 100644
--- a/boards/arm/stm32/b-g431b-esc1/README.txt
+++ b/boards/arm/stm32/b-g431b-esc1/README.txt
@@ -48,6 +48,9 @@ Configuration Sub-directories
ENCO_Z/HALL_H3 TIM4_CH3 PB8
BUTTON GPIO_PC10 PC10
PWM PA15
+ CAN_RX PA11
+ CAN_TX PB9
+ CAN_TERM PC14
Current shunt resistance = 0.003
PGA gain = 16
diff --git a/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig
new file mode 100644
index 0000000..65af7ee
--- /dev/null
+++ b/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig
@@ -0,0 +1,57 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_FPU is not set
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_NSH_CMDPARMS is not set
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+# CONFIG_NSH_DISABLE_PS is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="b-g431b-esc1"
+CONFIG_ARCH_BOARD_B_G431B_ESC1=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CHIP="stm32"
+CONFIG_ARCH_CHIP_STM32=y
+CONFIG_ARCH_CHIP_STM32G431C=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=8499
+CONFIG_BOARD_STM32_BG431BESC1_USE_HSE=y
+CONFIG_BUILTIN=y
+CONFIG_CAN=y
+CONFIG_CAN_ERRORS=y
+CONFIG_CAN_EXTID=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_EXAMPLES_CAN=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=22528
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_START_DAY=14
+CONFIG_START_MONTH=10
+CONFIG_START_YEAR=2014
+CONFIG_STM32_FDCAN1=y
+CONFIG_STM32_FDCAN1_BITRATE=250000
+CONFIG_STM32_FDCAN1_NTSEG1=13
+CONFIG_STM32_FDCAN1_NTSEG2=2
+CONFIG_STM32_JTAG_SW_ENABLE=y
+CONFIG_STM32_USART2=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_USART2_SERIAL_CONSOLE=y
diff --git a/boards/arm/stm32/b-g431b-esc1/include/board.h b/boards/arm/stm32/b-g431b-esc1/include/board.h
index b35f38c..0026c9a 100644
--- a/boards/arm/stm32/b-g431b-esc1/include/board.h
+++ b/boards/arm/stm32/b-g431b-esc1/include/board.h
@@ -247,6 +247,15 @@
#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY)
#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY)
+#ifdef CONFIG_STM32_FDCAN
+# ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSE
+# define STM32_CCIPR_FDCANSRC (RCC_CCIPR_FDCANSEL_HSE)
+# define STM32_FDCAN_FREQUENCY (STM32_HSE_FREQUENCY)
+# else
+# error For now FDCAN supported only if HSE enabled
+# endif
+#endif
+
/* LED definitions **********************************************************/
/* The B-G431B-ESC1 has four user LEDs.
@@ -333,4 +342,9 @@
#define DMACHAN_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1 */
#define DMACHAN_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1 */
+/* CAN configuration ********************************************************/
+
+#define GPIO_FDCAN1_RX GPIO_FDCAN1_RX_1 /* PA11 */
+#define GPIO_FDCAN1_TX GPIO_FDCAN1_TX_2 /* PB9 */
+
#endif /* __BOARDS_ARM_STM32_B_G431B_ESC1_INCLUDE_BOARD_H */
diff --git a/boards/arm/stm32/b-g431b-esc1/src/Make.defs b/boards/arm/stm32/b-g431b-esc1/src/Make.defs
index 88fbd4d..618f986 100644
--- a/boards/arm/stm32/b-g431b-esc1/src/Make.defs
+++ b/boards/arm/stm32/b-g431b-esc1/src/Make.defs
@@ -41,6 +41,10 @@ ifeq ($(CONFIG_STM32_FOC),y)
CSRCS += stm32_foc.c
endif
+ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y)
+CSRCS += stm32_can.c
+endif
+
DEPPATH += --dep-path board
VPATH += :board
CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board)
diff --git a/boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h b/boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h
index afa2052..deef8ea 100644
--- a/boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h
+++ b/boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h
@@ -88,6 +88,11 @@
GPIO_PORTB | GPIO_PIN8)
#endif
+/* CAN_TERM - PC14 */
+
+#define GPIO_CANTERM (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \
+ GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN14)
+
/****************************************************************************
* Public Data
****************************************************************************/
@@ -140,4 +145,16 @@ int stm32_adc_setup(void);
int stm32_foc_setup(void);
#endif
+/****************************************************************************
+ * Name: stm32_can_setup
+ *
+ * Description:
+ * Initialize CAN and register the CAN device
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32_FDCAN_CHARDRIVER
+int stm32_can_setup(void);
+#endif
+
#endif /* __BOARDS_ARM_STM32_B_G431B_ESC1_SRC_B_G431B_ESC1_H */
diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c
index 044e535..57d2168 100644
--- a/boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c
+++ b/boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c
@@ -149,6 +149,16 @@ int stm32_bringup(void)
}
#endif
+#ifdef CONFIG_STM32_FDCAN_CHARDRIVER
+ /* Initialize CAN and register the CAN driver. */
+
+ ret = stm32_can_setup();
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: stm32_fdcan_setup failed: %d\n", ret);
+ }
+#endif
+
UNUSED(ret);
return OK;
}
diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_can.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_can.c
new file mode 100644
index 0000000..bf5e483
--- /dev/null
+++ b/boards/arm/stm32/b-g431b-esc1/src/stm32_can.c
@@ -0,0 +1,104 @@
+/****************************************************************************
+ * boards/arm/stm32/b-g431b-esc1/src/stm32_can.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/can/can.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "arm_arch.h"
+
+#include "stm32.h"
+#include "stm32_fdcan.h"
+#include "b-g431b-esc1.h"
+
+#ifdef CONFIG_CAN
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#if !defined(CONFIG_STM32_FDCAN1)
+# error "No CAN is enable. Please eneable at least one CAN device"
+#endif
+
+#ifdef CONFIG_BOARD_STM32_BG431BESC1_CANTERM
+# define BG431BESC1_CANTERM (true)
+#else
+# define BG431BESC1_CANTERM (false)
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_can_setup
+ *
+ * Description:
+ * Initialize CAN and register the CAN device
+ *
+ ****************************************************************************/
+
+int stm32_can_setup(void)
+{
+ struct can_dev_s *can;
+ int ret;
+
+ /* Call stm32_fdcaninitialize() to get an instance of the CAN interface */
+
+ can = stm32_fdcaninitialize(1);
+ if (can == NULL)
+ {
+ canerr("ERROR: Failed to get CAN interface\n");
+ return -ENODEV;
+ }
+
+ /* Register the CAN driver at "/dev/can0" */
+
+ ret = can_register("/dev/can0", can);
+ if (ret < 0)
+ {
+ canerr("ERROR: can_register failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Configure CAN_TERM pin for output */
+
+ stm32_configgpio(GPIO_CANTERM);
+
+ /* Set CAN_TERM pin high or low */
+
+ stm32_gpiowrite(GPIO_CANTERM, BG431BESC1_CANTERM);
+
+ return OK;
+}
+
+#endif /* CONFIG_CAN */
[incubator-nuttx] 02/04: boards/nucleo-g431rb: add option to select HSI or HSE ass PLL source
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit d3841eb753af3cc8d05a518f55b680fdc834d912
Author: raiden00pl <ra...@railab.me>
AuthorDate: Sat Jan 15 13:40:39 2022 +0100
boards/nucleo-g431rb: add option to select HSI or HSE ass PLL source
---
boards/arm/stm32/nucleo-g431rb/Kconfig | 12 ++++
boards/arm/stm32/nucleo-g431rb/include/board.h | 92 +++++++++++++++++++++++++-
2 files changed, 102 insertions(+), 2 deletions(-)
diff --git a/boards/arm/stm32/nucleo-g431rb/Kconfig b/boards/arm/stm32/nucleo-g431rb/Kconfig
index f61cd04..1239f49 100644
--- a/boards/arm/stm32/nucleo-g431rb/Kconfig
+++ b/boards/arm/stm32/nucleo-g431rb/Kconfig
@@ -5,6 +5,18 @@
if ARCH_BOARD_NUCLEO_G431RB
+choice
+ prompt "PLL Clock source"
+ default BOARD_NUCLEO_G431RB_HSI
+
+config BOARD_NUCLEO_G431RB_USE_HSI
+ bool "HSI"
+
+config BOARD_NUCLEO_G431RB_USE_HSE
+ bool "HSE"
+
+endchoice
+
if SENSORS_QENCODER
config NUCLEO_G431RB_QETIMER
diff --git a/boards/arm/stm32/nucleo-g431rb/include/board.h b/boards/arm/stm32/nucleo-g431rb/include/board.h
index 36af6e1..ecadfef 100644
--- a/boards/arm/stm32/nucleo-g431rb/include/board.h
+++ b/boards/arm/stm32/nucleo-g431rb/include/board.h
@@ -33,13 +33,15 @@
/* Clocking *****************************************************************/
-#undef STM32_BOARD_XTAL /* Not installed by default */
+#define STM32_BOARD_XTAL 24000000 /* 8MHz */
#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */
#define STM32_LSI_FREQUENCY 32000 /* 32kHz */
-#undef STM32_HSE_FREQUENCY /* Not installed by default */
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#undef STM32_LSE_FREQUENCY /* Not available on this board */
+#ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSI
+
/* Main PLL Configuration.
*
* PLL source is HSI = 16MHz
@@ -120,6 +122,92 @@
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
+#endif /* CONFIG_BOARD_NUCLEO_G431RB_USE_HSI */
+
+#ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSE
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE = 24MHz
+ * PLLN = 86, PLLM = 6, PLLP = 10, PLLQ = 2, PLLR = 2
+ *
+ * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM)
+ * f(PLL_P) = f(VCO Clock) / PLLP
+ * f(PLL_Q) = f(VCO Clock) / PLLQ
+ * f(PLL_R) = f(VCO Clock) / PLLR
+ *
+ * Where:
+ * 8 <= PLLN <= 127
+ * 1 <= PLLM <= 16
+ * PLLP = 2 through 31
+ * PLLQ = 2, 4, 6, or 8
+ * PLLR = 2, 4, 6, or 8
+ *
+ * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R).
+ * 64MHz <= f(VCO Clock) <= 344MHz.
+ *
+ * Given the above:
+ *
+ * f(VCO Clock) = HSE x PLLN / PLLM
+ * = 24MHz x 86 / 6
+ * = 340MHz
+ *
+ * PLLPCLK = f(VCO Clock) / PLLP
+ * = 340MHz / 10
+ * = 34MHz
+ * (May be used for ADC)
+ *
+ * PLLQCLK = f(VCO Clock) / PLLQ
+ * = 340MHz / 2
+ * = 170MHz
+ * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to
+ * 48MHz, may be used for USB, RNG.)
+ *
+ * PLLRCLK = f(VCO Clock) / PLLR
+ * = 340MHz / 2
+ * = 170MHz
+ * (May be used for SYSCLK and most peripherals.)
+ */
+
+#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSE
+#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \
+ RCC_PLLCFGR_PLLQEN | \
+ RCC_PLLCFGR_PLLREN)
+
+#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(86)
+#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(6)
+#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10)
+#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2
+#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2
+
+#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85)
+#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10)
+#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2)
+#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2)
+
+/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */
+
+#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
+#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
+#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY
+
+/* AHB clock (HCLK) is SYSCLK (170MHz) */
+
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
+#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
+
+/* APB1 clock (PCLK1) is HCLK (170MHz) */
+
+#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
+#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY
+
+/* APB2 clock (PCLK2) is HCLK (170MHz) */
+
+#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
+#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
+
+#endif /* CONFIG_BOARD_NUCLEO_G431RB_USE_HSE */
+
/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */
/* Timers driven from APB2 will be PCLK2 */
[incubator-nuttx] 01/04: boards/b-g431b-esc1: add option to select HSI or HSE as PLL source
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 72ce934f73859b31dc887646b7746d571d56cc19
Author: raiden00pl <ra...@railab.me>
AuthorDate: Sat Jan 15 13:39:05 2022 +0100
boards/b-g431b-esc1: add option to select HSI or HSE as PLL source
---
boards/arm/stm32/b-g431b-esc1/Kconfig | 12 ++++
boards/arm/stm32/b-g431b-esc1/include/board.h | 92 ++++++++++++++++++++++++++-
2 files changed, 102 insertions(+), 2 deletions(-)
diff --git a/boards/arm/stm32/b-g431b-esc1/Kconfig b/boards/arm/stm32/b-g431b-esc1/Kconfig
index 4e90243..203c3cf 100644
--- a/boards/arm/stm32/b-g431b-esc1/Kconfig
+++ b/boards/arm/stm32/b-g431b-esc1/Kconfig
@@ -5,6 +5,18 @@
if ARCH_BOARD_B_G431B_ESC1
+choice
+ prompt "PLL clock source"
+ default BOARD_STM32_BG431BESC1_HSI
+
+config BOARD_STM32_BG431BESC1_USE_HSI
+ bool "HSI"
+
+config BOARD_STM32_BG431BESC1_USE_HSE
+ bool "HSE"
+
+endchoice
+
if STM32_FOC
config BOARD_STM32_BG431BESC1_FOC_VBUS
diff --git a/boards/arm/stm32/b-g431b-esc1/include/board.h b/boards/arm/stm32/b-g431b-esc1/include/board.h
index 872c00c..b35f38c 100644
--- a/boards/arm/stm32/b-g431b-esc1/include/board.h
+++ b/boards/arm/stm32/b-g431b-esc1/include/board.h
@@ -33,13 +33,15 @@
/* Clocking *****************************************************************/
-#undef STM32_BOARD_XTAL /* Not installed by default */
+#define STM32_BOARD_XTAL 8000000 /* 8MHz */
#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */
#define STM32_LSI_FREQUENCY 32000 /* 32kHz */
-#undef STM32_HSE_FREQUENCY /* Not installed by default */
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL /* Y2 on board */
#undef STM32_LSE_FREQUENCY /* Not available on this board */
+#ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSI
+
/* Main PLL Configuration.
*
* PLL source is HSI = 16MHz
@@ -120,6 +122,92 @@
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
+#endif /* CONFIG_BOARD_STM32_BG431BESC1_USE_HSI */
+
+#ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSE
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE = 8MHz
+ * PLLN = 85, PLLM = 2, PLLP = 10, PLLQ = 2, PLLR = 2
+ *
+ * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM)
+ * f(PLL_P) = f(VCO Clock) / PLLP
+ * f(PLL_Q) = f(VCO Clock) / PLLQ
+ * f(PLL_R) = f(VCO Clock) / PLLR
+ *
+ * Where:
+ * 8 <= PLLN <= 127
+ * 1 <= PLLM <= 16
+ * PLLP = 2 through 31
+ * PLLQ = 2, 4, 6, or 8
+ * PLLR = 2, 4, 6, or 8
+ *
+ * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R).
+ * 64MHz <= f(VCO Clock) <= 344MHz.
+ *
+ * Given the above:
+ *
+ * f(VCO Clock) = HSI x PLLN / PLLM
+ * = 8MHz x 85 / 2
+ * = 340MHz
+ *
+ * PLLPCLK = f(VCO Clock) / PLLP
+ * = 340MHz / 10
+ * = 34MHz
+ * (May be used for ADC)
+ *
+ * PLLQCLK = f(VCO Clock) / PLLQ
+ * = 340MHz / 2
+ * = 170MHz
+ * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to
+ * 48MHz, may be used for USB, RNG.)
+ *
+ * PLLRCLK = f(VCO Clock) / PLLR
+ * = 340MHz / 2
+ * = 170MHz
+ * (May be used for SYSCLK and most peripherals.)
+ */
+
+#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSE
+#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \
+ RCC_PLLCFGR_PLLQEN | \
+ RCC_PLLCFGR_PLLREN)
+
+#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85)
+#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(2)
+#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10)
+#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2
+#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2
+
+#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85)
+#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10)
+#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2)
+#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2)
+
+/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */
+
+#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
+#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
+#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY
+
+/* AHB clock (HCLK) is SYSCLK (170MHz) */
+
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
+#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
+
+/* APB1 clock (PCLK1) is HCLK (170MHz) */
+
+#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
+#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY
+
+/* APB2 clock (PCLK2) is HCLK (170MHz) */
+
+#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
+#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
+
+#endif /* CONFIG_BOARD_STM32_BG431BESC1_USE_HSE */
+
/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */
/* Timers driven from APB2 will be PCLK2 */