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Posted to commits@nuttx.apache.org by ac...@apache.org on 2020/02/29 15:22:33 UTC
[incubator-nuttx] 10/13: Updated STM32H7 startup with check for
ACTVOSRDY per recommendation in reference manual.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch pr402
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit f7577e204ab02943043526c661b94494b475c087
Author: Joshua Lange <jl...@2g-eng.com>
AuthorDate: Fri Feb 21 14:06:05 2020 -0600
Updated STM32H7 startup with check for ACTVOSRDY per recommendation in reference manual.
---
arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h | 15 +++++++++++++--
arch/arm/src/stm32h7/stm32h7x3xx_rcc.c | 5 +++++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h
index 647dbf7..7cae78c 100644
--- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h
@@ -104,8 +104,19 @@
# define PWR_CR1_ALS_2V8 (3 << PWR_CR1_ALS_SHIFT) /* 11: */
/* Bits 19-31: Reserved */
-/* Power control/status register 1 (CRS1) */
-
+/* Power control/status register 1 (CSR1) */
+ /* Bits 0-3: Reserved */
+#define PWR_CSR1_PVDO (1 << 4) /* Bit 4: Programmable voltage detect output*/
+ /* Bits 5-12: Reserved */
+#define PWR_CSR1_ACTVOSRDY (1 << 13) /* Bit 13: VOS voltage level ready */
+#define PWR_CSR1_ACTVOS_SHIFT (14) /* Bits 14-15: Current VOS applied */
+# define PWR_CSR1_VOS_SCALE_3R (0 << PWR_CSR1_ACTVOS_SHIFT)
+# define PWR_CSR1_VOS_SCALE_3 (1 << PWR_CSR1_ACTVOS_SHIFT)
+# define PWR_CSR1_VOS_SCALE_2 (2 << PWR_CSR1_ACTVOS_SHIFT)
+# define PWR_CSR1_VOS_SCALE_1 (3 << PWR_CSR1_ACTVOS_SHIFT)
+# define PWR_CSR1_VOS_SCALE_0 (3 << PWR_CSR1_ACTVOS_SHIFT)
+#define PWR_CSR1_AVDO (1 << 16) /* Bit 16: Analog voltage detector output */
+ /* Bits 17-31: Reserved */
/* Power control register 2 (CR2) */
#define PWR_CR2_BREN (1 << 0) /* Bit 0: Backup regulator enable */
diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
index 54f3f8f..536b225 100644
--- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
+++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
@@ -804,6 +804,11 @@ static void stm32_stdclockconfig(void)
{
}
+ /* See Reference manual Section 5.4.1, System supply startup */
+ while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ACTVOSRDY) == 0)
+ {
+ }
+
/* Over-drive is needed if
* - Voltage output scale 1 mode is selected and SYSCLK frequency is
* over 400 Mhz.