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Posted to commits@tvm.apache.org by GitBox <gi...@apache.org> on 2021/10/11 17:46:16 UTC

[GitHub] [tvm] mehrdadh edited a comment on issue #9226: [Bug] Direct SIMD Conv2d Bug

mehrdadh edited a comment on issue #9226:
URL: https://github.com/apache/tvm/issues/9226#issuecomment-940226266


   @sergey-grovety thanks for working on it. I'm adding other instances that this happens.
   
   - from Visual Wake Word model:
   ```
   Check failed: (expr_equal(lhs, rhs)) is false: Failed to match the compute with TensorIntrin tensor_intrin's declaration 
   provided= reduce(combiner=comm_reducer(result=[(x + y)], lhs=[x], rhs=[y], identity_element=[0]), source=
   [(int32(a[(i*2), k])*int32(b[j, k]))], init=[], axis=[iter_var(k, range(min=0, ext=3))], where=(bool)1, value_index=0), intrin=  
   reduce(combiner=comm_reducer(result=[(x + y)], lhs=[x], rhs=[y], identity_element=[0]), source=[(int32(a[i, k])*int32(b[j, 
   k]))], init=[], axis=[iter_var(k, range(min=0, ext=3))], where=(bool)1, value_index=0), running this stage: stage(conv2d, 
   compute(conv2d, body=[reduce(combiner=comm_reducer(result=[(x + y)], lhs=[x], rhs=[y], identity_element=[0]), 
   source=[(int32(padded_data[nn, ((yy*2) + ry), ((xx*2) + rx), rc])*int32(placeholder[ry, rx, ff, rc]))], init=[], axis=[iter_var(ry, 
   range(min=0, ext=3)), iter_var(rx, range(min=0, ext=3)), iter_var(rc, range(min=0, ext=3))], where=(bool)1, 
   value_index=0)], axis=[iter_var(nn, range(min=0, ext=1)), iter_var(yy, range(min=0, ext=48)), iter_var(xx, range(min=0, 
   ext=48)), iter_var(ff, range(min=0, ext=8))], reduce_axis=[iter_var(ry, range(min=0, ext=3)), iter_var(rx, range(min=0, 
   ext=3)), iter_var(rc, range(min=0, ext=3))], tag=conv2d_nhwc, attrs={"workload": ["conv2d_direct_simd.arm_cpu", 
   ["TENSOR", [1, 96, 96, 3], "int16"], ["TENSOR", [3, 3, 8, 3], "int16"], [2, 2], [0, 0, 1, 1], [1, 1], "int32"]}))
   
   ```


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