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Posted to commits@nuttx.apache.org by ac...@apache.org on 2024/06/04 21:53:21 UTC
(nuttx) 01/02: esp32s2: add simple boot support
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 16f8966fa9fbed1a2b4785468f3de60d53f939bb
Author: Almir Okato <al...@espressif.com>
AuthorDate: Thu May 23 10:36:29 2024 +0200
esp32s2: add simple boot support
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.
This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s2 targets and removes the need
for running 'make bootloader' command for it.
Signed-off-by: Almir Okato <al...@espressif.com>
---
.../platforms/risc-v/esp32c3-legacy/index.rst | 2 +-
Documentation/platforms/risc-v/esp32c3/index.rst | 2 +-
Documentation/platforms/risc-v/esp32c6/index.rst | 2 +-
Documentation/platforms/risc-v/esp32h2/index.rst | 2 +-
Documentation/platforms/xtensa/esp32/index.rst | 2 +-
Documentation/platforms/xtensa/esp32s2/index.rst | 2 +-
Documentation/platforms/xtensa/esp32s3/index.rst | 2 +-
arch/xtensa/src/esp32s2/Bootloader.mk | 28 +-
arch/xtensa/src/esp32s2/Kconfig | 29 +-
arch/xtensa/src/esp32s2/Make.defs | 6 +-
arch/xtensa/src/esp32s2/esp32s2_clockconfig.c | 2 +-
arch/xtensa/src/esp32s2/esp32s2_rng.c | 2 +-
arch/xtensa/src/esp32s2/esp32s2_rt_timer.c | 2 +-
arch/xtensa/src/esp32s2/esp32s2_rtc.c | 4 +-
arch/xtensa/src/esp32s2/esp32s2_spiflash.c | 6 +-
arch/xtensa/src/esp32s2/esp32s2_spiflash_mtd.c | 2 +-
arch/xtensa/src/esp32s2/esp32s2_spiram.c | 6 +-
arch/xtensa/src/esp32s2/esp32s2_start.c | 191 +-
arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h | 12 +-
arch/xtensa/src/esp32s2/hal.mk | 51 +-
.../src/esp32s2/hardware/esp32s2_cache_memory.h | 110 +-
arch/xtensa/src/esp32s2/hardware/esp32s2_extmem.h | 2757 -----------------
arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h | 314 +-
arch/xtensa/src/esp32s2/hardware/esp32s2_spi.h | 3098 +-------------------
arch/xtensa/src/esp32s2/loader.c | 300 ++
.../xtensa/src/esp32s2/loader.h | 83 +-
.../xtensa/esp32s2/common/scripts/flat_memory.ld | 10 +
.../esp32s2/common/scripts/mcuboot_sections.ld | 37 +-
.../common/scripts/simple_boot_sections.ld | 288 +-
boards/xtensa/esp32s2/common/src/Make.defs | 9 +
.../xtensa/esp32s2/common/src/esp32s2_board_twai.c | 2 -
.../esp32s2/esp32s2-kaluga-1/scripts/Make.defs | 2 +
.../esp32s2/esp32s2-saola-1/scripts/Make.defs | 2 +
.../esp32s2/esp32s2-saola-1/src/esp32s2_ledc.c | 1 -
.../esp32s2/franzininho-wifi/scripts/Make.defs | 2 +
.../esp32s3/common/scripts/simple_boot_sections.ld | 2 +-
tools/esp32/Config.mk | 2 +-
tools/esp32c3/Config.mk | 2 +-
tools/esp32c6/Config.mk | 2 +-
tools/esp32s2/Config.mk | 28 +-
tools/esp32s3/Config.mk | 4 +-
tools/espressif/Config.mk | 2 +-
42 files changed, 663 insertions(+), 6749 deletions(-)
diff --git a/Documentation/platforms/risc-v/esp32c3-legacy/index.rst b/Documentation/platforms/risc-v/esp32c3-legacy/index.rst
index 4fdee90272..415b363d84 100644
--- a/Documentation/platforms/risc-v/esp32c3-legacy/index.rst
+++ b/Documentation/platforms/risc-v/esp32c3-legacy/index.rst
@@ -90,7 +90,7 @@ Building and flashing
First make sure that ``esptool.py`` is installed. This tool is used to convert
the ELF to a compatible ESP32 image and to flash the image into the board.
-It can be installed with: ``pip install esptool``.
+It can be installed with: ``pip install esptool==4.8.dev4``.
Configure the NuttX project: ``./tools/configure.sh esp32c3-devkit:nsh``
Run ``make`` to build the project. Note that the conversion mentioned above is
diff --git a/Documentation/platforms/risc-v/esp32c3/index.rst b/Documentation/platforms/risc-v/esp32c3/index.rst
index d1524b86f9..25ec59852c 100644
--- a/Documentation/platforms/risc-v/esp32c3/index.rst
+++ b/Documentation/platforms/risc-v/esp32c3/index.rst
@@ -94,7 +94,7 @@ Building and flashing
First, make sure that ``esptool.py`` is installed. This tool is used to convert
the ELF to a compatible ESP32-C3 image and to flash the image into the board.
-It can be installed with: ``pip install esptool``.
+It can be installed with: ``pip install esptool==4.8.dev4``.
Configure the NuttX project: ``./tools/configure.sh esp32c3-generic:nsh``
Run ``make`` to build the project. Note that the conversion mentioned above is
diff --git a/Documentation/platforms/risc-v/esp32c6/index.rst b/Documentation/platforms/risc-v/esp32c6/index.rst
index f09f1797df..1d61a6d8af 100644
--- a/Documentation/platforms/risc-v/esp32c6/index.rst
+++ b/Documentation/platforms/risc-v/esp32c6/index.rst
@@ -84,7 +84,7 @@ Building and flashing
First, make sure that ``esptool.py`` is installed. This tool is used to convert
the ELF to a compatible ESP32-C6 image and to flash the image into the board.
-It can be installed with: ``pip install esptool``.
+It can be installed with: ``pip install esptool==4.8.dev4``.
Configure the NuttX project: ``./tools/configure.sh esp32c6-devkitc:nsh``
Run ``make`` to build the project. Note that the conversion mentioned above is
diff --git a/Documentation/platforms/risc-v/esp32h2/index.rst b/Documentation/platforms/risc-v/esp32h2/index.rst
index 0e9102c796..9e26197625 100644
--- a/Documentation/platforms/risc-v/esp32h2/index.rst
+++ b/Documentation/platforms/risc-v/esp32h2/index.rst
@@ -84,7 +84,7 @@ Building and flashing
First, make sure that ``esptool.py`` is installed. This tool is used to convert
the ELF to a compatible ESP32-H2 image and to flash the image into the board.
-It can be installed with: ``pip install esptool``.
+It can be installed with: ``pip install esptool==4.8.dev4``.
Configure the NuttX project: ``./tools/configure.sh esp32h2-devkit:nsh``
Run ``make`` to build the project. Note that the conversion mentioned above is
diff --git a/Documentation/platforms/xtensa/esp32/index.rst b/Documentation/platforms/xtensa/esp32/index.rst
index dce0af96c7..24059e7d42 100644
--- a/Documentation/platforms/xtensa/esp32/index.rst
+++ b/Documentation/platforms/xtensa/esp32/index.rst
@@ -505,7 +505,7 @@ Prerequisites
First of all, we need to install ``imgtool`` (a MCUboot utility application to manipulate binary
images) and ``esptool`` (the ESP32 toolkit)::
- $ pip install imgtool esptool
+ $ pip install imgtool esptool==4.8.dev4
We also need to make sure that the python modules are added to ``PATH``::
diff --git a/Documentation/platforms/xtensa/esp32s2/index.rst b/Documentation/platforms/xtensa/esp32s2/index.rst
index 9ef5adad19..95b1dde7f0 100644
--- a/Documentation/platforms/xtensa/esp32s2/index.rst
+++ b/Documentation/platforms/xtensa/esp32s2/index.rst
@@ -359,7 +359,7 @@ Prerequisites
First of all, we need to install ``imgtool`` (a MCUboot utility application to manipulate binary
images) and ``esptool`` (the ESP32-S2 toolkit)::
- $ pip install imgtool esptool
+ $ pip install imgtool esptool==4.8.dev4
We also need to make sure that the python modules are added to ``PATH``::
diff --git a/Documentation/platforms/xtensa/esp32s3/index.rst b/Documentation/platforms/xtensa/esp32s3/index.rst
index 5501cb1f59..4d6e2df612 100644
--- a/Documentation/platforms/xtensa/esp32s3/index.rst
+++ b/Documentation/platforms/xtensa/esp32s3/index.rst
@@ -129,7 +129,7 @@ Building and Flashing
First, make sure that ``esptool.py`` is installed. This tool is used to convert the ELF to a
compatible ESP32-S3 image and to flash the image into the board.
-It can be installed with: ``pip install esptool``.
+It can be installed with: ``pip install esptool==4.8.dev4``.
It's a two-step process where the first converts the ELF file into an ESP32-S3 compatible binary
and the second flashes it to the board. These steps are included in the build system and it is
diff --git a/arch/xtensa/src/esp32s2/Bootloader.mk b/arch/xtensa/src/esp32s2/Bootloader.mk
index 3a75b42721..f92624924a 100644
--- a/arch/xtensa/src/esp32s2/Bootloader.mk
+++ b/arch/xtensa/src/esp32s2/Bootloader.mk
@@ -20,7 +20,7 @@
.PHONY: bootloader clean_bootloader
-ifeq ($(CONFIG_ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE),y)
+ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),)
TOOLSDIR = $(TOPDIR)/tools/espressif
CHIPDIR = $(TOPDIR)/arch/xtensa/src/chip
@@ -114,8 +114,13 @@ else ifeq ($(CONFIG_ESP32S2_APP_FORMAT_LEGACY),y)
$(call cfg_val,CONFIG_PARTITION_TABLE_OFFSET,$(CONFIG_ESP32S2_PARTITION_TABLE_OFFSET)) \
} >> $(BOOTLOADER_CONFIG)
endif
+endif
-ifeq ($(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT),y)
+ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+bootloader:
+ $(Q) echo "Using direct bootloader to boot NuttX."
+
+else ifeq ($(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT),y)
BOOTLOADER_BIN = $(TOPDIR)/mcuboot-esp32s2.bin
BOOTLOADER_SIGNED_BIN = $(TOPDIR)/mcuboot-esp32s2.signed.bin
@@ -181,22 +186,3 @@ clean_bootloader:
$(call DELFILE,$(TOPDIR)/partition-table-esp32s2.bin)
endif
-
-else ifeq ($(CONFIG_ESP32S2_BOOTLOADER_DOWNLOAD_PREBUILT),y)
-
-BOOTLOADER_VERSION = latest
-BOOTLOADER_URL = https://github.com/espressif/esp-nuttx-bootloader/releases/download/$(BOOTLOADER_VERSION)
-
-ifeq ($(CONFIG_ESP32S2_APP_FORMAT_LEGACY),y)
-
-bootloader:
- $(call DOWNLOAD,$(BOOTLOADER_URL),bootloader-esp32s2.bin,$(TOPDIR)/bootloader-esp32s2.bin)
- $(call DOWNLOAD,$(BOOTLOADER_URL),partition-table-esp32s2.bin,$(TOPDIR)/partition-table-esp32s2.bin)
-
-clean_bootloader:
- $(call DELFILE,$(TOPDIR)/bootloader-esp32s2.bin)
- $(call DELFILE,$(TOPDIR)/partition-table-esp32s2.bin)
-
-endif
-
-endif
diff --git a/arch/xtensa/src/esp32s2/Kconfig b/arch/xtensa/src/esp32s2/Kconfig
index 16e5a62e84..0bc2b9bfc0 100644
--- a/arch/xtensa/src/esp32s2/Kconfig
+++ b/arch/xtensa/src/esp32s2/Kconfig
@@ -1222,9 +1222,14 @@ config ESP32S2_HAVE_OTA_PARTITION
menu "Bootloader and Image Configuration"
-config ESP32S2_APP_FORMAT_LEGACY
+config ESPRESSIF_SIMPLE_BOOT
bool
- default y if !ESP32S2_APP_FORMAT_MCUBOOT
+ depends on !ESP32S2_APP_FORMAT_MCUBOOT
+ depends on !ESP32S2_APP_FORMAT_LEGACY
+ default y
+
+config ESP32S2_APP_FORMAT_LEGACY
+ bool "Enable Legacy boot format"
depends on !ESP32S2_APP_FORMAT_MCUBOOT
---help---
This is the legacy application image format, as supported by the ESP-IDF
@@ -1233,28 +1238,11 @@ config ESP32S2_APP_FORMAT_LEGACY
config ESP32S2_APP_FORMAT_MCUBOOT
bool "Enable MCUboot-bootable format"
depends on !MCUBOOT_BOOTLOADER
+ default n
select ESP32S2_HAVE_OTA_PARTITION
- select ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE
---help---
Enables the Espressif port of MCUboot to be used as 2nd stage bootloader.
-config ESP32S2_BOOTLOADER_DOWNLOAD_PREBUILT
- bool
- default y if !ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE
- depends on !ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE
- ---help---
- The build system will download the prebuilt binaries from
- https://github.com/espressif/esp-nuttx-bootloader according to the chosen
- Application Image Format (ESP32S2_APP_FORMAT_LEGACY or ESP32S2_APP_FORMAT_MCUBOOT)
-
-config ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE
- bool "Build binaries from source"
- ---help---
- The build system will build all the required binaries from source. It will clone
- the https://github.com/espressif/esp-nuttx-bootloader repository and build a
- custom bootloader according to the chosen Application Image Format
- (ESP32S2_APP_FORMAT_LEGACY or ESP32S2_APP_FORMAT_MCUBOOT) and partition information.
-
choice
prompt "Target slot for image flashing"
default ESP32S2_ESPTOOL_TARGET_PRIMARY
@@ -1299,7 +1287,6 @@ config ESP32S2_CUSTOM_PARTITION_TABLE_OFFSET
bool "Customize partition table offset"
default n
depends on ESP32S2_APP_FORMAT_LEGACY
- select ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE
---help---
Enable to select the offset of the partition table in the flash.
diff --git a/arch/xtensa/src/esp32s2/Make.defs b/arch/xtensa/src/esp32s2/Make.defs
index fca3569fe7..0f2775c67b 100644
--- a/arch/xtensa/src/esp32s2/Make.defs
+++ b/arch/xtensa/src/esp32s2/Make.defs
@@ -143,6 +143,10 @@ ifeq ($(CONFIG_RTC_DRIVER),y)
CHIP_CSRCS += esp32s2_rtc_lowerhalf.c
endif
+ifeq ($(ESP32S2_APP_FORMAT_LEGACY), )
+CHIP_CSRCS += loader.c
+endif
+
#############################################################################
# Espressif HAL for 3rd Party Platforms
#############################################################################
@@ -151,7 +155,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
- ESP_HAL_3RDPARTY_VERSION = 22804823777dbbb7f43925b7729b3a32331aa7cd
+ ESP_HAL_3RDPARTY_VERSION = 7247aeb8749d8c6e29f951fa499100f593042408
endif
ifndef ESP_HAL_3RDPARTY_URL
diff --git a/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c
index 610a789c27..1fca78e0ac 100644
--- a/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c
+++ b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c
@@ -28,7 +28,7 @@
#include <sys/param.h>
#include "xtensa.h"
-#include "xtensa_attr.h"
+#include "esp_attr.h"
#include "hardware/esp32s2_soc.h"
#include "hardware/esp32s2_uart.h"
#include "hardware/esp32s2_rtccntl.h"
diff --git a/arch/xtensa/src/esp32s2/esp32s2_rng.c b/arch/xtensa/src/esp32s2/esp32s2_rng.c
index 8d5086314e..5d7d662688 100644
--- a/arch/xtensa/src/esp32s2/esp32s2_rng.c
+++ b/arch/xtensa/src/esp32s2/esp32s2_rng.c
@@ -41,7 +41,7 @@
#include <arch/xtensa/core_macros.h>
#include "xtensa.h"
-#include "xtensa_attr.h"
+#include "esp_attr.h"
#include "hardware/wdev_reg.h"
#include "esp32s2_clockconfig.h"
diff --git a/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c b/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c
index 7b0e387da6..ce26aec5e7 100644
--- a/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c
+++ b/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c
@@ -40,7 +40,7 @@
#include <nuttx/semaphore.h>
#include "xtensa.h"
-#include "xtensa_attr.h"
+#include "esp_attr.h"
#include "hardware/esp32s2_soc.h"
#include "hardware/esp32s2_system.h"
diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc.c b/arch/xtensa/src/esp32s2/esp32s2_rtc.c
index b8e777c3ff..3e59c397c4 100644
--- a/arch/xtensa/src/esp32s2/esp32s2_rtc.c
+++ b/arch/xtensa/src/esp32s2/esp32s2_rtc.c
@@ -45,13 +45,13 @@
#include "hardware/esp32s2_tim.h"
#include "hardware/regi2c_ctrl.h"
#include "hardware/esp32s2_spi_mem_reg.h"
-#include "hardware/esp32s2_extmem.h"
#include "hardware/esp32s2_syscon.h"
#include "hardware/regi2c_bbpll.h"
#include "hardware/regi2c_lp_bias.h"
#include "xtensa.h"
-#include "xtensa_attr.h"
+#include "esp_attr.h"
+#include "soc/extmem_reg.h"
#include "esp32s2_rtc.h"
diff --git a/arch/xtensa/src/esp32s2/esp32s2_spiflash.c b/arch/xtensa/src/esp32s2/esp32s2_spiflash.c
index 6c1e8e879f..76daeece2a 100644
--- a/arch/xtensa/src/esp32s2/esp32s2_spiflash.c
+++ b/arch/xtensa/src/esp32s2/esp32s2_spiflash.c
@@ -41,7 +41,7 @@
#include <nuttx/mtd/mtd.h>
#include "xtensa.h"
-#include "xtensa_attr.h"
+#include "esp_attr.h"
#include "hardware/esp32s2_spi_mem_reg.h"
#include "rom/esp32s2_spiflash.h"
#include "rom/esp32s2_opi_flash.h"
@@ -156,7 +156,7 @@
buffer, size, \
NULL, 0, \
0, \
- true)
+ true)
# define READ_DATA_FROM_FLASH(addr, buffer, size) \
esp32s2_spi_trans(READ_CMD(addr), 8, \
@@ -164,7 +164,7 @@
NULL, 0, \
buffer, size, \
READ_DUMMY(addr), \
- false)
+ false)
/****************************************************************************
* Private Types
diff --git a/arch/xtensa/src/esp32s2/esp32s2_spiflash_mtd.c b/arch/xtensa/src/esp32s2/esp32s2_spiflash_mtd.c
index 2d1067c0b4..54ead194a4 100644
--- a/arch/xtensa/src/esp32s2/esp32s2_spiflash_mtd.c
+++ b/arch/xtensa/src/esp32s2/esp32s2_spiflash_mtd.c
@@ -40,7 +40,7 @@
#include "hardware/esp32s2_soc.h"
-#include "xtensa_attr.h"
+#include "esp_attr.h"
#include "esp32s2_spiflash.h"
#include "rom/esp32s2_spiflash.h"
diff --git a/arch/xtensa/src/esp32s2/esp32s2_spiram.c b/arch/xtensa/src/esp32s2/esp32s2_spiram.c
index d356529f5a..b02b7c48bd 100644
--- a/arch/xtensa/src/esp32s2/esp32s2_spiram.c
+++ b/arch/xtensa/src/esp32s2/esp32s2_spiram.c
@@ -35,14 +35,16 @@
#include <nuttx/spinlock.h>
#include "xtensa.h"
-#include "xtensa_attr.h"
+#include "esp_attr.h"
#include "esp32s2_psram.h"
#include "esp32s2_spiram.h"
#include "hardware/esp32s2_soc.h"
#include "hardware/esp32s2_cache_memory.h"
-#include "hardware/esp32s2_extmem.h"
#include "hardware/esp32s2_iomux.h"
+#include "soc/extmem_reg.h"
+#include "soc/ext_mem_defs.h"
+
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
diff --git a/arch/xtensa/src/esp32s2/esp32s2_start.c b/arch/xtensa/src/esp32s2/esp32s2_start.c
index 9d991bbaef..e26265568f 100644
--- a/arch/xtensa/src/esp32s2/esp32s2_start.c
+++ b/arch/xtensa/src/esp32s2/esp32s2_start.c
@@ -31,10 +31,9 @@
#include <nuttx/irq.h>
#include "xtensa.h"
-#include "xtensa_attr.h"
+#include "esp_attr.h"
#include "hardware/esp32s2_cache_memory.h"
-#include "hardware/esp32s2_extmem.h"
#include "rom/esp32s2_libc_stubs.h"
#include "esp32s2_clockconfig.h"
#include "esp32s2_region.h"
@@ -43,6 +42,25 @@
#include "esp32s2_lowputc.h"
#include "esp32s2_wdt.h"
#include "esp32s2_rtc.h"
+#include "loader.h"
+
+#include "soc/extmem_reg.h"
+#include "hal/mmu_hal.h"
+#include "hal/mmu_types.h"
+#include "hal/cache_types.h"
+#include "hal/cache_ll.h"
+#include "hal/cache_hal.h"
+#include "rom/spi_flash.h"
+
+# include "bootloader_flash_priv.h"
+# include "esp_rom_efuse.h"
+#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
+# include "bootloader_init.h"
+# include "bootloader_random.h"
+# include "esp_rom_uart.h"
+# include "esp_rom_sys.h"
+# include "esp_app_format.h"
+#endif
/****************************************************************************
* Pre-processor Definitions
@@ -54,28 +72,26 @@
# define showprogress(c)
#endif
-#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
-
-#define PRIMARY_SLOT_OFFSET CONFIG_ESP32S2_OTA_PRIMARY_SLOT_OFFSET
+#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
+ defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
+# ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
+# define PRIMARY_SLOT_OFFSET CONFIG_ESP32S2_OTA_PRIMARY_SLOT_OFFSET
+# else
+ /* Force offset to the beginning of the whole image */
-#define HDR_ATTR __attribute__((section(".entry_addr"))) \
+# define PRIMARY_SLOT_OFFSET 0x0000
+# endif
+# define HDR_ATTR __attribute__((section(".entry_addr"))) \
__attribute__((used))
-/* Cache MMU block size */
-
-#define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */
-
-/* Cache MMU address mask (MMU tables ignore bits which are zero) */
-
-#define MMU_FLASH_MASK (~(MMU_BLOCK_SIZE - 1))
-
#endif
/****************************************************************************
* Private Types
****************************************************************************/
-#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
+#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
+ defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
extern uint8_t _image_irom_vma[];
extern uint8_t _image_irom_lma[];
extern uint8_t _image_irom_size[];
@@ -120,11 +136,9 @@ typedef enum
* ROM Function Prototypes
****************************************************************************/
-#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
+#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
+ defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
extern int ets_printf(const char *fmt, ...) printf_like(1, 2);
-extern int cache_ibus_mmu_set(uint32_t ext_ram, uint32_t vaddr,
- uint32_t paddr, uint32_t psize, uint32_t num,
- uint32_t fixed);
#endif
extern uint32_t cache_suspend_icache(void);
@@ -146,7 +160,8 @@ extern void cache_enable_dcache(uint32_t autoload);
* Private Function Prototypes
****************************************************************************/
-#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
+#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
+ defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
noreturn_function void __start(void);
#endif
@@ -154,7 +169,8 @@ noreturn_function void __start(void);
* Private Data
****************************************************************************/
-#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
+#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
+ defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
HDR_ATTR static void (*_entry_point)(void) = __start;
#endif
@@ -296,6 +312,7 @@ static void IRAM_ATTR configure_cpu_caches(void)
static void noreturn_function IRAM_ATTR __esp32s2_start(void)
{
+#ifndef CONFIG_ESPRESSIF_SIMPLE_BOOT
uint32_t sp;
/* Make sure that normal interrupts are disabled. This is really only an
@@ -315,9 +332,11 @@ static void noreturn_function IRAM_ATTR __esp32s2_start(void)
sp = (uint32_t)g_idlestack + IDLETHREAD_STACKSIZE;
__asm__ __volatile__("mov sp, %0\n" : : "r"(sp));
+#ifndef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
/* Make page 0 access raise an exception */
esp32s2_region_protection();
+#endif
/* Move CPU0 exception vectors to IRAM */
@@ -331,6 +350,7 @@ static void noreturn_function IRAM_ATTR __esp32s2_start(void)
{
*dest++ = 0;
}
+#endif
/* The 2nd stage bootloader enables RTC WDT to check on startup sequence
* related issues in application. Hence disable that as we are about to
@@ -395,127 +415,44 @@ static void noreturn_function IRAM_ATTR __esp32s2_start(void)
}
/****************************************************************************
- * Name: calc_mmu_pages
- *
- * Description:
- * Calculate the number of cache pages to map.
- *
- * Input Parameters:
- * size - Size of data to map
- * vaddr - Virtual address where data will be mapped
- *
- * Returned Value:
- * Number of cache MMU pages required to do the mapping.
- *
+ * Public Functions
****************************************************************************/
-#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
-static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr)
-{
- return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) /
- MMU_BLOCK_SIZE;
-}
-#endif
-
/****************************************************************************
- * Name: map_rom_segments
+ * Name: __start
*
* Description:
- * Configure the MMU and Cache peripherals for accessing ROM code and data.
- *
- * Input Parameters:
- * None.
- *
- * Returned Value:
- * None.
+ * We arrive here after the bootloader finished loading the program from
+ * flash. We do have a stack, so we can do the initialization in C.
*
****************************************************************************/
-#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
-static int map_rom_segments(void)
+noreturn_function void IRAM_ATTR __start(void)
{
- uint32_t rc = 0;
- uint32_t regval;
- uint32_t drom_lma_aligned;
- uint32_t drom_vma_aligned;
- uint32_t drom_page_count;
- uint32_t irom_lma_aligned;
- uint32_t irom_vma_aligned;
- uint32_t irom_page_count;
-
+#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
+ defined(CONFIG_ESPRESSIF_SIMPLE_BOOT)
size_t partition_offset = PRIMARY_SLOT_OFFSET;
- uint32_t app_irom_lma = partition_offset + (uint32_t)_image_irom_lma;
- uint32_t app_irom_size = (uint32_t)_image_irom_size;
- uint32_t app_irom_vma = (uint32_t)_image_irom_vma;
- uint32_t app_drom_lma = partition_offset + (uint32_t)_image_drom_lma;
- uint32_t app_drom_size = (uint32_t)_image_drom_size;
- uint32_t app_drom_vma = (uint32_t)_image_drom_vma;
-
- uint32_t autoload = cache_suspend_icache();
- cache_invalidate_icache_all();
-
- /* Clear the MMU entries that are already set up, so the new app only has
- * the mappings it creates.
- */
-
- for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++)
- {
- FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
- }
-
- drom_lma_aligned = app_drom_lma & MMU_FLASH_MASK;
- drom_vma_aligned = app_drom_vma & MMU_FLASH_MASK;
- drom_page_count = calc_mmu_pages(app_drom_size, app_drom_vma);
- rc = cache_ibus_mmu_set(MMU_ACCESS_FLASH, drom_vma_aligned,
- drom_lma_aligned, 64, (int)drom_page_count, 0);
+ uint32_t app_irom_start = partition_offset + (uint32_t)_image_irom_lma;
+ uint32_t app_irom_size = (uint32_t)_image_irom_size;
+ uint32_t app_irom_vaddr = (uint32_t)_image_irom_vma;
+ uint32_t app_drom_start = partition_offset + (uint32_t)_image_drom_lma;
+ uint32_t app_drom_size = (uint32_t)_image_drom_size;
+ uint32_t app_drom_vaddr = (uint32_t)_image_drom_vma;
+
+# ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
+ /* Move CPU0 exception vectors to IRAM */
- irom_lma_aligned = app_irom_lma & MMU_FLASH_MASK;
- irom_vma_aligned = app_irom_vma & MMU_FLASH_MASK;
- irom_page_count = calc_mmu_pages(app_irom_size, app_irom_vma);
+ __asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (_init_start));
- if (app_irom_lma + app_irom_size > IRAM1_ADDRESS_LOW)
+ if (bootloader_init() != 0)
{
- rc |= cache_ibus_mmu_set(MMU_ACCESS_FLASH, IRAM0_ADDRESS_LOW, 0, 64,
- 64, 1);
- rc |= cache_ibus_mmu_set(MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64,
- 64, 1);
-
- regval = getreg32(EXTMEM_PRO_ICACHE_CTRL1_REG);
- regval &= ~(EXTMEM_PRO_ICACHE_MASK_IRAM1);
- putreg32(regval, EXTMEM_PRO_ICACHE_CTRL1_REG);
+ ets_printf("Hardware init failed, aborting\n");
+ while (true);
}
+# endif
- rc |= cache_ibus_mmu_set(MMU_ACCESS_FLASH, irom_vma_aligned,
- irom_lma_aligned, 64, (int)irom_page_count, 0);
-
- regval = getreg32(EXTMEM_PRO_ICACHE_CTRL1_REG);
- regval &= ~(EXTMEM_PRO_ICACHE_MASK_IRAM0 |
- EXTMEM_PRO_ICACHE_MASK_DROM0);
- putreg32(regval, EXTMEM_PRO_ICACHE_CTRL1_REG);
-
- cache_resume_icache(autoload);
-
- return (int)rc;
-}
-#endif
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: __start
- *
- * Description:
- * We arrive here after the bootloader finished loading the program from
- * flash. We do have a stack, so we can do the initialization in C.
- *
- ****************************************************************************/
-
-void IRAM_ATTR __start(void)
-{
-#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
- if (map_rom_segments() != 0)
+ if (map_rom_segments(app_drom_start, app_drom_vaddr, app_drom_size,
+ app_irom_start, app_irom_vaddr, app_irom_size) != 0)
{
ets_printf("Failed to setup XIP, aborting\n");
while (true);
diff --git a/arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h b/arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h
index 2e48f6d349..a7177c5d3d 100644
--- a/arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h
+++ b/arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h
@@ -1244,9 +1244,9 @@ static inline void touch_lh_timeout_disable(void)
static inline void touch_lh_timeout_set_threshold(uint32_t threshold)
{
- return REG_SET_FIELD(RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG,
- RTC_CNTL_TOUCH_TIMEOUT_NUM,
- threshold);
+ REG_SET_FIELD(RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG,
+ RTC_CNTL_TOUCH_TIMEOUT_NUM,
+ threshold);
}
/****************************************************************************
@@ -2195,9 +2195,9 @@ static inline enum touch_pad_e touch_lh_sleep_get_channel_num(void)
static inline void touch_lh_sleep_set_threshold(uint32_t touch_thres)
{
- return REG_SET_FIELD(RTC_CNTL_TOUCH_SLP_THRES_REG,
- RTC_CNTL_TOUCH_SLP_TH,
- touch_thres);
+ REG_SET_FIELD(RTC_CNTL_TOUCH_SLP_THRES_REG,
+ RTC_CNTL_TOUCH_SLP_TH,
+ touch_thres);
}
/****************************************************************************
diff --git a/arch/xtensa/src/esp32s2/hal.mk b/arch/xtensa/src/esp32s2/hal.mk
index cd59abb11d..3279cbfd0c 100644
--- a/arch/xtensa/src/esp32s2/hal.mk
+++ b/arch/xtensa/src/esp32s2/hal.mk
@@ -21,10 +21,12 @@
# Include header paths
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)$(DELIM)include
-INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)include
-INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)private_include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)private_include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)private_include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private
@@ -49,6 +51,9 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include
@@ -69,6 +74,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c
@@ -78,6 +84,10 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)wdt_hal_iram.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mpu_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c
@@ -94,4 +104,41 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c
+ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)bootloader_banner_wrap.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console_loader.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_${CHIP_SERIES}.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_init.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common_loader.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash_config_${CHIP_SERIES}.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_efuse.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_mem.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random_${CHIP_SERIES}.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_sha.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_crc.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_esp32s2_esp32s3.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_fields.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_utility.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_api.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)efuse_controller$(DELIM)keys$(DELIM)with_key_purposes$(DELIM)esp_efuse_api_key.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_fields.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_table.c
+ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_utility.c
+
+ LDFLAGS += --wrap=bootloader_print_banner
+endif
+
CFLAGS += ${DEFINE_PREFIX}ESP_PLATFORM=1
diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_cache_memory.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_cache_memory.h
index 654107723b..35c4fc17f3 100644
--- a/arch/xtensa/src/esp32s2/hardware/esp32s2_cache_memory.h
+++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_cache_memory.h
@@ -30,100 +30,6 @@
* Pre-processor Definitions
****************************************************************************/
-/* IRAM0 is connected with Cache IBUS0 */
-
-#define IRAM0_ADDRESS_LOW 0x40000000
-#define IRAM0_ADDRESS_HIGH 0x40400000
-#define IRAM0_CACHE_ADDRESS_LOW 0x40080000
-#define IRAM0_CACHE_ADDRESS_HIGH 0x40400000
-
-/* IRAM1 is connected with Cache IBUS1 */
-
-#define IRAM1_ADDRESS_LOW 0x40400000
-#define IRAM1_ADDRESS_HIGH 0x40800000
-
-/* DROM0 is connected with Cache IBUS2 */
-
-#define DROM0_ADDRESS_LOW 0x3f000000
-#define DROM0_ADDRESS_HIGH 0x3f400000
-
-/* DRAM0 is connected with Cache DBUS0 */
-
-#define DRAM0_ADDRESS_LOW 0x3fc00000
-#define DRAM0_ADDRESS_HIGH 0x40000000
-#define DRAM0_CACHE_ADDRESS_LOW 0x3fc00000
-#define DRAM0_CACHE_ADDRESS_HIGH 0x3ff80000
-
-/* DRAM1 is connected with Cache DBUS1 */
-
-#define DRAM1_ADDRESS_LOW 0x3f800000
-#define DRAM1_ADDRESS_HIGH 0x3fc00000
-
-/* DPORT is connected with Cache DBUS2 */
-
-#define DPORT_ADDRESS_LOW 0x3f400000
-#define DPORT_ADDRESS_HIGH 0x3f800000
-#define DPORT_CACHE_ADDRESS_LOW 0x3f500000
-#define DPORT_CACHE_ADDRESS_HIGH 0x3f800000
-
-#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - \
- bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW \
- && (vaddr) < \
- bus_name##_ADDRESS_HIGH)
-
-#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
-#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
-#define ADDRESS_IN_IRAM1(vaddr) ADDRESS_IN_BUS(IRAM1, vaddr)
-#define ADDRESS_IN_DROM0(vaddr) ADDRESS_IN_BUS(DROM0, vaddr)
-#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
-#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
-#define ADDRESS_IN_DRAM1(vaddr) ADDRESS_IN_BUS(DRAM1, vaddr)
-#define ADDRESS_IN_DPORT(vaddr) ADDRESS_IN_BUS(DPORT, vaddr)
-#define ADDRESS_IN_DPORT_CACHE(vaddr) ADDRESS_IN_BUS(DPORT_CACHE, vaddr)
-
-#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
-#define BUS_IRAM1_CACHE_SIZE BUS_SIZE(IRAM1)
-#define BUS_IROM0_CACHE_SIZE BUS_SIZE(IROM0)
-#define BUS_DROM0_CACHE_SIZE BUS_SIZE(DROM0)
-#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
-#define BUS_DRAM1_CACHE_SIZE BUS_SIZE(DRAM1)
-#define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT)
-
-#define PRO_CACHE_IBUS0 0
-#define PRO_CACHE_IBUS0_MMU_START 0
-#define PRO_CACHE_IBUS0_MMU_END 0x100
-
-#define PRO_CACHE_IBUS1 1
-#define PRO_CACHE_IBUS1_MMU_START 0x100
-#define PRO_CACHE_IBUS1_MMU_END 0x200
-
-#define PRO_CACHE_IBUS2 2
-#define PRO_CACHE_IBUS2_MMU_START 0x200
-#define PRO_CACHE_IBUS2_MMU_END 0x300
-
-#define PRO_CACHE_DBUS0 3
-#define PRO_CACHE_DBUS0_MMU_START 0x300
-#define PRO_CACHE_DBUS0_MMU_END 0x400
-
-#define PRO_CACHE_DBUS1 4
-#define PRO_CACHE_DBUS1_MMU_START 0x400
-#define PRO_CACHE_DBUS1_MMU_END 0x500
-
-#define PRO_CACHE_DBUS2 5
-#define PRO_CACHE_DBUS2_MMU_START 0x500
-#define PRO_CACHE_DBUS2_MMU_END 0x600
-
-#define ICACHE_MMU_SIZE 0x300
-#define DCACHE_MMU_SIZE 0x300
-
-#define MMU_BUS_START(i) ((i) * 0x100)
-#define MMU_BUS_SIZE 0x100
-
-#define MMU_INVALID BIT(14)
-#define MMU_ACCESS_FLASH BIT(15)
-#define MMU_ACCESS_SPIRAM BIT(16)
-
#define FLASH_MMU_TABLE ((volatile uint32_t *)DR_REG_MMU_TABLE)
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE / sizeof(uint32_t))
@@ -131,23 +37,9 @@
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
#define MMU_ADDRESS_MASK 0x3fff
#define MMU_PAGE_SIZE 0x10000
+#define INVALID_PHY_PAGE 0xffff
#define BUS_ADDR_SIZE 0x400000
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
-#define BUS_NUM_MASK 0x3
-
-#define CACHE_MEMORY_BANK_SIZE 8192
-#define CACHE_MEMORY_BANK_NUM 4
-#define CACHE_MEMORY_BANK_NUM_MASK 0x3
-#define CACHE_MEMORY_LAYOUT_SHIFT 4
-#define CACHE_MEMORY_LAYOUT_SHIFT0 0
-#define CACHE_MEMORY_LAYOUT_SHIFT1 4
-#define CACHE_MEMORY_LAYOUT_SHIFT2 8
-#define CACHE_MEMORY_LAYOUT_SHIFT3 12
-#define CACHE_MEMORY_LAYOUT_MASK 0xf
-#define CACHE_MEMORY_BANK0_ADDR 0x3ffb0000
-#define CACHE_MEMORY_BANK1_ADDR 0x3ffb2000
-#define CACHE_MEMORY_BANK2_ADDR 0x3ffb4000
-#define CACHE_MEMORY_BANK3_ADDR 0x3ffb6000
#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_CACHE_MEMORY_H */
diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_extmem.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_extmem.h
deleted file mode 100644
index bc11d21cc0..0000000000
--- a/arch/xtensa/src/esp32s2/hardware/esp32s2_extmem.h
+++ /dev/null
@@ -1,2757 +0,0 @@
-/****************************************************************************
- * arch/xtensa/src/esp32s2/hardware/esp32s2_extmem.h
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_EXTMEM_H
-#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_EXTMEM_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "esp32s2_soc.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* EXTMEM_PRO_DCACHE_CTRL_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0)
-
-/* EXTMEM_PRO_DCACHE_LOCK_DONE : RO; bitpos: [25]; default: 0;
- * The bit is used to indicate lock operation is finished.
- */
-
-#define EXTMEM_PRO_DCACHE_LOCK_DONE (BIT(25))
-#define EXTMEM_PRO_DCACHE_LOCK_DONE_M (EXTMEM_PRO_DCACHE_LOCK_DONE_V << EXTMEM_PRO_DCACHE_LOCK_DONE_S)
-#define EXTMEM_PRO_DCACHE_LOCK_DONE_V 0x00000001
-#define EXTMEM_PRO_DCACHE_LOCK_DONE_S 25
-
-/* EXTMEM_PRO_DCACHE_LOCK_ENA : R/W; bitpos: [24]; default: 0;
- * The bit is used to enable lock operation. It will be cleared by hardware
- * after lock operation done.
- */
-
-#define EXTMEM_PRO_DCACHE_LOCK_ENA (BIT(24))
-#define EXTMEM_PRO_DCACHE_LOCK_ENA_M (EXTMEM_PRO_DCACHE_LOCK_ENA_V << EXTMEM_PRO_DCACHE_LOCK_ENA_S)
-#define EXTMEM_PRO_DCACHE_LOCK_ENA_V 0x00000001
-#define EXTMEM_PRO_DCACHE_LOCK_ENA_S 24
-
-/* EXTMEM_PRO_DCACHE_UNLOCK_DONE : RO; bitpos: [23]; default: 0;
- * The bit is used to indicate unlock operation is finished.
- */
-
-#define EXTMEM_PRO_DCACHE_UNLOCK_DONE (BIT(23))
-#define EXTMEM_PRO_DCACHE_UNLOCK_DONE_M (EXTMEM_PRO_DCACHE_UNLOCK_DONE_V << EXTMEM_PRO_DCACHE_UNLOCK_DONE_S)
-#define EXTMEM_PRO_DCACHE_UNLOCK_DONE_V 0x00000001
-#define EXTMEM_PRO_DCACHE_UNLOCK_DONE_S 23
-
-/* EXTMEM_PRO_DCACHE_UNLOCK_ENA : R/W; bitpos: [22]; default: 0;
- * The bit is used to enable unlock operation. It will be cleared by
- * hardware after unlock operation done.
- */
-
-#define EXTMEM_PRO_DCACHE_UNLOCK_ENA (BIT(22))
-#define EXTMEM_PRO_DCACHE_UNLOCK_ENA_M (EXTMEM_PRO_DCACHE_UNLOCK_ENA_V << EXTMEM_PRO_DCACHE_UNLOCK_ENA_S)
-#define EXTMEM_PRO_DCACHE_UNLOCK_ENA_V 0x00000001
-#define EXTMEM_PRO_DCACHE_UNLOCK_ENA_S 22
-
-/* EXTMEM_PRO_DCACHE_PRELOAD_DONE : RO; bitpos: [21]; default: 0;
- * The bit is used to indicate preload operation is finished.
- */
-
-#define EXTMEM_PRO_DCACHE_PRELOAD_DONE (BIT(21))
-#define EXTMEM_PRO_DCACHE_PRELOAD_DONE_M (EXTMEM_PRO_DCACHE_PRELOAD_DONE_V << EXTMEM_PRO_DCACHE_PRELOAD_DONE_S)
-#define EXTMEM_PRO_DCACHE_PRELOAD_DONE_V 0x00000001
-#define EXTMEM_PRO_DCACHE_PRELOAD_DONE_S 21
-
-/* EXTMEM_PRO_DCACHE_PRELOAD_ENA : R/W; bitpos: [20]; default: 0;
- * The bit is used to enable preload operation. It will be cleared by
- * hardware after preload operation done.
- */
-
-#define EXTMEM_PRO_DCACHE_PRELOAD_ENA (BIT(20))
-#define EXTMEM_PRO_DCACHE_PRELOAD_ENA_M (EXTMEM_PRO_DCACHE_PRELOAD_ENA_V << EXTMEM_PRO_DCACHE_PRELOAD_ENA_S)
-#define EXTMEM_PRO_DCACHE_PRELOAD_ENA_V 0x00000001
-#define EXTMEM_PRO_DCACHE_PRELOAD_ENA_S 20
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_DONE : RO; bitpos: [19]; default: 0;
- * The bit is used to indicate conditional-preload operation is finished.
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE (BIT(19))
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_M (EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_V << EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_S)
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_V 0x00000001
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_S 19
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_ENA : R/W; bitpos: [18]; default: 0;
- * The bit is used to enable and disable conditional-preload operation. It
- * is combined with pre_dcache_autoload_done. 1: enable, 0: disable.
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA (BIT(18))
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_M (EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_V << EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_S)
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_V 0x00000001
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_S 18
-
-/* EXTMEM_PRO_DCACHE_LOCK1_EN : R/W; bitpos: [15]; default: 0;
- * The bit is used to enable pre-lock operation which is combined with
- * PRO_DCACHE_LOCK1_ADDR_REG and PRO_DCACHE_LOCK1_SIZE_REG.
- */
-
-#define EXTMEM_PRO_DCACHE_LOCK1_EN (BIT(15))
-#define EXTMEM_PRO_DCACHE_LOCK1_EN_M (EXTMEM_PRO_DCACHE_LOCK1_EN_V << EXTMEM_PRO_DCACHE_LOCK1_EN_S)
-#define EXTMEM_PRO_DCACHE_LOCK1_EN_V 0x00000001
-#define EXTMEM_PRO_DCACHE_LOCK1_EN_S 15
-
-/* EXTMEM_PRO_DCACHE_LOCK0_EN : R/W; bitpos: [14]; default: 0;
- * The bit is used to enable pre-lock operation which is combined with
- * PRO_DCACHE_LOCK0_ADDR_REG and PRO_DCACHE_LOCK0_SIZE_REG.
- */
-
-#define EXTMEM_PRO_DCACHE_LOCK0_EN (BIT(14))
-#define EXTMEM_PRO_DCACHE_LOCK0_EN_M (EXTMEM_PRO_DCACHE_LOCK0_EN_V << EXTMEM_PRO_DCACHE_LOCK0_EN_S)
-#define EXTMEM_PRO_DCACHE_LOCK0_EN_V 0x00000001
-#define EXTMEM_PRO_DCACHE_LOCK0_EN_S 14
-
-/* EXTMEM_PRO_DCACHE_CLEAN_DONE : RO; bitpos: [13]; default: 0;
- * The bit is used to indicate clean operation is finished.
- */
-
-#define EXTMEM_PRO_DCACHE_CLEAN_DONE (BIT(13))
-#define EXTMEM_PRO_DCACHE_CLEAN_DONE_M (EXTMEM_PRO_DCACHE_CLEAN_DONE_V << EXTMEM_PRO_DCACHE_CLEAN_DONE_S)
-#define EXTMEM_PRO_DCACHE_CLEAN_DONE_V 0x00000001
-#define EXTMEM_PRO_DCACHE_CLEAN_DONE_S 13
-
-/* EXTMEM_PRO_DCACHE_CLEAN_ENA : R/W; bitpos: [12]; default: 0;
- * The bit is used to enable clean operation. It will be cleared by hardware
- * after clean operation done.
- */
-
-#define EXTMEM_PRO_DCACHE_CLEAN_ENA (BIT(12))
-#define EXTMEM_PRO_DCACHE_CLEAN_ENA_M (EXTMEM_PRO_DCACHE_CLEAN_ENA_V << EXTMEM_PRO_DCACHE_CLEAN_ENA_S)
-#define EXTMEM_PRO_DCACHE_CLEAN_ENA_V 0x00000001
-#define EXTMEM_PRO_DCACHE_CLEAN_ENA_S 12
-
-/* EXTMEM_PRO_DCACHE_FLUSH_DONE : RO; bitpos: [11]; default: 0;
- * The bit is used to indicate flush operation is finished.
- */
-
-#define EXTMEM_PRO_DCACHE_FLUSH_DONE (BIT(11))
-#define EXTMEM_PRO_DCACHE_FLUSH_DONE_M (EXTMEM_PRO_DCACHE_FLUSH_DONE_V << EXTMEM_PRO_DCACHE_FLUSH_DONE_S)
-#define EXTMEM_PRO_DCACHE_FLUSH_DONE_V 0x00000001
-#define EXTMEM_PRO_DCACHE_FLUSH_DONE_S 11
-
-/* EXTMEM_PRO_DCACHE_FLUSH_ENA : R/W; bitpos: [10]; default: 0;
- * The bit is used to enable flush operation. It will be cleared by hardware
- * after flush operation done.
- */
-
-#define EXTMEM_PRO_DCACHE_FLUSH_ENA (BIT(10))
-#define EXTMEM_PRO_DCACHE_FLUSH_ENA_M (EXTMEM_PRO_DCACHE_FLUSH_ENA_V << EXTMEM_PRO_DCACHE_FLUSH_ENA_S)
-#define EXTMEM_PRO_DCACHE_FLUSH_ENA_V 0x00000001
-#define EXTMEM_PRO_DCACHE_FLUSH_ENA_S 10
-
-/* EXTMEM_PRO_DCACHE_INVALIDATE_DONE : RO; bitpos: [9]; default: 0;
- * The bit is used to indicate invalidate operation is finished.
- */
-
-#define EXTMEM_PRO_DCACHE_INVALIDATE_DONE (BIT(9))
-#define EXTMEM_PRO_DCACHE_INVALIDATE_DONE_M (EXTMEM_PRO_DCACHE_INVALIDATE_DONE_V << EXTMEM_PRO_DCACHE_INVALIDATE_DONE_S)
-#define EXTMEM_PRO_DCACHE_INVALIDATE_DONE_V 0x00000001
-#define EXTMEM_PRO_DCACHE_INVALIDATE_DONE_S 9
-
-/* EXTMEM_PRO_DCACHE_INVALIDATE_ENA : R/W; bitpos: [8]; default: 1;
- * The bit is used to enable invalidate operation. It will be cleared by
- * hardware after invalidate operation done.
- */
-
-#define EXTMEM_PRO_DCACHE_INVALIDATE_ENA (BIT(8))
-#define EXTMEM_PRO_DCACHE_INVALIDATE_ENA_M (EXTMEM_PRO_DCACHE_INVALIDATE_ENA_V << EXTMEM_PRO_DCACHE_INVALIDATE_ENA_S)
-#define EXTMEM_PRO_DCACHE_INVALIDATE_ENA_V 0x00000001
-#define EXTMEM_PRO_DCACHE_INVALIDATE_ENA_S 8
-
-/* EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE : R/W; bitpos: [3]; default: 0;
- * The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes
- */
-
-#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE (BIT(3))
-#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_M (EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_V << EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_S)
-#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_V 0x00000001
-#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_S 3
-
-/* EXTMEM_PRO_DCACHE_SETSIZE_MODE : R/W; bitpos: [2]; default: 0;
- * The bit is used to configure cache memory size.0: 8KB, 1: 16KB
- */
-
-#define EXTMEM_PRO_DCACHE_SETSIZE_MODE (BIT(2))
-#define EXTMEM_PRO_DCACHE_SETSIZE_MODE_M (EXTMEM_PRO_DCACHE_SETSIZE_MODE_V << EXTMEM_PRO_DCACHE_SETSIZE_MODE_S)
-#define EXTMEM_PRO_DCACHE_SETSIZE_MODE_V 0x00000001
-#define EXTMEM_PRO_DCACHE_SETSIZE_MODE_S 2
-
-/* EXTMEM_PRO_DCACHE_ENABLE : R/W; bitpos: [0]; default: 0;
- * The bit is used to activate the data cache. 0: disable, 1: enable
- */
-
-#define EXTMEM_PRO_DCACHE_ENABLE (BIT(0))
-#define EXTMEM_PRO_DCACHE_ENABLE_M (EXTMEM_PRO_DCACHE_ENABLE_V << EXTMEM_PRO_DCACHE_ENABLE_S)
-#define EXTMEM_PRO_DCACHE_ENABLE_V 0x00000001
-#define EXTMEM_PRO_DCACHE_ENABLE_S 0
-
-/* EXTMEM_PRO_DCACHE_CTRL1_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x4)
-
-/* EXTMEM_PRO_DCACHE_MASK_BUS2 : R/W; bitpos: [2]; default: 1;
- * The bit is used to disable dbus2, 0: enable, 1: disable
- */
-
-#define EXTMEM_PRO_DCACHE_MASK_BUS2 (BIT(2))
-#define EXTMEM_PRO_DCACHE_MASK_BUS2_M (EXTMEM_PRO_DCACHE_MASK_BUS2_V << EXTMEM_PRO_DCACHE_MASK_BUS2_S)
-#define EXTMEM_PRO_DCACHE_MASK_BUS2_V 0x00000001
-#define EXTMEM_PRO_DCACHE_MASK_BUS2_S 2
-
-/* EXTMEM_PRO_DCACHE_MASK_BUS1 : R/W; bitpos: [1]; default: 1;
- * The bit is used to disable dbus1, 0: enable, 1: disable
- */
-
-#define EXTMEM_PRO_DCACHE_MASK_BUS1 (BIT(1))
-#define EXTMEM_PRO_DCACHE_MASK_BUS1_M (EXTMEM_PRO_DCACHE_MASK_BUS1_V << EXTMEM_PRO_DCACHE_MASK_BUS1_S)
-#define EXTMEM_PRO_DCACHE_MASK_BUS1_V 0x00000001
-#define EXTMEM_PRO_DCACHE_MASK_BUS1_S 1
-
-/* EXTMEM_PRO_DCACHE_MASK_BUS0 : R/W; bitpos: [0]; default: 1;
- * The bit is used to disable dbus0, 0: enable, 1: disable
- */
-
-#define EXTMEM_PRO_DCACHE_MASK_BUS0 (BIT(0))
-#define EXTMEM_PRO_DCACHE_MASK_BUS0_M (EXTMEM_PRO_DCACHE_MASK_BUS0_V << EXTMEM_PRO_DCACHE_MASK_BUS0_S)
-#define EXTMEM_PRO_DCACHE_MASK_BUS0_V 0x00000001
-#define EXTMEM_PRO_DCACHE_MASK_BUS0_S 0
-
-/* EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x8)
-
-/* EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
- * The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd,
- * 1: power up
- */
-
-#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU (BIT(2))
-#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_M (EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_V << EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_S)
-#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_V 0x00000001
-#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_S 2
-
-/* EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
- * The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd,
- * 1: power down
- */
-
-#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD (BIT(1))
-#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_M (EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_V << EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_S)
-#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_V 0x00000001
-#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_S 1
-
-/* EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1;
- * The bit is used to close clock gating of dcache tag memory. 1: close
- * gating, 0: open clock gating.
- */
-
-#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON (BIT(0))
-#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_M (EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_V << EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_S)
-#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_V 0x00000001
-#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_S 0
-
-/* EXTMEM_PRO_DCACHE_LOCK0_ADDR_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_LOCK0_ADDR_REG (DR_REG_EXTMEM_BASE + 0xc)
-
-/* EXTMEM_PRO_DCACHE_LOCK0_ADDR : R/W; bitpos: [31:0]; default: 0;
- * The bits are used to configure the first start virtual address of data
- * locking, which is combined with PRO_DCACHE_LOCK0_SIZE_REG
- */
-
-#define EXTMEM_PRO_DCACHE_LOCK0_ADDR 0xffffffff
-#define EXTMEM_PRO_DCACHE_LOCK0_ADDR_M (EXTMEM_PRO_DCACHE_LOCK0_ADDR_V << EXTMEM_PRO_DCACHE_LOCK0_ADDR_S)
-#define EXTMEM_PRO_DCACHE_LOCK0_ADDR_V 0xffffffff
-#define EXTMEM_PRO_DCACHE_LOCK0_ADDR_S 0
-
-/* EXTMEM_PRO_DCACHE_LOCK0_SIZE_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_LOCK0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x10)
-
-/* EXTMEM_PRO_DCACHE_LOCK0_SIZE : R/W; bitpos: [15:0]; default: 0;
- * The bits are used to configure the first length of data locking, which is
- * combined with PRO_DCACHE_LOCK0_ADDR_REG
- */
-
-#define EXTMEM_PRO_DCACHE_LOCK0_SIZE 0x0000ffff
-#define EXTMEM_PRO_DCACHE_LOCK0_SIZE_M (EXTMEM_PRO_DCACHE_LOCK0_SIZE_V << EXTMEM_PRO_DCACHE_LOCK0_SIZE_S)
-#define EXTMEM_PRO_DCACHE_LOCK0_SIZE_V 0x0000ffff
-#define EXTMEM_PRO_DCACHE_LOCK0_SIZE_S 0
-
-/* EXTMEM_PRO_DCACHE_LOCK1_ADDR_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_LOCK1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x14)
-
-/* EXTMEM_PRO_DCACHE_LOCK1_ADDR : R/W; bitpos: [31:0]; default: 0;
- * The bits are used to configure the second start virtual address of data
- * locking, which is combined with PRO_DCACHE_LOCK1_SIZE_REG
- */
-
-#define EXTMEM_PRO_DCACHE_LOCK1_ADDR 0xffffffff
-#define EXTMEM_PRO_DCACHE_LOCK1_ADDR_M (EXTMEM_PRO_DCACHE_LOCK1_ADDR_V << EXTMEM_PRO_DCACHE_LOCK1_ADDR_S)
-#define EXTMEM_PRO_DCACHE_LOCK1_ADDR_V 0xffffffff
-#define EXTMEM_PRO_DCACHE_LOCK1_ADDR_S 0
-
-/* EXTMEM_PRO_DCACHE_LOCK1_SIZE_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_LOCK1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x18)
-
-/* EXTMEM_PRO_DCACHE_LOCK1_SIZE : R/W; bitpos: [15:0]; default: 0;
- * The bits are used to configure the second length of data locking, which
- * is combined with PRO_DCACHE_LOCK1_ADDR_REG
- */
-
-#define EXTMEM_PRO_DCACHE_LOCK1_SIZE 0x0000ffff
-#define EXTMEM_PRO_DCACHE_LOCK1_SIZE_M (EXTMEM_PRO_DCACHE_LOCK1_SIZE_V << EXTMEM_PRO_DCACHE_LOCK1_SIZE_S)
-#define EXTMEM_PRO_DCACHE_LOCK1_SIZE_V 0x0000ffff
-#define EXTMEM_PRO_DCACHE_LOCK1_SIZE_S 0
-
-/* EXTMEM_PRO_DCACHE_MEM_SYNC0_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_MEM_SYNC0_REG (DR_REG_EXTMEM_BASE + 0x1c)
-
-/* EXTMEM_PRO_DCACHE_MEMSYNC_ADDR : R/W; bitpos: [31:0]; default: 0;
- * The bits are used to configure the start virtual address for invalidate,
- * flush, clean, lock and unlock operations. The manual operations will be
- * issued if the address is validate. The auto operations will be issued if
- * the address is invalidate. It should be combined with
- * PRO_DCACHE_MEM_SYNC1.
- */
-
-#define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR 0xffffffff
-#define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_M (EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_V << EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_S)
-#define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_V 0xffffffff
-#define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_S 0
-
-/* EXTMEM_PRO_DCACHE_MEM_SYNC1_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_MEM_SYNC1_REG (DR_REG_EXTMEM_BASE + 0x20)
-
-/* EXTMEM_PRO_DCACHE_MEMSYNC_SIZE : R/W; bitpos: [18:0]; default: 0;
- * The bits are used to configure the length for invalidate, flush, clean,
- * lock and unlock operations. The manual operations will be issued if it is
- * validate. The auto operations will be issued if it is invalidate. It
- * should be combined with PRO_DCACHE_MEM_SYNC0.
- */
-
-#define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE 0x0007ffff
-#define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_M (EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_V << EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_S)
-#define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_V 0x0007ffff
-#define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_S 0
-
-/* EXTMEM_PRO_DCACHE_PRELOAD_ADDR_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x24)
-
-/* EXTMEM_PRO_DCACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
- * The bits are used to configure the start virtual address for manual
- * pre-load operation. It should be combined with
- * PRO_DCACHE_PRELOAD_SIZE_REG.
- */
-
-#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR 0xffffffff
-#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_M (EXTMEM_PRO_DCACHE_PRELOAD_ADDR_V << EXTMEM_PRO_DCACHE_PRELOAD_ADDR_S)
-#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_V 0xffffffff
-#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_S 0
-
-/* EXTMEM_PRO_DCACHE_PRELOAD_SIZE_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x28)
-
-/* EXTMEM_PRO_DCACHE_PRELOAD_ORDER : R/W; bitpos: [10]; default: 0;
- * The bits are used to configure the direction of manual pre-load
- * operation. 1: descending, 0: ascending.
- */
-
-#define EXTMEM_PRO_DCACHE_PRELOAD_ORDER (BIT(10))
-#define EXTMEM_PRO_DCACHE_PRELOAD_ORDER_M (EXTMEM_PRO_DCACHE_PRELOAD_ORDER_V << EXTMEM_PRO_DCACHE_PRELOAD_ORDER_S)
-#define EXTMEM_PRO_DCACHE_PRELOAD_ORDER_V 0x00000001
-#define EXTMEM_PRO_DCACHE_PRELOAD_ORDER_S 10
-
-/* EXTMEM_PRO_DCACHE_PRELOAD_SIZE : R/W; bitpos: [9:0]; default: 512;
- * The bits are used to configure the length for manual pre-load operation.
- * It should be combined with PRO_DCACHE_PRELOAD_ADDR_REG..
- */
-
-#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE 0x000003ff
-#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_M (EXTMEM_PRO_DCACHE_PRELOAD_SIZE_V << EXTMEM_PRO_DCACHE_PRELOAD_SIZE_S)
-#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_V 0x000003ff
-#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_S 0
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_REG (DR_REG_EXTMEM_BASE + 0x2c)
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
- * The bits are used to enable the first section for conditional pre-load
- * operation.
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA (BIT(9))
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_M (EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_V << EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_S)
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_V 0x00000001
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_S 9
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
- * The bits are used to enable the second section for conditional pre-load
- * operation.
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA (BIT(8))
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_M (EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_V << EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_S)
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_V 0x00000001
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_S 8
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE : R/W; bitpos: [7:6]; default: 0;
- * The bits are used to configure the numbers of the cache block for the
- * issuing conditional pre-load operation.
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE 0x00000003
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_M (EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_V << EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_S)
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_V 0x00000003
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_S 6
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_RQST : R/W; bitpos: [5:4]; default: 0;
- * The bits are used to configure trigger conditions for conditional
- * pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST 0x00000003
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_M (EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_V << EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_S)
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_V 0x00000003
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_S 4
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER : R/W; bitpos: [3]; default: 0;
- * The bits are used to configure the direction of conditional pre-load
- * operation. 1: descending, 0: ascending.
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER (BIT(3))
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_M (EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_V << EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_S)
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_V 0x00000001
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_S 3
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_STEP : R/W; bitpos: [2:1]; default: 0;
- * Reserved.
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP 0x00000003
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_M (EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_V << EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_S)
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_V 0x00000003
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_S 1
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_MODE : R/W; bitpos: [0]; default: 0;
- * Reserved.
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE (BIT(0))
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_M (EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_V << EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_S)
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_V 0x00000001
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_S 0
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_ADDR_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x30)
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- * The bits are used to configure the start virtual address of the first
- * section for conditional pre-load operation. It should be combined with
- * pro_dcache_autoload_sct0_ena.
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR 0xffffffff
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_M (EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_V << EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_S)
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xffffffff
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_S 0
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_SIZE_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x34)
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [23:0]; default:
- * 32768;
- * The bits are used to configure the length of the first section for
- * conditional pre-load operation. It should be combined with
- * pro_dcache_autoload_sct0_ena.
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE 0x00ffffff
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_M (EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V << EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_S)
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V 0x00ffffff
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_S 0
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_ADDR_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x38)
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- * The bits are used to configure the start virtual address of the second
- * section for conditional pre-load operation. It should be combined with
- * pro_dcache_autoload_sct1_ena.
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR 0xffffffff
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_M (EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_V << EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_S)
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xffffffff
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_S 0
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_SIZE_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x3c)
-
-/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [23:0]; default:
- * 32768;
- * The bits are used to configure the length of the second section for
- * conditional pre-load operation. It should be combined with
- * pro_dcache_autoload_sct1_ena.
- */
-
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE 0x00ffffff
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_M (EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V << EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_S)
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V 0x00ffffff
-#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_S 0
-
-/* EXTMEM_PRO_ICACHE_CTRL_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x40)
-
-/* EXTMEM_PRO_ICACHE_LOCK_DONE : RO; bitpos: [25]; default: 0;
- * The bit is used to indicate lock operation is finished.
- */
-
-#define EXTMEM_PRO_ICACHE_LOCK_DONE (BIT(25))
-#define EXTMEM_PRO_ICACHE_LOCK_DONE_M (EXTMEM_PRO_ICACHE_LOCK_DONE_V << EXTMEM_PRO_ICACHE_LOCK_DONE_S)
-#define EXTMEM_PRO_ICACHE_LOCK_DONE_V 0x00000001
-#define EXTMEM_PRO_ICACHE_LOCK_DONE_S 25
-
-/* EXTMEM_PRO_ICACHE_LOCK_ENA : R/W; bitpos: [24]; default: 0;
- * The bit is used to enable lock operation. It will be cleared by hardware
- * after lock operation done.
- */
-
-#define EXTMEM_PRO_ICACHE_LOCK_ENA (BIT(24))
-#define EXTMEM_PRO_ICACHE_LOCK_ENA_M (EXTMEM_PRO_ICACHE_LOCK_ENA_V << EXTMEM_PRO_ICACHE_LOCK_ENA_S)
-#define EXTMEM_PRO_ICACHE_LOCK_ENA_V 0x00000001
-#define EXTMEM_PRO_ICACHE_LOCK_ENA_S 24
-
-/* EXTMEM_PRO_ICACHE_UNLOCK_DONE : RO; bitpos: [23]; default: 0;
- * The bit is used to indicate unlock operation is finished.
- */
-
-#define EXTMEM_PRO_ICACHE_UNLOCK_DONE (BIT(23))
-#define EXTMEM_PRO_ICACHE_UNLOCK_DONE_M (EXTMEM_PRO_ICACHE_UNLOCK_DONE_V << EXTMEM_PRO_ICACHE_UNLOCK_DONE_S)
-#define EXTMEM_PRO_ICACHE_UNLOCK_DONE_V 0x00000001
-#define EXTMEM_PRO_ICACHE_UNLOCK_DONE_S 23
-
-/* EXTMEM_PRO_ICACHE_UNLOCK_ENA : R/W; bitpos: [22]; default: 0;
- * The bit is used to enable unlock operation. It will be cleared by
- * hardware after unlock operation done.
- */
-
-#define EXTMEM_PRO_ICACHE_UNLOCK_ENA (BIT(22))
-#define EXTMEM_PRO_ICACHE_UNLOCK_ENA_M (EXTMEM_PRO_ICACHE_UNLOCK_ENA_V << EXTMEM_PRO_ICACHE_UNLOCK_ENA_S)
-#define EXTMEM_PRO_ICACHE_UNLOCK_ENA_V 0x00000001
-#define EXTMEM_PRO_ICACHE_UNLOCK_ENA_S 22
-
-/* EXTMEM_PRO_ICACHE_PRELOAD_DONE : RO; bitpos: [21]; default: 0;
- * The bit is used to indicate preload operation is finished.
- */
-
-#define EXTMEM_PRO_ICACHE_PRELOAD_DONE (BIT(21))
-#define EXTMEM_PRO_ICACHE_PRELOAD_DONE_M (EXTMEM_PRO_ICACHE_PRELOAD_DONE_V << EXTMEM_PRO_ICACHE_PRELOAD_DONE_S)
-#define EXTMEM_PRO_ICACHE_PRELOAD_DONE_V 0x00000001
-#define EXTMEM_PRO_ICACHE_PRELOAD_DONE_S 21
-
-/* EXTMEM_PRO_ICACHE_PRELOAD_ENA : R/W; bitpos: [20]; default: 0;
- * The bit is used to enable preload operation. It will be cleared by
- * hardware after preload operation done.
- */
-
-#define EXTMEM_PRO_ICACHE_PRELOAD_ENA (BIT(20))
-#define EXTMEM_PRO_ICACHE_PRELOAD_ENA_M (EXTMEM_PRO_ICACHE_PRELOAD_ENA_V << EXTMEM_PRO_ICACHE_PRELOAD_ENA_S)
-#define EXTMEM_PRO_ICACHE_PRELOAD_ENA_V 0x00000001
-#define EXTMEM_PRO_ICACHE_PRELOAD_ENA_S 20
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_DONE : RO; bitpos: [19]; default: 0;
- * The bit is used to indicate conditional-preload operation is finished.
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE (BIT(19))
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_M (EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_V << EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_S)
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_V 0x00000001
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_S 19
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_ENA : R/W; bitpos: [18]; default: 0;
- * The bit is used to enable and disable conditional-preload operation. It
- * is combined with pre_dcache_autoload_done. 1: enable, 0: disable.
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA (BIT(18))
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_M (EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_V << EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_S)
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_V 0x00000001
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_S 18
-
-/* EXTMEM_PRO_ICACHE_LOCK1_EN : R/W; bitpos: [15]; default: 0;
- * The bit is used to enable pre-lock operation which is combined with
- * PRO_ICACHE_LOCK1_ADDR_REG and PRO_ICACHE_LOCK1_SIZE_REG.
- */
-
-#define EXTMEM_PRO_ICACHE_LOCK1_EN (BIT(15))
-#define EXTMEM_PRO_ICACHE_LOCK1_EN_M (EXTMEM_PRO_ICACHE_LOCK1_EN_V << EXTMEM_PRO_ICACHE_LOCK1_EN_S)
-#define EXTMEM_PRO_ICACHE_LOCK1_EN_V 0x00000001
-#define EXTMEM_PRO_ICACHE_LOCK1_EN_S 15
-
-/* EXTMEM_PRO_ICACHE_LOCK0_EN : R/W; bitpos: [14]; default: 0;
- * The bit is used to enable pre-lock operation which is combined with
- * PRO_ICACHE_LOCK0_ADDR_REG and PRO_ICACHE_LOCK0_SIZE_REG.
- */
-
-#define EXTMEM_PRO_ICACHE_LOCK0_EN (BIT(14))
-#define EXTMEM_PRO_ICACHE_LOCK0_EN_M (EXTMEM_PRO_ICACHE_LOCK0_EN_V << EXTMEM_PRO_ICACHE_LOCK0_EN_S)
-#define EXTMEM_PRO_ICACHE_LOCK0_EN_V 0x00000001
-#define EXTMEM_PRO_ICACHE_LOCK0_EN_S 14
-
-/* EXTMEM_PRO_ICACHE_INVALIDATE_DONE : RO; bitpos: [9]; default: 0;
- * The bit is used to indicate invalidate operation is finished.
- */
-
-#define EXTMEM_PRO_ICACHE_INVALIDATE_DONE (BIT(9))
-#define EXTMEM_PRO_ICACHE_INVALIDATE_DONE_M (EXTMEM_PRO_ICACHE_INVALIDATE_DONE_V << EXTMEM_PRO_ICACHE_INVALIDATE_DONE_S)
-#define EXTMEM_PRO_ICACHE_INVALIDATE_DONE_V 0x00000001
-#define EXTMEM_PRO_ICACHE_INVALIDATE_DONE_S 9
-
-/* EXTMEM_PRO_ICACHE_INVALIDATE_ENA : R/W; bitpos: [8]; default: 1;
- * The bit is used to enable invalidate operation. It will be cleared by
- * hardware after invalidate operation done.
- */
-
-#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA (BIT(8))
-#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA_M (EXTMEM_PRO_ICACHE_INVALIDATE_ENA_V << EXTMEM_PRO_ICACHE_INVALIDATE_ENA_S)
-#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA_V 0x00000001
-#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA_S 8
-
-/* EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE : R/W; bitpos: [3]; default: 0;
- * The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes
- */
-
-#define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE (BIT(3))
-#define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_M (EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_V << EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_S)
-#define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_V 0x00000001
-#define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_S 3
-
-/* EXTMEM_PRO_ICACHE_SETSIZE_MODE : R/W; bitpos: [2]; default: 0;
- * The bit is used to configure cache memory size.0: 8KB, 1: 16KB
- */
-
-#define EXTMEM_PRO_ICACHE_SETSIZE_MODE (BIT(2))
-#define EXTMEM_PRO_ICACHE_SETSIZE_MODE_M (EXTMEM_PRO_ICACHE_SETSIZE_MODE_V << EXTMEM_PRO_ICACHE_SETSIZE_MODE_S)
-#define EXTMEM_PRO_ICACHE_SETSIZE_MODE_V 0x00000001
-#define EXTMEM_PRO_ICACHE_SETSIZE_MODE_S 2
-
-/* EXTMEM_PRO_ICACHE_ENABLE : R/W; bitpos: [0]; default: 0;
- * The bit is used to activate the data cache. 0: disable, 1: enable
- */
-
-#define EXTMEM_PRO_ICACHE_ENABLE (BIT(0))
-#define EXTMEM_PRO_ICACHE_ENABLE_M (EXTMEM_PRO_ICACHE_ENABLE_V << EXTMEM_PRO_ICACHE_ENABLE_S)
-#define EXTMEM_PRO_ICACHE_ENABLE_V 0x00000001
-#define EXTMEM_PRO_ICACHE_ENABLE_S 0
-
-/* EXTMEM_PRO_ICACHE_CTRL1_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x44)
-
-/* EXTMEM_PRO_ICACHE_MASK_BUS2 : R/W; bitpos: [2]; default: 1;
- * The bit is used to disable ibus2, 0: enable, 1: disable
- */
-
-#define EXTMEM_PRO_ICACHE_MASK_BUS2 (BIT(2))
-#define EXTMEM_PRO_ICACHE_MASK_BUS2_M (EXTMEM_PRO_ICACHE_MASK_BUS2_V << EXTMEM_PRO_ICACHE_MASK_BUS2_S)
-#define EXTMEM_PRO_ICACHE_MASK_BUS2_V 0x00000001
-#define EXTMEM_PRO_ICACHE_MASK_BUS2_S 2
-
-/* EXTMEM_PRO_ICACHE_MASK_BUS1 : R/W; bitpos: [1]; default: 1;
- * The bit is used to disable ibus1, 0: enable, 1: disable
- */
-
-#define EXTMEM_PRO_ICACHE_MASK_BUS1 (BIT(1))
-#define EXTMEM_PRO_ICACHE_MASK_BUS1_M (EXTMEM_PRO_ICACHE_MASK_BUS1_V << EXTMEM_PRO_ICACHE_MASK_BUS1_S)
-#define EXTMEM_PRO_ICACHE_MASK_BUS1_V 0x00000001
-#define EXTMEM_PRO_ICACHE_MASK_BUS1_S 1
-
-/* EXTMEM_PRO_ICACHE_MASK_BUS0 : R/W; bitpos: [0]; default: 1;
- * The bit is used to disable ibus0, 0: enable, 1: disable
- */
-
-#define EXTMEM_PRO_ICACHE_MASK_BUS0 (BIT(0))
-#define EXTMEM_PRO_ICACHE_MASK_BUS0_M (EXTMEM_PRO_ICACHE_MASK_BUS0_V << EXTMEM_PRO_ICACHE_MASK_BUS0_S)
-#define EXTMEM_PRO_ICACHE_MASK_BUS0_V 0x00000001
-#define EXTMEM_PRO_ICACHE_MASK_BUS0_S 0
-#define EXTMEM_PRO_ICACHE_MASK_IRAM0 EXTMEM_PRO_ICACHE_MASK_BUS0
-#define EXTMEM_PRO_ICACHE_MASK_IRAM1 EXTMEM_PRO_ICACHE_MASK_BUS1
-#define EXTMEM_PRO_ICACHE_MASK_DROM0 EXTMEM_PRO_ICACHE_MASK_BUS2
-
-/* EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x48)
-
-/* EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
- * The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1:
- * power up
- */
-
-#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU (BIT(2))
-#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_M (EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_V << EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_S)
-#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_V 0x00000001
-#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_S 2
-
-/* EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
- * The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1:
- * power down
- */
-
-#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD (BIT(1))
-#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_M (EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_V << EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_S)
-#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_V 0x00000001
-#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_S 1
-
-/* EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1;
- * The bit is used to close clock gating of icache tag memory. 1: close
- * gating, 0: open clock gating.
- */
-
-#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON (BIT(0))
-#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_M (EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_V << EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_S)
-#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_V 0x00000001
-#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_S 0
-
-/* EXTMEM_PRO_ICACHE_LOCK0_ADDR_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_LOCK0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x4c)
-
-/* EXTMEM_PRO_ICACHE_LOCK0_ADDR : R/W; bitpos: [31:0]; default: 0;
- * The bits are used to configure the first start virtual address of data
- * locking, which is combined with PRO_ICACHE_LOCK0_SIZE_REG
- */
-
-#define EXTMEM_PRO_ICACHE_LOCK0_ADDR 0xffffffff
-#define EXTMEM_PRO_ICACHE_LOCK0_ADDR_M (EXTMEM_PRO_ICACHE_LOCK0_ADDR_V << EXTMEM_PRO_ICACHE_LOCK0_ADDR_S)
-#define EXTMEM_PRO_ICACHE_LOCK0_ADDR_V 0xffffffff
-#define EXTMEM_PRO_ICACHE_LOCK0_ADDR_S 0
-
-/* EXTMEM_PRO_ICACHE_LOCK0_SIZE_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_LOCK0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x50)
-
-/* EXTMEM_PRO_ICACHE_LOCK0_SIZE : R/W; bitpos: [15:0]; default: 0;
- * The bits are used to configure the first length of data locking, which is
- * combined with PRO_ICACHE_LOCK0_ADDR_REG
- */
-
-#define EXTMEM_PRO_ICACHE_LOCK0_SIZE 0x0000ffff
-#define EXTMEM_PRO_ICACHE_LOCK0_SIZE_M (EXTMEM_PRO_ICACHE_LOCK0_SIZE_V << EXTMEM_PRO_ICACHE_LOCK0_SIZE_S)
-#define EXTMEM_PRO_ICACHE_LOCK0_SIZE_V 0x0000ffff
-#define EXTMEM_PRO_ICACHE_LOCK0_SIZE_S 0
-
-/* EXTMEM_PRO_ICACHE_LOCK1_ADDR_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_LOCK1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x54)
-
-/* EXTMEM_PRO_ICACHE_LOCK1_ADDR : R/W; bitpos: [31:0]; default: 0;
- * The bits are used to configure the second start virtual address of data
- * locking, which is combined with PRO_ICACHE_LOCK1_SIZE_REG
- */
-
-#define EXTMEM_PRO_ICACHE_LOCK1_ADDR 0xffffffff
-#define EXTMEM_PRO_ICACHE_LOCK1_ADDR_M (EXTMEM_PRO_ICACHE_LOCK1_ADDR_V << EXTMEM_PRO_ICACHE_LOCK1_ADDR_S)
-#define EXTMEM_PRO_ICACHE_LOCK1_ADDR_V 0xffffffff
-#define EXTMEM_PRO_ICACHE_LOCK1_ADDR_S 0
-
-/* EXTMEM_PRO_ICACHE_LOCK1_SIZE_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_LOCK1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x58)
-
-/* EXTMEM_PRO_ICACHE_LOCK1_SIZE : R/W; bitpos: [15:0]; default: 0;
- * The bits are used to configure the second length of data locking, which
- * is combined with PRO_ICACHE_LOCK1_ADDR_REG
- */
-
-#define EXTMEM_PRO_ICACHE_LOCK1_SIZE 0x0000ffff
-#define EXTMEM_PRO_ICACHE_LOCK1_SIZE_M (EXTMEM_PRO_ICACHE_LOCK1_SIZE_V << EXTMEM_PRO_ICACHE_LOCK1_SIZE_S)
-#define EXTMEM_PRO_ICACHE_LOCK1_SIZE_V 0x0000ffff
-#define EXTMEM_PRO_ICACHE_LOCK1_SIZE_S 0
-
-/* EXTMEM_PRO_ICACHE_MEM_SYNC0_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_MEM_SYNC0_REG (DR_REG_EXTMEM_BASE + 0x5c)
-
-/* EXTMEM_PRO_ICACHE_MEMSYNC_ADDR : R/W; bitpos: [31:0]; default: 0;
- * The bits are used to configure the start virtual address for invalidate,
- * flush, clean, lock and unlock operations. The manual operations will be
- * issued if the address is validate. The auto operations will be issued if
- * the address is invalidate. It should be combined with
- * PRO_ICACHE_MEM_SYNC1.
- */
-
-#define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR 0xffffffff
-#define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_M (EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_V << EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_S)
-#define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_V 0xffffffff
-#define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_S 0
-
-/* EXTMEM_PRO_ICACHE_MEM_SYNC1_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_MEM_SYNC1_REG (DR_REG_EXTMEM_BASE + 0x60)
-
-/* EXTMEM_PRO_ICACHE_MEMSYNC_SIZE : R/W; bitpos: [18:0]; default: 0;
- * The bits are used to configure the length for invalidate, flush, clean,
- * lock and unlock operations. The manual operations will be issued if it is
- * validate. The auto operations will be issued if it is invalidate. It
- * should be combined with PRO_ICACHE_MEM_SYNC0.
- */
-
-#define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE 0x0007ffff
-#define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_M (EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_V << EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_S)
-#define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_V 0x0007ffff
-#define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_S 0
-
-/* EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x64)
-
-/* EXTMEM_PRO_ICACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
- * The bits are used to configure the start virtual address for manual
- * pre-load operation. It should be combined with
- * PRO_ICACHE_PRELOAD_SIZE_REG.
- */
-
-#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR 0xffffffff
-#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_M (EXTMEM_PRO_ICACHE_PRELOAD_ADDR_V << EXTMEM_PRO_ICACHE_PRELOAD_ADDR_S)
-#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_V 0xffffffff
-#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_S 0
-
-/* EXTMEM_PRO_ICACHE_PRELOAD_SIZE_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x68)
-
-/* EXTMEM_PRO_ICACHE_PRELOAD_ORDER : R/W; bitpos: [10]; default: 0;
- * The bits are used to configure the direction of manual pre-load
- * operation. 1: descending, 0: ascending.
- */
-
-#define EXTMEM_PRO_ICACHE_PRELOAD_ORDER (BIT(10))
-#define EXTMEM_PRO_ICACHE_PRELOAD_ORDER_M (EXTMEM_PRO_ICACHE_PRELOAD_ORDER_V << EXTMEM_PRO_ICACHE_PRELOAD_ORDER_S)
-#define EXTMEM_PRO_ICACHE_PRELOAD_ORDER_V 0x00000001
-#define EXTMEM_PRO_ICACHE_PRELOAD_ORDER_S 10
-
-/* EXTMEM_PRO_ICACHE_PRELOAD_SIZE : R/W; bitpos: [9:0]; default: 512;
- * The bits are used to configure the length for manual pre-load operation.
- * It should be combined with PRO_ICACHE_PRELOAD_ADDR_REG..
- */
-
-#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE 0x000003ff
-#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_M (EXTMEM_PRO_ICACHE_PRELOAD_SIZE_V << EXTMEM_PRO_ICACHE_PRELOAD_SIZE_S)
-#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_V 0x000003ff
-#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_S 0
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_REG (DR_REG_EXTMEM_BASE + 0x6c)
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
- * The bits are used to enable the first section for conditional pre-load
- * operation.
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA (BIT(9))
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_M (EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_V << EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_S)
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_V 0x00000001
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_S 9
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
- * The bits are used to enable the second section for conditional pre-load
- * operation.
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA (BIT(8))
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_M (EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_V << EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_S)
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_V 0x00000001
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_S 8
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE : R/W; bitpos: [7:6]; default: 0;
- * The bits are used to configure the numbers of the cache block for the
- * issuing conditional pre-load operation.
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE 0x00000003
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_M (EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_V << EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_S)
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_V 0x00000003
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_S 6
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_RQST : R/W; bitpos: [5:4]; default: 0;
- * The bits are used to configure trigger conditions for conditional
- * pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST 0x00000003
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_M (EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_V << EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_S)
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_V 0x00000003
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_S 4
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER : R/W; bitpos: [3]; default: 0;
- * The bits are used to configure the direction of conditional pre-load
- * operation. 1: descending, 0: ascending.
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER (BIT(3))
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_M (EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_V << EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_S)
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_V 0x00000001
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_S 3
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_STEP : R/W; bitpos: [2:1]; default: 0;
- * Reserved.
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP 0x00000003
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_M (EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_V << EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_S)
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_V 0x00000003
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_S 1
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_MODE : R/W; bitpos: [0]; default: 0;
- * Reserved.
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE (BIT(0))
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_M (EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_V << EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_S)
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_V 0x00000001
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_S 0
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_ADDR_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x70)
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- * The bits are used to configure the start virtual address of the first
- * section for conditional pre-load operation. It should be combined with
- * pro_icache_autoload_sct0_ena.
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR 0xffffffff
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_M (EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_V << EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_S)
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xffffffff
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_S 0
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_SIZE_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x74)
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [23:0]; default:
- * 32768;
- * The bits are used to configure the length of the first section for
- * conditional pre-load operation. It should be combined with
- * pro_icache_autoload_sct0_ena.
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE 0x00ffffff
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_M (EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V << EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_S)
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V 0x00ffffff
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_S 0
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_ADDR_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x78)
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- * The bits are used to configure the start virtual address of the second
- * section for conditional pre-load operation. It should be combined with
- * pro_icache_autoload_sct1_ena.
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR 0xffffffff
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_M (EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_V << EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_S)
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_V 0xffffffff
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_S 0
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_SIZE_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x7c)
-
-/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [23:0]; default:
- * 32768;
- * The bits are used to configure the length of the second section for
- * conditional pre-load operation. It should be combined with
- * pro_icache_autoload_sct1_ena.
- */
-
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE 0x00ffffff
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_M (EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V << EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_S)
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V 0x00ffffff
-#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_S 0
-
-/* EXTMEM_IC_PRELOAD_CNT_REG register
- * register description
- */
-
-#define EXTMEM_IC_PRELOAD_CNT_REG (DR_REG_EXTMEM_BASE + 0x80)
-
-/* EXTMEM_IC_PRELOAD_CNT : RO; bitpos: [15:0]; default: 0;
- * The bits are used to count the number of issued pre-load which include
- * manual pre-load and conditional pre-load.
- */
-
-#define EXTMEM_IC_PRELOAD_CNT 0x0000ffff
-#define EXTMEM_IC_PRELOAD_CNT_M (EXTMEM_IC_PRELOAD_CNT_V << EXTMEM_IC_PRELOAD_CNT_S)
-#define EXTMEM_IC_PRELOAD_CNT_V 0x0000ffff
-#define EXTMEM_IC_PRELOAD_CNT_S 0
-
-/* EXTMEM_IC_PRELOAD_MISS_CNT_REG register
- * register description
- */
-
-#define EXTMEM_IC_PRELOAD_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x84)
-
-/* EXTMEM_IC_PRELOAD_MISS_CNT : RO; bitpos: [15:0]; default: 0;
- * The bits are used to count the number of missed pre-load which include
- * manual pre-load and conditional pre-load.
- */
-
-#define EXTMEM_IC_PRELOAD_MISS_CNT 0x0000ffff
-#define EXTMEM_IC_PRELOAD_MISS_CNT_M (EXTMEM_IC_PRELOAD_MISS_CNT_V << EXTMEM_IC_PRELOAD_MISS_CNT_S)
-#define EXTMEM_IC_PRELOAD_MISS_CNT_V 0x0000ffff
-#define EXTMEM_IC_PRELOAD_MISS_CNT_S 0
-
-/* EXTMEM_IBUS2_ABANDON_CNT_REG register
- * register description
- */
-
-#define EXTMEM_IBUS2_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x88)
-
-/* EXTMEM_IBUS2_ABANDON_CNT : RO; bitpos: [15:0]; default: 0;
- * The bits are used to count the number of the abandoned ibus2 access.
- */
-
-#define EXTMEM_IBUS2_ABANDON_CNT 0x0000ffff
-#define EXTMEM_IBUS2_ABANDON_CNT_M (EXTMEM_IBUS2_ABANDON_CNT_V << EXTMEM_IBUS2_ABANDON_CNT_S)
-#define EXTMEM_IBUS2_ABANDON_CNT_V 0x0000ffff
-#define EXTMEM_IBUS2_ABANDON_CNT_S 0
-
-/* EXTMEM_IBUS1_ABANDON_CNT_REG register
- * register description
- */
-
-#define EXTMEM_IBUS1_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x8c)
-
-/* EXTMEM_IBUS1_ABANDON_CNT : RO; bitpos: [15:0]; default: 0;
- * The bits are used to count the number of the abandoned ibus1 access.
- */
-
-#define EXTMEM_IBUS1_ABANDON_CNT 0x0000ffff
-#define EXTMEM_IBUS1_ABANDON_CNT_M (EXTMEM_IBUS1_ABANDON_CNT_V << EXTMEM_IBUS1_ABANDON_CNT_S)
-#define EXTMEM_IBUS1_ABANDON_CNT_V 0x0000ffff
-#define EXTMEM_IBUS1_ABANDON_CNT_S 0
-
-/* EXTMEM_IBUS0_ABANDON_CNT_REG register
- * register description
- */
-
-#define EXTMEM_IBUS0_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x90)
-
-/* EXTMEM_IBUS0_ABANDON_CNT : RO; bitpos: [15:0]; default: 0;
- * The bits are used to count the number of the abandoned ibus0 access.
- */
-
-#define EXTMEM_IBUS0_ABANDON_CNT 0x0000ffff
-#define EXTMEM_IBUS0_ABANDON_CNT_M (EXTMEM_IBUS0_ABANDON_CNT_V << EXTMEM_IBUS0_ABANDON_CNT_S)
-#define EXTMEM_IBUS0_ABANDON_CNT_V 0x0000ffff
-#define EXTMEM_IBUS0_ABANDON_CNT_S 0
-
-/* EXTMEM_IBUS2_ACS_MISS_CNT_REG register
- * register description
- */
-
-#define EXTMEM_IBUS2_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x94)
-
-/* EXTMEM_IBUS2_ACS_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- * The bits are used to count the number of the cache miss caused by ibus2
- * access.
- */
-
-#define EXTMEM_IBUS2_ACS_MISS_CNT 0xffffffff
-#define EXTMEM_IBUS2_ACS_MISS_CNT_M (EXTMEM_IBUS2_ACS_MISS_CNT_V << EXTMEM_IBUS2_ACS_MISS_CNT_S)
-#define EXTMEM_IBUS2_ACS_MISS_CNT_V 0xffffffff
-#define EXTMEM_IBUS2_ACS_MISS_CNT_S 0
-
-/* EXTMEM_IBUS1_ACS_MISS_CNT_REG register
- * register description
- */
-
-#define EXTMEM_IBUS1_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x98)
-
-/* EXTMEM_IBUS1_ACS_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- * The bits are used to count the number of the cache miss caused by ibus1
- * access.
- */
-
-#define EXTMEM_IBUS1_ACS_MISS_CNT 0xffffffff
-#define EXTMEM_IBUS1_ACS_MISS_CNT_M (EXTMEM_IBUS1_ACS_MISS_CNT_V << EXTMEM_IBUS1_ACS_MISS_CNT_S)
-#define EXTMEM_IBUS1_ACS_MISS_CNT_V 0xffffffff
-#define EXTMEM_IBUS1_ACS_MISS_CNT_S 0
-
-/* EXTMEM_IBUS0_ACS_MISS_CNT_REG register
- * register description
- */
-
-#define EXTMEM_IBUS0_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x9c)
-
-/* EXTMEM_IBUS0_ACS_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- * The bits are used to count the number of the cache miss caused by ibus0
- * access.
- */
-
-#define EXTMEM_IBUS0_ACS_MISS_CNT 0xffffffff
-#define EXTMEM_IBUS0_ACS_MISS_CNT_M (EXTMEM_IBUS0_ACS_MISS_CNT_V << EXTMEM_IBUS0_ACS_MISS_CNT_S)
-#define EXTMEM_IBUS0_ACS_MISS_CNT_V 0xffffffff
-#define EXTMEM_IBUS0_ACS_MISS_CNT_S 0
-
-/* EXTMEM_IBUS2_ACS_CNT_REG register
- * register description
- */
-
-#define EXTMEM_IBUS2_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xa0)
-
-/* EXTMEM_IBUS2_ACS_CNT : RO; bitpos: [31:0]; default: 0;
- * The bits are used to count the number of ibus2 access icache.
- */
-
-#define EXTMEM_IBUS2_ACS_CNT 0xffffffff
-#define EXTMEM_IBUS2_ACS_CNT_M (EXTMEM_IBUS2_ACS_CNT_V << EXTMEM_IBUS2_ACS_CNT_S)
-#define EXTMEM_IBUS2_ACS_CNT_V 0xffffffff
-#define EXTMEM_IBUS2_ACS_CNT_S 0
-
-/* EXTMEM_IBUS1_ACS_CNT_REG register
- * register description
- */
-
-#define EXTMEM_IBUS1_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xa4)
-
-/* EXTMEM_IBUS1_ACS_CNT : RO; bitpos: [31:0]; default: 0;
- * The bits are used to count the number of ibus1 access icache.
- */
-
-#define EXTMEM_IBUS1_ACS_CNT 0xffffffff
-#define EXTMEM_IBUS1_ACS_CNT_M (EXTMEM_IBUS1_ACS_CNT_V << EXTMEM_IBUS1_ACS_CNT_S)
-#define EXTMEM_IBUS1_ACS_CNT_V 0xffffffff
-#define EXTMEM_IBUS1_ACS_CNT_S 0
-
-/* EXTMEM_IBUS0_ACS_CNT_REG register
- * register description
- */
-
-#define EXTMEM_IBUS0_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xa8)
-
-/* EXTMEM_IBUS0_ACS_CNT : RO; bitpos: [31:0]; default: 0;
- * The bits are used to count the number of ibus0 access icache.
- */
-
-#define EXTMEM_IBUS0_ACS_CNT 0xffffffff
-#define EXTMEM_IBUS0_ACS_CNT_M (EXTMEM_IBUS0_ACS_CNT_V << EXTMEM_IBUS0_ACS_CNT_S)
-#define EXTMEM_IBUS0_ACS_CNT_V 0xffffffff
-#define EXTMEM_IBUS0_ACS_CNT_S 0
-
-/* EXTMEM_DC_PRELOAD_CNT_REG register
- * register description
- */
-
-#define EXTMEM_DC_PRELOAD_CNT_REG (DR_REG_EXTMEM_BASE + 0xac)
-
-/* EXTMEM_DC_PRELOAD_CNT : RO; bitpos: [15:0]; default: 0;
- * The bits are used to count the number of issued pre-load which include
- * manual pre-load and conditional pre-load.
- */
-
-#define EXTMEM_DC_PRELOAD_CNT 0x0000ffff
-#define EXTMEM_DC_PRELOAD_CNT_M (EXTMEM_DC_PRELOAD_CNT_V << EXTMEM_DC_PRELOAD_CNT_S)
-#define EXTMEM_DC_PRELOAD_CNT_V 0x0000ffff
-#define EXTMEM_DC_PRELOAD_CNT_S 0
-
-/* EXTMEM_DC_PRELOAD_EVICT_CNT_REG register
- * register description
- */
-
-#define EXTMEM_DC_PRELOAD_EVICT_CNT_REG (DR_REG_EXTMEM_BASE + 0xb0)
-
-/* EXTMEM_DC_PRELOAD_EVICT_CNT : RO; bitpos: [15:0]; default: 0;
- * The bits are used to count the number of cache evictions by pre-load
- * which include manual pre-load and conditional pre-load.
- */
-
-#define EXTMEM_DC_PRELOAD_EVICT_CNT 0x0000ffff
-#define EXTMEM_DC_PRELOAD_EVICT_CNT_M (EXTMEM_DC_PRELOAD_EVICT_CNT_V << EXTMEM_DC_PRELOAD_EVICT_CNT_S)
-#define EXTMEM_DC_PRELOAD_EVICT_CNT_V 0x0000ffff
-#define EXTMEM_DC_PRELOAD_EVICT_CNT_S 0
-
-/* EXTMEM_DC_PRELOAD_MISS_CNT_REG register
- * register description
- */
-
-#define EXTMEM_DC_PRELOAD_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xb4)
-
-/* EXTMEM_DC_PRELOAD_MISS_CNT : RO; bitpos: [15:0]; default: 0;
- * The bits are used to count the number of missed pre-load which include
- * manual pre-load and conditional pre-load.
- */
-
-#define EXTMEM_DC_PRELOAD_MISS_CNT 0x0000ffff
-#define EXTMEM_DC_PRELOAD_MISS_CNT_M (EXTMEM_DC_PRELOAD_MISS_CNT_V << EXTMEM_DC_PRELOAD_MISS_CNT_S)
-#define EXTMEM_DC_PRELOAD_MISS_CNT_V 0x0000ffff
-#define EXTMEM_DC_PRELOAD_MISS_CNT_S 0
-
-/* EXTMEM_DBUS2_ABANDON_CNT_REG register
- * register description
- */
-
-#define EXTMEM_DBUS2_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0xb8)
-
-/* EXTMEM_DBUS2_ABANDON_CNT : RO; bitpos: [15:0]; default: 0;
- * The bits are used to count the number of the abandoned dbus2 access.
- */
-
-#define EXTMEM_DBUS2_ABANDON_CNT 0x0000ffff
-#define EXTMEM_DBUS2_ABANDON_CNT_M (EXTMEM_DBUS2_ABANDON_CNT_V << EXTMEM_DBUS2_ABANDON_CNT_S)
-#define EXTMEM_DBUS2_ABANDON_CNT_V 0x0000ffff
-#define EXTMEM_DBUS2_ABANDON_CNT_S 0
-
-/* EXTMEM_DBUS1_ABANDON_CNT_REG register
- * register description
- */
-
-#define EXTMEM_DBUS1_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0xbc)
-
-/* EXTMEM_DBUS1_ABANDON_CNT : RO; bitpos: [15:0]; default: 0;
- * The bits are used to count the number of the abandoned dbus1 access.
- */
-
-#define EXTMEM_DBUS1_ABANDON_CNT 0x0000ffff
-#define EXTMEM_DBUS1_ABANDON_CNT_M (EXTMEM_DBUS1_ABANDON_CNT_V << EXTMEM_DBUS1_ABANDON_CNT_S)
-#define EXTMEM_DBUS1_ABANDON_CNT_V 0x0000ffff
-#define EXTMEM_DBUS1_ABANDON_CNT_S 0
-
-/* EXTMEM_DBUS0_ABANDON_CNT_REG register
- * register description
- */
-
-#define EXTMEM_DBUS0_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0xc0)
-
-/* EXTMEM_DBUS0_ABANDON_CNT : RO; bitpos: [15:0]; default: 0;
- * The bits are used to count the number of the abandoned dbus0 access.
- */
-
-#define EXTMEM_DBUS0_ABANDON_CNT 0x0000ffff
-#define EXTMEM_DBUS0_ABANDON_CNT_M (EXTMEM_DBUS0_ABANDON_CNT_V << EXTMEM_DBUS0_ABANDON_CNT_S)
-#define EXTMEM_DBUS0_ABANDON_CNT_V 0x0000ffff
-#define EXTMEM_DBUS0_ABANDON_CNT_S 0
-
-/* EXTMEM_DBUS2_ACS_WB_CNT_REG register
- * register description
- */
-
-#define EXTMEM_DBUS2_ACS_WB_CNT_REG (DR_REG_EXTMEM_BASE + 0xc4)
-
-/* EXTMEM_DBUS2_ACS_WB_CNT : RO; bitpos: [19:0]; default: 0;
- * The bits are used to count the number of cache evictions by dbus2 access
- * cache.
- */
-
-#define EXTMEM_DBUS2_ACS_WB_CNT 0x000fffff
-#define EXTMEM_DBUS2_ACS_WB_CNT_M (EXTMEM_DBUS2_ACS_WB_CNT_V << EXTMEM_DBUS2_ACS_WB_CNT_S)
-#define EXTMEM_DBUS2_ACS_WB_CNT_V 0x000fffff
-#define EXTMEM_DBUS2_ACS_WB_CNT_S 0
-
-/* EXTMEM_DBUS1_ACS_WB_CNT_REG register
- * register description
- */
-
-#define EXTMEM_DBUS1_ACS_WB_CNT_REG (DR_REG_EXTMEM_BASE + 0xc8)
-
-/* EXTMEM_DBUS1_ACS_WB_CNT : RO; bitpos: [19:0]; default: 0;
- * The bits are used to count the number of cache evictions by dbus1 access
- * cache.
- */
-
-#define EXTMEM_DBUS1_ACS_WB_CNT 0x000fffff
-#define EXTMEM_DBUS1_ACS_WB_CNT_M (EXTMEM_DBUS1_ACS_WB_CNT_V << EXTMEM_DBUS1_ACS_WB_CNT_S)
-#define EXTMEM_DBUS1_ACS_WB_CNT_V 0x000fffff
-#define EXTMEM_DBUS1_ACS_WB_CNT_S 0
-
-/* EXTMEM_DBUS0_ACS_WB_CNT_REG register
- * register description
- */
-
-#define EXTMEM_DBUS0_ACS_WB_CNT_REG (DR_REG_EXTMEM_BASE + 0xcc)
-
-/* EXTMEM_DBUS0_ACS_WB_CNT : RO; bitpos: [19:0]; default: 0;
- * The bits are used to count the number of cache evictions by dbus0 access
- * cache.
- */
-
-#define EXTMEM_DBUS0_ACS_WB_CNT 0x000fffff
-#define EXTMEM_DBUS0_ACS_WB_CNT_M (EXTMEM_DBUS0_ACS_WB_CNT_V << EXTMEM_DBUS0_ACS_WB_CNT_S)
-#define EXTMEM_DBUS0_ACS_WB_CNT_V 0x000fffff
-#define EXTMEM_DBUS0_ACS_WB_CNT_S 0
-
-/* EXTMEM_DBUS2_ACS_MISS_CNT_REG register
- * register description
- */
-
-#define EXTMEM_DBUS2_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xd0)
-
-/* EXTMEM_DBUS2_ACS_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- * The bits are used to count the number of the cache miss caused by dbus2
- * access.
- */
-
-#define EXTMEM_DBUS2_ACS_MISS_CNT 0xffffffff
-#define EXTMEM_DBUS2_ACS_MISS_CNT_M (EXTMEM_DBUS2_ACS_MISS_CNT_V << EXTMEM_DBUS2_ACS_MISS_CNT_S)
-#define EXTMEM_DBUS2_ACS_MISS_CNT_V 0xffffffff
-#define EXTMEM_DBUS2_ACS_MISS_CNT_S 0
-
-/* EXTMEM_DBUS1_ACS_MISS_CNT_REG register
- * register description
- */
-
-#define EXTMEM_DBUS1_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xd4)
-
-/* EXTMEM_DBUS1_ACS_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- * The bits are used to count the number of the cache miss caused by dbus1
- * access.
- */
-
-#define EXTMEM_DBUS1_ACS_MISS_CNT 0xffffffff
-#define EXTMEM_DBUS1_ACS_MISS_CNT_M (EXTMEM_DBUS1_ACS_MISS_CNT_V << EXTMEM_DBUS1_ACS_MISS_CNT_S)
-#define EXTMEM_DBUS1_ACS_MISS_CNT_V 0xffffffff
-#define EXTMEM_DBUS1_ACS_MISS_CNT_S 0
-
-/* EXTMEM_DBUS0_ACS_MISS_CNT_REG register
- * register description
- */
-
-#define EXTMEM_DBUS0_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xd8)
-
-/* EXTMEM_DBUS0_ACS_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- * The bits are used to count the number of the cache miss caused by dbus0
- * access.
- */
-
-#define EXTMEM_DBUS0_ACS_MISS_CNT 0xffffffff
-#define EXTMEM_DBUS0_ACS_MISS_CNT_M (EXTMEM_DBUS0_ACS_MISS_CNT_V << EXTMEM_DBUS0_ACS_MISS_CNT_S)
-#define EXTMEM_DBUS0_ACS_MISS_CNT_V 0xffffffff
-#define EXTMEM_DBUS0_ACS_MISS_CNT_S 0
-
-/* EXTMEM_DBUS2_ACS_CNT_REG register
- * register description
- */
-
-#define EXTMEM_DBUS2_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xdc)
-
-/* EXTMEM_DBUS2_ACS_CNT : RO; bitpos: [31:0]; default: 0;
- * The bits are used to count the number of dbus2 access dcache.
- */
-
-#define EXTMEM_DBUS2_ACS_CNT 0xffffffff
-#define EXTMEM_DBUS2_ACS_CNT_M (EXTMEM_DBUS2_ACS_CNT_V << EXTMEM_DBUS2_ACS_CNT_S)
-#define EXTMEM_DBUS2_ACS_CNT_V 0xffffffff
-#define EXTMEM_DBUS2_ACS_CNT_S 0
-
-/* EXTMEM_DBUS1_ACS_CNT_REG register
- * register description
- */
-
-#define EXTMEM_DBUS1_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xe0)
-
-/* EXTMEM_DBUS1_ACS_CNT : RO; bitpos: [31:0]; default: 0;
- * The bits are used to count the number of dbus1 access dcache.
- */
-
-#define EXTMEM_DBUS1_ACS_CNT 0xffffffff
-#define EXTMEM_DBUS1_ACS_CNT_M (EXTMEM_DBUS1_ACS_CNT_V << EXTMEM_DBUS1_ACS_CNT_S)
-#define EXTMEM_DBUS1_ACS_CNT_V 0xffffffff
-#define EXTMEM_DBUS1_ACS_CNT_S 0
-
-/* EXTMEM_DBUS0_ACS_CNT_REG register
- * register description
- */
-
-#define EXTMEM_DBUS0_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xe4)
-
-/* EXTMEM_DBUS0_ACS_CNT : RO; bitpos: [31:0]; default: 0;
- * The bits are used to count the number of dbus0 access dcache.
- */
-
-#define EXTMEM_DBUS0_ACS_CNT 0xffffffff
-#define EXTMEM_DBUS0_ACS_CNT_M (EXTMEM_DBUS0_ACS_CNT_V << EXTMEM_DBUS0_ACS_CNT_S)
-#define EXTMEM_DBUS0_ACS_CNT_V 0xffffffff
-#define EXTMEM_DBUS0_ACS_CNT_S 0
-
-/* EXTMEM_CACHE_DBG_INT_ENA_REG register
- * register description
- */
-
-#define EXTMEM_CACHE_DBG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0xe8)
-
-/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W; bitpos: [19]; default: 0;
- * The bit is used to enable interrupt by mmu entry fault.
- */
-
-#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(19))
-#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V << EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S)
-#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x00000001
-#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 19
-
-/* EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA : R/W; bitpos: [18]; default: 0;
- * The bit is used to enable interrupt by illegal writing lock registers of
- * dcache while dcache is busy to issue lock,sync or pre-load operations.
- */
-
-#define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA (BIT(18))
-#define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_M (EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_V << EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_S)
-#define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_V 0x00000001
-#define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_S 18
-
-/* EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA : R/W; bitpos: [17]; default: 0;
- * The bit is used to enable interrupt by illegal writing sync registers of
- * dcache while dcache is busy to issue lock,sync and pre-load operations.
- */
-
-#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA (BIT(17))
-#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_M (EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_V << EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_S)
-#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_V 0x00000001
-#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_S 17
-
-/* EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA : R/W; bitpos: [16]; default: 0;
- * The bit is used to enable interrupt by illegal writing preload registers
- * of dcache while dcache is busy to issue lock,sync and pre-load operations.
- */
-
-#define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA (BIT(16))
-#define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_M (EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_V << EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_S)
-#define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_V 0x00000001
-#define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_S 16
-
-/* EXTMEM_DCACHE_REJECT_INT_ENA : R/W; bitpos: [15]; default: 0;
- * The bit is used to enable interrupt by authentication fail.
- */
-
-#define EXTMEM_DCACHE_REJECT_INT_ENA (BIT(15))
-#define EXTMEM_DCACHE_REJECT_INT_ENA_M (EXTMEM_DCACHE_REJECT_INT_ENA_V << EXTMEM_DCACHE_REJECT_INT_ENA_S)
-#define EXTMEM_DCACHE_REJECT_INT_ENA_V 0x00000001
-#define EXTMEM_DCACHE_REJECT_INT_ENA_S 15
-
-/* EXTMEM_DCACHE_WRITE_FLASH_INT_ENA : R/W; bitpos: [14]; default: 0;
- * The bit is used to enable interrupt by dcache trying to write flash.
- */
-
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA (BIT(14))
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_M (EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V << EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S)
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V 0x00000001
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S 14
-
-/* EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA : R/W; bitpos: [13]; default: 0;
- * The bit is used to enable interrupt by manual pre-load configurations
- * fault.
- */
-
-#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA (BIT(13))
-#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_M (EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_V << EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_S)
-#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_V 0x00000001
-#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_S 13
-
-/* EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA : R/W; bitpos: [12]; default: 0;
- * The bit is used to enable interrupt by manual sync configurations fault.
- */
-
-#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA (BIT(12))
-#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_M (EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_V << EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_S)
-#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_V 0x00000001
-#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_S 12
-
-/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
- * The bit is used to enable interrupt by dbus counter overflow.
- */
-
-#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(11))
-#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (EXTMEM_DBUS_CNT_OVF_INT_ENA_V << EXTMEM_DBUS_CNT_OVF_INT_ENA_S)
-#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x00000001
-#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 11
-
-/* EXTMEM_DBUS_ACS_MSK_DC_INT_ENA : R/W; bitpos: [10]; default: 0;
- * The bit is used to enable interrupt by cpu access dcache while the
- * corresponding dbus is disabled which include speculative access.
- */
-
-#define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA (BIT(10))
-#define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_M (EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_V << EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_S)
-#define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_V 0x00000001
-#define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_S 10
-
-/* EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA : R/W; bitpos: [9]; default: 0;
- * The bit is used to enable interrupt by illegal writing lock registers of
- * icache while icache is busy to issue lock,sync or pre-load operations.
- */
-
-#define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA (BIT(9))
-#define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_M (EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_V << EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_S)
-#define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_V 0x00000001
-#define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_S 9
-
-/* EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA : R/W; bitpos: [8]; default: 0;
- * The bit is used to enable interrupt by illegal writing sync registers of
- * icache while icache is busy to issue lock,sync and pre-load operations.
- */
-
-#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA (BIT(8))
-#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_M (EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_V << EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_S)
-#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_V 0x00000001
-#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_S 8
-
-/* EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA : R/W; bitpos: [7]; default: 0;
- * The bit is used to enable interrupt by illegal writing preload registers
- * of icache while icache is busy to issue lock,sync and pre-load operations.
- */
-
-#define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA (BIT(7))
-#define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_M (EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_V << EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_S)
-#define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_V 0x00000001
-#define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_S 7
-
-/* EXTMEM_ICACHE_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0;
- * The bit is used to enable interrupt by authentication fail.
- */
-
-#define EXTMEM_ICACHE_REJECT_INT_ENA (BIT(6))
-#define EXTMEM_ICACHE_REJECT_INT_ENA_M (EXTMEM_ICACHE_REJECT_INT_ENA_V << EXTMEM_ICACHE_REJECT_INT_ENA_S)
-#define EXTMEM_ICACHE_REJECT_INT_ENA_V 0x00000001
-#define EXTMEM_ICACHE_REJECT_INT_ENA_S 6
-
-/* EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA : R/W; bitpos: [5]; default: 0;
- * The bit is used to enable interrupt by manual pre-load configurations
- * fault.
- */
-
-#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA (BIT(5))
-#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_M (EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_V << EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_S)
-#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_V 0x00000001
-#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_S 5
-
-/* EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA : R/W; bitpos: [4]; default: 0;
- * The bit is used to enable interrupt by manual sync configurations fault.
- */
-
-#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA (BIT(4))
-#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_M (EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_V << EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_S)
-#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_V 0x00000001
-#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_S 4
-
-/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W; bitpos: [3]; default: 0;
- * The bit is used to enable interrupt by ibus counter overflow.
- */
-
-#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(3))
-#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (EXTMEM_IBUS_CNT_OVF_INT_ENA_V << EXTMEM_IBUS_CNT_OVF_INT_ENA_S)
-#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x00000001
-#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 3
-
-/* EXTMEM_IBUS_ACS_MSK_IC_INT_ENA : R/W; bitpos: [2]; default: 0;
- * The bit is used to enable interrupt by cpu access icache while the
- * corresponding ibus is disabled which include speculative access.
- */
-
-#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA (BIT(2))
-#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_M (EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_V << EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_S)
-#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_V 0x00000001
-#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_S 2
-
-/* EXTMEM_CACHE_DBG_EN : R/W; bitpos: [0]; default: 1;
- * The bit is used to activate the cache track function. 1: enable, 0:
- * disable.
- */
-
-#define EXTMEM_CACHE_DBG_EN (BIT(0))
-#define EXTMEM_CACHE_DBG_EN_M (EXTMEM_CACHE_DBG_EN_V << EXTMEM_CACHE_DBG_EN_S)
-#define EXTMEM_CACHE_DBG_EN_V 0x00000001
-#define EXTMEM_CACHE_DBG_EN_S 0
-
-/* EXTMEM_CACHE_DBG_INT_CLR_REG register
- * register description
- */
-
-#define EXTMEM_CACHE_DBG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xec)
-
-/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD; bitpos: [13]; default: 0;
- * The bit is used to clear interrupt by mmu entry fault.
- */
-
-#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(13))
-#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V << EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S)
-#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x00000001
-#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 13
-
-/* EXTMEM_DCACHE_SET_ILG_INT_CLR : WOD; bitpos: [12]; default: 0;
- * The bit is used to clear interrupt by illegal writing lock registers of
- * dcache while dcache is busy to issue lock,sync or pre-load operations.
- */
-
-#define EXTMEM_DCACHE_SET_ILG_INT_CLR (BIT(12))
-#define EXTMEM_DCACHE_SET_ILG_INT_CLR_M (EXTMEM_DCACHE_SET_ILG_INT_CLR_V << EXTMEM_DCACHE_SET_ILG_INT_CLR_S)
-#define EXTMEM_DCACHE_SET_ILG_INT_CLR_V 0x00000001
-#define EXTMEM_DCACHE_SET_ILG_INT_CLR_S 12
-
-/* EXTMEM_DCACHE_REJECT_INT_CLR : WOD; bitpos: [11]; default: 0;
- * The bit is used to clear interrupt by authentication fail.
- */
-
-#define EXTMEM_DCACHE_REJECT_INT_CLR (BIT(11))
-#define EXTMEM_DCACHE_REJECT_INT_CLR_M (EXTMEM_DCACHE_REJECT_INT_CLR_V << EXTMEM_DCACHE_REJECT_INT_CLR_S)
-#define EXTMEM_DCACHE_REJECT_INT_CLR_V 0x00000001
-#define EXTMEM_DCACHE_REJECT_INT_CLR_S 11
-
-/* EXTMEM_DCACHE_WRITE_FLASH_INT_CLR : WOD; bitpos: [10]; default: 0;
- * The bit is used to clear interrupt by dcache trying to write flash.
- */
-
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR (BIT(10))
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_M (EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V << EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S)
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V 0x00000001
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S 10
-
-/* EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR : WOD; bitpos: [9]; default: 0;
- * The bit is used to clear interrupt by manual pre-load configurations
- * fault.
- */
-
-#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR (BIT(9))
-#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_M (EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_V << EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_S)
-#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_V 0x00000001
-#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_S 9
-
-/* EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR : WOD; bitpos: [8]; default: 0;
- * The bit is used to clear interrupt by manual sync configurations fault.
- */
-
-#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR (BIT(8))
-#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_M (EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_V << EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_S)
-#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_V 0x00000001
-#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_S 8
-
-/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD; bitpos: [7]; default: 0;
- * The bit is used to clear interrupt by dbus counter overflow.
- */
-
-#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(7))
-#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (EXTMEM_DBUS_CNT_OVF_INT_CLR_V << EXTMEM_DBUS_CNT_OVF_INT_CLR_S)
-#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x00000001
-#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 7
-
-/* EXTMEM_DBUS_ACS_MSK_DC_INT_CLR : WOD; bitpos: [6]; default: 0;
- * The bit is used to clear interrupt by cpu access dcache while the
- * corresponding dbus is disabled or dcache is disabled which include
- * speculative access.
- */
-
-#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR (BIT(6))
-#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_M (EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_V << EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_S)
-#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_V 0x00000001
-#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_S 6
-
-/* EXTMEM_ICACHE_SET_ILG_INT_CLR : WOD; bitpos: [5]; default: 0;
- * The bit is used to clear interrupt by illegal writing lock registers of
- * icache while icache is busy to issue lock,sync or pre-load operations.
- */
-
-#define EXTMEM_ICACHE_SET_ILG_INT_CLR (BIT(5))
-#define EXTMEM_ICACHE_SET_ILG_INT_CLR_M (EXTMEM_ICACHE_SET_ILG_INT_CLR_V << EXTMEM_ICACHE_SET_ILG_INT_CLR_S)
-#define EXTMEM_ICACHE_SET_ILG_INT_CLR_V 0x00000001
-#define EXTMEM_ICACHE_SET_ILG_INT_CLR_S 5
-
-/* EXTMEM_ICACHE_REJECT_INT_CLR : WOD; bitpos: [4]; default: 0;
- * The bit is used to clear interrupt by authentication fail.
- */
-
-#define EXTMEM_ICACHE_REJECT_INT_CLR (BIT(4))
-#define EXTMEM_ICACHE_REJECT_INT_CLR_M (EXTMEM_ICACHE_REJECT_INT_CLR_V << EXTMEM_ICACHE_REJECT_INT_CLR_S)
-#define EXTMEM_ICACHE_REJECT_INT_CLR_V 0x00000001
-#define EXTMEM_ICACHE_REJECT_INT_CLR_S 4
-
-/* EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR : WOD; bitpos: [3]; default: 0;
- * The bit is used to clear interrupt by manual pre-load configurations
- * fault.
- */
-
-#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR (BIT(3))
-#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_M (EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_V << EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_S)
-#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_V 0x00000001
-#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_S 3
-
-/* EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR : WOD; bitpos: [2]; default: 0;
- * The bit is used to clear interrupt by manual sync configurations fault.
- */
-
-#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR (BIT(2))
-#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_M (EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_V << EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_S)
-#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_V 0x00000001
-#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_S 2
-
-/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD; bitpos: [1]; default: 0;
- * The bit is used to clear interrupt by ibus counter overflow.
- */
-
-#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(1))
-#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (EXTMEM_IBUS_CNT_OVF_INT_CLR_V << EXTMEM_IBUS_CNT_OVF_INT_CLR_S)
-#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x00000001
-#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 1
-
-/* EXTMEM_IBUS_ACS_MSK_IC_INT_CLR : WOD; bitpos: [0]; default: 0;
- * The bit is used to clear interrupt by cpu access icache while the
- * corresponding ibus is disabled or icache is disabled which include
- * speculative access.
- */
-
-#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR (BIT(0))
-#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_M (EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_V << EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_S)
-#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_V 0x00000001
-#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_S 0
-
-/* EXTMEM_CACHE_DBG_STATUS0_REG register
- * register description
- */
-
-#define EXTMEM_CACHE_DBG_STATUS0_REG (DR_REG_EXTMEM_BASE + 0xf0)
-
-/* EXTMEM_ICACHE_SET_LOCK_ILG_ST : RO; bitpos: [24]; default: 0;
- * The bit is used to indicate interrupt by illegal writing lock registers
- * of icache while icache is busy to issue lock,sync or pre-load operations.
- */
-
-#define EXTMEM_ICACHE_SET_LOCK_ILG_ST (BIT(24))
-#define EXTMEM_ICACHE_SET_LOCK_ILG_ST_M (EXTMEM_ICACHE_SET_LOCK_ILG_ST_V << EXTMEM_ICACHE_SET_LOCK_ILG_ST_S)
-#define EXTMEM_ICACHE_SET_LOCK_ILG_ST_V 0x00000001
-#define EXTMEM_ICACHE_SET_LOCK_ILG_ST_S 24
-
-/* EXTMEM_ICACHE_SET_SYNC_ILG_ST : RO; bitpos: [23]; default: 0;
- * The bit is used to indicate interrupt by illegal writing sync registers
- * of icache while icache is busy to issue lock,sync and pre-load operations.
- */
-
-#define EXTMEM_ICACHE_SET_SYNC_ILG_ST (BIT(23))
-#define EXTMEM_ICACHE_SET_SYNC_ILG_ST_M (EXTMEM_ICACHE_SET_SYNC_ILG_ST_V << EXTMEM_ICACHE_SET_SYNC_ILG_ST_S)
-#define EXTMEM_ICACHE_SET_SYNC_ILG_ST_V 0x00000001
-#define EXTMEM_ICACHE_SET_SYNC_ILG_ST_S 23
-
-/* EXTMEM_ICACHE_SET_PRELOAD_ILG_ST : RO; bitpos: [22]; default: 0;
- * The bit is used to indicate interrupt by illegal writing preload
- * registers of icache while icache is busy to issue lock,sync and pre-load
- * operations.
- */
-
-#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST (BIT(22))
-#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_M (EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_V << EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_S)
-#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_V 0x00000001
-#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_S 22
-
-/* EXTMEM_ICACHE_REJECT_ST : RO; bitpos: [21]; default: 0;
- * The bit is used to indicate interrupt by authentication fail.
- */
-
-#define EXTMEM_ICACHE_REJECT_ST (BIT(21))
-#define EXTMEM_ICACHE_REJECT_ST_M (EXTMEM_ICACHE_REJECT_ST_V << EXTMEM_ICACHE_REJECT_ST_S)
-#define EXTMEM_ICACHE_REJECT_ST_V 0x00000001
-#define EXTMEM_ICACHE_REJECT_ST_S 21
-
-/* EXTMEM_IC_PRELOAD_SIZE_FAULT_ST : RO; bitpos: [20]; default: 0;
- * The bit is used to indicate interrupt by manual pre-load configurations
- * fault.
- */
-
-#define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST (BIT(20))
-#define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_M (EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_V << EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_S)
-#define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_V 0x00000001
-#define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_S 20
-
-/* EXTMEM_IC_SYNC_SIZE_FAULT_ST : RO; bitpos: [19]; default: 0;
- * The bit is used to indicate interrupt by manual sync configurations fault.
- */
-
-#define EXTMEM_IC_SYNC_SIZE_FAULT_ST (BIT(19))
-#define EXTMEM_IC_SYNC_SIZE_FAULT_ST_M (EXTMEM_IC_SYNC_SIZE_FAULT_ST_V << EXTMEM_IC_SYNC_SIZE_FAULT_ST_S)
-#define EXTMEM_IC_SYNC_SIZE_FAULT_ST_V 0x00000001
-#define EXTMEM_IC_SYNC_SIZE_FAULT_ST_S 19
-
-/* EXTMEM_IC_PRELOAD_CNT_OVF_ST : RO; bitpos: [18]; default: 0;
- * The bit is used to indicate interrupt by pre-load counter overflow.
- */
-
-#define EXTMEM_IC_PRELOAD_CNT_OVF_ST (BIT(18))
-#define EXTMEM_IC_PRELOAD_CNT_OVF_ST_M (EXTMEM_IC_PRELOAD_CNT_OVF_ST_V << EXTMEM_IC_PRELOAD_CNT_OVF_ST_S)
-#define EXTMEM_IC_PRELOAD_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_IC_PRELOAD_CNT_OVF_ST_S 18
-
-/* EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST : RO; bitpos: [16]; default: 0;
- * The bit is used to indicate interrupt by pre-load miss counter overflow.
- */
-
-#define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST (BIT(16))
-#define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_M (EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_V << EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_S)
-#define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_S 16
-
-/* EXTMEM_IBUS2_ABANDON_CNT_OVF_ST : RO; bitpos: [14]; default: 0;
- * The bit is used to indicate interrupt by ibus2 abandon counter overflow.
- */
-
-#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST (BIT(14))
-#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_M (EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_V << EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_S)
-#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_S 14
-
-/* EXTMEM_IBUS1_ABANDON_CNT_OVF_ST : RO; bitpos: [13]; default: 0;
- * The bit is used to indicate interrupt by ibus1 abandon counter overflow.
- */
-
-#define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST (BIT(13))
-#define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_M (EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_V << EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_S)
-#define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_S 13
-
-/* EXTMEM_IBUS0_ABANDON_CNT_OVF_ST : RO; bitpos: [12]; default: 0;
- * The bit is used to indicate interrupt by ibus0 abandon counter overflow.
- */
-
-#define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST (BIT(12))
-#define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_M (EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_V << EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_S)
-#define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_S 12
-
-/* EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST : RO; bitpos: [10]; default: 0;
- * The bit is used to indicate interrupt by ibus2 miss counter overflow.
- */
-
-#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST (BIT(10))
-#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_M (EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_V << EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_S)
-#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_S 10
-
-/* EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST : RO; bitpos: [9]; default: 0;
- * The bit is used to indicate interrupt by ibus1 miss counter overflow.
- */
-
-#define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST (BIT(9))
-#define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_M (EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_V << EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_S)
-#define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_S 9
-
-/* EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST : RO; bitpos: [8]; default: 0;
- * The bit is used to indicate interrupt by ibus0 miss counter overflow.
- */
-
-#define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST (BIT(8))
-#define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_M (EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_V << EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_S)
-#define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_S 8
-
-/* EXTMEM_IBUS2_ACS_CNT_OVF_ST : RO; bitpos: [6]; default: 0;
- * The bit is used to indicate interrupt by ibus2 counter overflow.
- */
-
-#define EXTMEM_IBUS2_ACS_CNT_OVF_ST (BIT(6))
-#define EXTMEM_IBUS2_ACS_CNT_OVF_ST_M (EXTMEM_IBUS2_ACS_CNT_OVF_ST_V << EXTMEM_IBUS2_ACS_CNT_OVF_ST_S)
-#define EXTMEM_IBUS2_ACS_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_IBUS2_ACS_CNT_OVF_ST_S 6
-
-/* EXTMEM_IBUS1_ACS_CNT_OVF_ST : RO; bitpos: [5]; default: 0;
- * The bit is used to indicate interrupt by ibus1 counter overflow.
- */
-
-#define EXTMEM_IBUS1_ACS_CNT_OVF_ST (BIT(5))
-#define EXTMEM_IBUS1_ACS_CNT_OVF_ST_M (EXTMEM_IBUS1_ACS_CNT_OVF_ST_V << EXTMEM_IBUS1_ACS_CNT_OVF_ST_S)
-#define EXTMEM_IBUS1_ACS_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_IBUS1_ACS_CNT_OVF_ST_S 5
-
-/* EXTMEM_IBUS0_ACS_CNT_OVF_ST : RO; bitpos: [4]; default: 0;
- * The bit is used to indicate interrupt by ibus0 counter overflow.
- */
-
-#define EXTMEM_IBUS0_ACS_CNT_OVF_ST (BIT(4))
-#define EXTMEM_IBUS0_ACS_CNT_OVF_ST_M (EXTMEM_IBUS0_ACS_CNT_OVF_ST_V << EXTMEM_IBUS0_ACS_CNT_OVF_ST_S)
-#define EXTMEM_IBUS0_ACS_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_IBUS0_ACS_CNT_OVF_ST_S 4
-
-/* EXTMEM_IBUS2_ACS_MSK_ICACHE_ST : RO; bitpos: [2]; default: 0;
- * The bit is used to indicate interrupt by cpu access icache while the
- * ibus2 is disabled or icache is disabled which include speculative access.
- */
-
-#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST (BIT(2))
-#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_M (EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_V << EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_S)
-#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_V 0x00000001
-#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_S 2
-
-/* EXTMEM_IBUS1_ACS_MSK_ICACHE_ST : RO; bitpos: [1]; default: 0;
- * The bit is used to indicate interrupt by cpu access icache while the
- * ibus1 is disabled or icache is disabled which include speculative access.
- */
-
-#define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST (BIT(1))
-#define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_M (EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_V << EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_S)
-#define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_V 0x00000001
-#define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_S 1
-
-/* EXTMEM_IBUS0_ACS_MSK_ICACHE_ST : RO; bitpos: [0]; default: 0;
- * The bit is used to indicate interrupt by cpu access icache while the
- * ibus0 is disabled or icache is disabled which include speculative access.
- */
-
-#define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST (BIT(0))
-#define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_M (EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_V << EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_S)
-#define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_V 0x00000001
-#define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_S 0
-
-/* EXTMEM_CACHE_DBG_STATUS1_REG register
- * register description
- */
-
-#define EXTMEM_CACHE_DBG_STATUS1_REG (DR_REG_EXTMEM_BASE + 0xf4)
-
-/* EXTMEM_MMU_ENTRY_FAULT_ST : RO; bitpos: [30]; default: 0;
- * The bit is used to indicate interrupt by mmu entry fault.
- */
-
-#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(30))
-#define EXTMEM_MMU_ENTRY_FAULT_ST_M (EXTMEM_MMU_ENTRY_FAULT_ST_V << EXTMEM_MMU_ENTRY_FAULT_ST_S)
-#define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x00000001
-#define EXTMEM_MMU_ENTRY_FAULT_ST_S 30
-
-/* EXTMEM_DCACHE_SET_LOCK_ILG_ST : RO; bitpos: [29]; default: 0;
- * The bit is used to indicate interrupt by illegal writing lock registers
- * of icache while icache is busy to issue lock,sync or pre-load operations.
- */
-
-#define EXTMEM_DCACHE_SET_LOCK_ILG_ST (BIT(29))
-#define EXTMEM_DCACHE_SET_LOCK_ILG_ST_M (EXTMEM_DCACHE_SET_LOCK_ILG_ST_V << EXTMEM_DCACHE_SET_LOCK_ILG_ST_S)
-#define EXTMEM_DCACHE_SET_LOCK_ILG_ST_V 0x00000001
-#define EXTMEM_DCACHE_SET_LOCK_ILG_ST_S 29
-
-/* EXTMEM_DCACHE_SET_SYNC_ILG_ST : RO; bitpos: [28]; default: 0;
- * The bit is used to indicate interrupt by illegal writing sync registers
- * of icache while icache is busy to issue lock,sync and pre-load operations.
- */
-
-#define EXTMEM_DCACHE_SET_SYNC_ILG_ST (BIT(28))
-#define EXTMEM_DCACHE_SET_SYNC_ILG_ST_M (EXTMEM_DCACHE_SET_SYNC_ILG_ST_V << EXTMEM_DCACHE_SET_SYNC_ILG_ST_S)
-#define EXTMEM_DCACHE_SET_SYNC_ILG_ST_V 0x00000001
-#define EXTMEM_DCACHE_SET_SYNC_ILG_ST_S 28
-
-/* EXTMEM_DCACHE_SET_PRELOAD_ILG_ST : RO; bitpos: [27]; default: 0;
- * The bit is used to indicate interrupt by illegal writing preload
- * registers of icache while icache is busy to issue lock,sync and pre-load
- * operations.
- */
-
-#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST (BIT(27))
-#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_M (EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_V << EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_S)
-#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_V 0x00000001
-#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_S 27
-
-/* EXTMEM_DCACHE_REJECT_ST : RO; bitpos: [26]; default: 0;
- * The bit is used to indicate interrupt by authentication fail.
- */
-
-#define EXTMEM_DCACHE_REJECT_ST (BIT(26))
-#define EXTMEM_DCACHE_REJECT_ST_M (EXTMEM_DCACHE_REJECT_ST_V << EXTMEM_DCACHE_REJECT_ST_S)
-#define EXTMEM_DCACHE_REJECT_ST_V 0x00000001
-#define EXTMEM_DCACHE_REJECT_ST_S 26
-
-/* EXTMEM_DCACHE_WRITE_FLASH_ST : RO; bitpos: [25]; default: 0;
- * The bit is used to indicate interrupt by dcache trying to write flash.
- */
-
-#define EXTMEM_DCACHE_WRITE_FLASH_ST (BIT(25))
-#define EXTMEM_DCACHE_WRITE_FLASH_ST_M (EXTMEM_DCACHE_WRITE_FLASH_ST_V << EXTMEM_DCACHE_WRITE_FLASH_ST_S)
-#define EXTMEM_DCACHE_WRITE_FLASH_ST_V 0x00000001
-#define EXTMEM_DCACHE_WRITE_FLASH_ST_S 25
-
-/* EXTMEM_DC_PRELOAD_SIZE_FAULT_ST : RO; bitpos: [24]; default: 0;
- * The bit is used to indicate interrupt by manual pre-load configurations
- * fault.
- */
-
-#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST (BIT(24))
-#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_M (EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_V << EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_S)
-#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_V 0x00000001
-#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_S 24
-
-/* EXTMEM_DC_SYNC_SIZE_FAULT_ST : RO; bitpos: [23]; default: 0;
- * The bit is used to indicate interrupt by manual sync configurations fault.
- */
-
-#define EXTMEM_DC_SYNC_SIZE_FAULT_ST (BIT(23))
-#define EXTMEM_DC_SYNC_SIZE_FAULT_ST_M (EXTMEM_DC_SYNC_SIZE_FAULT_ST_V << EXTMEM_DC_SYNC_SIZE_FAULT_ST_S)
-#define EXTMEM_DC_SYNC_SIZE_FAULT_ST_V 0x00000001
-#define EXTMEM_DC_SYNC_SIZE_FAULT_ST_S 23
-
-/* EXTMEM_DC_PRELOAD_CNT_OVF_ST : RO; bitpos: [22]; default: 0;
- * The bit is used to indicate interrupt by pre-load counter overflow.
- */
-
-#define EXTMEM_DC_PRELOAD_CNT_OVF_ST (BIT(22))
-#define EXTMEM_DC_PRELOAD_CNT_OVF_ST_M (EXTMEM_DC_PRELOAD_CNT_OVF_ST_V << EXTMEM_DC_PRELOAD_CNT_OVF_ST_S)
-#define EXTMEM_DC_PRELOAD_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_DC_PRELOAD_CNT_OVF_ST_S 22
-
-/* EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST : RO; bitpos: [21]; default: 0;
- * The bit is used to indicate interrupt by pre-load eviction counter
- * overflow.
- */
-
-#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST (BIT(21))
-#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_M (EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_V << EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_S)
-#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_S 21
-
-/* EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST : RO; bitpos: [20]; default: 0;
- * The bit is used to indicate interrupt by pre-load miss counter overflow.
- */
-
-#define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST (BIT(20))
-#define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_M (EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_V << EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_S)
-#define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_S 20
-
-/* EXTMEM_DBUS2_ABANDON_CNT_OVF_ST : RO; bitpos: [18]; default: 0;
- * The bit is used to indicate interrupt by dbus2 abandon counter overflow.
- */
-
-#define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST (BIT(18))
-#define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_M (EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_V << EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_S)
-#define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_S 18
-
-/* EXTMEM_DBUS1_ABANDON_CNT_OVF_ST : RO; bitpos: [17]; default: 0;
- * The bit is used to indicate interrupt by dbus1 abandon counter overflow.
- */
-
-#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST (BIT(17))
-#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_M (EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_V << EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_S)
-#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_S 17
-
-/* EXTMEM_DBUS0_ABANDON_CNT_OVF_ST : RO; bitpos: [16]; default: 0;
- * The bit is used to indicate interrupt by dbus0 abandon counter overflow.
- */
-
-#define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST (BIT(16))
-#define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_M (EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_V << EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_S)
-#define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_S 16
-
-/* EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST : RO; bitpos: [14]; default: 0;
- * The bit is used to indicate interrupt by dbus2 eviction counter overflow.
- */
-
-#define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST (BIT(14))
-#define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_M (EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_V << EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_S)
-#define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_S 14
-
-/* EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST : RO; bitpos: [13]; default: 0;
- * The bit is used to indicate interrupt by dbus1 eviction counter overflow.
- */
-
-#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST (BIT(13))
-#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_M (EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_V << EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_S)
-#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_S 13
-
-/* EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST : RO; bitpos: [12]; default: 0;
- * The bit is used to indicate interrupt by dbus0 eviction counter overflow.
- */
-
-#define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST (BIT(12))
-#define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_M (EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_V << EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_S)
-#define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_S 12
-
-/* EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST : RO; bitpos: [10]; default: 0;
- * The bit is used to indicate interrupt by dbus2 miss counter overflow.
- */
-
-#define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST (BIT(10))
-#define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_M (EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_V << EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_S)
-#define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_S 10
-
-/* EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST : RO; bitpos: [9]; default: 0;
- * The bit is used to indicate interrupt by dbus1 miss counter overflow.
- */
-
-#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST (BIT(9))
-#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_M (EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_V << EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_S)
-#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_S 9
-
-/* EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST : RO; bitpos: [8]; default: 0;
- * The bit is used to indicate interrupt by dbus0 miss counter overflow.
- */
-
-#define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST (BIT(8))
-#define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_M (EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_V << EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_S)
-#define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_S 8
-
-/* EXTMEM_DBUS2_ACS_CNT_OVF_ST : RO; bitpos: [6]; default: 0;
- * The bit is used to indicate interrupt by dbus2 counter overflow.
- */
-
-#define EXTMEM_DBUS2_ACS_CNT_OVF_ST (BIT(6))
-#define EXTMEM_DBUS2_ACS_CNT_OVF_ST_M (EXTMEM_DBUS2_ACS_CNT_OVF_ST_V << EXTMEM_DBUS2_ACS_CNT_OVF_ST_S)
-#define EXTMEM_DBUS2_ACS_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_DBUS2_ACS_CNT_OVF_ST_S 6
-
-/* EXTMEM_DBUS1_ACS_CNT_OVF_ST : RO; bitpos: [5]; default: 0;
- * The bit is used to indicate interrupt by dbus1 counter overflow.
- */
-
-#define EXTMEM_DBUS1_ACS_CNT_OVF_ST (BIT(5))
-#define EXTMEM_DBUS1_ACS_CNT_OVF_ST_M (EXTMEM_DBUS1_ACS_CNT_OVF_ST_V << EXTMEM_DBUS1_ACS_CNT_OVF_ST_S)
-#define EXTMEM_DBUS1_ACS_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_DBUS1_ACS_CNT_OVF_ST_S 5
-
-/* EXTMEM_DBUS0_ACS_CNT_OVF_ST : RO; bitpos: [4]; default: 0;
- * The bit is used to indicate interrupt by dbus0 counter overflow.
- */
-
-#define EXTMEM_DBUS0_ACS_CNT_OVF_ST (BIT(4))
-#define EXTMEM_DBUS0_ACS_CNT_OVF_ST_M (EXTMEM_DBUS0_ACS_CNT_OVF_ST_V << EXTMEM_DBUS0_ACS_CNT_OVF_ST_S)
-#define EXTMEM_DBUS0_ACS_CNT_OVF_ST_V 0x00000001
-#define EXTMEM_DBUS0_ACS_CNT_OVF_ST_S 4
-
-/* EXTMEM_DBUS2_ACS_MSK_DCACHE_ST : RO; bitpos: [2]; default: 0;
- * The bit is used to indicate interrupt by cpu access dcache while the
- * dbus2 is disabled or dcache is disabled which include speculative access.
- */
-
-#define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST (BIT(2))
-#define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_M (EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_V << EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_S)
-#define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_V 0x00000001
-#define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_S 2
-
-/* EXTMEM_DBUS1_ACS_MSK_DCACHE_ST : RO; bitpos: [1]; default: 0;
- * The bit is used to indicate interrupt by cpu access dcache while the
- * dbus1 is disabled or dcache is disabled which include speculative access.
- */
-
-#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST (BIT(1))
-#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_M (EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_V << EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_S)
-#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_V 0x00000001
-#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_S 1
-
-/* EXTMEM_DBUS0_ACS_MSK_DCACHE_ST : RO; bitpos: [0]; default: 0;
- * The bit is used to indicate interrupt by cpu access dcache while the
- * dbus0 is disabled or dcache is disabled which include speculative access.
- */
-
-#define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST (BIT(0))
-#define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_M (EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_V << EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_S)
-#define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_V 0x00000001
-#define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_S 0
-
-/* EXTMEM_PRO_CACHE_ACS_CNT_CLR_REG register
- * register description
- */
-
-#define EXTMEM_PRO_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0xf8)
-
-/* EXTMEM_PRO_ICACHE_ACS_CNT_CLR : WOD; bitpos: [1]; default: 0;
- * The bit is used to clear icache counter which include IC_PRELOAD_CNT_REG,
- * IC_PRELOAD_MISS_CNT_REG, IBUS0-2_ABANDON_CNT_REG,
- * IBUS0-2_ACS_MISS_CNT_REG and IBUS0-2_ACS_CNT_REG.
- */
-
-#define EXTMEM_PRO_ICACHE_ACS_CNT_CLR (BIT(1))
-#define EXTMEM_PRO_ICACHE_ACS_CNT_CLR_M (EXTMEM_PRO_ICACHE_ACS_CNT_CLR_V << EXTMEM_PRO_ICACHE_ACS_CNT_CLR_S)
-#define EXTMEM_PRO_ICACHE_ACS_CNT_CLR_V 0x00000001
-#define EXTMEM_PRO_ICACHE_ACS_CNT_CLR_S 1
-
-/* EXTMEM_PRO_DCACHE_ACS_CNT_CLR : WOD; bitpos: [0]; default: 0;
- * The bit is used to clear dcache counter which include DC_PRELOAD_CNT_REG,
- * DC_PRELOAD_EVICT_CNT_REG, DC_PRELOAD_MISS_CNT_REG,
- * DBUS0-2_ABANDON_CNT_REG, DBUS0-2_ACS_WB_CNT_REG, DBUS0-2_ACS_MISS_CNT_REG
- * and DBUS0-2_ACS_CNT_REG.
- */
-
-#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR (BIT(0))
-#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR_M (EXTMEM_PRO_DCACHE_ACS_CNT_CLR_V << EXTMEM_PRO_DCACHE_ACS_CNT_CLR_S)
-#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR_V 0x00000001
-#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR_S 0
-
-/* EXTMEM_PRO_DCACHE_REJECT_ST_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0xfc)
-
-/* EXTMEM_PRO_DCACHE_CPU_ATTR : RO; bitpos: [5:3]; default: 0;
- * The bits are used to indicate the attribute of CPU access dcache when
- * authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4:
- * write-able.
- */
-
-#define EXTMEM_PRO_DCACHE_CPU_ATTR 0x00000007
-#define EXTMEM_PRO_DCACHE_CPU_ATTR_M (EXTMEM_PRO_DCACHE_CPU_ATTR_V << EXTMEM_PRO_DCACHE_CPU_ATTR_S)
-#define EXTMEM_PRO_DCACHE_CPU_ATTR_V 0x00000007
-#define EXTMEM_PRO_DCACHE_CPU_ATTR_S 3
-
-/* EXTMEM_PRO_DCACHE_TAG_ATTR : RO; bitpos: [2:0]; default: 0;
- * The bits are used to indicate the attribute of data from external memory
- * when authentication fail. 0: invalidate, 1: execute-able, 2: read-able,
- * 4: write-able.
- */
-
-#define EXTMEM_PRO_DCACHE_TAG_ATTR 0x00000007
-#define EXTMEM_PRO_DCACHE_TAG_ATTR_M (EXTMEM_PRO_DCACHE_TAG_ATTR_V << EXTMEM_PRO_DCACHE_TAG_ATTR_S)
-#define EXTMEM_PRO_DCACHE_TAG_ATTR_V 0x00000007
-#define EXTMEM_PRO_DCACHE_TAG_ATTR_S 0
-
-/* EXTMEM_PRO_DCACHE_REJECT_VADDR_REG register
- * register description
- */
-
-#define EXTMEM_PRO_DCACHE_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x100)
-
-/* EXTMEM_PRO_DCACHE_CPU_VADDR : RO; bitpos: [31:0]; default: 0;
- * The bits are used to indicate the virtual address of CPU access dcache
- * when authentication fail.
- */
-
-#define EXTMEM_PRO_DCACHE_CPU_VADDR 0xffffffff
-#define EXTMEM_PRO_DCACHE_CPU_VADDR_M (EXTMEM_PRO_DCACHE_CPU_VADDR_V << EXTMEM_PRO_DCACHE_CPU_VADDR_S)
-#define EXTMEM_PRO_DCACHE_CPU_VADDR_V 0xffffffff
-#define EXTMEM_PRO_DCACHE_CPU_VADDR_S 0
-
-/* EXTMEM_PRO_ICACHE_REJECT_ST_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x104)
-
-/* EXTMEM_PRO_ICACHE_CPU_ATTR : RO; bitpos: [5:3]; default: 0;
- * The bits are used to indicate the attribute of CPU access icache when
- * authentication fail. 0: invalidate, 1: execute-able, 2: read-able
- */
-
-#define EXTMEM_PRO_ICACHE_CPU_ATTR 0x00000007
-#define EXTMEM_PRO_ICACHE_CPU_ATTR_M (EXTMEM_PRO_ICACHE_CPU_ATTR_V << EXTMEM_PRO_ICACHE_CPU_ATTR_S)
-#define EXTMEM_PRO_ICACHE_CPU_ATTR_V 0x00000007
-#define EXTMEM_PRO_ICACHE_CPU_ATTR_S 3
-
-/* EXTMEM_PRO_ICACHE_TAG_ATTR : RO; bitpos: [2:0]; default: 0;
- * The bits are used to indicate the attribute of data from external memory
- * when authentication fail. 0: invalidate, 1: execute-able, 2: read-able,
- * 4: write-able.
- */
-
-#define EXTMEM_PRO_ICACHE_TAG_ATTR 0x00000007
-#define EXTMEM_PRO_ICACHE_TAG_ATTR_M (EXTMEM_PRO_ICACHE_TAG_ATTR_V << EXTMEM_PRO_ICACHE_TAG_ATTR_S)
-#define EXTMEM_PRO_ICACHE_TAG_ATTR_V 0x00000007
-#define EXTMEM_PRO_ICACHE_TAG_ATTR_S 0
-
-/* EXTMEM_PRO_ICACHE_REJECT_VADDR_REG register
- * register description
- */
-
-#define EXTMEM_PRO_ICACHE_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x108)
-
-/* EXTMEM_PRO_ICACHE_CPU_VADDR : RO; bitpos: [31:0]; default: 0;
- * The bits are used to indicate the virtual address of CPU access icache
- * when authentication fail.
- */
-
-#define EXTMEM_PRO_ICACHE_CPU_VADDR 0xffffffff
-#define EXTMEM_PRO_ICACHE_CPU_VADDR_M (EXTMEM_PRO_ICACHE_CPU_VADDR_V << EXTMEM_PRO_ICACHE_CPU_VADDR_S)
-#define EXTMEM_PRO_ICACHE_CPU_VADDR_V 0xffffffff
-#define EXTMEM_PRO_ICACHE_CPU_VADDR_S 0
-
-/* EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG register
- * register description
- */
-
-#define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x10c)
-
-/* EXTMEM_PRO_CACHE_MMU_FAULT_CODE : RO; bitpos: [19:17]; default: 0;
- * The bits are used to indicate the operations which cause mmu fault
- * occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: flush, 4: cpu
- * miss evict recovery address, 5: load miss evict recovery address, 6:
- * external dma tx, 7: external dma rx
- */
-
-#define EXTMEM_PRO_CACHE_MMU_FAULT_CODE 0x00000007
-#define EXTMEM_PRO_CACHE_MMU_FAULT_CODE_M (EXTMEM_PRO_CACHE_MMU_FAULT_CODE_V << EXTMEM_PRO_CACHE_MMU_FAULT_CODE_S)
-#define EXTMEM_PRO_CACHE_MMU_FAULT_CODE_V 0x00000007
-#define EXTMEM_PRO_CACHE_MMU_FAULT_CODE_S 17
-
-/* EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT : RO; bitpos: [16:0]; default: 0;
- * The bits are used to indicate the content of mmu entry which cause mmu
- * fault..
- */
-
-#define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT 0x0001ffff
-#define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_M (EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_V << EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_S)
-#define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_V 0x0001ffff
-#define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_S 0
-
-/* EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_REG register
- * register description
- */
-
-#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x110)
-
-/* EXTMEM_PRO_CACHE_MMU_FAULT_VADDR : RO; bitpos: [31:0]; default: 0;
- * The bits are used to indicate the virtual address which cause mmu fault..
- */
-
-#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR 0xffffffff
-#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_M (EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_V << EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_S)
-#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_V 0xffffffff
-#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_S 0
-
-/* EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_REG register
- * register description
- */
-
-#define EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x114)
-
-/* EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND : R/W; bitpos: [1]; default: 0;
- * The bit is used to enable wrap around mode when read data from spiram.
- */
-
-#define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND (BIT(1))
-#define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_M (EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_V << EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_S)
-#define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_V 0x00000001
-#define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_S 1
-
-/* EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND : R/W; bitpos: [0]; default: 0;
- * The bit is used to enable wrap around mode when read data from flash.
- */
-
-#define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND (BIT(0))
-#define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_M (EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_V << EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_S)
-#define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_V 0x00000001
-#define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_S 0
-
-/* EXTMEM_PRO_CACHE_MMU_POWER_CTRL_REG register
- * register description
- */
-
-#define EXTMEM_PRO_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x118)
-
-/* EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
- * The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power
- * up
- */
-
-#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU (BIT(2))
-#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_M (EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_V << EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_S)
-#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_V 0x00000001
-#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_S 2
-
-/* EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
- * The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power
- * down
- */
-
-#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD (BIT(1))
-#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_M (EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_V << EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_S)
-#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_V 0x00000001
-#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_S 1
-
-/* EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1;
- * The bit is used to enable clock gating to save power when access mmu
- * memory, 0: enable, 1: disable
- */
-
-#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON (BIT(0))
-#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_M (EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_V << EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_S)
-#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_V 0x00000001
-#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_S 0
-
-/* EXTMEM_PRO_CACHE_STATE_REG register
- * register description
- */
-
-#define EXTMEM_PRO_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0x11c)
-
-/* EXTMEM_PRO_DCACHE_STATE : RO; bitpos: [23:12]; default: 0;
- * The bit is used to indicate dcache main fsm is in idle state or not. 1:
- * in idle state, 0: not in idle state
- */
-
-#define EXTMEM_PRO_DCACHE_STATE 0x00000fff
-#define EXTMEM_PRO_DCACHE_STATE_M (EXTMEM_PRO_DCACHE_STATE_V << EXTMEM_PRO_DCACHE_STATE_S)
-#define EXTMEM_PRO_DCACHE_STATE_V 0x00000fff
-#define EXTMEM_PRO_DCACHE_STATE_S 12
-
-/* EXTMEM_PRO_ICACHE_STATE : RO; bitpos: [11:0]; default: 0;
- * The bit is used to indicate icache main fsm is in idle state or not. 1:
- * in idle state, 0: not in idle state
- */
-
-#define EXTMEM_PRO_ICACHE_STATE 0x00000fff
-#define EXTMEM_PRO_ICACHE_STATE_M (EXTMEM_PRO_ICACHE_STATE_V << EXTMEM_PRO_ICACHE_STATE_S)
-#define EXTMEM_PRO_ICACHE_STATE_V 0x00000fff
-#define EXTMEM_PRO_ICACHE_STATE_S 0
-
-/* EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG register
- * register description
- */
-
-#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0x120)
-
-/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W; bitpos: [1]; default: 0;
- * Reserved.
- */
-
-#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1))
-#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V << EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S)
-#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x00000001
-#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1
-
-/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W; bitpos: [0]; default: 0;
- * Reserved.
- */
-
-#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0))
-#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V << EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S)
-#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x00000001
-#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0
-
-/* EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG register
- * register description
- */
-
-#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x124)
-
-/* EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT : R/W; bitpos: [2];
- * default: 1;
- * The bit is used to close clock gating of encrypt and decrypt clock. 1:
- * close gating, 0: open clock gating.
- */
-
-#define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT (BIT(2))
-#define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_M (EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_V << EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_S)
-#define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_V 0x00000001
-#define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_S 2
-
-/* EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT : R/W; bitpos: [1]; default: 1;
- * The bit is used to close clock gating of decrypt clock. 1: close gating,
- * 0: open clock gating.
- */
-
-#define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT (BIT(1))
-#define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_M (EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_V << EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_S)
-#define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_V 0x00000001
-#define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_S 1
-
-/* EXTMEM_CLK_FORCE_ON_DB_ENCRYPT : R/W; bitpos: [0]; default: 1;
- * The bit is used to close clock gating of encrypt clock. 1: close gating,
- * 0: open clock gating.
- */
-
-#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT (BIT(0))
-#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_M (EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_V << EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_S)
-#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_V 0x00000001
-#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_S 0
-
-/* EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG register
- * register description
- */
-
-#define EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x128)
-
-/* EXTMEM_ALLOC_WB_HOLD_ARBITER : R/W; bitpos: [0]; default: 0;
- * Reserved.
- */
-
-#define EXTMEM_ALLOC_WB_HOLD_ARBITER (BIT(0))
-#define EXTMEM_ALLOC_WB_HOLD_ARBITER_M (EXTMEM_ALLOC_WB_HOLD_ARBITER_V << EXTMEM_ALLOC_WB_HOLD_ARBITER_S)
-#define EXTMEM_ALLOC_WB_HOLD_ARBITER_V 0x00000001
-#define EXTMEM_ALLOC_WB_HOLD_ARBITER_S 0
-
-/* EXTMEM_CACHE_PRELOAD_INT_CTRL_REG register
- * register description
- */
-
-#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x12c)
-
-/* EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR : WOD; bitpos: [5]; default: 0;
- * The bit is used to clear the interrupt by dcache pre-load done.
- */
-
-#define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR (BIT(5))
-#define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_M (EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_V << EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_S)
-#define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_V 0x00000001
-#define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_S 5
-
-/* EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA : R/W; bitpos: [4]; default: 0;
- * The bit is used to enable the interrupt by dcache pre-load done.
- */
-
-#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA (BIT(4))
-#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_M (EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_V << EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_S)
-#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_V 0x00000001
-#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_S 4
-
-/* EXTMEM_PRO_DCACHE_PRELOAD_INT_ST : RO; bitpos: [3]; default: 0;
- * The bit is used to indicate the interrupt by dcache pre-load done.
- */
-
-#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST (BIT(3))
-#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_M (EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_V << EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_S)
-#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_V 0x00000001
-#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_S 3
-
-/* EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR : WOD; bitpos: [2]; default: 0;
- * The bit is used to clear the interrupt by icache pre-load done.
- */
-
-#define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR (BIT(2))
-#define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_M (EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_V << EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_S)
-#define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_V 0x00000001
-#define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_S 2
-
-/* EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA : R/W; bitpos: [1]; default: 0;
- * The bit is used to enable the interrupt by icache pre-load done.
- */
-
-#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA (BIT(1))
-#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_M (EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_V << EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_S)
-#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_V 0x00000001
-#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_S 1
-
-/* EXTMEM_PRO_ICACHE_PRELOAD_INT_ST : RO; bitpos: [0]; default: 0;
- * The bit is used to indicate the interrupt by icache pre-load done.
- */
-
-#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST (BIT(0))
-#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_M (EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_V << EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_S)
-#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_V 0x00000001
-#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_S 0
-
-/* EXTMEM_CACHE_SYNC_INT_CTRL_REG register
- * register description
- */
-
-#define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x130)
-
-/* EXTMEM_PRO_DCACHE_SYNC_INT_CLR : WOD; bitpos: [5]; default: 0;
- * The bit is used to clear the interrupt by dcache sync done.
- */
-
-#define EXTMEM_PRO_DCACHE_SYNC_INT_CLR (BIT(5))
-#define EXTMEM_PRO_DCACHE_SYNC_INT_CLR_M (EXTMEM_PRO_DCACHE_SYNC_INT_CLR_V << EXTMEM_PRO_DCACHE_SYNC_INT_CLR_S)
-#define EXTMEM_PRO_DCACHE_SYNC_INT_CLR_V 0x00000001
-#define EXTMEM_PRO_DCACHE_SYNC_INT_CLR_S 5
-
-/* EXTMEM_PRO_DCACHE_SYNC_INT_ENA : R/W; bitpos: [4]; default: 0;
- * The bit is used to enable the interrupt by dcache sync done.
- */
-
-#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA (BIT(4))
-#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA_M (EXTMEM_PRO_DCACHE_SYNC_INT_ENA_V << EXTMEM_PRO_DCACHE_SYNC_INT_ENA_S)
-#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA_V 0x00000001
-#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA_S 4
-
-/* EXTMEM_PRO_DCACHE_SYNC_INT_ST : RO; bitpos: [3]; default: 0;
- * The bit is used to indicate the interrupt by dcache sync done.
- */
-
-#define EXTMEM_PRO_DCACHE_SYNC_INT_ST (BIT(3))
-#define EXTMEM_PRO_DCACHE_SYNC_INT_ST_M (EXTMEM_PRO_DCACHE_SYNC_INT_ST_V << EXTMEM_PRO_DCACHE_SYNC_INT_ST_S)
-#define EXTMEM_PRO_DCACHE_SYNC_INT_ST_V 0x00000001
-#define EXTMEM_PRO_DCACHE_SYNC_INT_ST_S 3
-
-/* EXTMEM_PRO_ICACHE_SYNC_INT_CLR : WOD; bitpos: [2]; default: 0;
- * The bit is used to clear the interrupt by icache sync done.
- */
-
-#define EXTMEM_PRO_ICACHE_SYNC_INT_CLR (BIT(2))
-#define EXTMEM_PRO_ICACHE_SYNC_INT_CLR_M (EXTMEM_PRO_ICACHE_SYNC_INT_CLR_V << EXTMEM_PRO_ICACHE_SYNC_INT_CLR_S)
-#define EXTMEM_PRO_ICACHE_SYNC_INT_CLR_V 0x00000001
-#define EXTMEM_PRO_ICACHE_SYNC_INT_CLR_S 2
-
-/* EXTMEM_PRO_ICACHE_SYNC_INT_ENA : R/W; bitpos: [1]; default: 0;
- * The bit is used to enable the interrupt by icache sync done.
- */
-
-#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA (BIT(1))
-#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA_M (EXTMEM_PRO_ICACHE_SYNC_INT_ENA_V << EXTMEM_PRO_ICACHE_SYNC_INT_ENA_S)
-#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA_V 0x00000001
-#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA_S 1
-
-/* EXTMEM_PRO_ICACHE_SYNC_INT_ST : RO; bitpos: [0]; default: 0;
- * The bit is used to indicate the interrupt by icache sync done.
- */
-
-#define EXTMEM_PRO_ICACHE_SYNC_INT_ST (BIT(0))
-#define EXTMEM_PRO_ICACHE_SYNC_INT_ST_M (EXTMEM_PRO_ICACHE_SYNC_INT_ST_V << EXTMEM_PRO_ICACHE_SYNC_INT_ST_S)
-#define EXTMEM_PRO_ICACHE_SYNC_INT_ST_V 0x00000001
-#define EXTMEM_PRO_ICACHE_SYNC_INT_ST_S 0
-
-/* EXTMEM_CACHE_CONF_MISC_REG register
- * register description
- */
-
-#define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0x134)
-
-/* EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W; bitpos: [1]; default:
- * 1;
- * The bit is used to disable checking mmu entry fault by sync operation.
- */
-
-#define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1))
-#define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V << EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S)
-#define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x00000001
-#define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1
-
-/* EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W; bitpos: [0];
- * default: 1;
- * The bit is used to disable checking mmu entry fault by preload operation.
- */
-
-#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0))
-#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V << EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S)
-#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x00000001
-#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0
-
-/* EXTMEM_CLOCK_GATE_REG register
- * register description
- */
-
-#define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x138)
-
-/* EXTMEM_CLK_EN : R/W; bitpos: [0]; default: 1;
- * Reserved.
- */
-
-#define EXTMEM_CLK_EN (BIT(0))
-#define EXTMEM_CLK_EN_M (EXTMEM_CLK_EN_V << EXTMEM_CLK_EN_S)
-#define EXTMEM_CLK_EN_V 0x00000001
-#define EXTMEM_CLK_EN_S 0
-
-/* EXTMEM_PRO_EXTMEM_REG_DATE_REG register
- * register description
- */
-
-#define EXTMEM_PRO_EXTMEM_REG_DATE_REG (DR_REG_EXTMEM_BASE + 0x3fc)
-
-/* EXTMEM_PRO_EXTMEM_REG_DATE : R/W; bitpos: [27:0]; default: 26231168;
- * Reserved.
- */
-
-#define EXTMEM_PRO_EXTMEM_REG_DATE 0x0fffffff
-#define EXTMEM_PRO_EXTMEM_REG_DATE_M (EXTMEM_PRO_EXTMEM_REG_DATE_V << EXTMEM_PRO_EXTMEM_REG_DATE_S)
-#define EXTMEM_PRO_EXTMEM_REG_DATE_V 0x0fffffff
-#define EXTMEM_PRO_EXTMEM_REG_DATE_S 0
-
-#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_EXTMEM_H */
diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h
index aa0c30cd1f..453b087018 100644
--- a/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h
+++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h
@@ -29,161 +29,15 @@
#include <stdbool.h>
#include "xtensa.h"
-#include "xtensa_attr.h"
#include <nuttx/bits.h>
+#include "soc/soc.h"
+#include "esp_attr.h"
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
-/* Register Bits */
-
-#define BIT31 0x80000000
-#define BIT30 0x40000000
-#define BIT29 0x20000000
-#define BIT28 0x10000000
-#define BIT27 0x08000000
-#define BIT26 0x04000000
-#define BIT25 0x02000000
-#define BIT24 0x01000000
-#define BIT23 0x00800000
-#define BIT22 0x00400000
-#define BIT21 0x00200000
-#define BIT20 0x00100000
-#define BIT19 0x00080000
-#define BIT18 0x00040000
-#define BIT17 0x00020000
-#define BIT16 0x00010000
-#define BIT15 0x00008000
-#define BIT14 0x00004000
-#define BIT13 0x00002000
-#define BIT12 0x00001000
-#define BIT11 0x00000800
-#define BIT10 0x00000400
-#define BIT9 0x00000200
-#define BIT8 0x00000100
-#define BIT7 0x00000080
-#define BIT6 0x00000040
-#define BIT5 0x00000020
-#define BIT4 0x00000010
-#define BIT3 0x00000008
-#define BIT2 0x00000004
-#define BIT1 0x00000002
-#define BIT0 0x00000001
-
-#define PRO_CPU_NUM (0)
-
-#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) /* Largest span of contiguous memory (DRAM or IRAM) in the address space */
-
-/* Registers Operation */
-
-#define ETS_UNCACHED_ADDR(addr) (addr)
-#define ETS_CACHED_ADDR(addr) (addr)
-
-/* Write value to register */
-
-#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
-
-/* Read value from register */
-
-#define REG_READ(_r) (*(volatile uint32_t *)(_r))
-
-/* Get bit or get bits from register */
-
-#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b))
-
-/* Set bit or set bits to register */
-
-#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
-
-/* Clear bit or clear bits of register */
-
-#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
-
-/* Set bits of register controlled by mask */
-
-#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
-
-/* Get field from register,
- * used when _f is not left shifted by _f##_S
- */
-
-#define REG_GET_FIELD(addr, field) ((getreg32(addr) >> (field##_S)) & (field##_V))
-
-/* Set field to register,
- * used when _f is not left shifted by _f##_S
- */
-
-#define REG_SET_FIELD(addr, field, val) (modifyreg32((addr), (field##_M), (((uint32_t) val) & (field##_V)) << (field##_S)))
-
-/* Set field value from a variable,
- * used when _f is not left shifted by _f##_S
- */
-
-#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
-
-/* Get field value from a variable,
- * used when _f is left shifted by _f##_S
- */
-
-#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
-
-/* Set field value to a variable,
- * used when _f is not left shifted by _f##_S
- */
-
-#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
-
-/* Set field value to a variable,
- * used when _f is left shifted by _f##_S
- */
-
-#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
-
-/* Generate a value from a field value,
- * used when _f is not left shifted by _f##_S
- */
-
-#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
-
-/* Generate a value from a field value,
- * used when _f is left shifted by _f##_S
- */
-
-#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
-
-/* Read value from register */
-
-#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
-
-/* Write value to register */
-
-#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
-
-/* Clear bits of register controlled by mask */
-
-#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
-
-/* Set bits of register controlled by mask */
-
-#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
-
-/* Get bits of register controlled by mask */
-
-#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask))
-
-/* Get bits of register controlled by highest bit and lowest bit */
-
-#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
-
-/* Set bits of register controlled by mask and shift */
-
-#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
-
-/* Get field of register */
-
-#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask))
-
/* Extract the field from the register and shift it to avoid wrong reading */
#define REG_MASK(_reg, _field) ((_reg & (_field##_M)) >> (_field##_S))
@@ -192,118 +46,11 @@
#define VALUE_TO_FIELD(_value, _field) (((_value) << (_field##_S)) & (_field##_M))
-/* Periheral Clock */
-
-#define APB_CLK_FREQ_ROM 40 * 1000000
-#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
-#define UART_CLK_FREQ_ROM APB_CLK_FREQ_ROM
-#define CPU_CLK_FREQ APB_CLK_FREQ
-#define APB_CLK_FREQ 80 * 1000000 /* Unit: Hz */
-#define REF_CLK_FREQ (1000000)
-#define UART_CLK_FREQ APB_CLK_FREQ
-#define MWDT_CLK_FREQ APB_CLK_FREQ
-#define TIMER_CLK_FREQ (80000000 >> 4) /* 80MHz divided by 16 */
-#define SPI_CLK_DIV 4
-#define TICKS_PER_US_ROM 40 /* CPU is 80MHz */
-
-#define DR_REG_SYSTEM_BASE 0x3f4c0000
-#define DR_REG_SENSITIVE_BASE 0x3f4c1000
-#define DR_REG_INTERRUPT_BASE 0x3f4c2000
-#define DR_REG_DMA_COPY_BASE 0x3f4c3000
-#define DR_REG_EXTMEM_BASE 0x61800000
-#define DR_REG_MMU_TABLE 0x61801000
-#define DR_REG_ITAG_TABLE 0x61802000
-#define DR_REG_DTAG_TABLE 0x61803000
-#define DR_REG_AES_BASE 0x6003a000
-#define DR_REG_SHA_BASE 0x6003b000
-#define DR_REG_RSA_BASE 0x6003c000
-#define DR_REG_HMAC_BASE 0x6003e000
-#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000
-#define DR_REG_CRYPTO_DMA_BASE 0x6003f000
-#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000
-#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000
-#define DR_REG_INTRUSION_BASE 0x3f4d0000
-#define DR_REG_DPORT_END 0x3f4d3FFC
-#define DR_REG_UART_BASE 0x3f400000
-#define DR_REG_SPI1_BASE 0x3f402000
-#define DR_REG_SPI0_BASE 0x3f403000
-#define DR_REG_GPIO_BASE 0x3f404000
-#define DR_REG_GPIO_SD_BASE 0x3f404f00
-#define DR_REG_FE2_BASE 0x3f405000
-#define DR_REG_FE_BASE 0x3f406000
-#define DR_REG_FRC_TIMER_BASE 0x3f407000
-#define DR_REG_RTCCNTL_BASE 0x3f408000
-#define DR_REG_RTCIO_BASE 0x3f408400
-#define DR_REG_SENS_BASE 0x3f408800
-#define DR_REG_RTC_I2C_BASE 0x3f408C00
-#define DR_REG_IO_MUX_BASE 0x3f409000
-#define DR_REG_HINF_BASE 0x3f40B000
-#define DR_REG_I2S_BASE 0x3f40F000
-#define DR_REG_UART1_BASE 0x3f410000
-#define DR_REG_I2C_EXT_BASE 0x3f413000
-#define DR_REG_UHCI0_BASE 0x3f414000
-#define DR_REG_SLCHOST_BASE 0x3f415000
-#define DR_REG_RMT_BASE 0x3f416000
-#define DR_REG_PCNT_BASE 0x3f417000
-#define DR_REG_SLC_BASE 0x3f418000
-#define DR_REG_LEDC_BASE 0x3f419000
-#define DR_REG_CP_BASE 0x3f4c3000
-#define DR_REG_EFUSE_BASE 0x3f41A000
-#define DR_REG_NRX_BASE 0x3f41CC00
-#define DR_REG_BB_BASE 0x3f41D000
-#define DR_REG_TIMERGROUP0_BASE 0x3f41F000
-#define DR_REG_TIMERGROUP1_BASE 0x3f420000
-#define DR_REG_RTC_SLOWMEM_BASE 0x3f421000
-#define DR_REG_SYSTIMER_BASE 0x3f423000
-#define DR_REG_SPI2_BASE 0x3f424000
-#define DR_REG_SPI3_BASE 0x3f425000
-#define DR_REG_SYSCON_BASE 0x3f426000
-#define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */
-#define DR_REG_I2C1_EXT_BASE 0x3f427000
-#define DR_REG_SPI4_BASE 0x3f437000
-#define DR_REG_USB_WRAP_BASE 0x3f439000
-#define DR_REG_APB_SARADC_BASE 0x3f440000
-#define DR_REG_TWAI_BASE 0x6002B000
-#define DR_REG_USB_BASE 0x60080000
-
-#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE)
-#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000 )
-#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 )
-#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
-#define REG_I2S_BASE(i) (DR_REG_I2S_BASE)
-#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000)
-#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
-#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
-
-#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i) > 3) ? ((((i) - 2) * 0x1000) + 0x10000) : (((i) - 2) * 0x1000)))
-
/* Registers Operation */
+#define DR_REG_TWAI_BASE 0x6002B000
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 )
-/* Overall memory map */
-
-#define SOC_DROM_LOW 0x3f000000 /* drom0 low address for icache */
-#define SOC_DROM_HIGH 0x3ff80000 /* dram0 high address for dcache */
-#define SOC_IROM_LOW 0x40080000
-#define SOC_IROM_HIGH 0x40800000
-#define SOC_IROM_MASK_LOW 0x40000000
-#define SOC_IROM_MASK_HIGH 0x40020000
-#define SOC_IRAM_LOW 0x40020000
-#define SOC_IRAM_HIGH 0x40070000
-#define SOC_DRAM_LOW 0x3ffb0000
-#define SOC_DRAM_HIGH 0x40000000
-#define SOC_RTC_IRAM_LOW 0x40070000
-#define SOC_RTC_IRAM_HIGH 0x40072000
-#define SOC_RTC_DRAM_LOW 0x3ff9e000
-#define SOC_RTC_DRAM_HIGH 0x3ffa0000
-#define SOC_RTC_DATA_LOW 0x50000000
-#define SOC_RTC_DATA_HIGH 0x50002000
-#define SOC_EXTRAM_DATA_LOW 0x3f500000
-#define SOC_EXTRAM_DATA_HIGH 0x3ff80000
-
-#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
-
/* Virtual address 0 */
#define VADDR0_START_ADDR SOC_DROM_LOW
@@ -317,59 +64,6 @@
#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c)
#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038)
-/* Interrupt cpu using table */
-
-/****************************************************************************
- *Intr num Level Type PRO CPU usage APP CPU uasge
- * 0 1 extern level WMAC Reserved
- * 1 1 extern level BT/BLE Host VHCI Reserved
- * 2 1 extern level FROM_CPU FROM_CPU
- * 3 1 extern level TG0_WDT Reserved
- * 4 1 extern level WBB
- * 5 1 extern level BT Controller
- * 6 1 timer RTOS Tick RTOS Tick
- * 7 1 software Reserved Reserved
- * 8 1 extern level BLE Controller
- * 9 1 extern level
- * 10 1 extern edge Internal Timer
- * 11 3 profiling
- * 12 1 extern level
- * 13 1 extern level
- * 14 7 nmi Reserved Reserved
- * 15 3 timer Internal Timer
- * 16 5 timer
- * 17 1 extern level
- * 18 1 extern level
- * 19 2 extern level
- * 20 2 extern level
- * 21 2 extern level
- * 22 3 extern edge
- * 23 3 extern level
- * 24 4 extern level
- * 25 4 extern level Reserved Reserved
- * 26 5 extern level Reserved Reserved
- * 27 3 extern level Reserved Reserved
- * 28 4 extern edge
- * 29 3 software Reserved Reserved
- * 30 4 extern edge Reserved Reserved
- * 31 5 extern level Reserved Reserved
- ****************************************************************************/
-
-/* CPU0 Interrupt number reserved, not touch this. */
-
-#define ETS_WMAC_INUM 0
-#define ETS_BT_HOST_INUM 1
-#define ETS_FROM_CPU_INUM 2
-#define ETS_T0_WDT_INUM 3
-#define ETS_WBB_INUM 4
-#define ETS_TG0_T1_INUM 10 /* Use edge interrupt */
-
-/* CPU0 Interrupt number used in ROM, should be cancelled in SDK */
-
-#define ETS_SLC_INUM 1
-#define ETS_UART0_INUM 5
-#define ETS_UART1_INUM 5
-
/* Other interrupt numbers should be managed by the user */
#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0)
diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_spi.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_spi.h
index cb948e6764..3ca3718962 100644
--- a/arch/xtensa/src/esp32s2/hardware/esp32s2_spi.h
+++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_spi.h
@@ -26,2856 +26,12 @@
****************************************************************************/
#include "esp32s2_soc.h"
+#include "soc/spi_reg.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
-/* SPI_CMD_REG register */
-
-#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
-
-/* SPI_USR : R/W; bitpos: [24]; default: 0;
- * User define command enable. An operation will be triggered when the bit
- * is set. The bit will be cleared once the operation done.1: enable 0:
- * disable. Can not be changed by CONF_buf.
- */
-
-#define SPI_USR (BIT(24))
-#define SPI_USR_M (SPI_USR_V << SPI_USR_S)
-#define SPI_USR_V 0x00000001
-#define SPI_USR_S 24
-
-/* SPI_CONF_BITLEN : R/W; bitpos: [22:0]; default: 104;
- * Define the spi_clk cycles of SPI_CONF state.
- */
-
-#define SPI_CONF_BITLEN 0x007FFFFF
-#define SPI_CONF_BITLEN_M (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S)
-#define SPI_CONF_BITLEN_V 0x007FFFFF
-#define SPI_CONF_BITLEN_S 0
-
-/* SPI_ADDR_REG register */
-
-#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)
-
-/* SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
- * [31:8]:address to slave, [7:0]:Reserved.
- */
-
-#define SPI_USR_ADDR_VALUE 0xFFFFFFFF
-#define SPI_USR_ADDR_VALUE_M (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S)
-#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF
-#define SPI_USR_ADDR_VALUE_S 0
-
-/* SPI_CTRL_REG register */
-
-#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)
-
-/* SPI_WR_BIT_ORDER : R/W; bitpos: [26]; default: 0;
- * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first
- */
-
-#define SPI_WR_BIT_ORDER (BIT(26))
-#define SPI_WR_BIT_ORDER_M (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S)
-#define SPI_WR_BIT_ORDER_V 0x00000001
-#define SPI_WR_BIT_ORDER_S 26
-
-/* SPI_RD_BIT_ORDER : R/W; bitpos: [25]; default: 0;
- * In read-data (MISO) phase 1: LSB first 0: MSB first
- */
-
-#define SPI_RD_BIT_ORDER (BIT(25))
-#define SPI_RD_BIT_ORDER_M (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S)
-#define SPI_RD_BIT_ORDER_V 0x00000001
-#define SPI_RD_BIT_ORDER_S 25
-
-/* SPI_WP_REG : R/W; bitpos: [21]; default: 1;
- * Write protect signal output when SPI is idle. 1: output high, 0: output
- * low.
- */
-
-#define SPI_WP_REG (BIT(21))
-#define SPI_WP_REG_M (SPI_WP_REG_V << SPI_WP_REG_S)
-#define SPI_WP_REG_V 0x00000001
-#define SPI_WP_REG_S 21
-
-/* SPI_D_POL : R/W; bitpos: [19]; default: 1;
- * The bit is used to set MOSI line polarity, 1: high 0, low
- */
-
-#define SPI_D_POL (BIT(19))
-#define SPI_D_POL_M (SPI_D_POL_V << SPI_D_POL_S)
-#define SPI_D_POL_V 0x00000001
-#define SPI_D_POL_S 19
-
-/* SPI_Q_POL : R/W; bitpos: [18]; default: 1;
- * The bit is used to set MISO line polarity, 1: high 0, low
- */
-
-#define SPI_Q_POL (BIT(18))
-#define SPI_Q_POL_M (SPI_Q_POL_V << SPI_Q_POL_S)
-#define SPI_Q_POL_V 0x00000001
-#define SPI_Q_POL_S 18
-
-/* SPI_FREAD_OCT : R/W; bitpos: [16]; default: 0;
- * In the read operations read-data phase apply 8 signals. 1: enable 0:
- * disable.
- */
-
-#define SPI_FREAD_OCT (BIT(16))
-#define SPI_FREAD_OCT_M (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S)
-#define SPI_FREAD_OCT_V 0x00000001
-#define SPI_FREAD_OCT_S 16
-
-/* SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0;
- * In the read operations read-data phase apply 4 signals. 1: enable 0:
- * disable.
- */
-
-#define SPI_FREAD_QUAD (BIT(15))
-#define SPI_FREAD_QUAD_M (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S)
-#define SPI_FREAD_QUAD_V 0x00000001
-#define SPI_FREAD_QUAD_S 15
-
-/* SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
- * In the read operations, read-data phase apply 2 signals. 1: enable 0:
- * disable.
- */
-
-#define SPI_FREAD_DUAL (BIT(14))
-#define SPI_FREAD_DUAL_M (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S)
-#define SPI_FREAD_DUAL_V 0x00000001
-#define SPI_FREAD_DUAL_S 14
-
-/* SPI_FCMD_OCT : R/W; bitpos: [10]; default: 0;
- * Apply 8 signals during command phase 1:enable 0: disable
- */
-
-#define SPI_FCMD_OCT (BIT(10))
-#define SPI_FCMD_OCT_M (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S)
-#define SPI_FCMD_OCT_V 0x00000001
-#define SPI_FCMD_OCT_S 10
-
-/* SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0;
- * Apply 4 signals during command phase 1:enable 0: disable
- */
-
-#define SPI_FCMD_QUAD (BIT(9))
-#define SPI_FCMD_QUAD_M (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S)
-#define SPI_FCMD_QUAD_V 0x00000001
-#define SPI_FCMD_QUAD_S 9
-
-/* SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0;
- * Apply 2 signals during command phase 1:enable 0: disable
- */
-
-#define SPI_FCMD_DUAL (BIT(8))
-#define SPI_FCMD_DUAL_M (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S)
-#define SPI_FCMD_DUAL_V 0x00000001
-#define SPI_FCMD_DUAL_S 8
-
-/* SPI_FADDR_OCT : R/W; bitpos: [7]; default: 0;
- * Apply 8 signals during addr phase 1:enable 0: disable
- */
-
-#define SPI_FADDR_OCT (BIT(7))
-#define SPI_FADDR_OCT_M (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S)
-#define SPI_FADDR_OCT_V 0x00000001
-#define SPI_FADDR_OCT_S 7
-
-/* SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0;
- * Apply 4 signals during addr phase 1:enable 0: disable
- */
-
-#define SPI_FADDR_QUAD (BIT(6))
-#define SPI_FADDR_QUAD_M (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S)
-#define SPI_FADDR_QUAD_V 0x00000001
-#define SPI_FADDR_QUAD_S 6
-
-/* SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
- * Apply 2 signals during addr phase 1:enable 0: disable
- */
-
-#define SPI_FADDR_DUAL (BIT(5))
-#define SPI_FADDR_DUAL_M (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S)
-#define SPI_FADDR_DUAL_V 0x00000001
-#define SPI_FADDR_DUAL_S 5
-
-/* SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
- * In the dummy phase the signal level of spi is output by the spi
- * controller.
- */
-
-#define SPI_DUMMY_OUT (BIT(3))
-#define SPI_DUMMY_OUT_M (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S)
-#define SPI_DUMMY_OUT_V 0x00000001
-#define SPI_DUMMY_OUT_S 3
-
-/* SPI_EXT_HOLD_EN : R/W; bitpos: [2]; default: 0;
- * Set the bit to hold spi. The bit is combined with
- * spi_usr_prep_hold,spi_usr_cmd_hold,spi_usr_addr_hold, spi_usr_dummy_hold,
- * spi_usr_din_hold,spi_usr_dout_hold and spi_usr_hold_pol.
- */
-
-#define SPI_EXT_HOLD_EN (BIT(2))
-#define SPI_EXT_HOLD_EN_M (SPI_EXT_HOLD_EN_V << SPI_EXT_HOLD_EN_S)
-#define SPI_EXT_HOLD_EN_V 0x00000001
-#define SPI_EXT_HOLD_EN_S 2
-
-/* SPI_CTRL1_REG register */
-
-#define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0xc)
-
-/* SPI_CS_HOLD_DELAY : R/W; bitpos: [19:14]; default: 1;
- * SPI cs signal is delayed by spi clock cycles.
- */
-
-#define SPI_CS_HOLD_DELAY 0x0000003F
-#define SPI_CS_HOLD_DELAY_M (SPI_CS_HOLD_DELAY_V << SPI_CS_HOLD_DELAY_S)
-#define SPI_CS_HOLD_DELAY_V 0x0000003F
-#define SPI_CS_HOLD_DELAY_S 14
-
-/* SPI_W16_17_WR_ENA : R/W; bitpos: [4]; default: 1;
- * 1:reg_buf[16] [17] can be written 0:reg_buf[16] [17] can not be
- * written.
- */
-
-#define SPI_W16_17_WR_ENA (BIT(4))
-#define SPI_W16_17_WR_ENA_M (SPI_W16_17_WR_ENA_V << SPI_W16_17_WR_ENA_S)
-#define SPI_W16_17_WR_ENA_V 0x00000001
-#define SPI_W16_17_WR_ENA_S 4
-
-/* SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0;
- * It saves half a cycle when tsck is the same as rsck. 1: output data at
- * rsck posedge 0: output data at tsck posedge
- */
-
-#define SPI_RSCK_DATA_OUT (BIT(3))
-#define SPI_RSCK_DATA_OUT_M (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S)
-#define SPI_RSCK_DATA_OUT_V 0x00000001
-#define SPI_RSCK_DATA_OUT_S 3
-
-/* SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0;
- * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data
- * B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data
- * B[1]/B[6].
- */
-
-#define SPI_CLK_MODE_13 (BIT(2))
-#define SPI_CLK_MODE_13_M (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S)
-#define SPI_CLK_MODE_13_V 0x00000001
-#define SPI_CLK_MODE_13_S 2
-
-/* SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
- * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is
- * delayed one cycle after CS inactive 2: SPI clock is delayed two cycles
- * after CS inactive 3: SPI clock is alwasy on.
- */
-
-#define SPI_CLK_MODE 0x00000003
-#define SPI_CLK_MODE_M (SPI_CLK_MODE_V << SPI_CLK_MODE_S)
-#define SPI_CLK_MODE_V 0x00000003
-#define SPI_CLK_MODE_S 0
-
-/* SPI_CTRL2_REG register */
-
-#define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x10)
-
-/* SPI_CS_DELAY_NUM : R/W; bitpos: [30:29]; default: 0;
- * spi_cs signal is delayed by system clock cycles
- */
-
-#define SPI_CS_DELAY_NUM 0x00000003
-#define SPI_CS_DELAY_NUM_M (SPI_CS_DELAY_NUM_V << SPI_CS_DELAY_NUM_S)
-#define SPI_CS_DELAY_NUM_V 0x00000003
-#define SPI_CS_DELAY_NUM_S 29
-
-/* SPI_CS_DELAY_MODE : R/W; bitpos: [28:26]; default: 0;
- * spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or
- * spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle
- * 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle,
- * else delayed by half cycle 3: delayed one cycle
- */
-
-#define SPI_CS_DELAY_MODE 0x00000007
-#define SPI_CS_DELAY_MODE_M (SPI_CS_DELAY_MODE_V << SPI_CS_DELAY_MODE_S)
-#define SPI_CS_DELAY_MODE_V 0x00000007
-#define SPI_CS_DELAY_MODE_S 26
-
-/* SPI_CS_HOLD_TIME : R/W; bitpos: [25:13]; default: 1;
- * delay cycles of cs pin by spi clock this bits are combined with
- * spi_cs_hold bit.
- */
-
-#define SPI_CS_HOLD_TIME 0x00001FFF
-#define SPI_CS_HOLD_TIME_M (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S)
-#define SPI_CS_HOLD_TIME_V 0x00001FFF
-#define SPI_CS_HOLD_TIME_S 13
-
-/* SPI_CS_SETUP_TIME : R/W; bitpos: [12:0]; default: 1;
- * (cycles-1) of prepare phase by spi clock this bits are combined with
- * spi_cs_setup bit.
- */
-
-#define SPI_CS_SETUP_TIME 0x00001FFF
-#define SPI_CS_SETUP_TIME_M (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S)
-#define SPI_CS_SETUP_TIME_V 0x00001FFF
-#define SPI_CS_SETUP_TIME_S 0
-
-/* SPI_CLOCK_REG register */
-
-#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x14)
-
-/* SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
- * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided
- * from system clock.
- */
-
-#define SPI_CLK_EQU_SYSCLK (BIT(31))
-#define SPI_CLK_EQU_SYSCLK_M (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S)
-#define SPI_CLK_EQU_SYSCLK_V 0x00000001
-#define SPI_CLK_EQU_SYSCLK_S 31
-
-/* SPI_CLKDIV_PRE : R/W; bitpos: [30:18]; default: 0;
- * In the master mode it is pre-divider of spi_clk.
- */
-
-#define SPI_CLKDIV_PRE 0x00001FFF
-#define SPI_CLKDIV_PRE_M (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S)
-#define SPI_CLKDIV_PRE_V 0x00001FFF
-#define SPI_CLKDIV_PRE_S 18
-
-/* SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3;
- * In the master mode it is the divider of spi_clk. So spi_clk frequency is
- * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)
- */
-
-#define SPI_CLKCNT_N 0x0000003F
-#define SPI_CLKCNT_N_M (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S)
-#define SPI_CLKCNT_N_V 0x0000003F
-#define SPI_CLKCNT_N_S 12
-
-/* SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1;
- * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave
- * mode it must be 0.
- */
-
-#define SPI_CLKCNT_H 0x0000003F
-#define SPI_CLKCNT_H_M (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S)
-#define SPI_CLKCNT_H_V 0x0000003F
-#define SPI_CLKCNT_H_S 6
-
-/* SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
- * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it
- * must be 0.
- */
-
-#define SPI_CLKCNT_L 0x0000003F
-#define SPI_CLKCNT_L_M (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S)
-#define SPI_CLKCNT_L_V 0x0000003F
-#define SPI_CLKCNT_L_S 0
-
-/* SPI_USER_REG register */
-
-#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x18)
-
-/* SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1;
- * This bit enable the command phase of an operation.
- */
-
-#define SPI_USR_COMMAND (BIT(31))
-#define SPI_USR_COMMAND_M (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S)
-#define SPI_USR_COMMAND_V 0x00000001
-#define SPI_USR_COMMAND_S 31
-
-/* SPI_USR_ADDR : R/W; bitpos: [30]; default: 0;
- * This bit enable the address phase of an operation.
- */
-
-#define SPI_USR_ADDR (BIT(30))
-#define SPI_USR_ADDR_M (SPI_USR_ADDR_V << SPI_USR_ADDR_S)
-#define SPI_USR_ADDR_V 0x00000001
-#define SPI_USR_ADDR_S 30
-
-/* SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0;
- * This bit enable the dummy phase of an operation.
- */
-
-#define SPI_USR_DUMMY (BIT(29))
-#define SPI_USR_DUMMY_M (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S)
-#define SPI_USR_DUMMY_V 0x00000001
-#define SPI_USR_DUMMY_S 29
-
-/* SPI_USR_MISO : R/W; bitpos: [28]; default: 0;
- * This bit enable the read-data phase of an operation.
- */
-
-#define SPI_USR_MISO (BIT(28))
-#define SPI_USR_MISO_M (SPI_USR_MISO_V << SPI_USR_MISO_S)
-#define SPI_USR_MISO_V 0x00000001
-#define SPI_USR_MISO_S 28
-
-/* SPI_USR_MOSI : R/W; bitpos: [27]; default: 0;
- * This bit enable the write-data phase of an operation.
- */
-
-#define SPI_USR_MOSI (BIT(27))
-#define SPI_USR_MOSI_M (SPI_USR_MOSI_V << SPI_USR_MOSI_S)
-#define SPI_USR_MOSI_V 0x00000001
-#define SPI_USR_MOSI_S 27
-
-/* SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
- * spi clock is disable in dummy phase when the bit is enable.
- */
-
-#define SPI_USR_DUMMY_IDLE (BIT(26))
-#define SPI_USR_DUMMY_IDLE_M (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S)
-#define SPI_USR_DUMMY_IDLE_V 0x00000001
-#define SPI_USR_DUMMY_IDLE_S 26
-
-/* SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
- * write-data phase only access to high-part of the buffer spi_w8~spi_w15.
- * 1: enable 0: disable.
- */
-
-#define SPI_USR_MOSI_HIGHPART (BIT(25))
-#define SPI_USR_MOSI_HIGHPART_M (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S)
-#define SPI_USR_MOSI_HIGHPART_V 0x00000001
-#define SPI_USR_MOSI_HIGHPART_S 25
-
-/* SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
- * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1:
- * enable 0: disable.
- */
-
-#define SPI_USR_MISO_HIGHPART (BIT(24))
-#define SPI_USR_MISO_HIGHPART_M (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S)
-#define SPI_USR_MISO_HIGHPART_V 0x00000001
-#define SPI_USR_MISO_HIGHPART_S 24
-
-/* SPI_USR_PREP_HOLD : R/W; bitpos: [23]; default: 0;
- * spi is hold at prepare state the bit are combined with spi_usr_hold_pol
- * bit.
- */
-
-#define SPI_USR_PREP_HOLD (BIT(23))
-#define SPI_USR_PREP_HOLD_M (SPI_USR_PREP_HOLD_V << SPI_USR_PREP_HOLD_S)
-#define SPI_USR_PREP_HOLD_V 0x00000001
-#define SPI_USR_PREP_HOLD_S 23
-
-/* SPI_USR_CMD_HOLD : R/W; bitpos: [22]; default: 0;
- * spi is hold at command state the bit are combined with spi_usr_hold_pol
- * bit.
- */
-
-#define SPI_USR_CMD_HOLD (BIT(22))
-#define SPI_USR_CMD_HOLD_M (SPI_USR_CMD_HOLD_V << SPI_USR_CMD_HOLD_S)
-#define SPI_USR_CMD_HOLD_V 0x00000001
-#define SPI_USR_CMD_HOLD_S 22
-
-/* SPI_USR_ADDR_HOLD : R/W; bitpos: [21]; default: 0;
- * spi is hold at address state the bit are combined with spi_usr_hold_pol
- * bit.
- */
-
-#define SPI_USR_ADDR_HOLD (BIT(21))
-#define SPI_USR_ADDR_HOLD_M (SPI_USR_ADDR_HOLD_V << SPI_USR_ADDR_HOLD_S)
-#define SPI_USR_ADDR_HOLD_V 0x00000001
-#define SPI_USR_ADDR_HOLD_S 21
-
-/* SPI_USR_DUMMY_HOLD : R/W; bitpos: [20]; default: 0;
- * spi is hold at dummy state the bit are combined with spi_usr_hold_pol bit.
- */
-
-#define SPI_USR_DUMMY_HOLD (BIT(20))
-#define SPI_USR_DUMMY_HOLD_M (SPI_USR_DUMMY_HOLD_V << SPI_USR_DUMMY_HOLD_S)
-#define SPI_USR_DUMMY_HOLD_V 0x00000001
-#define SPI_USR_DUMMY_HOLD_S 20
-
-/* SPI_USR_DIN_HOLD : R/W; bitpos: [19]; default: 0;
- * spi is hold at data in state the bit are combined with spi_usr_hold_pol
- * bit.
- */
-
-#define SPI_USR_DIN_HOLD (BIT(19))
-#define SPI_USR_DIN_HOLD_M (SPI_USR_DIN_HOLD_V << SPI_USR_DIN_HOLD_S)
-#define SPI_USR_DIN_HOLD_V 0x00000001
-#define SPI_USR_DIN_HOLD_S 19
-
-/* SPI_USR_DOUT_HOLD : R/W; bitpos: [18]; default: 0;
- * spi is hold at data out state the bit are combined with spi_usr_hold_pol
- * bit.
- */
-
-#define SPI_USR_DOUT_HOLD (BIT(18))
-#define SPI_USR_DOUT_HOLD_M (SPI_USR_DOUT_HOLD_V << SPI_USR_DOUT_HOLD_S)
-#define SPI_USR_DOUT_HOLD_V 0x00000001
-#define SPI_USR_DOUT_HOLD_S 18
-
-/* SPI_USR_HOLD_POL : R/W; bitpos: [17]; default: 0;
- * It is combined with hold bits to set the polarity of spi hold line 1: spi
- * will be held when spi hold line is high 0: spi will be held when spi hold
- * line is low
- */
-
-#define SPI_USR_HOLD_POL (BIT(17))
-#define SPI_USR_HOLD_POL_M (SPI_USR_HOLD_POL_V << SPI_USR_HOLD_POL_S)
-#define SPI_USR_HOLD_POL_V 0x00000001
-#define SPI_USR_HOLD_POL_S 17
-
-/* SPI_SIO : R/W; bitpos: [16]; default: 0;
- * Set the bit to enable 3-line half duplex communication mosi and miso
- * signals share the same pin. 1: enable 0: disable.
- */
-
-#define SPI_SIO (BIT(16))
-#define SPI_SIO_M (SPI_SIO_V << SPI_SIO_S)
-#define SPI_SIO_V 0x00000001
-#define SPI_SIO_S 16
-
-/* SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0;
- * 1: Enable the DMA CONF phase of next seg-trans operation, which means
- * seg-trans will continue. 0: The seg-trans will end after the current SPI
- * seg-trans or this is not seg-trans mode.
- */
-
-#define SPI_USR_CONF_NXT (BIT(15))
-#define SPI_USR_CONF_NXT_M (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S)
-#define SPI_USR_CONF_NXT_V 0x00000001
-#define SPI_USR_CONF_NXT_S 15
-
-/* SPI_FWRITE_OCT : R/W; bitpos: [14]; default: 0;
- * In the write operations read-data phase apply 8 signals
- */
-
-#define SPI_FWRITE_OCT (BIT(14))
-#define SPI_FWRITE_OCT_M (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S)
-#define SPI_FWRITE_OCT_V 0x00000001
-#define SPI_FWRITE_OCT_S 14
-
-/* SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
- * In the write operations read-data phase apply 4 signals
- */
-
-#define SPI_FWRITE_QUAD (BIT(13))
-#define SPI_FWRITE_QUAD_M (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S)
-#define SPI_FWRITE_QUAD_V 0x00000001
-#define SPI_FWRITE_QUAD_S 13
-
-/* SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
- * In the write operations read-data phase apply 2 signals
- */
-
-#define SPI_FWRITE_DUAL (BIT(12))
-#define SPI_FWRITE_DUAL_M (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S)
-#define SPI_FWRITE_DUAL_V 0x00000001
-#define SPI_FWRITE_DUAL_S 12
-
-/* SPI_WR_BYTE_ORDER : R/W; bitpos: [11]; default: 0;
- * In command address write-data (MOSI) phases 1: big-endian 0: litte_endian
- */
-
-#define SPI_WR_BYTE_ORDER (BIT(11))
-#define SPI_WR_BYTE_ORDER_M (SPI_WR_BYTE_ORDER_V << SPI_WR_BYTE_ORDER_S)
-#define SPI_WR_BYTE_ORDER_V 0x00000001
-#define SPI_WR_BYTE_ORDER_S 11
-
-/* SPI_RD_BYTE_ORDER : R/W; bitpos: [10]; default: 0;
- * In read-data (MISO) phase 1: big-endian 0: little_endian
- */
-
-#define SPI_RD_BYTE_ORDER (BIT(10))
-#define SPI_RD_BYTE_ORDER_M (SPI_RD_BYTE_ORDER_V << SPI_RD_BYTE_ORDER_S)
-#define SPI_RD_BYTE_ORDER_V 0x00000001
-#define SPI_RD_BYTE_ORDER_S 10
-
-/* SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
- * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay
- * mode.
- */
-
-#define SPI_CK_OUT_EDGE (BIT(9))
-#define SPI_CK_OUT_EDGE_M (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S)
-#define SPI_CK_OUT_EDGE_V 0x00000001
-#define SPI_CK_OUT_EDGE_S 9
-
-/* SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0;
- * In the slave mode, this bit can be used to change the polarity of rsck.
- * 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.
- */
-
-#define SPI_RSCK_I_EDGE (BIT(8))
-#define SPI_RSCK_I_EDGE_M (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S)
-#define SPI_RSCK_I_EDGE_V 0x00000001
-#define SPI_RSCK_I_EDGE_S 8
-
-/* SPI_CS_SETUP : R/W; bitpos: [7]; default: 0;
- * spi cs is enable when spi is in prepare phase. 1: enable 0: disable.
- */
-
-#define SPI_CS_SETUP (BIT(7))
-#define SPI_CS_SETUP_M (SPI_CS_SETUP_V << SPI_CS_SETUP_S)
-#define SPI_CS_SETUP_V 0x00000001
-#define SPI_CS_SETUP_S 7
-
-/* SPI_CS_HOLD : R/W; bitpos: [6]; default: 0;
- * spi cs keep low when spi is in done phase. 1: enable 0: disable.
- */
-
-#define SPI_CS_HOLD (BIT(6))
-#define SPI_CS_HOLD_M (SPI_CS_HOLD_V << SPI_CS_HOLD_S)
-#define SPI_CS_HOLD_V 0x00000001
-#define SPI_CS_HOLD_S 6
-
-/* SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0;
- * In the slave mode, this bit can be used to change the polarity of tsck.
- * 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.
- */
-
-#define SPI_TSCK_I_EDGE (BIT(5))
-#define SPI_TSCK_I_EDGE_M (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S)
-#define SPI_TSCK_I_EDGE_V 0x00000001
-#define SPI_TSCK_I_EDGE_S 5
-
-/* SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
- * Set the bit to enable full duplex communication. 1: enable 0: disable.
- */
-
-#define SPI_DOUTDIN (BIT(0))
-#define SPI_DOUTDIN_M (SPI_DOUTDIN_V << SPI_DOUTDIN_S)
-#define SPI_DOUTDIN_V 0x00000001
-#define SPI_DOUTDIN_S 0
-
-/* SPI_USER1_REG register */
-
-#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x1c)
-
-/* SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23;
- * The length in bits of address phase. The register value shall be
- * (bit_num-1).
- */
-
-#define SPI_USR_ADDR_BITLEN 0x0000001F
-#define SPI_USR_ADDR_BITLEN_M (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S)
-#define SPI_USR_ADDR_BITLEN_V 0x0000001F
-#define SPI_USR_ADDR_BITLEN_S 27
-
-/* SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
- * The length in spi_clk cycles of dummy phase. The register value shall be
- * (cycle_num-1).
- */
-
-#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
-#define SPI_USR_DUMMY_CYCLELEN_M (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S)
-#define SPI_USR_DUMMY_CYCLELEN_V 0x000000FF
-#define SPI_USR_DUMMY_CYCLELEN_S 0
-
-/* SPI_USER2_REG register */
-
-#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x20)
-
-/* SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
- * The length in bits of command phase. The register value shall be
- * (bit_num-1)
- */
-
-#define SPI_USR_COMMAND_BITLEN 0x0000000F
-#define SPI_USR_COMMAND_BITLEN_M (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S)
-#define SPI_USR_COMMAND_BITLEN_V 0x0000000F
-#define SPI_USR_COMMAND_BITLEN_S 28
-
-/* SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
- * The value of command.
- */
-
-#define SPI_USR_COMMAND_VALUE 0x0000FFFF
-#define SPI_USR_COMMAND_VALUE_M (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S)
-#define SPI_USR_COMMAND_VALUE_V 0x0000FFFF
-#define SPI_USR_COMMAND_VALUE_S 0
-
-/* SPI_MOSI_DLEN_REG register */
-
-#define SPI_MOSI_DLEN_REG(i) (REG_SPI_BASE(i) + 0x24)
-
-/* SPI_USR_MOSI_DBITLEN : R/W; bitpos: [22:0]; default: 0;
- * The length in bits of write-data. The register value shall be (bit_num-1).
- */
-
-#define SPI_USR_MOSI_DBITLEN 0x007FFFFF
-#define SPI_USR_MOSI_DBITLEN_M (SPI_USR_MOSI_DBITLEN_V << SPI_USR_MOSI_DBITLEN_S)
-#define SPI_USR_MOSI_DBITLEN_V 0x007FFFFF
-#define SPI_USR_MOSI_DBITLEN_S 0
-
-/* SPI_MISO_DLEN_REG register */
-
-#define SPI_MISO_DLEN_REG(i) (REG_SPI_BASE(i) + 0x28)
-
-/* SPI_USR_MISO_DBITLEN : R/W; bitpos: [22:0]; default: 0;
- * The length in bits of read-data. The register value shall be (bit_num-1).
- */
-
-#define SPI_USR_MISO_DBITLEN 0x007FFFFF
-#define SPI_USR_MISO_DBITLEN_M (SPI_USR_MISO_DBITLEN_V << SPI_USR_MISO_DBITLEN_S)
-#define SPI_USR_MISO_DBITLEN_V 0x007FFFFF
-#define SPI_USR_MISO_DBITLEN_S 0
-
-/* SPI_OPI_MODE : R/W; bitpos: [1]; default: 0;
- * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0:
- * others.
- */
-
-#define SPI_OPI_MODE (BIT(1))
-#define SPI_OPI_MODE_M (SPI_OPI_MODE_V << SPI_OPI_MODE_S)
-#define SPI_OPI_MODE_V 0x00000001
-#define SPI_OPI_MODE_S 1
-
-/* SPI_QPI_MODE : R/W; bitpos: [0]; default: 0;
- * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0:
- * others.
- */
-
-#define SPI_QPI_MODE (BIT(0))
-#define SPI_QPI_MODE_M (SPI_QPI_MODE_V << SPI_QPI_MODE_S)
-#define SPI_QPI_MODE_V 0x00000001
-#define SPI_QPI_MODE_S 0
-
-/* SPI_MISC_REG register */
-
-#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x2c)
-
-/* SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0;
- * 1: spi quad input swap enable 0: spi quad input swap disable
- */
-
-#define SPI_QUAD_DIN_PIN_SWAP (BIT(31))
-#define SPI_QUAD_DIN_PIN_SWAP_M (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S)
-#define SPI_QUAD_DIN_PIN_SWAP_V 0x00000001
-#define SPI_QUAD_DIN_PIN_SWAP_S 31
-
-/* SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0;
- * spi cs line keep low when the bit is set.
- */
-
-#define SPI_CS_KEEP_ACTIVE (BIT(30))
-#define SPI_CS_KEEP_ACTIVE_M (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S)
-#define SPI_CS_KEEP_ACTIVE_V 0x00000001
-#define SPI_CS_KEEP_ACTIVE_S 30
-
-/* SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0;
- * 1: spi clk line is high when idle 0: spi clk line is low when idle
- */
-
-#define SPI_CK_IDLE_EDGE (BIT(29))
-#define SPI_CK_IDLE_EDGE_M (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S)
-#define SPI_CK_IDLE_EDGE_V 0x00000001
-#define SPI_CK_IDLE_EDGE_S 29
-
-/* SPI_CD_IDLE_EDGE : R/W; bitpos: [26]; default: 0;
- * The default value of spi_cd.
- */
-
-#define SPI_CD_IDLE_EDGE (BIT(26))
-#define SPI_CD_IDLE_EDGE_M (SPI_CD_IDLE_EDGE_V << SPI_CD_IDLE_EDGE_S)
-#define SPI_CD_IDLE_EDGE_V 0x00000001
-#define SPI_CD_IDLE_EDGE_S 26
-
-/* SPI_CD_CMD_SET : R/W; bitpos: [25]; default: 0;
- * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_CMD state.
- * 0: spi_cd = spi_cd_idle_edge.
- */
-
-#define SPI_CD_CMD_SET (BIT(25))
-#define SPI_CD_CMD_SET_M (SPI_CD_CMD_SET_V << SPI_CD_CMD_SET_S)
-#define SPI_CD_CMD_SET_V 0x00000001
-#define SPI_CD_CMD_SET_S 25
-
-/* SPI_DQS_IDLE_EDGE : R/W; bitpos: [24]; default: 0;
- * The default value of spi_dqs.
- */
-
-#define SPI_DQS_IDLE_EDGE (BIT(24))
-#define SPI_DQS_IDLE_EDGE_M (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S)
-#define SPI_DQS_IDLE_EDGE_V 0x00000001
-#define SPI_DQS_IDLE_EDGE_S 24
-
-/* SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0;
- * spi slave input cs polarity select. 1: inv 0: not change
- */
-
-#define SPI_SLAVE_CS_POL (BIT(23))
-#define SPI_SLAVE_CS_POL_M (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S)
-#define SPI_SLAVE_CS_POL_V 0x00000001
-#define SPI_SLAVE_CS_POL_S 23
-
-/* SPI_CD_ADDR_SET : R/W; bitpos: [22]; default: 0;
- * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_ADDR state.
- * 0: spi_cd = spi_cd_idle_edge.
- */
-
-#define SPI_CD_ADDR_SET (BIT(22))
-#define SPI_CD_ADDR_SET_M (SPI_CD_ADDR_SET_V << SPI_CD_ADDR_SET_S)
-#define SPI_CD_ADDR_SET_V 0x00000001
-#define SPI_CD_ADDR_SET_S 22
-
-/* SPI_CD_DUMMY_SET : R/W; bitpos: [21]; default: 0;
- * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DUMMY state. 0:
- * spi_cd = spi_cd_idle_edge.
- */
-
-#define SPI_CD_DUMMY_SET (BIT(21))
-#define SPI_CD_DUMMY_SET_M (SPI_CD_DUMMY_SET_V << SPI_CD_DUMMY_SET_S)
-#define SPI_CD_DUMMY_SET_V 0x00000001
-#define SPI_CD_DUMMY_SET_S 21
-
-/* SPI_CD_DATA_SET : R/W; bitpos: [20]; default: 0;
- * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DOUT or SPI_DIN
- * state. 0: spi_cd = spi_cd_idle_edge.
- */
-
-#define SPI_CD_DATA_SET (BIT(20))
-#define SPI_CD_DATA_SET_M (SPI_CD_DATA_SET_V << SPI_CD_DATA_SET_S)
-#define SPI_CD_DATA_SET_V 0x00000001
-#define SPI_CD_DATA_SET_S 20
-
-/* SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0;
- * In the master mode the bits are the polarity of spi cs line, the value is
- * equivalent to spi_cs ^ spi_master_cs_pol.
- */
-
-#define SPI_MASTER_CS_POL 0x0000003F
-#define SPI_MASTER_CS_POL_M (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S)
-#define SPI_MASTER_CS_POL_V 0x0000003F
-#define SPI_MASTER_CS_POL_S 7
-
-/* SPI_CK_DIS : R/W; bitpos: [6]; default: 0;
- * 1: spi clk out disable, 0: spi clk out enable
- */
-
-#define SPI_CK_DIS (BIT(6))
-#define SPI_CK_DIS_M (SPI_CK_DIS_V << SPI_CK_DIS_S)
-#define SPI_CK_DIS_V 0x00000001
-#define SPI_CK_DIS_S 6
-
-/* SPI_CS5_DIS : R/W; bitpos: [5]; default: 1;
- * SPI CS5 pin enable, 1: disable CS5, 0: SPI_CS5 signal is from/to CS5 pin
- */
-
-#define SPI_CS5_DIS (BIT(5))
-#define SPI_CS5_DIS_M (SPI_CS5_DIS_V << SPI_CS5_DIS_S)
-#define SPI_CS5_DIS_V 0x00000001
-#define SPI_CS5_DIS_S 5
-
-/* SPI_CS4_DIS : R/W; bitpos: [4]; default: 1;
- * SPI CS4 pin enable, 1: disable CS4, 0: SPI_CS4 signal is from/to CS4 pin
- */
-
-#define SPI_CS4_DIS (BIT(4))
-#define SPI_CS4_DIS_M (SPI_CS4_DIS_V << SPI_CS4_DIS_S)
-#define SPI_CS4_DIS_V 0x00000001
-#define SPI_CS4_DIS_S 4
-
-/* SPI_CS3_DIS : R/W; bitpos: [3]; default: 1;
- * SPI CS3 pin enable, 1: disable CS3, 0: SPI_CS3 signal is from/to CS3 pin
- */
-
-#define SPI_CS3_DIS (BIT(3))
-#define SPI_CS3_DIS_M (SPI_CS3_DIS_V << SPI_CS3_DIS_S)
-#define SPI_CS3_DIS_V 0x00000001
-#define SPI_CS3_DIS_S 3
-
-/* SPI_CS2_DIS : R/W; bitpos: [2]; default: 1;
- * SPI CS2 pin enable, 1: disable CS2, 0: SPI_CS2 signal is from/to CS2 pin
- */
-
-#define SPI_CS2_DIS (BIT(2))
-#define SPI_CS2_DIS_M (SPI_CS2_DIS_V << SPI_CS2_DIS_S)
-#define SPI_CS2_DIS_V 0x00000001
-#define SPI_CS2_DIS_S 2
-
-/* SPI_CS1_DIS : R/W; bitpos: [1]; default: 1;
- * SPI CS1 pin enable, 1: disable CS1, 0: SPI_CS1 signal is from/to CS1 pin
- */
-
-#define SPI_CS1_DIS (BIT(1))
-#define SPI_CS1_DIS_M (SPI_CS1_DIS_V << SPI_CS1_DIS_S)
-#define SPI_CS1_DIS_V 0x00000001
-#define SPI_CS1_DIS_S 1
-
-/* SPI_CS0_DIS : R/W; bitpos: [0]; default: 1;
- * SPI CS0 pin enable, 1: disable CS0, 0: SPI_CS0 signal is from/to CS0 pin
- */
-
-#define SPI_CS0_DIS (BIT(0))
-#define SPI_CS0_DIS_M (SPI_CS0_DIS_V << SPI_CS0_DIS_S)
-#define SPI_CS0_DIS_V 0x00000001
-#define SPI_CS0_DIS_S 0
-
-/* SPI_SLAVE_REG register */
-
-#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x30)
-
-/* SPI_SOFT_RESET : R/W; bitpos: [31]; default: 0;
- * Software reset enable, reset the spi clock line cs line and data lines.
- */
-
-#define SPI_SOFT_RESET (BIT(31))
-#define SPI_SOFT_RESET_M (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S)
-#define SPI_SOFT_RESET_V 0x00000001
-#define SPI_SOFT_RESET_S 31
-
-/* SPI_SLAVE_MODE : R/W; bitpos: [30]; default: 0;
- * Set SPI work mode. 1: slave mode 0: master mode.
- */
-
-#define SPI_SLAVE_MODE (BIT(30))
-#define SPI_SLAVE_MODE_M (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S)
-#define SPI_SLAVE_MODE_V 0x00000001
-#define SPI_SLAVE_MODE_S 30
-
-/* SPI_TRANS_DONE_AUTO_CLR_EN : R/W; bitpos: [29]; default: 0;
- * spi_trans_done auto clear enable, clear it 3 apb cycles after the pos
- * edge of spi_trans_done. 0:disable. 1: enable.
- */
-
-#define SPI_TRANS_DONE_AUTO_CLR_EN (BIT(29))
-#define SPI_TRANS_DONE_AUTO_CLR_EN_M (SPI_TRANS_DONE_AUTO_CLR_EN_V << SPI_TRANS_DONE_AUTO_CLR_EN_S)
-#define SPI_TRANS_DONE_AUTO_CLR_EN_V 0x00000001
-#define SPI_TRANS_DONE_AUTO_CLR_EN_S 29
-
-/* SPI_TRANS_CNT : RO; bitpos: [26:23]; default: 0;
- * The operations counter in both the master mode and the slave mode.
- */
-
-#define SPI_TRANS_CNT 0x0000000F
-#define SPI_TRANS_CNT_M (SPI_TRANS_CNT_V << SPI_TRANS_CNT_S)
-#define SPI_TRANS_CNT_V 0x0000000F
-#define SPI_TRANS_CNT_S 23
-
-/* SPI_SEG_MAGIC_ERR_INT_EN : R/W; bitpos: [11]; default: 0;
- * 1: Enable seg magic value error interrupt. 0: Others
- */
-
-#define SPI_SEG_MAGIC_ERR_INT_EN (BIT(11))
-#define SPI_SEG_MAGIC_ERR_INT_EN_M (SPI_SEG_MAGIC_ERR_INT_EN_V << SPI_SEG_MAGIC_ERR_INT_EN_S)
-#define SPI_SEG_MAGIC_ERR_INT_EN_V 0x00000001
-#define SPI_SEG_MAGIC_ERR_INT_EN_S 11
-
-/* SPI_INT_DMA_SEG_TRANS_EN : R/W; bitpos: [10]; default: 0;
- * spi_dma_seg_trans_done Interrupt enable. 1: enable 0: disable
- */
-
-#define SPI_INT_DMA_SEG_TRANS_EN (BIT(10))
-#define SPI_INT_DMA_SEG_TRANS_EN_M (SPI_INT_DMA_SEG_TRANS_EN_V << SPI_INT_DMA_SEG_TRANS_EN_S)
-#define SPI_INT_DMA_SEG_TRANS_EN_V 0x00000001
-#define SPI_INT_DMA_SEG_TRANS_EN_S 10
-
-/* SPI_INT_TRANS_DONE_EN : R/W; bitpos: [9]; default: 1;
- * spi_trans_done Interrupt enable. 1: enable 0: disable
- */
-
-#define SPI_INT_TRANS_DONE_EN (BIT(9))
-#define SPI_INT_TRANS_DONE_EN_M (SPI_INT_TRANS_DONE_EN_V << SPI_INT_TRANS_DONE_EN_S)
-#define SPI_INT_TRANS_DONE_EN_V 0x00000001
-#define SPI_INT_TRANS_DONE_EN_S 9
-
-/* SPI_INT_WR_DMA_DONE_EN : R/W; bitpos: [8]; default: 0;
- * spi_slv_wr_dma Interrupt enable. 1: enable 0: disable
- */
-
-#define SPI_INT_WR_DMA_DONE_EN (BIT(8))
-#define SPI_INT_WR_DMA_DONE_EN_M (SPI_INT_WR_DMA_DONE_EN_V << SPI_INT_WR_DMA_DONE_EN_S)
-#define SPI_INT_WR_DMA_DONE_EN_V 0x00000001
-#define SPI_INT_WR_DMA_DONE_EN_S 8
-
-/* SPI_INT_RD_DMA_DONE_EN : R/W; bitpos: [7]; default: 0;
- * spi_slv_rd_dma Interrupt enable. 1: enable 0: disable
- */
-
-#define SPI_INT_RD_DMA_DONE_EN (BIT(7))
-#define SPI_INT_RD_DMA_DONE_EN_M (SPI_INT_RD_DMA_DONE_EN_V << SPI_INT_RD_DMA_DONE_EN_S)
-#define SPI_INT_RD_DMA_DONE_EN_V 0x00000001
-#define SPI_INT_RD_DMA_DONE_EN_S 7
-
-/* SPI_INT_WR_BUF_DONE_EN : R/W; bitpos: [6]; default: 0;
- * spi_slv_wr_buf Interrupt enable. 1: enable 0: disable
- */
-
-#define SPI_INT_WR_BUF_DONE_EN (BIT(6))
-#define SPI_INT_WR_BUF_DONE_EN_M (SPI_INT_WR_BUF_DONE_EN_V << SPI_INT_WR_BUF_DONE_EN_S)
-#define SPI_INT_WR_BUF_DONE_EN_V 0x00000001
-#define SPI_INT_WR_BUF_DONE_EN_S 6
-
-/* SPI_INT_RD_BUF_DONE_EN : R/W; bitpos: [5]; default: 0;
- * spi_slv_rd_buf Interrupt enable. 1: enable 0: disable
- */
-
-#define SPI_INT_RD_BUF_DONE_EN (BIT(5))
-#define SPI_INT_RD_BUF_DONE_EN_M (SPI_INT_RD_BUF_DONE_EN_V << SPI_INT_RD_BUF_DONE_EN_S)
-#define SPI_INT_RD_BUF_DONE_EN_V 0x00000001
-#define SPI_INT_RD_BUF_DONE_EN_S 5
-
-/* SPI_INT_EN : R/W ;bitpos:[11:5] ;default: 7'b001_0000 ; */
-
-/* Description: Interrupt enable bits for the 7 sources */
-
-#define SPI_INT_EN 0x0000007F
-#define SPI_INT_EN_M ((SPI_INT_EN_V)<<(SPI_INT_EN_S))
-#define SPI_INT_EN_V 0x7F
-#define SPI_INT_EN_S 5
-
-/* SPI_TRANS_DONE : R/W; bitpos: [4]; default: 0;
- * The interrupt raw bit for the completion of any operation in both the
- * master mode and the slave mode. Can not be changed by CONF_buf.
- */
-
-#define SPI_TRANS_DONE (BIT(4))
-#define SPI_TRANS_DONE_M (SPI_TRANS_DONE_V << SPI_TRANS_DONE_S)
-#define SPI_TRANS_DONE_V 0x00000001
-#define SPI_TRANS_DONE_S 4
-
-/* SPI_SLAVE1_REG register */
-
-#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x34)
-
-/* SPI_SLV_LAST_ADDR : R/W; bitpos: [31:24]; default: 0;
- * In the slave mode it is the value of address.
- */
-
-#define SPI_SLV_LAST_ADDR 0x000000FF
-#define SPI_SLV_LAST_ADDR_M (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S)
-#define SPI_SLV_LAST_ADDR_V 0x000000FF
-#define SPI_SLV_LAST_ADDR_S 24
-
-/* SPI_SLV_LAST_COMMAND : R/W; bitpos: [23:16]; default: 0;
- * In the slave mode it is the value of command.
- */
-
-#define SPI_SLV_LAST_COMMAND 0x000000FF
-#define SPI_SLV_LAST_COMMAND_M (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S)
-#define SPI_SLV_LAST_COMMAND_V 0x000000FF
-#define SPI_SLV_LAST_COMMAND_S 16
-
-/* SPI_SLV_WR_DMA_DONE : R/W; bitpos: [15]; default: 0;
- * The interrupt raw bit for the completion of dma write operation in the
- * slave mode. Can not be changed by CONF_buf.
- */
-
-#define SPI_SLV_WR_DMA_DONE (BIT(15))
-#define SPI_SLV_WR_DMA_DONE_M (SPI_SLV_WR_DMA_DONE_V << SPI_SLV_WR_DMA_DONE_S)
-#define SPI_SLV_WR_DMA_DONE_V 0x00000001
-#define SPI_SLV_WR_DMA_DONE_S 15
-
-/* SPI_SLV_CMD_ERR : R/W; bitpos: [14]; default: 0;
- * 1: The command value of the last SPI transfer is not supported by SPI
- * slave. 0: The command value is supported or no command value is received.
- */
-
-#define SPI_SLV_CMD_ERR (BIT(14))
-#define SPI_SLV_CMD_ERR_M (SPI_SLV_CMD_ERR_V << SPI_SLV_CMD_ERR_S)
-#define SPI_SLV_CMD_ERR_V 0x00000001
-#define SPI_SLV_CMD_ERR_S 14
-
-/* SPI_SLV_ADDR_ERR : R/W; bitpos: [13]; default: 0;
- * 1: The address value of the last SPI transfer is not supported by SPI
- * slave. 0: The address value is supported or no address value is received.
- */
-
-#define SPI_SLV_ADDR_ERR (BIT(13))
-#define SPI_SLV_ADDR_ERR_M (SPI_SLV_ADDR_ERR_V << SPI_SLV_ADDR_ERR_S)
-#define SPI_SLV_ADDR_ERR_V 0x00000001
-#define SPI_SLV_ADDR_ERR_S 13
-
-/* SPI_SLV_RD_DMA_DONE : R/W; bitpos: [8]; default: 0;
- * The interrupt raw bit for the completion of Rd-DMA operation in the slave
- * mode. Can not be changed by CONF_buf.
- */
-
-#define SPI_SLV_RD_DMA_DONE (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_M (SPI_SLV_RD_DMA_DONE_V << SPI_SLV_RD_DMA_DONE_S)
-#define SPI_SLV_RD_DMA_DONE_V 0x00000001
-#define SPI_SLV_RD_DMA_DONE_S 8
-
-/* SPI_SLV_WRBUF_DLEN_REG register */
-
-#define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x38)
-
-/* SPI_CONF_BASE_BITLEN : R/W; bitpos: [31:25]; default: 108;
- * The basic spi_clk cycles of CONF state. The real cycle length of CONF
- * state, if spi_usr_conf is enabled, is spi_conf_base_bitlen[6:0] +
- * spi_conf_bitlen[23:0].
- */
-
-#define SPI_CONF_BASE_BITLEN 0x0000007F
-#define SPI_CONF_BASE_BITLEN_M (SPI_CONF_BASE_BITLEN_V << SPI_CONF_BASE_BITLEN_S)
-#define SPI_CONF_BASE_BITLEN_V 0x0000007F
-#define SPI_CONF_BASE_BITLEN_S 25
-
-/* SPI_SLV_WR_BUF_DONE : R/W; bitpos: [24]; default: 0;
- * The interrupt raw bit for the completion of write-buffer operation in the
- * slave mode. Can not be changed by CONF_buf.
- */
-
-#define SPI_SLV_WR_BUF_DONE (BIT(24))
-#define SPI_SLV_WR_BUF_DONE_M (SPI_SLV_WR_BUF_DONE_V << SPI_SLV_WR_BUF_DONE_S)
-#define SPI_SLV_WR_BUF_DONE_V 0x00000001
-#define SPI_SLV_WR_BUF_DONE_S 24
-
-/* SPI_SLV_RDBUF_DLEN_REG register */
-
-#define SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x3c)
-
-/* SPI_SEG_MAGIC_ERR : R/W; bitpos: [25]; default: 0;
- * 1: The recent magic value in CONF buffer is not right in master DMA
- * seg-trans mode. 0: others.
- */
-
-#define SPI_SEG_MAGIC_ERR (BIT(25))
-#define SPI_SEG_MAGIC_ERR_M (SPI_SEG_MAGIC_ERR_V << SPI_SEG_MAGIC_ERR_S)
-#define SPI_SEG_MAGIC_ERR_V 0x00000001
-#define SPI_SEG_MAGIC_ERR_S 25
-
-/* SPI_SLV_RD_BUF_DONE : R/W; bitpos: [24]; default: 0;
- * The interrupt raw bit for the completion of read-buffer operation in the
- * slave mode. Can not be changed by CONF_buf.
- */
-
-#define SPI_SLV_RD_BUF_DONE (BIT(24))
-#define SPI_SLV_RD_BUF_DONE_M (SPI_SLV_RD_BUF_DONE_V << SPI_SLV_RD_BUF_DONE_S)
-#define SPI_SLV_RD_BUF_DONE_V 0x00000001
-#define SPI_SLV_RD_BUF_DONE_S 24
-
-/* SPI_SLV_DMA_RD_BYTELEN : R/W; bitpos: [19:0]; default: 0;
- * In the slave mode it is the length in bytes for read operations. The
- * register value shall be byte_num.
- */
-
-#define SPI_SLV_DMA_RD_BYTELEN 0x000FFFFF
-#define SPI_SLV_DMA_RD_BYTELEN_M (SPI_SLV_DMA_RD_BYTELEN_V << SPI_SLV_DMA_RD_BYTELEN_S)
-#define SPI_SLV_DMA_RD_BYTELEN_V 0x000FFFFF
-#define SPI_SLV_DMA_RD_BYTELEN_S 0
-
-/* SPI_SLV_RD_BYTE_REG register */
-
-#define SPI_SLV_RD_BYTE_REG(i) (REG_SPI_BASE(i) + 0x40)
-
-/* SPI_USR_CONF : R/W; bitpos: [31]; default: 0;
- * 1: Enable the DMA CONF phase of current seg-trans operation, which means
- * seg-trans will start. 0: This is not seg-trans mode.
- */
-
-#define SPI_USR_CONF (BIT(31))
-#define SPI_USR_CONF_M (SPI_USR_CONF_V << SPI_USR_CONF_S)
-#define SPI_USR_CONF_V 0x00000001
-#define SPI_USR_CONF_S 31
-
-/* SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [29:24]; default: 23;
- * The magic value of BM table in master DMA seg-trans.
- */
-
-#define SPI_DMA_SEG_MAGIC_VALUE 0x0000003F
-#define SPI_DMA_SEG_MAGIC_VALUE_M (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S)
-#define SPI_DMA_SEG_MAGIC_VALUE_V 0x0000003F
-#define SPI_DMA_SEG_MAGIC_VALUE_S 24
-
-/* SPI_SLV_WRBUF_BYTELEN_EN : R/W; bitpos: [23]; default: 0;
- * 1: spi_slv_data_bytelen stores data byte length of master-write-to-slave
- * data length in CPU controlled mode(Wr_BUF). 0: others
- */
-
-#define SPI_SLV_WRBUF_BYTELEN_EN (BIT(23))
-#define SPI_SLV_WRBUF_BYTELEN_EN_M (SPI_SLV_WRBUF_BYTELEN_EN_V << SPI_SLV_WRBUF_BYTELEN_EN_S)
-#define SPI_SLV_WRBUF_BYTELEN_EN_V 0x00000001
-#define SPI_SLV_WRBUF_BYTELEN_EN_S 23
-
-/* SPI_SLV_RDBUF_BYTELEN_EN : R/W; bitpos: [22]; default: 0;
- * 1: spi_slv_data_bytelen stores data byte length of master-read-slave data
- * length in CPU controlled mode(Rd_BUF). 0: others
- */
-
-#define SPI_SLV_RDBUF_BYTELEN_EN (BIT(22))
-#define SPI_SLV_RDBUF_BYTELEN_EN_M (SPI_SLV_RDBUF_BYTELEN_EN_V << SPI_SLV_RDBUF_BYTELEN_EN_S)
-#define SPI_SLV_RDBUF_BYTELEN_EN_V 0x00000001
-#define SPI_SLV_RDBUF_BYTELEN_EN_S 22
-
-/* SPI_SLV_WRDMA_BYTELEN_EN : R/W; bitpos: [21]; default: 0;
- * 1: spi_slv_data_bytelen stores data byte length of master-write-to-slave
- * data length in DMA controlled mode(Wr_DMA). 0: others
- */
-
-#define SPI_SLV_WRDMA_BYTELEN_EN (BIT(21))
-#define SPI_SLV_WRDMA_BYTELEN_EN_M (SPI_SLV_WRDMA_BYTELEN_EN_V << SPI_SLV_WRDMA_BYTELEN_EN_S)
-#define SPI_SLV_WRDMA_BYTELEN_EN_V 0x00000001
-#define SPI_SLV_WRDMA_BYTELEN_EN_S 21
-
-/* SPI_SLV_RDDMA_BYTELEN_EN : R/W; bitpos: [20]; default: 0;
- * 1: spi_slv_data_bytelen stores data byte length of master-read-slave data
- * length in DMA controlled mode(Rd_DMA). 0: others
- */
-
-#define SPI_SLV_RDDMA_BYTELEN_EN (BIT(20))
-#define SPI_SLV_RDDMA_BYTELEN_EN_M (SPI_SLV_RDDMA_BYTELEN_EN_V << SPI_SLV_RDDMA_BYTELEN_EN_S)
-#define SPI_SLV_RDDMA_BYTELEN_EN_V 0x00000001
-#define SPI_SLV_RDDMA_BYTELEN_EN_S 20
-
-/* SPI_SLV_DATA_BYTELEN : R/W; bitpos: [19:0]; default: 0;
- * The full-duplex or half-duplex data byte length of the last SPI transfer
- * in slave mode. In half-duplex mode, this value is controlled by bits
- * [23:20].
- */
-
-#define SPI_SLV_DATA_BYTELEN 0x000FFFFF
-#define SPI_SLV_DATA_BYTELEN_M (SPI_SLV_DATA_BYTELEN_V << SPI_SLV_DATA_BYTELEN_S)
-#define SPI_SLV_DATA_BYTELEN_V 0x000FFFFF
-#define SPI_SLV_DATA_BYTELEN_S 0
-
-/* SPI_FSM_REG register */
-
-#define SPI_FSM_REG(i) (REG_SPI_BASE(i) + 0x44)
-
-/* SPI_MST_DMA_RD_BYTELEN : R/W; bitpos: [31:12]; default: 0;
- * Define the master DMA read byte length in non seg-trans or seg-trans
- * mode. Invalid when spi_rx_eof_en is 0.
- */
-
-#define SPI_MST_DMA_RD_BYTELEN 0x000FFFFF
-#define SPI_MST_DMA_RD_BYTELEN_M (SPI_MST_DMA_RD_BYTELEN_V << SPI_MST_DMA_RD_BYTELEN_S)
-#define SPI_MST_DMA_RD_BYTELEN_V 0x000FFFFF
-#define SPI_MST_DMA_RD_BYTELEN_S 12
-
-/* SPI_ST : RO; bitpos: [3:0]; default: 0;
- * The status of spi state machine. 0: idle state, 1: preparation state, 2:
- * send command state, 3: send data state, 4: red data state, 5:write data
- * state, 6: wait state, 7: done state.
- */
-
-#define SPI_ST 0x0000000F
-#define SPI_ST_M (SPI_ST_V << SPI_ST_S)
-#define SPI_ST_V 0x0000000F
-#define SPI_ST_S 0
-
-/* SPI_HOLD_REG register */
-
-#define SPI_HOLD_REG(i) (REG_SPI_BASE(i) + 0x48)
-
-/* SPI_DMA_SEG_TRANS_DONE : R/W; bitpos: [7]; default: 0;
- * 1: spi master DMA full-duplex/half-duplex seg-trans ends or slave
- * half-duplex seg-trans ends. And data has been pushed to corresponding
- * memory. 0: seg-trans is not ended or not occurred. Can not be changed
- * by CONF_buf.
- */
-
-#define SPI_DMA_SEG_TRANS_DONE (BIT(7))
-#define SPI_DMA_SEG_TRANS_DONE_M (SPI_DMA_SEG_TRANS_DONE_V << SPI_DMA_SEG_TRANS_DONE_S)
-#define SPI_DMA_SEG_TRANS_DONE_V 0x00000001
-#define SPI_DMA_SEG_TRANS_DONE_S 7
-
-/* SPI_HOLD_OUT_TIME : R/W; bitpos: [6:4]; default: 0;
- * set the hold cycles of output spi_hold signal when spi_hold_out_en is
- * enable.
- */
-
-#define SPI_HOLD_OUT_TIME 0x00000007
-#define SPI_HOLD_OUT_TIME_M (SPI_HOLD_OUT_TIME_V << SPI_HOLD_OUT_TIME_S)
-#define SPI_HOLD_OUT_TIME_V 0x00000007
-#define SPI_HOLD_OUT_TIME_S 4
-
-/* SPI_HOLD_OUT_EN : R/W; bitpos: [3]; default: 0;
- * Enable set spi output hold value to spi_hold_reg. It can be used to hold
- * spi state machine with spi_ext_hold_en and other usr hold signals.
- */
-
-#define SPI_HOLD_OUT_EN (BIT(3))
-#define SPI_HOLD_OUT_EN_M (SPI_HOLD_OUT_EN_V << SPI_HOLD_OUT_EN_S)
-#define SPI_HOLD_OUT_EN_V 0x00000001
-#define SPI_HOLD_OUT_EN_S 3
-
-/* SPI_HOLD_VAL_REG : R/W; bitpos: [2]; default: 0;
- * spi hold output value, which should be used with spi_hold_out_en.
- */
-
-#define SPI_HOLD_VAL_REG (BIT(2))
-#define SPI_HOLD_VAL_REG_M (SPI_HOLD_VAL_REG_V << SPI_HOLD_VAL_REG_S)
-#define SPI_HOLD_VAL_REG_V 0x00000001
-#define SPI_HOLD_VAL_REG_S 2
-
-/* SPI_INT_HOLD_ENA : R/W; bitpos: [1:0]; default: 0;
- * This register is for two SPI masters to share the same cs clock and data
- * signals. The bits of one SPI are set, if the other SPI is busy, the SPI
- * will be hold. 1(3): hold at idle phase 2: hold at prepare phase.
- */
-
-#define SPI_INT_HOLD_ENA 0x00000003
-#define SPI_INT_HOLD_ENA_M (SPI_INT_HOLD_ENA_V << SPI_INT_HOLD_ENA_S)
-#define SPI_INT_HOLD_ENA_V 0x00000003
-#define SPI_INT_HOLD_ENA_S 0
-
-/* SPI_DMA_CONF_REG register */
-
-#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x4c)
-
-/* SPI_EXT_MEM_BK_SIZE : R/W; bitpos: [27:26]; default: 0;
- * Select the external memory block size.
- */
-
-#define SPI_EXT_MEM_BK_SIZE 0x00000003
-#define SPI_EXT_MEM_BK_SIZE_M (SPI_EXT_MEM_BK_SIZE_V << SPI_EXT_MEM_BK_SIZE_S)
-#define SPI_EXT_MEM_BK_SIZE_V 0x00000003
-#define SPI_EXT_MEM_BK_SIZE_S 26
-
-/* SPI_DMA_OUTFIFO_EMPTY_ERR : R/W; bitpos: [25]; default: 0;
- * 1:spi_dma_outfifo_empty and spi_pop_data_prep are valid, which means that
- * there is no data to pop but pop is valid. 0: Others. Can not be changed
- * by CONF_buf.
- */
-
-#define SPI_DMA_OUTFIFO_EMPTY_ERR (BIT(25))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_M (SPI_DMA_OUTFIFO_EMPTY_ERR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_V 0x00000001
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_S 25
-
-/* SPI_DMA_INFIFO_FULL_ERR : R/W; bitpos: [24]; default: 0;
- * 1:spi_dma_infifo_full and spi_push_data_prep are valid, which means that
- * DMA Rx buffer is full but push is valid. 0: Others. Can not be changed
- * by CONF_buf.
- */
-
-#define SPI_DMA_INFIFO_FULL_ERR (BIT(24))
-#define SPI_DMA_INFIFO_FULL_ERR_M (SPI_DMA_INFIFO_FULL_ERR_V << SPI_DMA_INFIFO_FULL_ERR_S)
-#define SPI_DMA_INFIFO_FULL_ERR_V 0x00000001
-#define SPI_DMA_INFIFO_FULL_ERR_S 24
-
-/* SPI_DMA_OUTFIFO_EMPTY_CLR : R/W; bitpos: [23]; default: 0;
- * 1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it.
- */
-
-#define SPI_DMA_OUTFIFO_EMPTY_CLR (BIT(23))
-#define SPI_DMA_OUTFIFO_EMPTY_CLR_M (SPI_DMA_OUTFIFO_EMPTY_CLR_V << SPI_DMA_OUTFIFO_EMPTY_CLR_S)
-#define SPI_DMA_OUTFIFO_EMPTY_CLR_V 0x00000001
-#define SPI_DMA_OUTFIFO_EMPTY_CLR_S 23
-
-/* SPI_DMA_INFIFO_FULL_CLR : R/W; bitpos: [22]; default: 0;
- * 1:Clear spi_dma_infifo_full_vld. 0: Do not control it.
- */
-
-#define SPI_DMA_INFIFO_FULL_CLR (BIT(22))
-#define SPI_DMA_INFIFO_FULL_CLR_M (SPI_DMA_INFIFO_FULL_CLR_V << SPI_DMA_INFIFO_FULL_CLR_S)
-#define SPI_DMA_INFIFO_FULL_CLR_V 0x00000001
-#define SPI_DMA_INFIFO_FULL_CLR_S 22
-
-/* SPI_REG_SPI_REG_RX_EOF_EN : R/W; bitpos: [21]; default: 0;
- * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is
- * equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma
- * transition. 0: spi_dma_inlink_eof is set by spi_trans_done in
- * non-seg-trans or spi_dma_seg_trans_done in seg-trans.
- */
-
-#define SPI_REG_SPI_REG_RX_EOF_EN (BIT(21))
-#define SPI_REG_SPI_REG_RX_EOF_EN_M (SPI_REG_SPI_REG_RX_EOF_EN_V << SPI_REG_SPI_REG_RX_EOF_EN_S)
-#define SPI_REG_SPI_REG_RX_EOF_EN_V 0x00000001
-#define SPI_REG_SPI_REG_RX_EOF_EN_S 21
-
-/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0;
- * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
- * spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
- */
-
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20))
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S)
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x00000001
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20
-
-/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0;
- * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
- * spi_dma_infifo_full_vld is cleared by spi_trans_done.
- */
-
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19))
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S)
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x00000001
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19
-
-/* SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0;
- * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0:
- * disable.
- */
-
-#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18))
-#define SPI_DMA_SLV_SEG_TRANS_EN_M (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S)
-#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x00000001
-#define SPI_DMA_SLV_SEG_TRANS_EN_S 18
-
-/* SPI_SLV_LAST_SEG_POP_CLR : R/W; bitpos: [17]; default: 0;
- * 1: Clear spi_slv_seg_frt_pop_mask. 0 : others
- */
-
-#define SPI_SLV_LAST_SEG_POP_CLR (BIT(17))
-#define SPI_SLV_LAST_SEG_POP_CLR_M (SPI_SLV_LAST_SEG_POP_CLR_V << SPI_SLV_LAST_SEG_POP_CLR_S)
-#define SPI_SLV_LAST_SEG_POP_CLR_V 0x00000001
-#define SPI_SLV_LAST_SEG_POP_CLR_S 17
-
-/* SPI_DMA_CONTINUE : R/W; bitpos: [16]; default: 0;
- * spi dma continue tx/rx data.
- */
-
-#define SPI_DMA_CONTINUE (BIT(16))
-#define SPI_DMA_CONTINUE_M (SPI_DMA_CONTINUE_V << SPI_DMA_CONTINUE_S)
-#define SPI_DMA_CONTINUE_V 0x00000001
-#define SPI_DMA_CONTINUE_S 16
-
-/* SPI_DMA_TX_STOP : R/W; bitpos: [15]; default: 0;
- * spi dma write data stop when in continue tx/rx mode.
- */
-
-#define SPI_DMA_TX_STOP (BIT(15))
-#define SPI_DMA_TX_STOP_M (SPI_DMA_TX_STOP_V << SPI_DMA_TX_STOP_S)
-#define SPI_DMA_TX_STOP_V 0x00000001
-#define SPI_DMA_TX_STOP_S 15
-
-/* SPI_REG_SPI_REG_DMA_RX_STOP : R/W; bitpos: [14]; default: 0;
- * spi dma read data stop when in continue tx/rx mode.
- */
-
-#define SPI_REG_SPI_REG_DMA_RX_STOP (BIT(14))
-#define SPI_REG_SPI_REG_DMA_RX_STOP_M (SPI_REG_SPI_REG_DMA_RX_STOP_V << SPI_REG_SPI_REG_DMA_RX_STOP_S)
-#define SPI_REG_SPI_REG_DMA_RX_STOP_V 0x00000001
-#define SPI_REG_SPI_REG_DMA_RX_STOP_S 14
-
-/* SPI_MEM_TRANS_EN : R/W; bitpos: [13]; default: 0;
- * DMA internal memory data transfer enable signal.
- */
-
-#define SPI_MEM_TRANS_EN (BIT(13))
-#define SPI_MEM_TRANS_EN_M (SPI_MEM_TRANS_EN_V << SPI_MEM_TRANS_EN_S)
-#define SPI_MEM_TRANS_EN_V 0x00000001
-#define SPI_MEM_TRANS_EN_S 13
-
-/* SPI_OUT_DATA_BURST_EN : R/W; bitpos: [12]; default: 0;
- * spi dma read data from memory in burst mode.
- */
-
-#define SPI_OUT_DATA_BURST_EN (BIT(12))
-#define SPI_OUT_DATA_BURST_EN_M (SPI_OUT_DATA_BURST_EN_V << SPI_OUT_DATA_BURST_EN_S)
-#define SPI_OUT_DATA_BURST_EN_V 0x00000001
-#define SPI_OUT_DATA_BURST_EN_S 12
-
-/* SPI_INDSCR_BURST_EN : R/W; bitpos: [11]; default: 0;
- * read descriptor use burst mode when write data to memory.
- */
-
-#define SPI_INDSCR_BURST_EN (BIT(11))
-#define SPI_INDSCR_BURST_EN_M (SPI_INDSCR_BURST_EN_V << SPI_INDSCR_BURST_EN_S)
-#define SPI_INDSCR_BURST_EN_V 0x00000001
-#define SPI_INDSCR_BURST_EN_S 11
-
-/* SPI_OUTDSCR_BURST_EN : R/W; bitpos: [10]; default: 0;
- * read descriptor use burst mode when read data for memory.
- */
-
-#define SPI_OUTDSCR_BURST_EN (BIT(10))
-#define SPI_OUTDSCR_BURST_EN_M (SPI_OUTDSCR_BURST_EN_V << SPI_OUTDSCR_BURST_EN_S)
-#define SPI_OUTDSCR_BURST_EN_V 0x00000001
-#define SPI_OUTDSCR_BURST_EN_S 10
-
-/* SPI_OUT_EOF_MODE : R/W; bitpos: [9]; default: 1;
- * out eof flag generation mode . 1: when dma pop all data from fifo 0:when
- * ahb push all data to fifo.
- */
-
-#define SPI_OUT_EOF_MODE (BIT(9))
-#define SPI_OUT_EOF_MODE_M (SPI_OUT_EOF_MODE_V << SPI_OUT_EOF_MODE_S)
-#define SPI_OUT_EOF_MODE_V 0x00000001
-#define SPI_OUT_EOF_MODE_S 9
-
-/* SPI_OUT_AUTO_WRBACK : R/W; bitpos: [8]; default: 0;
- * when the bit is set, DMA continue to use the next inlink node when the
- * length of inlink is 0.
- */
-
-#define SPI_OUT_AUTO_WRBACK (BIT(8))
-#define SPI_OUT_AUTO_WRBACK_M (SPI_OUT_AUTO_WRBACK_V << SPI_OUT_AUTO_WRBACK_S)
-#define SPI_OUT_AUTO_WRBACK_V 0x00000001
-#define SPI_OUT_AUTO_WRBACK_S 8
-
-/* SPI_OUT_LOOP_TEST : R/W; bitpos: [7]; default: 0;
- * Set bit to test out link.
- */
-
-#define SPI_OUT_LOOP_TEST (BIT(7))
-#define SPI_OUT_LOOP_TEST_M (SPI_OUT_LOOP_TEST_V << SPI_OUT_LOOP_TEST_S)
-#define SPI_OUT_LOOP_TEST_V 0x00000001
-#define SPI_OUT_LOOP_TEST_S 7
-
-/* SPI_IN_LOOP_TEST : R/W; bitpos: [6]; default: 0;
- * Set bit to test in link.
- */
-
-#define SPI_IN_LOOP_TEST (BIT(6))
-#define SPI_IN_LOOP_TEST_M (SPI_IN_LOOP_TEST_V << SPI_IN_LOOP_TEST_S)
-#define SPI_IN_LOOP_TEST_V 0x00000001
-#define SPI_IN_LOOP_TEST_S 6
-
-/* SPI_AHBM_RST : R/W; bitpos: [5]; default: 0;
- * Reset spi dma ahb master.
- */
-
-#define SPI_AHBM_RST (BIT(5))
-#define SPI_AHBM_RST_M (SPI_AHBM_RST_V << SPI_AHBM_RST_S)
-#define SPI_AHBM_RST_V 0x00000001
-#define SPI_AHBM_RST_S 5
-
-/* SPI_AHBM_FIFO_RST : R/W; bitpos: [4]; default: 0;
- * Reset spi dma ahb master fifo pointer.
- */
-
-#define SPI_AHBM_FIFO_RST (BIT(4))
-#define SPI_AHBM_FIFO_RST_M (SPI_AHBM_FIFO_RST_V << SPI_AHBM_FIFO_RST_S)
-#define SPI_AHBM_FIFO_RST_V 0x00000001
-#define SPI_AHBM_FIFO_RST_S 4
-
-/* SPI_OUT_RST : R/W; bitpos: [3]; default: 0;
- * The bit is used to reset out dma fsm and out data fifo pointer.
- */
-
-#define SPI_OUT_RST (BIT(3))
-#define SPI_OUT_RST_M (SPI_OUT_RST_V << SPI_OUT_RST_S)
-#define SPI_OUT_RST_V 0x00000001
-#define SPI_OUT_RST_S 3
-
-/* SPI_IN_RST : R/W; bitpos: [2]; default: 0;
- * The bit is used to reset in dma fsm and in data fifo pointer.
- */
-
-#define SPI_IN_RST (BIT(2))
-#define SPI_IN_RST_M (SPI_IN_RST_V << SPI_IN_RST_S)
-#define SPI_IN_RST_V 0x00000001
-#define SPI_IN_RST_S 2
-
-/* SPI_DMA_OUT_LINK_REG register */
-
-#define SPI_DMA_OUT_LINK_REG(i) (REG_SPI_BASE(i) + 0x50)
-
-/* SPI_DMA_TX_ENA : R/W; bitpos: [31]; default: 0;
- * spi dma write data status bit.
- */
-
-#define SPI_DMA_TX_ENA (BIT(31))
-#define SPI_DMA_TX_ENA_M (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S)
-#define SPI_DMA_TX_ENA_V 0x00000001
-#define SPI_DMA_TX_ENA_S 31
-
-/* SPI_OUTLINK_RESTART : R/W; bitpos: [30]; default: 0;
- * Set the bit to mount on new outlink descriptors.
- */
-
-#define SPI_OUTLINK_RESTART (BIT(30))
-#define SPI_OUTLINK_RESTART_M (SPI_OUTLINK_RESTART_V << SPI_OUTLINK_RESTART_S)
-#define SPI_OUTLINK_RESTART_V 0x00000001
-#define SPI_OUTLINK_RESTART_S 30
-
-/* SPI_OUTLINK_START : R/W; bitpos: [29]; default: 0;
- * Set the bit to start to use outlink descriptor.
- */
-
-#define SPI_OUTLINK_START (BIT(29))
-#define SPI_OUTLINK_START_M (SPI_OUTLINK_START_V << SPI_OUTLINK_START_S)
-#define SPI_OUTLINK_START_V 0x00000001
-#define SPI_OUTLINK_START_S 29
-
-/* SPI_OUTLINK_STOP : R/W; bitpos: [28]; default: 0;
- * Set the bit to stop to use outlink descriptor.
- */
-
-#define SPI_OUTLINK_STOP (BIT(28))
-#define SPI_OUTLINK_STOP_M (SPI_OUTLINK_STOP_V << SPI_OUTLINK_STOP_S)
-#define SPI_OUTLINK_STOP_V 0x00000001
-#define SPI_OUTLINK_STOP_S 28
-
-/* SPI_OUTLINK_ADDR : R/W; bitpos: [19:0]; default: 0;
- * The address of the first outlink descriptor.
- */
-
-#define SPI_OUTLINK_ADDR 0x000FFFFF
-#define SPI_OUTLINK_ADDR_M (SPI_OUTLINK_ADDR_V << SPI_OUTLINK_ADDR_S)
-#define SPI_OUTLINK_ADDR_V 0x000FFFFF
-#define SPI_OUTLINK_ADDR_S 0
-
-/* SPI_DMA_IN_LINK_REG register */
-
-#define SPI_DMA_IN_LINK_REG(i) (REG_SPI_BASE(i) + 0x54)
-
-/* SPI_DMA_RX_ENA : R/W; bitpos: [31]; default: 0;
- * spi dma read data status bit.
- */
-
-#define SPI_DMA_RX_ENA (BIT(31))
-#define SPI_DMA_RX_ENA_M (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S)
-#define SPI_DMA_RX_ENA_V 0x00000001
-#define SPI_DMA_RX_ENA_S 31
-
-/* SPI_INLINK_RESTART : R/W; bitpos: [30]; default: 0;
- * Set the bit to mount on new inlink descriptors.
- */
-
-#define SPI_INLINK_RESTART (BIT(30))
-#define SPI_INLINK_RESTART_M (SPI_INLINK_RESTART_V << SPI_INLINK_RESTART_S)
-#define SPI_INLINK_RESTART_V 0x00000001
-#define SPI_INLINK_RESTART_S 30
-
-/* SPI_INLINK_START : R/W; bitpos: [29]; default: 0;
- * Set the bit to start to use inlink descriptor.
- */
-
-#define SPI_INLINK_START (BIT(29))
-#define SPI_INLINK_START_M (SPI_INLINK_START_V << SPI_INLINK_START_S)
-#define SPI_INLINK_START_V 0x00000001
-#define SPI_INLINK_START_S 29
-
-/* SPI_INLINK_STOP : R/W; bitpos: [28]; default: 0;
- * Set the bit to stop to use inlink descriptor.
- */
-
-#define SPI_INLINK_STOP (BIT(28))
-#define SPI_INLINK_STOP_M (SPI_INLINK_STOP_V << SPI_INLINK_STOP_S)
-#define SPI_INLINK_STOP_V 0x00000001
-#define SPI_INLINK_STOP_S 28
-
-/* SPI_INLINK_AUTO_RET : R/W; bitpos: [20]; default: 0;
- * when the bit is set, the inlink descriptor returns to the first link node
- * when a packet is error.
- */
-
-#define SPI_INLINK_AUTO_RET (BIT(20))
-#define SPI_INLINK_AUTO_RET_M (SPI_INLINK_AUTO_RET_V << SPI_INLINK_AUTO_RET_S)
-#define SPI_INLINK_AUTO_RET_V 0x00000001
-#define SPI_INLINK_AUTO_RET_S 20
-
-/* SPI_INLINK_ADDR : R/W; bitpos: [19:0]; default: 0;
- * The address of the first inlink descriptor.
- */
-
-#define SPI_INLINK_ADDR 0x000FFFFF
-#define SPI_INLINK_ADDR_M (SPI_INLINK_ADDR_V << SPI_INLINK_ADDR_S)
-#define SPI_INLINK_ADDR_V 0x000FFFFF
-#define SPI_INLINK_ADDR_S 0
-
-/* SPI_DMA_INT_ENA_REG register */
-
-#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x58)
-
-/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W; bitpos: [8]; default: 0;
- * The enable bit for sending all the packets to host done.
- */
-
-#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8))
-#define SPI_OUT_TOTAL_EOF_INT_ENA_M (SPI_OUT_TOTAL_EOF_INT_ENA_V << SPI_OUT_TOTAL_EOF_INT_ENA_S)
-#define SPI_OUT_TOTAL_EOF_INT_ENA_V 0x00000001
-#define SPI_OUT_TOTAL_EOF_INT_ENA_S 8
-
-/* SPI_OUT_EOF_INT_ENA : R/W; bitpos: [7]; default: 0;
- * The enable bit for sending a packet to host done.
- */
-
-#define SPI_OUT_EOF_INT_ENA (BIT(7))
-#define SPI_OUT_EOF_INT_ENA_M (SPI_OUT_EOF_INT_ENA_V << SPI_OUT_EOF_INT_ENA_S)
-#define SPI_OUT_EOF_INT_ENA_V 0x00000001
-#define SPI_OUT_EOF_INT_ENA_S 7
-
-/* SPI_OUT_DONE_INT_ENA : R/W; bitpos: [6]; default: 0;
- * The enable bit for completing usage of a outlink descriptor .
- */
-
-#define SPI_OUT_DONE_INT_ENA (BIT(6))
-#define SPI_OUT_DONE_INT_ENA_M (SPI_OUT_DONE_INT_ENA_V << SPI_OUT_DONE_INT_ENA_S)
-#define SPI_OUT_DONE_INT_ENA_V 0x00000001
-#define SPI_OUT_DONE_INT_ENA_S 6
-
-/* SPI_IN_SUC_EOF_INT_ENA : R/W; bitpos: [5]; default: 0;
- * The enable bit for completing receiving all the packets from host.
- */
-
-#define SPI_IN_SUC_EOF_INT_ENA (BIT(5))
-#define SPI_IN_SUC_EOF_INT_ENA_M (SPI_IN_SUC_EOF_INT_ENA_V << SPI_IN_SUC_EOF_INT_ENA_S)
-#define SPI_IN_SUC_EOF_INT_ENA_V 0x00000001
-#define SPI_IN_SUC_EOF_INT_ENA_S 5
-
-/* SPI_IN_ERR_EOF_INT_ENA : R/W; bitpos: [4]; default: 0;
- * The enable bit for receiving error.
- */
-
-#define SPI_IN_ERR_EOF_INT_ENA (BIT(4))
-#define SPI_IN_ERR_EOF_INT_ENA_M (SPI_IN_ERR_EOF_INT_ENA_V << SPI_IN_ERR_EOF_INT_ENA_S)
-#define SPI_IN_ERR_EOF_INT_ENA_V 0x00000001
-#define SPI_IN_ERR_EOF_INT_ENA_S 4
-
-/* SPI_IN_DONE_INT_ENA : R/W; bitpos: [3]; default: 0;
- * The enable bit for completing usage of a inlink descriptor.
- */
-
-#define SPI_IN_DONE_INT_ENA (BIT(3))
-#define SPI_IN_DONE_INT_ENA_M (SPI_IN_DONE_INT_ENA_V << SPI_IN_DONE_INT_ENA_S)
-#define SPI_IN_DONE_INT_ENA_V 0x00000001
-#define SPI_IN_DONE_INT_ENA_S 3
-
-/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W; bitpos: [2]; default: 0;
- * The enable bit for inlink descriptor error.
- */
-
-#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2))
-#define SPI_INLINK_DSCR_ERROR_INT_ENA_M (SPI_INLINK_DSCR_ERROR_INT_ENA_V << SPI_INLINK_DSCR_ERROR_INT_ENA_S)
-#define SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x00000001
-#define SPI_INLINK_DSCR_ERROR_INT_ENA_S 2
-
-/* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0;
- * The enable bit for outlink descriptor error.
- */
-
-#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1))
-#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (SPI_OUTLINK_DSCR_ERROR_INT_ENA_V << SPI_OUTLINK_DSCR_ERROR_INT_ENA_S)
-#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x00000001
-#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1
-
-/* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
- * The enable bit for lack of enough inlink descriptors.
- */
-
-#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0))
-#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (SPI_INLINK_DSCR_EMPTY_INT_ENA_V << SPI_INLINK_DSCR_EMPTY_INT_ENA_S)
-#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x00000001
-#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0
-
-/* SPI_DMA_INT_RAW_REG register */
-
-#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x5c)
-
-/* SPI_OUT_TOTAL_EOF_INT_RAW : RO; bitpos: [8]; default: 0;
- * The raw bit for sending all the packets to host done.
- */
-
-#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8))
-#define SPI_OUT_TOTAL_EOF_INT_RAW_M (SPI_OUT_TOTAL_EOF_INT_RAW_V << SPI_OUT_TOTAL_EOF_INT_RAW_S)
-#define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x00000001
-#define SPI_OUT_TOTAL_EOF_INT_RAW_S 8
-
-/* SPI_OUT_EOF_INT_RAW : RO; bitpos: [7]; default: 0;
- * The raw bit for sending a packet to host done.
- */
-
-#define SPI_OUT_EOF_INT_RAW (BIT(7))
-#define SPI_OUT_EOF_INT_RAW_M (SPI_OUT_EOF_INT_RAW_V << SPI_OUT_EOF_INT_RAW_S)
-#define SPI_OUT_EOF_INT_RAW_V 0x00000001
-#define SPI_OUT_EOF_INT_RAW_S 7
-
-/* SPI_OUT_DONE_INT_RAW : RO; bitpos: [6]; default: 0;
- * The raw bit for completing usage of a outlink descriptor.
- */
-
-#define SPI_OUT_DONE_INT_RAW (BIT(6))
-#define SPI_OUT_DONE_INT_RAW_M (SPI_OUT_DONE_INT_RAW_V << SPI_OUT_DONE_INT_RAW_S)
-#define SPI_OUT_DONE_INT_RAW_V 0x00000001
-#define SPI_OUT_DONE_INT_RAW_S 6
-
-/* SPI_IN_SUC_EOF_INT_RAW : RO; bitpos: [5]; default: 0;
- * The raw bit for completing receiving all the packets from host.
- */
-
-#define SPI_IN_SUC_EOF_INT_RAW (BIT(5))
-#define SPI_IN_SUC_EOF_INT_RAW_M (SPI_IN_SUC_EOF_INT_RAW_V << SPI_IN_SUC_EOF_INT_RAW_S)
-#define SPI_IN_SUC_EOF_INT_RAW_V 0x00000001
-#define SPI_IN_SUC_EOF_INT_RAW_S 5
-
-/* SPI_IN_ERR_EOF_INT_RAW : RO; bitpos: [4]; default: 0;
- * The raw bit for receiving error.
- */
-
-#define SPI_IN_ERR_EOF_INT_RAW (BIT(4))
-#define SPI_IN_ERR_EOF_INT_RAW_M (SPI_IN_ERR_EOF_INT_RAW_V << SPI_IN_ERR_EOF_INT_RAW_S)
-#define SPI_IN_ERR_EOF_INT_RAW_V 0x00000001
-#define SPI_IN_ERR_EOF_INT_RAW_S 4
-
-/* SPI_IN_DONE_INT_RAW : RO; bitpos: [3]; default: 0;
- * The raw bit for completing usage of a inlink descriptor.
- */
-
-#define SPI_IN_DONE_INT_RAW (BIT(3))
-#define SPI_IN_DONE_INT_RAW_M (SPI_IN_DONE_INT_RAW_V << SPI_IN_DONE_INT_RAW_S)
-#define SPI_IN_DONE_INT_RAW_V 0x00000001
-#define SPI_IN_DONE_INT_RAW_S 3
-
-/* SPI_INLINK_DSCR_ERROR_INT_RAW : RO; bitpos: [2]; default: 0;
- * The raw bit for inlink descriptor error.
- */
-
-#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2))
-#define SPI_INLINK_DSCR_ERROR_INT_RAW_M (SPI_INLINK_DSCR_ERROR_INT_RAW_V << SPI_INLINK_DSCR_ERROR_INT_RAW_S)
-#define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x00000001
-#define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2
-
-/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO; bitpos: [1]; default: 0;
- * The raw bit for outlink descriptor error.
- */
-
-#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1))
-#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (SPI_OUTLINK_DSCR_ERROR_INT_RAW_V << SPI_OUTLINK_DSCR_ERROR_INT_RAW_S)
-#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x00000001
-#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1
-
-/* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO; bitpos: [0]; default: 0;
- * The raw bit for lack of enough inlink descriptors.
- */
-
-#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0))
-#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (SPI_INLINK_DSCR_EMPTY_INT_RAW_V << SPI_INLINK_DSCR_EMPTY_INT_RAW_S)
-#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x00000001
-#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0
-
-/* SPI_DMA_INT_ST_REG register */
-
-#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x60)
-
-/* SPI_OUT_TOTAL_EOF_INT_ST : RO; bitpos: [8]; default: 0;
- * The status bit for sending all the packets to host done.
- */
-
-#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8))
-#define SPI_OUT_TOTAL_EOF_INT_ST_M (SPI_OUT_TOTAL_EOF_INT_ST_V << SPI_OUT_TOTAL_EOF_INT_ST_S)
-#define SPI_OUT_TOTAL_EOF_INT_ST_V 0x00000001
-#define SPI_OUT_TOTAL_EOF_INT_ST_S 8
-
-/* SPI_OUT_EOF_INT_ST : RO; bitpos: [7]; default: 0;
- * The status bit for sending a packet to host done.
- */
-
-#define SPI_OUT_EOF_INT_ST (BIT(7))
-#define SPI_OUT_EOF_INT_ST_M (SPI_OUT_EOF_INT_ST_V << SPI_OUT_EOF_INT_ST_S)
-#define SPI_OUT_EOF_INT_ST_V 0x00000001
-#define SPI_OUT_EOF_INT_ST_S 7
-
-/* SPI_OUT_DONE_INT_ST : RO; bitpos: [6]; default: 0;
- * The status bit for completing usage of a outlink descriptor.
- */
-
-#define SPI_OUT_DONE_INT_ST (BIT(6))
-#define SPI_OUT_DONE_INT_ST_M (SPI_OUT_DONE_INT_ST_V << SPI_OUT_DONE_INT_ST_S)
-#define SPI_OUT_DONE_INT_ST_V 0x00000001
-#define SPI_OUT_DONE_INT_ST_S 6
-
-/* SPI_IN_SUC_EOF_INT_ST : RO; bitpos: [5]; default: 0;
- * The status bit for completing receiving all the packets from host.
- */
-
-#define SPI_IN_SUC_EOF_INT_ST (BIT(5))
-#define SPI_IN_SUC_EOF_INT_ST_M (SPI_IN_SUC_EOF_INT_ST_V << SPI_IN_SUC_EOF_INT_ST_S)
-#define SPI_IN_SUC_EOF_INT_ST_V 0x00000001
-#define SPI_IN_SUC_EOF_INT_ST_S 5
-
-/* SPI_IN_ERR_EOF_INT_ST : RO; bitpos: [4]; default: 0;
- * The status bit for receiving error.
- */
-
-#define SPI_IN_ERR_EOF_INT_ST (BIT(4))
-#define SPI_IN_ERR_EOF_INT_ST_M (SPI_IN_ERR_EOF_INT_ST_V << SPI_IN_ERR_EOF_INT_ST_S)
-#define SPI_IN_ERR_EOF_INT_ST_V 0x00000001
-#define SPI_IN_ERR_EOF_INT_ST_S 4
-
-/* SPI_IN_DONE_INT_ST : RO; bitpos: [3]; default: 0;
- * The status bit for completing usage of a inlink descriptor.
- */
-
-#define SPI_IN_DONE_INT_ST (BIT(3))
-#define SPI_IN_DONE_INT_ST_M (SPI_IN_DONE_INT_ST_V << SPI_IN_DONE_INT_ST_S)
-#define SPI_IN_DONE_INT_ST_V 0x00000001
-#define SPI_IN_DONE_INT_ST_S 3
-
-/* SPI_INLINK_DSCR_ERROR_INT_ST : RO; bitpos: [2]; default: 0;
- * The status bit for inlink descriptor error.
- */
-
-#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2))
-#define SPI_INLINK_DSCR_ERROR_INT_ST_M (SPI_INLINK_DSCR_ERROR_INT_ST_V << SPI_INLINK_DSCR_ERROR_INT_ST_S)
-#define SPI_INLINK_DSCR_ERROR_INT_ST_V 0x00000001
-#define SPI_INLINK_DSCR_ERROR_INT_ST_S 2
-
-/* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO; bitpos: [1]; default: 0;
- * The status bit for outlink descriptor error.
- */
-
-#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1))
-#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M (SPI_OUTLINK_DSCR_ERROR_INT_ST_V << SPI_OUTLINK_DSCR_ERROR_INT_ST_S)
-#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x00000001
-#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1
-
-/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO; bitpos: [0]; default: 0;
- * The status bit for lack of enough inlink descriptors.
- */
-
-#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0))
-#define SPI_INLINK_DSCR_EMPTY_INT_ST_M (SPI_INLINK_DSCR_EMPTY_INT_ST_V << SPI_INLINK_DSCR_EMPTY_INT_ST_S)
-#define SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x00000001
-#define SPI_INLINK_DSCR_EMPTY_INT_ST_S 0
-
-/* SPI_DMA_INT_CLR_REG register */
-
-#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x64)
-
-/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W; bitpos: [8]; default: 0;
- * The clear bit for sending all the packets to host done.
- */
-
-#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8))
-#define SPI_OUT_TOTAL_EOF_INT_CLR_M (SPI_OUT_TOTAL_EOF_INT_CLR_V << SPI_OUT_TOTAL_EOF_INT_CLR_S)
-#define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x00000001
-#define SPI_OUT_TOTAL_EOF_INT_CLR_S 8
-
-/* SPI_OUT_EOF_INT_CLR : R/W; bitpos: [7]; default: 0;
- * The clear bit for sending a packet to host done.
- */
-
-#define SPI_OUT_EOF_INT_CLR (BIT(7))
-#define SPI_OUT_EOF_INT_CLR_M (SPI_OUT_EOF_INT_CLR_V << SPI_OUT_EOF_INT_CLR_S)
-#define SPI_OUT_EOF_INT_CLR_V 0x00000001
-#define SPI_OUT_EOF_INT_CLR_S 7
-
-/* SPI_OUT_DONE_INT_CLR : R/W; bitpos: [6]; default: 0;
- * The clear bit for completing usage of a outlink descriptor.
- */
-
-#define SPI_OUT_DONE_INT_CLR (BIT(6))
-#define SPI_OUT_DONE_INT_CLR_M (SPI_OUT_DONE_INT_CLR_V << SPI_OUT_DONE_INT_CLR_S)
-#define SPI_OUT_DONE_INT_CLR_V 0x00000001
-#define SPI_OUT_DONE_INT_CLR_S 6
-
-/* SPI_IN_SUC_EOF_INT_CLR : R/W; bitpos: [5]; default: 0;
- * The clear bit for completing receiving all the packets from host.
- */
-
-#define SPI_IN_SUC_EOF_INT_CLR (BIT(5))
-#define SPI_IN_SUC_EOF_INT_CLR_M (SPI_IN_SUC_EOF_INT_CLR_V << SPI_IN_SUC_EOF_INT_CLR_S)
-#define SPI_IN_SUC_EOF_INT_CLR_V 0x00000001
-#define SPI_IN_SUC_EOF_INT_CLR_S 5
-
-/* SPI_IN_ERR_EOF_INT_CLR : R/W; bitpos: [4]; default: 0;
- * The clear bit for receiving error.
- */
-
-#define SPI_IN_ERR_EOF_INT_CLR (BIT(4))
-#define SPI_IN_ERR_EOF_INT_CLR_M (SPI_IN_ERR_EOF_INT_CLR_V << SPI_IN_ERR_EOF_INT_CLR_S)
-#define SPI_IN_ERR_EOF_INT_CLR_V 0x00000001
-#define SPI_IN_ERR_EOF_INT_CLR_S 4
-
-/* SPI_IN_DONE_INT_CLR : R/W; bitpos: [3]; default: 0;
- * The clear bit for completing usage of a inlink descriptor.
- */
-
-#define SPI_IN_DONE_INT_CLR (BIT(3))
-#define SPI_IN_DONE_INT_CLR_M (SPI_IN_DONE_INT_CLR_V << SPI_IN_DONE_INT_CLR_S)
-#define SPI_IN_DONE_INT_CLR_V 0x00000001
-#define SPI_IN_DONE_INT_CLR_S 3
-
-/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W; bitpos: [2]; default: 0;
- * The clear bit for inlink descriptor error.
- */
-
-#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2))
-#define SPI_INLINK_DSCR_ERROR_INT_CLR_M (SPI_INLINK_DSCR_ERROR_INT_CLR_V << SPI_INLINK_DSCR_ERROR_INT_CLR_S)
-#define SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x00000001
-#define SPI_INLINK_DSCR_ERROR_INT_CLR_S 2
-
-/* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W; bitpos: [1]; default: 0;
- * The clear bit for outlink descriptor error.
- */
-
-#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1))
-#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (SPI_OUTLINK_DSCR_ERROR_INT_CLR_V << SPI_OUTLINK_DSCR_ERROR_INT_CLR_S)
-#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x00000001
-#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1
-
-/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W; bitpos: [0]; default: 0;
- * The clear bit for lack of enough inlink descriptors.
- */
-
-#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0))
-#define SPI_INLINK_DSCR_EMPTY_INT_CLR_M (SPI_INLINK_DSCR_EMPTY_INT_CLR_V << SPI_INLINK_DSCR_EMPTY_INT_CLR_S)
-#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x00000001
-#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0
-
-/* SPI_IN_ERR_EOF_DES_ADDR_REG register */
-
-#define SPI_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x68)
-
-/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- * The inlink descriptor address when spi dma produce receiving error.
- */
-
-#define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF
-#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M (SPI_DMA_IN_ERR_EOF_DES_ADDR_V << SPI_DMA_IN_ERR_EOF_DES_ADDR_S)
-#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF
-#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0
-
-/* SPI_IN_SUC_EOF_DES_ADDR_REG register */
-
-#define SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x6c)
-
-/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- * The last inlink descriptor address when spi dma produce from_suc_eof.
- */
-
-#define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF
-#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M (SPI_DMA_IN_SUC_EOF_DES_ADDR_V << SPI_DMA_IN_SUC_EOF_DES_ADDR_S)
-#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF
-#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0
-
-/* SPI_INLINK_DSCR_REG register */
-
-#define SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x70)
-
-/* SPI_DMA_INLINK_DSCR : RO; bitpos: [31:0]; default: 0;
- * The content of current in descriptor pointer.
- */
-
-#define SPI_DMA_INLINK_DSCR 0xFFFFFFFF
-#define SPI_DMA_INLINK_DSCR_M (SPI_DMA_INLINK_DSCR_V << SPI_DMA_INLINK_DSCR_S)
-#define SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF
-#define SPI_DMA_INLINK_DSCR_S 0
-
-/* SPI_INLINK_DSCR_BF0_REG register */
-
-#define SPI_INLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x74)
-
-/* SPI_DMA_INLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0;
- * The content of next in descriptor pointer.
- */
-
-#define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF
-#define SPI_DMA_INLINK_DSCR_BF0_M (SPI_DMA_INLINK_DSCR_BF0_V << SPI_DMA_INLINK_DSCR_BF0_S)
-#define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF
-#define SPI_DMA_INLINK_DSCR_BF0_S 0
-
-/* SPI_INLINK_DSCR_BF1_REG register */
-
-#define SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x84)
-
-/* SPI_DMA_INLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0;
- * The content of current in descriptor data buffer pointer.
- */
-
-#define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF
-#define SPI_DMA_INLINK_DSCR_BF1_M (SPI_DMA_INLINK_DSCR_BF1_V << SPI_DMA_INLINK_DSCR_BF1_S)
-#define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF
-#define SPI_DMA_INLINK_DSCR_BF1_S 0
-
-/* SPI_OUT_EOF_BFR_DES_ADDR_REG register */
-
-#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x7c)
-
-/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- * The address of buffer relative to the outlink descriptor that produce eof.
- */
-
-#define SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF
-#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M (SPI_DMA_OUT_EOF_BFR_DES_ADDR_V << SPI_DMA_OUT_EOF_BFR_DES_ADDR_S)
-#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF
-#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0
-
-/* SPI_OUT_EOF_DES_ADDR_REG register */
-
-#define SPI_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x80)
-
-/* SPI_DMA_OUT_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- * The last outlink descriptor address when spi dma produce to_eof.
- */
-
-#define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF
-#define SPI_DMA_OUT_EOF_DES_ADDR_M (SPI_DMA_OUT_EOF_DES_ADDR_V << SPI_DMA_OUT_EOF_DES_ADDR_S)
-#define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF
-#define SPI_DMA_OUT_EOF_DES_ADDR_S 0
-
-/* SPI_OUTLINK_DSCR_REG register */
-
-#define SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x84)
-
-/* SPI_DMA_OUTLINK_DSCR : RO; bitpos: [31:0]; default: 0;
- * The content of current out descriptor pointer.
- */
-
-#define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF
-#define SPI_DMA_OUTLINK_DSCR_M (SPI_DMA_OUTLINK_DSCR_V << SPI_DMA_OUTLINK_DSCR_S)
-#define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF
-#define SPI_DMA_OUTLINK_DSCR_S 0
-
-/* SPI_OUTLINK_DSCR_BF0_REG register */
-
-#define SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x88)
-
-/* SPI_DMA_OUTLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0;
- * The content of next out descriptor pointer.
- */
-
-#define SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF
-#define SPI_DMA_OUTLINK_DSCR_BF0_M (SPI_DMA_OUTLINK_DSCR_BF0_V << SPI_DMA_OUTLINK_DSCR_BF0_S)
-#define SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF
-#define SPI_DMA_OUTLINK_DSCR_BF0_S 0
-
-/* SPI_OUTLINK_DSCR_BF1_REG register */
-
-#define SPI_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x8c)
-
-/* SPI_DMA_OUTLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0;
- * The content of current out descriptor data buffer pointer.
- */
-
-#define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF
-#define SPI_DMA_OUTLINK_DSCR_BF1_M (SPI_DMA_OUTLINK_DSCR_BF1_V << SPI_DMA_OUTLINK_DSCR_BF1_S)
-#define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF
-#define SPI_DMA_OUTLINK_DSCR_BF1_S 0
-
-/* SPI_DMA_OUTSTATUS_REG register */
-
-#define SPI_DMA_OUTSTATUS_REG(i) (REG_SPI_BASE(i) + 0x90)
-
-/* SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [31]; default: 1;
- * SPI dma outfifo is empty.
- */
-
-#define SPI_DMA_OUTFIFO_EMPTY (BIT(31))
-#define SPI_DMA_OUTFIFO_EMPTY_M (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S)
-#define SPI_DMA_OUTFIFO_EMPTY_V 0x00000001
-#define SPI_DMA_OUTFIFO_EMPTY_S 31
-
-/* SPI_DMA_OUTFIFO_FULL : RO; bitpos: [30]; default: 0;
- * SPI dma outfifo is full.
- */
-
-#define SPI_DMA_OUTFIFO_FULL (BIT(30))
-#define SPI_DMA_OUTFIFO_FULL_M (SPI_DMA_OUTFIFO_FULL_V << SPI_DMA_OUTFIFO_FULL_S)
-#define SPI_DMA_OUTFIFO_FULL_V 0x00000001
-#define SPI_DMA_OUTFIFO_FULL_S 30
-
-/* SPI_DMA_OUTFIFO_CNT : RO; bitpos: [29:23]; default: 0;
- * The remains of SPI dma outfifo data.
- */
-
-#define SPI_DMA_OUTFIFO_CNT 0x0000007F
-#define SPI_DMA_OUTFIFO_CNT_M (SPI_DMA_OUTFIFO_CNT_V << SPI_DMA_OUTFIFO_CNT_S)
-#define SPI_DMA_OUTFIFO_CNT_V 0x0000007F
-#define SPI_DMA_OUTFIFO_CNT_S 23
-
-/* SPI_DMA_OUT_STATE : RO; bitpos: [22:20]; default: 0;
- * SPI dma out data state.
- */
-
-#define SPI_DMA_OUT_STATE 0x00000007
-#define SPI_DMA_OUT_STATE_M (SPI_DMA_OUT_STATE_V << SPI_DMA_OUT_STATE_S)
-#define SPI_DMA_OUT_STATE_V 0x00000007
-#define SPI_DMA_OUT_STATE_S 20
-
-/* SPI_DMA_OUTDSCR_STATE : RO; bitpos: [19:18]; default: 0;
- * SPI dma out descriptor state.
- */
-
-#define SPI_DMA_OUTDSCR_STATE 0x00000003
-#define SPI_DMA_OUTDSCR_STATE_M (SPI_DMA_OUTDSCR_STATE_V << SPI_DMA_OUTDSCR_STATE_S)
-#define SPI_DMA_OUTDSCR_STATE_V 0x00000003
-#define SPI_DMA_OUTDSCR_STATE_S 18
-
-/* SPI_DMA_OUTDSCR_ADDR : RO; bitpos: [17:0]; default: 0;
- * SPI dma out descriptor address.
- */
-
-#define SPI_DMA_OUTDSCR_ADDR 0x0003FFFF
-#define SPI_DMA_OUTDSCR_ADDR_M (SPI_DMA_OUTDSCR_ADDR_V << SPI_DMA_OUTDSCR_ADDR_S)
-#define SPI_DMA_OUTDSCR_ADDR_V 0x0003FFFF
-#define SPI_DMA_OUTDSCR_ADDR_S 0
-
-/* SPI_DMA_INSTATUS_REG register */
-
-#define SPI_DMA_INSTATUS_REG(i) (REG_SPI_BASE(i) + 0x94)
-
-/* SPI_DMA_INFIFO_EMPTY : RO; bitpos: [31]; default: 1;
- * SPI dma infifo is empty.
- */
-
-#define SPI_DMA_INFIFO_EMPTY (BIT(31))
-#define SPI_DMA_INFIFO_EMPTY_M (SPI_DMA_INFIFO_EMPTY_V << SPI_DMA_INFIFO_EMPTY_S)
-#define SPI_DMA_INFIFO_EMPTY_V 0x00000001
-#define SPI_DMA_INFIFO_EMPTY_S 31
-
-/* SPI_DMA_INFIFO_FULL : RO; bitpos: [30]; default: 0;
- * SPI dma infifo is full.
- */
-
-#define SPI_DMA_INFIFO_FULL (BIT(30))
-#define SPI_DMA_INFIFO_FULL_M (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S)
-#define SPI_DMA_INFIFO_FULL_V 0x00000001
-#define SPI_DMA_INFIFO_FULL_S 30
-
-/* SPI_DMA_INFIFO_CNT : RO; bitpos: [29:23]; default: 0;
- * The remains of SPI dma infifo data.
- */
-
-#define SPI_DMA_INFIFO_CNT 0x0000007F
-#define SPI_DMA_INFIFO_CNT_M (SPI_DMA_INFIFO_CNT_V << SPI_DMA_INFIFO_CNT_S)
-#define SPI_DMA_INFIFO_CNT_V 0x0000007F
-#define SPI_DMA_INFIFO_CNT_S 23
-
-/* SPI_DMA_IN_STATE : RO; bitpos: [22:20]; default: 0;
- * SPI dma in data state.
- */
-
-#define SPI_DMA_IN_STATE 0x00000007
-#define SPI_DMA_IN_STATE_M (SPI_DMA_IN_STATE_V << SPI_DMA_IN_STATE_S)
-#define SPI_DMA_IN_STATE_V 0x00000007
-#define SPI_DMA_IN_STATE_S 20
-
-/* SPI_DMA_INDSCR_STATE : RO; bitpos: [19:18]; default: 0;
- * SPI dma in descriptor state.
- */
-
-#define SPI_DMA_INDSCR_STATE 0x00000003
-#define SPI_DMA_INDSCR_STATE_M (SPI_DMA_INDSCR_STATE_V << SPI_DMA_INDSCR_STATE_S)
-#define SPI_DMA_INDSCR_STATE_V 0x00000003
-#define SPI_DMA_INDSCR_STATE_S 18
-
-/* SPI_DMA_INDSCR_ADDR : RO; bitpos: [17:0]; default: 0;
- * SPI dma in descriptor address.
- */
-
-#define SPI_DMA_INDSCR_ADDR 0x0003FFFF
-#define SPI_DMA_INDSCR_ADDR_M (SPI_DMA_INDSCR_ADDR_V << SPI_DMA_INDSCR_ADDR_S)
-#define SPI_DMA_INDSCR_ADDR_V 0x0003FFFF
-#define SPI_DMA_INDSCR_ADDR_S 0
-
-/* SPI_W0_REG register */
-
-#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98)
-
-/* SPI_BUF0 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF0 0xFFFFFFFF
-#define SPI_BUF0_M (SPI_BUF0_V << SPI_BUF0_S)
-#define SPI_BUF0_V 0xFFFFFFFF
-#define SPI_BUF0_S 0
-
-/* SPI_W1_REG register */
-
-#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9c)
-
-/* SPI_BUF1 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF1 0xFFFFFFFF
-#define SPI_BUF1_M (SPI_BUF1_V << SPI_BUF1_S)
-#define SPI_BUF1_V 0xFFFFFFFF
-#define SPI_BUF1_S 0
-
-/* SPI_W2_REG register */
-
-#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xa0)
-
-/* SPI_BUF2 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF2 0xFFFFFFFF
-#define SPI_BUF2_M (SPI_BUF2_V << SPI_BUF2_S)
-#define SPI_BUF2_V 0xFFFFFFFF
-#define SPI_BUF2_S 0
-
-/* SPI_W3_REG register */
-
-#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xa4)
-
-/* SPI_BUF3 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF3 0xFFFFFFFF
-#define SPI_BUF3_M (SPI_BUF3_V << SPI_BUF3_S)
-#define SPI_BUF3_V 0xFFFFFFFF
-#define SPI_BUF3_S 0
-
-/* SPI_W4_REG register */
-
-#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xa8)
-
-/* SPI_BUF4 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF4 0xFFFFFFFF
-#define SPI_BUF4_M (SPI_BUF4_V << SPI_BUF4_S)
-#define SPI_BUF4_V 0xFFFFFFFF
-#define SPI_BUF4_S 0
-
-/* SPI_W5_REG register */
-
-#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xac)
-
-/* SPI_BUF5 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF5 0xFFFFFFFF
-#define SPI_BUF5_M (SPI_BUF5_V << SPI_BUF5_S)
-#define SPI_BUF5_V 0xFFFFFFFF
-#define SPI_BUF5_S 0
-
-/* SPI_W6_REG register */
-
-#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xb0)
-
-/* SPI_BUF6 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF6 0xFFFFFFFF
-#define SPI_BUF6_M (SPI_BUF6_V << SPI_BUF6_S)
-#define SPI_BUF6_V 0xFFFFFFFF
-#define SPI_BUF6_S 0
-
-/* SPI_W7_REG register */
-
-#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xb4)
-
-/* SPI_BUF7 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF7 0xFFFFFFFF
-#define SPI_BUF7_M (SPI_BUF7_V << SPI_BUF7_S)
-#define SPI_BUF7_V 0xFFFFFFFF
-#define SPI_BUF7_S 0
-
-/* SPI_W8_REG register */
-
-#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xb8)
-
-/* SPI_BUF8 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF8 0xFFFFFFFF
-#define SPI_BUF8_M (SPI_BUF8_V << SPI_BUF8_S)
-#define SPI_BUF8_V 0xFFFFFFFF
-#define SPI_BUF8_S 0
-
-/* SPI_W9_REG register */
-
-#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xbc)
-
-/* SPI_BUF9 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF9 0xFFFFFFFF
-#define SPI_BUF9_M (SPI_BUF9_V << SPI_BUF9_S)
-#define SPI_BUF9_V 0xFFFFFFFF
-#define SPI_BUF9_S 0
-
-/* SPI_W10_REG register */
-
-#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xc0)
-
-/* SPI_BUF10 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF10 0xFFFFFFFF
-#define SPI_BUF10_M (SPI_BUF10_V << SPI_BUF10_S)
-#define SPI_BUF10_V 0xFFFFFFFF
-#define SPI_BUF10_S 0
-
-/* SPI_W11_REG register */
-
-#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xc4)
-
-/* SPI_BUF11 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF11 0xFFFFFFFF
-#define SPI_BUF11_M (SPI_BUF11_V << SPI_BUF11_S)
-#define SPI_BUF11_V 0xFFFFFFFF
-#define SPI_BUF11_S 0
-
-/* SPI_W12_REG register */
-
-#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xc8)
-
-/* SPI_BUF12 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF12 0xFFFFFFFF
-#define SPI_BUF12_M (SPI_BUF12_V << SPI_BUF12_S)
-#define SPI_BUF12_V 0xFFFFFFFF
-#define SPI_BUF12_S 0
-
-/* SPI_W13_REG register */
-
-#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xcc)
-
-/* SPI_BUF13 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF13 0xFFFFFFFF
-#define SPI_BUF13_M (SPI_BUF13_V << SPI_BUF13_S)
-#define SPI_BUF13_V 0xFFFFFFFF
-#define SPI_BUF13_S 0
-
-/* SPI_W14_REG register */
-
-#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xd0)
-
-/* SPI_BUF14 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF14 0xFFFFFFFF
-#define SPI_BUF14_M (SPI_BUF14_V << SPI_BUF14_S)
-#define SPI_BUF14_V 0xFFFFFFFF
-#define SPI_BUF14_S 0
-
-/* SPI_W15_REG register */
-
-#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xd4)
-
-/* SPI_BUF15 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF15 0xFFFFFFFF
-#define SPI_BUF15_M (SPI_BUF15_V << SPI_BUF15_S)
-#define SPI_BUF15_V 0xFFFFFFFF
-#define SPI_BUF15_S 0
-
-/* SPI_W16_REG register */
-
-#define SPI_W16_REG(i) (REG_SPI_BASE(i) + 0xd8)
-
-/* SPI_BUF16 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF16 0xFFFFFFFF
-#define SPI_BUF16_M (SPI_BUF16_V << SPI_BUF16_S)
-#define SPI_BUF16_V 0xFFFFFFFF
-#define SPI_BUF16_S 0
-
-/* SPI_W17_REG register */
-
-#define SPI_W17_REG(i) (REG_SPI_BASE(i) + 0xdc)
-
-/* SPI_BUF17 : R/W; bitpos: [31:0]; default: 0;
- * data buffer
- */
-
-#define SPI_BUF17 0xFFFFFFFF
-#define SPI_BUF17_M (SPI_BUF17_V << SPI_BUF17_S)
-#define SPI_BUF17_V 0xFFFFFFFF
-#define SPI_BUF17_S 0
-
-/* SPI_DIN_MODE_REG register */
-
-#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0xe0)
-
-/* SPI_TIMING_CLK_ENA : R/W; bitpos: [24]; default: 0;
- * 1:enable hclk in spi_timing.v. 0: disable it.
- */
-
-#define SPI_TIMING_CLK_ENA (BIT(24))
-#define SPI_TIMING_CLK_ENA_M (SPI_TIMING_CLK_ENA_V << SPI_TIMING_CLK_ENA_S)
-#define SPI_TIMING_CLK_ENA_V 0x00000001
-#define SPI_TIMING_CLK_ENA_S 24
-
-/* SPI_DIN7_MODE : R/W; bitpos: [23:21]; default: 0;
- * Configure the input signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DIN7_MODE 0x00000007
-#define SPI_DIN7_MODE_M (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S)
-#define SPI_DIN7_MODE_V 0x00000007
-#define SPI_DIN7_MODE_S 21
-
-/* SPI_DIN6_MODE : R/W; bitpos: [20:18]; default: 0;
- * Configure the input signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DIN6_MODE 0x00000007
-#define SPI_DIN6_MODE_M (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S)
-#define SPI_DIN6_MODE_V 0x00000007
-#define SPI_DIN6_MODE_S 18
-
-/* SPI_DIN5_MODE : R/W; bitpos: [17:15]; default: 0;
- * Configure the input signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DIN5_MODE 0x00000007
-#define SPI_DIN5_MODE_M (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S)
-#define SPI_DIN5_MODE_V 0x00000007
-#define SPI_DIN5_MODE_S 15
-
-/* SPI_DIN4_MODE : R/W; bitpos: [14:12]; default: 0;
- * Configure the input signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DIN4_MODE 0x00000007
-#define SPI_DIN4_MODE_M (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S)
-#define SPI_DIN4_MODE_V 0x00000007
-#define SPI_DIN4_MODE_S 12
-
-/* SPI_DIN3_MODE : R/W; bitpos: [11:9]; default: 0;
- * Configure the input signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DIN3_MODE 0x00000007
-#define SPI_DIN3_MODE_M (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S)
-#define SPI_DIN3_MODE_V 0x00000007
-#define SPI_DIN3_MODE_S 9
-
-/* SPI_DIN2_MODE : R/W; bitpos: [8:6]; default: 0;
- * Configure the input signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DIN2_MODE 0x00000007
-#define SPI_DIN2_MODE_M (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S)
-#define SPI_DIN2_MODE_V 0x00000007
-#define SPI_DIN2_MODE_S 6
-
-/* SPI_DIN1_MODE : R/W; bitpos: [5:3]; default: 0;
- * Configure the input signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DIN1_MODE 0x00000007
-#define SPI_DIN1_MODE_M (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S)
-#define SPI_DIN1_MODE_V 0x00000007
-#define SPI_DIN1_MODE_S 3
-
-/* SPI_DIN0_MODE : R/W; bitpos: [2:0]; default: 0;
- * Configure the input signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DIN0_MODE 0x00000007
-#define SPI_DIN0_MODE_M (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S)
-#define SPI_DIN0_MODE_V 0x00000007
-#define SPI_DIN0_MODE_S 0
-
-/* SPI_DIN_NUM_REG register */
-
-#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0xe4)
-
-/* SPI_DIN7_NUM : R/W; bitpos: [15:14]; default: 0;
- * the input signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DIN7_NUM 0x00000003
-#define SPI_DIN7_NUM_M (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S)
-#define SPI_DIN7_NUM_V 0x00000003
-#define SPI_DIN7_NUM_S 14
-
-/* SPI_DIN6_NUM : R/W; bitpos: [13:12]; default: 0;
- * the input signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DIN6_NUM 0x00000003
-#define SPI_DIN6_NUM_M (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S)
-#define SPI_DIN6_NUM_V 0x00000003
-#define SPI_DIN6_NUM_S 12
-
-/* SPI_DIN5_NUM : R/W; bitpos: [11:10]; default: 0;
- * the input signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DIN5_NUM 0x00000003
-#define SPI_DIN5_NUM_M (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S)
-#define SPI_DIN5_NUM_V 0x00000003
-#define SPI_DIN5_NUM_S 10
-
-/* SPI_DIN4_NUM : R/W; bitpos: [9:8]; default: 0;
- * the input signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DIN4_NUM 0x00000003
-#define SPI_DIN4_NUM_M (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S)
-#define SPI_DIN4_NUM_V 0x00000003
-#define SPI_DIN4_NUM_S 8
-
-/* SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
- * the input signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DIN3_NUM 0x00000003
-#define SPI_DIN3_NUM_M (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S)
-#define SPI_DIN3_NUM_V 0x00000003
-#define SPI_DIN3_NUM_S 6
-
-/* SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
- * the input signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DIN2_NUM 0x00000003
-#define SPI_DIN2_NUM_M (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S)
-#define SPI_DIN2_NUM_V 0x00000003
-#define SPI_DIN2_NUM_S 4
-
-/* SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
- * the input signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DIN1_NUM 0x00000003
-#define SPI_DIN1_NUM_M (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S)
-#define SPI_DIN1_NUM_V 0x00000003
-#define SPI_DIN1_NUM_S 2
-
-/* SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
- * the input signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DIN0_NUM 0x00000003
-#define SPI_DIN0_NUM_M (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S)
-#define SPI_DIN0_NUM_V 0x00000003
-#define SPI_DIN0_NUM_S 0
-
-/* SPI_DOUT_MODE_REG register */
-
-#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0xe8)
-
-/* SPI_DOUT7_MODE : R/W; bitpos: [23:21]; default: 0;
- * Configure the output signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DOUT7_MODE 0x00000007
-#define SPI_DOUT7_MODE_M (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S)
-#define SPI_DOUT7_MODE_V 0x00000007
-#define SPI_DOUT7_MODE_S 21
-
-/* SPI_DOUT6_MODE : R/W; bitpos: [20:18]; default: 0;
- * Configure the output signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DOUT6_MODE 0x00000007
-#define SPI_DOUT6_MODE_M (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S)
-#define SPI_DOUT6_MODE_V 0x00000007
-#define SPI_DOUT6_MODE_S 18
-
-/* SPI_DOUT5_MODE : R/W; bitpos: [17:15]; default: 0;
- * Configure the output signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DOUT5_MODE 0x00000007
-#define SPI_DOUT5_MODE_M (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S)
-#define SPI_DOUT5_MODE_V 0x00000007
-#define SPI_DOUT5_MODE_S 15
-
-/* SPI_DOUT4_MODE : R/W; bitpos: [14:12]; default: 0;
- * Configure the output signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DOUT4_MODE 0x00000007
-#define SPI_DOUT4_MODE_M (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S)
-#define SPI_DOUT4_MODE_V 0x00000007
-#define SPI_DOUT4_MODE_S 12
-
-/* SPI_DOUT3_MODE : R/W; bitpos: [11:9]; default: 0;
- * Configure the output signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DOUT3_MODE 0x00000007
-#define SPI_DOUT3_MODE_M (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S)
-#define SPI_DOUT3_MODE_V 0x00000007
-#define SPI_DOUT3_MODE_S 9
-
-/* SPI_DOUT2_MODE : R/W; bitpos: [8:6]; default: 0;
- * Configure the output signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DOUT2_MODE 0x00000007
-#define SPI_DOUT2_MODE_M (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S)
-#define SPI_DOUT2_MODE_V 0x00000007
-#define SPI_DOUT2_MODE_S 6
-
-/* SPI_DOUT1_MODE : R/W; bitpos: [5:3]; default: 0;
- * Configure the output signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DOUT1_MODE 0x00000007
-#define SPI_DOUT1_MODE_M (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S)
-#define SPI_DOUT1_MODE_V 0x00000007
-#define SPI_DOUT1_MODE_S 3
-
-/* SPI_DOUT0_MODE : R/W; bitpos: [2:0]; default: 0;
- * Configure the output signal delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_DOUT0_MODE 0x00000007
-#define SPI_DOUT0_MODE_M (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S)
-#define SPI_DOUT0_MODE_V 0x00000007
-#define SPI_DOUT0_MODE_S 0
-
-/* SPI_DOUT_NUM_REG register */
-
-#define SPI_DOUT_NUM_REG(i) (REG_SPI_BASE(i) + 0xec)
-
-/* SPI_DOUT7_NUM : R/W; bitpos: [15:14]; default: 0;
- * the output signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DOUT7_NUM 0x00000003
-#define SPI_DOUT7_NUM_M (SPI_DOUT7_NUM_V << SPI_DOUT7_NUM_S)
-#define SPI_DOUT7_NUM_V 0x00000003
-#define SPI_DOUT7_NUM_S 14
-
-/* SPI_DOUT6_NUM : R/W; bitpos: [13:12]; default: 0;
- * the output signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DOUT6_NUM 0x00000003
-#define SPI_DOUT6_NUM_M (SPI_DOUT6_NUM_V << SPI_DOUT6_NUM_S)
-#define SPI_DOUT6_NUM_V 0x00000003
-#define SPI_DOUT6_NUM_S 12
-
-/* SPI_DOUT5_NUM : R/W; bitpos: [11:10]; default: 0;
- * the output signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DOUT5_NUM 0x00000003
-#define SPI_DOUT5_NUM_M (SPI_DOUT5_NUM_V << SPI_DOUT5_NUM_S)
-#define SPI_DOUT5_NUM_V 0x00000003
-#define SPI_DOUT5_NUM_S 10
-
-/* SPI_DOUT4_NUM : R/W; bitpos: [9:8]; default: 0;
- * the output signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DOUT4_NUM 0x00000003
-#define SPI_DOUT4_NUM_M (SPI_DOUT4_NUM_V << SPI_DOUT4_NUM_S)
-#define SPI_DOUT4_NUM_V 0x00000003
-#define SPI_DOUT4_NUM_S 8
-
-/* SPI_DOUT3_NUM : R/W; bitpos: [7:6]; default: 0;
- * the output signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DOUT3_NUM 0x00000003
-#define SPI_DOUT3_NUM_M (SPI_DOUT3_NUM_V << SPI_DOUT3_NUM_S)
-#define SPI_DOUT3_NUM_V 0x00000003
-#define SPI_DOUT3_NUM_S 6
-
-/* SPI_DOUT2_NUM : R/W; bitpos: [5:4]; default: 0;
- * the output signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DOUT2_NUM 0x00000003
-#define SPI_DOUT2_NUM_M (SPI_DOUT2_NUM_V << SPI_DOUT2_NUM_S)
-#define SPI_DOUT2_NUM_V 0x00000003
-#define SPI_DOUT2_NUM_S 4
-
-/* SPI_DOUT1_NUM : R/W; bitpos: [3:2]; default: 0;
- * the output signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DOUT1_NUM 0x00000003
-#define SPI_DOUT1_NUM_M (SPI_DOUT1_NUM_V << SPI_DOUT1_NUM_S)
-#define SPI_DOUT1_NUM_V 0x00000003
-#define SPI_DOUT1_NUM_S 2
-
-/* SPI_DOUT0_NUM : R/W; bitpos: [1:0]; default: 0;
- * the output signals are delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_DOUT0_NUM 0x00000003
-#define SPI_DOUT0_NUM_M (SPI_DOUT0_NUM_V << SPI_DOUT0_NUM_S)
-#define SPI_DOUT0_NUM_V 0x00000003
-#define SPI_DOUT0_NUM_S 0
-
-/* SPI_LCD_CTRL_REG register */
-
-#define SPI_LCD_CTRL_REG(i) (REG_SPI_BASE(i) + 0xf0)
-
/* SPI_LCD_SRGB_MODE_EN : R/W; bitpos: [31]; default: 0;
* 1: Enable LCD mode output vsync, hsync, de. 0: Disable.
*/
@@ -2885,256 +41,4 @@
#define SPI_LCD_SRGB_MODE_EN_V 0x00000001
#define SPI_LCD_SRGB_MODE_EN_S 31
-/* SPI_LCD_VT_HEIGHT : R/W; bitpos: [30:21]; default: 0;
- * It is the vertical total height of a frame.
- */
-
-#define SPI_LCD_VT_HEIGHT 0x000003FF
-#define SPI_LCD_VT_HEIGHT_M (SPI_LCD_VT_HEIGHT_V << SPI_LCD_VT_HEIGHT_S)
-#define SPI_LCD_VT_HEIGHT_V 0x000003FF
-#define SPI_LCD_VT_HEIGHT_S 21
-
-/* SPI_LCD_VA_HEIGHT : R/W; bitpos: [20:11]; default: 0;
- * It is the vertical active height of a frame.
- */
-
-#define SPI_LCD_VA_HEIGHT 0x000003FF
-#define SPI_LCD_VA_HEIGHT_M (SPI_LCD_VA_HEIGHT_V << SPI_LCD_VA_HEIGHT_S)
-#define SPI_LCD_VA_HEIGHT_V 0x000003FF
-#define SPI_LCD_VA_HEIGHT_S 11
-
-/* SPI_LCD_HB_FRONT : R/W; bitpos: [10:0]; default: 0;
- * It is the horizontal blank front porch of a frame.
- */
-
-#define SPI_LCD_HB_FRONT 0x000007FF
-#define SPI_LCD_HB_FRONT_M (SPI_LCD_HB_FRONT_V << SPI_LCD_HB_FRONT_S)
-#define SPI_LCD_HB_FRONT_V 0x000007FF
-#define SPI_LCD_HB_FRONT_S 0
-
-/* SPI_LCD_CTRL1_REG register */
-
-#define SPI_LCD_CTRL1_REG(i) (REG_SPI_BASE(i) + 0xf4)
-
-/* SPI_LCD_HT_WIDTH : R/W; bitpos: [31:20]; default: 0;
- * It is the horizontal total width of a frame.
- */
-
-#define SPI_LCD_HT_WIDTH 0x00000FFF
-#define SPI_LCD_HT_WIDTH_M (SPI_LCD_HT_WIDTH_V << SPI_LCD_HT_WIDTH_S)
-#define SPI_LCD_HT_WIDTH_V 0x00000FFF
-#define SPI_LCD_HT_WIDTH_S 20
-
-/* SPI_LCD_HA_WIDTH : R/W; bitpos: [19:8]; default: 0;
- * It is the horizontal active width of a frame.
- */
-
-#define SPI_LCD_HA_WIDTH 0x00000FFF
-#define SPI_LCD_HA_WIDTH_M (SPI_LCD_HA_WIDTH_V << SPI_LCD_HA_WIDTH_S)
-#define SPI_LCD_HA_WIDTH_V 0x00000FFF
-#define SPI_LCD_HA_WIDTH_S 8
-
-/* SPI_LCD_VB_FRONT : R/W; bitpos: [7:0]; default: 0;
- * It is the vertical blank front porch of a frame.
- */
-
-#define SPI_LCD_VB_FRONT 0x000000FF
-#define SPI_LCD_VB_FRONT_M (SPI_LCD_VB_FRONT_V << SPI_LCD_VB_FRONT_S)
-#define SPI_LCD_VB_FRONT_V 0x000000FF
-#define SPI_LCD_VB_FRONT_S 0
-
-/* SPI_LCD_CTRL2_REG register */
-
-#define SPI_LCD_CTRL2_REG(i) (REG_SPI_BASE(i) + 0xf8)
-
-/* SPI_LCD_HSYNC_POSITION : R/W; bitpos: [31:24]; default: 0;
- * It is the position of spi_hsync_out active pulse in a line.
- */
-
-#define SPI_LCD_HSYNC_POSITION 0x000000FF
-#define SPI_LCD_HSYNC_POSITION_M (SPI_LCD_HSYNC_POSITION_V << SPI_LCD_HSYNC_POSITION_S)
-#define SPI_LCD_HSYNC_POSITION_V 0x000000FF
-#define SPI_LCD_HSYNC_POSITION_S 24
-
-/* SPI_HSYNC_IDLE_POL : R/W; bitpos: [23]; default: 0;
- * It is the idle value of spi_hsync_out.
- */
-
-#define SPI_HSYNC_IDLE_POL (BIT(23))
-#define SPI_HSYNC_IDLE_POL_M (SPI_HSYNC_IDLE_POL_V << SPI_HSYNC_IDLE_POL_S)
-#define SPI_HSYNC_IDLE_POL_V 0x00000001
-#define SPI_HSYNC_IDLE_POL_S 23
-
-/* SPI_LCD_HSYNC_WIDTH : R/W; bitpos: [22:16]; default: 0;
- * It is the position of spi_hsync_out active pulse in a line.
- */
-
-#define SPI_LCD_HSYNC_WIDTH 0x0000007F
-#define SPI_LCD_HSYNC_WIDTH_M (SPI_LCD_HSYNC_WIDTH_V << SPI_LCD_HSYNC_WIDTH_S)
-#define SPI_LCD_HSYNC_WIDTH_V 0x0000007F
-#define SPI_LCD_HSYNC_WIDTH_S 16
-
-/* SPI_LCD_VSYNC_POSITION : R/W; bitpos: [15:8]; default: 0;
- * It is the position of spi_vsync_out active pulse in a line.
- */
-
-#define SPI_LCD_VSYNC_POSITION 0x000000FF
-#define SPI_LCD_VSYNC_POSITION_M (SPI_LCD_VSYNC_POSITION_V << SPI_LCD_VSYNC_POSITION_S)
-#define SPI_LCD_VSYNC_POSITION_V 0x000000FF
-#define SPI_LCD_VSYNC_POSITION_S 8
-
-/* SPI_VSYNC_IDLE_POL : R/W; bitpos: [7]; default: 0;
- * It is the idle value of spi_vsync_out.
- */
-
-#define SPI_VSYNC_IDLE_POL (BIT(7))
-#define SPI_VSYNC_IDLE_POL_M (SPI_VSYNC_IDLE_POL_V << SPI_VSYNC_IDLE_POL_S)
-#define SPI_VSYNC_IDLE_POL_V 0x00000001
-#define SPI_VSYNC_IDLE_POL_S 7
-
-/* SPI_LCD_VSYNC_WIDTH : R/W; bitpos: [6:0]; default: 0;
- * It is the position of spi_vsync_out active pulse in a line.
- */
-
-#define SPI_LCD_VSYNC_WIDTH 0x0000007F
-#define SPI_LCD_VSYNC_WIDTH_M (SPI_LCD_VSYNC_WIDTH_V << SPI_LCD_VSYNC_WIDTH_S)
-#define SPI_LCD_VSYNC_WIDTH_V 0x0000007F
-#define SPI_LCD_VSYNC_WIDTH_S 0
-
-/* SPI_LCD_D_MODE_REG register */
-
-#define SPI_LCD_D_MODE_REG(i) (REG_SPI_BASE(i) + 0xfc)
-
-/* SPI_D_VSYNC_MODE : R/W; bitpos: [14:12]; default: 0;
- * Configure the output spi_vsync delay mode. 0: without delayed, 1: with
- * the posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the
- * posedge of hclk, whose frequency is the double of the clk_apb frequency,
- * 4: with the negedge of hclk, 5: with the posedge of spi_clk, 6: with the
- * negedge of spi_clk.
- */
-
-#define SPI_D_VSYNC_MODE 0x00000007
-#define SPI_D_VSYNC_MODE_M (SPI_D_VSYNC_MODE_V << SPI_D_VSYNC_MODE_S)
-#define SPI_D_VSYNC_MODE_V 0x00000007
-#define SPI_D_VSYNC_MODE_S 12
-
-/* SPI_D_HSYNC_MODE : R/W; bitpos: [11:9]; default: 0;
- * Configure the output spi_hsync delay mode. 0: without delayed, 1: with
- * the posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the
- * posedge of hclk, whose frequency is the double of the clk_apb frequency,
- * 4: with the negedge of hclk, 5: with the posedge of spi_clk, 6: with the
- * negedge of spi_clk.
- */
-
-#define SPI_D_HSYNC_MODE 0x00000007
-#define SPI_D_HSYNC_MODE_M (SPI_D_HSYNC_MODE_V << SPI_D_HSYNC_MODE_S)
-#define SPI_D_HSYNC_MODE_V 0x00000007
-#define SPI_D_HSYNC_MODE_S 9
-
-/* SPI_D_DE_MODE : R/W; bitpos: [8:6]; default: 0;
- * Configure the output spi_de delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_D_DE_MODE 0x00000007
-#define SPI_D_DE_MODE_M (SPI_D_DE_MODE_V << SPI_D_DE_MODE_S)
-#define SPI_D_DE_MODE_V 0x00000007
-#define SPI_D_DE_MODE_S 6
-
-/* SPI_D_CD_MODE : R/W; bitpos: [5:3]; default: 0;
- * Configure the output spi_cd delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_D_CD_MODE 0x00000007
-#define SPI_D_CD_MODE_M (SPI_D_CD_MODE_V << SPI_D_CD_MODE_S)
-#define SPI_D_CD_MODE_V 0x00000007
-#define SPI_D_CD_MODE_S 3
-
-/* SPI_D_DQS_MODE : R/W; bitpos: [2:0]; default: 0;
- * Configure the output spi_dqs delay mode. 0: without delayed, 1: with the
- * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge
- * of hclk, whose frequency is the double of the clk_apb frequency, 4: with
- * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge
- * of spi_clk.
- */
-
-#define SPI_D_DQS_MODE 0x00000007
-#define SPI_D_DQS_MODE_M (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S)
-#define SPI_D_DQS_MODE_V 0x00000007
-#define SPI_D_DQS_MODE_S 0
-
-/* SPI_LCD_D_NUM_REG register */
-
-#define SPI_LCD_D_NUM_REG(i) (REG_SPI_BASE(i) + 0x100)
-
-/* SPI_D_VSYNC_NUM : R/W; bitpos: [9:8]; default: 0;
- * the output spi_vsync is delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_D_VSYNC_NUM 0x00000003
-#define SPI_D_VSYNC_NUM_M (SPI_D_VSYNC_NUM_V << SPI_D_VSYNC_NUM_S)
-#define SPI_D_VSYNC_NUM_V 0x00000003
-#define SPI_D_VSYNC_NUM_S 8
-
-/* SPI_D_HSYNC_NUM : R/W; bitpos: [7:6]; default: 0;
- * the output spi_hsync is delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_D_HSYNC_NUM 0x00000003
-#define SPI_D_HSYNC_NUM_M (SPI_D_HSYNC_NUM_V << SPI_D_HSYNC_NUM_S)
-#define SPI_D_HSYNC_NUM_V 0x00000003
-#define SPI_D_HSYNC_NUM_S 6
-
-/* SPI_D_DE_NUM : R/W; bitpos: [5:4]; default: 0;
- * the output spi_de is delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_D_DE_NUM 0x00000003
-#define SPI_D_DE_NUM_M (SPI_D_DE_NUM_V << SPI_D_DE_NUM_S)
-#define SPI_D_DE_NUM_V 0x00000003
-#define SPI_D_DE_NUM_S 4
-
-/* SPI_D_CD_NUM : R/W; bitpos: [3:2]; default: 0;
- * the output spi_cd is delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_D_CD_NUM 0x00000003
-#define SPI_D_CD_NUM_M (SPI_D_CD_NUM_V << SPI_D_CD_NUM_S)
-#define SPI_D_CD_NUM_V 0x00000003
-#define SPI_D_CD_NUM_S 2
-
-/* SPI_D_DQS_NUM : R/W; bitpos: [1:0]; default: 0;
- * the output spi_dqs is delayed by system clock cycles, 0: delayed by 1
- * cycle, 1: delayed by 2 cycles,...
- */
-
-#define SPI_D_DQS_NUM 0x00000003
-#define SPI_D_DQS_NUM_M (SPI_D_DQS_NUM_V << SPI_D_DQS_NUM_S)
-#define SPI_D_DQS_NUM_V 0x00000003
-#define SPI_D_DQS_NUM_S 0
-
-/* SPI_REG_DATE_REG register */
-
-#define SPI_REG_DATE_REG(i) (REG_SPI_BASE(i) + 0x3fc)
-
-/* SPI_DATE : RW; bitpos: [27:0]; default: 26222993;
- * SPI register version.
- */
-
-#define SPI_DATE 0x0FFFFFFF
-#define SPI_DATE_M (SPI_DATE_V << SPI_DATE_S)
-#define SPI_DATE_V 0x0FFFFFFF
-#define SPI_DATE_S 0
-
#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SPI_H */
diff --git a/arch/xtensa/src/esp32s2/loader.c b/arch/xtensa/src/esp32s2/loader.c
new file mode 100644
index 0000000000..a8839c9cd3
--- /dev/null
+++ b/arch/xtensa/src/esp32s2/loader.c
@@ -0,0 +1,300 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s2/loader.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+
+#include "xtensa.h"
+#include "esp_attr.h"
+
+#include "hal/mmu_hal.h"
+#include "hal/mmu_types.h"
+#include "hal/cache_types.h"
+#include "hal/cache_ll.h"
+#include "hal/cache_hal.h"
+#include "soc/extmem_reg.h"
+#include "rom/cache.h"
+#include "spi_flash_mmap.h"
+
+# include "bootloader_flash_priv.h"
+#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
+# include "bootloader_init.h"
+# include "esp_rom_uart.h"
+# include "esp_rom_sys.h"
+# include "esp_app_format.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
+ defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
+# define HDR_ATTR __attribute__((section(".entry_addr"))) \
+ __attribute__((used))
+# define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */
+# define CACHE_REG EXTMEM_ICACHE_CTRL1_REG
+# define CACHE_MASK (EXTMEM_ICACHE_SHUT_IBUS_M | \
+ EXTMEM_ICACHE_SHUT_DBUS_M)
+
+# define CHECKSUM_ALIGN 16
+# define IS_PADD(addr) (addr == 0)
+# define IS_DRAM(addr) (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH)
+# define IS_IRAM(addr) (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH)
+# define IS_IROM(addr) (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH)
+# define IS_DROM(addr) (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH)
+# define IS_SRAM(addr) (IS_IRAM(addr) || IS_DRAM(addr))
+# define IS_MMAP(addr) (IS_IROM(addr) || IS_DROM(addr))
+# ifdef SOC_RTC_FAST_MEM_SUPPORTED
+# define IS_RTC_FAST_IRAM(addr) \
+ (addr >= SOC_RTC_IRAM_LOW && addr < SOC_RTC_IRAM_HIGH)
+# define IS_RTC_FAST_DRAM(addr) \
+ (addr >= SOC_RTC_DRAM_LOW && addr < SOC_RTC_DRAM_HIGH)
+# else
+# define IS_RTC_FAST_IRAM(addr) 0
+# define IS_RTC_FAST_DRAM(addr) 0
+# endif
+# ifdef SOC_RTC_SLOW_MEM_SUPPORTED
+# define IS_RTC_SLOW_DRAM(addr) \
+ (addr >= SOC_RTC_DATA_LOW && addr < SOC_RTC_DATA_HIGH)
+# else
+# define IS_RTC_SLOW_DRAM(addr) 0
+# endif
+
+# define IS_NONE(addr) (!IS_IROM(addr) && !IS_DROM(addr) \
+ && !IS_IRAM(addr) && !IS_DRAM(addr) \
+ && !IS_RTC_FAST_IRAM(addr) && !IS_RTC_FAST_DRAM(addr) \
+ && !IS_RTC_SLOW_DRAM(addr) && !IS_PADD(addr))
+
+# define IS_MAPPING(addr) IS_IROM(addr) || IS_DROM(addr)
+
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
+ defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
+extern uint8_t _image_irom_vma[];
+extern uint8_t _image_irom_lma[];
+extern uint8_t _image_irom_size[];
+
+extern uint8_t _image_drom_vma[];
+extern uint8_t _image_drom_lma[];
+extern uint8_t _image_drom_size[];
+#endif
+
+/****************************************************************************
+ * ROM Function Prototypes
+ ****************************************************************************/
+
+#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
+ defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
+extern int ets_printf(const char *fmt, ...) printf_like(1, 2);
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: map_rom_segments
+ *
+ * Description:
+ * Configure the MMU and Cache peripherals for accessing ROM code and data.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
+ uint32_t app_drom_size, uint32_t app_irom_start,
+ uint32_t app_irom_vaddr, uint32_t app_irom_size)
+{
+ uint32_t rc = 0;
+ uint32_t actual_mapped_len = 0;
+ uint32_t app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK;
+ uint32_t app_irom_vaddr_aligned = app_irom_vaddr & MMU_FLASH_MASK;
+ uint32_t app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK;
+ uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK;
+
+#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
+ esp_image_header_t image_header; /* Header for entire image */
+ esp_image_segment_header_t WORD_ALIGNED_ATTR segment_hdr;
+ bool padding_checksum = false;
+ unsigned int segments = 0;
+ unsigned int ram_segments = 0;
+ unsigned int rom_segments = 0;
+ size_t offset = CONFIG_BOOTLOADER_OFFSET_IN_FLASH;
+
+ /* Read image header */
+
+ if (bootloader_flash_read(offset, &image_header,
+ sizeof(esp_image_header_t),
+ true) != ESP_OK)
+ {
+ ets_printf("Failed to load image header!\n");
+ abort();
+ }
+
+ offset += sizeof(esp_image_header_t);
+
+ /* Iterate for segment information parsing */
+
+ while (segments++ < 16 && rom_segments < 2)
+ {
+ /* Read segment header */
+
+ if (bootloader_flash_read(offset, &segment_hdr,
+ sizeof(esp_image_segment_header_t),
+ true) != ESP_OK)
+ {
+ ets_printf("failed to read segment header at %x\n", offset);
+ abort();
+ }
+
+ if (IS_NONE(segment_hdr.load_addr))
+ {
+ break;
+ }
+
+ if (IS_RTC_FAST_IRAM(segment_hdr.load_addr) ||
+ IS_RTC_FAST_DRAM(segment_hdr.load_addr) ||
+ IS_RTC_SLOW_DRAM(segment_hdr.load_addr))
+ {
+ /* RTC segment is loaded by ROM bootloader */
+
+ ram_segments++;
+ }
+
+ ets_printf("%s: lma 0x%08x vma 0x%08x len 0x%-6x (%u)\n",
+ IS_NONE(segment_hdr.load_addr) ? "???" :
+ IS_RTC_FAST_IRAM(segment_hdr.load_addr) ||
+ IS_RTC_FAST_DRAM(segment_hdr.load_addr) ||
+ IS_RTC_SLOW_DRAM(segment_hdr.load_addr) ? "rtc" :
+ IS_MMAP(segment_hdr.load_addr) ?
+ IS_IROM(segment_hdr.load_addr) ? "imap" : "dmap" :
+ IS_PADD(segment_hdr.load_addr) ? "padd" :
+ IS_DRAM(segment_hdr.load_addr) ? "dram" : "iram",
+ offset + sizeof(esp_image_segment_header_t),
+ segment_hdr.load_addr, segment_hdr.data_len,
+ segment_hdr.data_len);
+
+ /* Fix drom and irom produced be the linker, as this
+ * is later invalidated by the elf2image command.
+ */
+
+ if (IS_DROM(segment_hdr.load_addr) &&
+ segment_hdr.load_addr == (uint32_t)_image_drom_vma)
+ {
+ app_drom_start = offset + sizeof(esp_image_segment_header_t);
+ app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK;
+ rom_segments++;
+ }
+
+ if (IS_IROM(segment_hdr.load_addr) &&
+ segment_hdr.load_addr == (uint32_t)_image_irom_vma)
+ {
+ app_irom_start = offset + sizeof(esp_image_segment_header_t);
+ app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK;
+ rom_segments++;
+ }
+
+ if (IS_SRAM(segment_hdr.load_addr))
+ {
+ ram_segments++;
+ }
+
+ offset += sizeof(esp_image_segment_header_t) + segment_hdr.data_len;
+ if (ram_segments == image_header.segment_count && !padding_checksum)
+ {
+ offset += (CHECKSUM_ALIGN - 1) - (offset % CHECKSUM_ALIGN) + 1;
+ padding_checksum = true;
+ }
+ }
+
+ if (segments == 0 || segments == 16)
+ {
+ ets_printf("Error parsing segments\n");
+ }
+
+ ets_printf("total segments stored %d\n", segments - 1);
+#endif
+
+#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
+ ets_printf("IROM segment aligned lma 0x%08x vma 0x%08x len 0x%06x (%u)\n",
+ app_irom_start_aligned, app_irom_vaddr_aligned,
+ app_irom_size, app_irom_size);
+ ets_printf("DROM segment aligned lma 0x%08x vma 0x%08x len 0x%06x (%u)\n",
+ app_drom_start_aligned, app_drom_vaddr_aligned,
+ app_drom_size, app_drom_size);
+#endif
+
+ cache_hal_disable(CACHE_TYPE_ALL);
+
+ /* Clear the MMU entries that are already set up,
+ * so the new app only has the mappings it creates.
+ */
+
+ mmu_hal_unmap_all();
+
+ mmu_hal_map_region(0, MMU_TARGET_FLASH0,
+ app_drom_vaddr_aligned, app_drom_start_aligned,
+ app_drom_size, &actual_mapped_len);
+
+ mmu_hal_map_region(0, MMU_TARGET_FLASH0,
+ app_irom_vaddr_aligned, app_irom_start_aligned,
+ app_irom_size, &actual_mapped_len);
+
+ /* ------------------Enable corresponding buses--------------------- */
+
+ cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, app_drom_vaddr_aligned,
+ app_drom_size);
+ cache_ll_l1_enable_bus(0, bus_mask);
+ bus_mask = cache_ll_l1_get_bus(0, app_irom_vaddr_aligned, app_irom_size);
+ cache_ll_l1_enable_bus(0, bus_mask);
+#if CONFIG_ESPRESSIF_NUM_CPUS > 1
+ bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_aligned, app_drom_size);
+ cache_ll_l1_enable_bus(1, bus_mask);
+ bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_aligned, app_irom_size);
+ cache_ll_l1_enable_bus(1, bus_mask);
+#endif
+
+ /* ------------------Enable Cache----------------------------------- */
+
+ cache_hal_enable(CACHE_TYPE_ALL);
+
+ return (int)rc;
+}
diff --git a/boards/xtensa/esp32s2/common/src/esp32s2_board_twai.c b/arch/xtensa/src/esp32s2/loader.h
similarity index 60%
copy from boards/xtensa/esp32s2/common/src/esp32s2_board_twai.c
copy to arch/xtensa/src/esp32s2/loader.h
index 73c56476ac..9c7e09adc3 100644
--- a/boards/xtensa/esp32s2/common/src/esp32s2_board_twai.c
+++ b/arch/xtensa/src/esp32s2/loader.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/xtensa/esp32s2/common/src/esp32s2_board_twai.c
+ * arch/xtensa/src/esp32s2/loader.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,72 +18,63 @@
*
****************************************************************************/
+#ifndef __ARCH_XTENSA_SRC_ESP32S2_LOADER_H
+#define __ARCH_XTENSA_SRC_ESP32S2_LOADER_H
+
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
+#include <stdint.h>
-#include <errno.h>
-#include <debug.h>
-
-#include <nuttx/can/can.h>
-#include <arch/board/board.h>
-
-#include "chip.h"
-
-#include "esp32s2_twai.h"
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
-#ifdef CONFIG_CAN
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
/****************************************************************************
- * Pre-processor Definitions
+ * Public Data
****************************************************************************/
-/* Configuration ************************************************************/
+#ifndef __ASSEMBLY__
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
/****************************************************************************
- * Public Functions
+ * Public Functions Prototypes
****************************************************************************/
/****************************************************************************
- * Name: board_twai_setup
+ * Name: map_rom_segments
*
* Description:
- * Initialize TWAI and register the TWAI device
+ * Configure the MMU and Cache peripherals for accessing ROM code and data.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
*
****************************************************************************/
-int board_twai_setup(void)
-{
-#ifdef CONFIG_ESP32S2_TWAI
- struct can_dev_s *twai;
- int ret;
-
- /* Call esp32s2_twaiinitialize() to get an instance of the TWAI
- * interface
- * */
-
- twai = esp32s2_twaiinitialize();
- if (twai == NULL)
- {
- canerr("ERROR: Failed to get TWAI interface\n");
- return -ENODEV;
- }
+int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
+ uint32_t app_drom_size, uint32_t app_irom_start,
+ uint32_t app_irom_vaddr, uint32_t app_irom_size);
- /* Register the TWAI driver at "/dev/can0" */
-
- ret = can_register("/dev/can0", twai);
- if (ret < 0)
- {
- canerr("ERROR: TWAI1 register failed: %d\n", ret);
- return ret;
- }
-
- return OK;
-#else
- return -ENODEV;
-#endif
+#undef EXTERN
+#if defined(__cplusplus)
}
+#endif
-#endif /* CONFIG_CAN */
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_XTENSA_SRC_ESP32S2_LOADER_H */
diff --git a/boards/xtensa/esp32s2/common/scripts/flat_memory.ld b/boards/xtensa/esp32s2/common/scripts/flat_memory.ld
index a4fde38598..108fad0083 100644
--- a/boards/xtensa/esp32s2/common/scripts/flat_memory.ld
+++ b/boards/xtensa/esp32s2/common/scripts/flat_memory.ld
@@ -72,6 +72,16 @@ MEMORY
metadata (RX) : org = CONFIG_ESP32S2_APP_MCUBOOT_HEADER_SIZE, len = 0x20
ROM (RX) : org = ORIGIN(metadata) + LENGTH(metadata),
len = FLASH_SIZE - ORIGIN(ROM)
+#elif defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
+ /* The 0x20 offset is a convenience for the app binary image generation.
+ * Flash cache has 64KB pages. The .bin file which is flashed to the chip
+ * has a 0x18 byte file header, and each segment has a 0x08 byte segment
+ * header. Setting this offset makes it simple to meet the flash cache MMU's
+ * constraint that (paddr % 64KB == vaddr % 64KB).
+ */
+
+ ROM (RX) : org = 0x20,
+ len = FLASH_SIZE - ORIGIN(ROM)
#endif
/* Below values assume the flash cache is on, and have the blocks this
diff --git a/boards/xtensa/esp32s2/common/scripts/mcuboot_sections.ld b/boards/xtensa/esp32s2/common/scripts/mcuboot_sections.ld
index dfc0790ff3..3b793eee4e 100644
--- a/boards/xtensa/esp32s2/common/scripts/mcuboot_sections.ld
+++ b/boards/xtensa/esp32s2/common/scripts/mcuboot_sections.ld
@@ -62,8 +62,14 @@ SECTIONS
.flash.rodata :
{
_srodata = ABSOLUTE(.);
- *(EXCLUDE_FILE (esp32s2_start.*) .rodata)
- *(EXCLUDE_FILE (esp32s2_start.*) .rodata.*)
+ *(EXCLUDE_FILE (esp32s2_start.* loader.* esp32s2_region.*
+ *libarch.a:esp32s2_spiflash.*
+ *libarch.a:*cache_hal.* *libarch.a:*mmu_hal.*
+ *libarch.a:*mpu_hal.*) .rodata)
+ *(EXCLUDE_FILE (esp32s2_start.* loader.* esp32s2_region.*
+ *libarch.a:esp32s2_spiflash.*
+ *libarch.a:*cache_hal.* *libarch.a:*mmu_hal.*
+ *libarch.a:*mpu_hal.*) .rodata.*)
*(.srodata.*)
@@ -161,6 +167,14 @@ SECTIONS
*(.iram1 .iram1.*)
esp32s2_start.*(.literal .text .literal.* .text.*)
+ esp32s2_region.*(.text .text.* .literal .literal.*)
+ loader.*(.text .text.* .literal .literal.*)
+
+ *libarch.a:esp32s2_spiflash.*(.literal .text .literal.* .text.*)
+ *libarch.a:*cache_hal.*(.text .text.* .literal .literal.*)
+ *libarch.a:*uart_hal.*(.text .text.* .literal .literal.*)
+ *libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*)
+ *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*)
/* align + add 16B for CPU dummy speculative instr. fetch */
@@ -233,6 +247,15 @@ SECTIONS
KEEP (*(.jcr))
*(.dram1 .dram1.*)
esp32s2_start.*(.rodata .rodata.*)
+ esp32s2_region.*(.rodata .rodata.*)
+ loader.*(.rodata .rodata.*)
+
+ *libarch.a:esp32s2_spiflash.*(.rodata .rodata.*)
+ *libarch.a:*cache_hal.*(.rodata .rodata.*)
+ *libarch.a:*uart_hal.*(.rodata .rodata.*)
+ *libarch.a:*mpu_hal.*(.rodata .rodata.*)
+ *libarch.a:*mmu_hal.*(.rodata .rodata.*)
+
_edata = ABSOLUTE(.);
. = ALIGN(4);
@@ -254,7 +277,7 @@ SECTIONS
_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma;
/* The alignment of the ".flash.text" output section is forced to
- * 0x0000FFFF (64KB) to ensure that it will be allocated at the beginning
+ * 0x00010000 (64KB) to ensure that it will be allocated at the beginning
* of the next available Flash block.
* This is required to meet the following constraint from the external
* flash MMU:
@@ -264,7 +287,7 @@ SECTIONS
* be equal.
*/
- .flash_text_dummy (NOLOAD) : ALIGN(0x0000FFFF)
+ .flash_text_dummy (NOLOAD) : ALIGN(0x00010000)
{
/* This section is required to skip .flash.rodata area because irom0_0_seg
* and drom0_0_seg reflect the same address space on different buses.
@@ -273,7 +296,7 @@ SECTIONS
. = SIZEOF(.flash.rodata);
} >irom0_0_seg
- .flash.text : ALIGN(0x0000FFFF)
+ .flash.text : ALIGN(0x00010000)
{
_stext = .;
@@ -307,7 +330,7 @@ SECTIONS
.rtc.bss (NOLOAD) :
{
*(.rtc.bss)
- } >rtc_data_seg
+ } >rtc_slow_seg
.rtc.data :
{
@@ -318,5 +341,5 @@ SECTIONS
. = ALIGN (4);
_srtcheap = ABSOLUTE(.);
- } >rtc_data_seg AT>ROM
+ } >rtc_slow_seg AT>ROM
}
diff --git a/boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld b/boards/xtensa/esp32s2/common/scripts/simple_boot_sections.ld
similarity index 62%
copy from boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld
copy to boards/xtensa/esp32s2/common/scripts/simple_boot_sections.ld
index a7c15d17ba..8a5e259b25 100644
--- a/boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld
+++ b/boards/xtensa/esp32s2/common/scripts/simple_boot_sections.ld
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld
+ * boards/xtensa/esp32s2/common/scripts/simple_boot_sections.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,19 +18,15 @@
*
****************************************************************************/
-#include <nuttx/config.h>
-
/* Default entry point: */
ENTRY(__start);
-_diram_i_start = 0x40378000;
-
SECTIONS
{
/* Send .iram0 code to iram */
- .iram0.vectors :
+ .iram0.vectors : ALIGN(4)
{
_iram_start = ABSOLUTE(.);
@@ -63,82 +59,22 @@ SECTIONS
. = 0x400;
*(.*_vector.literal)
- . = ALIGN(16);
-
+ . = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
_init_end = ABSOLUTE(.);
} >iram0_0_seg AT>ROM
- .iram0.text :
+ .iram0.text : ALIGN(4)
{
/* Code marked as running out of IRAM */
*(.iram1 .iram1.*)
- esp32s3_start.*(.literal .text .literal.* .text.*)
-
- *libarch.a:esp32s3_cpuindex.*(.literal .text .literal.* .text.*)
- *libarch.a:esp32s3_irq.*(.literal .text .literal.* .text.*)
- *libarch.a:esp32s3_user.*(.literal .text .literal.* .text.*)
- *libarch.a:esp32s3_spiflash.*(.literal .text .literal.* .text.*)
- *libarch.a:xtensa_assert.*(.literal .text .literal.* .text.*)
- *libarch.a:xtensa_cpuint.*(.literal .text .literal.* .text.*)
- *libarch.a:xtensa_cpupause.*(.literal .text .literal.* .text.*)
- *libarch.a:xtensa_irqdispatch.*(.literal .text .literal.* .text.*)
- *libarch.a:xtensa_modifyreg32.*(.literal .text .literal.* .text.*)
- *libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*)
-
-#ifdef CONFIG_ESP32S3_BLE
- *libc.a:sq_remlast.*(.literal .text .literal.* .text.*)
-#endif
-
- *libdrivers.a:syslog_flush.*(.literal .text .literal.* .text.*)
-
- *libsched.a:assert.*(.literal .text .literal.* .text.*)
- *libsched.a:irq_csection.*(.literal .text .literal.* .text.*)
- *libsched.a:irq_dispatch.*(.literal .text .literal.* .text.*)
- *libsched.a:irq_spinlock.*(.literal .text .literal.* .text.*)
- *libsched.a:sched_note.*(.literal .text .literal.* .text.*)
- *libsched.a:sched_suspendscheduler.*(.literal .text .literal.* .text.*)
- *libsched.a:sched_thistask.*(.literal .text .literal.* .text.*)
- *libsched.a:spinlock.*(.literal .text .literal.* .text.*)
- *libsched.a:*sched_get_stackinfo.*(.literal .text .literal.* .text.*)
-
-#ifdef CONFIG_ESP32S3_SPEED_UP_ISR
- *libarch.a:xtensa_switchcontext.*(.literal.up_switch_context .text.up_switch_context)
-
- *libarch.a:esp32s3_timerisr.*(.literal.systimer_isr .text.systimer_isr)
- *libarch.a:esp32s3_idle.*(.literal.up_idle .text.up_idle)
- *libarch.a:esp32s3_dma.*(.literal.esp32s3_dma_load .text.esp32s3_dma_load \
- .literal.esp32s3_dma_enable .text.esp32s3_dma_enable)
-
- *libsched.a:sched_processtimer.*(.literal.nxsched_process_timer .text.nxsched_process_timer)
- *libsched.a:clock_initialize.*(.literal.clock_timer .text.clock_timer)
- *libsched.a:wd_start.*(.literal.wd_timer .text.wd_timer)
- *libsched.a:sched_roundrobin.*(.literal.nxsched_process_roundrobin .text.nxsched_process_roundrobin)
- *libsched.a:sched_reprioritizertr.*(.literal.nxsched_reprioritize_rtr .text.nxsched_reprioritize_rtr)
- *libsched.a:sched_removereadytorun.*(.literal.nxsched_remove_readytorun .text.nxsched_remove_readytorun)
- *libsched.a:sched_addreadytorun.*(.literal.nxsched_add_readytorun .text.nxsched_add_readytorun)
- *libsched.a:sched_addprioritized.*(.literal.nxsched_add_prioritized .text.nxsched_add_prioritized)
- *libsched.a:sched_mergepending.*(.literal.nxsched_merge_pending .text.nxsched_merge_pending)
- *libsched.a:sched_resumescheduler.*(.literal.nxsched_resume_scheduler .text.nxsched_resume_scheduler)
-
- *libc.a:sq_remfirst.*(.literal.sq_remfirst .text.sq_remfirst)
-#endif
-
- *libarch.a:esp32s3_spi_timing.*(.literal .text .literal.* .text.*)
-#ifdef CONFIG_ESP32S3_SPIRAM_MODE_QUAD
- *libarch.a:esp32s3_psram_quad.*(.literal .text .literal.* .text.*)
-#endif
-#ifdef CONFIG_ESP32S3_SPIRAM_MODE_OCT
- *libarch.a:esp32s3_psram_octal.*(.literal .text .literal.* .text.*)
-#endif
-#if defined(CONFIG_STACK_CANARIES) && \
- (defined(CONFIG_ESP32S3_SPIFLASH) || \
- defined(CONFIG_ESP32S3_SPIRAM))
- *libc.a:lib_stackchk.*(.literal .text .literal.* .text.*)
-#endif
+ . = ALIGN (4);
+ esp32s2_start.*(.literal .text .literal.* .text.*)
+ esp32s2_region.*(.text .text.* .literal .literal.*)
+ loader.*(.literal .text .literal.* .text.*)
*libarch.a:*brownout_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*cpu.*(.text .text.* .literal .literal.*)
@@ -146,6 +82,7 @@ SECTIONS
*libarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*)
*libarch.a:*clk.*(.text .text.* .literal .literal.*)
*libarch.a:*efuse_hal.*(.literal.is_eco0 .text.is_eco0)
+ *libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_clk.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*)
@@ -164,9 +101,9 @@ SECTIONS
*libarch.a:*bootloader_common_loader.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_console.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_console_loader.*(.text .text.* .literal .literal.*)
- *libarch.a:*bootloader_esp32s3.*(.text .text.* .literal .literal.*)
+ *libarch.a:*bootloader_esp32s2.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_flash.*(.text .text.* .literal .literal.*)
- *libarch.a:*bootloader_flash_config_esp32s3.*(.text .text.* .literal .literal.*)
+ *libarch.a:*bootloader_flash_config_esp32s2.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_clock_init.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_clock_loader.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_efuse.*(.text .text.* .literal .literal.*)
@@ -175,7 +112,7 @@ SECTIONS
*libarch.a:*bootloader_random.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
*libarch.a:*bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
- *libarch.a:*bootloader_random_esp32s3.*(.text .text.* .literal .literal.*)
+ *libarch.a:*bootloader_random_esp32s2.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_image_format.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_soc.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_sha.*(.text .text.* .literal .literal.*)
@@ -184,7 +121,6 @@ SECTIONS
*libarch.a:*uart_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*)
- *libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*uart_periph.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*)
@@ -196,31 +132,28 @@ SECTIONS
*libarch.a:*log.*(.text .text.* .literal .literal.*)
*libarch.a:*log_noos.*(.text .text.* .literal .literal.*)
*libarch.a:*cpu_region_protect.*(.text .text.* .literal .literal.*)
- *libarch.a:*mspi_timing_tuning.*(.text .text.* .literal .literal.*)
-
- *libc.a:*lib_instrument.*(.text .text.* .literal .literal.*)
-
- *(.wifirxiram .wifirxiram.*)
- *(.wifi0iram .wifi0iram.*)
- *(.wifiorslpiram .wifiorslpiram.*)
- *(.wifislpiram .wifislpiram.*)
- *(.wifislprxiram .wifislprxiram.*)
- *(.phyiram .phyiram.*)
/* align + add 16B for CPU dummy speculative instr. fetch */
. = ALIGN(4) + 16;
-
_iram_text = ABSOLUTE(.);
- } >iram0_0_seg AT > ROM
+ } >iram0_0_seg AT>ROM
- .dram0.dummy (NOLOAD) :
+ /* Marks the end of IRAM code segment */
+
+ .iram0.text_end (NOLOAD) :
+ {
+ . = ALIGN (4);
+ _iram_end = ABSOLUTE(.);
+ } >iram0_0_seg
+
+ .dram0.dummy (NOLOAD):
{
/* This section is required to skip .iram0.text area because iram0_0_seg
* and dram0_0_seg reflect the same address space on different buses.
*/
- . = ORIGIN(dram0_0_seg) + MAX(_iram_end, _diram_i_start) - _diram_i_start;
+ . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
} >dram0_0_seg
/* Shared RAM */
@@ -229,12 +162,9 @@ SECTIONS
{
/* .bss initialized on power-up */
- . = ALIGN(8);
+ . = ALIGN (8);
_bss_start = ABSOLUTE(.);
_sbss = ABSOLUTE(.);
-
- *(.bss .bss.*)
- *(COMMON)
*(.dynsbss)
*(.sbss)
*(.sbss.*)
@@ -244,31 +174,32 @@ SECTIONS
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
+ KEEP (*(.bss))
+ *(.bss.*)
*(.share.mem)
*(.gnu.linkonce.b.*)
-
+ *(COMMON)
. = ALIGN(8);
_ebss = ABSOLUTE(.);
_bss_end = ABSOLUTE(.);
} >dram0_0_seg
- .noinit (NOLOAD) :
+ .noinit (NOLOAD):
{
/* This section contains data that is not initialized during load,
* or during the application's initialization sequence.
*/
. = ALIGN(4);
-
- *(.noinit .noinit.*)
-
+ *(.noinit)
+ *(.noinit.*)
. = ALIGN(4);
} >dram0_0_seg
- .dram0.data :
+ .dram0.data : ALIGN(4)
{
/* .data initialized on power-up in ROMed configurations. */
- . = ALIGN (16);
+
_data_start = ABSOLUTE(.);
_sdata = ABSOLUTE(.);
KEEP (*(.data))
@@ -283,18 +214,10 @@ SECTIONS
KEEP (*(.gnu.linkonce.s2.*))
KEEP (*(.jcr))
*(.dram1 .dram1.*)
- esp32s3_start.*(.rodata .rodata.*)
-
- *libphy.a:(.rodata .rodata.*)
- *libarch.a:xtensa_context.*(.rodata .rodata.*)
-#if defined(CONFIG_STACK_CANARIES) && \
- (defined(CONFIG_ESP32S3_SPIFLASH) || \
- defined(CONFIG_ESP32S3_SPIRAM))
- *libc.a:lib_stackchk.*(.rodata .rodata.*)
-#endif
-
- *libsched.a:*sched_get_stackinfo.*(.rodata .rodata.*)
- *libarch.a:esp32s3_spiflash.*(.rodata .rodata.*)
+ esp32s2_start.*(.rodata .rodata.*)
+ esp32s2_region.*(.rodata .rodata.*)
+ loader.*(.rodata .rodata.*)
+
*libarch.a:*brownout.*(.rodata .rodata.*)
*libarch.a:*cpu.*(.rodata .rodata.*)
*libarch.a:*gpio_hal.*(.rodata .rodata.*)
@@ -318,16 +241,16 @@ SECTIONS
*libarch.a:*bootloader_common_loader.*(.rodata .rodata.*)
*libarch.a:*bootloader_console.*(.rodata .rodata.*)
*libarch.a:*bootloader_console_loader.*(.rodata .rodata.*)
- *libarch.a:*bootloader_esp32s3.*(.rodata .rodata.*)
+ *libarch.a:*bootloader_esp32s2.*(.rodata .rodata.*)
*libarch.a:*bootloader_flash.*(.rodata .rodata.*)
- *libarch.a:*bootloader_flash_config_esp32s3.*(.rodata .rodata.*)
+ *libarch.a:*bootloader_flash_config_esp32s2.*(.rodata .rodata.*)
*libarch.a:*bootloader_clock_init.*(.rodata .rodata.*)
*libarch.a:*bootloader_clock_loader.*(.rodata .rodata.*)
*libarch.a:*bootloader_efuse.*(.rodata .rodata.*)
*libarch.a:*bootloader_panic.*(.rodata .rodata.*)
*libarch.a:*bootloader_mem.*(.rodata .rodata.*)
*libarch.a:*bootloader_random.*(.rodata .rodata.*)
- *libarch.a:*bootloader_random_esp32s3.*(.rodata .rodata.*)
+ *libarch.a:*bootloader_random_esp32s2.*(.rodata .rodata.*)
*libarch.a:*esp_image_format.*(.rodata .rodata.*)
*libarch.a:*bootloader_soc.*(.rodata .rodata.*)
*libarch.a:*bootloader_sha.*(.rodata .rodata.*)
@@ -347,13 +270,6 @@ SECTIONS
*libarch.a:*log.*(.rodata .rodata.*)
*libarch.a:*log_noos.*(.rodata .rodata.*)
*libarch.a:*cpu_region_protect.*(.rodata .rodata.*)
- *libarch.a:*mspi_timing_tuning.*(.rodata .rodata.*)
-#ifdef CONFIG_ESP32S3_SPIRAM_MODE_QUAD
- *libarch.a:esp32s3_psram_quad.*(.rodata .rodata.*)
-#endif
-#ifdef CONFIG_ESP32S3_SPIRAM_MODE_OCT
- *libarch.a:esp32s3_psram_octal.*(.rodata .rodata.*)
-#endif
. = ALIGN(4);
_edata = ABSOLUTE(.);
@@ -386,33 +302,24 @@ SECTIONS
.flash.rodata :
{
- _rodata_reserved_start = ABSOLUTE(.);
-
_srodata = ABSOLUTE(.);
- *(EXCLUDE_FILE (esp32s3_start.*) .rodata)
- *(EXCLUDE_FILE (esp32s3_start.*) .rodata.*)
+ *(EXCLUDE_FILE (esp32s2_start.*) .rodata)
+ *(EXCLUDE_FILE (esp32s2_start.*) .rodata.*)
+ *(.srodata.*)
*(.rodata)
*(.rodata.*)
-#ifdef CONFIG_ESP32S3_WIRELESS
- *(.rodata_wlog_verbose.*)
- *(.rodata_wlog_debug.*)
- *(.rodata_wlog_info.*)
- *(.rodata_wlog_warning.*)
- *(.rodata_wlog_error.*)
-#endif
+
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
- *(.gcc_except_table)
- *(.gcc_except_table.*)
+ *(.gcc_except_table .gcc_except_table.*)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
- *(.eh_frame)
-
- . = ALIGN(4);
+ KEEP(*(.eh_frame))
+ . = (. + 3) & ~ 3;
/* C++ constructor and destructor tables, properly ordered: */
@@ -436,6 +343,7 @@ SECTIONS
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
+ . = ALIGN(4); /* This table MUST be 4-byte aligned */
_erodata = ABSOLUTE(.);
/* Literals are also RO data. */
@@ -446,24 +354,23 @@ SECTIONS
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
- } >drom0_0_seg AT>ROM
-
- .flash.rodata_noload (NOLOAD) :
- {
- /*
- This is a symbol marking the flash.rodata end, this can be
- used for mmu driver to maintain virtual address
- We don't need to include the noload rodata in this section
- */
- _rodata_reserved_end = ABSOLUTE(.);
- . = ALIGN (4);
- mapping[rodata_noload]
- } >drom0_0_seg
+ } >default_rodata_seg AT>ROM
_image_irom_vma = ADDR(.flash.text);
_image_irom_lma = LOADADDR(.flash.text);
_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma;
+ /* The alignment of the ".flash.text" output section is forced to
+ * 0x0000FFFF (64KB) to ensure that it will be allocated at the beginning
+ * of the next available Flash block.
+ * This is required to meet the following constraint from the external
+ * flash MMU:
+ * VMA % 64KB == LMA % 64KB
+ * i.e. the lower 16 bits of both the virtual address (address seen by the
+ * CPU) and the load address (physical address of the external flash) must
+ * be equal.
+ */
+
.flash.text_dummy (NOLOAD) :
{
. += SIZEOF(.flash.rodata);
@@ -473,57 +380,18 @@ SECTIONS
.flash.text :
{
_stext = .;
- _instruction_reserved_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
-
- /* CPU will try to prefetch up to 16 bytes of instructions.
- * This means that any configuration (e.g. MMU, PMS) must allow
- * safe access to up to 16 bytes after the last real instruction, add
- * dummy bytes to ensure this
- */
+ . = ALIGN(4);
. += 16;
- _instruction_reserved_end = ABSOLUTE(.);
_etext = .;
- } >irom0_0_seg AT>ROM
-
- /* Marks the end of IRAM code segment */
-
- .iram0.text_end (NOLOAD) :
- {
- /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and
- * 256B alignment for PMS split lines.
- */
-
- . += 16;
- . = ALIGN(256);
- _iram_end = ABSOLUTE(.);
- } >iram0_0_seg
-
- .iram0.data :
- {
- . = ALIGN(4);
-
- *(.iram.data)
- *(.iram.data.*)
- } >iram0_0_seg
-
- .iram0.bss (NOLOAD) :
- {
- . = ALIGN(4);
-
- *(.iram.bss)
- *(.iram.bss.*)
-
- . = ALIGN(4);
- _iram_end = ABSOLUTE(.);
- } >iram0_0_seg
+ } >default_code_seg AT>ROM
.rtc.text :
{
@@ -531,6 +399,15 @@ SECTIONS
*(.rtc.literal .rtc.text)
} >rtc_iram_seg AT>ROM
+ .rtc.dummy (NOLOAD) :
+ {
+ /* This section is required to skip .rtc.text area because the text and
+ * data segments reflect the same address space on different buses.
+ */
+
+ . = SIZEOF(.rtc.text);
+ } >rtc_data_seg
+
/* RTC BSS section. */
.rtc.bss (NOLOAD) :
@@ -540,33 +417,12 @@ SECTIONS
.rtc.data :
{
- . = ALIGN(4);
*(.rtc.data)
- *(.rtc.data.*)
*(.rtc.rodata)
- *(.rtc.rodata.*)
- /* Whatever is left from the RTC memory is used as a special heap. */
+ /* Whatever is left from the RTC memory is used as a special heap. */
. = ALIGN (4);
_srtcheap = ABSOLUTE(.);
- } >rtc_slow_seg
-
- /*
- * This section holds RTC data that should have fixed addresses.
- * The data are not initialized at power-up and are retained during deep sleep.
- */
- .rtc_reserved (NOLOAD):
- {
- . = ALIGN(4);
- _rtc_reserved_start = ABSOLUTE(.);
- /* New data can only be added here to ensure existing data are not moved.
- Because data have adhered to the end of the segment and code is relied on it.
- >> put new data here << */
-
- *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
- KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
- _rtc_reserved_end = ABSOLUTE(.);
- } > rtc_reserved_seg
-
+ } >rtc_slow_seg AT>ROM
}
diff --git a/boards/xtensa/esp32s2/common/src/Make.defs b/boards/xtensa/esp32s2/common/src/Make.defs
index 2fde45ed4c..bb59ccdeeb 100644
--- a/boards/xtensa/esp32s2/common/src/Make.defs
+++ b/boards/xtensa/esp32s2/common/src/Make.defs
@@ -72,6 +72,15 @@ ifeq ($(CONFIG_ESP_RMT),y)
CSRCS += esp32s2_board_rmt.c
endif
+ifeq ($(CONFIG_ESP32S2_TWAI)$(CONFIG_ARCH_BUTTONS),y)
+ CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES))
+ CHIPHALDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)chip$(DELIM)esp-hal-3rdparty
+ CFLAGS += -Wno-undef
+ CFLAGS += ${INCDIR_PREFIX}$(CHIPHALDIR)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include
+ CFLAGS += ${INCDIR_PREFIX}$(CHIPHALDIR)$(DELIM)components$(DELIM)esp_common$(DELIM)include
+ CFLAGS += ${INCDIR_PREFIX}$(CHIPHALDIR)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include
+endif
+
DEPPATH += --dep-path src
VPATH += :src
CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src
diff --git a/boards/xtensa/esp32s2/common/src/esp32s2_board_twai.c b/boards/xtensa/esp32s2/common/src/esp32s2_board_twai.c
index 73c56476ac..5cf7aa83bf 100644
--- a/boards/xtensa/esp32s2/common/src/esp32s2_board_twai.c
+++ b/boards/xtensa/esp32s2/common/src/esp32s2_board_twai.c
@@ -30,8 +30,6 @@
#include <nuttx/can/can.h>
#include <arch/board/board.h>
-#include "chip.h"
-
#include "esp32s2_twai.h"
#ifdef CONFIG_CAN
diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/scripts/Make.defs b/boards/xtensa/esp32s2/esp32s2-kaluga-1/scripts/Make.defs
index d91a4b141d..d0490b384b 100644
--- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/scripts/Make.defs
+++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/scripts/Make.defs
@@ -33,6 +33,8 @@ ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ifeq ($(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
+else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+ ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif
diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs
index f4386876f5..8c4e097bfb 100644
--- a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs
+++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs
@@ -33,6 +33,8 @@ ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ifeq ($(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
+else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+ ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif
diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_ledc.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_ledc.c
index 57241a0a34..00e8a2a95d 100644
--- a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_ledc.c
+++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_ledc.c
@@ -33,7 +33,6 @@
#include <arch/board/board.h>
-#include "chip.h"
#include "esp32s2_ledc.h"
/****************************************************************************
diff --git a/boards/xtensa/esp32s2/franzininho-wifi/scripts/Make.defs b/boards/xtensa/esp32s2/franzininho-wifi/scripts/Make.defs
index f285b29490..6a1ccb8073 100644
--- a/boards/xtensa/esp32s2/franzininho-wifi/scripts/Make.defs
+++ b/boards/xtensa/esp32s2/franzininho-wifi/scripts/Make.defs
@@ -33,6 +33,8 @@ ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ifeq ($(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
+else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+ ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif
diff --git a/boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld b/boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld
index a7c15d17ba..3ce09f1c3d 100644
--- a/boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld
+++ b/boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld
+ * boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
diff --git a/tools/esp32/Config.mk b/tools/esp32/Config.mk
index fc8b18a71c..2e3e6ee562 100644
--- a/tools/esp32/Config.mk
+++ b/tools/esp32/Config.mk
@@ -229,7 +229,7 @@ define MKIMAGE
$(Q) echo "MKIMAGE: ESP32 binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
- echo "esptool.py not found. Please run: \"pip install esptool\""; \
+ echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
exit 1; \
diff --git a/tools/esp32c3/Config.mk b/tools/esp32c3/Config.mk
index 1a2663fb21..96e4a2e11a 100644
--- a/tools/esp32c3/Config.mk
+++ b/tools/esp32c3/Config.mk
@@ -218,7 +218,7 @@ define MKIMAGE
$(Q) echo "MKIMAGE: ESP32-C3 binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
- echo "esptool.py not found. Please run: \"pip install esptool\""; \
+ echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
exit 1; \
diff --git a/tools/esp32c6/Config.mk b/tools/esp32c6/Config.mk
index f07f590f22..181d90a6e8 100644
--- a/tools/esp32c6/Config.mk
+++ b/tools/esp32c6/Config.mk
@@ -47,7 +47,7 @@ define POSTBUILD
$(Q) echo "MKIMAGE: ESP32-C6 binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
- echo "esptool.py not found. Please run: \"pip install esptool\""; \
+ echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
echo "Or run: \"make -C $(TOPDIR)/tools/esp32c6\" to install all IDF tools."; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
diff --git a/tools/esp32s2/Config.mk b/tools/esp32s2/Config.mk
index 769a4bd656..c863f3fd3f 100644
--- a/tools/esp32s2/Config.mk
+++ b/tools/esp32s2/Config.mk
@@ -124,6 +124,13 @@ else ifeq ($(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT),y)
IMGTOOL_SIGN_ARGS := --pad $(VERIFIED) $(IMGTOOL_ALIGN_ARGS) -v 0 -s auto \
-H $(CONFIG_ESP32S2_APP_MCUBOOT_HEADER_SIZE) --pad-header \
-S $(CONFIG_ESP32S2_OTA_SLOT_SIZE)
+else
+# CONFIG_ESPRESSIF_SIMPLE_BOOT
+
+ APP_OFFSET := 0x1000
+ APP_IMAGE := nuttx.bin
+ FLASH_APP := $(APP_OFFSET) $(APP_IMAGE)
+ ESPTOOL_BINDIR := .
endif
ESPTOOL_BINS += $(FLASH_APP)
@@ -214,7 +221,7 @@ define MKIMAGE
$(Q) echo "MKIMAGE: ESP32-S2 binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
- echo "esptool.py not found. Please run: \"pip install esptool\""; \
+ echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
exit 1; \
@@ -241,6 +248,25 @@ define MKIMAGE
$(Q) echo nuttx.bin >> nuttx.manifest
$(Q) echo "Generated: nuttx.bin (MCUboot compatible)"
endef
+else
+define MKIMAGE
+ $(Q) echo "MKIMAGE: ESP32-S2 binary"
+ $(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
+ echo ""; \
+ echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
+ echo ""; \
+ echo "Run make again to create the nuttx.bin image."; \
+ exit 1; \
+ fi
+ $(Q) if [ -z $(FLASH_SIZE) ]; then \
+ echo "Missing Flash memory size configuration."; \
+ exit 1; \
+ fi
+ $(eval ELF2IMAGE_OPTS := $(if $(CONFIG_ESPRESSIF_SIMPLE_BOOT),--ram-only-header) -fs $(FLASH_SIZE) -fm $(FLASH_MODE) -ff $(FLASH_FREQ))
+ esptool.py -c esp32s2 elf2image $(ELF2IMAGE_OPTS) -o nuttx.bin nuttx
+ $(Q) echo nuttx.bin >> nuttx.manifest
+ $(Q) echo "Generated: nuttx.bin"
+endef
endif
endif
diff --git a/tools/esp32s3/Config.mk b/tools/esp32s3/Config.mk
index b44c081a0a..e7a0b614cd 100644
--- a/tools/esp32s3/Config.mk
+++ b/tools/esp32s3/Config.mk
@@ -137,7 +137,7 @@ define MKIMAGE
$(Q) echo "MKIMAGE: ESP32-S3 binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
- echo "esptool.py not found. Please run: \"pip install esptool\""; \
+ echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
exit 1; \
@@ -169,7 +169,7 @@ define MKIMAGE
$(Q) echo "MKIMAGE: ESP32-S3 binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
- echo "esptool.py not found. Please run: \"pip install esptool\""; \
+ echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
exit 1; \
diff --git a/tools/espressif/Config.mk b/tools/espressif/Config.mk
index e2d9b4cb8d..9700917bcf 100644
--- a/tools/espressif/Config.mk
+++ b/tools/espressif/Config.mk
@@ -155,7 +155,7 @@ define MKIMAGE
$(Q) echo "MKIMAGE: NuttX binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
- echo "esptool.py not found. Please run: \"pip install esptool\""; \
+ echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
exit 1; \