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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/09/21 10:07:12 UTC
[incubator-nuttx] 02/04: armv7a/r: refact cp15_cache functions

This is an automated email from the ASF dual-hosted git repository.

xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git

commit 6d92810d5a8d6a02e8737a91821f7ef82c8ee1b2
Author: ligd <li...@xiaomi.com>
AuthorDate: Fri Sep 16 14:31:52 2022 +0800

    armv7a/r: refact cp15_cache functions
    
    Signed-off-by: ligd <li...@xiaomi.com>
---
 arch/arm/src/armv7-a/Make.defs                    |   8 +-
 arch/arm/src/armv7-a/cp15_cache_size.S            |  85 --------
 arch/arm/src/armv7-a/cp15_cacheops.c              | 245 ++++++++++++++++++++++
 arch/arm/src/armv7-a/cp15_clean_dcache.S          | 116 ----------
 arch/arm/src/armv7-a/cp15_clean_dcache_all.S      | 127 -----------
 arch/arm/src/armv7-a/cp15_coherent_dcache.S       | 138 ------------
 arch/arm/src/armv7-a/cp15_flush_dcache.S          | 116 ----------
 arch/arm/src/armv7-a/cp15_flush_dcache_all.S      | 128 -----------
 arch/arm/src/armv7-a/cp15_invalidate_dcache.S     | 123 -----------
 arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S | 128 -----------
 arch/arm/src/armv7-r/Make.defs                    |   9 +-
 arch/arm/src/armv7-r/cp15_cache_size.S            |  84 --------
 arch/arm/src/armv7-r/cp15_cacheops.c              | 245 ++++++++++++++++++++++
 arch/arm/src/armv7-r/cp15_clean_dcache.S          | 116 ----------
 arch/arm/src/armv7-r/cp15_clean_dcache_all.S      | 129 ------------
 arch/arm/src/armv7-r/cp15_coherent_dcache.S       | 140 -------------
 arch/arm/src/armv7-r/cp15_flush_dcache.S          | 116 ----------
 arch/arm/src/armv7-r/cp15_flush_dcache_all.S      | 129 ------------
 arch/arm/src/armv7-r/cp15_invalidate_dcache.S     | 123 -----------
 arch/arm/src/armv7-r/cp15_invalidate_dcache_all.S | 128 -----------
 20 files changed, 494 insertions(+), 1939 deletions(-)

diff --git a/arch/arm/src/armv7-a/Make.defs b/arch/arm/src/armv7-a/Make.defs
index 2ab71d59b2..791275125d 100644
--- a/arch/arm/src/armv7-a/Make.defs
+++ b/arch/arm/src/armv7-a/Make.defs
@@ -36,11 +36,7 @@ endif
 
 # Common assembly language files
 
-CMN_ASRCS += arm_cpuhead.S arm_vectoraddrexcptn.S
-CMN_ASRCS += arm_vectors.S cp15_cache_size.S cp15_clean_dcache_all.S
-CMN_ASRCS += cp15_clean_dcache.S cp15_coherent_dcache.S
-CMN_ASRCS += cp15_flush_dcache_all.S cp15_flush_dcache.S
-CMN_ASRCS += cp15_invalidate_dcache_all.S cp15_invalidate_dcache.S
+CMN_ASRCS += arm_cpuhead.S arm_vectoraddrexcptn.S arm_vectors.S
 
 # Common C source files
 
@@ -49,7 +45,7 @@ CMN_CSRCS += arm_doirq.c arm_gicv2.c arm_gicv2_dump.c
 CMN_CSRCS += arm_initialstate.c arm_mmu.c arm_prefetchabort.c
 CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
 CMN_CSRCS += arm_syscall.c arm_tcbinfo.c arm_undefinedinsn.c
-CMN_CSRCS += arm_perf.c
+CMN_CSRCS += arm_perf.c cp15_cacheops.c
 
 ifeq ($(CONFIG_ARMV7A_HAVE_PTM), y)
   CMN_CSRCS += arm_timer.c
diff --git a/arch/arm/src/armv7-a/cp15_cache_size.S b/arch/arm/src/armv7-a/cp15_cache_size.S
deleted file mode 100644
index e53aac1d72..0000000000
--- a/arch/arm/src/armv7-a/cp15_cache_size.S
+++ /dev/null
@@ -1,85 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_cache_size.S
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements.  See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.  The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License.  You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_cache_size.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_cache_size
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_cache_size
- *
- * Description:
- *   Get cp15 cache size in byte
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   Cache size in byte
- *
- ****************************************************************************/
-
-	.globl	cp15_cache_size
-	.type	cp15_cache_size, function
-
-cp15_cache_size:
-
-	mrc		CP15_CCSIDR(r0)			/* Read the Cache Size Identification Register */
-
-	ldr		r3, =0x7fff			/* Isolate the NumSets field (bits 13-27) */
-	and		r2, r3, r0, lsr #13		/* r2=NumSets (number of sets - 1) */
-	add		r2, #1
-
-	ldr		r3, =0x3ff			/* Isolate the way field (bits 3-12) */
-	and		r1, r3, r0, lsr #3		/* r1=(number of ways - 1) */
-	add		r1, #1
-
-	ldr		r3,=0x7				/* Isolate the LineSize field (bits 0-2) */
-	and		r0, r3				/* r0=(Log2LineSize - 2) in word */
-	add		r0, #4				/* r0=Log2lineSize in byte */
-
-	mul		r2, r1, r2			/* r2=Sets*Ways */
-	lsl		r0, r2, r0			/* r0=Sets*Ways*LineSize */
-
-	bx		lr
-
-	.size cp15_cache_size, . - cp15_cache_size
-	.end
diff --git a/arch/arm/src/armv7-a/cp15_cacheops.c b/arch/arm/src/armv7-a/cp15_cacheops.c
new file mode 100644
index 0000000000..fcdf566caa
--- /dev/null
+++ b/arch/arm/src/armv7-a/cp15_cacheops.c
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/cp15_cacheops.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/cache.h>
+#include <nuttx/irq.h>
+
+#include "cp15_cacheops.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CP15_CACHE_INVALIDATE       0
+#define CP15_CACHE_CLEAN            1
+#define CP15_CACHE_CLEANINVALIDATE  2
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline uint32_t ilog2(uint32_t u)
+{
+  int i = 0;
+
+  while (u >>= 1)
+    {
+      i++;
+    }
+
+  return i;
+}
+
+static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways)
+{
+  uint32_t ccsidr = CP15_GET(CCSIDR);
+
+  if (sets)
+    {
+      *sets = ((ccsidr >> 13) & 0x7fff) + 1;
+    }
+
+  if (ways)
+    {
+      *ways = ((ccsidr >> 3) & 0x3ff) + 1;
+    }
+
+  return (1 << ((ccsidr & 0x7) + 2)) * 4;
+}
+
+static void cp15_dcache_op_level(uint32_t level, int op)
+{
+  uint32_t sets;
+  uint32_t ways;
+  uint32_t set;
+  uint32_t way;
+  uint32_t line;
+  uint32_t way_shift;
+  uint32_t set_shift;
+  uint32_t val = level << 1;
+
+  /* Select by CSSELR */
+
+  CP15_SET(CSSELR, val);
+
+  /* Get cache info */
+
+  line = cp15_cache_get_info(&sets, &ways);
+
+  way_shift = 32 - ilog2(ways);
+  set_shift = ilog2(line);
+
+  ARM_DSB();
+
+  /* A: Log2(ways)
+   * B: L+S
+   * L: Log2(line)
+   * S: Log2(sets)
+   *
+   * The bits are packed as follows:
+   *  31  31-A        B B-1    L L-1   4 3   1 0
+   * |---|-------------|--------|-------|-----|-|
+   * |Way|    zeros    |   Set  | zeros |level|0|
+   * |---|-------------|--------|-------|-----|-|
+   */
+
+  for (way = 0; way < ways; way++)
+    {
+      for (set = 0; set < sets; set++)
+        {
+          val  = level << 1;
+          val |= way << way_shift;
+          val |= set << set_shift;
+
+          switch (op)
+            {
+              case CP15_CACHE_INVALIDATE:
+                cp15_invalidate_dcacheline_bysetway(val);
+                break;
+              case CP15_CACHE_CLEAN:
+                cp15_clean_dcache_bysetway(val);
+                break;
+              case CP15_CACHE_CLEANINVALIDATE:
+                cp15_cleaninvalidate_dcacheline(val);
+                break;
+              default:
+                break;
+            }
+        }
+    }
+
+  ARM_ISB();
+}
+
+static void cp15_dcache_op(int op)
+{
+  uint32_t clidr = CP15_GET(CLIDR);
+  int level;
+
+  for (level = 0; level < 7; level++)
+    {
+      uint32_t ctype = clidr & 0x7;
+
+      switch (ctype)
+        {
+          case 0x2:
+          case 0x3:
+          case 0x4:
+            cp15_dcache_op_level(level, op);
+            break;
+          default:
+            break;
+        }
+
+      clidr >>= 3;
+      if (clidr == 0)
+        {
+          break;
+        }
+    }
+}
+
+static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
+{
+  uint32_t line;
+
+  line = cp15_cache_get_info(NULL, NULL);
+  start &= ~(line - 1);
+
+  ARM_DSB();
+
+  while (start < end)
+    {
+      switch (op)
+        {
+          case CP15_CACHE_INVALIDATE:
+            cp15_invalidate_dcacheline_bymva(start);
+            break;
+          case CP15_CACHE_CLEAN:
+            cp15_clean_dcache_bymva(start);
+            break;
+          case CP15_CACHE_CLEANINVALIDATE:
+            cp15_cleaninvalidate_dcacheline_bymva(start);
+            break;
+          default:
+            break;
+        }
+
+      start += line;
+    }
+
+  ARM_ISB();
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void cp15_coherent_dcache(uintptr_t start, uintptr_t end)
+{
+  cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
+  cp15_invalidate_icache();
+}
+
+void cp15_invalidate_dcache(uintptr_t start, uintptr_t end)
+{
+  cp15_dcache_op_mva(start, end, CP15_CACHE_INVALIDATE);
+}
+
+void cp15_invalidate_dcache_all(void)
+{
+  cp15_dcache_op(CP15_CACHE_INVALIDATE);
+}
+
+void cp15_clean_dcache(uintptr_t start, uintptr_t end)
+{
+  cp15_dcache_op_mva(start, end, CP15_CACHE_CLEAN);
+}
+
+void cp15_clean_dcache_all(void)
+{
+  cp15_dcache_op(CP15_CACHE_CLEAN);
+}
+
+void cp15_flush_dcache(uintptr_t start, uintptr_t end)
+{
+  cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
+}
+
+void cp15_flush_dcache_all(void)
+{
+  cp15_dcache_op(CP15_CACHE_CLEANINVALIDATE);
+}
+
+uint32_t cp15_cache_size(void)
+{
+  uint32_t sets;
+  uint32_t ways;
+  uint32_t line;
+
+  line = cp15_cache_get_info(&sets, &ways);
+
+  return sets * ways * line;
+}
diff --git a/arch/arm/src/armv7-a/cp15_clean_dcache.S b/arch/arm/src/armv7-a/cp15_clean_dcache.S
deleted file mode 100644
index 89f980eb67..0000000000
--- a/arch/arm/src/armv7-a/cp15_clean_dcache.S
+++ /dev/null
@@ -1,116 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_clean_dcache.S
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- *   Copyright (c) 2012, Atmel Corporation
- *   All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- *    be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- *  "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- *   Copyright (c) 2010  ARM. All rights reserved. ARM DDI 0434B (ID101810)
- *  "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- *   Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- *   DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_clean_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_clean_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_clean_dcache
- *
- * Description:
- *   Clean the data cache within the specified region by flushing the
- *   contents of the data cache to memory.
- *
- * Input Parameters:
- *   start - virtual start address of region
- *   end   - virtual end address of region + 1
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-	.globl	cp15_clean_dcache
-	.type	cp15_clean_dcache, function
-
-cp15_clean_dcache:
-
-	mrc		CP15_CTR(r3)			/* Read the Cache Type Register */
-	lsr		r3, r3, #16			/* Isolate the DMinLine field */
-	and		r3, r3, #0xf
-	mov		r2, #4
-	mov		r2, r2, lsl r3			/* Get the cache line size in bytes */
-
-	sub		r3, r2, #1			/* R3=Cache line size mask */
-	bic		r0, r0, r3			/* R0=aligned start address */
-
-	/* Loop, cleaning each cache line by writing its contents to memory */
-
-1:
-	mcr		CP15_DCCMVAC(r0)		/* Clean data cache line to PoC by VA */
-	add		r0, r0, r2			/* R12=Next cache line */
-	cmp		r0, r1				/* Loop until all cache lines have been cleaned */
-	blo		1b
-
-	dsb
-	bx		lr
-	.size cp15_clean_dcache, . - cp15_clean_dcache
-	.end
diff --git a/arch/arm/src/armv7-a/cp15_clean_dcache_all.S b/arch/arm/src/armv7-a/cp15_clean_dcache_all.S
deleted file mode 100644
index d95d31e73e..0000000000
--- a/arch/arm/src/armv7-a/cp15_clean_dcache_all.S
+++ /dev/null
@@ -1,127 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_clean_dcache_all.S
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- *   Copyright (c) 2012, Atmel Corporation
- *   All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- *    be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- *  "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- *   Copyright (c) 2010  ARM. All rights reserved. ARM DDI 0434B (ID101810)
- *  "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- *   Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- *   DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_clean_dcache_all.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_clean_dcache_all
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_clean_dcache_all
- *
- * Description:
- *   Clean the entire contents of D cache.
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-	.globl	cp15_clean_dcache_all
-	.type	cp15_clean_dcache_all, function
-
-cp15_clean_dcache_all:
-
-	push		{r4, r5}
-
-	mrc		CP15_CCSIDR(r1)			/* Read the Cache Size Identification Register */
-	ldr		r3, =0x7fff			/* Isolate the NumSets field (bits 13-27) */
-	and		r0, r3, r1, lsr #13		/* r0=NumSets (number of sets - 1) */
-
-	ldr		r3,=0x7				/* Isolate the LineSize field (bits 0-2) */
-	and		r5, r3, r1			/* r4=(Log2LineSize - 2) in word */
-	add		r5, #4				/* r4=Set/way operation line shfit */
-
-	ldr		r3, =0x3ff			/* Isolate the way field (bits 3-12) */
-	and		r1, r3, r1, lsr #3		/* r1=(number of ways - 1) */
-
-	add		r4, r1, #1
-	clz		r4, r4
-	add		r4, #1				/* r4=Set/way operation Way shift */
-
-way_loop:
-	mov		r3, r0				/* Init Sets */
-set_loop:
-	mov		r2, r1, lsl r4			/* r2 = way loop counter << way shift */
-	orr		r2, r3, lsl r5			/* r2 = set/way cache operation format */
-	mcr		CP15_DCCSW(r2)			/* Data Cache Clean by Set/Way */
-	subs		r3, r3, #1			/* Subtraction set counter */
-	bcs		set_loop			/* Keep looping if not */
-
-	subs		r1, r1, #1			/* Subtraction the way counter */
-	bcs		way_loop			/* Keep looping if not */
-
-	dsb
-	pop		{r4, r5}
-	bx		lr
-	.size cp15_clean_dcache_all, . - cp15_clean_dcache_all
-	.end
diff --git a/arch/arm/src/armv7-a/cp15_coherent_dcache.S b/arch/arm/src/armv7-a/cp15_coherent_dcache.S
deleted file mode 100644
index 88c5feb4c3..0000000000
--- a/arch/arm/src/armv7-a/cp15_coherent_dcache.S
+++ /dev/null
@@ -1,138 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_coherent_dcache.S
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- *   Copyright (c) 2012, Atmel Corporation
- *   All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- *    be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- *  "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- *   Copyright (c) 2010  ARM. All rights reserved. ARM DDI 0434B (ID101810)
- *  "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- *   Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- *   DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_coherent_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_coherent_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_coherent_dcache
- *
- * Description:
- *   Ensure that the I and D caches are coherent within specified region
- *   by cleaning the D cache (i.e., flushing the D cache contents to memory
- *   and invalidating the I cache. This is typically used when code has been
- *   written to a memory region, and will be executed.
- *
- * Input Parameters:
- *   start - virtual start address of region
- *   end   - virtual end address of region + 1
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-	.globl	cp15_coherent_dcache
-	.type	cp15_coherent_dcache, function
-
-cp15_coherent_dcache:
-	mrc		CP15_CTR(r3)			/* Read the Cache Type Register */
-	lsr		r3, r3, #16			/* Isolate the DMinLine field */
-	and		r3, r3, #0xf
-	mov		r2, #4
-	mov		r2, r2, lsl r3			/* Get the cache line size in bytes */
-
-	sub		r3, r2, #1			/* R3=Cache line size mask */
-	bic		r12, r0, r3			/* R12=aligned start address */
-
-	/* Loop, flushing each D cache line to memory */
-1:
-	mcr		CP15_DCCMVAU(r12)		/* Clean data or unified cache line by VA to PoU */
-	add		r12, r12, r2			/* R12=Next cache line */
-	cmp		r12, r1				/* Loop until all cache lines have been cleaned */
-	blo		1b
-
-	dsb
-
-	mrc		CP15_CTR(r3)			/* Read the Cache Type Register */
-	and		r3, r3, #0xf			/* Isolate the IminLine field */
-	mov		r2, #4
-	mov		r2, r2, lsl r3			/* Get the cache line size in bytes */
-
-	sub		r3, r2, #1			/* R3=Cache line size mask */
-	bic		r12, r0, r3			/* R12=aligned start address */
-
-	/* Loop, invalidating each I cache line to memory */
-1:
-	mcr		CP15_ICIMVAU(r12)		/* Invalidate instruction cache by VA to PoU */
-	add		r12, r12, r2			/* R12=Next cache line */
-	cmp		r12, r1				/* Loop until all cache lines have been invalidated */
-	blo		1b
-
-	mov		r0, #0
-	mcr		CP15_BPIALLIS(r0)		/* Invalidate entire branch predictor array Inner Shareable */
-	mcr		CP15_BPIALL(r0)			/* Invalidate entire branch predictor array Inner Shareable */
-
-	dsb
-	isb
-	bx		lr
-	.size cp15_coherent_dcache, . - cp15_coherent_dcache
-	.end
diff --git a/arch/arm/src/armv7-a/cp15_flush_dcache.S b/arch/arm/src/armv7-a/cp15_flush_dcache.S
deleted file mode 100644
index 88423cb246..0000000000
--- a/arch/arm/src/armv7-a/cp15_flush_dcache.S
+++ /dev/null
@@ -1,116 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_flush_dcache.S
- *
- *   Copyright (C) 2013, 2018 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- *   Copyright (c) 2012, Atmel Corporation
- *   All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- *    be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- *  "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- *   Copyright (c) 2010  ARM. All rights reserved. ARM DDI 0434B (ID101810)
- *  "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- *   Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- *   DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_flush_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_flush_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_flush_dcache
- *
- * Description:
- *   Flush the data cache within the specified region by cleaning and
- *   invalidating the D cache.
- *
- * Input Parameters:
- *   start - virtual start address of region
- *   end   - virtual end address of region + 1
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-	.globl	cp15_flush_dcache
-	.type	cp15_flush_dcache, function
-
-cp15_flush_dcache:
-
-	mrc		CP15_CTR(r3)			/* Read the Cache Type Register */
-	lsr		r3, r3, #16			/* Isolate the DMinLine field */
-	and		r3, r3, #0xf
-	mov		r2, #4
-	mov		r2, r2, lsl r3			/* Get the cache line size in bytes */
-
-	sub		r3, r2, #1			/* R3=Cache line size mask */
-	bic		r0, r0, r3			/* R0=aligned start address */
-
-	/* Loop, cleaning and invaliding each D cache line in the address range */
-
-1:
-	mcr		CP15_DCCIMVAC(r0)		/* Clean and invalidate data cache line by VA to PoC */
-	add		r0, r0, r2			/* R12=Next cache line */
-	cmp		r0, r1				/* Loop until all cache lines have been cleaned */
-	blo		1b
-
-	dsb
-	bx		lr
-	.size cp15_flush_dcache, . - cp15_flush_dcache
-	.end
diff --git a/arch/arm/src/armv7-a/cp15_flush_dcache_all.S b/arch/arm/src/armv7-a/cp15_flush_dcache_all.S
deleted file mode 100644
index ddb5d70637..0000000000
--- a/arch/arm/src/armv7-a/cp15_flush_dcache_all.S
+++ /dev/null
@@ -1,128 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_flush_dcache_all.S
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- *   Copyright (c) 2012, Atmel Corporation
- *   All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- *    be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- *  "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- *   Copyright (c) 2010  ARM. All rights reserved. ARM DDI 0434B (ID101810)
- *  "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- *   Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- *   DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_flush_dcache_all.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_flush_dcache_all
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_flush_dcache_all
- *
- * Description:
- *   Flush the entire contents of D cache.
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-	.globl	cp15_flush_dcache_all
-	.type	cp15_flush_dcache_all, function
-
-cp15_flush_dcache_all:
-
-	push		{r4, r5}
-
-	mrc		CP15_CCSIDR(r1)			/* Read the Cache Size Identification Register */
-
-	ldr		r3, =0x7fff			/* Isolate the NumSets field (bits 13-27) */
-	and		r0, r3, r1, lsr #13		/* r0=NumSets (number of sets - 1) */
-
-	ldr		r3,=0x7				/* Isolate the LineSize field (bits 0-2) */
-	and		r5, r3, r1			/* r4=(Log2LineSize - 2) in word */
-	add		r5, #4				/* r4=Set/way operation line shfit */
-
-	ldr		r3, =0x3ff			/* Isolate the way field (bits 3-12) */
-	and		r1, r3, r1, lsr #3		/* r1=(number of ways - 1) */
-
-	add		r4, r1, #1
-	clz		r4, r4
-	add		r4, #1				/* r4=Set/way operation Way shift */
-
-way_loop:
-	mov		r3, r0				/* Init Sets */
-set_loop:
-	mov		r2, r1, lsl r4			/* r2 = way loop counter << way shift */
-	orr		r2, r3, lsl r5			/* r2 = set/way cache operation format */
-	mcr		CP15_DCCISW(r2)			/* Data Cache Clean and Invalidate by Set/Way */
-	subs		r3, r3, #1			/* Subtraction set counter */
-	bcs		set_loop			/* Keep looping if not */
-
-	subs		r1, r1, #1			/* Subtraction the way counter */
-	bcs		way_loop			/* Keep looping if not */
-
-	dsb
-	pop		{r4, r5}
-	bx		lr
-	.size cp15_flush_dcache_all, . - cp15_flush_dcache_all
-	.end
diff --git a/arch/arm/src/armv7-a/cp15_invalidate_dcache.S b/arch/arm/src/armv7-a/cp15_invalidate_dcache.S
deleted file mode 100644
index 4f04a5e74e..0000000000
--- a/arch/arm/src/armv7-a/cp15_invalidate_dcache.S
+++ /dev/null
@@ -1,123 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_invalidate_dcache.S
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- *   Copyright (c) 2012, Atmel Corporation
- *   All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- *    be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- *  "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- *   Copyright (c) 2010  ARM. All rights reserved. ARM DDI 0434B (ID101810)
- *  "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- *   Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- *   DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_invalidate_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_invalidate_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_invalidate_dcache
- *
- * Description:
- *   Invalidate the data cache within the specified region; we will be
- *   performing a DMA operation in this region and we want to purge old data
- *   in the cache.
- *
- * Input Parameters:
- *   start - virtual start address of region
- *   end   - virtual end address of region + 1
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-	.globl	cp15_invalidate_dcache
-	.type	cp15_invalidate_dcache, function
-
-cp15_invalidate_dcache:
-
-	mrc		CP15_CTR(r3)			/* Read the Cache Type Register */
-	lsr		r3, r3, #16			/* Isolate the DMinLine field */
-	and		r3, r3, #0xf
-	mov		r2, #4
-	mov		r2, r2, lsl r3			/* Get the cache line size in bytes */
-
-	sub		r3, r2, #1			/* R3=Cache line size mask */
-	tst		r0, r3
-	bic		r0, r0, r3			/* R0=aligned start address */
-
-	mcrne		CP15_DCCIMVAC(r0)		/* Clean and invalidate data cache line by VA to PoC */
-
-	tst		r1, r3
-	bic		r1, r1, r3			/* R0=aligned end address */
-	mcrne		CP15_DCCIMVAC(r1)		/* Clean and invalidate data cache line by VA to PoC */
-
-	/* Loop, invalidating each D cache line */
-1:
-	mcr		CP15_DCIMVAC(r0)		/* Invalidate data cache line by VA to PoC */
-	add		r0, r0, r2			/* R12=Next cache line */
-	cmp		r0, r1				/* Loop until all cache lines have been invalidate */
-	blo		1b
-
-	dsb
-	bx		lr
-	.size cp15_invalidate_dcache, . - cp15_invalidate_dcache
-	.end
diff --git a/arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S b/arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S
deleted file mode 100644
index 9b5f95491e..0000000000
--- a/arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S
+++ /dev/null
@@ -1,128 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- *   Copyright (c) 2012, Atmel Corporation
- *   All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- *    be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- *  "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- *   Copyright (c) 2010  ARM. All rights reserved. ARM DDI 0434B (ID101810)
- *  "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- *   Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- *   DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_invalidate_dcache_all.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_invalidate_dcache_all
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_invalidate_dcache_all
- *
- * Description:
- *   Invalidate the entire contents of D cache.
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-	.globl	cp15_invalidate_dcache_all
-	.type	cp15_invalidate_dcache_all, function
-
-cp15_invalidate_dcache_all:
-
-	push		{r4, r5}
-
-	mrc		CP15_CCSIDR(r1)			/* Read the Cache Size Identification Register */
-
-	ldr		r3, =0x7fff			/* Isolate the NumSets field (bits 13-27) */
-	and		r0, r3, r1, lsr #13		/* r0=NumSets (number of sets - 1) */
-
-	ldr		r3,=0x7				/* Isolate the LineSize field (bits 0-2) */
-	and		r5, r3, r1			/* r4=(Log2LineSize - 2) in word */
-	add		r5, #4				/* r4=Set/way operation line shfit */
-
-	ldr		r3, =0x3ff			/* Isolate the way field (bits 3-12) */
-	and		r1, r3, r1, lsr #3		/* r1=(number of ways - 1) */
-
-	add		r4, r1, #1
-	clz		r4, r4
-	add		r4, #1				/* r4=Set/way operation Way shift */
-
-way_loop:
-	mov		r3, r0				/* Init Sets */
-set_loop:
-	mov		r2, r1, lsl r4			/* r2 = way loop counter << way shift */
-	orr		r2, r3, lsl r5			/* r2 = set/way cache operation format */
-	mcr		CP15_DCISW(r2)			/* Data Cache Invalidate by Set/Way */
-	subs		r3, r3, #1			/* Subtraction set counter */
-	bcs		set_loop			/* Keep looping if not */
-
-	subs		r1, r1, #1			/* Subtraction the way counter */
-	bcs		way_loop			/* Keep looping if not */
-
-	dsb
-	pop		{r4, r5}
-	bx		lr
-	.size cp15_invalidate_dcache_all, . - cp15_invalidate_dcache_all
-	.end
diff --git a/arch/arm/src/armv7-r/Make.defs b/arch/arm/src/armv7-r/Make.defs
index 749c0ad60f..faece6ac8b 100644
--- a/arch/arm/src/armv7-r/Make.defs
+++ b/arch/arm/src/armv7-r/Make.defs
@@ -33,16 +33,11 @@ CMN_CSRCS += arm_cache.c arm_dataabort.c arm_doirq.c arm_gicv2.c
 CMN_CSRCS += arm_initialstate.c arm_prefetchabort.c
 CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
 CMN_CSRCS += arm_syscall.c arm_tcbinfo.c arm_undefinedinsn.c
-CMN_CSRCS += arm_perf.c
+CMN_CSRCS += arm_perf.c cp15_cacheops.c
 
 # Common C source files
 
-CMN_ASRCS += arm_head.S arm_vectoraddrexcptn.S
-CMN_ASRCS += arm_vectors.S cp15_cache_size.S
-CMN_ASRCS += cp15_clean_dcache_all.S cp15_clean_dcache.S
-CMN_ASRCS += cp15_coherent_dcache.S cp15_flush_dcache_all.S
-CMN_ASRCS += cp15_flush_dcache.S cp15_invalidate_dcache_all.S
-CMN_ASRCS += cp15_invalidate_dcache.S
+CMN_ASRCS += arm_head.S arm_vectoraddrexcptn.S arm_vectors.S
 
 ifeq ($(CONFIG_ARMV7R_HAVE_PTM), y)
   CMN_CSRCS += arm_timer.c
diff --git a/arch/arm/src/armv7-r/cp15_cache_size.S b/arch/arm/src/armv7-r/cp15_cache_size.S
deleted file mode 100644
index a1e6a328cc..0000000000
--- a/arch/arm/src/armv7-r/cp15_cache_size.S
+++ /dev/null
@@ -1,84 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_cache_size.S
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements.  See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.  The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License.  You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_cache_size.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_cache_size
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_cache_size
- *
- * Description:
- *   Get cp15 cache size in byte
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   Cache size in byte
- *
- ****************************************************************************/
-
-	.globl	cp15_cache_size
-	.type	cp15_cache_size, function
-
-cp15_cache_size:
-
-	mrc		CP15_CCSIDR(r0)			/* Read the Cache Size Identification Register */
-
-	ldr		r3, =0x7fff			/* Isolate the NumSets field (bits 13-27) */
-	and		r2, r3, r0, lsr #13		/* r2=NumSets (number of sets - 1) */
-	add		r2, #1
-
-	ldr		r3, =0x3ff			/* Isolate the way field (bits 3-12) */
-	and		r1, r3, r0, lsr #3		/* r1=(number of ways - 1) */
-	add		r1, #1
-
-	ldr		r3,=0x7				/* Isolate the LineSize field (bits 0-2) */
-	and		r0, r3				/* r0=(Log2LineSize - 2) in word */
-	add		r0, #4				/* r0=Log2lineSize in byte */
-
-	mul		r2, r1, r2			/* r2=Sets*Ways */
-	lsl		r0, r2, r0			/* r0=Sets*Ways*LineSize */
-
-	bx		lr
-
-	.size cp15_cache_size, . - cp15_cache_size
-	.end
diff --git a/arch/arm/src/armv7-r/cp15_cacheops.c b/arch/arm/src/armv7-r/cp15_cacheops.c
new file mode 100644
index 0000000000..7938d3bd05
--- /dev/null
+++ b/arch/arm/src/armv7-r/cp15_cacheops.c
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm/src/armv7-r/cp15_cacheops.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/cache.h>
+#include <nuttx/irq.h>
+
+#include "cp15_cacheops.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CP15_CACHE_INVALIDATE       0
+#define CP15_CACHE_CLEAN            1
+#define CP15_CACHE_CLEANINVALIDATE  2
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline uint32_t ilog2(uint32_t u)
+{
+  int i = 0;
+
+  while (u >>= 1)
+    {
+      i++;
+    }
+
+  return i;
+}
+
+static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways)
+{
+  uint32_t ccsidr = CP15_GET(CCSIDR);
+
+  if (sets)
+    {
+      *sets = ((ccsidr >> 13) & 0x7fff) + 1;
+    }
+
+  if (ways)
+    {
+      *ways = ((ccsidr >> 3) & 0x3ff) + 1;
+    }
+
+  return (1 << ((ccsidr & 0x7) + 2)) * 4;
+}
+
+static void cp15_dcache_op_level(uint32_t level, int op)
+{
+  uint32_t sets;
+  uint32_t ways;
+  uint32_t set;
+  uint32_t way;
+  uint32_t line;
+  uint32_t way_shift;
+  uint32_t set_shift;
+  uint32_t val = level << 1;
+
+  /* Select by CSSELR */
+
+  CP15_SET(CSSELR, val);
+
+  /* Get cache info */
+
+  line = cp15_cache_get_info(&sets, &ways);
+
+  way_shift = 32 - ilog2(ways);
+  set_shift = ilog2(line);
+
+  ARM_DSB();
+
+  /* A: Log2(ways)
+   * B: L+S
+   * L: Log2(line)
+   * S: Log2(sets)
+   *
+   * The bits are packed as follows:
+   *  31  31-A        B B-1    L L-1   4 3   1 0
+   * |---|-------------|--------|-------|-----|-|
+   * |Way|    zeros    |   Set  | zeros |level|0|
+   * |---|-------------|--------|-------|-----|-|
+   */
+
+  for (way = 0; way < ways; way++)
+    {
+      for (set = 0; set < sets; set++)
+        {
+          val  = level << 1;
+          val |= way << way_shift;
+          val |= set << set_shift;
+
+          switch (op)
+            {
+              case CP15_CACHE_INVALIDATE:
+                cp15_invalidate_dcacheline_bysetway(val);
+                break;
+              case CP15_CACHE_CLEAN:
+                cp15_clean_dcache_bysetway(val);
+                break;
+              case CP15_CACHE_CLEANINVALIDATE:
+                cp15_cleaninvalidate_dcacheline(val);
+                break;
+              default:
+                break;
+            }
+        }
+    }
+
+  ARM_ISB();
+}
+
+static void cp15_dcache_op(int op)
+{
+  uint32_t clidr = CP15_GET(CLIDR);
+  int level;
+
+  for (level = 0; level < 7; level++)
+    {
+      uint32_t ctype = clidr & 0x7;
+
+      switch (ctype)
+        {
+          case 0x2:
+          case 0x3:
+          case 0x4:
+            cp15_dcache_op_level(level, op);
+            break;
+          default:
+            break;
+        }
+
+      clidr >>= 3;
+      if (clidr == 0)
+        {
+          break;
+        }
+    }
+}
+
+static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
+{
+  uint32_t line;
+
+  line = cp15_cache_get_info(NULL, NULL);
+  start &= ~(line - 1);
+
+  ARM_DSB();
+
+  while (start < end)
+    {
+      switch (op)
+        {
+          case CP15_CACHE_INVALIDATE:
+            cp15_invalidate_dcacheline_bymva(start);
+            break;
+          case CP15_CACHE_CLEAN:
+            cp15_clean_dcache_bymva(start);
+            break;
+          case CP15_CACHE_CLEANINVALIDATE:
+            cp15_cleaninvalidate_dcacheline_bymva(start);
+            break;
+          default:
+            break;
+        }
+
+      start += line;
+    }
+
+  ARM_ISB();
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void cp15_coherent_dcache(uintptr_t start, uintptr_t end)
+{
+  cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
+  cp15_invalidate_icache();
+}
+
+void cp15_invalidate_dcache(uintptr_t start, uintptr_t end)
+{
+  cp15_dcache_op_mva(start, end, CP15_CACHE_INVALIDATE);
+}
+
+void cp15_invalidate_dcache_all(void)
+{
+  cp15_dcache_op(CP15_CACHE_INVALIDATE);
+}
+
+void cp15_clean_dcache(uintptr_t start, uintptr_t end)
+{
+  cp15_dcache_op_mva(start, end, CP15_CACHE_CLEAN);
+}
+
+void cp15_clean_dcache_all(void)
+{
+  cp15_dcache_op(CP15_CACHE_CLEAN);
+}
+
+void cp15_flush_dcache(uintptr_t start, uintptr_t end)
+{
+  cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
+}
+
+void cp15_flush_dcache_all(void)
+{
+  cp15_dcache_op(CP15_CACHE_CLEANINVALIDATE);
+}
+
+uint32_t cp15_cache_size(void)
+{
+  uint32_t sets;
+  uint32_t ways;
+  uint32_t line;
+
+  line = cp15_cache_get_info(&sets, &ways);
+
+  return sets * ways * line;
+}
diff --git a/arch/arm/src/armv7-r/cp15_clean_dcache.S b/arch/arm/src/armv7-r/cp15_clean_dcache.S
deleted file mode 100644
index 71a9534d8e..0000000000
--- a/arch/arm/src/armv7-r/cp15_clean_dcache.S
+++ /dev/null
@@ -1,116 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_clean_dcache.S
- *
- *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- *   Copyright (c) 2012, Atmel Corporation
- *   All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- *    be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- *  "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- *   Copyright (c) 2010  ARM. All rights reserved. ARM DDI 0434B (ID101810)
- *  "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- *   Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- *   DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_clean_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_clean_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_clean_dcache
- *
- * Description:
- *   Clean the data cache within the specified region by flushing the
- *   contents of the data cache to memory.
- *
- * Input Parameters:
- *   start - virtual start address of region
- *   end   - virtual end address of region + 1
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-	.globl	cp15_clean_dcache
-	.type	cp15_clean_dcache, function
-
-cp15_clean_dcache:
-
-	mrc		CP15_CTR(r3)			/* Read the Cache Type Register */
-	lsr		r3, r3, #16			/* Isolate the DMinLine field */
-	and		r3, r3, #0xf
-	mov		r2, #4
-	mov		r2, r2, lsl r3			/* Get the cache line size in bytes */
-
-	sub		r3, r2, #1			/* R3=Cache line size mask */
-	bic		r0, r0, r3			/* R0=aligned start address */
-
-	/* Loop, cleaning each cache line by writing its contents to memory */
-
-1:
-	mcr		CP15_DCCMVAC(r0)		/* Clean data cache line to PoC by VA */
-	add		r0, r0, r2			/* R12=Next cache line */
-	cmp		r0, r1				/* Loop until all cache lines have been cleaned */
-	blo		1b
-
-	dsb
-	bx		lr
-	.size cp15_clean_dcache, . - cp15_clean_dcache
-	.end
diff --git a/arch/arm/src/armv7-r/cp15_clean_dcache_all.S b/arch/arm/src/armv7-r/cp15_clean_dcache_all.S
deleted file mode 100644
index 4a08dfbc70..0000000000
--- a/arch/arm/src/armv7-r/cp15_clean_dcache_all.S
+++ /dev/null
@@ -1,129 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_clean_dcache_all.S
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- *   Copyright (c) 2012, Atmel Corporation
- *   All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- *    be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- *  "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- *   Copyright (c) 2010  ARM. All rights reserved. ARM DDI 0434B (ID101810)
- *  "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- *   Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- *   DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_clean_dcache_all.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_clean_dcache_all
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_clean_dcache_all
- *
- * Description:
- *   clean the entire contents of D cache.
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-	.globl	cp15_clean_dcache_all
-	.type	cp15_clean_dcache_all, function
-
-cp15_clean_dcache_all:
-
-	push		{r4, r5}
-
-	mrc		CP15_CCSIDR(r1)			/* Read the Cache Size Identification Register */
-
-	ldr		r3, =0x7fff			/* Isolate the NumSets field (bits 13-27) */
-	and		r0, r3, r1, lsr #13		/* r0=NumSets (number of sets - 1) */
-
-	ldr		r3,=0x7				/* Isolate the LineSize field (bits 0-2) */
-	and		r5, r3, r1			/* r4=(Log2LineSize - 2) in word */
-	add		r5, #4				/* r4=Set/way operation line shfit */
-
-	ldr		r3, =0x3ff			/* Isolate the way field (bits 3-12) */
-	and		r1, r3, r1, lsr #3		/* r1=(number of ways - 1) */
-
-	add		r4, r1, #1
-	clz		r4, r4
-	add		r4, #1				/* r4=Set/way operation Way shift */
-
-way_loop:
-	mov		r3, r0				/* Init Sets */
-set_loop:
-	mov		r2, r1, lsl #30			/* r2 = way loop counter << 30 */
-	orr		r2, r3, lsl #5			/* r2 = set/way cache operation format */
-	mcr		CP15_DCCSW(r2)			/* Data Cache Clean by Set/Way */
-	subs		r3, r3, #1			/* Subtraction set counter */
-	bcs		set_loop			/* Keep looping if not */
-
-	subs		r1, r1, #1			/* Subtraction the way counter */
-	bcs		way_loop			/* Keep looping if not */
-
-	dsb
-	pop		{r4, r5}
-	bx		lr
-	.size cp15_clean_dcache_all, . - cp15_clean_dcache_all
-	.end
-
diff --git a/arch/arm/src/armv7-r/cp15_coherent_dcache.S b/arch/arm/src/armv7-r/cp15_coherent_dcache.S
deleted file mode 100644
index cb4589452b..0000000000
--- a/arch/arm/src/armv7-r/cp15_coherent_dcache.S
+++ /dev/null
@@ -1,140 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_coherent_dcache.S
- *
- *   Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- *   Copyright (c) 2012, Atmel Corporation
- *   All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- *    be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- *  "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- *   Copyright (c) 2010  ARM. All rights reserved. ARM DDI 0434B (ID101810)
- *  "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- *   Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- *   DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_coherent_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_coherent_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_coherent_dcache
- *
- * Description:
- *   Ensure that the I and D caches are coherent within specified region
- *   by cleaning the D cache (i.e., flushing the D cache contents to memory
- *   and invalidating the I cache. This is typically used when code has been
- *   written to a memory region, and will be executed.
- *
- * Input Parameters:
- *   start - virtual start address of region
- *   end   - virtual end address of region + 1
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-	.globl	cp15_coherent_dcache
-	.type	cp15_coherent_dcache, function
-
-cp15_coherent_dcache:
-	mrc		CP15_CTR(r3)			/* Read the Cache Type Register */
-	lsr		r3, r3, #16			/* Isolate the DMinLine field */
-	and		r3, r3, #0xf
-	mov		r2, #4
-	mov		r2, r2, lsl r3			/* Get the cache line size in bytes */
-
-	sub		r3, r2, #1			/* R3=Cache line size mask */
-	bic		r12, r0, r3			/* R12=aligned start address */
-
-	/* Loop, flushing each D cache line to memory */
-1:
-	mcr		CP15_DCCMVAU(r12)		/* Clean data or unified cache line by VA to PoU */
-	add		r12, r12, r2			/* R12=Next cache line */
-	cmp		r12, r1				/* Loop until all cache lines have been cleaned */
-	blo		1b
-
-	dsb
-
-	mrc		CP15_CTR(r3)			/* Read the Cache Type Register */
-	and		r3, r3, #0xf			/* Isolate the IminLine field */
-	mov		r2, #4
-	mov		r2, r2, lsl r3			/* Get the cache line size in bytes */
-
-	sub		r3, r2, #1			/* R3=Cache line size mask */
-	bic		r12, r0, r3			/* R12=aligned start address */
-
-	/* Loop, invalidating each I cache line to memory */
-1:
-	mcr		CP15_ICIMVAU(r12)		/* Invalidate instruction cache by VA to PoU */
-	add		r12, r12, r2			/* R12=Next cache line */
-	cmp		r12, r1				/* Loop until all cache lines have been invalidated */
-	blo		1b
-
-	mov		r0, #0
-#ifdef CONFIG_SMP
-	mcr		CP15_BPIALLIS(r0)		/* Invalidate entire branch predictor array Inner Shareable */
-#endif
-	mcr		CP15_BPIALL(r0)			/* Invalidate all branch predictors */
-
-	dsb
-	isb
-	bx		lr
-	.size cp15_coherent_dcache, . - cp15_coherent_dcache
-	.end
diff --git a/arch/arm/src/armv7-r/cp15_flush_dcache.S b/arch/arm/src/armv7-r/cp15_flush_dcache.S
deleted file mode 100644
index 2bdc4e5474..0000000000
--- a/arch/arm/src/armv7-r/cp15_flush_dcache.S
+++ /dev/null
@@ -1,116 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_flush_dcache.S
- *
- *   Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- *   Copyright (c) 2012, Atmel Corporation
- *   All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- *    be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- *  "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- *   Copyright (c) 2010  ARM. All rights reserved. ARM DDI 0434B (ID101810)
- *  "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- *   Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- *   DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_flush_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_flush_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_flush_dcache
- *
- * Description:
- *   Flush the data cache within the specified region by cleaning and
- *   invalidating the D cache.
- *
- * Input Parameters:
- *   start - virtual start address of region
- *   end   - virtual end address of region + 1
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-	.globl	cp15_flush_dcache
-	.type	cp15_flush_dcache, function
-
-cp15_flush_dcache:
-
-	mrc		CP15_CTR(r3)			/* Read the Cache Type Register */
-	lsr		r3, r3, #16			/* Isolate the DMinLine field */
-	and		r3, r3, #0xf
-	mov		r2, #4
-	mov		r2, r2, lsl r3			/* Get the cache line size in bytes */
-
-	sub		r3, r2, #1			/* R3=Cache line size mask */
-	bic		r0, r0, r3			/* R0=aligned start address */
-
-	/* Loop, cleaning and invaliding each D cache line in the address range */
-
-1:
-	mcr		CP15_DCCIMVAC(r0)		/* Clean and invalidate data cache line by VA to PoC */
-	add		r0, r0, r2			/* R12=Next cache line */
-	cmp		r0, r1				/* Loop until all cache lines have been cleaned */
-	blo		1b
-
-	dsb
-	bx		lr
-	.size cp15_flush_dcache, . - cp15_flush_dcache
-	.end
diff --git a/arch/arm/src/armv7-r/cp15_flush_dcache_all.S b/arch/arm/src/armv7-r/cp15_flush_dcache_all.S
deleted file mode 100644
index 747d12271d..0000000000
--- a/arch/arm/src/armv7-r/cp15_flush_dcache_all.S
+++ /dev/null
@@ -1,129 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_flush_dcache_all.S
- *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- *   Copyright (c) 2012, Atmel Corporation
- *   All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- *    be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- *  "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- *   Copyright (c) 2010  ARM. All rights reserved. ARM DDI 0434B (ID101810)
- *  "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- *   Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- *   DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_flush_dcache_all.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_flush_dcache_all
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_flush_dcache_all
- *
- * Description:
- *   Flush the entire contents of D cache.
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-	.globl	cp15_flush_dcache_all
-	.type	cp15_flush_dcache_all, function
-
-cp15_flush_dcache_all:
-
-	push		{r4, r5}
-
-	mrc		CP15_CCSIDR(r1)			/* Read the Cache Size Identification Register */
-
-	ldr		r3, =0x7fff			/* Isolate the NumSets field (bits 13-27) */
-	and		r0, r3, r1, lsr #13		/* r0=NumSets (number of sets - 1) */
-
-	ldr		r3,=0x7				/* Isolate the LineSize field (bits 0-2) */
-	and		r5, r3, r1			/* r4=(Log2LineSize - 2) in word */
-	add		r5, #4				/* r4=Set/way operation line shfit */
-
-	ldr		r3, =0x3ff			/* Isolate the way field (bits 3-12) */
-	and		r1, r3, r1, lsr #3		/* r1=(number of ways - 1) */
-
-	add		r4, r1, #1
-	clz		r4, r4
-	add		r4, #1				/* r4=Set/way operation Way shift */
-
-way_loop:
-	mov		r3, r0				/* Init Sets */
-set_loop:
-	mov		r2, r1, lsl #30			/* r2 = way loop counter << 30 */
-	orr		r2, r3, lsl #5			/* r2 = set/way cache operation format */
-	mcr		CP15_DCCISW(r2)			/* Data Cache Clean and Invalidate by Set/Way */
-	subs		r3, r3, #1			/* Subtraction set counter */
-	bcs		set_loop			/* Keep looping if not */
-
-	subs		r1, r1, #1			/* Subtraction the way counter */
-	bcs		way_loop			/* Keep looping if not */
-
-	dsb
-	pop		{r4, r5}
-	bx		lr
-	.size cp15_flush_dcache_all, . - cp15_flush_dcache_all
-	.end
-
diff --git a/arch/arm/src/armv7-r/cp15_invalidate_dcache.S b/arch/arm/src/armv7-r/cp15_invalidate_dcache.S
deleted file mode 100644
index 67d11603c8..0000000000
--- a/arch/arm/src/armv7-r/cp15_invalidate_dcache.S
+++ /dev/null
@@ -1,123 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_invalidate_dcache.S
- *
- *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- *   Copyright (c) 2012, Atmel Corporation
- *   All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- *    be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- *  "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- *   Copyright (c) 2010  ARM. All rights reserved. ARM DDI 0434B (ID101810)
- *  "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- *   Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- *   DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_invalidate_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_invalidate_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_invalidate_dcache
- *
- * Description:
- *   Invalidate the data cache within the specified region; we will be
- *   performing a DMA operation in this region and we want to purge old data
- *   in the cache.
- *
- * Input Parameters:
- *   start - virtual start address of region
- *   end   - virtual end address of region + 1
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-	.globl	cp15_invalidate_dcache
-	.type	cp15_invalidate_dcache, function
-
-cp15_invalidate_dcache:
-
-	mrc		CP15_CTR(r3)			/* Read the Cache Type Register */
-	lsr		r3, r3, #16			/* Isolate the DMinLine field */
-	and		r3, r3, #0xf
-	mov		r2, #4
-	mov		r2, r2, lsl r3			/* Get the cache line size in bytes */
-
-	sub		r3, r2, #1			/* R3=Cache line size mask */
-	tst		r0, r3
-	bic		r0, r0, r3			/* R0=aligned start address */
-
-	mcrne		CP15_DCCIMVAC(r0)		/* Clean and invalidate data cache line by VA to PoC */
-
-	tst		r1, r3
-	bic		r1, r1, r3			/* R0=aligned end address */
-	mcrne		CP15_DCCIMVAC(r1)		/* Clean and invalidate data cache line by VA to PoC */
-
-	/* Loop, invalidating each D cache line */
-1:
-	mcr		CP15_DCIMVAC(r0)		/* Invalidate data cache line by VA to PoC */
-	add		r0, r0, r2			/* R12=Next cache line */
-	cmp		r0, r1				/* Loop until all cache lines have been invalidate */
-	blo		1b
-
-	dsb
-	bx		lr
-	.size cp15_invalidate_dcache, . - cp15_invalidate_dcache
-	.end
diff --git a/arch/arm/src/armv7-r/cp15_invalidate_dcache_all.S b/arch/arm/src/armv7-r/cp15_invalidate_dcache_all.S
deleted file mode 100644
index 399e8cf8e2..0000000000
--- a/arch/arm/src/armv7-r/cp15_invalidate_dcache_all.S
+++ /dev/null
@@ -1,128 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_invalidate_dcache_all.S
- *
- *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- *   Copyright (c) 2012, Atmel Corporation
- *   All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- *    be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- *  "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- *   Copyright (c) 2010  ARM. All rights reserved. ARM DDI 0434B (ID101810)
- *  "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- *   Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- *   DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
-	.file	"cp15_invalidate_dcache_all.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-	.globl	cp15_invalidate_dcache_all
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-	.text
-
-/****************************************************************************
- * Name: cp15_invalidate_dcache_all
- *
- * Description:
- *   Invalidate the entire contents of D cache.
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-	.globl	cp15_invalidate_dcache_all
-	.type	cp15_invalidate_dcache_all, function
-
-cp15_invalidate_dcache_all:
-
-	push		{r4, r5}
-
-	mrc		CP15_CCSIDR(r1)			/* Read the Cache Size Identification Register */
-
-	ldr		r3, =0x7fff			/* Isolate the NumSets field (bits 13-27) */
-	and		r0, r3, r1, lsr #13		/* r0=NumSets (number of sets - 1) */
-
-	ldr		r3,=0x7				/* Isolate the LineSize field (bits 0-2) */
-	and		r5, r3, r1			/* r4=(Log2LineSize - 2) in word */
-	add		r5, #4				/* r4=Set/way operation line shfit */
-
-	ldr		r3, =0x3ff			/* Isolate the way field (bits 3-12) */
-	and		r1, r3, r1, lsr #3		/* r1=(number of ways - 1) */
-
-	add		r4, r1, #1
-	clz		r4, r4
-	add		r4, #1				/* r4=Set/way operation Way shift */
-
-way_loop:
-	mov		r3, r0				/* Init Sets */
-set_loop:
-	mov		r2, r1, lsl #30			/* r2 = way loop counter << 30 */
-	orr		r2, r3, lsl #5			/* r2 = set/way cache operation format */
-	mcr		CP15_DCISW(r2)			/* Data Cache Invalidate by Set/Way */
-	subs		r3, r3, #1			/* Subtraction set counter */
-	bcs		set_loop			/* Keep looping if not */
-
-	subs		r1, r1, #1			/* Subtraction the way counter */
-	bcs		way_loop			/* Keep looping if not */
-
-	dsb
-	pop		{r4, r5}
-	bx		lr
-	.size cp15_invalidate_dcache_all, . - cp15_invalidate_dcache_all
-	.end