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Posted to commits@nuttx.apache.org by xi...@apache.org on 2024/09/25 13:47:23 UTC
(nuttx) 01/02: arch/risc-v/src/mpfs: Remove CONFIG_MPFS_COREPWMx_PWMCLK configs
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 7e6e18697cb6e06e42d3ca327e5a857e1667ec86
Author: Jukka Laitinen <ju...@ssrc.tii.ae>
AuthorDate: Fri May 12 10:23:31 2023 +0300
arch/risc-v/src/mpfs: Remove CONFIG_MPFS_COREPWMx_PWMCLK configs
These are always the same as FPGA peripheral clock, so use that directly
Signed-off-by: Jukka Laitinen <ju...@ssrc.tii.ae>
---
arch/risc-v/src/mpfs/Kconfig | 12 ------------
arch/risc-v/src/mpfs/mpfs_corepwm.c | 9 +++------
2 files changed, 3 insertions(+), 18 deletions(-)
diff --git a/arch/risc-v/src/mpfs/Kconfig b/arch/risc-v/src/mpfs/Kconfig
index 290332d1d5..6855dd7159 100644
--- a/arch/risc-v/src/mpfs/Kconfig
+++ b/arch/risc-v/src/mpfs/Kconfig
@@ -578,12 +578,6 @@ config MPFS_COREPWM0_BASE
default 0x44000000
depends on MPFS_COREPWM0
-config MPFS_COREPWM0_PWMCLK
- int "Clock frequency of the CorePWM0 block (Hz)"
- default 25000000
- range 1000000 100000000
- depends on MPFS_COREPWM0
-
config MPFS_COREPWM0_REGWIDTH
int "Width of the PWM register (8, 16 or 32 bits)"
default 32
@@ -607,12 +601,6 @@ config MPFS_COREPWM1_BASE
default 0x45000000
depends on MPFS_COREPWM1
-config MPFS_COREPWM1_PWMCLK
- int "Clock frequency of the CorePWM1 block (Hz)"
- default 25000000
- range 1000000 100000000
- depends on MPFS_COREPWM1
-
config MPFS_COREPWM1_REGWIDTH
int "Width of the PWM register (8, 16 or 32 bits)"
default 32
diff --git a/arch/risc-v/src/mpfs/mpfs_corepwm.c b/arch/risc-v/src/mpfs/mpfs_corepwm.c
index e291bc6ab5..b59d3250b6 100644
--- a/arch/risc-v/src/mpfs/mpfs_corepwm.c
+++ b/arch/risc-v/src/mpfs/mpfs_corepwm.c
@@ -76,7 +76,6 @@ struct mpfs_pwmtimer_s
struct mpfs_pwmchan_s channels[MPFS_MAX_PWM_CHANNELS];
uint32_t frequency; /* Current frequency setting */
uintptr_t base; /* The base address of the pwm block */
- uint32_t pwmclk; /* The frequency of the pwm clock */
};
/****************************************************************************
@@ -187,7 +186,6 @@ static struct mpfs_pwmtimer_s g_pwm0dev =
}
},
.base = CONFIG_MPFS_COREPWM0_BASE,
- .pwmclk = CONFIG_MPFS_COREPWM0_PWMCLK,
};
#endif
@@ -249,7 +247,6 @@ static struct mpfs_pwmtimer_s g_pwm1dev =
}
},
.base = CONFIG_MPFS_COREPWM1_BASE,
- .pwmclk = CONFIG_MPFS_COREPWM1_PWMCLK,
};
#endif
@@ -404,12 +401,12 @@ static int pwm_timer(struct mpfs_pwmtimer_s *priv,
* PERIOD = pwmclk / frequency = 25,000,000 / 50 = 500,000
*/
- pwminfo("PWM%u frequency: %u PWMCLK: %u prescaler: %u\n",
- priv->pwmid, info->frequency, priv->pwmclk, prescaler);
+ pwminfo("PWM%u frequency: %u PWMCLK: %lu prescaler: %u\n",
+ priv->pwmid, info->frequency, MPFS_FPGA_PERIPHERAL_CLK, prescaler);
/* Set the reload and prescaler values */
- period = priv->pwmclk / info->frequency;
+ period = MPFS_FPGA_PERIPHERAL_CLK / info->frequency;
pwm_putreg(priv, MPFS_COREPWM_PERIOD_OFFSET, period);
pwm_putreg(priv, MPFS_COREPWM_PRESCALE_OFFSET, prescaler);