You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@mynewt.apache.org by GitBox <gi...@apache.org> on 2021/02/18 02:40:55 UTC
[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2487: [KINETIS] Multiple fixes: boot, systick and debug.
apache-mynewt-bot commented on pull request #2487:
URL: https://github.com/apache/mynewt-core/pull/2487#issuecomment-781002548
<!-- style-bot -->
## Style check summary
### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
#### hw/bsp/frdm-k82f/src/clock_config.c
<details>
```diff
@@ -32,13 +32,13 @@
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Clocks v5.0
-processor: MK82FN256xxx15
-package_id: MK82FN256VDC15
-mcu_data: ksdk2_0
-processor_version: 5.0.0
-board: FRDM-K82F
+ !!GlobalInfo
+ product: Clocks v5.0
+ processor: MK82FN256xxx15
+ package_id: MK82FN256VDC15
+ mcu_data: ksdk2_0
+ processor_version: 5.0.0
+ board: FRDM-K82F
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
@@ -90,103 +92,98 @@
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockHSRUN
-outputs:
-- {id: Bus_clock.outFreq, value: 75 MHz}
-- {id: Core_clock.outFreq, value: 150 MHz, locked: true, accuracy: '0.001'}
-- {id: Flash_clock.outFreq, value: 25 MHz}
-- {id: FlexBus_clock.outFreq, value: 75 MHz}
-- {id: LPO_clock.outFreq, value: 1 kHz}
-- {id: MCGFFCLK.outFreq, value: 375 kHz}
-- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
-- {id: MCGPLLCLK.outFreq, value: 150 MHz}
-- {id: MCGPLLCLK2X.outFreq, value: 300 MHz}
-- {id: OSCERCLK.outFreq, value: 12 MHz}
-- {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
-- {id: PLLFLLCLK.outFreq, value: 150 MHz}
-- {id: System_clock.outFreq, value: 150 MHz}
-settings:
-- {id: MCGMode, value: PEE}
-- {id: powerMode, value: HSRUN}
-- {id: MCG.FCRDIV.scale, value: '1'}
-- {id: MCG.FRDIV.scale, value: '32'}
-- {id: MCG.IREFS.sel, value: MCG.FRDIV}
-- {id: MCG.PLLS.sel, value: MCG.PLL_DIV2}
-- {id: MCG.VDIV.scale, value: '25'}
-- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
-- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
-- {id: MCG_C2_RANGE0_CFG, value: Very_high}
-- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
-- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
-- {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
-- {id: RTC_CR_OSCE_CFG, value: Enabled}
-- {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
-- {id: SIM.EMVSIMSRCSEL.sel, value: OSC.OSCERCLK}
-- {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK}
-- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
-- {id: SIM.OUTDIV2.scale, value: '2'}
-- {id: SIM.OUTDIV4.scale, value: '6'}
-- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
-- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
-- {id: SIM.TPMSRCSEL.sel, value: OSC.OSCERCLK}
-- {id: SIM.USBFRAC.scale, value: '1', locked: true}
-- {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV}
-sources:
-- {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
+ !!Configuration
+ name: BOARD_BootClockHSRUN
+ outputs:
+ - {id: Bus_clock.outFreq, value: 75 MHz}
+ - {id: Core_clock.outFreq, value: 150 MHz, locked: true, accuracy: '0.001'}
+ - {id: Flash_clock.outFreq, value: 25 MHz}
+ - {id: FlexBus_clock.outFreq, value: 75 MHz}
+ - {id: LPO_clock.outFreq, value: 1 kHz}
+ - {id: MCGFFCLK.outFreq, value: 375 kHz}
+ - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
+ - {id: MCGPLLCLK.outFreq, value: 150 MHz}
+ - {id: MCGPLLCLK2X.outFreq, value: 300 MHz}
+ - {id: OSCERCLK.outFreq, value: 12 MHz}
+ - {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
+ - {id: PLLFLLCLK.outFreq, value: 150 MHz}
+ - {id: System_clock.outFreq, value: 150 MHz}
+ settings:
+ - {id: MCGMode, value: PEE}
+ - {id: powerMode, value: HSRUN}
+ - {id: MCG.FCRDIV.scale, value: '1'}
+ - {id: MCG.FRDIV.scale, value: '32'}
+ - {id: MCG.IREFS.sel, value: MCG.FRDIV}
+ - {id: MCG.PLLS.sel, value: MCG.PLL_DIV2}
+ - {id: MCG.VDIV.scale, value: '25'}
+ - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+ - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+ - {id: MCG_C2_RANGE0_CFG, value: Very_high}
+ - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+ - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+ - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
+ - {id: RTC_CR_OSCE_CFG, value: Enabled}
+ - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
+ - {id: SIM.EMVSIMSRCSEL.sel, value: OSC.OSCERCLK}
+ - {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK}
+ - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
+ - {id: SIM.OUTDIV2.scale, value: '2'}
+ - {id: SIM.OUTDIV4.scale, value: '6'}
+ - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
+ - {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
+ - {id: SIM.TPMSRCSEL.sel, value: OSC.OSCERCLK}
+ - {id: SIM.USBFRAC.scale, value: '1', locked: true}
+ - {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV}
+ sources:
+ - {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockHSRUN configuration
******************************************************************************/
-const mcg_config_t mcgConfig_BOARD_BootClockHSRUN =
- {
- .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
- .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
- .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
- .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
- .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
- .drs = kMCG_DrsLow, /* Low frequency range */
- .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
- .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
- .pll0Config =
- {
- .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
- .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
- .vdiv = 0x9U, /* VCO divider: multiplied by 25 */
- },
- };
-const sim_clock_config_t simConfig_BOARD_BootClockHSRUN =
- {
- .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
- .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
- .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
- .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
- .clkdiv1 = 0x1150000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /6 */
- };
-const osc_config_t oscConfig_BOARD_BootClockHSRUN =
- {
- .freq = 12000000U, /* Oscillator frequency: 12000000Hz */
- .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
- .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
- .oscerConfig =
- {
- .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
- .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
- }
- };
+const mcg_config_t mcgConfig_BOARD_BootClockHSRUN = {
+ .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
+ .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+ .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
+ .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
+ .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
+ .drs = kMCG_DrsLow, /* Low frequency range */
+ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+ .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
+ .pll0Config = {
+ .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
+ .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
+ .vdiv = 0x9U, /* VCO divider: multiplied by 25 */
+ },
+};
+const sim_clock_config_t simConfig_BOARD_BootClockHSRUN = {
+ .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
+ .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
+ .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
+ .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+ .clkdiv1 = 0x1150000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /6 */
+};
+const osc_config_t oscConfig_BOARD_BootClockHSRUN = {
+ .freq = 12000000U, /* Oscillator frequency: 12000000Hz */
+ .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
+ .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
+ .oscerConfig = {
+ .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
+ .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
+ }
+};
/*******************************************************************************
* Code for BOARD_BootClockHSRUN configuration
******************************************************************************/
-void BOARD_BootClockHSRUN(void)
+void
+BOARD_BootClockHSRUN(void)
{
/* Set HSRUN power mode */
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC);
- while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
- {
+ while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun) {
}
/* Set the system clock dividers in SIM to safe value. */
CLOCK_SetSimSafeDivs();
@@ -195,7 +192,7 @@
CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockHSRUN.freq);
/* Configure the Internal Reference clock (MCGIRCLK). */
CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode,
- mcgConfig_BOARD_BootClockHSRUN.ircs,
+ mcgConfig_BOARD_BootClockHSRUN.ircs,
mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
/* Configure FLL external reference divider (FRDIV). */
CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv);
@@ -214,81 +211,77 @@
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockVLPR
-outputs:
-- {id: Bus_clock.outFreq, value: 4 MHz}
-- {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
-- {id: Flash_clock.outFreq, value: 800 kHz}
-- {id: FlexBus_clock.outFreq, value: 4 MHz}
-- {id: LPO_clock.outFreq, value: 1 kHz}
-- {id: MCGIRCLK.outFreq, value: 4 MHz}
-- {id: System_clock.outFreq, value: 4 MHz}
-settings:
-- {id: MCGMode, value: BLPI}
-- {id: powerMode, value: VLPR}
-- {id: MCG.CLKS.sel, value: MCG.IRCS}
-- {id: MCG.FCRDIV.scale, value: '1'}
-- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
-- {id: MCG.PRDIV.scale, value: '1', locked: true}
-- {id: MCG.VDIV.scale, value: '16', locked: true}
-- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
-- {id: RTC_CR_OSCE_CFG, value: Enabled}
-- {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
-- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
-- {id: SIM.OUTDIV3.scale, value: '1', locked: true}
-- {id: SIM.OUTDIV4.scale, value: '5'}
-- {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
-- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
-sources:
-- {id: OSC.OSC.outFreq, value: 12 MHz}
+ !!Configuration
+ name: BOARD_BootClockVLPR
+ outputs:
+ - {id: Bus_clock.outFreq, value: 4 MHz}
+ - {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
+ - {id: Flash_clock.outFreq, value: 800 kHz}
+ - {id: FlexBus_clock.outFreq, value: 4 MHz}
+ - {id: LPO_clock.outFreq, value: 1 kHz}
+ - {id: MCGIRCLK.outFreq, value: 4 MHz}
+ - {id: System_clock.outFreq, value: 4 MHz}
+ settings:
+ - {id: MCGMode, value: BLPI}
+ - {id: powerMode, value: VLPR}
+ - {id: MCG.CLKS.sel, value: MCG.IRCS}
+ - {id: MCG.FCRDIV.scale, value: '1'}
+ - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+ - {id: MCG.PRDIV.scale, value: '1', locked: true}
+ - {id: MCG.VDIV.scale, value: '16', locked: true}
+ - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+ - {id: RTC_CR_OSCE_CFG, value: Enabled}
+ - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
+ - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
+ - {id: SIM.OUTDIV3.scale, value: '1', locked: true}
+ - {id: SIM.OUTDIV4.scale, value: '5'}
+ - {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
+ - {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
+ sources:
+ - {id: OSC.OSC.outFreq, value: 12 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockVLPR configuration
******************************************************************************/
-const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
- {
- .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
- .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
- .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
- .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
- .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
- .drs = kMCG_DrsLow, /* Low frequency range */
- .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
- .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
- .pll0Config =
- {
- .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
- .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
- .vdiv = 0x0U, /* VCO divider: multiplied by 16 */
- },
- };
-const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
- {
- .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
- .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
- .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
- .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
- .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
- };
-const osc_config_t oscConfig_BOARD_BootClockVLPR =
- {
- .freq = 0U, /* Oscillator frequency: 0Hz */
- .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
- .workMode = kOSC_ModeExt, /* Use external clock */
- .oscerConfig =
- {
- .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
- .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
- }
- };
+const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
+ .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
+ .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+ .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
+ .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
+ .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
+ .drs = kMCG_DrsLow, /* Low frequency range */
+ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+ .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
+ .pll0Config = {
+ .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
+ .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
+ .vdiv = 0x0U, /* VCO divider: multiplied by 16 */
+ },
+};
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
+ .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
+ .pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
+ .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
+ .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+ .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
+};
+const osc_config_t oscConfig_BOARD_BootClockVLPR = {
+ .freq = 0U, /* Oscillator frequency: 0Hz */
+ .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
+ .workMode = kOSC_ModeExt, /* Use external clock */
+ .oscerConfig = {
+ .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+ .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
+ }
+};
/*******************************************************************************
* Code for BOARD_BootClockVLPR configuration
******************************************************************************/
-void BOARD_BootClockVLPR(void)
+void
+BOARD_BootClockVLPR(void)
{
/* Set the system clock dividers in SIM to safe value. */
CLOCK_SetSimSafeDivs();
@@ -317,94 +309,90 @@
******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockRUN
-called_from_default_init: true
-outputs:
-- {id: Bus_clock.outFreq, value: 60 MHz}
-- {id: Core_clock.outFreq, value: 120 MHz}
-- {id: Flash_clock.outFreq, value: 24 MHz}
-- {id: FlexBus_clock.outFreq, value: 60 MHz}
-- {id: LPO_clock.outFreq, value: 1 kHz}
-- {id: LPUARTCLK.outFreq, value: 32.768 kHz}
-- {id: MCGFFCLK.outFreq, value: 375 kHz}
-- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
-- {id: MCGPLLCLK.outFreq, value: 120 MHz}
-- {id: MCGPLLCLK2X.outFreq, value: 240 MHz}
-- {id: OSCERCLK.outFreq, value: 12 MHz}
-- {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
-- {id: PLLFLLCLK.outFreq, value: 120 MHz}
-- {id: System_clock.outFreq, value: 120 MHz}
-settings:
-- {id: MCGMode, value: PEE}
-- {id: LPUARTClkConfig, value: 'yes'}
-- {id: MCG.FCRDIV.scale, value: '1', locked: true}
-- {id: MCG.FRDIV.scale, value: '32'}
-- {id: MCG.IREFS.sel, value: MCG.FRDIV}
-- {id: MCG.PLLS.sel, value: MCG.PLL_DIV2}
-- {id: MCG.PRDIV.scale, value: '1', locked: true}
-- {id: MCG.VDIV.scale, value: '20', locked: true}
-- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
-- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
-- {id: MCG_C2_RANGE0_CFG, value: Very_high}
-- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
-- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
-- {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
-- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
-- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
-- {id: SIM.OUTDIV2.scale, value: '2'}
-- {id: SIM.OUTDIV4.scale, value: '5', locked: true}
-- {id: SIM.PLLFLLDIV.scale, value: '5'}
-- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
-sources:
-- {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
+ !!Configuration
+ name: BOARD_BootClockRUN
+ called_from_default_init: true
+ outputs:
+ - {id: Bus_clock.outFreq, value: 60 MHz}
+ - {id: Core_clock.outFreq, value: 120 MHz}
+ - {id: Flash_clock.outFreq, value: 24 MHz}
+ - {id: FlexBus_clock.outFreq, value: 60 MHz}
+ - {id: LPO_clock.outFreq, value: 1 kHz}
+ - {id: LPUARTCLK.outFreq, value: 32.768 kHz}
+ - {id: MCGFFCLK.outFreq, value: 375 kHz}
+ - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
+ - {id: MCGPLLCLK.outFreq, value: 120 MHz}
+ - {id: MCGPLLCLK2X.outFreq, value: 240 MHz}
+ - {id: OSCERCLK.outFreq, value: 12 MHz}
+ - {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
+ - {id: PLLFLLCLK.outFreq, value: 120 MHz}
+ - {id: System_clock.outFreq, value: 120 MHz}
+ settings:
+ - {id: MCGMode, value: PEE}
+ - {id: LPUARTClkConfig, value: 'yes'}
+ - {id: MCG.FCRDIV.scale, value: '1', locked: true}
+ - {id: MCG.FRDIV.scale, value: '32'}
+ - {id: MCG.IREFS.sel, value: MCG.FRDIV}
+ - {id: MCG.PLLS.sel, value: MCG.PLL_DIV2}
+ - {id: MCG.PRDIV.scale, value: '1', locked: true}
+ - {id: MCG.VDIV.scale, value: '20', locked: true}
+ - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+ - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+ - {id: MCG_C2_RANGE0_CFG, value: Very_high}
+ - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+ - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+ - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
+ - {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
+ - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
+ - {id: SIM.OUTDIV2.scale, value: '2'}
+ - {id: SIM.OUTDIV4.scale, value: '5', locked: true}
+ - {id: SIM.PLLFLLDIV.scale, value: '5'}
+ - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
+ sources:
+ - {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
-const mcg_config_t mcgConfig_BOARD_BootClockRUN =
- {
- .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
- .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
- .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
- .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
- .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
- .drs = kMCG_DrsLow, /* Low frequency range */
- .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
- .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
- .pll0Config =
- {
- .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
- .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
- .vdiv = 0x4U, /* VCO divider: multiplied by 20 */
- },
- };
-const sim_clock_config_t simConfig_BOARD_BootClockRUN =
- {
- .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
- .pllFllDiv = 4, /* PLLFLLSEL clock divider divisor: divided by 5 */
- .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
- .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
- .clkdiv1 = 0x1140000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /5 */
- };
-const osc_config_t oscConfig_BOARD_BootClockRUN =
- {
- .freq = 12000000U, /* Oscillator frequency: 12000000Hz */
- .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
- .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
- .oscerConfig =
- {
- .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
- .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
- }
- };
+const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
+ .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
+ .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+ .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
+ .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
+ .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
+ .drs = kMCG_DrsLow, /* Low frequency range */
+ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+ .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
+ .pll0Config = {
+ .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
+ .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
+ .vdiv = 0x4U, /* VCO divider: multiplied by 20 */
+ },
+};
+const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
+ .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
+ .pllFllDiv = 4, /* PLLFLLSEL clock divider divisor: divided by 5 */
+ .pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
+ .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+ .clkdiv1 = 0x1140000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /5 */
+};
+const osc_config_t oscConfig_BOARD_BootClockRUN = {
+ .freq = 12000000U, /* Oscillator frequency: 12000000Hz */
+ .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
+ .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
+ .oscerConfig = {
+ .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
+ .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
+ }
+};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
-void BOARD_BootClockRUN(void)
+void
+BOARD_BootClockRUN(void)
{
/* Set the system clock dividers in SIM to safe value. */
CLOCK_SetSimSafeDivs();
@@ -413,7 +401,7 @@
CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
/* Configure the Internal Reference clock (MCGIRCLK). */
CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
- mcgConfig_BOARD_BootClockRUN.ircs,
+ mcgConfig_BOARD_BootClockRUN.ircs,
mcgConfig_BOARD_BootClockRUN.fcrdiv);
/* Configure FLL external reference divider (FRDIV). */
CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
```
</details>
#### hw/mcu/nxp/kinetis/src/hal_os_tick.c
<details>
```diff
@@ -26,7 +26,8 @@
#include "mcu/cmsis_nvic.h"
#include "fsl_clock.h"
-static void sys_tick_handler(void)
+static void
+sys_tick_handler(void)
{
uint32_t sr;
```
</details>
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org