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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/07/28 10:35:14 UTC
[GitHub] [incubator-nuttx] raiden00pl opened a new pull request, #6730: boards/stm32f7: add intial support for ST steval-eth001v board
raiden00pl opened a new pull request, #6730:
URL: https://github.com/apache/incubator-nuttx/pull/6730
## Summary
boards/stm32f7: add intial support for ST steval-eth001v board
## Impact
none
## Testing
nsh
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[GitHub] [incubator-nuttx] raiden00pl commented on a diff in pull request #6730: boards/stm32f7: add intial support for ST steval-eth001v1 board
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on code in PR #6730:
URL: https://github.com/apache/incubator-nuttx/pull/6730#discussion_r932093084
##########
boards/arm/stm32f7/steval-eth001v1/include/board.h:
##########
@@ -0,0 +1,216 @@
+/****************************************************************************
+ * boards/arm/stm32f7/steval-eth001v1/include/board.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H
+#define __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking */
+
+/* HSI: 16 MHz RC factory-trimmed
+ * LSI: 32 KHz RC
+ * HSE: On-board crystal frequency is 26MHz
+ * LSE: 32.768 kHz
+ */
+
+#define STM32_BOARD_XTAL 26000000ul
+
+#define STM32_HSI_FREQUENCY 16000000ul
+#define STM32_LSI_FREQUENCY 32000
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY 32768
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE = 26,000,000
+ *
+ * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
+ * Subject to:
+ *
+ * 2 <= PLLM <= 63
+ * 192 <= PLLN <= 432
+ * 192 MHz <= PLL_VCO <= 432MHz
+ *
+ * SYSCLK = PLL_VCO / PLLP
+ * Subject to
+ *
+ * PLLP = {2, 4, 6, 8}
+ * SYSCLK <= 216 MHz
+ *
+ * USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
+ * Subject to
+ * The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
+ * and the random number generator need a frequency lower than or equal
+ * to 48 MHz to work correctly.
+ *
+ * 2 <= PLLQ <= 15
+ */
+
+/* Highest SYSCLK
+ *
+ * PLL_VCO = (26,000,000 / 26) * 432 = 432 MHz
+ * SYSCLK = 432 MHz / 2 = 216 MHz
+ */
+
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
+#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
+#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10)
+
+#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 25) * 432)
+#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
+
+/* Configure Dedicated Clock Configuration Register */
+
+#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(0)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(0)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(1)
+#define STM32_RCC_DCKCFGR1_SAI1SRC 0
+#define STM32_RCC_DCKCFGR1_SAI2SRC 0
+#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
+#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
+#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
+
+/* Configure Dedicated Clock Configuration Register 2 */
+
+#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
+#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
+#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
+#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
+#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
+#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
+#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
+#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
+#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
+#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
+#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI
+#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
+#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
+
+/* Several prescalers allow the configuration of the two AHB buses, the
+ * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
+ * frequency of the two AHB buses is 216 MHz while the maximum frequency of
+ * the high-speed APB domains is 108 MHz. The maximum allowed frequency of
+ * the low-speed APB domain is 54 MHz.
+ */
+
+/* AHB clock (HCLK) is SYSCLK (216 MHz) */
+
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
Review Comment:
Thanks for the review ;]
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[GitHub] [incubator-nuttx] davids5 commented on a diff in pull request #6730: boards/stm32f7: add intial support for ST steval-eth001v1 board
Posted by GitBox <gi...@apache.org>.
davids5 commented on code in PR #6730:
URL: https://github.com/apache/incubator-nuttx/pull/6730#discussion_r932067674
##########
boards/arm/stm32f7/steval-eth001v1/include/board.h:
##########
@@ -0,0 +1,216 @@
+/****************************************************************************
+ * boards/arm/stm32f7/steval-eth001v1/include/board.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H
+#define __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking */
+
+/* HSI: 16 MHz RC factory-trimmed
+ * LSI: 32 KHz RC
+ * HSE: On-board crystal frequency is 26MHz
+ * LSE: 32.768 kHz
+ */
+
+#define STM32_BOARD_XTAL 26000000ul
+
+#define STM32_HSI_FREQUENCY 16000000ul
+#define STM32_LSI_FREQUENCY 32000
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY 32768
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE = 26,000,000
+ *
+ * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
+ * Subject to:
+ *
+ * 2 <= PLLM <= 63
+ * 192 <= PLLN <= 432
+ * 192 MHz <= PLL_VCO <= 432MHz
+ *
+ * SYSCLK = PLL_VCO / PLLP
+ * Subject to
+ *
+ * PLLP = {2, 4, 6, 8}
+ * SYSCLK <= 216 MHz
+ *
+ * USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
+ * Subject to
+ * The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
+ * and the random number generator need a frequency lower than or equal
+ * to 48 MHz to work correctly.
+ *
+ * 2 <= PLLQ <= 15
+ */
+
+/* Highest SYSCLK
+ *
+ * PLL_VCO = (26,000,000 / 26) * 432 = 432 MHz
+ * SYSCLK = 432 MHz / 2 = 216 MHz
+ */
+
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
+#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
+#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10)
+
+#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 25) * 432)
Review Comment:
26?
##########
boards/arm/stm32f7/steval-eth001v1/include/board.h:
##########
@@ -0,0 +1,216 @@
+/****************************************************************************
+ * boards/arm/stm32f7/steval-eth001v1/include/board.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H
+#define __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking */
+
+/* HSI: 16 MHz RC factory-trimmed
+ * LSI: 32 KHz RC
+ * HSE: On-board crystal frequency is 26MHz
+ * LSE: 32.768 kHz
+ */
+
+#define STM32_BOARD_XTAL 26000000ul
+
+#define STM32_HSI_FREQUENCY 16000000ul
+#define STM32_LSI_FREQUENCY 32000
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY 32768
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE = 26,000,000
+ *
+ * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
+ * Subject to:
+ *
+ * 2 <= PLLM <= 63
+ * 192 <= PLLN <= 432
+ * 192 MHz <= PLL_VCO <= 432MHz
+ *
+ * SYSCLK = PLL_VCO / PLLP
+ * Subject to
+ *
+ * PLLP = {2, 4, 6, 8}
+ * SYSCLK <= 216 MHz
+ *
+ * USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
+ * Subject to
+ * The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
+ * and the random number generator need a frequency lower than or equal
+ * to 48 MHz to work correctly.
+ *
+ * 2 <= PLLQ <= 15
+ */
+
+/* Highest SYSCLK
+ *
+ * PLL_VCO = (26,000,000 / 26) * 432 = 432 MHz
+ * SYSCLK = 432 MHz / 2 = 216 MHz
+ */
+
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
+#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
+#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10)
+
+#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 25) * 432)
+#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
+
+/* Configure Dedicated Clock Configuration Register */
+
+#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(0)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(0)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(1)
+#define STM32_RCC_DCKCFGR1_SAI1SRC 0
+#define STM32_RCC_DCKCFGR1_SAI2SRC 0
+#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
+#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
+#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
+
+/* Configure Dedicated Clock Configuration Register 2 */
+
+#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
+#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
+#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
+#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
+#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
+#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
+#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
+#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
+#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
+#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
+#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI
+#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
+#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
+
+/* Several prescalers allow the configuration of the two AHB buses, the
+ * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
+ * frequency of the two AHB buses is 216 MHz while the maximum frequency of
+ * the high-speed APB domains is 108 MHz. The maximum allowed frequency of
+ * the low-speed APB domain is 54 MHz.
+ */
+
+/* AHB clock (HCLK) is SYSCLK (216 MHz) */
+
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
Review Comment:
Above is SYSCLK = 432 MHz / 2 - Should it be 2 here as well?
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[GitHub] [incubator-nuttx] raiden00pl commented on a diff in pull request #6730: boards/stm32f7: add intial support for ST steval-eth001v1 board
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on code in PR #6730:
URL: https://github.com/apache/incubator-nuttx/pull/6730#discussion_r932083925
##########
boards/arm/stm32f7/steval-eth001v1/include/board.h:
##########
@@ -0,0 +1,216 @@
+/****************************************************************************
+ * boards/arm/stm32f7/steval-eth001v1/include/board.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H
+#define __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking */
+
+/* HSI: 16 MHz RC factory-trimmed
+ * LSI: 32 KHz RC
+ * HSE: On-board crystal frequency is 26MHz
+ * LSE: 32.768 kHz
+ */
+
+#define STM32_BOARD_XTAL 26000000ul
+
+#define STM32_HSI_FREQUENCY 16000000ul
+#define STM32_LSI_FREQUENCY 32000
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY 32768
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE = 26,000,000
+ *
+ * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
+ * Subject to:
+ *
+ * 2 <= PLLM <= 63
+ * 192 <= PLLN <= 432
+ * 192 MHz <= PLL_VCO <= 432MHz
+ *
+ * SYSCLK = PLL_VCO / PLLP
+ * Subject to
+ *
+ * PLLP = {2, 4, 6, 8}
+ * SYSCLK <= 216 MHz
+ *
+ * USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
+ * Subject to
+ * The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
+ * and the random number generator need a frequency lower than or equal
+ * to 48 MHz to work correctly.
+ *
+ * 2 <= PLLQ <= 15
+ */
+
+/* Highest SYSCLK
+ *
+ * PLL_VCO = (26,000,000 / 26) * 432 = 432 MHz
+ * SYSCLK = 432 MHz / 2 = 216 MHz
+ */
+
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
+#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
+#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10)
+
+#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 25) * 432)
+#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
+
+/* Configure Dedicated Clock Configuration Register */
+
+#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(0)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(0)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(1)
+#define STM32_RCC_DCKCFGR1_SAI1SRC 0
+#define STM32_RCC_DCKCFGR1_SAI2SRC 0
+#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
+#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
+#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
+
+/* Configure Dedicated Clock Configuration Register 2 */
+
+#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
+#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
+#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
+#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
+#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
+#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
+#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
+#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
+#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
+#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
+#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI
+#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
+#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
+
+/* Several prescalers allow the configuration of the two AHB buses, the
+ * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
+ * frequency of the two AHB buses is 216 MHz while the maximum frequency of
+ * the high-speed APB domains is 108 MHz. The maximum allowed frequency of
+ * the low-speed APB domain is 54 MHz.
+ */
+
+/* AHB clock (HCLK) is SYSCLK (216 MHz) */
+
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
Review Comment:
I'm not sure what you mean. HCLK is not divided SYSCLK, so HCLK = SYSCLK / 1 is correct.
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[GitHub] [incubator-nuttx] raiden00pl commented on a diff in pull request #6730: boards/stm32f7: add intial support for ST steval-eth001v1 board
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on code in PR #6730:
URL: https://github.com/apache/incubator-nuttx/pull/6730#discussion_r932076544
##########
boards/arm/stm32f7/steval-eth001v1/include/board.h:
##########
@@ -0,0 +1,216 @@
+/****************************************************************************
+ * boards/arm/stm32f7/steval-eth001v1/include/board.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H
+#define __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking */
+
+/* HSI: 16 MHz RC factory-trimmed
+ * LSI: 32 KHz RC
+ * HSE: On-board crystal frequency is 26MHz
+ * LSE: 32.768 kHz
+ */
+
+#define STM32_BOARD_XTAL 26000000ul
+
+#define STM32_HSI_FREQUENCY 16000000ul
+#define STM32_LSI_FREQUENCY 32000
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY 32768
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE = 26,000,000
+ *
+ * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
+ * Subject to:
+ *
+ * 2 <= PLLM <= 63
+ * 192 <= PLLN <= 432
+ * 192 MHz <= PLL_VCO <= 432MHz
+ *
+ * SYSCLK = PLL_VCO / PLLP
+ * Subject to
+ *
+ * PLLP = {2, 4, 6, 8}
+ * SYSCLK <= 216 MHz
+ *
+ * USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
+ * Subject to
+ * The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
+ * and the random number generator need a frequency lower than or equal
+ * to 48 MHz to work correctly.
+ *
+ * 2 <= PLLQ <= 15
+ */
+
+/* Highest SYSCLK
+ *
+ * PLL_VCO = (26,000,000 / 26) * 432 = 432 MHz
+ * SYSCLK = 432 MHz / 2 = 216 MHz
+ */
+
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
+#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
+#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10)
+
+#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 25) * 432)
Review Comment:
fixed
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[GitHub] [incubator-nuttx] xiaoxiang781216 merged pull request #6730: boards/stm32f7: add intial support for ST steval-eth001v1 board
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 merged PR #6730:
URL: https://github.com/apache/incubator-nuttx/pull/6730
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[GitHub] [incubator-nuttx] davids5 commented on a diff in pull request #6730: boards/stm32f7: add intial support for ST steval-eth001v1 board
Posted by GitBox <gi...@apache.org>.
davids5 commented on code in PR #6730:
URL: https://github.com/apache/incubator-nuttx/pull/6730#discussion_r932090468
##########
boards/arm/stm32f7/steval-eth001v1/include/board.h:
##########
@@ -0,0 +1,216 @@
+/****************************************************************************
+ * boards/arm/stm32f7/steval-eth001v1/include/board.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H
+#define __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking */
+
+/* HSI: 16 MHz RC factory-trimmed
+ * LSI: 32 KHz RC
+ * HSE: On-board crystal frequency is 26MHz
+ * LSE: 32.768 kHz
+ */
+
+#define STM32_BOARD_XTAL 26000000ul
+
+#define STM32_HSI_FREQUENCY 16000000ul
+#define STM32_LSI_FREQUENCY 32000
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY 32768
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE = 26,000,000
+ *
+ * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
+ * Subject to:
+ *
+ * 2 <= PLLM <= 63
+ * 192 <= PLLN <= 432
+ * 192 MHz <= PLL_VCO <= 432MHz
+ *
+ * SYSCLK = PLL_VCO / PLLP
+ * Subject to
+ *
+ * PLLP = {2, 4, 6, 8}
+ * SYSCLK <= 216 MHz
+ *
+ * USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
+ * Subject to
+ * The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
+ * and the random number generator need a frequency lower than or equal
+ * to 48 MHz to work correctly.
+ *
+ * 2 <= PLLQ <= 15
+ */
+
+/* Highest SYSCLK
+ *
+ * PLL_VCO = (26,000,000 / 26) * 432 = 432 MHz
+ * SYSCLK = 432 MHz / 2 = 216 MHz
+ */
+
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
+#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
+#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10)
+
+#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 25) * 432)
+#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
+
+/* Configure Dedicated Clock Configuration Register */
+
+#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(0)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(0)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(1)
+#define STM32_RCC_DCKCFGR1_SAI1SRC 0
+#define STM32_RCC_DCKCFGR1_SAI2SRC 0
+#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
+#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
+#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
+
+/* Configure Dedicated Clock Configuration Register 2 */
+
+#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
+#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
+#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
+#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
+#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
+#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
+#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
+#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
+#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
+#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
+#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI
+#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
+#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
+
+/* Several prescalers allow the configuration of the two AHB buses, the
+ * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
+ * frequency of the two AHB buses is 216 MHz while the maximum frequency of
+ * the high-speed APB domains is 108 MHz. The maximum allowed frequency of
+ * the low-speed APB domain is 54 MHz.
+ */
+
+/* AHB clock (HCLK) is SYSCLK (216 MHz) */
+
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
Review Comment:
My bad; SYSCLK = 432 MHz / 2 = 216 MHz confused me
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