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Posted to commits@nuttx.apache.org by ac...@apache.org on 2020/11/26 21:42:31 UTC
[incubator-nuttx] 05/05: Fix nxstyle warning
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit d6c24312aa94430ff68a8430484b1972dbee6e66
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Fri Nov 27 00:33:25 2020 +0800
Fix nxstyle warning
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
---
libs/libc/machine/arm/armv8-m/arch_ceil.c | 2 +-
libs/libc/machine/arm/armv8-m/arch_ceilf.c | 2 +-
libs/libc/machine/arm/armv8-m/arch_elf.c | 56 ++++++++++++++---------------
libs/libc/machine/arm/armv8-m/arch_floorf.c | 2 +-
4 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/libs/libc/machine/arm/armv8-m/arch_ceil.c b/libs/libc/machine/arm/armv8-m/arch_ceil.c
index 9394fde..4210245 100644
--- a/libs/libc/machine/arm/armv8-m/arch_ceil.c
+++ b/libs/libc/machine/arm/armv8-m/arch_ceil.c
@@ -48,7 +48,7 @@
double ceil(double x)
{
double result;
- asm volatile ( "vrintp.f64\t%P0, %P1" : "=w" (result) : "w" (x) );
+ asm volatile("vrintp.f64\t%P0, %P1" : "=w"(result) : "w"(x));
return result;
}
diff --git a/libs/libc/machine/arm/armv8-m/arch_ceilf.c b/libs/libc/machine/arm/armv8-m/arch_ceilf.c
index 490c4ca..ed27ec7 100644
--- a/libs/libc/machine/arm/armv8-m/arch_ceilf.c
+++ b/libs/libc/machine/arm/armv8-m/arch_ceilf.c
@@ -48,7 +48,7 @@
float ceilf(float x)
{
float result;
- asm volatile ( "vrintp.f32\t%0, %1" : "=t" (result) : "t" (x) );
+ asm volatile("vrintp.f32\t%0, %1" : "=t"(result) : "t"(x));
return result;
}
diff --git a/libs/libc/machine/arm/armv8-m/arch_elf.c b/libs/libc/machine/arm/armv8-m/arch_elf.c
index 6664584..a70f100 100644
--- a/libs/libc/machine/arm/armv8-m/arch_elf.c
+++ b/libs/libc/machine/arm/armv8-m/arch_elf.c
@@ -210,23 +210,23 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
*
* upper_insn:
*
- * 1 1 1 1 1 1
- * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +----------+---+-------------------------------+--------------+
- * |1 1 1 |OP1| OP2 | | 32-Bit Instructions
- * +----------+---+--+-----+----------------------+--------------+
- * |1 1 1 | 1 0| S | imm10 | BL Instruction
- * +----------+------+-----+-------------------------------------+
+ * 1 1 1 1 1 1
+ * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-------+---+----------------------+-----------+
+ * |1 1 1|OP1| OP2 | | 32Bit Instruction
+ * +-------+---+-+---+----------------+-----------+
+ * |1 1 1| 1 0| S | imm10 | BL Instruction
+ * +-------+-----+---+----------------------------+
*
* lower_insn:
*
- * 1 1 1 1 1 1
- * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +---+---------------------------------------------------------+
- * |OP | | 32-Bit Instructions
- * +---+--+---+---+---+------------------------------------------+
- * |1 1 |J1 | 1 |J2 | imm11 | BL Instruction
- * +------+---+---+---+------------------------------------------+
+ * 1 1 1 1 1 1
+ * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +--+-------------------------------------------+
+ * |OP| | 32Bit Instruction
+ * +--+-+--+--+--+--------------------------------+
+ * |1 1|J1| 1|J2| imm11 | BL Instruction
+ * +----+--+--+--+--------------------------------+
*
* The branch target is encoded in these bits:
*
@@ -385,23 +385,23 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
*
* upper_insn:
*
- * 1 1 1 1 1 1
- * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +----------+---+-------------------------------+--------------+
- * |1 1 1 |OP1| OP2 | | 32-Bit Instructions
- * +----------+---+--+-----+----------------------+--------------+
- * |1 1 1 | 1 0| i | 1 0 1 1 0 0 | imm4 | MOVT Instruction
- * +----------+------+-----+----------------------+--------------+
+ * 1 1 1 1 1 1
+ * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-------+---+-----------------------+----------+
+ * |1 1 1|OP1| OP2 | | 32Bit Instruction
+ * +-------+---+-+---+-----------------+----------+
+ * |1 1 1| 1 0| i | 1 0 1 1 0 0 | imm4 | MOVT Instruction
+ * +-------+-----+---+-----------------+----------+
*
* lower_insn:
*
- * 1 1 1 1 1 1
- * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +---+---------------------------------------------------------+
- * |OP | | 32-Bit Instructions
- * +---+----------+--------------+-------------------------------+
- * |0 | imm3 | Rd | imm8 | MOVT Instruction
- * +---+----------+--------------+-------------------------------+
+ * 1 1 1 1 1 1
+ * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +--+-------------------------------------------+
+ * |OP| | 32Bit Instruction
+ * +--+--------+----------+-----------------------+
+ * |0 | imm3 | Rd | imm8 | MOVT Instruction
+ * +--+--------+----------+-----------------------+
*
* The 16-bit immediate value is encoded in these bits:
*
diff --git a/libs/libc/machine/arm/armv8-m/arch_floorf.c b/libs/libc/machine/arm/armv8-m/arch_floorf.c
index 6adb678..5d481ec 100644
--- a/libs/libc/machine/arm/armv8-m/arch_floorf.c
+++ b/libs/libc/machine/arm/armv8-m/arch_floorf.c
@@ -48,7 +48,7 @@
float floorf(float x)
{
float result;
- asm volatile ( "vrintm.f32\t%0, %1" : "=t" (result) : "t" (x) );
+ asm volatile("vrintm.f32\t%0, %1" : "=t"(result) : "t"(x));
return result;
}