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Posted to commits@nuttx.apache.org by ac...@apache.org on 2023/08/14 19:29:27 UTC
[nuttx] branch master updated (14563aa48c -> 281ab83309)
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
from 14563aa48c arch/armv7r: Sync gic/timer with armv7-a and armv8-a
new 7dafbb05a1 esp32s3/peripherals: Add initialization routine for the peripherals
new 31476bcb34 esp32s3/rtc: Initialize RTC subsystem
new 6089f58f00 esp32s3/irq: Enhance IRQ subsystem
new ec4149c61d esp32s3/hardware: Update `regi2c_ctrl.h` functions name
new 6589887284 esp32s3/wlan: check if the network device's IOB isn't null
new 012dddf7c9 esp32s3/wlan: check for all connections on wlan_txpoll
new 33f03fc98c esp32s3/wlan: Always run `wlan_rxpoll` work queue
new 655d00b1e7 arch/xtensa/esp32s3: initial effort to get BLE running on ESP32-S3
new 7d605551cd esp32s3/wifi: Enable peripheral interrupt to the same CPU interrupt
new 01b6c87b15 esp32s3: Implement the Wi-Fi/BLE coexistence
new 6f235c5f0a esp32-devkitc: Enable softAP on `blewifi` defconfig to ease testing
new 281ab83309 esp32s3: Use `PANIC()` instead of `assert(0)`
The 12 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/xtensa/include/esp32s3/irq.h | 18 +-
arch/xtensa/src/esp32s3/Kconfig | 74 +-
arch/xtensa/src/esp32s3/Make.defs | 4 +-
arch/xtensa/src/esp32s3/Wireless.mk | 21 +-
arch/xtensa/src/esp32s3/esp32s3_ble.c | 325 +++
arch/xtensa/src/esp32s3/esp32s3_ble.h | 50 +
arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c | 2690 ++++++++++++++++++++
.../{esp32s3_wireless.h => esp32s3_ble_adapter.h} | 117 +-
arch/xtensa/src/esp32s3/esp32s3_irq.c | 88 +-
arch/xtensa/src/esp32s3/esp32s3_irq.h | 18 +
arch/xtensa/src/esp32s3/esp32s3_periph.c | 715 ++++++
.../{esp32s3_wireless.h => esp32s3_periph.h} | 159 +-
arch/xtensa/src/esp32s3/esp32s3_reset_reasons.h | 101 +
arch/xtensa/src/esp32s3/esp32s3_rtc.c | 46 +-
arch/xtensa/src/esp32s3/esp32s3_rtc.h | 22 +-
arch/xtensa/src/esp32s3/esp32s3_start.c | 11 +
arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c | 828 ++++--
arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h | 19 +
arch/xtensa/src/esp32s3/esp32s3_wireless.c | 260 +-
arch/xtensa/src/esp32s3/esp32s3_wireless.h | 105 +-
arch/xtensa/src/esp32s3/esp32s3_wlan.c | 28 +-
arch/xtensa/src/esp32s3/hardware/esp32s3_bb.h | 60 +
arch/xtensa/src/esp32s3/hardware/esp32s3_fe.h | 62 +
arch/xtensa/src/esp32s3/hardware/esp32s3_nrx.h | 80 +
arch/xtensa/src/esp32s3/hardware/esp32s3_system.h | 20 +-
arch/xtensa/src/esp32s3/hardware/regi2c_ctrl.h | 27 +-
.../esp32/esp32-devkitc/configs/blewifi/defconfig | 1 +
.../esp32s3/common/scripts/esp32s3_aliases.ld | 29 +
.../xtensa/esp32s3/common/scripts/esp32s3_rom.ld | 213 +-
.../esp32s3/common/scripts/esp32s3_rom_aliases.ld | 37 +
.../esp32s3/common/scripts/esp32s3_rom_api.ld | 79 +
.../xtensa/esp32s3/common/scripts/flat_memory.ld | 2 +
.../esp32s3/common/scripts/protected_memory.ld | 2 +
.../esp32s3/esp32s3-devkit/configs/ble/defconfig | 71 +
.../esp32s3-devkit/configs/blewifi/defconfig | 100 +
.../esp32s3/esp32s3-devkit/scripts/Make.defs | 2 +
.../esp32s3/esp32s3-devkit/src/esp32s3_bringup.c | 28 +
.../xtensa/esp32s3/esp32s3-eye/scripts/Make.defs | 2 +
.../esp32s3/esp32s3-meadow/scripts/Make.defs | 2 +
39 files changed, 5885 insertions(+), 631 deletions(-)
create mode 100644 arch/xtensa/src/esp32s3/esp32s3_ble.c
create mode 100644 arch/xtensa/src/esp32s3/esp32s3_ble.h
create mode 100644 arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c
copy arch/xtensa/src/esp32s3/{esp32s3_wireless.h => esp32s3_ble_adapter.h} (57%)
create mode 100644 arch/xtensa/src/esp32s3/esp32s3_periph.c
copy arch/xtensa/src/esp32s3/{esp32s3_wireless.h => esp32s3_periph.h} (55%)
create mode 100644 arch/xtensa/src/esp32s3/esp32s3_reset_reasons.h
create mode 100644 arch/xtensa/src/esp32s3/hardware/esp32s3_bb.h
create mode 100644 arch/xtensa/src/esp32s3/hardware/esp32s3_fe.h
create mode 100644 arch/xtensa/src/esp32s3/hardware/esp32s3_nrx.h
create mode 100644 boards/xtensa/esp32s3/common/scripts/esp32s3_aliases.ld
create mode 100644 boards/xtensa/esp32s3/common/scripts/esp32s3_rom_aliases.ld
create mode 100644 boards/xtensa/esp32s3/common/scripts/esp32s3_rom_api.ld
create mode 100644 boards/xtensa/esp32s3/esp32s3-devkit/configs/ble/defconfig
create mode 100644 boards/xtensa/esp32s3/esp32s3-devkit/configs/blewifi/defconfig
[nuttx] 02/12: esp32s3/rtc: Initialize RTC subsystem
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 31476bcb34d039ba7fb42a142e7c9adacebf8f31
Author: Tiago Medicci Serrano <ti...@espressif.com>
AuthorDate: Tue Aug 8 08:48:43 2023 -0300
esp32s3/rtc: Initialize RTC subsystem
RTC subsystem controls not only the RTC itself but functions that
use RTC-enabled features like Bluetooth and Wi-Fi. Initialization
must be performed during the system start-up.
---
arch/xtensa/src/esp32s3/esp32s3_rtc.c | 46 ++++++++++-----
arch/xtensa/src/esp32s3/esp32s3_rtc.h | 22 ++-----
arch/xtensa/src/esp32s3/esp32s3_start.c | 6 ++
arch/xtensa/src/esp32s3/hardware/esp32s3_bb.h | 60 +++++++++++++++++++
arch/xtensa/src/esp32s3/hardware/esp32s3_fe.h | 62 ++++++++++++++++++++
arch/xtensa/src/esp32s3/hardware/esp32s3_nrx.h | 80 ++++++++++++++++++++++++++
6 files changed, 245 insertions(+), 31 deletions(-)
diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc.c b/arch/xtensa/src/esp32s3/esp32s3_rtc.c
index 730e5dbaa4..ebc18ee078 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_rtc.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_rtc.c
@@ -34,6 +34,9 @@
#include "esp32s3_clockconfig.h"
#include "esp32s3_rt_timer.h"
+#include "hardware/esp32s3_bb.h"
+#include "hardware/esp32s3_nrx.h"
+#include "hardware/esp32s3_fe.h"
#include "hardware/esp32s3_rtccntl.h"
#include "hardware/esp32s3_rtc_io.h"
#include "hardware/esp32s3_system.h"
@@ -111,10 +114,6 @@
#define RCT_FAST_D256_FREQ_APPROX (RTC_FAST_CLK_FREQ_APPROX / 256)
#define RTC_SLOW_CLK_FREQ_APPROX 32768
-/* Number of fractional bits in values returned by rtc_clk_cal */
-
-#define RTC_CLK_CAL_FRACT 19
-
/* Disable logging from the ROM code. */
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16))
@@ -421,10 +420,30 @@ extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
static void IRAM_ATTR
esp32s3_rtc_sleep_pu(struct esp32s3_rtc_sleep_pu_config_s cfg)
{
+ REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG,
+ RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
+ REG_SET_FIELD(RTC_CNTL_RTC_PWC_REG,
+ RTC_CNTL_RTC_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
+ REG_SET_FIELD(RTC_CNTL_RTC_PWC_REG,
+ RTC_CNTL_RTC_SLOWMEM_FORCE_LPU, cfg.rtc_fpu);
+ REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG,
+ SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu);
+ REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG,
+ SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
+ REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG,
+ SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu);
+ REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
+ REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
+ REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
+ REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu);
+ REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
+ REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
+ REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
+
if (cfg.sram_fpu)
{
- REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP,
- SYSCON_SRAM_POWER_UP);
+ REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG,
+ SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP);
}
else
{
@@ -1496,6 +1515,14 @@ void IRAM_ATTR esp32s3_rtc_init(void)
/* set wifi timer */
+ REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, 1);
+ REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, 1);
+
+ /* set bt timer */
+
+ REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, 1);
+ REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, 1);
+
/* Reset RTC bias to default value (needed if waking up from deep sleep) */
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP,
@@ -2507,13 +2534,6 @@ int up_rtc_settime(const struct timespec *ts)
int up_rtc_initialize(void)
{
-#ifndef CONFIG_PM
- /* Initialize RTC controller parameters */
-
- esp32s3_rtc_init();
- esp32s3_rtc_clk_set();
-#endif
-
g_rtc_save = &rtc_saved_data;
/* If saved data is invalid, clear offset information */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc.h b/arch/xtensa/src/esp32s3/esp32s3_rtc.h
index 21d57aef4e..dae9db3135 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_rtc.h
+++ b/arch/xtensa/src/esp32s3/esp32s3_rtc.h
@@ -64,6 +64,10 @@ extern "C"
#define EXT_OSC_FLAG BIT(3)
+/* Number of fractional bits in values returned by rtc_clk_cal */
+
+#define RTC_CLK_CAL_FRACT 19
+
/****************************************************************************
* Public Types
****************************************************************************/
@@ -298,24 +302,6 @@ void esp32s3_rtc_update_to_xtal(int freq, int div);
void esp32s3_rtc_bbpll_enable(void);
-/****************************************************************************
- * Name: esp32s3_rtc_bbpll_configure
- *
- * Description:
- * Configure main XTAL frequency values according to pll_freq.
- *
- * Input Parameters:
- * xtal_freq - XTAL frequency values
- * pll_freq - PLL frequency values
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
-static void IRAM_ATTR esp32s3_rtc_bbpll_configure(
- enum esp32s3_rtc_xtal_freq_e xtal_freq, int pll_freq);
-
/****************************************************************************
* Name: esp32s3_rtc_clk_set
*
diff --git a/arch/xtensa/src/esp32s3/esp32s3_start.c b/arch/xtensa/src/esp32s3/esp32s3_start.c
index d2b0bb9c58..0db7633620 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_start.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_start.c
@@ -38,6 +38,7 @@
#include "esp32s3_clockconfig.h"
#include "esp32s3_region.h"
#include "esp32s3_periph.h"
+#include "esp32s3_rtc.h"
#include "esp32s3_spiram.h"
#include "esp32s3_wdt.h"
#ifdef CONFIG_BUILD_PROTECTED
@@ -322,6 +323,11 @@ void noreturn_function IRAM_ATTR __esp32s3_start(void)
esp32s3_wdt_early_deinit();
+ /* Initialize RTC controller parameters */
+
+ esp32s3_rtc_init();
+ esp32s3_rtc_clk_set();
+
/* Set CPU frequency configured in board.h */
esp32s3_clockconfig();
diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_bb.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_bb.h
new file mode 100644
index 0000000000..16bce13ae8
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_bb.h
@@ -0,0 +1,60 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_bb.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_BB_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_BB_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Some of the baseband control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
+
+#define BB_FFT_FORCE_PU (BIT(3))
+#define BB_FFT_FORCE_PU_M (BIT(3))
+#define BB_FFT_FORCE_PU_V 1
+#define BB_FFT_FORCE_PU_S 3
+
+#define BB_FFT_FORCE_PD (BIT(2))
+#define BB_FFT_FORCE_PD_M (BIT(2))
+#define BB_FFT_FORCE_PD_V 1
+#define BB_FFT_FORCE_PD_S 2
+
+#define BB_DC_EST_FORCE_PU (BIT(1))
+#define BB_DC_EST_FORCE_PU_M (BIT(1))
+#define BB_DC_EST_FORCE_PU_V 1
+#define BB_DC_EST_FORCE_PU_S 1
+
+#define BB_DC_EST_FORCE_PD (BIT(0))
+#define BB_DC_EST_FORCE_PD_M (BIT(0))
+#define BB_DC_EST_FORCE_PD_V 1
+#define BB_DC_EST_FORCE_PD_S 0
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_BB_H */
diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_fe.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_fe.h
new file mode 100644
index 0000000000..35bfb1361f
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_fe.h
@@ -0,0 +1,62 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_fe.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_FE_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_FE_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Some of the RF frontend control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
+
+#define FE_IQ_EST_FORCE_PU (BIT(5))
+#define FE_IQ_EST_FORCE_PU_M (BIT(5))
+#define FE_IQ_EST_FORCE_PU_V 1
+#define FE_IQ_EST_FORCE_PU_S 5
+
+#define FE_IQ_EST_FORCE_PD (BIT(4))
+#define FE_IQ_EST_FORCE_PD_M (BIT(4))
+#define FE_IQ_EST_FORCE_PD_V 1
+#define FE_IQ_EST_FORCE_PD_S 4
+
+#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
+
+#define FE2_TX_INF_FORCE_PU (BIT(10))
+#define FE2_TX_INF_FORCE_PU_M (BIT(10))
+#define FE2_TX_INF_FORCE_PU_V 1
+#define FE2_TX_INF_FORCE_PU_S 10
+
+#define FE2_TX_INF_FORCE_PD (BIT(9))
+#define FE2_TX_INF_FORCE_PD_M (BIT(9))
+#define FE2_TX_INF_FORCE_PD_V 1
+#define FE2_TX_INF_FORCE_PD_S 9
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_FE_H */
diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_nrx.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_nrx.h
new file mode 100644
index 0000000000..0937525824
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_nrx.h
@@ -0,0 +1,80 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_nrx.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_NRX_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_NRX_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Some of the WiFi RX control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
+
+#define NRX_CHAN_EST_FORCE_PU (BIT(7))
+#define NRX_CHAN_EST_FORCE_PU_M (BIT(7))
+#define NRX_CHAN_EST_FORCE_PU_V 1
+#define NRX_CHAN_EST_FORCE_PU_S 7
+
+#define NRX_CHAN_EST_FORCE_PD (BIT(6))
+#define NRX_CHAN_EST_FORCE_PD_M (BIT(6))
+#define NRX_CHAN_EST_FORCE_PD_V 1
+#define NRX_CHAN_EST_FORCE_PD_S 6
+
+#define NRX_RX_ROT_FORCE_PU (BIT(5))
+#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
+#define NRX_RX_ROT_FORCE_PU_V 1
+#define NRX_RX_ROT_FORCE_PU_S 5
+
+#define NRX_RX_ROT_FORCE_PD (BIT(4))
+#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
+#define NRX_RX_ROT_FORCE_PD_V 1
+#define NRX_RX_ROT_FORCE_PD_S 4
+
+#define NRX_VIT_FORCE_PU (BIT(3))
+#define NRX_VIT_FORCE_PU_M (BIT(3))
+#define NRX_VIT_FORCE_PU_V 1
+#define NRX_VIT_FORCE_PU_S 3
+
+#define NRX_VIT_FORCE_PD (BIT(2))
+#define NRX_VIT_FORCE_PD_M (BIT(2))
+#define NRX_VIT_FORCE_PD_V 1
+#define NRX_VIT_FORCE_PD_S 2
+
+#define NRX_DEMAP_FORCE_PU (BIT(1))
+#define NRX_DEMAP_FORCE_PU_M (BIT(1))
+#define NRX_DEMAP_FORCE_PU_V 1
+#define NRX_DEMAP_FORCE_PU_S 1
+
+#define NRX_DEMAP_FORCE_PD (BIT(0))
+#define NRX_DEMAP_FORCE_PD_M (BIT(0))
+#define NRX_DEMAP_FORCE_PD_V 1
+#define NRX_DEMAP_FORCE_PD_S 0
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_NRX_H */
[nuttx] 03/12: esp32s3/irq: Enhance IRQ subsystem
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 6089f58f00a80b15bcbfdf9d03cf523becd7d6ce
Author: Tiago Medicci Serrano <ti...@espressif.com>
AuthorDate: Tue Aug 1 15:02:52 2023 -0300
esp32s3/irq: Enhance IRQ subsystem
- Fix macro values from `arch/xtensa/include/esp32s3/irq.h`
- Remove references to unexisting edge-triggered CPU interrupts
- Add `esp32s3_getirq` to get IRQ based on core and the `cpuint`
---
arch/xtensa/include/esp32s3/irq.h | 10 ++----
arch/xtensa/src/esp32s3/esp32s3_irq.c | 61 ++++++++++++++++++++++++-----------
arch/xtensa/src/esp32s3/esp32s3_irq.h | 18 +++++++++++
3 files changed, 62 insertions(+), 27 deletions(-)
diff --git a/arch/xtensa/include/esp32s3/irq.h b/arch/xtensa/include/esp32s3/irq.h
index 7f6f49a14c..591384a0fa 100644
--- a/arch/xtensa/include/esp32s3/irq.h
+++ b/arch/xtensa/include/esp32s3/irq.h
@@ -438,15 +438,9 @@
#define ESP32S3_CPUINT_LEVELPERIPH_20 31
#define ESP32S3_CPUINT_NLEVELPERIPHS 21
-#define ESP32S3_CPUINT_LEVELSET 0x8fbe333f
+#define ESP32S3_CPUINT_LEVELSET 0xdffe373f
-#define ESP32S3_CPUINT_EDGEPERIPH_0 10
-#define ESP32S3_CPUINT_EDGEPERIPH_1 22
-#define ESP32S3_CPUINT_EDGEPERIPH_2 28
-#define ESP32S3_CPUINT_EDGEPERIPH_3 30
-
-#define ESP32S3_CPUINT_NEDGEPERIPHS 4
-#define ESP32S3_CPUINT_EDGESET 0x50400400
+#define ESP32S3_CPUINT_NEDGEPERIPHS 0
#define ESP32S3_CPUINT_NNMIPERIPHS 1
#define ESP32S3_CPUINT_NMISET 0x00004000
diff --git a/arch/xtensa/src/esp32s3/esp32s3_irq.c b/arch/xtensa/src/esp32s3/esp32s3_irq.c
index 0e8abdf90a..5303f441aa 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_irq.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_irq.c
@@ -346,27 +346,14 @@ static int esp32s3_alloc_cpuint(int priority, int type)
DEBUGASSERT(priority >= ESP32S3_MIN_PRIORITY &&
priority <= ESP32S3_MAX_PRIORITY);
- DEBUGASSERT(type == ESP32S3_CPUINT_LEVEL ||
- type == ESP32S3_CPUINT_EDGE);
+ DEBUGASSERT(type == ESP32S3_CPUINT_LEVEL);
- if (type == ESP32S3_CPUINT_LEVEL)
- {
- /* Check if there are any level CPU interrupts available at the
- * requested interrupt priority.
- */
-
- mask = g_priority[ESP32S3_PRIO_INDEX(priority)] &
- ESP32S3_CPUINT_LEVELSET;
- }
- else
- {
- /* Check if there are any edge CPU interrupts available at the
- * requested interrupt priority.
- */
+ /* Check if there are any level CPU interrupts available at the
+ * requested interrupt priority.
+ */
- mask = g_priority[ESP32S3_PRIO_INDEX(priority)] &
- ESP32S3_CPUINT_EDGESET;
- }
+ mask = g_priority[ESP32S3_PRIO_INDEX(priority)] &
+ ESP32S3_CPUINT_LEVELSET;
return esp32s3_getcpuint(mask);
}
@@ -834,6 +821,42 @@ void esp32s3_teardown_irq(int cpu, int periphid, int cpuint)
leave_critical_section(irqstate);
}
+/****************************************************************************
+ * Name: esp32s3_getirq
+ *
+ * Description:
+ * This function returns the IRQ associated with a CPU interrupt
+ *
+ * Input Parameters:
+ * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
+ * cpuint - The CPU interrupt associated to the IRQ
+ *
+ * Returned Value:
+ * The IRQ associated with such CPU interrupt or CPUINT_UNASSIGNED if
+ * IRQ is not yet assigned to a CPU interrupt.
+ *
+ ****************************************************************************/
+
+int esp32s3_getirq(int cpu, int cpuint)
+{
+ uint8_t *intmap;
+
+#ifdef CONFIG_SMP
+ /* Select PRO or APP CPU interrupt mapping table */
+
+ if (cpu != 0)
+ {
+ intmap = g_cpu1_intmap;
+ }
+ else
+#endif
+ {
+ intmap = g_cpu0_intmap;
+ }
+
+ return CPUINT_GETIRQ(intmap[cpuint]);
+}
+
/****************************************************************************
* Name: xtensa_int_decode
*
diff --git a/arch/xtensa/src/esp32s3/esp32s3_irq.h b/arch/xtensa/src/esp32s3/esp32s3_irq.h
index 2ef8f26e31..6119cf7348 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_irq.h
+++ b/arch/xtensa/src/esp32s3/esp32s3_irq.h
@@ -114,6 +114,24 @@ int esp32s3_setup_irq(int cpu, int periphid, int priority, int type);
void esp32s3_teardown_irq(int cpu, int periphid, int cpuint);
+/****************************************************************************
+ * Name: esp32s3_getirq
+ *
+ * Description:
+ * This function returns the IRQ associated with a CPU interrupt
+ *
+ * Input Parameters:
+ * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
+ * cpuint - The CPU interrupt associated to the IRQ
+ *
+ * Returned Value:
+ * The IRQ associated with such CPU interrupt or CPUINT_UNASSIGNED if
+ * IRQ is not yet assigned to a CPU interrupt.
+ *
+ ****************************************************************************/
+
+int esp32s3_getirq(int cpu, int cpuint);
+
#undef EXTERN
#if defined(__cplusplus)
}
[nuttx] 11/12: esp32-devkitc: Enable softAP on `blewifi` defconfig to ease testing
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 6f235c5f0a9faeefb148752564edbcf882a2218e
Author: Tiago Medicci Serrano <ti...@espressif.com>
AuthorDate: Thu Aug 10 13:49:37 2023 -0300
esp32-devkitc: Enable softAP on `blewifi` defconfig to ease testing
In order to properly test the W-Fi/BT coexistence mode, set the
Wi-Fi mode to station + softAP.
---
boards/xtensa/esp32/esp32-devkitc/configs/blewifi/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/blewifi/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/blewifi/defconfig
index b73e735a58..adc0d40343 100644
--- a/boards/xtensa/esp32/esp32-devkitc/configs/blewifi/defconfig
+++ b/boards/xtensa/esp32/esp32-devkitc/configs/blewifi/defconfig
@@ -85,6 +85,7 @@ CONFIG_ESP32_STORAGE_MTD_SIZE=0x80000
CONFIG_ESP32_UART0=y
CONFIG_ESP32_WIFI=y
CONFIG_ESP32_WIFI_BT_COEXIST=y
+CONFIG_ESP32_WIFI_STATION_SOFTAP=y
CONFIG_EXAMPLE_POWER_SAVE_MIN_MODEM=y
CONFIG_FILE_STREAM=y
CONFIG_FS_PROCFS=y
[nuttx] 12/12: esp32s3: Use `PANIC()` instead of `assert(0)`
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 281ab833097c0472063728e13732c3b44fef4eb9
Author: Tiago Medicci Serrano <ti...@espressif.com>
AuthorDate: Mon Aug 14 10:17:40 2023 -0300
esp32s3: Use `PANIC()` instead of `assert(0)`
Considering kernel code, it's reasonable to use `PANIC()` instead
of `assert(0)` to handle with situations that require abort. Unlike
`assert`, `PANIC()` doesn't dependent on `NDEBUG`.
---
arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c | 2 +-
arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c
index 1e5c0c2cda..520dc9e938 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c
@@ -2317,7 +2317,7 @@ int esp32s3_bt_controller_init(void)
else
{
wlerr("Internal 150kHz RC oscillator not detected.");
- assert(0);
+ PANIC();
}
#endif
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
index 4168a7cf77..b794f6b203 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
@@ -802,7 +802,7 @@ static void esp_set_isr(int32_t n, void *f, void *arg)
if (!adapter)
{
wlerr("Failed to alloc %d memory\n", tmp);
- assert(0);
+ PANIC();
return;
}
@@ -813,7 +813,7 @@ static void esp_set_isr(int32_t n, void *f, void *arg)
if (ret)
{
wlerr("Failed to attach IRQ %d\n", irq);
- assert(0);
+ PANIC();
return;
}
@@ -821,7 +821,7 @@ static void esp_set_isr(int32_t n, void *f, void *arg)
if (ret)
{
wlerr("Failed to attach IRQ %d\n", irq);
- assert(0);
+ PANIC();
return;
}
}
[nuttx] 08/12: arch/xtensa/esp32s3: initial effort to get BLE running on ESP32-S3
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 655d00b1e714bac76ab71d3b93cf4d70d360df6b
Author: Petro Karashchenko <pe...@gmail.com>
AuthorDate: Fri Jun 9 18:59:55 2023 +0300
arch/xtensa/esp32s3: initial effort to get BLE running on ESP32-S3
Signed-off-by: Petro Karashchenko <pe...@gmail.com>
---
arch/xtensa/include/esp32s3/irq.h | 7 +-
arch/xtensa/src/esp32s3/Kconfig | 30 +
arch/xtensa/src/esp32s3/Make.defs | 3 +-
arch/xtensa/src/esp32s3/Wireless.mk | 14 +-
arch/xtensa/src/esp32s3/esp32s3_ble.c | 325 +++
arch/xtensa/src/esp32s3/esp32s3_ble.h | 50 +
arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c | 2686 ++++++++++++++++++++
.../{esp32s3_wireless.h => esp32s3_ble_adapter.h} | 117 +-
arch/xtensa/src/esp32s3/esp32s3_irq.c | 23 +-
arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c | 156 +-
arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h | 19 +
arch/xtensa/src/esp32s3/esp32s3_wireless.c | 260 +-
arch/xtensa/src/esp32s3/esp32s3_wireless.h | 105 +-
.../esp32s3/common/scripts/esp32s3_aliases.ld | 29 +
.../xtensa/esp32s3/common/scripts/esp32s3_rom.ld | 213 +-
.../esp32s3/common/scripts/esp32s3_rom_aliases.ld | 37 +
.../esp32s3/common/scripts/esp32s3_rom_api.ld | 79 +
.../xtensa/esp32s3/common/scripts/flat_memory.ld | 2 +
.../esp32s3/common/scripts/protected_memory.ld | 2 +
.../esp32s3/esp32s3-devkit/configs/ble/defconfig | 71 +
.../esp32s3/esp32s3-devkit/scripts/Make.defs | 2 +
.../esp32s3/esp32s3-devkit/src/esp32s3_bringup.c | 24 +
.../xtensa/esp32s3/esp32s3-eye/scripts/Make.defs | 2 +
.../esp32s3/esp32s3-meadow/scripts/Make.defs | 2 +
24 files changed, 3940 insertions(+), 318 deletions(-)
diff --git a/arch/xtensa/include/esp32s3/irq.h b/arch/xtensa/include/esp32s3/irq.h
index 591384a0fa..45d2e0f4ad 100644
--- a/arch/xtensa/include/esp32s3/irq.h
+++ b/arch/xtensa/include/esp32s3/irq.h
@@ -208,8 +208,8 @@
#define ESP32S3_IRQ_PWR (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PWR)
#define ESP32S3_IRQ_BB (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BB)
#define ESP32S3_IRQ_BT_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BT_MAC)
-#define ESP32S3_IRQ_BT_BB (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BB)
-#define ESP32S3_IRQ_BT_BB_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BB_NMI)
+#define ESP32S3_IRQ_BT_BB (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BT_BB)
+#define ESP32S3_IRQ_BT_BB_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BT_BB_NMI)
#define ESP32S3_IRQ_RWBT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RWBT)
#define ESP32S3_IRQ_RWBLE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RWBLE)
#define ESP32S3_IRQ_RWBT_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RWBT_NMI)
@@ -446,9 +446,10 @@
#define ESP32S3_CPUINT_NMISET 0x00004000
#define ESP32S3_CPUINT_MAC 0
-#define ESP32S3_CPUINT_MAC_NMI 1
+#define ESP32S3_CPUINT_RWBLE 5
#define ESP32S3_CPUINT_TIMER0 6
#define ESP32S3_CPUINT_SOFTWARE0 7
+#define ESP32S3_CPUINT_BT_BB 8
#define ESP32S3_CPUINT_PROFILING 11
#define ESP32S3_CPUINT_TIMER1 15
#define ESP32S3_CPUINT_TIMER2 16
diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig
index c7d5beba49..389bb7d80e 100644
--- a/arch/xtensa/src/esp32s3/Kconfig
+++ b/arch/xtensa/src/esp32s3/Kconfig
@@ -363,6 +363,13 @@ config ESP32S3_WIFI
---help---
Enable Wi-Fi support
+config ESP32S3_BLE
+ bool "BLE"
+ default n
+ select ESP32S3_WIRELESS
+ ---help---
+ Enable BLE support
+
config ESP32S3_I2C0
bool "I2C 0"
default n
@@ -463,6 +470,11 @@ config ESP32S3_WCL
endmenu # ESP32-S3 Peripheral Selection
+menuconfig ESP32S3_WIFI_BT_COEXIST
+ bool "Wi-Fi and BT coexist"
+ default n
+ depends on ESP32S3_WIFI && ESP32S3_BLE
+
menu "SPI RAM Configuration"
depends on ESP32S3_SPIRAM
@@ -951,6 +963,24 @@ config EXAMPLE_WIFI_LISTEN_INTERVAL
endmenu # ESP32S3_WIFI
+menu "BLE Configuration"
+ depends on ESP32S3_BLE
+
+config ESP32S3_BLE_TTY_NAME
+ string "BLE TTY device name"
+ default "/dev/ttyHCI0"
+ depends on UART_BTH4
+
+config ESP32S3_BLE_TASK_STACK_SIZE
+ int "Controller task stack size"
+ default 4096
+
+config ESP32S3_BLE_TASK_PRIORITY
+ int "Controller task priority"
+ default 253
+
+endmenu # BLE Configuration
+
menu "Timer/Counter Configuration"
depends on ESP32S3_TIMER
diff --git a/arch/xtensa/src/esp32s3/Make.defs b/arch/xtensa/src/esp32s3/Make.defs
index 9618616b6a..c7e4c47cf6 100644
--- a/arch/xtensa/src/esp32s3/Make.defs
+++ b/arch/xtensa/src/esp32s3/Make.defs
@@ -149,9 +149,8 @@ ifeq ($(CONFIG_ESP32S3_WIRELESS),y)
include chip/Wireless.mk
endif
-ifeq ($(CONFIG_ESP32S3_RTC),y)
CHIP_CSRCS += esp32s3_rtc.c
+
ifeq ($(CONFIG_RTC_DRIVER),y)
CHIP_CSRCS += esp32s3_rtc_lowerhalf.c
endif
-endif
diff --git a/arch/xtensa/src/esp32s3/Wireless.mk b/arch/xtensa/src/esp32s3/Wireless.mk
index e9b3086f92..a9d7749618 100644
--- a/arch/xtensa/src/esp32s3/Wireless.mk
+++ b/arch/xtensa/src/esp32s3/Wireless.mk
@@ -21,7 +21,7 @@
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ESP_HAL_3RDPARTY_PATH = $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)
ifndef ESP_HAL_3RDPARTY_VERSION
- ESP_HAL_3RDPARTY_VERSION = 2c8e45665ea37dfe3c7b6206cc2b53701eb7dcde
+ ESP_HAL_3RDPARTY_VERSION = 8758b1e760f17af5867405a6711aad3e4722b317
endif
ifndef ESP_HAL_3RDPARTY_URL
@@ -40,7 +40,7 @@ CFLAGS += -Wno-undef -Wno-unused-variable
context:: chip/$(ESP_HAL_3RDPARTY_REPO)
$(Q) echo "Espressif HAL for 3rd Party Platforms: initializing submodules..."
- $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init --depth=1 components/mbedtls/mbedtls components/esp_phy/lib components/esp_wifi/lib
+ $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init --depth=1 components/mbedtls/mbedtls components/esp_phy/lib components/esp_wifi/lib components/bt/controller/lib_esp32c3_family components/esp_coex/lib
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls reset --quiet --hard
$(Q) echo "Applying patches..."
$(Q) cd chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls && git apply ../../../nuttx/patches/components/mbedtls/mbedtls/*.patch
@@ -49,6 +49,7 @@ distclean::
$(call DELDIR, chip/$(ESP_HAL_3RDPARTY_REPO))
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include
+INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)include$(DELIM)esp32c3$(DELIM)include
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_event$(DELIM)include
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)esp32s3$(DELIM)include
@@ -65,13 +66,20 @@ INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)lib$(DELIM)esp32s3
EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)lib$(DELIM)esp32s3
+EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)controller$(DELIM)lib_esp32c3_family$(DELIM)esp32s3
+EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)lib$(DELIM)esp32s3
-EXTRA_LIBS += -lphy
+EXTRA_LIBS += -lphy -lcoexist
# Wireless interfaces.
CHIP_CSRCS += esp32s3_wireless.c
+ifeq ($(CONFIG_ESP32S3_BLE),y)
+CHIP_CSRCS += esp32s3_ble_adapter.c esp32s3_ble.c
+EXTRA_LIBS += -lbtbb -lbtdm_app
+endif
+
ifeq ($(CONFIG_ESP32S3_WIFI),y)
CHIP_CSRCS += esp32s3_wlan.c esp32s3_wifi_utils.c esp32s3_wifi_adapter.c
EXTRA_LIBS += -lcore -lnet80211 -lpp
diff --git a/arch/xtensa/src/esp32s3/esp32s3_ble.c b/arch/xtensa/src/esp32s3/esp32s3_ble.c
new file mode 100644
index 0000000000..a3e7cd964b
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_ble.c
@@ -0,0 +1,325 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_ble.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <sys/types.h>
+
+#include <sys/socket.h>
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/nuttx.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/wqueue.h>
+#include <nuttx/net/bluetooth.h>
+#include <nuttx/wireless/bluetooth/bt_driver.h>
+#include <nuttx/wireless/bluetooth/bt_uart.h>
+
+#if defined(CONFIG_UART_BTH4)
+# include <nuttx/serial/uart_bth4.h>
+#endif
+
+#include "esp32s3_ble_adapter.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* BLE packet buffer max size */
+
+#define BLE_BUF_SIZE 1024
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct esp32s3_ble_priv_s
+{
+ struct bt_driver_s drv; /* NuttX BT/BLE driver data */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int esp32s3_ble_open(struct bt_driver_s *drv);
+static int esp32s3_ble_send(struct bt_driver_s *drv,
+ enum bt_buf_type_e type,
+ void *data, size_t len);
+static void esp32s3_ble_close(struct bt_driver_s *drv);
+
+static void esp32s3_ble_send_ready(void);
+static int esp32s3_ble_recv_cb(uint8_t *data, uint16_t len);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static struct esp32s3_ble_priv_s g_ble_priv =
+{
+ .drv =
+ {
+ .head_reserve = H4_HEADER_SIZE,
+ .open = esp32s3_ble_open,
+ .send = esp32s3_ble_send,
+ .close = esp32s3_ble_close
+ }
+};
+
+static esp_vhci_host_callback_t vhci_host_cb =
+{
+ .notify_host_send_available = esp32s3_ble_send_ready,
+ .notify_host_recv = esp32s3_ble_recv_cb
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_ble_send_ready
+ *
+ * Description:
+ * If the controller could send HCI comand will callback this function.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void esp32s3_ble_send_ready(void)
+{
+}
+
+/****************************************************************************
+ * Name: esp32s3_ble_recv_cb
+ *
+ * Description:
+ * BLE receive callback function when BLE hardware receive packet
+ *
+ * Input Parameters:
+ * data - BLE packet data pointer
+ * len - BLE packet length
+ *
+ * Returned Value:
+ * 0 on success or a negated value on failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_ble_recv_cb(uint8_t *data, uint16_t len)
+{
+ int ret;
+ bool valid = true;
+ enum bt_buf_type_e type;
+ struct esp32s3_ble_priv_s *priv = &g_ble_priv;
+
+ switch (data[0])
+ {
+ case H4_EVT:
+ type = BT_EVT;
+ break;
+ case H4_ACL:
+ type = BT_ACL_IN;
+ break;
+ case H4_ISO:
+ type = BT_ISO_IN;
+ break;
+ default:
+ valid = false;
+ break;
+ }
+
+ if (!valid)
+ {
+ ret = ERROR;
+ }
+ else
+ {
+ /* send packet to host */
+
+ ret = bt_netdev_receive(&priv->drv, type,
+ &data[H4_HEADER_SIZE],
+ len - H4_HEADER_SIZE);
+ if (ret < 0)
+ {
+ wlerr("Failed to receive ret=%d\n", ret);
+ }
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_ble_send
+ *
+ * Description:
+ * ESP32-S3 BLE send callback function for BT driver.
+ *
+ * Input Parameters:
+ * drv - BT driver pointer
+ * type - BT packet type
+ * data - BT packet data buffer pointer
+ * len - BT packet length
+ *
+ * Returned Value:
+ * Sent bytes on success or a negated value on failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_ble_send(struct bt_driver_s *drv,
+ enum bt_buf_type_e type,
+ void *data, size_t len)
+{
+ uint8_t *hdr = (uint8_t *)data - drv->head_reserve;
+
+ if ((len + H4_HEADER_SIZE) > BLE_BUF_SIZE)
+ {
+ return -EINVAL;
+ }
+
+ if (type == BT_CMD)
+ {
+ *hdr = H4_CMD;
+ }
+ else if (type == BT_ACL_OUT)
+ {
+ *hdr = H4_ACL;
+ }
+ else if (type == BT_ISO_OUT)
+ {
+ *hdr = H4_ISO;
+ }
+ else
+ {
+ return -EINVAL;
+ }
+
+ if (esp32s3_vhci_host_check_send_available())
+ {
+ esp32s3_vhci_host_send_packet(hdr, len + drv->head_reserve);
+ }
+
+ return len;
+}
+
+/****************************************************************************
+ * Name: esp32s3_ble_close
+ *
+ * Description:
+ * ESP32-C3 BLE close callback function for BT driver.
+ *
+ * Input Parameters:
+ * drv - BT driver pointer
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void esp32s3_ble_close(struct bt_driver_s *drv)
+{
+}
+
+/****************************************************************************
+ * Name: esp32s3_ble_open
+ *
+ * Description:
+ * ESP32-C3 BLE open callback function for BT driver.
+ *
+ * Input Parameters:
+ * drv - BT driver pointer
+ *
+ * Returned Value:
+ * OK
+ *
+ ****************************************************************************/
+
+static int esp32s3_ble_open(struct bt_driver_s *drv)
+{
+ return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_ble_initialize
+ *
+ * Description:
+ * Init BT controller
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * OK on success or a negated value on failure.
+ *
+ ****************************************************************************/
+
+int esp32s3_ble_initialize(void)
+{
+ int ret;
+
+ ret = esp32s3_bt_controller_init();
+ if (ret)
+ {
+ wlerr("Failed to initialize BLE ret=%d\n", ret);
+ return ERROR;
+ }
+
+ ret = esp32s3_bt_controller_enable(ESP_BT_MODE_BLE);
+ if (ret)
+ {
+ wlerr("Failed to Enable BLE ret=%d\n", ret);
+ return ERROR;
+ }
+
+ ret = esp32s3_vhci_register_callback(&vhci_host_cb);
+ if (ret)
+ {
+ wlerr("Failed to register BLE callback ret=%d\n", ret);
+ return ERROR;
+ }
+
+#if defined(CONFIG_UART_BTH4)
+ ret = uart_bth4_register(CONFIG_ESP32S3_BLE_TTY_NAME, &g_ble_priv.drv);
+#else
+ ret = bt_netdev_register(&g_ble_priv.drv);
+#endif
+ if (ret < 0)
+ {
+ wlerr("bt_netdev_register or uart_bth4_register error: %d\n", ret);
+ return ret;
+ }
+
+ return OK;
+}
diff --git a/arch/xtensa/src/esp32s3/esp32s3_ble.h b/arch/xtensa/src/esp32s3/esp32s3_ble.h
new file mode 100644
index 0000000000..b68fc61d0f
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_ble.h
@@ -0,0 +1,50 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_ble.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_BLE_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_BLE_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_ble_initialize
+ *
+ * Description:
+ * Init BT controller
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * success or fail
+ *
+ ****************************************************************************/
+
+int esp32s3_ble_initialize(void);
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_BLE_H */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c
new file mode 100644
index 0000000000..5eb7d873f5
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c
@@ -0,0 +1,2686 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stddef.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <assert.h>
+#include <debug.h>
+#include <pthread.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <clock/clock.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <nuttx/kmalloc.h>
+#include <nuttx/mqueue.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/irq.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/kthread.h>
+#include <nuttx/wdog.h>
+#include <nuttx/wqueue.h>
+#include <nuttx/sched.h>
+#include <nuttx/signal.h>
+
+#include "hardware/esp32s3_rtccntl.h"
+#include "hardware/esp32s3_syscon.h"
+#include "hardware/wdev_reg.h"
+#include "rom/esp32s3_spiflash.h"
+#include "xtensa.h"
+#include "xtensa_attr.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_periph.h"
+#include "esp32s3_rt_timer.h"
+#include "esp32s3_rtc.h"
+#include "esp32s3_spiflash.h"
+#include "esp32s3_wireless.h"
+#include "esp32s3_wireless.h"
+
+#include "esp32s3_ble_adapter.h"
+
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+# include "esp_coexist_internal.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define OSI_FUNCS_TIME_BLOCKING 0xffffffff
+#define OSI_VERSION 0x00010006
+#define OSI_MAGIC_VALUE 0xfadebead
+
+#define BTDM_MIN_TIMER_UNCERTAINTY_US (1800)
+
+/* Sleep and wakeup interval control */
+
+#define BTDM_MIN_SLEEP_DURATION (24) /* Threshold of interval in half slots to allow to fall into sleep mode */
+#define BTDM_MODEM_WAKE_UP_DELAY (8) /* delay in half slots of modem wake up procedure, including re-enable PHY/RF */
+
+/* Low Power Clock Selection */
+
+#define BTDM_LPCLK_SEL_XTAL (0)
+#define BTDM_LPCLK_SEL_XTAL32K (1)
+#define BTDM_LPCLK_SEL_RTC_SLOW (2)
+#define BTDM_LPCLK_SEL_8M (3)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* BLE message queue private data */
+
+struct mq_adpt_s
+{
+ struct file mq; /* Message queue handle */
+ uint32_t msgsize; /* Message size */
+ char name[16]; /* Message queue name */
+};
+
+/* BLE interrupt adapter private data */
+
+struct irq_adpt_s
+{
+ void (*func)(void *arg); /* Interrupt callback function */
+ void *arg; /* Interrupt private data */
+};
+
+typedef enum btdm_vnd_ol_sig_e
+{
+ BTDM_VND_OL_SIG_WAKEUP_TMR,
+ BTDM_VND_OL_SIG_NUM,
+} btdm_vnd_ol_sig_t;
+
+/* low power control struct */
+
+typedef union
+{
+ struct
+ {
+ uint32_t enable : 1; /* whether low power mode is required */
+ uint32_t lpclk_sel : 2; /* low power clock source */
+ uint32_t mac_bb_pd : 1; /* whether hardware(MAC, BB) force-power-down is required during sleep */
+ uint32_t wakeup_timer_required : 1; /* whether system timer is needed */
+ uint32_t no_light_sleep : 1; /* do not allow system to enter light sleep after bluetooth is enabled */
+ uint32_t main_xtal_pu : 1; /* power up main XTAL */
+ uint32_t reserved : 25; /* reserved */
+ };
+ uint32_t val;
+} btdm_lpcntl_t;
+
+/* low power control status */
+
+typedef union
+{
+ struct
+ {
+ uint32_t pm_lock_released : 1; /* whether power management lock is released */
+ uint32_t mac_bb_pd : 1; /* whether hardware(MAC, BB) is powered down */
+ uint32_t phy_enabled : 1; /* whether phy is switched on */
+ uint32_t wakeup_timer_started : 1; /* whether wakeup timer is started */
+ uint32_t reserved : 28; /* reserved */
+ };
+ uint32_t val;
+} btdm_lpstat_t;
+
+/* wakeup request sources */
+
+enum btdm_wakeup_src_e
+{
+ BTDM_ASYNC_WAKEUP_SRC_VHCI,
+ BTDM_ASYNC_WAKEUP_SRC_DISA,
+ BTDM_ASYNC_WAKEUP_SRC_TMR,
+ BTDM_ASYNC_WAKEUP_SRC_MAX,
+};
+
+/* prototype of function to handle vendor dependent signals */
+
+typedef void (*btdm_vnd_ol_task_func_t)(void *param);
+
+/* VHCI function interface */
+
+typedef struct vhci_host_callback_s
+{
+ void (*notify_host_send_available)(void); /* callback used to notify that the host can send packet to controller */
+ int (*notify_host_recv)(uint8_t *data, uint16_t len); /* callback used to notify that the controller has a packet to send to the host */
+} vhci_host_callback_t;
+
+typedef void (*osi_intr_handler)(void);
+
+/* BLE OS function */
+
+struct osi_funcs_s
+{
+ uint32_t _magic;
+ uint32_t _version;
+ void (*_interrupt_set)(int cpu_no, int intr_source,
+ int interrupt_no, int interrpt_prio);
+ void (*_interrupt_clear)(int interrupt_source, int interrupt_no);
+ void (*_interrupt_handler_set)(int interrupt_no, void * fn, void *arg);
+ void (*_interrupt_disable)(void);
+ void (*_interrupt_restore)(void);
+ void (*_task_yield)(void);
+ void (*_task_yield_from_isr)(void);
+ void *(*_semphr_create)(uint32_t max, uint32_t init);
+ void (*_semphr_delete)(void *semphr);
+ int (*_semphr_take_from_isr)(void *semphr, void *hptw);
+ int (*_semphr_give_from_isr)(void *semphr, void *hptw);
+ int (*_semphr_take)(void *semphr, uint32_t block_time_ms);
+ int (*_semphr_give)(void *semphr);
+ void *(*_mutex_create)(void);
+ void (*_mutex_delete)(void *mutex);
+ int (*_mutex_lock)(void *mutex);
+ int (*_mutex_unlock)(void *mutex);
+ void *(* _queue_create)(uint32_t queue_len, uint32_t item_size);
+ void (* _queue_delete)(void *queue);
+ int (* _queue_send)(void *queue, void *item, uint32_t block_time_ms);
+ int (* _queue_send_from_isr)(void *queue, void *item, void *hptw);
+ int (* _queue_recv)(void *queue, void *item, uint32_t block_time_ms);
+ int (* _queue_recv_from_isr)(void *queue, void *item, void *hptw);
+ int (* _task_create)(void *task_func, const char *name,
+ uint32_t stack_depth, void *param, uint32_t prio,
+ void *task_handle, uint32_t core_id);
+ void (* _task_delete)(void *task_handle);
+ bool (* _is_in_isr)(void);
+ int (* _cause_sw_intr_to_core)(int core_id, int intr_no);
+ void *(* _malloc)(size_t size);
+ void *(* _malloc_internal)(size_t size);
+ void (* _free)(void *p);
+ int (* _read_efuse_mac)(uint8_t mac[6]);
+ void (* _srand)(unsigned int seed);
+ int (* _rand)(void);
+ uint32_t (* _btdm_lpcycles_2_hus)(uint32_t cycles, uint32_t *error_corr);
+ uint32_t (* _btdm_hus_2_lpcycles)(uint32_t us);
+ bool (* _btdm_sleep_check_duration)(int32_t *slot_cnt);
+ void (* _btdm_sleep_enter_phase1)(uint32_t lpcycles); /* called when interrupt is disabled */
+ void (* _btdm_sleep_enter_phase2)(void);
+ void (* _btdm_sleep_exit_phase1)(void); /* called from ISR */
+ void (* _btdm_sleep_exit_phase2)(void); /* called from ISR */
+ void (* _btdm_sleep_exit_phase3)(void); /* called from task */
+ void (* _coex_wifi_sleep_set)(bool sleep);
+ int (* _coex_core_ble_conn_dyn_prio_get)(bool *low, bool *high);
+ void (* _coex_schm_status_bit_set)(uint32_t type, uint32_t status);
+ void (* _coex_schm_status_bit_clear)(uint32_t type, uint32_t status);
+ void (* _interrupt_on)(int intr_num);
+ void (* _interrupt_off)(int intr_num);
+ void (* _esp_hw_power_down)(void);
+ void (* _esp_hw_power_up)(void);
+ void (* _ets_backup_dma_copy)(uint32_t reg,
+ uint32_t mem_addr, uint32_t num,
+ bool to_rem);
+};
+
+/****************************************************************************
+ * Private Function
+ ****************************************************************************/
+
+static void interrupt_set_wrapper(int cpu_no, int intr_source,
+ int intr_num, int intr_prio);
+static void interrupt_clear_wrapper(int intr_source, int intr_num);
+static void interrupt_handler_set_wrapper(int intr_num, void *fn, void *arg);
+static void IRAM_ATTR interrupt_disable(void);
+static void IRAM_ATTR interrupt_restore(void);
+static void IRAM_ATTR task_yield_from_isr(void);
+static void *semphr_create_wrapper(uint32_t max, uint32_t init);
+static void semphr_delete_wrapper(void *semphr);
+static int IRAM_ATTR semphr_take_from_isr_wrapper(void *semphr, void *hptw);
+static int IRAM_ATTR semphr_give_from_isr_wrapper(void *semphr, void *hptw);
+static int semphr_take_wrapper(void *semphr, uint32_t block_time_ms);
+static int semphr_give_wrapper(void *semphr);
+static void *mutex_create_wrapper(void);
+static void mutex_delete_wrapper(void *mutex);
+static int mutex_lock_wrapper(void *mutex);
+static int mutex_unlock_wrapper(void *mutex);
+static int IRAM_ATTR queue_send_from_isr_wrapper(void *queue, void *item,
+ void *hptw);
+static int IRAM_ATTR queue_recv_from_isr_wrapper(void *queue, void *item,
+ void *hptw);
+static int task_create_wrapper(void *task_func, const char *name,
+ uint32_t stack_depth, void *param,
+ uint32_t prio, void *task_handle,
+ uint32_t core_id);
+static void task_delete_wrapper(void *task_handle);
+static bool IRAM_ATTR is_in_isr_wrapper(void);
+static void *malloc_wrapper(size_t size);
+static void *malloc_internal_wrapper(size_t size);
+static int IRAM_ATTR read_mac_wrapper(uint8_t mac[6]);
+static void IRAM_ATTR srand_wrapper(unsigned int seed);
+static int IRAM_ATTR rand_wrapper(void);
+static uint32_t IRAM_ATTR btdm_lpcycles_2_hus(uint32_t cycles,
+ uint32_t *error_corr);
+static uint32_t IRAM_ATTR btdm_hus_2_lpcycles(uint32_t us);
+static void coex_wifi_sleep_set_hook(bool sleep);
+static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status);
+static void coex_schm_status_bit_clear_wrapper(uint32_t type,
+ uint32_t status);
+static void interrupt_on_wrapper(int intr_num);
+static void interrupt_off_wrapper(int intr_num);
+static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size);
+static int queue_send_wrapper(void *queue, void *item,
+ uint32_t block_time_ms);
+static int queue_recv_wrapper(void *queue, void *item,
+ uint32_t block_time_ms);
+static void queue_delete_wrapper(void *queue);
+
+static bool IRAM_ATTR btdm_sleep_check_duration(int32_t *half_slot_cnt);
+static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles);
+static void btdm_sleep_enter_phase2_wrapper(void);
+static void btdm_sleep_exit_phase3_wrapper(void);
+
+void IRAM_ATTR esp_wifi_bt_power_domain_on(void);
+void IRAM_ATTR btdm_hw_mac_power_down_wrapper(void);
+void IRAM_ATTR btdm_hw_mac_power_up_wrapper(void);
+void IRAM_ATTR btdm_backup_dma_copy_wrapper(uint32_t reg, uint32_t mem_addr,
+ uint32_t num, bool to_mem);
+
+static void esp32s3_bt_controller_deinit_internal(void);
+
+/****************************************************************************
+ * Extern Functions declaration and value
+ ****************************************************************************/
+
+extern int btdm_osi_funcs_register(void *osi_funcs);
+
+/* Initialise and De-initialise */
+
+extern int btdm_controller_init(esp_bt_controller_config_t *config_opts);
+extern void btdm_controller_deinit(void);
+extern int btdm_controller_enable(esp_bt_mode_t mode);
+extern void btdm_controller_disable(void);
+extern uint8_t btdm_controller_get_mode(void);
+extern const char *btdm_controller_get_compile_version(void);
+extern void btdm_rf_bb_init_phase2(void); /* shall be called after PHY/RF is enabled */
+
+/* Sleep */
+
+extern void btdm_controller_enable_sleep(bool enable);
+extern uint8_t btdm_controller_get_sleep_mode(void);
+extern bool btdm_power_state_active(void);
+extern void btdm_wakeup_request(void);
+extern void btdm_in_wakeup_requesting_set(bool in_wakeup_requesting);
+
+/* vendor dependent tasks to be posted and handled by controller task */
+
+extern int btdm_vnd_offload_task_register(btdm_vnd_ol_sig_t sig,
+ btdm_vnd_ol_task_func_t func);
+extern int btdm_vnd_offload_task_deregister(btdm_vnd_ol_sig_t sig);
+extern int r_btdm_vnd_offload_post_from_isr(btdm_vnd_ol_sig_t sig,
+ void *param, bool need_yield);
+extern int r_btdm_vnd_offload_post(btdm_vnd_ol_sig_t sig, void *param);
+
+/* Low Power Clock */
+
+extern bool btdm_lpclk_select_src(uint32_t sel);
+extern bool btdm_lpclk_set_div(uint32_t div);
+extern int btdm_hci_tl_io_event_post(int event);
+
+/* VHCI */
+
+extern bool api_vhci_host_check_send_available(void); /* Functions in bt lib */
+extern void api_vhci_host_send_packet(uint8_t * data, uint16_t len);
+extern int api_vhci_host_register_callback(const vhci_host_callback_t
+ *callback);
+
+/* TX power */
+
+extern int ble_txpwr_set(int power_type, int power_level);
+extern int ble_txpwr_get(int power_type);
+
+extern uint16_t l2c_ble_link_get_tx_buf_num(void);
+extern int coex_core_ble_conn_dyn_prio_get(bool *low, bool *high);
+extern void coex_pti_v2(void);
+
+extern bool btdm_deep_sleep_mem_init(void);
+extern void btdm_deep_sleep_mem_deinit(void);
+extern void btdm_ble_power_down_dma_copy(bool copy);
+extern uint8_t btdm_sleep_clock_sync(void);
+
+#if CONFIG_MAC_BB_PD
+extern void esp_mac_bb_power_down(void);
+extern void esp_mac_bb_power_up(void);
+extern void ets_backup_dma_copy(uint32_t reg, uint32_t mem_addr,
+ uint32_t num, bool to_mem);
+#endif
+
+extern uint8_t _bt_bss_start[];
+extern uint8_t _bt_bss_end[];
+extern uint8_t _btdm_bss_start[];
+extern uint8_t _btdm_bss_end[];
+extern uint8_t _bt_data_start[];
+extern uint8_t _bt_data_end[];
+extern uint8_t _btdm_data_start[];
+extern uint8_t _btdm_data_end[];
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static DRAM_ATTR struct osi_funcs_s *osi_funcs_p;
+
+/* Controller status */
+
+static DRAM_ATTR esp_bt_controller_status_t btdm_controller_status =
+ ESP_BT_CONTROLLER_STATUS_IDLE;
+
+/* low power control struct */
+
+static DRAM_ATTR btdm_lpcntl_t g_lp_cntl;
+
+/* low power status struct */
+
+static DRAM_ATTR btdm_lpstat_t g_lp_stat;
+
+/* measured average low power clock period in micro seconds */
+
+static DRAM_ATTR uint32_t g_btdm_lpcycle_us = 0;
+
+/* number of fractional bit for g_btdm_lpcycle_us */
+
+static DRAM_ATTR uint8_t g_btdm_lpcycle_us_frac = 0;
+
+/* semaphore used for blocking VHCI API to wait for controller to wake up */
+
+static DRAM_ATTR void * g_wakeup_req_sem = NULL;
+
+/* wakeup timer */
+
+static DRAM_ATTR esp_timer_handle_t g_btdm_slp_tmr;
+
+#ifdef CONFIG_PM
+static DRAM_ATTR void * g_pm_lock;
+
+/* pm_lock to prevent light sleep due to incompatibility currently */
+
+static DRAM_ATTR void * g_light_sleep_pm_lock;
+#endif
+
+/* BT interrupt private data */
+
+static irqstate_t g_inter_flags;
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* BLE OS adapter data */
+
+static struct osi_funcs_s g_osi_funcs =
+{
+ ._magic = OSI_MAGIC_VALUE,
+ ._version = OSI_VERSION,
+ ._interrupt_set = interrupt_set_wrapper,
+ ._interrupt_clear = interrupt_clear_wrapper,
+ ._interrupt_handler_set = interrupt_handler_set_wrapper,
+ ._interrupt_disable = interrupt_disable,
+ ._interrupt_restore = interrupt_restore,
+ ._task_yield = task_yield_from_isr,
+ ._task_yield_from_isr = task_yield_from_isr,
+ ._semphr_create = semphr_create_wrapper,
+ ._semphr_delete = semphr_delete_wrapper,
+ ._semphr_take_from_isr = semphr_take_from_isr_wrapper,
+ ._semphr_give_from_isr = semphr_give_from_isr_wrapper,
+ ._semphr_take = semphr_take_wrapper,
+ ._semphr_give = semphr_give_wrapper,
+ ._mutex_create = mutex_create_wrapper,
+ ._mutex_delete = mutex_delete_wrapper,
+ ._mutex_lock = mutex_lock_wrapper,
+ ._mutex_unlock = mutex_unlock_wrapper,
+ ._queue_create = queue_create_wrapper,
+ ._queue_delete = queue_delete_wrapper,
+ ._queue_send = queue_send_wrapper,
+ ._queue_send_from_isr = queue_send_from_isr_wrapper,
+ ._queue_recv = queue_recv_wrapper,
+ ._queue_recv_from_isr = queue_recv_from_isr_wrapper,
+ ._task_create = task_create_wrapper,
+ ._task_delete = task_delete_wrapper,
+ ._is_in_isr = is_in_isr_wrapper,
+ ._cause_sw_intr_to_core = NULL,
+ ._malloc = malloc_wrapper,
+ ._malloc_internal = malloc_internal_wrapper,
+ ._free = free,
+ ._read_efuse_mac = read_mac_wrapper,
+ ._srand = srand_wrapper,
+ ._rand = rand_wrapper,
+ ._btdm_lpcycles_2_hus = btdm_lpcycles_2_hus,
+ ._btdm_hus_2_lpcycles = btdm_hus_2_lpcycles,
+ ._btdm_sleep_check_duration = btdm_sleep_check_duration,
+ ._btdm_sleep_enter_phase1 = btdm_sleep_enter_phase1_wrapper,
+ ._btdm_sleep_enter_phase2 = btdm_sleep_enter_phase2_wrapper,
+ ._btdm_sleep_exit_phase1 = NULL,
+ ._btdm_sleep_exit_phase2 = NULL,
+ ._btdm_sleep_exit_phase3 = btdm_sleep_exit_phase3_wrapper,
+ ._coex_wifi_sleep_set = coex_wifi_sleep_set_hook,
+ ._coex_core_ble_conn_dyn_prio_get = NULL,
+ ._coex_schm_status_bit_set = coex_schm_status_bit_set_wrapper,
+ ._coex_schm_status_bit_clear = coex_schm_status_bit_clear_wrapper,
+ ._interrupt_on = interrupt_on_wrapper,
+ ._interrupt_off = interrupt_off_wrapper,
+ ._esp_hw_power_down = btdm_hw_mac_power_down_wrapper,
+ ._esp_hw_power_up = btdm_hw_mac_power_up_wrapper,
+ ._ets_backup_dma_copy = btdm_backup_dma_copy_wrapper,
+};
+
+/****************************************************************************
+ * Private Functions and Public Functions only used by libraries
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: btdm_hw_mac_power_down_wrapper
+ *
+ * Description:
+ * Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * none
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR btdm_hw_mac_power_down_wrapper(void)
+{
+}
+
+/****************************************************************************
+ * Name: btdm_hw_mac_power_up_wrapper
+
+ *
+ * Description:
+ * Power up MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * none
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR btdm_hw_mac_power_up_wrapper(void)
+{
+}
+
+/****************************************************************************
+ * Name: btdm_backup_dma_copy_wrapper
+
+ *
+ * Description:
+ * Copy btdm backup DMA when PHY is disabled
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * none
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR btdm_backup_dma_copy_wrapper(uint32_t reg, uint32_t mem_addr,
+ uint32_t num, bool to_mem)
+{
+}
+
+/****************************************************************************
+ * Name: esp_bt_power_domain_on
+ *
+ * Description:
+ * Power up the BT domain
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * none
+ *
+ ****************************************************************************/
+
+static IRAM_ATTR void esp_bt_power_domain_on(void)
+{
+#if SOC_PM_SUPPORT_BT_PD
+ modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PD, 0);
+ modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_ISO, 0);
+#endif
+ esp_wifi_bt_power_domain_on();
+}
+
+/****************************************************************************
+ * Name: esp_bt_power_domain_off
+ *
+ * Description:
+ * Power down the BT domain
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * none
+ *
+ ****************************************************************************/
+
+static IRAM_ATTR void esp_bt_power_domain_off(void)
+{
+#if SOC_PM_SUPPORT_BT_PD
+ modifyreg32(RTC_CNTL_DIG_ISO_REG, 0, RTC_CNTL_BT_FORCE_ISO);
+ modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_BT_FORCE_PD);
+#endif
+ esp_wifi_bt_power_domain_off();
+}
+
+/****************************************************************************
+ * Name: esp_errno_trans
+ *
+ * Description:
+ * Transform from nuttx error code to Wi-Fi adapter error code
+ *
+ * Input Parameters:
+ * ret - NuttX error code
+ *
+ * Returned Value:
+ * Wi-Fi adapter error code
+ *
+ ****************************************************************************/
+
+static inline int32_t esp_errno_trans(int ret)
+{
+ return ret == 0;
+}
+
+/****************************************************************************
+ * Name: interrupt_set_wrapper
+ *
+ * Description:
+ * Bind IRQ and resource with given parameters.
+ *
+ * Input Parameters:
+ * cpu_no - The CPU which the interrupt number belongs.
+ * intr_source - The interrupt peripheral number.
+ * intr_num - The interrupt CPU number.
+ * intr_prio - The interrupt priority.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void interrupt_set_wrapper(int cpu_no,
+ int intr_source,
+ int intr_num,
+ int intr_prio)
+{
+ /* There is no need to set up the interrupt matrix here - neither by
+ * calling `esp_rom_route_intr_matrix` nor by directly setting the
+ * related registers - because the callback `interrupt_on_wrapper` calls
+ * `up_enable_irq`, which already set this up.
+ */
+
+ wlinfo("cpu_no=%d , intr_source=%d , intr_num=%d, intr_prio=%d\n",
+ cpu_no, intr_source, intr_num, intr_prio);
+}
+
+/****************************************************************************
+ * Name: interrupt_clear_wrapper
+ *
+ * Description:
+ * Not supported. Clear previously bound interrupt IRQ.
+ *
+ * Input Parameters:
+ * intr_source - The interrupt peripheral number.
+ * intr_num - The interrupt CPU number.
+ *
+ * Returned Value:
+ * NuttX error code
+ *
+ ****************************************************************************/
+
+static void IRAM_ATTR interrupt_clear_wrapper(int intr_source, int intr_num)
+{
+}
+
+/****************************************************************************
+ * Name: esp_int_adpt_cb
+ *
+ * Description:
+ * BT interrupt adapter callback function
+ *
+ * Input Parameters:
+ * arg - interrupt adapter private data
+ *
+ * Returned Value:
+ * NuttX error code
+ *
+ ****************************************************************************/
+
+static int IRAM_ATTR esp_int_adpt_cb(int irq, void *context, void *arg)
+{
+ struct irq_adpt_s *adapter = (struct irq_adpt_s *)arg;
+
+ adapter->func(adapter->arg);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: interrupt_handler_set_wrapper
+ *
+ * Description:
+ * Register interrupt function
+ *
+ * Input Parameters:
+ * intr_num - The interrupt CPU number.
+ * fn - Interrupt function
+ * arg - Function private data
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void interrupt_handler_set_wrapper(int intr_num, void *fn, void *arg)
+{
+ int ret;
+ struct irq_adpt_s *adapter;
+ int irq = esp32s3_getirq(0, intr_num);
+
+ wlinfo("intr_num=%d fn=%p arg=%p irq=%d\n", intr_num, fn, arg, irq);
+
+ adapter = kmm_malloc(sizeof(struct irq_adpt_s));
+ DEBUGASSERT(adapter);
+
+ adapter->func = fn;
+ adapter->arg = arg;
+
+ ret = irq_attach(irq, esp_int_adpt_cb, adapter);
+ DEBUGASSERT(ret == OK);
+}
+
+/****************************************************************************
+ * Name: interrupt_on_wrapper
+ *
+ * Description:
+ * Enable Wi-Fi interrupt
+ *
+ * Input Parameters:
+ * intr_num - No mean
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void interrupt_on_wrapper(int intr_num)
+{
+ up_enable_irq(intr_num + XTENSA_IRQ_FIRSTPERIPH);
+}
+
+/****************************************************************************
+ * Name: interrupt_off_wrapper
+ *
+ * Description:
+ * Disable Wi-Fi interrupt
+ *
+ * Input Parameters:
+ * intr_num - No mean
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void interrupt_off_wrapper(int intr_num)
+{
+ up_disable_irq(intr_num + XTENSA_IRQ_FIRSTPERIPH);
+}
+
+/****************************************************************************
+ * Name: interrupt_disable
+ *
+ * Description:
+ * Enter critical section by disabling interrupts and taking the spin lock
+ * if in SMP mode.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+static void IRAM_ATTR interrupt_disable(void)
+{
+ g_inter_flags = enter_critical_section();
+}
+
+/****************************************************************************
+ * Name: interrupt_restore
+ *
+ * Description:
+ * Exit from critical section by enabling interrupts and releasing the spin
+ * lock if in SMP mode.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void IRAM_ATTR interrupt_restore(void)
+{
+ leave_critical_section(g_inter_flags);
+}
+
+/****************************************************************************
+ * Name: task_yield_from_isr
+ *
+ * Description:
+ * Perform a solicited context switch on FreeRTOS. Do nothing in NuttX.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void IRAM_ATTR task_yield_from_isr(void)
+{
+}
+
+/****************************************************************************
+ * Name: semphr_create_wrapper
+ *
+ * Description:
+ * Create and initialize semaphore
+ *
+ * Input Parameters:
+ * max - Unused
+ * init - semaphore initialization value
+ *
+ * Returned Value:
+ * Semaphore data pointer
+ *
+ ****************************************************************************/
+
+static void *semphr_create_wrapper(uint32_t max, uint32_t init)
+{
+ int ret;
+ sem_t *sem;
+ int tmp;
+
+ tmp = sizeof(sem_t);
+ sem = kmm_malloc(tmp);
+ if (!sem)
+ {
+ wlerr("ERROR: Failed to alloc %d memory\n", tmp);
+ return NULL;
+ }
+
+ ret = nxsem_init(sem, 0, init);
+ if (ret)
+ {
+ wlerr("ERROR: Failed to initialize sem error=%d\n", ret);
+ kmm_free(sem);
+ return NULL;
+ }
+
+ return sem;
+}
+
+/****************************************************************************
+ * Name: semphr_delete_wrapper
+ *
+ * Description:
+ * Delete semaphore
+ *
+ * Input Parameters:
+ * semphr - Semaphore data pointer
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void semphr_delete_wrapper(void *semphr)
+{
+ sem_t *sem = (sem_t *)semphr;
+ nxsem_destroy(sem);
+ kmm_free(sem);
+}
+
+/****************************************************************************
+ * Name: semphr_take_from_isr_wrapper
+ *
+ * Description:
+ * Take a semaphore from an ISR
+ *
+ * Input Parameters:
+ * semphr - Semaphore data pointer.
+ * hptw - Unused.
+ *
+ * Returned Value:
+ * True if success or false if fail
+ *
+ ****************************************************************************/
+
+static int IRAM_ATTR semphr_take_from_isr_wrapper(void *semphr, void *hptw)
+{
+ DEBUGPANIC();
+ return false;
+}
+
+/****************************************************************************
+ * Name: semphr_give_from_isr_wrapper
+ *
+ * Description:
+ * Post semaphore
+ *
+ * Input Parameters:
+ * semphr - Semaphore data pointer
+ * hptw - Unused.
+ *
+ * Returned Value:
+ * True if success or false if fail
+ *
+ ****************************************************************************/
+
+static int IRAM_ATTR semphr_give_from_isr_wrapper(void *semphr, void *hptw)
+{
+ sem_t *sem = (sem_t *)semphr;
+
+ return esp_errno_trans(semphr_give_wrapper(sem));
+}
+
+/****************************************************************************
+ * Name: esp_update_time
+ *
+ * Description:
+ * Transform ticks to time and add this time to timespec value
+ *
+ * Input Parameters:
+ * ticks - System ticks
+ *
+ * Output Parameters:
+ * timespec - Input timespec data pointer
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void esp_update_time(struct timespec *timespec, uint32_t ticks)
+{
+ uint32_t tmp;
+
+ tmp = TICK2SEC(ticks);
+ timespec->tv_sec += tmp;
+
+ ticks -= SEC2TICK(tmp);
+ tmp = TICK2NSEC(ticks);
+
+ timespec->tv_nsec += tmp;
+}
+
+/****************************************************************************
+ * Name: semphr_take_wrapper
+ *
+ * Description:
+ * Wait semaphore within a certain period of time
+ *
+ * Input Parameters:
+ * semphr - Semaphore data pointer
+ * block_time_ms - Wait time
+ *
+ * Returned Value:
+ * True if success or false if fail
+ *
+ ****************************************************************************/
+
+static int semphr_take_wrapper(void *semphr, uint32_t block_time_ms)
+{
+ int ret;
+ sem_t *sem = (sem_t *)semphr;
+
+ if (block_time_ms == OSI_FUNCS_TIME_BLOCKING)
+ {
+ ret = nxsem_wait(sem);
+ }
+ else
+ {
+ if (block_time_ms > 0)
+ {
+ ret = nxsem_tickwait(sem, MSEC2TICK(block_time_ms));
+ }
+ else
+ {
+ ret = nxsem_trywait(sem);
+ }
+ }
+
+ if (ret)
+ {
+ wlerr("Failed to take sem error=%d\n", ret);
+ }
+
+ return esp_errno_trans(ret);
+}
+
+/****************************************************************************
+ * Name: semphr_give_wrapper
+ *
+ * Description:
+ * Post semaphore
+ *
+ * Input Parameters:
+ * semphr - Semaphore data pointer
+ *
+ * Returned Value:
+ * True if success or false if fail
+ *
+ ****************************************************************************/
+
+static int semphr_give_wrapper(void *semphr)
+{
+ int ret;
+ sem_t *sem = (sem_t *)semphr;
+
+ ret = nxsem_post(sem);
+ if (ret)
+ {
+ wlerr("Failed to post sem error=%d\n", ret);
+ }
+
+ return esp_errno_trans(ret);
+}
+
+/****************************************************************************
+ * Name: mutex_create_wrapper
+ *
+ * Description:
+ * Create mutex
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Mutex data pointer
+ *
+ ****************************************************************************/
+
+static void *mutex_create_wrapper(void)
+{
+ int ret;
+ pthread_mutex_t *mutex;
+ int tmp;
+
+ tmp = sizeof(pthread_mutex_t);
+ mutex = kmm_malloc(tmp);
+ DEBUGASSERT(mutex);
+
+ ret = pthread_mutex_init(mutex, NULL);
+ if (ret)
+ {
+ wlerr("Failed to initialize mutex error=%d\n", ret);
+ kmm_free(mutex);
+ return NULL;
+ }
+
+ return mutex;
+}
+
+/****************************************************************************
+ * Name: mutex_delete_wrapper
+ *
+ * Description:
+ * Delete mutex
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Mutex data pointer
+ *
+ ****************************************************************************/
+
+static void mutex_delete_wrapper(void *mutex)
+{
+ pthread_mutex_destroy(mutex);
+ kmm_free(mutex);
+}
+
+/****************************************************************************
+ * Name: mutex_lock_wrapper
+ *
+ * Description:
+ * Lock mutex
+ *
+ * Input Parameters:
+ * mutex_data - mutex data pointer
+ *
+ * Returned Value:
+ * True if success or false if fail
+ *
+ ****************************************************************************/
+
+static int mutex_lock_wrapper(void *mutex)
+{
+ int ret;
+
+ ret = pthread_mutex_lock(mutex);
+ if (ret)
+ {
+ wlerr("Failed to lock mutex error=%d\n", ret);
+ }
+
+ return esp_errno_trans(ret);
+}
+
+/****************************************************************************
+ * Name: mutex_unlock_wrapper
+ *
+ * Description:
+ * Unlock mutex
+ *
+ * Input Parameters:
+ * mutex_data - mutex data pointer
+ *
+ * Returned Value:
+ * True if success or false if fail
+ *
+ ****************************************************************************/
+
+static int mutex_unlock_wrapper(void *mutex)
+{
+ int ret;
+
+ ret = pthread_mutex_unlock(mutex);
+ if (ret)
+ {
+ wlerr("Failed to unlock mutex error=%d\n", ret);
+ }
+
+ return esp_errno_trans(ret);
+}
+
+/****************************************************************************
+ * Name: esp_queue_send_generic
+ *
+ * Description:
+ * Generic send message to queue within a certain period of time
+ *
+ * Input Parameters:
+ * queue - Message queue data pointer
+ * item - Message data pointer
+ * ticks - Wait ticks
+ * prio - Message priority
+ *
+ * Returned Value:
+ * True if success or false if fail
+ *
+ ****************************************************************************/
+
+static int32_t esp_queue_send_generic(void *queue, void *item,
+ uint32_t ticks, int prio)
+{
+ int ret;
+ struct timespec timeout;
+ struct mq_adpt_s *mq_adpt = (struct mq_adpt_s *)queue;
+
+ if (ticks == OSI_FUNCS_TIME_BLOCKING || ticks == 0)
+ {
+ /**
+ * BLE interrupt function will call this adapter function to send
+ * message to message queue, so here we should call kernel API
+ * instead of application API
+ */
+
+ ret = file_mq_send(&mq_adpt->mq, (const char *)item,
+ mq_adpt->msgsize, prio);
+ if (ret < 0)
+ {
+ wlerr("Failed to send message to mqueue error=%d\n", ret);
+ }
+ }
+ else
+ {
+ ret = clock_gettime(CLOCK_REALTIME, &timeout);
+ if (ret < 0)
+ {
+ wlerr("Failed to get time %d\n", ret);
+ return esp_errno_trans(ret);
+ }
+
+ if (ticks)
+ {
+ esp_update_time(&timeout, ticks);
+ }
+
+ ret = file_mq_timedsend(&mq_adpt->mq, (const char *)item,
+ mq_adpt->msgsize, prio, &timeout);
+ if (ret < 0)
+ {
+ wlerr("Failed to timedsend message to mqueue error=%d\n", ret);
+ }
+ }
+
+ return esp_errno_trans(ret);
+}
+
+/****************************************************************************
+ * Name: queue_create_wrapper
+ *
+ * Description:
+ * Create message queue
+ *
+ * Input Parameters:
+ * queue_len - queue message number
+ * item_size - message size
+ *
+ * Returned Value:
+ * Message queue data pointer
+ *
+ ****************************************************************************/
+
+static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size)
+{
+ struct mq_attr attr;
+ struct mq_adpt_s *mq_adpt;
+ int ret;
+
+ mq_adpt = kmm_malloc(sizeof(struct mq_adpt_s));
+ DEBUGASSERT(mq_adpt);
+
+ snprintf(mq_adpt->name, sizeof(mq_adpt->name), "/tmp/%p", mq_adpt);
+
+ attr.mq_maxmsg = queue_len;
+ attr.mq_msgsize = item_size;
+ attr.mq_curmsgs = 0;
+ attr.mq_flags = 0;
+
+ ret = file_mq_open(&mq_adpt->mq, mq_adpt->name,
+ O_RDWR | O_CREAT, 0644, &attr);
+
+ if (ret < 0)
+ {
+ wlerr("Failed to create mqueue %d\n", ret);
+ kmm_free(mq_adpt);
+ return NULL;
+ }
+
+ mq_adpt->msgsize = item_size;
+ return (void *)mq_adpt;
+}
+
+/****************************************************************************
+ * Name: queue_delete_wrapper
+ *
+ * Description:
+ * Delete message queue
+ *
+ * Input Parameters:
+ * queue - Message queue data pointer
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void queue_delete_wrapper(void *queue)
+{
+ struct mq_adpt_s *mq_adpt = (struct mq_adpt_s *)queue;
+
+ file_mq_close(&mq_adpt->mq);
+ file_mq_unlink(mq_adpt->name);
+ kmm_free(mq_adpt);
+}
+
+/****************************************************************************
+ * Name: queue_send_wrapper
+ *
+ * Description:
+ * Generic send message to queue within a certain period of time
+ *
+ * Input Parameters:
+ * queue - Message queue data pointer
+ * item - Item to be sent.
+ * block_time_ms - Wait time
+ *
+ * Returned Value:uint32_t
+ * True if success or false if fail
+ *
+ ****************************************************************************/
+
+static int queue_send_wrapper(void *queue, void *item,
+ uint32_t block_time_ms)
+{
+ return esp_queue_send_generic(queue, item, block_time_ms, 0);
+}
+
+/****************************************************************************
+ * Name: queue_send_from_isr_wrapper
+ *
+ * Description:
+ * Send message of low priority to queue in ISR within
+ * a certain period of time
+ *
+ * Input Parameters:
+ * queue - Message queue data pointer
+ * item - Message data pointer
+ * hptw - Unused
+ *
+ * Returned Value:
+ * True if success or false if fail
+ *
+ ****************************************************************************/
+
+static int IRAM_ATTR queue_send_from_isr_wrapper(void *queue,
+ void *item,
+ void *hptw)
+{
+ return esp_queue_send_generic(queue, item, 0, 0);
+}
+
+/****************************************************************************
+ * Name: queue_recv_wrapper
+ *
+ * Description:
+ * Receive message from queue within a certain period of time
+ *
+ * Input Parameters:
+ * queue - Message queue data pointer
+ * item - Message data pointer
+ * block_time_ms - Wait time
+ *
+ * Returned Value:
+ * True if success or false if fail
+ *
+ ****************************************************************************/
+
+static int queue_recv_wrapper(void *queue, void *item,
+ uint32_t block_time_ms)
+{
+ ssize_t ret;
+ struct timespec timeout;
+ unsigned int prio;
+ struct mq_adpt_s *mq_adpt = (struct mq_adpt_s *)queue;
+
+ if (block_time_ms == OSI_FUNCS_TIME_BLOCKING)
+ {
+ ret = file_mq_receive(&mq_adpt->mq, (char *)item,
+ mq_adpt->msgsize, &prio);
+
+ if (ret < 0)
+ {
+ wlerr("Failed to receive from mqueue error=%d\n", ret);
+ }
+ }
+ else
+ {
+ ret = clock_gettime(CLOCK_REALTIME, &timeout);
+
+ if (ret < 0)
+ {
+ wlerr("Failed to get time %d\n", ret);
+ return false;
+ }
+
+ if (block_time_ms)
+ {
+ esp_update_time(&timeout, MSEC2TICK(block_time_ms));
+ }
+
+ ret = file_mq_timedreceive(&mq_adpt->mq, (char *)item,
+ mq_adpt->msgsize, &prio, &timeout);
+
+ if (ret < 0 && ret != -ETIMEDOUT)
+ {
+ wlerr("Failed to timedreceive from mqueue error=%d\n", ret);
+ }
+ }
+
+ return ret > 0 ? true : false;
+}
+
+/****************************************************************************
+ * Name: queue_recv_from_isr_wrapper
+ *
+ * Description:
+ * Receive message from queue within a certain period of time
+ *
+ * Input Parameters:
+ * queue - Message queue data pointer
+ * item - Message data pointer
+ * hptw - Unused
+ *
+ * Returned Value:
+ * True if success or false if fail
+ *
+ ****************************************************************************/
+
+static int IRAM_ATTR queue_recv_from_isr_wrapper(void *queue,
+ void *item,
+ void *hptw)
+{
+ ssize_t ret;
+ struct timespec timeout;
+ unsigned int prio;
+ struct mq_adpt_s *mq_adpt = (struct mq_adpt_s *)queue;
+
+ ret = clock_gettime(CLOCK_REALTIME, &timeout);
+
+ if (ret < 0)
+ {
+ wlerr("Failed to get time %d\n", ret);
+ return false;
+ }
+
+ ret = file_mq_timedreceive(&mq_adpt->mq, (char *)item,
+ mq_adpt->msgsize, &prio, &timeout);
+
+ if (ret < 0 && ret != -ETIMEDOUT)
+ {
+ wlerr("Failed to timedreceive from mqueue error=%d\n", ret);
+ }
+
+ return ret > 0 ? true : false;
+}
+
+/****************************************************************************
+ * Name: esp_task_create_pinned_to_core
+ *
+ * Description:
+ * Create task and bind it to target CPU, the task will run when it
+ * is created
+ *
+ * Input Parameters:
+ * entry - Task entry
+ * name - Task name
+ * stack_depth - Task stack size
+ * param - Task private data
+ * prio - Task priority
+ * task_handle - Task handle pointer which is used to pause, resume
+ * and delete the task
+ * core_id - CPU which the task runs in
+ *
+ * Returned Value:
+ * True if success or false if fail
+ *
+ ****************************************************************************/
+
+static int32_t esp_task_create_pinned_to_core(void *entry,
+ const char *name,
+ uint32_t stack_depth,
+ void *param,
+ uint32_t prio,
+ void *task_handle,
+ uint32_t core_id)
+{
+ int pid;
+#ifdef CONFIG_SMP
+ int ret;
+ cpu_set_t cpuset;
+#endif
+
+ DEBUGASSERT(task_handle != NULL);
+
+ pid = kthread_create(name, prio, stack_depth, entry,
+ (char * const *)param);
+ if (pid > 0)
+ {
+ if (task_handle)
+ {
+ *((int *)task_handle) = pid;
+ }
+
+#ifdef CONFIG_SMP
+ if (core_id < CONFIG_SMP_NCPUS)
+ {
+ CPU_ZERO(&cpuset);
+ CPU_SET(core_id, &cpuset);
+ ret = nxsched_set_affinity(pid, sizeof(cpuset), &cpuset);
+ if (ret)
+ {
+ wlerr("Failed to set affinity error=%d\n", ret);
+ return false;
+ }
+ }
+#endif
+ }
+ else
+ {
+ wlerr("Failed to create task, error %d\n", pid);
+ }
+
+ return pid > 0;
+}
+
+/****************************************************************************
+ * Name: task_create_wrapper
+ *
+ * Description:
+ * Create task and the task will run when it is created
+ *
+ * Input Parameters:
+ * entry - Task entry
+ * name - Task name
+ * stack_depth - Task stack size
+ * param - Task private data
+ * prio - Task priority
+ * task_handle - Task handle pointer which is used to pause, resume
+ * and delete the task
+ *
+ * Returned Value:
+ * True if success or false if fail
+ *
+ ****************************************************************************/
+
+static int task_create_wrapper(void *task_func, const char *name,
+ uint32_t stack_depth, void *param,
+ uint32_t prio, void *task_handle,
+ uint32_t core_id)
+{
+ return esp_task_create_pinned_to_core(task_func, name,
+ stack_depth, param,
+ prio, task_handle, UINT32_MAX);
+}
+
+/****************************************************************************
+ * Name: task_delete_wrapper
+ *
+ * Description:
+ * Delete the target task
+ *
+ * Input Parameters:
+ * task_handle - Task handle pointer which is used to pause, resume
+ * and delete the task
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void task_delete_wrapper(void *task_handle)
+{
+ pid_t pid = (pid_t)((uintptr_t)task_handle);
+ kthread_delete(pid);
+}
+
+/****************************************************************************
+ * Name: is_in_isr_wrapper
+ *
+ * Description:
+ * Check current is in interrupt
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * true if in interrupt or false if not
+ *
+ ****************************************************************************/
+
+static bool IRAM_ATTR is_in_isr_wrapper(void)
+{
+ return up_interrupt_context();
+}
+
+/****************************************************************************
+ * Name: malloc_wrapper
+ *
+ * Description:
+ * Malloc buffer
+ *
+ * Input Parameters:
+ * size - buffer size
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void *malloc_wrapper(size_t size)
+{
+ void * p = kmm_malloc(size);
+ DEBUGASSERT(p);
+
+ return p;
+}
+
+/****************************************************************************
+ * Name: malloc_internal_wrapper
+ *
+ * Description:
+ * Malloc buffer in DRAM
+ *
+ * Input Parameters:
+ * size - buffer size
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void *malloc_internal_wrapper(size_t size)
+{
+ void * p = kmm_malloc(size);
+
+ if (p != NULL)
+ {
+ if (esp32s3_ptr_extram(p))
+ {
+ kmm_free(p);
+ return NULL;
+ }
+ }
+
+ return p;
+}
+
+/****************************************************************************
+ * Name: read_mac_wrapper
+ *
+ * Description:
+ * Get Mac Address
+ *
+ * Input Parameters:
+ * mac - mac address
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. Otherwise, -1 (ERROR) is returned.
+ *
+ ****************************************************************************/
+
+static int IRAM_ATTR read_mac_wrapper(uint8_t mac[6])
+{
+ return esp_read_mac(mac, ESP_MAC_BT);
+}
+
+/****************************************************************************
+ * Name: srand_wrapper
+ *
+ * Description:
+ * Get random value with seed input. Not implemented.
+ *
+ * Input Parameters:
+ * seed - Value to be used as seed.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void IRAM_ATTR srand_wrapper(unsigned int seed)
+{
+}
+
+/****************************************************************************
+ * Name: rand_wrapper
+ *
+ * Description:
+ * Get random value.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Random value
+ *
+ ****************************************************************************/
+
+static int IRAM_ATTR rand_wrapper(void)
+{
+ return esp_random();
+}
+
+/****************************************************************************
+ * Name: btdm_lpcycles_2_hus
+ *
+ * Description:
+ * Converts a number of low power clock cycles into a duration in half us.
+ *
+ * Input Parameters:
+ * cycles - number of CPU cycles
+ * error_corr - local error corr
+ *
+ * Returned Value:
+ * res - value equivalent to the CPU cycles
+ *
+ ****************************************************************************/
+
+static uint32_t IRAM_ATTR btdm_lpcycles_2_hus(uint32_t cycles,
+ uint32_t *error_corr)
+{
+ uint64_t local_error_corr;
+ uint64_t res;
+
+ local_error_corr = (error_corr == NULL) ? 0 : (uint64_t)(*error_corr);
+ res = (uint64_t)g_btdm_lpcycle_us * cycles * 2;
+
+ local_error_corr += res;
+ res = (local_error_corr >> g_btdm_lpcycle_us_frac);
+ local_error_corr -= (res << g_btdm_lpcycle_us_frac);
+ if (error_corr)
+ {
+ *error_corr = (uint32_t)local_error_corr;
+ }
+ return (uint32_t)res;
+}
+
+/****************************************************************************
+ * Name: btdm_hus_2_lpcycles
+ *
+ * Description:
+ * Converts a duration in half us into a number of low power clock cycles.
+ *
+ * Input Parameters:
+ * hus - sleep duration (us)
+ *
+ * Returned Value:
+ * cycles
+ *
+ ****************************************************************************/
+
+static uint32_t IRAM_ATTR btdm_hus_2_lpcycles(uint32_t hus)
+{
+ /* The number of sleep duration(us) should not lead to overflow. Thrs: 100s
+ * Compute the sleep duration in us to low power clock cycles, with
+ * calibration result applied clock measurement is conducted
+ */
+
+ uint64_t cycles;
+
+ cycles = ((uint64_t)(hus) << g_btdm_lpcycle_us_frac) / g_btdm_lpcycle_us;
+ cycles >>= 1;
+
+ return (uint32_t)cycles;
+}
+
+/****************************************************************************
+ * Name: btdm_sleep_check_duration
+ *
+ * Description:
+ * Wake up in advance considering the delay in enabling PHY/RF.
+ *
+ * Input Parameters:
+ * half_slot_cnt - half slots to allow to fall into modem sleep
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static bool IRAM_ATTR btdm_sleep_check_duration(int32_t *half_slot_cnt)
+{
+ if (*half_slot_cnt < BTDM_MIN_SLEEP_DURATION)
+ {
+ return false;
+ }
+
+ *half_slot_cnt -= BTDM_MODEM_WAKE_UP_DELAY;
+ return true;
+}
+
+/****************************************************************************
+ * Name: btdm_sleep_enter_phase1_wrapper
+ *
+ * Description:
+ * ESP32-S3 BLE lightsleep callback function.
+ *
+ * Input Parameters:
+ * lpcycles - light sleep cycles
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles)
+{
+ uint32_t us_to_sleep;
+ uint32_t uncertainty;
+
+ if (!g_lp_cntl.wakeup_timer_required)
+ {
+ return;
+ }
+
+ /* start a timer to wake up and acquire the pm_lock before sleep awakes */
+
+ us_to_sleep = btdm_lpcycles_2_hus(lpcycles, NULL) >> 1;
+
+ DEBUGASSERT(us_to_sleep > BTDM_MIN_TIMER_UNCERTAINTY_US);
+ uncertainty = (us_to_sleep >> 11);
+
+ if (uncertainty < BTDM_MIN_TIMER_UNCERTAINTY_US)
+ {
+ uncertainty = BTDM_MIN_TIMER_UNCERTAINTY_US;
+ }
+
+ DEBUGASSERT(g_lp_stat.wakeup_timer_started == false);
+
+ if (esp_timer_start_once(g_btdm_slp_tmr,
+ us_to_sleep - uncertainty) == ESP_OK)
+ {
+ g_lp_stat.wakeup_timer_started = true;
+ }
+ else
+ {
+ wlerr("timer start failed");
+ DEBUGPANIC();
+ }
+}
+
+/****************************************************************************
+ * Name: btdm_sleep_enter_phase2_wrapper
+ *
+ * Description:
+ * ESP32-S3 BLE lightsleep callback function.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void btdm_sleep_enter_phase2_wrapper(void)
+{
+ if (btdm_controller_get_sleep_mode() == ESP_BT_SLEEP_MODE_1)
+ {
+ if (g_lp_stat.phy_enabled)
+ {
+ esp32s3_phy_disable();
+ g_lp_stat.phy_enabled = false;
+ }
+ else
+ {
+ DEBUGPANIC();
+ }
+
+ if (!g_lp_stat.pm_lock_released)
+ {
+#ifdef CONFIG_PM_ENABLE
+ esp32s3_pm_lockrelease();
+#endif
+ g_lp_stat.pm_lock_released = true;
+ }
+ }
+}
+
+/****************************************************************************
+ * Name: btdm_sleep_exit_phase3_wrapper
+ *
+ * Description:
+ * ESP32-S3 BLE lightsleep callback function..
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void btdm_sleep_exit_phase3_wrapper(void)
+{
+#ifdef CONFIG_PM_ENABLE
+ if (g_lp_stat.pm_lock_released)
+ {
+ esp32s3_pm_lockacquire();
+ g_lp_stat.pm_lock_released = false;
+ }
+#endif
+
+ if (btdm_controller_get_sleep_mode() == ESP_BT_SLEEP_MODE_1)
+ {
+ if (!g_lp_stat.phy_enabled)
+ {
+ esp32s3_phy_enable();
+ g_lp_stat.phy_enabled = true;
+ }
+ }
+
+ if (g_lp_cntl.wakeup_timer_required && g_lp_stat.wakeup_timer_started)
+ {
+ esp_timer_stop(g_btdm_slp_tmr);
+ g_lp_stat.wakeup_timer_started = false;
+ }
+
+ while (btdm_sleep_clock_sync());
+}
+
+/****************************************************************************
+ * Name: btdm_sleep_exit_phase0
+ *
+ * Description:
+ * Acquire PM lock and stop esp timer.
+ *
+ * Input Parameters:
+ * param - wakeup event
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void IRAM_ATTR btdm_sleep_exit_phase0(void *param)
+{
+ DEBUGASSERT(g_lp_cntl.enable);
+
+#ifdef CONFIG_PM
+ if (g_lp_stat.pm_lock_released)
+ {
+ esp32s3_pm_lockacquire();
+ g_lp_stat.pm_lock_released = false;
+ }
+#endif
+
+ int event = (int)param;
+
+ if (event == BTDM_ASYNC_WAKEUP_SRC_VHCI ||
+ event == BTDM_ASYNC_WAKEUP_SRC_DISA)
+ {
+ btdm_wakeup_request();
+ }
+
+ if (g_lp_cntl.wakeup_timer_required && g_lp_stat.wakeup_timer_started)
+ {
+ esp_timer_stop(g_btdm_slp_tmr);
+ g_lp_stat.wakeup_timer_started = false;
+ }
+
+ if (event == BTDM_ASYNC_WAKEUP_SRC_VHCI ||
+ event == BTDM_ASYNC_WAKEUP_SRC_DISA)
+ {
+ semphr_give_wrapper(g_wakeup_req_sem);
+ }
+}
+
+/****************************************************************************
+ * Name: btdm_slp_tmr_callback
+ *
+ * Description:
+ * ESP-S3 BLE sleep callback function.
+ *
+ * Input Parameters:
+ * arg - Unused
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void IRAM_ATTR btdm_slp_tmr_callback(void *arg)
+{
+#ifdef CONFIG_PM
+ btdm_vnd_offload_post(BTDM_VND_OL_SIG_WAKEUP_TMR,
+ (void *)BTDM_ASYNC_WAKEUP_SRC_TMR);
+#endif
+}
+
+/****************************************************************************
+ * Name: coex_schm_status_bit_set_wrapper
+ *
+ * Description:
+ * Set coexistence status.
+ *
+ * Input Parameters:
+ * type - Coexistence status type
+ * status - Coexistence status
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status)
+{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ coex_schm_status_bit_set(type, status);
+#endif
+}
+
+/****************************************************************************
+ * Name: coex_schm_status_bit_clear_wrapper
+ *
+ * Description:
+ * Clear coexistence status.
+ *
+ * Input Parameters:
+ * type - Coexistence status type
+ * status - Coexistence status
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void coex_schm_status_bit_clear_wrapper(uint32_t type,
+ uint32_t status)
+{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ coex_schm_status_bit_clear(type, status);
+#endif
+}
+
+/****************************************************************************
+ * Name: esp32s3_vhci_host_check_send_available
+ *
+ * Description:
+ * Check if the host can send packet to controller or not.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * bool - true or false
+ *
+ ****************************************************************************/
+
+bool esp32s3_vhci_host_check_send_available(void)
+{
+ if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED)
+ {
+ return false;
+ }
+
+ return api_vhci_host_check_send_available();
+}
+
+/****************************************************************************
+ * Name: esp32s3_vhci_host_send_packet
+ *
+ * Description:
+ * Host send packet to controller.
+ *
+ * Input Parameters:
+ * data - the packet pointer
+ * len - the packet length
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp32s3_vhci_host_send_packet(uint8_t *data, uint16_t len)
+{
+ if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED)
+ {
+ return;
+ }
+
+ api_vhci_host_send_packet(data, len);
+}
+
+/****************************************************************************
+ * Name: esp32s3_vhci_register_callback
+ *
+ * Description:
+ * Register the vhci reference callback.
+ *
+ * Input Parameters:
+ * callback - struct defined by vhci_host_callback structure.
+ *
+ * Returned Value:
+ * status - success or fail
+ *
+ ****************************************************************************/
+
+int esp32s3_vhci_register_callback(const esp_vhci_host_callback_t *callback)
+{
+ int ret = ERROR;
+ if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED)
+ {
+ return ret;
+ }
+
+ ret = api_vhci_host_register_callback(
+ (const vhci_host_callback_t *)callback) == 0 ? 0 : -1;
+ return ret;
+}
+
+/****************************************************************************
+ * Name: btdm_controller_mem_init
+ *
+ * Description:
+ * Initialize BT controller to allocate task and other resource.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void btdm_controller_mem_init(void)
+{
+ extern void btdm_controller_rom_data_init(void);
+ btdm_controller_rom_data_init();
+}
+
+#if CONFIG_MAC_BB_PD
+static void IRAM_ATTR btdm_mac_bb_power_down_cb(void)
+{
+ if (g_lp_cntl.mac_bb_pd && g_lp_stat.mac_bb_pd == 0)
+ {
+ btdm_ble_power_down_dma_copy(true);
+ g_lp_stat.mac_bb_pd = 1;
+ }
+}
+
+static void IRAM_ATTR btdm_mac_bb_power_up_cb(void)
+{
+ if (g_lp_cntl.mac_bb_pd && g_lp_stat.mac_bb_pd)
+ {
+ btdm_ble_power_down_dma_copy(false);
+ g_lp_stat.mac_bb_pd = 0;
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: coex_wifi_sleep_set_hook
+ *
+ * Description:
+ * Set Wi-Fi/BT coexistence sleep.
+ *
+ * Input Parameters:
+ * sleep - True to set sleep, false otherwise.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void coex_wifi_sleep_set_hook(bool sleep)
+{
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_bt_controller_init
+ *
+ * Description:
+ * Init BT controller.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+int esp32s3_bt_controller_init(void)
+{
+ esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
+ esp_bt_controller_config_t *cfg = &bt_cfg;
+ bool select_src_ret;
+ bool set_div_ret;
+
+ if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE)
+ {
+ wlerr("Invalid controller status");
+ return ERROR;
+ }
+
+ if (cfg == NULL)
+ {
+ return ESP_ERR_INVALID_ARG;
+ }
+
+ if (cfg->controller_task_prio != ESP_TASK_BT_CONTROLLER_PRIO ||
+ cfg->controller_task_stack_size < ESP_TASK_BT_CONTROLLER_STACK)
+ {
+ wlerr("Invalid controller task prioriy or stack size");
+ return ERROR;
+ }
+
+ if (cfg->bluetooth_mode != ESP_BT_MODE_BLE)
+ {
+ wlerr("Controller only support BLE only mode");
+ return ERROR;
+ }
+
+ if (cfg->bluetooth_mode & ESP_BT_MODE_BLE)
+ {
+ if ((cfg->ble_max_act <= 0) ||
+ (cfg->ble_max_act > BT_CTRL_BLE_MAX_ACT_LIMIT))
+ {
+ wlerr("Invalid value of ble_max_act");
+ return ERROR;
+ }
+ }
+
+ if (cfg->sleep_mode == ESP_BT_SLEEP_MODE_1)
+ {
+ if (cfg->sleep_clock == ESP_BT_SLEEP_CLOCK_NONE)
+ {
+ wlerr("SLEEP_MODE_1 enabled but sleep clock not configured");
+ return ERROR;
+ }
+ }
+
+ cfg->controller_task_stack_size = CONFIG_ESP32S3_BLE_TASK_STACK_SIZE;
+ cfg->controller_task_prio = CONFIG_ESP32S3_BLE_TASK_PRIORITY;
+ cfg->controller_task_run_cpu = CONFIG_BT_CTRL_PINNED_TO_CORE;
+ cfg->magic = ESP_BT_CTRL_CONFIG_MAGIC_VAL;
+
+ esp_bt_power_domain_on();
+
+ btdm_controller_mem_init();
+
+ osi_funcs_p = (struct osi_funcs_s *)kmm_malloc(sizeof(struct osi_funcs_s));
+ if (osi_funcs_p == NULL)
+ {
+ return -ENOMEM;
+ }
+
+ memcpy(osi_funcs_p, &g_osi_funcs, sizeof(struct osi_funcs_s));
+
+ if (btdm_osi_funcs_register(osi_funcs_p) != 0)
+ {
+ wlerr("Error, probably invalid OSI Functions\n");
+ return -EINVAL;
+ }
+
+ wlinfo("BT controller compile version [%s]\n",
+ btdm_controller_get_compile_version());
+
+ /* init low-power control resources */
+
+ do
+ {
+ /* set default values for global states or resources */
+
+ g_lp_cntl.val = 0;
+ g_lp_stat.val = 0;
+ g_wakeup_req_sem = NULL;
+ g_btdm_slp_tmr = NULL;
+
+ /* configure and initialize resources */
+
+ g_lp_cntl.enable = (cfg->sleep_mode == ESP_BT_SLEEP_MODE_1) ? 1 : 0;
+ g_lp_cntl.no_light_sleep = 0;
+
+ if (g_lp_cntl.enable)
+ {
+#if CONFIG_MAC_BB_PD
+ if (!btdm_deep_sleep_mem_init())
+ {
+ goto error;
+ }
+
+ g_lp_cntl.mac_bb_pd = 1;
+#endif
+#ifdef CONFIG_PM
+ g_lp_cntl.wakeup_timer_required = true;
+#endif
+ /* async wakeup semaphore for VHCI */
+
+ g_wakeup_req_sem = semphr_create_wrapper(1, 0);
+ if (g_wakeup_req_sem == NULL)
+ {
+ goto error;
+ }
+
+ btdm_vnd_offload_task_register(BTDM_VND_OL_SIG_WAKEUP_TMR,
+ btdm_sleep_exit_phase0);
+ }
+
+ if (g_lp_cntl.wakeup_timer_required)
+ {
+ esp_timer_create_args_t create_args =
+ {
+ .callback = btdm_slp_tmr_callback,
+ .arg = NULL,
+ .name = "btSlp",
+ };
+
+ if (esp_timer_create(&create_args, &g_btdm_slp_tmr) != OK)
+ {
+ wlerr("Failed to create timer");
+ goto error;
+ }
+ }
+
+ g_btdm_lpcycle_us_frac = RTC_CLK_CAL_FRACT;
+ g_btdm_lpcycle_us = 2 << (g_btdm_lpcycle_us_frac);
+
+ /* set default bluetooth sleep clock source */
+
+ g_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_XTAL; /* set default value */
+
+#if CONFIG_BT_CTRL_LPCLK_SEL_EXT_32K_XTAL
+ if (esp32s3_rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_32K_XTAL)
+ {
+ g_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_XTAL32K;
+ }
+ else
+ {
+ wlwarn("32.768kHz XTAL not detected");
+#if !CONFIG_BT_CTRL_MAIN_XTAL_PU_DURING_LIGHT_SLEEP
+ g_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_XTAL;
+#endif
+ }
+#elif (CONFIG_BT_CTRL_LPCLK_SEL_MAIN_XTAL)
+ wlwarn("Bluetooth will use main XTAL as Bluetooth sleep clock.");
+#if !CONFIG_BT_CTRL_MAIN_XTAL_PU_DURING_LIGHT_SLEEP
+ g_lp_cntl.no_light_sleep = 1;
+#endif
+#elif (CONFIG_BT_CTRL_LPCLK_SEL_RTC_SLOW)
+ /* check whether or not internal 150 kHz RC oscillator is working */
+
+ if (rtc_clk_slow_src_get() == RTC_SLOW_FREQ_RTC)
+ {
+ g_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_RTC_SLOW; /* Internal 150 kHz RC oscillator */
+ wlwarn("Internal 150kHz RC osciallator. The accuracy of this "
+ "clock is a lot larger than 500ppm which is required in "
+ "Bluetooth communication, so don't select this option in "
+ "scenarios such as BLE connection state.");
+ }
+ else
+ {
+ wlerr("Internal 150kHz RC oscillator not detected.");
+ assert(0);
+ }
+#endif
+
+ if (g_lp_cntl.lpclk_sel == BTDM_LPCLK_SEL_XTAL)
+ {
+ uint32_t rtc_clk_xtal_freq = 0;
+#ifdef CONFIG_BT_CTRL_MAIN_XTAL_PU_DURING_LIGHT_SLEEP
+ s_lp_cntl.main_xtal_pu = 1;
+#endif
+ select_src_ret = btdm_lpclk_select_src(BTDM_LPCLK_SEL_XTAL);
+ rtc_clk_xtal_freq = esp32s3_rtc_clk_xtal_freq_get();
+ set_div_ret = btdm_lpclk_set_div(rtc_clk_xtal_freq);
+ DEBUGASSERT(select_src_ret && set_div_ret);
+ g_btdm_lpcycle_us_frac = RTC_CLK_CAL_FRACT;
+ g_btdm_lpcycle_us = 1 << (g_btdm_lpcycle_us_frac);
+ }
+ else if (g_lp_cntl.lpclk_sel == BTDM_LPCLK_SEL_XTAL32K)
+ {
+ select_src_ret = btdm_lpclk_select_src(BTDM_LPCLK_SEL_XTAL32K);
+ set_div_ret = btdm_lpclk_set_div(0);
+ DEBUGASSERT(select_src_ret && set_div_ret);
+ g_btdm_lpcycle_us_frac = RTC_CLK_CAL_FRACT;
+ g_btdm_lpcycle_us = (RTC_CLK_CAL_FRACT > 15) ?
+ (1000000 << (RTC_CLK_CAL_FRACT - 15)) :
+ (1000000 >> (15 - RTC_CLK_CAL_FRACT));
+ DEBUGASSERT(g_btdm_lpcycle_us != 0);
+ }
+ else if (g_lp_cntl.lpclk_sel == BTDM_LPCLK_SEL_RTC_SLOW)
+ {
+ select_src_ret = btdm_lpclk_select_src(BTDM_LPCLK_SEL_RTC_SLOW);
+ set_div_ret = btdm_lpclk_set_div(0);
+ DEBUGASSERT(select_src_ret && set_div_ret);
+ g_btdm_lpcycle_us_frac = RTC_CLK_CAL_FRACT;
+ g_btdm_lpcycle_us = esp32s3_clk_slowclk_cal_get();
+ }
+ else
+ {
+ goto error;
+ }
+
+#if CONFIG_ESP32S3_WIFI_BT_COEXIST
+ coex_update_lpclk_interval();
+#endif
+
+#ifdef CONFIG_PM
+ g_lp_stat.pm_lock_released = 1;
+#endif
+ }
+ while (0);
+
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ coex_init();
+#endif
+
+ esp32s3_periph_module_enable(PERIPH_BT_MODULE);
+ esp32s3_periph_module_reset(PERIPH_BT_MODULE);
+
+ esp32s3_phy_enable();
+ g_lp_stat.phy_enabled = true;
+
+ if (btdm_controller_init(cfg) != 0)
+ {
+ esp32s3_phy_disable();
+ g_lp_stat.phy_enabled = false;
+ return -EIO;
+ }
+
+ coex_pti_v2();
+
+ btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
+
+ return OK;
+
+error:
+
+ esp32s3_bt_controller_deinit_internal ();
+
+ return -ENOMEM;
+}
+
+/****************************************************************************
+ * Name: esp32s3_bt_controller_deinit
+ *
+ * Description:
+ * Deinit BT controller.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. Otherwise, -1 (ERROR) is returned.
+ *
+ ****************************************************************************/
+
+int esp32s3_bt_controller_deinit(void)
+{
+ if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_INITED)
+ {
+ return ERROR;
+ }
+
+ btdm_controller_deinit();
+
+ esp32s3_bt_controller_deinit_internal();
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_bt_controller_deinit_internal
+ *
+ * Description:
+ * Deinit BT internal controller.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void esp32s3_bt_controller_deinit_internal(void)
+{
+ esp32s3_periph_module_disable(PERIPH_BT_MODULE);
+
+ if (g_lp_stat.phy_enabled)
+ {
+ esp32s3_phy_disable();
+ g_lp_stat.phy_enabled = 0;
+ }
+
+ /* deinit low power control resources */
+
+#if CONFIG_MAC_BB_PD
+ if (g_lp_cntl.mac_bb_pd)
+ {
+ btdm_deep_sleep_mem_deinit();
+ g_lp_cntl.mac_bb_pd = 0;
+ }
+#endif
+
+#ifdef CONFIG_PM
+ if (g_lp_cntl.no_light_sleep)
+ {
+ if (g_light_sleep_pm_lock != NULL)
+ {
+ esp_pm_lock_delete(g_light_sleep_pm_lock);
+ g_light_sleep_pm_lock = NULL;
+ }
+ }
+
+ if (g_pm_lock != NULL)
+ {
+ esp_pm_lock_delete(g_pm_lock);
+ g_pm_lock = NULL;
+ g_lp_stat.pm_lock_released = 0;
+ }
+#endif
+
+ if (g_lp_cntl.wakeup_timer_required)
+ {
+ if (g_lp_stat.wakeup_timer_started)
+ {
+ esp_timer_stop(g_btdm_slp_tmr);
+ }
+
+ g_lp_stat.wakeup_timer_started = 0;
+ esp_timer_delete(g_btdm_slp_tmr);
+ g_btdm_slp_tmr = NULL;
+ }
+
+ if (g_lp_cntl.enable)
+ {
+ btdm_vnd_offload_task_deregister(BTDM_VND_OL_SIG_WAKEUP_TMR);
+ if (g_wakeup_req_sem != NULL)
+ {
+ semphr_delete_wrapper(g_wakeup_req_sem);
+ g_wakeup_req_sem = NULL;
+ }
+ }
+
+ if (g_lp_cntl.lpclk_sel == BTDM_LPCLK_SEL_XTAL)
+ {
+#ifdef CONFIG_BT_CTRL_MAIN_XTAL_PU_DURING_LIGHT_SLEEP
+ if (g_lp_cntl.main_xtal_pu)
+ {
+ esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_OFF);
+ g_lp_cntl.main_xtal_pu = 0;
+ }
+#endif
+
+ btdm_lpclk_select_src(BTDM_LPCLK_SEL_RTC_SLOW);
+ btdm_lpclk_set_div(0);
+#if CONFIG_ESP32S3_WIFI_BT_COEXIST
+ coex_update_lpclk_interval();
+#endif
+ }
+
+ g_btdm_lpcycle_us = 0;
+
+#if CONFIG_MAC_BB_PD
+ esp_unregister_mac_bb_pd_callback(btdm_mac_bb_power_down_cb);
+ esp_unregister_mac_bb_pu_callback(btdm_mac_bb_power_up_cb);
+#endif
+
+ esp_bt_power_domain_off();
+#if CONFIG_MAC_BB_PD
+ esp_mac_bb_pd_mem_deinit();
+#endif
+
+ if (osi_funcs_p != NULL)
+ {
+ kmm_free(osi_funcs_p);
+ osi_funcs_p = NULL;
+ }
+
+ btdm_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
+}
+
+/****************************************************************************
+ * Name: esp32s3_bt_controller_disable
+ *
+ * Description:
+ * Disable BT controller.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+int esp32s3_bt_controller_disable(void)
+{
+ if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED)
+ {
+ return ERROR;
+ }
+
+ while (!btdm_power_state_active())
+ {
+ usleep(1000); /* wait */
+ }
+
+ btdm_controller_disable();
+
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ coex_disable();
+#endif
+
+ btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
+
+#ifdef CONFIG_PM
+ /* disable low power mode */
+
+ if (!g_lp_stat.pm_lock_released)
+ {
+ esp32s3_pm_lockrelease();
+ g_lp_stat.pm_lock_released = true;
+ }
+ else
+ {
+ DEBUGPANIC();
+ }
+#endif
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_bt_controller_enable
+ *
+ * Description:
+ * Enable BT controller.
+ *
+ * Input Parameters:
+ * mode - the mode(BLE/BT/BTDM) to enable. For compatible of API, retain
+ * this argument. This mode must be equal as the mode in "cfg" of
+ * esp_bt_controller_init().
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+int esp32s3_bt_controller_enable(esp_bt_mode_t mode)
+{
+ int ret = OK;
+
+ if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_INITED)
+ {
+ return ERROR;
+ }
+
+ if (mode != btdm_controller_get_mode())
+ {
+ wlerr("invalid mode %d, controller support mode is %d",
+ mode, btdm_controller_get_mode());
+ return ERROR;
+ }
+
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ coex_enable();
+#endif
+
+#ifdef CONFIG_PM
+ /* enable low power mode */
+
+ esp32s3_pm_lockacquire();
+ g_lp_stat.pm_lock_released = false;
+#endif
+
+ if (g_lp_cntl.enable)
+ {
+ btdm_controller_enable_sleep(true);
+ }
+
+ if (btdm_controller_enable(mode) != 0)
+ {
+ ret = ERROR;
+ goto error;
+ }
+
+ btdm_controller_status = ESP_BT_CONTROLLER_STATUS_ENABLED;
+
+ return ret;
+
+error:
+
+ /* disable low power mode */
+
+ btdm_controller_enable_sleep(false);
+
+#ifdef CONFIG_PM
+ if (!g_lp_stat.pm_lock_released)
+ {
+ esp32s3_pm_lockrelease();
+ g_lp_stat.pm_lock_released = true;
+ }
+#endif
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_bt_controller_get_status
+ *
+ * Description:
+ * Returns the status of the BT Controller
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * The current status (type esp_bt_controller_status_t)
+ *
+ ****************************************************************************/
+
+esp_bt_controller_status_t esp32s3_bt_controller_get_status(void)
+{
+ return btdm_controller_status;
+}
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wireless.h b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.h
similarity index 57%
copy from arch/xtensa/src/esp32s3/esp32s3_wireless.h
copy to arch/xtensa/src/esp32s3/esp32s3_ble_adapter.h
index 788be93d6b..73c0c82a85 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_wireless.h
+++ b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/xtensa/src/esp32s3/esp32s3_wireless.h
+ * arch/xtensa/src/esp32s3/esp32s3_ble_adapter.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,151 +18,158 @@
*
****************************************************************************/
-#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WIRELESS_H
-#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WIRELESS_H
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_BLE_ADAPTER_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_BLE_ADAPTER_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
+#include <stdint.h>
+#include <stdbool.h>
-#include "xtensa_attr.h"
-
-#include "esp_hal_wifi.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Note: Don't remove these definitions, they are needed by the 3rdparty IDF
- * headers
- */
-
-#define CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN 0
-#define CONFIG_MAC_BB_PD 0
-
-#define MAC_LEN (6)
+#include "esp_bt.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
- * Name: esp_read_mac
+ * Name: esp32s3_bt_controller_init
*
* Description:
- * Read MAC address from efuse
+ * Init BT controller.
*
* Input Parameters:
- * mac - MAC address buffer pointer
- * type - MAC address type
+ * None
*
* Returned Value:
- * 0 if success or -1 if fail
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-int32_t esp_read_mac(uint8_t *mac, esp_mac_type_t type);
+int esp32s3_bt_controller_init(void);
/****************************************************************************
- * Name: esp32s3_phy_enable
+ * Name: esp32s3_bt_controller_deinit
*
* Description:
- * Initialize PHY hardware
+ * Deinit BT controller.
*
* Input Parameters:
* None
*
* Returned Value:
- * None
+ * Zero (OK) is returned on success. Otherwise, -1 (ERROR) is returned.
*
****************************************************************************/
-void esp32s3_phy_enable(void);
+int esp32s3_bt_controller_deinit(void);
/****************************************************************************
- * Name: esp32s3_phy_disable
+ * Name: esp32s3_bt_controller_enable
*
* Description:
- * Deinitialize PHY hardware
+ * Enable BT controller.
*
* Input Parameters:
- * None
+ * mode - the mode(BLE/BT/BTDM) to enable. For compatible of API, retain
+ * this argument. This mode must be equal as the mode in "cfg" of
+ * esp_bt_controller_init().
*
* Returned Value:
- * None
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-void esp32s3_phy_disable(void);
+int esp32s3_bt_controller_enable(esp_bt_mode_t mode);
/****************************************************************************
- * Name: esp32s3_phy_enable_clock
+ * Name: esp32s3_bt_controller_disable
*
* Description:
- * Enable PHY clock
+ * Disable BT controller.
*
* Input Parameters:
* None
*
* Returned Value:
- * None
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-void esp32s3_phy_enable_clock(void);
+int esp32s3_bt_controller_disable(void);
/****************************************************************************
- * Name: esp32s3_phy_disable_clock
+ * Name: esp32s3_bt_controller_enable
*
* Description:
- * Disable PHY clock
+ * Enable BT controller.
*
* Input Parameters:
- * None
+ * mode - the mode(BLE/BT/BTDM) to enable. For compatible of API, retain
+ * this argument. This mode must be equal as the mode in "cfg" of
+ * esp_bt_controller_init().
*
* Returned Value:
- * None
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-void esp32s3_phy_disable_clock(void);
+esp_bt_controller_status_t esp32s3_bt_controller_get_status(void);
/****************************************************************************
- * Functions needed by libphy.a
+ * Name: esp32s3_vhci_host_check_send_available
+ *
+ * Description:
+ * Check if the host can send packet to controller or not.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * bool - true or false
+ *
****************************************************************************/
+bool esp32s3_vhci_host_check_send_available(void);
+
/****************************************************************************
- * Name: esp_dport_access_reg_read
+ * Name: esp32s3_vhci_host_send_packet
*
* Description:
- * Read register value safely in SMP
+ * Host send packet to controller.
*
* Input Parameters:
- * reg - Register address
+ * data - the packet pointer
+ * len - the packet length
*
* Returned Value:
- * Register value
+ * None
*
****************************************************************************/
-uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg);
+void esp32s3_vhci_host_send_packet(uint8_t *data, uint16_t len);
/****************************************************************************
- * Name: phy_printf
+ * Name: esp32s3_vhci_register_callback
*
* Description:
- * Output format string and its arguments
+ * Register the vhci reference callback.
*
* Input Parameters:
- * format - format string
+ * callback - struct defined by vhci_host_callback structure.
*
* Returned Value:
- * 0
+ * status - success or fail
*
****************************************************************************/
-int phy_printf(const char *format, ...) printf_like(1, 2);
+int esp32s3_vhci_register_callback(const esp_vhci_host_callback_t *callback);
-#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WIRELESS_H */
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_BLE_ADAPTER_H */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_irq.c b/arch/xtensa/src/esp32s3/esp32s3_irq.c
index 5303f441aa..278212c61d 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_irq.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_irq.c
@@ -113,6 +113,13 @@
# define ESP32S3_WIFI_RESERVE_INT 0
#endif
+#ifdef CONFIG_ESP32S3_BLE
+# define ESP32S3_BLE_RESERVE_INT ((1 << ESP32S3_CPUINT_BT_BB) | \
+ (1 << ESP32S3_CPUINT_RWBLE))
+#else
+# define ESP32S3_BLE_RESERVE_INT 0
+#endif
+
/****************************************************************************
* Public Data
****************************************************************************/
@@ -159,7 +166,8 @@ static uint32_t g_intenable[CONFIG_SMP_NCPUS];
*/
static uint32_t g_cpu0_freeints = ESP32S3_CPUINT_PERIPHSET &
- ~ESP32S3_WIFI_RESERVE_INT;
+ ~(ESP32S3_WIFI_RESERVE_INT |
+ ESP32S3_BLE_RESERVE_INT);
#ifdef CONFIG_SMP
static uint32_t g_cpu1_freeints = ESP32S3_CPUINT_PERIPHSET;
@@ -409,6 +417,7 @@ static void esp32s3_free_cpuint(int cpuint)
void up_irqinitialize(void)
{
int i;
+
for (i = 0; i < NR_IRQS; i++)
{
g_irqmap[i] = IRQ_UNMAPPED;
@@ -424,6 +433,11 @@ void up_irqinitialize(void)
g_irqmap[ESP32S3_IRQ_MAC] = IRQ_MKMAP(0, ESP32S3_CPUINT_MAC);
#endif
+#ifdef CONFIG_ESP32S3_BLE
+ g_irqmap[ESP32S3_IRQ_BT_BB] = IRQ_MKMAP(0, ESP32S3_CPUINT_BT_BB);
+ g_irqmap[ESP32S3_IRQ_RWBLE] = IRQ_MKMAP(0, ESP32S3_CPUINT_RWBLE);
+#endif
+
/* Initialize CPU interrupts */
esp32s3_cpuint_initialize();
@@ -435,6 +449,13 @@ void up_irqinitialize(void)
xtensa_enable_cpuint(&g_intenable[0], 1 << ESP32S3_CPUINT_MAC);
#endif
+#ifdef CONFIG_ESP32S3_BLE
+ g_cpu0_intmap[ESP32S3_CPUINT_BT_BB] = CPUINT_ASSIGN(ESP32S3_IRQ_BT_BB);
+ g_cpu0_intmap[ESP32S3_CPUINT_RWBLE] = CPUINT_ASSIGN(ESP32S3_IRQ_RWBLE);
+ xtensa_enable_cpuint(&g_intenable[0], 1 << ESP32S3_CPUINT_BT_BB);
+ xtensa_enable_cpuint(&g_intenable[0], 1 << ESP32S3_CPUINT_RWBLE);
+#endif
+
#ifdef CONFIG_SMP
/* Attach and enable the inter-CPU interrupt */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
index 4b751372a2..ccddf73815 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
@@ -543,7 +543,7 @@ static inline int32_t osi_errno_trans(int ret)
}
/****************************************************************************
- * Name: osi_errno_trans
+ * Name: wifi_errno_trans
*
* Description:
* Transform from ESP Wi-Fi error code to NuttX error code
@@ -4035,137 +4035,6 @@ int esp_mesh_send_event_internal(int32_t event_id,
* Functions needed by libwpa_supplicant.a
****************************************************************************/
-/****************************************************************************
- * Name: esp_timer_create
- *
- * Description:
- * Create timer with given arguments
- *
- * Input Parameters:
- * create_args - Timer arguments data pointer
- * out_handle - Timer handle pointer
- *
- * Returned Value:
- * 0 if success or -1 if fail
- *
- ****************************************************************************/
-
-int32_t esp_timer_create(const esp_timer_create_args_t *create_args,
- esp_timer_handle_t *out_handle)
-{
- int ret;
- struct rt_timer_args_s rt_timer_args;
- struct rt_timer_s *rt_timer;
-
- rt_timer_args.arg = create_args->arg;
- rt_timer_args.callback = create_args->callback;
-
- ret = esp32s3_rt_timer_create(&rt_timer_args, &rt_timer);
- if (ret)
- {
- wlerr("Failed to create rt_timer error=%d\n", ret);
- return ret;
- }
-
- *out_handle = (esp_timer_handle_t)rt_timer;
-
- return 0;
-}
-
-/****************************************************************************
- * Name: esp_timer_start_once
- *
- * Description:
- * Start timer with one shot mode
- *
- * Input Parameters:
- * timer - Timer handle pointer
- * timeout_us - Timeout value by micro second
- *
- * Returned Value:
- * 0 if success or -1 if fail
- *
- ****************************************************************************/
-
-int32_t esp_timer_start_once(esp_timer_handle_t timer, uint64_t timeout_us)
-{
- struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
-
- esp32s3_rt_timer_start(rt_timer, timeout_us, false);
-
- return 0;
-}
-
-/****************************************************************************
- * Name: esp_timer_start_periodic
- *
- * Description:
- * Start timer with periodic mode
- *
- * Input Parameters:
- * timer - Timer handle pointer
- * period - Timeout value by micro second
- *
- * Returned Value:
- * 0 if success or -1 if fail
- *
- ****************************************************************************/
-
-int32_t esp_timer_start_periodic(esp_timer_handle_t timer, uint64_t period)
-{
- struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
-
- esp32s3_rt_timer_start(rt_timer, period, true);
-
- return 0;
-}
-
-/****************************************************************************
- * Name: esp_timer_stop
- *
- * Description:
- * Stop timer
- *
- * Input Parameters:
- * timer - Timer handle pointer
- *
- * Returned Value:
- * 0 if success or -1 if fail
- *
- ****************************************************************************/
-
-int32_t esp_timer_stop(esp_timer_handle_t timer)
-{
- struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
-
- esp32s3_rt_timer_stop(rt_timer);
-
- return 0;
-}
-
-/****************************************************************************
- * Name: esp_timer_delete
- *
- * Description:
- * Delete timer and free resource
- *
- * Input Parameters:
- * timer - Timer handle pointer
- *
- * Returned Value:
- * 0 if success or -1 if fail
- *
- ****************************************************************************/
-
-int32_t esp_timer_delete(esp_timer_handle_t timer)
-{
- struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
-
- esp32s3_rt_timer_delete(rt_timer);
-
- return 0;
-}
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -6478,6 +6347,29 @@ int esp_wifi_softap_rssi(struct iwreq *iwr, bool set)
#endif /* ESP32S3_WLAN_HAS_SOFTAP */
+/****************************************************************************
+ * Name: esp32s3_wifi_bt_coexist_init
+ *
+ * Description:
+ * Initialize ESP32-S3 Wi-Fi and BT coexistance module.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * OK on success (positive non-zero values are cmd-specific)
+ * Negated errno returned on failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+int esp32s3_wifi_bt_coexist_init(void)
+{
+#error "BT and WiFi coexst not implemented!!!"
+ return ERROR;
+}
+#endif
+
/****************************************************************************
* Name: esp_wifi_stop_callback
*
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h
index d983419f20..c80ba8cbd6 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h
+++ b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h
@@ -824,6 +824,25 @@ int esp_wifi_softap_country(struct iwreq *iwr, bool set);
int esp_wifi_softap_rssi(struct iwreq *iwr, bool set);
#endif /* ESP32S3_WLAN_HAS_SOFTAP */
+/****************************************************************************
+ * Name: esp32s3_wifi_bt_coexist_init
+ *
+ * Description:
+ * Initialize ESP32-C3 Wi-Fi and BT coexistance module.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * OK on success (positive non-zero values are cmd-specific)
+ * Negated errno returned on failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+int esp32s3_wifi_bt_coexist_init(void);
+#endif
+
/****************************************************************************
* Name: esp_wifi_stop_callback
*
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wireless.c b/arch/xtensa/src/esp32s3/esp32s3_wireless.c
index 0208fd58cd..58d4eada21 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_wireless.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_wireless.c
@@ -29,13 +29,17 @@
#include <assert.h>
#include "xtensa.h"
+#include "hardware/esp32s3_rtccntl.h"
#include "hardware/esp32s3_soc.h"
#include "hardware/esp32s3_syscon.h"
#include "hardware/esp32s3_efuse.h"
-#include "esp32s3_wireless.h"
+#include "esp32s3_periph.h"
+
#include "esp_phy_init.h"
#include "phy_init_data.h"
+#include "esp32s3_wireless.h"
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -54,6 +58,7 @@ static inline void phy_digital_regs_load(void);
* Extern Functions declaration
****************************************************************************/
+extern void coex_pti_v2(void);
extern uint8_t esp_crc8(const uint8_t *p, uint32_t len);
extern void phy_wakeup_init(void);
extern void phy_close_rf(void);
@@ -82,6 +87,10 @@ static uint32_t *g_phy_digital_regs_mem = NULL;
static bool g_is_phy_calibrated = false;
+/* Reference count of power on of wifi and bt power domain */
+
+static uint8_t g_wifi_bt_pd_controller;
+
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -191,21 +200,9 @@ int phy_printf(const char *format, ...)
*
****************************************************************************/
-void esp32s3_phy_enable_clock(void)
+void IRAM_ATTR esp32s3_phy_enable_clock(void)
{
- irqstate_t flags;
-
- flags = enter_critical_section();
-
- if (g_phy_clk_en_cnt == 0)
- {
- modifyreg32(SYSTEM_WIFI_CLK_EN_REG, 0,
- SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M);
- }
-
- g_phy_clk_en_cnt++;
-
- leave_critical_section(flags);
+ esp32s3_periph_wifi_bt_common_module_enable();
}
/****************************************************************************
@@ -222,24 +219,9 @@ void esp32s3_phy_enable_clock(void)
*
****************************************************************************/
-void esp32s3_phy_disable_clock(void)
+void IRAM_ATTR esp32s3_phy_disable_clock(void)
{
- irqstate_t flags;
-
- flags = enter_critical_section();
-
- if (g_phy_clk_en_cnt > 0)
- {
- g_phy_clk_en_cnt--;
- if (g_phy_clk_en_cnt == 0)
- {
- modifyreg32(SYSTEM_WIFI_CLK_EN_REG,
- SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M,
- 0);
- }
- }
-
- leave_critical_section(flags);
+ esp32s3_periph_wifi_bt_common_module_disable();
}
/****************************************************************************
@@ -348,6 +330,8 @@ void esp32s3_phy_disable(void)
if (g_phy_access_ref == 0)
{
+ phy_digital_regs_store();
+
/* Disable PHY and RF. */
phy_close_rf();
@@ -385,6 +369,7 @@ void esp32s3_phy_enable(void)
static bool debug = false;
irqstate_t flags;
esp_phy_calibration_data_t *cal_data;
+
if (debug == false)
{
char *phy_version = get_phy_version_str();
@@ -392,13 +377,6 @@ void esp32s3_phy_enable(void)
debug = true;
}
- cal_data = kmm_zalloc(sizeof(esp_phy_calibration_data_t));
- if (!cal_data)
- {
- wlerr("ERROR: Failed to allocate PHY calibration data buffer.");
- abort();
- }
-
flags = enter_critical_section();
if (g_phy_access_ref == 0)
@@ -407,12 +385,21 @@ void esp32s3_phy_enable(void)
if (g_is_phy_calibrated == false)
{
+ cal_data = kmm_zalloc(sizeof(esp_phy_calibration_data_t));
+ if (cal_data == NULL)
+ {
+ wlerr("ERROR: Failed to allocate PHY"
+ "calibration data buffer.");
+ abort();
+ }
+
#if CONFIG_ESP_PHY_ENABLE_USB
phy_bbpll_en_usb(true);
#endif
wlinfo("calibrating");
register_chipv7_phy(&phy_init_data, cal_data, PHY_RF_CAL_FULL);
g_is_phy_calibrated = true;
+ kmm_free(cal_data);
}
else
{
@@ -422,6 +409,199 @@ void esp32s3_phy_enable(void)
}
g_phy_access_ref++;
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: esp_wifi_bt_power_domain_on
+ *
+ * Description:
+ * Initialize Bluetooth and Wi-Fi power domain
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR esp_wifi_bt_power_domain_on(void)
+{
+ irqstate_t flags;
+
+ flags = enter_critical_section();
+
+ if (g_wifi_bt_pd_controller++ == 0)
+ {
+ modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD, 0);
+
+ modifyreg32(SYSCON_WIFI_RST_EN_REG, 0, MODEM_RESET_FIELD_WHEN_PU);
+ modifyreg32(SYSCON_WIFI_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU, 0);
+
+ modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO, 0);
+ }
+
leave_critical_section(flags);
- kmm_free(cal_data);
+}
+
+/****************************************************************************
+ * Name: esp_wifi_bt_power_domain_off
+ *
+ * Description:
+ * Deinitialize Bluetooth and Wi-Fi power domain
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp_wifi_bt_power_domain_off(void)
+{
+ irqstate_t flags;
+
+ flags = enter_critical_section();
+
+ if (--g_wifi_bt_pd_controller == 0)
+ {
+ modifyreg32(RTC_CNTL_DIG_ISO_REG, 0, RTC_CNTL_WIFI_FORCE_ISO);
+ modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_WIFI_FORCE_PD);
+ }
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: esp_timer_create
+ *
+ * Description:
+ * Create timer with given arguments
+ *
+ * Input Parameters:
+ * create_args - Timer arguments data pointer
+ * out_handle - Timer handle pointer
+ *
+ * Returned Value:
+ * 0 if success or -1 if fail
+ *
+ ****************************************************************************/
+
+int32_t esp_timer_create(const esp_timer_create_args_t *create_args,
+ esp_timer_handle_t *out_handle)
+{
+ int ret;
+ struct rt_timer_args_s rt_timer_args;
+ struct rt_timer_s *rt_timer;
+
+ rt_timer_args.arg = create_args->arg;
+ rt_timer_args.callback = create_args->callback;
+
+ ret = esp32s3_rt_timer_create(&rt_timer_args, &rt_timer);
+ if (ret)
+ {
+ wlerr("Failed to create rt_timer error=%d\n", ret);
+ return ret;
+ }
+
+ *out_handle = (esp_timer_handle_t)rt_timer;
+
+ return 0;
+}
+
+/****************************************************************************
+ * Name: esp_timer_start_once
+ *
+ * Description:
+ * Start timer with one shot mode
+ *
+ * Input Parameters:
+ * timer - Timer handle pointer
+ * timeout_us - Timeout value by micro second
+ *
+ * Returned Value:
+ * 0 if success or -1 if fail
+ *
+ ****************************************************************************/
+
+int32_t esp_timer_start_once(esp_timer_handle_t timer, uint64_t timeout_us)
+{
+ struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
+
+ esp32s3_rt_timer_start(rt_timer, timeout_us, false);
+
+ return 0;
+}
+
+/****************************************************************************
+ * Name: esp_timer_start_periodic
+ *
+ * Description:
+ * Start timer with periodic mode
+ *
+ * Input Parameters:
+ * timer - Timer handle pointer
+ * period - Timeout value by micro second
+ *
+ * Returned Value:
+ * 0 if success or -1 if fail
+ *
+ ****************************************************************************/
+
+int32_t esp_timer_start_periodic(esp_timer_handle_t timer, uint64_t period)
+{
+ struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
+
+ esp32s3_rt_timer_start(rt_timer, period, true);
+
+ return 0;
+}
+
+/****************************************************************************
+ * Name: esp_timer_stop
+ *
+ * Description:
+ * Stop timer
+ *
+ * Input Parameters:
+ * timer - Timer handle pointer
+ *
+ * Returned Value:
+ * 0 if success or -1 if fail
+ *
+ ****************************************************************************/
+
+int32_t esp_timer_stop(esp_timer_handle_t timer)
+{
+ struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
+
+ esp32s3_rt_timer_stop(rt_timer);
+
+ return 0;
+}
+
+/****************************************************************************
+ * Name: esp_timer_delete
+ *
+ * Description:
+ * Delete timer and free resource
+ *
+ * Input Parameters:
+ * timer - Timer handle pointer
+ *
+ * Returned Value:
+ * 0 if success or -1 if fail
+ *
+ ****************************************************************************/
+
+int32_t esp_timer_delete(esp_timer_handle_t timer)
+{
+ struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
+
+ esp32s3_rt_timer_delete(rt_timer);
+
+ return 0;
}
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wireless.h b/arch/xtensa/src/esp32s3/esp32s3_wireless.h
index 788be93d6b..4125b88f49 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_wireless.h
+++ b/arch/xtensa/src/esp32s3/esp32s3_wireless.h
@@ -28,6 +28,7 @@
#include <nuttx/config.h>
#include "xtensa_attr.h"
+#include "esp32s3_rt_timer.h"
#include "esp_hal_wifi.h"
@@ -95,7 +96,7 @@ void esp32s3_phy_enable(void);
*
****************************************************************************/
-void esp32s3_phy_disable(void);
+void IRAM_ATTR esp32s3_phy_disable(void);
/****************************************************************************
* Name: esp32s3_phy_enable_clock
@@ -111,7 +112,7 @@ void esp32s3_phy_disable(void);
*
****************************************************************************/
-void esp32s3_phy_enable_clock(void);
+void IRAM_ATTR esp32s3_phy_enable_clock(void);
/****************************************************************************
* Name: esp32s3_phy_disable_clock
@@ -165,4 +166,104 @@ uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg);
int phy_printf(const char *format, ...) printf_like(1, 2);
+/****************************************************************************
+ * Name: esp_wifi_bt_power_domain_on
+ *
+ * Description:
+ * Initialize Bluetooth and Wi-Fi power domain
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR esp_wifi_bt_power_domain_on(void);
+
+/****************************************************************************
+ * Name: esp_timer_create
+ *
+ * Description:
+ * Create timer with given arguments
+ *
+ * Input Parameters:
+ * create_args - Timer arguments data pointer
+ * out_handle - Timer handle pointer
+ *
+ * Returned Value:
+ * 0 if success or -1 if fail
+ *
+ ****************************************************************************/
+
+int32_t esp_timer_create(const esp_timer_create_args_t *create_args,
+ esp_timer_handle_t *out_handle);
+
+/****************************************************************************
+ * Name: esp_timer_start_once
+ *
+ * Description:
+ * Start timer with one shot mode
+ *
+ * Input Parameters:
+ * timer - Timer handle pointer
+ * timeout_us - Timeout value by micro second
+ *
+ * Returned Value:
+ * 0 if success or -1 if fail
+ *
+ ****************************************************************************/
+
+int32_t esp_timer_start_once(esp_timer_handle_t timer, uint64_t timeout_us);
+
+/****************************************************************************
+ * Name: esp_timer_start_periodic
+ *
+ * Description:
+ * Start timer with periodic mode
+ *
+ * Input Parameters:
+ * timer - Timer handle pointer
+ * period - Timeout value by micro second
+ *
+ * Returned Value:
+ * 0 if success or -1 if fail
+ *
+ ****************************************************************************/
+
+int32_t esp_timer_start_periodic(esp_timer_handle_t timer, uint64_t period);
+
+/****************************************************************************
+ * Name: esp_timer_stop
+ *
+ * Description:
+ * Stop timer
+ *
+ * Input Parameters:
+ * timer - Timer handle pointer
+ *
+ * Returned Value:
+ * 0 if success or -1 if fail
+ *
+ ****************************************************************************/
+
+int32_t esp_timer_stop(esp_timer_handle_t timer);
+
+/****************************************************************************
+ * Name: esp_timer_delete
+ *
+ * Description:
+ * Delete timer and free resource
+ *
+ * Input Parameters:
+ * timer - Timer handle pointer
+ *
+ * Returned Value:
+ * 0 if success or -1 if fail
+ *
+ ****************************************************************************/
+
+int32_t esp_timer_delete(esp_timer_handle_t timer);
+
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WIRELESS_H */
diff --git a/boards/xtensa/esp32s3/common/scripts/esp32s3_aliases.ld b/boards/xtensa/esp32s3/common/scripts/esp32s3_aliases.ld
new file mode 100644
index 0000000000..fa3c4e8118
--- /dev/null
+++ b/boards/xtensa/esp32s3/common/scripts/esp32s3_aliases.ld
@@ -0,0 +1,29 @@
+/****************************************************************************
+ * boards/xtensa/esp32s3/common/scripts/esp32s3_aliases.ld
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Bluetooth needs symbol alias, to be removed after IDF rename it */
+
+#ifdef CONFIG_ESP32S3_BLE
+ api_vhci_host_check_send_available = API_vhci_host_check_send_available;
+ api_vhci_host_send_packet = API_vhci_host_send_packet;
+ api_vhci_host_register_callback = API_vhci_host_register_callback;
+#endif
diff --git a/boards/xtensa/esp32s3/common/scripts/esp32s3_rom.ld b/boards/xtensa/esp32s3/common/scripts/esp32s3_rom.ld
index 358e552f3d..263b9c8874 100644
--- a/boards/xtensa/esp32s3/common/scripts/esp32s3_rom.ld
+++ b/boards/xtensa/esp32s3/common/scripts/esp32s3_rom.ld
@@ -398,13 +398,13 @@ PROVIDE( Cache_Invalidate_DCache_Items = 0x40001680 );
PROVIDE( Cache_Clean_Items = 0x4000168c );
PROVIDE( Cache_WriteBack_Items = 0x40001698 );
PROVIDE( Cache_Op_Addr = 0x400016a4 );
-PROVIDE( cache_invalidate_addr = 0x400016b0 );
+PROVIDE( Cache_Invalidate_Addr = 0x400016b0 );
PROVIDE( Cache_Clean_Addr = 0x400016bc );
PROVIDE( Cache_WriteBack_Addr = 0x400016c8 );
-PROVIDE( cache_invalidate_icache_all = 0x400016d4 );
-PROVIDE( cache_invalidate_dcache_all = 0x400016e0 );
+PROVIDE( Cache_Invalidate_ICache_All = 0x400016d4 );
+PROVIDE( Cache_Invalidate_DCache_All = 0x400016e0 );
PROVIDE( Cache_Clean_All = 0x400016ec );
-PROVIDE( cache_writeback_all = 0x400016f8 );
+PROVIDE( Cache_WriteBack_All = 0x400016f8 );
PROVIDE( Cache_Mask_All = 0x40001704 );
PROVIDE( Cache_UnMask_Dram0 = 0x40001710 );
PROVIDE( Cache_Suspend_ICache_Autoload = 0x4000171c );
@@ -439,30 +439,30 @@ PROVIDE( Cache_Disable_ICache = 0x4000186c );
PROVIDE( Cache_Enable_ICache = 0x40001878 );
PROVIDE( Cache_Disable_DCache = 0x40001884 );
PROVIDE( Cache_Enable_DCache = 0x40001890 );
-PROVIDE( cache_suspend_icache = 0x4000189c );
-PROVIDE( cache_resume_icache = 0x400018a8 );
-PROVIDE( cache_suspend_dcache = 0x400018b4 );
-PROVIDE( cache_resume_dcache = 0x400018c0 );
+PROVIDE( Cache_Suspend_ICache = 0x4000189c );
+PROVIDE( Cache_Resume_ICache = 0x400018a8 );
+PROVIDE( Cache_Suspend_DCache = 0x400018b4 );
+PROVIDE( Cache_Resume_DCache = 0x400018c0 );
PROVIDE( Cache_Occupy_Items = 0x400018cc );
-PROVIDE( cache_occupy_addr = 0x400018d8 );
+PROVIDE( Cache_Occupy_Addr = 0x400018d8 );
PROVIDE( Cache_Freeze_ICache_Enable = 0x400018e4 );
PROVIDE( Cache_Freeze_ICache_Disable = 0x400018f0 );
PROVIDE( Cache_Freeze_DCache_Enable = 0x400018fc );
PROVIDE( Cache_Freeze_DCache_Disable = 0x40001908 );
-PROVIDE( cache_set_idrom_mmu_size = 0x40001914 );
+PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40001914 );
PROVIDE( flash2spiram_instruction_offset = 0x40001920 );
PROVIDE( flash2spiram_rodata_offset = 0x4000192c );
PROVIDE( flash_instr_rodata_start_page = 0x40001938 );
PROVIDE( flash_instr_rodata_end_page = 0x40001944 );
-PROVIDE( cache_set_idrom_mmu_info = 0x40001950 );
+PROVIDE( Cache_Set_IDROM_MMU_Info = 0x40001950 );
PROVIDE( Cache_Get_IROM_MMU_End = 0x4000195c );
PROVIDE( Cache_Get_DROM_MMU_End = 0x40001968 );
PROVIDE( Cache_Owner_Init = 0x40001974 );
PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40001980 );
PROVIDE( Cache_Occupy_DCache_MEMORY = 0x4000198c );
PROVIDE( Cache_MMU_Init = 0x40001998 );
-PROVIDE( cache_ibus_mmu_set = 0x400019a4 );
-PROVIDE( cache_dbus_mmu_set = 0x400019b0 );
+PROVIDE( Cache_Ibus_MMU_Set = 0x400019a4 );
+PROVIDE( Cache_Dbus_MMU_Set = 0x400019b0 );
PROVIDE( Cache_Count_Flash_Pages = 0x400019bc );
PROVIDE( Cache_Flash_To_SPIRAM_Copy = 0x400019c8 );
PROVIDE( Cache_Travel_Tag_Memory = 0x400019d4 );
@@ -626,7 +626,8 @@ ets_efuse_get_flash_delay_us = 0x40001f5c;
ets_efuse_get_mac = 0x40001f68;
ets_efuse_get_spiconfig = 0x40001f74;
ets_efuse_usb_print_is_disabled = 0x40001f80;
-ets_efuse_get_uart_print_channel = 0x40001f8c;
+/*ets_efuse_get_uart_print_channel = 0x40001f8c;*/
+ets_efuse_usb_serial_jtag_print_is_disabled = 0x40001f8c;
ets_efuse_get_uart_print_control = 0x40001f98;
ets_efuse_get_wp_pad = 0x40001fa4;
ets_efuse_legacy_spi_boot_mode_disabled = 0x40001fb0;
@@ -983,10 +984,14 @@ r_ble_util_data_rx_buf_reset = 0x40003288;
r_bt_bb_get_intr_mask = 0x40003294;
r_bt_bb_intr_clear = 0x400032a0;
r_bt_bb_intr_mask_set = 0x400032ac;
+/*
r_bt_bb_isr = 0x400032b8;
+*/
r_bt_rf_coex_cfg_set = 0x400032c4;
r_bt_rf_coex_conn_dynamic_pti_en_get = 0x400032d0;
+/*
r_bt_rf_coex_conn_phy_coded_data_time_limit_en_get = 0x400032dc;
+*/
r_bt_rf_coex_ext_adv_dynamic_pti_en_get = 0x400032e8;
r_bt_rf_coex_ext_scan_dynamic_pti_en_get = 0x400032f4;
r_bt_rf_coex_legacy_adv_dynamic_pti_en_get = 0x40003300;
@@ -1008,14 +1013,18 @@ r_bt_rtp_apply_rule_cs_fmt = 0x400033b4;
r_bt_rtp_apply_rule_cs_idx = 0x400033c0;
r_bt_rtp_deregister_rule_cs_fmt = 0x400033cc;
r_bt_rtp_deregister_rule_cs_idx = 0x400033d8;
+/*
r_bt_rtp_get_txpwr_idx_by_act = 0x400033e4;
+*/
r_bt_rtp_init = 0x400033f0;
r_bt_rtp_register_rule_cs_fmt = 0x400033fc;
r_bt_rtp_register_rule_cs_idx = 0x40003408;
r_btdm_isr = 0x40003414;
+/*
r_btdm_task_post = 0x40003420;
r_btdm_task_post_from_isr = 0x4000342c;
r_btdm_task_recycle = 0x40003438;
+*/
r_cali_phase_match_p = 0x40003444;
r_cmp_abs_time = 0x40003450;
r_cmp_dest_id = 0x4000345c;
@@ -1111,7 +1120,9 @@ r_hci_look_for_evt_desc = 0x40003888;
r_hci_look_for_le_evt_desc = 0x40003894;
r_hci_look_for_le_evt_desc_esp = 0x400038a0;
r_hci_pack_bytes = 0x400038ac;
+/*
r_hci_register_vendor_desc_tab = 0x400038b8;
+*/
r_hci_send_2_controller = 0x400038c4;
r_hci_send_2_host = 0x400038d0;
r_hci_tl_c2h_data_flow_on = 0x400038dc;
@@ -1168,7 +1179,9 @@ r_ke_task_handler_get = 0x40003b34;
r_ke_task_init = 0x40003b40;
r_ke_task_msg_flush = 0x40003b4c;
r_ke_task_saved_update = 0x40003b58;
+/*
r_ke_task_schedule = 0x40003b64;
+*/
r_ke_time = 0x40003b70;
r_ke_time_cmp = 0x40003b7c;
r_ke_time_past = 0x40003b88;
@@ -1196,7 +1209,9 @@ r_llc_dl_chg_check = 0x40003c84;
r_llc_dle_proc_err_cb = 0x40003c90;
r_llc_feats_exch_proc_err_cb = 0x40003c9c;
r_llc_hci_cmd_handler_tab_p_get = 0x40003ca8;
+/*
r_llc_hci_command_handler = 0x40003cb4;
+*/
r_llc_hci_con_param_req_evt_send = 0x40003cc0;
r_llc_hci_con_upd_info_send = 0x40003ccc;
r_llc_hci_disconnected_dis = 0x40003cd8;
@@ -1224,7 +1239,9 @@ r_llc_llcp_state_set = 0x40003dd4;
r_llc_llcp_trans_timer_set = 0x40003de0;
r_llc_llcp_tx_check = 0x40003dec;
r_llc_loc_ch_map_proc_continue = 0x40003df8;
+/*
r_llc_loc_con_upd_proc_continue = 0x40003e04;
+*/
r_llc_loc_con_upd_proc_err_cb = 0x40003e10;
r_llc_loc_dl_upd_proc_continue = 0x40003e1c;
r_llc_loc_encrypt_proc_continue = 0x40003e28;
@@ -1245,7 +1262,9 @@ r_llc_proc_timer_pause_set = 0x40003ed0;
r_llc_proc_timer_set = 0x40003edc;
r_llc_proc_unreg = 0x40003ee8;
r_llc_rem_ch_map_proc_continue = 0x40003ef4;
+/*
r_llc_rem_con_upd_proc_continue = 0x40003f00;
+*/
r_llc_rem_con_upd_proc_err_cb = 0x40003f0c;
r_llc_rem_dl_upd_proc = 0x40003f18;
r_llc_rem_encrypt_proc_continue = 0x40003f24;
@@ -1334,10 +1353,14 @@ r_lld_con_rx_isr = 0x400042fc;
r_lld_con_rx_link_info_check = 0x40004308;
r_lld_con_rx_llcp_check = 0x40004314;
r_lld_con_rx_sync_time_update = 0x40004320;
+/*
r_lld_con_sched = 0x4000432c;
+*/
r_lld_con_set_tx_power = 0x40004338;
r_lld_con_start = 0x40004344;
+/*
r_lld_con_stop = 0x40004350;
+*/
r_lld_con_tx = 0x4000435c;
r_lld_con_tx_enc = 0x40004368;
r_lld_con_tx_isr = 0x40004374;
@@ -1372,7 +1395,9 @@ r_lld_init_set_tx_power = 0x400044c4;
r_lld_init_start = 0x400044d0;
r_lld_init_stop = 0x400044dc;
r_lld_instant_proc_end = 0x400044e8;
+/*
r_lld_llcp_rx_ind_handler = 0x400044f4;
+*/
r_lld_per_adv_ch_map_update = 0x40004500;
r_lld_per_adv_chain_construct = 0x4000450c;
r_lld_per_adv_cleanup = 0x40004518;
@@ -1390,7 +1415,9 @@ r_lld_per_adv_init = 0x4000459c;
r_lld_per_adv_init_info_get = 0x400045a8;
r_lld_per_adv_list_add = 0x400045b4;
r_lld_per_adv_list_rem = 0x400045c0;
+/*
r_lld_per_adv_sched = 0x400045cc;
+*/
r_lld_per_adv_set_tx_power = 0x400045d8;
r_lld_per_adv_start = 0x400045e4;
r_lld_per_adv_stop = 0x400045f0;
@@ -1424,8 +1451,10 @@ r_lld_scan_frm_rx_isr = 0x40004734;
r_lld_scan_frm_skip_isr = 0x40004740;
r_lld_scan_init = 0x4000474c;
r_lld_scan_params_update = 0x40004758;
+/*
r_lld_scan_process_pkt_rx = 0x40004764;
r_lld_scan_process_pkt_rx_adv_rep = 0x40004770;
+*/
r_lld_scan_process_pkt_rx_aux_adv_ind = 0x4000477c;
r_lld_scan_process_pkt_rx_aux_chain_ind = 0x40004788;
r_lld_scan_process_pkt_rx_aux_scan_rsp = 0x40004794;
@@ -1500,7 +1529,9 @@ r_llm_is_dev_synced = 0x40004ac4;
r_llm_is_non_con_act_ongoing_check = 0x40004ad0;
r_llm_is_wl_accessible = 0x40004adc;
r_llm_le_evt_mask_check = 0x40004ae8;
+/*
r_llm_le_features_get = 0x40004af4;
+*/
r_llm_link_disc = 0x40004b00;
r_llm_master_ch_map_get = 0x40004b0c;
r_llm_msg_handler_tab_p_get = 0x40004b18;
@@ -1520,7 +1551,9 @@ r_misc_msg_handler_tab_p_get = 0x40004bb4;
r_notEqual256 = 0x40004bc0;
r_phy_upd_proc_start = 0x40004bcc;
r_platform_reset = 0x40004bd8;
+/*
r_register_esp_vendor_cmd_handler = 0x40004be4;
+*/
r_rf_em_init = 0x40004bf0;
r_rf_force_agc_enable = 0x40004bfc;
r_rf_reg_rd = 0x40004c08;
@@ -1530,8 +1563,10 @@ r_rf_rssi_convert = 0x40004c2c;
r_rf_rw_v9_le_disable = 0x40004c38;
r_rf_rw_v9_le_enable = 0x40004c44;
r_rf_sleep = 0x40004c50;
+/*
r_rf_txpwr_cs_get = 0x40004c5c;
r_rf_txpwr_dbm_get = 0x40004c68;
+*/
r_rf_util_cs_fmt_convert = 0x40004c74;
r_rw_crypto_aes_ccm = 0x40004c80;
r_rw_crypto_aes_encrypt = 0x40004c8c;
@@ -1545,7 +1580,9 @@ r_rw_crypto_aes_result_handler = 0x40004ce0;
r_rw_crypto_aes_s1 = 0x40004cec;
r_rw_cryto_aes_cmac = 0x40004cf8;
r_rw_v9_init_em_radio_table = 0x40004d04;
+/*
r_rwble_isr = 0x40004d10;
+*/
r_rwble_sleep_enter = 0x40004d1c;
r_rwble_sleep_wakeup_end = 0x40004d28;
r_rwbtdm_isr_wrapper = 0x40004d34;
@@ -1582,7 +1619,9 @@ r_sch_alarm_set = 0x40004e9c;
r_sch_alarm_timer_isr = 0x40004ea8;
r_sch_arb_conflict_check = 0x40004eb4;
r_sch_arb_elt_cancel = 0x40004ec0;
+/*
r_sch_arb_event_start_isr = 0x40004ecc;
+*/
r_sch_arb_init = 0x40004ed8;
r_sch_arb_insert = 0x40004ee4;
r_sch_arb_prog_timer = 0x40004ef0;
@@ -1597,8 +1636,10 @@ r_sch_plan_offset_req = 0x40004f50;
r_sch_plan_position_range_compute = 0x40004f5c;
r_sch_plan_rem = 0x40004f68;
r_sch_plan_req = 0x40004f74;
+/*
r_sch_plan_set = 0x40004f80;
r_sch_prog_end_isr = 0x40004f8c;
+*/
r_sch_prog_init = 0x40004f98;
r_sch_prog_push = 0x40004fa4;
r_sch_prog_rx_isr = 0x40004fb0;
@@ -1634,16 +1675,22 @@ r_lld_ext_adv_dynamic_pti_get = 0x4000510c;
r_lld_ext_adv_dynamic_aux_pti_process = 0x40005118;
r_lld_ext_adv_dynamic_pti_process = 0x40005124;
r_lld_adv_ext_pkt_prepare_set = 0x40005130;
+/*
r_lld_adv_ext_chain_none_construct = 0x4000513c;
+*/
r_lld_adv_ext_chain_connectable_construct = 0x40005148;
+/*
r_lld_adv_ext_chain_scannable_construct = 0x40005154;
+*/
r_lld_adv_pkt_rx_connect_post = 0x40005160;
r_lld_adv_start_init_evt_param = 0x4000516c;
r_lld_adv_start_set_cs = 0x40005178;
r_lld_adv_start_update_filter_policy = 0x40005184;
r_lld_adv_start_schedule_asap = 0x40005190;
r_lld_con_tx_prog_new_packet_coex = 0x4000519c;
+/*
r_lld_con_tx_prog_new_packet = 0x400051a8;
+*/
r_lld_per_adv_dynamic_pti_get = 0x400051b4;
r_lld_per_adv_evt_start_chm_upd = 0x400051c0;
r_lld_ext_scan_dynamic_pti_get = 0x400051cc;
@@ -1800,6 +1847,50 @@ rwip_coex_cfg = 0x3ff1eebe;
rwip_priority = 0x3ff1eea8;
veryBigHexP256 = 0x3ff1ee5c;
+/* bluetooth hook funcs */
+r_llc_loc_encrypt_proc_continue_hook = 0x40001c60;
+r_llc_loc_phy_upd_proc_continue_hook = 0x40001c64;
+r_llc_rem_phy_upd_proc_continue_hook = 0x40001c68;
+r_lld_scan_frm_eof_isr_hook = 0x40001c6c;
+r_lld_scan_evt_start_cbk_hook = 0x40001c70;
+/*
+r_lld_scan_start_hook = 0x40001c74;
+*/
+r_lld_scan_process_pkt_rx_ext_adv_hook = 0x40001c78;
+r_lld_scan_sched_hook = 0x40001c7c;
+/*
+r_lld_adv_start_hook = 0x40001c80;
+*/
+r_lld_adv_evt_start_cbk_hook = 0x40001c84;
+r_lld_adv_aux_evt_start_cbk_hook = 0x40001c88;
+r_lld_adv_frm_isr_hook = 0x40001c8c;
+r_lld_adv_start_init_evt_param_hook = 0x40001c90;
+r_lld_con_evt_canceled_cbk_hook = 0x40001c94;
+r_lld_con_frm_isr_hook = 0x40001c98;
+r_lld_con_tx_hook = 0x40001c9c;
+r_lld_con_rx_hook = 0x40001ca0;
+r_lld_con_evt_start_cbk_hook = 0x40001ca4;
+/*
+r_lld_con_start_hook = 0x40001ca8;
+*/
+r_lld_con_tx_prog_new_packet_hook = 0x40001cac;
+r_lld_init_frm_eof_isr_hook = 0x40001cb0;
+r_lld_init_evt_start_cbk_hook = 0x40001cb4;
+/*
+r_lld_init_start_hook = 0x40001cb8;
+*/
+r_lld_init_sched_hook = 0x40001cbc;
+r_lld_init_process_pkt_tx_hook = 0x40001cc0;
+r_lld_per_adv_evt_start_cbk_hook = 0x40001cc4;
+r_lld_per_adv_frm_isr_hook = 0x40001cc8;
+r_lld_per_adv_start_hook = 0x40001ccc;
+r_lld_sync_frm_eof_isr_hook = 0x40001cd0;
+r_lld_sync_evt_start_cbk_hook = 0x40001cd4;
+r_lld_sync_start_hook = 0x40001cd8;
+r_lld_sync_process_pkt_rx_pkt_check_hook = 0x40001cdc;
+r_sch_arb_insert_hook = 0x40001ce0;
+r_sch_plan_offset_req_hook = 0x40001ce4;
+
/***************************************
Group rom_pp
***************************************/
@@ -1810,11 +1901,11 @@ RC_GetBlockAckTime = 0x4000525c;
ebuf_list_remove = 0x40005268;
esf_buf_alloc = 0x40005274;
esf_buf_alloc_dynamic = 0x40005280;
-esf_buf_recycle = 0x4000528c;
+/*esf_buf_recycle = 0x4000528c;*/
GetAccess = 0x40005298;
hal_mac_is_low_rate_enabled = 0x400052a4;
hal_mac_tx_get_blockack = 0x400052b0;
-hal_mac_tx_set_ppdu = 0x400052bc;
+/* hal_mac_tx_set_ppdu = 0x400052bc;*/
ic_get_trc = 0x400052c8;
ic_mac_deinit = 0x400052d4;
ic_mac_init = 0x400052e0;
@@ -1837,11 +1928,11 @@ lmacRecycleMPDU = 0x400053a0;
lmacRxDone = 0x400053ac;
lmacSetTxFrame = 0x400053b8;
lmacTxDone = 0x400053c4;
-lmacTxFrame = 0x400053d0;
+/*lmacTxFrame = 0x400053d0;*/
mac_tx_set_duration = 0x400053dc;
-mac_tx_set_htsig = 0x400053e8;
+/* mac_tx_set_htsig = 0x400053e8;*/
mac_tx_set_plcp0 = 0x400053f4;
-mac_tx_set_plcp1 = 0x40005400;
+/* mac_tx_set_plcp1 = 0x40005400;*/
mac_tx_set_plcp2 = 0x4000540c;
pm_check_state = 0x40005418;
pm_disable_dream_timer = 0x40005424;
@@ -1856,16 +1947,16 @@ pm_set_beacon_filter = 0x40005484;
pm_is_in_wifi_slice_threshold = 0x40005490;
pm_is_waked = 0x4000549c;
pm_keep_alive = 0x400054a8;
-pm_on_beacon_rx = 0x400054b4;
+/* pm_on_beacon_rx = 0x400054b4; */
pm_on_data_rx = 0x400054c0;
pm_on_tbtt = 0x400054cc;
-pm_parse_beacon = 0x400054d8;
-pm_process_tim = 0x400054e4;
-pm_rx_beacon_process = 0x400054f0;
-pm_rx_data_process = 0x400054fc;
-pm_sleep = 0x40005508;
+/* pm_parse_beacon = 0x400054d8;*/
+/* pm_process_tim = 0x400054e4; */
+/*pm_rx_beacon_process = 0x400054f0;*/
+/* pm_rx_data_process = 0x400054fc; */
+/*pm_sleep = 0x40005508;*/
pm_sleep_for = 0x40005514;
-pm_tbtt_process = 0x40005520;
+/* pm_tbtt_process = 0x40005520; */
ppAMPDU2Normal = 0x4000552c;
ppAssembleAMPDU = 0x40005538;
ppCalFrameTimes = 0x40005544;
@@ -1879,7 +1970,7 @@ ppEnqueueRxq = 0x40005598;
ppEnqueueTxDone = 0x400055a4;
ppGetTxQFirstAvail_Locked = 0x400055b0;
ppGetTxframe = 0x400055bc;
-ppMapTxQueue = 0x400055c8;
+/*ppMapTxQueue = 0x400055c8;*/
ppProcessRxPktHdr = 0x400055e0;
ppProcessTxQ = 0x400055ec;
ppRecordBarRRC = 0x400055f8;
@@ -1896,7 +1987,7 @@ ppSearchTxQueue = 0x40005670;
ppSearchTxframe = 0x4000567c;
ppSelectNextQueue = 0x40005688;
ppSubFromAMPDU = 0x40005694;
-ppTask = 0x400056a0;
+/* ppTask = 0x400056a0; */
ppTxPkt = 0x400056ac;
ppTxProtoProc = 0x400056b8;
ppTxqUpdateBitmap = 0x400056c4;
@@ -1916,7 +2007,7 @@ rcClearCurStat = 0x40005760;
rcGetSched = 0x4000576c;
rcLowerSched = 0x40005778;
rcSetTxAmpduLimit = 0x40005784;
-rcTxUpdatePer = 0x40005790;
+/* rcTxUpdatePer = 0x40005790;*/
rcUpdateAckSnr = 0x4000579c;
rcUpdateRate = 0x400057a8;
/* rcUpdateTxDone = 0x400057b4; */
@@ -1948,13 +2039,13 @@ wdev_mac_special_reg_store = 0x400058e0;
wdev_mac_wakeup = 0x400058ec;
wdev_mac_sleep = 0x400058f8;
hal_mac_is_dma_enable = 0x40005904;
-wDev_ProcessFiq = 0x40005910;
+/* wDev_ProcessFiq = 0x40005910; */
wDev_ProcessRxSucData = 0x4000591c;
wdevProcessRxSucDataAll = 0x40005928;
wdev_csi_len_align = 0x40005934;
ppDequeueTxDone_Locked = 0x40005940;
-ppProcTxDone = 0x4000594c;
-pm_tx_data_done_process = 0x40005958;
+/*ppProcTxDone = 0x4000594c;*/
+/*pm_tx_data_done_process = 0x40005958;*/
config_is_cache_tx_buf_enabled = 0x40005964;
ppMapWaitTxq = 0x40005970;
ppProcessWaitingQueue = 0x4000597c;
@@ -2012,6 +2103,7 @@ g_tx_done_cb_func = 0x3fcef8ac;
g_per_conn_trc = 0x3fcef860;
s_encap_amsdu_func = 0x3fcef85c;
+
/***************************************
Group rom_net80211
***************************************/
@@ -2037,7 +2129,7 @@ ieee80211_is_tx_allowed = 0x40005a78;
ieee80211_output_pending_eb = 0x40005a84;
ieee80211_output_process = 0x40005a90;
ieee80211_set_tx_desc = 0x40005a9c;
-sta_input = 0x40005aa8;
+/*sta_input = 0x40005aa8;*/
wifi_get_macaddr = 0x40005ab4;
wifi_rf_phy_disable = 0x40005ac0;
wifi_rf_phy_enable = 0x40005acc;
@@ -2048,7 +2140,7 @@ ieee80211_recycle_cache_eb = 0x40005afc;
ieee80211_search_node = 0x40005b08;
roundup2 = 0x40005b14;
ieee80211_crypto_encap = 0x40005b20;
-ieee80211_crypto_decap = 0x40005b2c;
+/* ieee80211_crypto_decap = 0x40005b2c; */
/* ieee80211_decap = 0x40005b38; */
ieee80211_set_tx_pti = 0x40005b44;
wifi_is_started = 0x40005b50;
@@ -2064,6 +2156,7 @@ s_netstack_free = 0x3fcef840;
mesh_rxcb = 0x3fcef83c;
sta_rxcb = 0x3fcef838;
+
/***************************************
Group rom_coexist
***************************************/
@@ -2078,7 +2171,7 @@ coex_core_pti_get = 0x40005ba4;
coex_core_release = 0x40005bb0;
coex_core_request = 0x40005bbc;
coex_core_status_get = 0x40005bc8;
-coex_core_timer_idx_get = 0x40005bd4;
+/*coex_core_timer_idx_get = 0x40005bd4;*/
coex_event_duration_get = 0x40005be0;
coex_hw_timer_disable = 0x40005bec;
coex_hw_timer_enable = 0x40005bf8;
@@ -2097,6 +2190,7 @@ coexist_funcs = 0x3fcef828;
g_coa_funcs_p = 0x3fcef824;
g_coex_param_ptr = 0x3fcef820;
+
/***************************************
Group rom_phy
***************************************/
@@ -2122,10 +2216,10 @@ rom_get_bbgain_db = 0x40005d18;
rom_get_data_sat = 0x40005d24;
rom_get_i2c_read_mask = 0x40005d30;
rom_get_pwctrl_correct = 0x40005d3c;
-rom_i2c_readreg = 0x40005d48;
-rom_i2c_readreg_mask = 0x40005d54;
-rom_i2c_writereg = 0x40005d60;
-rom_i2c_writereg_mask = 0x40005d6c;
+rom_i2c_readReg = 0x40005d48;
+rom_i2c_readReg_Mask = 0x40005d54;
+rom_i2c_writeReg = 0x40005d60;
+rom_i2c_writeReg_Mask = 0x40005d6c;
rom_index_to_txbbgain = 0x40005d78;
rom_iq_est_disable = 0x40005d84;
rom_iq_est_enable = 0x40005d90;
@@ -2276,47 +2370,6 @@ phy_param_rom = 0x3fcef81c;
PROVIDE ( esp_rom_tjpgd_decomp = 0x40000864 );
PROVIDE ( esp_rom_tjpgd_prepare = 0x40000858 );
-PROVIDE ( esp_rom_crc32_le = crc32_le );
-PROVIDE ( esp_rom_crc16_le = crc16_le );
-PROVIDE ( esp_rom_crc8_le = crc8_le );
-PROVIDE ( esp_rom_crc32_be = crc32_be );
-PROVIDE ( esp_rom_crc16_be = crc16_be );
-PROVIDE ( esp_rom_crc8_be = crc8_be );
-
-PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio );
-PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup );
-PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv );
-PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold );
-PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in );
-PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
-
-PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 );
-PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig );
-PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad );
-PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
-
-PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush );
-PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char );
-PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle );
-PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char );
-PROVIDE ( esp_rom_uart_rx_string = UartRxString );
-PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
-PROVIDE ( esp_rom_uart_usb_acm_init = Uart_Init_USB );
-PROVIDE ( esp_rom_uart_putc = ets_write_char_uart );
-
-PROVIDE ( esp_rom_md5_init = MD5Init );
-PROVIDE ( esp_rom_md5_update = MD5Update );
-PROVIDE ( esp_rom_md5_final = MD5Final );
-
-PROVIDE ( esp_rom_printf = ets_printf );
-PROVIDE ( esp_rom_delay_us = ets_delay_us );
-PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
-PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
-
-PROVIDE( esp_rom_spiflash_attach = spi_flash_attach );
-PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
-PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);
-
/***************************************
Group libgcc
***************************************/
diff --git a/boards/xtensa/esp32s3/common/scripts/esp32s3_rom_aliases.ld b/boards/xtensa/esp32s3/common/scripts/esp32s3_rom_aliases.ld
new file mode 100644
index 0000000000..f7b48faef3
--- /dev/null
+++ b/boards/xtensa/esp32s3/common/scripts/esp32s3_rom_aliases.ld
@@ -0,0 +1,37 @@
+/****************************************************************************
+ * boards/xtensa/esp32s3/common/scripts/esp32s3_aliases.ld
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Lower-case aliases for symbols not compliant to nxstyle */
+
+PROVIDE( cache_dbus_mmu_set = Cache_Dbus_MMU_Set );
+PROVIDE( cache_ibus_mmu_set = Cache_Ibus_MMU_Set );
+PROVIDE( cache_invalidate_addr = Cache_Invalidate_Addr );
+PROVIDE( cache_invalidate_dcache_all = Cache_Invalidate_DCache_All );
+PROVIDE( cache_invalidate_icache_all = Cache_Invalidate_ICache_All );
+PROVIDE( cache_occupy_addr = Cache_Occupy_Addr );
+PROVIDE( cache_resume_dcache = Cache_Resume_DCache );
+PROVIDE( cache_resume_icache = Cache_Resume_ICache );
+PROVIDE( cache_set_idrom_mmu_info = Cache_Set_IDROM_MMU_Info );
+PROVIDE( cache_set_idrom_mmu_size = Cache_Set_IDROM_MMU_Size );
+PROVIDE( cache_suspend_dcache = Cache_Suspend_DCache );
+PROVIDE( cache_suspend_icache = Cache_Suspend_ICache );
+PROVIDE( cache_writeback_all = Cache_WriteBack_All );
diff --git a/boards/xtensa/esp32s3/common/scripts/esp32s3_rom_api.ld b/boards/xtensa/esp32s3/common/scripts/esp32s3_rom_api.ld
new file mode 100644
index 0000000000..5cfc7df437
--- /dev/null
+++ b/boards/xtensa/esp32s3/common/scripts/esp32s3_rom_api.ld
@@ -0,0 +1,79 @@
+/****************************************************************************
+ * boards/xtensa/esp32s3/common/scripts/esp32s3_peripherals.ld
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/**
+ * ROM APIs
+ */
+PROVIDE ( esp_rom_crc32_le = crc32_le );
+PROVIDE ( esp_rom_crc16_le = crc16_le );
+PROVIDE ( esp_rom_crc8_le = crc8_le );
+PROVIDE ( esp_rom_crc32_be = crc32_be );
+PROVIDE ( esp_rom_crc16_be = crc16_be );
+PROVIDE ( esp_rom_crc8_be = crc8_be );
+
+PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio );
+PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup );
+PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv );
+PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold );
+PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in );
+PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
+
+PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 );
+PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig );
+PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad );
+PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
+
+PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush );
+PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char );
+PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle );
+PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char );
+PROVIDE ( esp_rom_uart_rx_string = UartRxString );
+PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
+PROVIDE ( esp_rom_uart_usb_acm_init = Uart_Init_USB );
+PROVIDE ( esp_rom_uart_putc = ets_write_char_uart );
+
+PROVIDE ( esp_rom_md5_init = MD5Init );
+PROVIDE ( esp_rom_md5_update = MD5Update );
+PROVIDE ( esp_rom_md5_final = MD5Final );
+
+PROVIDE ( esp_rom_software_reset_system = software_reset );
+PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu );
+
+PROVIDE ( esp_rom_printf = ets_printf );
+PROVIDE ( esp_rom_delay_us = ets_delay_us );
+PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
+PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
+PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
+PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
+
+PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
+PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
+PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);
+PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea );
+
+PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix );
+PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs);
+PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction );
+PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command );
+
+PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg );
+PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask );
+PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg );
+PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask );
\ No newline at end of file
diff --git a/boards/xtensa/esp32s3/common/scripts/flat_memory.ld b/boards/xtensa/esp32s3/common/scripts/flat_memory.ld
index 531406969d..3131e5a654 100644
--- a/boards/xtensa/esp32s3/common/scripts/flat_memory.ld
+++ b/boards/xtensa/esp32s3/common/scripts/flat_memory.ld
@@ -31,6 +31,8 @@
#include <nuttx/config.h>
+#include "esp32s3_aliases.ld"
+
#define SRAM_IRAM_START 0x40370000
#define SRAM_DIRAM_I_START 0x40378000
diff --git a/boards/xtensa/esp32s3/common/scripts/protected_memory.ld b/boards/xtensa/esp32s3/common/scripts/protected_memory.ld
index 10a73d0ea4..896d87ab42 100644
--- a/boards/xtensa/esp32s3/common/scripts/protected_memory.ld
+++ b/boards/xtensa/esp32s3/common/scripts/protected_memory.ld
@@ -32,6 +32,8 @@
#include <nuttx/config.h>
+#include "esp32s3_aliases.ld"
+
#define SRAM_IRAM_START 0x40370000
#define SRAM_DIRAM_I_START 0x40378000
diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/ble/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/ble/defconfig
new file mode 100644
index 0000000000..ca1b103ee5
--- /dev/null
+++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/ble/defconfig
@@ -0,0 +1,71 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_LEDS is not set
+# CONFIG_NDEBUG is not set
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+CONFIG_ALLOW_BSD_COMPONENTS=y
+CONFIG_ARCH="xtensa"
+CONFIG_ARCH_BOARD="esp32s3-devkit"
+CONFIG_ARCH_BOARD_COMMON=y
+CONFIG_ARCH_BOARD_ESP32S3_DEVKIT=y
+CONFIG_ARCH_CHIP="esp32s3"
+CONFIG_ARCH_CHIP_ESP32S3=y
+CONFIG_ARCH_CHIP_ESP32S3WROOM1=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_XTENSA=y
+CONFIG_BOARDCTL_RESET=y
+CONFIG_BOARD_LOOPSPERMSEC=16717
+CONFIG_BTSAK=y
+CONFIG_BUILTIN=y
+CONFIG_DEFAULT_TASK_STACKSIZE=4096
+CONFIG_DRIVERS_BLUETOOTH=y
+CONFIG_DRIVERS_IEEE80211=y
+CONFIG_DRIVERS_WIRELESS=y
+CONFIG_ESP32S3_BLE=y
+CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096
+CONFIG_ESP32S3_UART0=y
+CONFIG_FS_LARGEFILE=y
+CONFIG_FS_PROCFS=y
+CONFIG_IDLETHREAD_STACKSIZE=3072
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INIT_STACKSIZE=8192
+CONFIG_INTELHEX_BINARY=y
+CONFIG_NAME_MAX=48
+CONFIG_NETDEV_LATEINIT=y
+CONFIG_NET_BLUETOOTH=y
+CONFIG_NET_ETH_PKTSIZE=1514
+CONFIG_NET_SOCKOPTS=y
+CONFIG_NET_TCP=y
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=2048
+CONFIG_PREALLOC_MQ_MSGS=32
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PTHREAD_MUTEX_TYPES=y
+CONFIG_RAM_SIZE=114688
+CONFIG_RAM_START=0x20000000
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SIG_DEFAULT=y
+CONFIG_SPINLOCK=y
+CONFIG_START_DAY=6
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2011
+CONFIG_SYSLOG_BUFFER=y
+CONFIG_SYSTEM_ARGTABLE3=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TIMER=y
+CONFIG_TLS_TASK_NELEM=4
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_BLUETOOTH=y
diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs
index 154b50a697..5bca3415a0 100644
--- a/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs
+++ b/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs
@@ -25,6 +25,8 @@ include $(TOPDIR)/arch/xtensa/src/lx7/Toolchain.defs
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_peripherals.ld
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom.ld
+ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom_api.ld
+ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom_aliases.ld
# Pick the linker scripts from the board level if they exist, if not
# pick the common linker scripts.
diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c
index 98bfc54580..9907a2cf7b 100644
--- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c
+++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c
@@ -46,6 +46,10 @@
# include "esp32s3_board_wlan.h"
#endif
+#ifdef CONFIG_ESP32S3_BLE
+# include "esp32s3_ble.h"
+#endif
+
#ifdef CONFIG_ESP32S3_RT_TIMER
# include "esp32s3_rt_timer.h"
#endif
@@ -225,6 +229,24 @@ int esp32s3_bringup(void)
}
#endif
+#ifdef CONFIG_ESP32S3_WIRELESS
+
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ ret = esp32s3_wifi_bt_coexist_init();
+ if (ret)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to initialize Wi-Fi and BT coexist\n");
+ }
+#endif
+
+#ifdef CONFIG_ESP32S3_BLE
+ ret = esp32s3_ble_initialize();
+ if (ret)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to initialize BLE\n");
+ }
+#endif
+
#ifdef CONFIG_ESP32S3_WIFI
ret = board_wlan_init();
if (ret < 0)
@@ -234,6 +256,8 @@ int esp32s3_bringup(void)
}
#endif
+#endif
+
#ifdef CONFIG_VIDEO_FB
ret = fb_register(0, 0);
if (ret < 0)
diff --git a/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs
index 056bbf7b31..001d639323 100644
--- a/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs
+++ b/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs
@@ -25,6 +25,8 @@ include $(TOPDIR)/arch/xtensa/src/lx7/Toolchain.defs
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_peripherals.ld
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom.ld
+ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom_api.ld
+ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom_aliases.ld
# Pick the linker scripts from the board level if they exist, if not
# pick the common linker scripts.
diff --git a/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs
index 3c937212f3..28863294b1 100644
--- a/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs
+++ b/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs
@@ -25,6 +25,8 @@ include $(TOPDIR)/arch/xtensa/src/lx7/Toolchain.defs
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_peripherals.ld
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom.ld
+ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom_api.ld
+ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom_aliases.ld
# Pick the linker scripts from the board level if they exist, if not
# pick the common linker scripts.
[nuttx] 01/12: esp32s3/peripherals: Add initialization routine for the peripherals
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 7dafbb05a14ac9c9c5606834a480932ef1ecde02
Author: Tiago Medicci Serrano <ti...@espressif.com>
AuthorDate: Wed Aug 2 09:47:51 2023 -0300
esp32s3/peripherals: Add initialization routine for the peripherals
It provides an initialization function that performs the
peripherals' initialization routine during the chip startup.
---
arch/xtensa/src/esp32s3/Make.defs | 1 +
arch/xtensa/src/esp32s3/esp32s3_periph.c | 715 ++++++++++++++++++++++
arch/xtensa/src/esp32s3/esp32s3_periph.h | 199 ++++++
arch/xtensa/src/esp32s3/esp32s3_reset_reasons.h | 101 +++
arch/xtensa/src/esp32s3/esp32s3_start.c | 5 +
arch/xtensa/src/esp32s3/hardware/esp32s3_system.h | 20 +-
6 files changed, 1031 insertions(+), 10 deletions(-)
diff --git a/arch/xtensa/src/esp32s3/Make.defs b/arch/xtensa/src/esp32s3/Make.defs
index 9aee50cb9e..9618616b6a 100644
--- a/arch/xtensa/src/esp32s3/Make.defs
+++ b/arch/xtensa/src/esp32s3/Make.defs
@@ -31,6 +31,7 @@ CHIP_CSRCS = esp32s3_irq.c esp32s3_clockconfig.c esp32s3_region.c
CHIP_CSRCS += esp32s3_systemreset.c esp32s3_user.c esp32s3_allocateheap.c
CHIP_CSRCS += esp32s3_wdt.c esp32s3_gpio.c esp32s3_lowputc.c esp32s3_serial.c
CHIP_CSRCS += esp32s3_rtc_gpio.c esp32s3_libc_stubs.c esp32s3_spi_timing.c
+CHIP_CSRCS += esp32s3_periph.c
# Configuration-dependent ESP32-S3 files
diff --git a/arch/xtensa/src/esp32s3/esp32s3_periph.c b/arch/xtensa/src/esp32s3/esp32s3_periph.c
new file mode 100644
index 0000000000..a371c668e5
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_periph.c
@@ -0,0 +1,715 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_periph.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+
+#include "hardware/esp32s3_syscon.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_reset_reasons.h"
+
+#include "xtensa.h"
+
+#include "esp32s3_periph.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint8_t ref_counts[PERIPH_MODULE_MAX];
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/* Get the reset reason for CPU. */
+
+extern esp32s3_periph_module_t esp_rom_get_reset_reason(int cpu_no);
+
+/****************************************************************************
+ * Name: esp32s3_periph_ll_get_clk_en_reg
+ *
+ * Description:
+ * Get module clock register through periph module
+ *
+ * Input Parameters:
+ * periph - Periph module (one of the esp32s3_periph_module_t values)
+ *
+ * Returned Value:
+ * Module clock register
+ *
+ ****************************************************************************/
+
+static uint32_t IRAM_ATTR esp32s3_periph_ll_get_clk_en_reg(
+ esp32s3_periph_module_t periph)
+{
+ switch (periph)
+ {
+ case PERIPH_DEDIC_GPIO_MODULE:
+ return SYSTEM_CPU_PERI_CLK_EN_REG;
+ case PERIPH_RNG_MODULE:
+ case PERIPH_WIFI_MODULE:
+ case PERIPH_BT_MODULE:
+ case PERIPH_WIFI_BT_COMMON_MODULE:
+ case PERIPH_BT_BASEBAND_MODULE:
+ case PERIPH_BT_LC_MODULE:
+ return SYSTEM_WIFI_CLK_EN_REG;
+ case PERIPH_UART2_MODULE:
+ case PERIPH_SDMMC_MODULE:
+ case PERIPH_LCD_CAM_MODULE:
+ case PERIPH_GDMA_MODULE:
+ case PERIPH_HMAC_MODULE:
+ case PERIPH_DS_MODULE:
+ case PERIPH_AES_MODULE:
+ case PERIPH_SHA_MODULE:
+ case PERIPH_RSA_MODULE:
+ return SYSTEM_PERIP_CLK_EN1_REG;
+ default:
+ return SYSTEM_PERIP_CLK_EN0_REG;
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_periph_ll_get_clk_en_mask
+ *
+ * Description:
+ * Get module clock bit through periph module
+ *
+ * Input Parameters:
+ * periph - Periph module (one of the esp32s3_periph_module_t values)
+ *
+ * Returned Value:
+ * Module clock bit
+ *
+ ****************************************************************************/
+
+static inline uint32_t IRAM_ATTR esp32s3_periph_ll_get_clk_en_mask(
+ esp32s3_periph_module_t periph)
+{
+ switch (periph)
+ {
+ case PERIPH_SARADC_MODULE:
+ return SYSTEM_APB_SARADC_CLK_EN;
+ case PERIPH_RMT_MODULE:
+ return SYSTEM_RMT_CLK_EN;
+ case PERIPH_LEDC_MODULE:
+ return SYSTEM_LEDC_CLK_EN;
+ case PERIPH_UART0_MODULE:
+ return SYSTEM_UART_CLK_EN;
+ case PERIPH_UART1_MODULE:
+ return SYSTEM_UART1_CLK_EN;
+ case PERIPH_UART2_MODULE:
+ return SYSTEM_UART2_CLK_EN;
+ case PERIPH_USB_MODULE:
+ return SYSTEM_USB_CLK_EN;
+ case PERIPH_I2C0_MODULE:
+ return SYSTEM_I2C_EXT0_CLK_EN;
+ case PERIPH_I2C1_MODULE:
+ return SYSTEM_I2C_EXT1_CLK_EN;
+ case PERIPH_I2S0_MODULE:
+ return SYSTEM_I2S0_CLK_EN;
+ case PERIPH_I2S1_MODULE:
+ return SYSTEM_I2S1_CLK_EN;
+ case PERIPH_LCD_CAM_MODULE:
+ return SYSTEM_LCD_CAM_CLK_EN;
+ case PERIPH_TIMG0_MODULE:
+ return SYSTEM_TIMERGROUP_CLK_EN;
+ case PERIPH_TIMG1_MODULE:
+ return SYSTEM_TIMERGROUP1_CLK_EN;
+ case PERIPH_PWM0_MODULE:
+ return SYSTEM_PWM0_CLK_EN;
+ case PERIPH_PWM1_MODULE:
+ return SYSTEM_PWM1_CLK_EN;
+ case PERIPH_UHCI0_MODULE:
+ return SYSTEM_UHCI0_CLK_EN;
+ case PERIPH_UHCI1_MODULE:
+ return SYSTEM_UHCI1_CLK_EN;
+ case PERIPH_PCNT_MODULE:
+ return SYSTEM_PCNT_CLK_EN;
+ case PERIPH_SPI_MODULE:
+ return SYSTEM_SPI01_CLK_EN;
+ case PERIPH_SPI2_MODULE:
+ return SYSTEM_SPI2_CLK_EN;
+ case PERIPH_SPI3_MODULE:
+ return SYSTEM_SPI3_CLK_EN;
+ case PERIPH_SDMMC_MODULE:
+ return SYSTEM_SDIO_HOST_CLK_EN;
+ case PERIPH_TWAI_MODULE:
+ return SYSTEM_TWAI_CLK_EN;
+ case PERIPH_RNG_MODULE:
+ return SYSTEM_WIFI_CLK_RNG_EN;
+ case PERIPH_WIFI_MODULE:
+ return SYSTEM_WIFI_CLK_WIFI_EN_M;
+ case PERIPH_BT_MODULE:
+ return SYSTEM_WIFI_CLK_BT_EN_M;
+ case PERIPH_WIFI_BT_COMMON_MODULE:
+ return SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M;
+ case PERIPH_BT_BASEBAND_MODULE:
+ return SYSTEM_BT_BASEBAND_EN;
+ case PERIPH_BT_LC_MODULE:
+ return SYSTEM_BT_LC_EN;
+ case PERIPH_SYSTIMER_MODULE:
+ return SYSTEM_SYSTIMER_CLK_EN;
+ case PERIPH_DEDIC_GPIO_MODULE:
+ return SYSTEM_CLK_EN_DEDICATED_GPIO;
+ case PERIPH_GDMA_MODULE:
+ return SYSTEM_DMA_CLK_EN;
+ case PERIPH_AES_MODULE:
+ return SYSTEM_CRYPTO_AES_CLK_EN;
+ case PERIPH_SHA_MODULE:
+ return SYSTEM_CRYPTO_SHA_CLK_EN;
+ case PERIPH_RSA_MODULE:
+ return SYSTEM_CRYPTO_RSA_CLK_EN;
+ case PERIPH_HMAC_MODULE:
+ return SYSTEM_CRYPTO_HMAC_CLK_EN;
+ case PERIPH_DS_MODULE:
+ return SYSTEM_CRYPTO_DS_CLK_EN;
+ default:
+ return 0;
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_periph_ll_get_rst_en_reg
+ *
+ * Description:
+ * Get system reset register through periph module
+ *
+ * Input Parameters:
+ * periph - Periph module (one of the esp32s3_periph_module_t values)
+ *
+ * Returned Value:
+ * System reset register
+ *
+ ****************************************************************************/
+
+static uint32_t IRAM_ATTR esp32s3_periph_ll_get_rst_en_reg(
+ esp32s3_periph_module_t periph)
+{
+ switch (periph)
+ {
+ case PERIPH_DEDIC_GPIO_MODULE:
+ return SYSTEM_CPU_PERI_RST_EN_REG;
+ case PERIPH_RNG_MODULE:
+ case PERIPH_WIFI_MODULE:
+ case PERIPH_BT_MODULE:
+ case PERIPH_WIFI_BT_COMMON_MODULE:
+ case PERIPH_BT_BASEBAND_MODULE:
+ case PERIPH_BT_LC_MODULE:
+ return SYSTEM_CORE_RST_EN_REG;
+ case PERIPH_UART2_MODULE:
+ case PERIPH_SDMMC_MODULE:
+ case PERIPH_LCD_CAM_MODULE:
+ case PERIPH_GDMA_MODULE:
+ case PERIPH_HMAC_MODULE:
+ case PERIPH_DS_MODULE:
+ case PERIPH_AES_MODULE:
+ case PERIPH_SHA_MODULE:
+ case PERIPH_RSA_MODULE:
+ return SYSTEM_PERIP_RST_EN1_REG;
+ default:
+ return SYSTEM_PERIP_RST_EN0_REG;
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_periph_ll_get_rst_en_mask
+ *
+ * Description:
+ * Get system reset bit through periph module
+ *
+ * Input Parameters:
+ * periph - Periph module (one of the esp32s3_periph_module_t values)
+ * enable - Whether hardware acceleration is enabled
+ *
+ * Returned Value:
+ * System reset bit
+ *
+ ****************************************************************************/
+
+static inline uint32_t IRAM_ATTR esp32s3_periph_ll_get_rst_en_mask(
+ esp32s3_periph_module_t periph,
+ bool enable)
+{
+ switch (periph)
+ {
+ case PERIPH_SARADC_MODULE:
+ return SYSTEM_APB_SARADC_RST;
+ case PERIPH_RMT_MODULE:
+ return SYSTEM_RMT_RST;
+ case PERIPH_LEDC_MODULE:
+ return SYSTEM_LEDC_RST;
+ case PERIPH_WIFI_MODULE:
+ return SYSTEM_WIFIMAC_RST;
+ case PERIPH_BT_MODULE:
+ return (SYSTEM_BTBB_RST | SYSTEM_BTBB_REG_RST |
+ SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST |
+ SYSTEM_RW_BTMAC_REG_RST | SYSTEM_RW_BTLP_REG_RST);
+ case PERIPH_UART0_MODULE:
+ return SYSTEM_UART_RST;
+ case PERIPH_UART1_MODULE:
+ return SYSTEM_UART1_RST;
+ case PERIPH_UART2_MODULE:
+ return SYSTEM_UART2_RST;
+ case PERIPH_USB_MODULE:
+ return SYSTEM_USB_RST;
+ case PERIPH_I2C0_MODULE:
+ return SYSTEM_I2C_EXT0_RST;
+ case PERIPH_I2C1_MODULE:
+ return SYSTEM_I2C_EXT1_RST;
+ case PERIPH_I2S0_MODULE:
+ return SYSTEM_I2S0_RST;
+ case PERIPH_I2S1_MODULE:
+ return SYSTEM_I2S1_RST;
+ case PERIPH_LCD_CAM_MODULE:
+ return SYSTEM_LCD_CAM_RST;
+ case PERIPH_TIMG0_MODULE:
+ return SYSTEM_TIMERGROUP_RST;
+ case PERIPH_TIMG1_MODULE:
+ return SYSTEM_TIMERGROUP1_RST;
+ case PERIPH_PWM0_MODULE:
+ return SYSTEM_PWM0_RST;
+ case PERIPH_PWM1_MODULE:
+ return SYSTEM_PWM1_RST;
+ case PERIPH_UHCI0_MODULE:
+ return SYSTEM_UHCI0_RST;
+ case PERIPH_UHCI1_MODULE:
+ return SYSTEM_UHCI1_RST;
+ case PERIPH_PCNT_MODULE:
+ return SYSTEM_PCNT_RST;
+ case PERIPH_SPI_MODULE:
+ return SYSTEM_SPI01_RST;
+ case PERIPH_SPI2_MODULE:
+ return SYSTEM_SPI2_RST;
+ case PERIPH_SPI3_MODULE:
+ return SYSTEM_SPI3_RST;
+ case PERIPH_SDMMC_MODULE:
+ return SYSTEM_SDIO_HOST_RST;
+ case PERIPH_TWAI_MODULE:
+ return SYSTEM_TWAI_RST;
+ case PERIPH_SYSTIMER_MODULE:
+ return SYSTEM_SYSTIMER_RST;
+ case PERIPH_DEDIC_GPIO_MODULE:
+ return SYSTEM_RST_EN_DEDICATED_GPIO;
+ case PERIPH_GDMA_MODULE:
+ return SYSTEM_DMA_RST;
+ case PERIPH_HMAC_MODULE:
+ return SYSTEM_CRYPTO_HMAC_RST;
+ case PERIPH_DS_MODULE:
+ return SYSTEM_CRYPTO_DS_RST;
+ case PERIPH_AES_MODULE:
+ if (enable)
+ {
+ /* Clear reset on digital signature, otherwise AES unit is
+ * held in reset also.
+ */
+
+ return (SYSTEM_CRYPTO_AES_RST | SYSTEM_CRYPTO_DS_RST);
+ }
+ else
+ {
+ /* Don't return other units to reset, as this pulls reset
+ * on RSA & SHA units, respectively.
+ */
+
+ return SYSTEM_CRYPTO_AES_RST;
+ }
+
+ case PERIPH_SHA_MODULE:
+ if (enable)
+ {
+ /* Clear reset on digital signature and HMAC, otherwise SHA is
+ * held in reset
+ */
+
+ return (SYSTEM_CRYPTO_SHA_RST | SYSTEM_CRYPTO_DS_RST |
+ SYSTEM_CRYPTO_HMAC_RST) ;
+ }
+ else
+ {
+ /* Don't assert reset on secure boot, otherwise AES is
+ * held in reset
+ */
+
+ return SYSTEM_CRYPTO_SHA_RST;
+ }
+
+ case PERIPH_RSA_MODULE:
+ if (enable)
+ {
+ /* also clear reset on digital signature, otherwise RSA is
+ * held in reset
+ */
+
+ return (SYSTEM_CRYPTO_RSA_RST | SYSTEM_CRYPTO_DS_RST);
+ }
+ else
+ {
+ /* don't reset digital signature unit, as this resets AES also */
+
+ return SYSTEM_CRYPTO_RSA_RST;
+ }
+
+ default:
+ return 0;
+ }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_periph_module_enable
+ *
+ * Description:
+ * Enable peripheral module
+ *
+ * Input Parameters:
+ * periph - Periph module (one of the esp32s3_periph_module_t values)
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp32s3_periph_module_enable(esp32s3_periph_module_t periph)
+{
+ irqstate_t flags = enter_critical_section();
+
+ ASSERT(periph < PERIPH_MODULE_MAX);
+ if (ref_counts[periph] == 0)
+ {
+ modifyreg32(esp32s3_periph_ll_get_clk_en_reg(periph), 0,
+ esp32s3_periph_ll_get_clk_en_mask(periph));
+ modifyreg32(esp32s3_periph_ll_get_rst_en_reg(periph),
+ esp32s3_periph_ll_get_rst_en_mask(periph, true), 0);
+ }
+
+ ref_counts[periph]++;
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: esp32s3_periph_module_disable
+ *
+ * Description:
+ * Disable peripheral module
+ *
+ * Input Parameters:
+ * periph - Periph module (one of enum esp32s3_periph_module_t values)
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp32s3_periph_module_disable(esp32s3_periph_module_t periph)
+{
+ irqstate_t flags = enter_critical_section();
+
+ ASSERT(periph < PERIPH_MODULE_MAX);
+ ref_counts[periph]--;
+ if (ref_counts[periph] == 0)
+ {
+ modifyreg32(esp32s3_periph_ll_get_clk_en_reg(periph),
+ esp32s3_periph_ll_get_clk_en_mask(periph), 0);
+ modifyreg32(esp32s3_periph_ll_get_rst_en_reg(periph), 0,
+ esp32s3_periph_ll_get_rst_en_mask(periph, false));
+ }
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: esp32s3_periph_module_reset
+ *
+ * Description:
+ * Reset peripheral module by asserting and de-asserting the reset signal.
+ *
+ * Input Parameters:
+ * periph - Periph module (one of the esp32s3_periph_module_t values)
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp32s3_periph_module_reset(esp32s3_periph_module_t periph)
+{
+ irqstate_t flags = enter_critical_section();
+
+ ASSERT(periph < PERIPH_MODULE_MAX);
+
+ modifyreg32(esp32s3_periph_ll_get_rst_en_reg(periph), 0,
+ esp32s3_periph_ll_get_rst_en_mask(periph, false));
+ modifyreg32(esp32s3_periph_ll_get_rst_en_reg(periph),
+ esp32s3_periph_ll_get_rst_en_mask(periph, false), 0);
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: esp32s3_periph_wifi_bt_common_module_enable
+ *
+ * Description:
+ * Enable Wi-Fi and BT common module.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR esp32s3_periph_wifi_bt_common_module_enable(void)
+{
+ irqstate_t flags = enter_critical_section();
+
+ if (ref_counts[PERIPH_WIFI_BT_COMMON_MODULE] == 0)
+ {
+ modifyreg32(SYSTEM_WIFI_CLK_EN_REG,
+ 0, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M);
+ modifyreg32(SYSTEM_CORE_RST_EN_REG, 0, 0);
+ }
+
+ ref_counts[PERIPH_WIFI_BT_COMMON_MODULE]++;
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: esp32s3_periph_wifi_bt_common_module_disable
+ *
+ * Description:
+ * Disable Wi-Fi and BT common module.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp32s3_periph_wifi_bt_common_module_disable(void)
+{
+ irqstate_t flags = enter_critical_section();
+
+ ref_counts[PERIPH_WIFI_BT_COMMON_MODULE]--;
+
+ if (ref_counts[PERIPH_WIFI_BT_COMMON_MODULE] == 0)
+ {
+ modifyreg32(SYSTEM_WIFI_CLK_EN_REG,
+ SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M, 0);
+ modifyreg32(SYSTEM_CORE_RST_EN_REG, 0, 0);
+ }
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: esp32s3_perip_clk_init
+ *
+ * Description:
+ * This function disables clock of useless peripherals when cpu starts.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR esp32s3_perip_clk_init(void)
+{
+ uint32_t common_perip_clk;
+ uint32_t common_perip_clk1 = 0;
+ uint32_t hwcrypto_perip_clk;
+ uint32_t wifi_bt_sdio_clk;
+
+#ifndef CONFIG_SMP
+ soc_reset_reason_t rst_reas[1];
+#else
+ soc_reset_reason_t rst_reas[2];
+#endif
+
+ rst_reas[0] = esp_rom_get_reset_reason(0);
+#ifdef CONFIG_SMP
+ rst_reas[1] = esp_rom_get_reset_reason(1);
+#endif
+
+ /* For reason that only reset CPU, do not disable the clocks
+ * that have been enabled before reset.
+ */
+
+ if ((rst_reas[0] == RESET_REASON_CPU0_MWDT0 ||
+ rst_reas[0] == RESET_REASON_CPU0_SW ||
+ rst_reas[0] == RESET_REASON_CPU0_RTC_WDT ||
+ rst_reas[0] == RESET_REASON_CPU0_MWDT1)
+#ifdef CONFIG_SMP
+ || (rst_reas[1] == RESET_REASON_CPU1_MWDT0 ||
+ rst_reas[1] == RESET_REASON_CPU1_SW ||
+ rst_reas[1] == RESET_REASON_CPU1_RTC_WDT ||
+ rst_reas[1] == RESET_REASON_CPU1_MWDT1)
+#endif
+ )
+ {
+ common_perip_clk = ~getreg32(SYSTEM_PERIP_CLK_EN0_REG);
+ hwcrypto_perip_clk = ~getreg32(SYSTEM_PERIP_CLK_EN1_REG);
+ wifi_bt_sdio_clk = ~getreg32(SYSTEM_WIFI_CLK_EN_REG);
+ }
+ else
+ {
+ common_perip_clk = SYSTEM_WDG_CLK_EN |
+ SYSTEM_I2S0_CLK_EN |
+#ifndef CONFIG_UART0_SERIAL_CONSOLE
+ SYSTEM_UART_CLK_EN |
+#endif
+#ifndef CONFIG_UART1_SERIAL_CONSOLE
+ SYSTEM_UART1_CLK_EN |
+#endif
+#ifndef CONFIG_UART2_SERIAL_CONSOLE
+ SYSTEM_UART2_CLK_EN |
+#endif
+ SYSTEM_USB_CLK_EN |
+ SYSTEM_SPI2_CLK_EN |
+ SYSTEM_I2C_EXT0_CLK_EN |
+ SYSTEM_UHCI0_CLK_EN |
+ SYSTEM_RMT_CLK_EN |
+ SYSTEM_PCNT_CLK_EN |
+ SYSTEM_LEDC_CLK_EN |
+ SYSTEM_TIMERGROUP1_CLK_EN |
+ SYSTEM_SPI3_CLK_EN |
+ SYSTEM_SPI4_CLK_EN |
+ SYSTEM_PWM0_CLK_EN |
+ SYSTEM_TWAI_CLK_EN |
+ SYSTEM_PWM1_CLK_EN |
+ SYSTEM_I2S1_CLK_EN |
+ SYSTEM_SPI2_DMA_CLK_EN |
+ SYSTEM_SPI3_DMA_CLK_EN |
+ SYSTEM_PWM2_CLK_EN |
+ SYSTEM_PWM3_CLK_EN;
+ common_perip_clk1 = 0;
+ hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN |
+ SYSTEM_CRYPTO_SHA_CLK_EN |
+ SYSTEM_CRYPTO_RSA_CLK_EN;
+ wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |
+ SYSTEM_WIFI_CLK_BT_EN_M |
+ SYSTEM_WIFI_CLK_I2C_CLK_EN |
+ SYSTEM_WIFI_CLK_UNUSED_BIT12 |
+ SYSTEM_WIFI_CLK_SDIO_HOST_EN;
+ }
+
+ /* Reset the communication peripherals like I2C, SPI, UART, I2S
+ * and bring them to known state.
+ */
+
+ common_perip_clk |= SYSTEM_I2S0_CLK_EN |
+#ifndef CONFIG_UART0_SERIAL_CONSOLE
+ SYSTEM_UART_CLK_EN |
+#endif
+#ifndef CONFIG_UART1_SERIAL_CONSOLE
+ SYSTEM_UART1_CLK_EN |
+#endif
+#ifndef CONFIG_UART2_SERIAL_CONSOLE
+ SYSTEM_UART2_CLK_EN |
+#endif
+ SYSTEM_USB_CLK_EN |
+ SYSTEM_SPI2_CLK_EN |
+ SYSTEM_I2C_EXT0_CLK_EN |
+ SYSTEM_UHCI0_CLK_EN |
+ SYSTEM_RMT_CLK_EN |
+ SYSTEM_UHCI1_CLK_EN |
+ SYSTEM_SPI3_CLK_EN |
+ SYSTEM_SPI4_CLK_EN |
+ SYSTEM_I2C_EXT1_CLK_EN |
+ SYSTEM_I2S1_CLK_EN |
+ SYSTEM_SPI2_DMA_CLK_EN |
+ SYSTEM_SPI3_DMA_CLK_EN;
+ common_perip_clk1 = 0;
+
+ /* Disable some peripheral clocks. */
+
+ modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk, 0);
+ modifyreg32(SYSTEM_PERIP_RST_EN0_REG, 0, common_perip_clk);
+
+ modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1, 0);
+ modifyreg32(SYSTEM_PERIP_RST_EN1_REG, 0, common_perip_clk1);
+
+ /* Disable hardware crypto clocks. */
+
+ modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk, 0);
+ modifyreg32(SYSTEM_PERIP_RST_EN1_REG, 0, hwcrypto_perip_clk);
+
+ /* Force clear backup dma reset signal. This is a fix to the backup dma
+ * implementation in the ROM, the reset signal was not cleared when the
+ * backup dma was started, which caused the backup dma operation to fail.
+ */
+
+ modifyreg32(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_PERI_BACKUP_RST, 0);
+
+ /* Disable WiFi/BT/SDIO clocks. */
+
+ modifyreg32(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk, 0);
+ modifyreg32(SYSTEM_WIFI_CLK_EN_REG, 0, SYSTEM_WIFI_CLK_EN);
+
+ /* Set WiFi light sleep clock source to RTC slow clock */
+
+ REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
+ modifyreg32(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M, 0);
+ modifyreg32(SYSTEM_BT_LPCK_DIV_FRAC_REG, 0, SYSTEM_LPCLK_SEL_RTC_SLOW);
+
+ /* Enable RNG clock. */
+
+ esp32s3_periph_module_enable(PERIPH_RNG_MODULE);
+
+ /* Enable TimerGroup 0 clock to ensure its reference counter will never
+ * be decremented to 0 during normal operation and preventing it from
+ * being disabled.
+ * If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
+ * registers (Flashboot protection included) will be reenabled, and some
+ * seconds later, will trigger an unintended reset.
+ */
+
+ esp32s3_periph_module_enable(PERIPH_TIMG0_MODULE);
+}
diff --git a/arch/xtensa/src/esp32s3/esp32s3_periph.h b/arch/xtensa/src/esp32s3/esp32s3_periph.h
new file mode 100644
index 0000000000..5741edec49
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_periph.h
@@ -0,0 +1,199 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_periph.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PERIPH_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PERIPH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <sys/types.h>
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+typedef enum
+{
+ PERIPH_LEDC_MODULE = 0,
+ PERIPH_UART0_MODULE,
+ PERIPH_UART1_MODULE,
+ PERIPH_UART2_MODULE,
+ PERIPH_USB_MODULE,
+ PERIPH_I2C0_MODULE,
+ PERIPH_I2C1_MODULE,
+ PERIPH_I2S0_MODULE,
+ PERIPH_I2S1_MODULE,
+ PERIPH_LCD_CAM_MODULE,
+ PERIPH_TIMG0_MODULE,
+ PERIPH_TIMG1_MODULE,
+ PERIPH_PWM0_MODULE,
+ PERIPH_PWM1_MODULE,
+ PERIPH_PWM2_MODULE,
+ PERIPH_PWM3_MODULE,
+ PERIPH_UHCI0_MODULE,
+ PERIPH_UHCI1_MODULE,
+ PERIPH_RMT_MODULE,
+ PERIPH_PCNT_MODULE,
+ PERIPH_SPI_MODULE,
+ PERIPH_SPI2_MODULE,
+ PERIPH_SPI3_MODULE,
+ PERIPH_SDMMC_MODULE,
+ PERIPH_TWAI_MODULE,
+ PERIPH_RNG_MODULE,
+ PERIPH_WIFI_MODULE,
+ PERIPH_BT_MODULE,
+ PERIPH_WIFI_BT_COMMON_MODULE,
+ PERIPH_BT_BASEBAND_MODULE,
+ PERIPH_BT_LC_MODULE,
+ PERIPH_AES_MODULE,
+ PERIPH_SHA_MODULE,
+ PERIPH_HMAC_MODULE,
+ PERIPH_DS_MODULE,
+ PERIPH_RSA_MODULE,
+ PERIPH_SYSTIMER_MODULE,
+ PERIPH_GDMA_MODULE,
+ PERIPH_DEDIC_GPIO_MODULE,
+ PERIPH_SARADC_MODULE,
+ PERIPH_TEMPSENSOR_MODULE,
+ PERIPH_MODULE_MAX
+} esp32s3_periph_module_t;
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_periph_module_enable
+ *
+ * Description:
+ * Enable peripheral module
+ *
+ * Input Parameters:
+ * periph - Periph module (one of enum esp32s3_periph_module_t values)
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp32s3_periph_module_enable(esp32s3_periph_module_t periph);
+
+/****************************************************************************
+ * Name: esp32s3_periph_module_disable
+ *
+ * Description:
+ * Disable peripheral module
+ *
+ * Input Parameters:
+ * periph - Periph module (one of enum esp32s3_periph_module_t values)
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp32s3_periph_module_disable(esp32s3_periph_module_t periph);
+
+/****************************************************************************
+ * Name: esp32s3_periph_module_reset
+ *
+ * Description:
+ * Reset peripheral module by asserting and de-asserting the reset signal.
+ *
+ * Input Parameters:
+ * periph - Periph module (one of the esp32s3_periph_module_t values)
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp32s3_periph_module_reset(esp32s3_periph_module_t periph);
+
+/****************************************************************************
+ * Name: esp32s3_periph_wifi_bt_common_module_enable
+ *
+ * Description:
+ * Enable Wi-Fi and BT common module.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp32s3_periph_wifi_bt_common_module_enable(void);
+
+/****************************************************************************
+ * Name: esp32s3_periph_wifi_bt_common_module_disable
+ *
+ * Description:
+ * Disable Wi-Fi and BT common module.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp32s3_periph_wifi_bt_common_module_disable(void);
+
+/****************************************************************************
+ * Name: esp32s3_perip_clk_init
+ *
+ * Description:
+ * This function disables clock of useless peripherals when cpu starts.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp32s3_perip_clk_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+#undef EXTERN
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PERIPH_H */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_reset_reasons.h b/arch/xtensa/src/esp32s3/esp32s3_reset_reasons.h
new file mode 100644
index 0000000000..29491c88dc
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_reset_reasons.h
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_reset_reasons.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RESET_REASONS_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RESET_REASONS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/**
+ *+-------------------------------Terminology-------------------------------+
+ *| |
+ *| CPU Reset: Reset CPU core only, once reset done, CPU will execute |
+ *| from reset vector |
+ *| |
+ *| Core Reset: Reset the whole digital system except RTC sub-system |
+ *| |
+ *| System Reset: Reset the whole digital system, including RTC sub-system |
+ *| |
+ *| Chip Reset: Reset the whole chip, including the analog part |
+ *| |
+ *+-------------------------------------------------------------------------+
+ */
+
+/**
+ * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
+ * @note refer to TRM: <Reset and Clock> chapter
+ */
+
+typedef enum
+{
+ RESET_REASON_CHIP_POWER_ON = 0x01, /* Power on reset */
+ RESET_REASON_CHIP_BROWN_OUT = 0x01, /* VDD voltage is not stable and resets the chip */
+ RESET_REASON_CHIP_SUPER_WDT = 0x01, /* Super watch dog resets the chip */
+ RESET_REASON_CORE_SW = 0x03, /* Software resets the digital core by RTC_CNTL_SW_SYS_RST */
+ RESET_REASON_CORE_DEEP_SLEEP = 0x05, /* Deep sleep reset the digital core */
+ RESET_REASON_CORE_MWDT0 = 0x07, /* Main watch dog 0 resets digital core */
+ RESET_REASON_CORE_MWDT1 = 0x08, /* Main watch dog 1 resets digital core */
+ RESET_REASON_CORE_RTC_WDT = 0x09, /* RTC watch dog resets digital core */
+ RESET_REASON_CPU0_MWDT0 = 0x0b, /* Main watch dog 0 resets CPU 0 */
+ RESET_REASON_CPU1_MWDT0 = 0x0b, /* Main watch dog 0 resets CPU 1 */
+ RESET_REASON_CPU0_SW = 0x0c, /* Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST */
+ RESET_REASON_CPU1_SW = 0x0c, /* Software resets CPU 1 by RTC_CNTL_SW_APPCPU_RST */
+ RESET_REASON_CPU0_RTC_WDT = 0x0d, /* RTC watch dog resets CPU 0 */
+ RESET_REASON_CPU1_RTC_WDT = 0x0d, /* RTC watch dog resets CPU 1 */
+ RESET_REASON_SYS_BROWN_OUT = 0x0f, /* VDD voltage is not stable and resets the digital core */
+ RESET_REASON_SYS_RTC_WDT = 0x10, /* RTC watch dog resets digital core and rtc module */
+ RESET_REASON_CPU0_MWDT1 = 0x11, /* Main watch dog 1 resets CPU 0 */
+ RESET_REASON_CPU1_MWDT1 = 0x11, /* Main watch dog 1 resets CPU 1 */
+ RESET_REASON_SYS_SUPER_WDT = 0x12, /* Super watch dog resets the digital core and rtc module */
+ RESET_REASON_SYS_CLK_GLITCH = 0x13, /* Glitch on clock resets the digital core and rtc module */
+ RESET_REASON_CORE_EFUSE_CRC = 0x14, /* eFuse CRC error resets the digital core */
+ RESET_REASON_CORE_USB_UART = 0x15, /* USB UART resets the digital core */
+ RESET_REASON_CORE_USB_JTAG = 0x16, /* USB JTAG resets the digital core */
+ RESET_REASON_CORE_PWR_GLITCH = 0x17, /* Glitch on power resets the digital core */
+} soc_reset_reason_t;
+
+#ifdef __cplusplus
+}
+#endif
+#undef EXTERN
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RESET_REASONS_H */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_start.c b/arch/xtensa/src/esp32s3/esp32s3_start.c
index 7a377e599c..d2b0bb9c58 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_start.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_start.c
@@ -37,6 +37,7 @@
#include "esp32s3_lowputc.h"
#include "esp32s3_clockconfig.h"
#include "esp32s3_region.h"
+#include "esp32s3_periph.h"
#include "esp32s3_spiram.h"
#include "esp32s3_wdt.h"
#ifdef CONFIG_BUILD_PROTECTED
@@ -325,6 +326,10 @@ void noreturn_function IRAM_ATTR __esp32s3_start(void)
esp32s3_clockconfig();
+ /* Initialize peripherals parameters */
+
+ esp32s3_perip_clk_init();
+
#ifndef CONFIG_SUPPRESS_UART_CONFIG
/* Configure the UART so we can get debug output */
diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_system.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_system.h
index ce9d514916..4fbe00207f 100644
--- a/arch/xtensa/src/esp32s3/hardware/esp32s3_system.h
+++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_system.h
@@ -299,14 +299,14 @@
#define SYSTEM_PWM1_CLK_EN_V 0x00000001
#define SYSTEM_PWM1_CLK_EN_S 20
-/* SYSTEM_CAN_CLK_EN : R/W; bitpos: [19]; default: 0;
+/* SYSTEM_TWAI_CLK_EN : R/W; bitpos: [19]; default: 0;
* Set 1 to enable CAN clock
*/
-#define SYSTEM_CAN_CLK_EN (BIT(19))
-#define SYSTEM_CAN_CLK_EN_M (SYSTEM_CAN_CLK_EN_V << SYSTEM_CAN_CLK_EN_S)
-#define SYSTEM_CAN_CLK_EN_V 0x00000001
-#define SYSTEM_CAN_CLK_EN_S 19
+#define SYSTEM_TWAI_CLK_EN (BIT(19))
+#define SYSTEM_TWAI_CLK_EN_M (SYSTEM_TWAI_CLK_EN_V << SYSTEM_TWAI_CLK_EN_S)
+#define SYSTEM_TWAI_CLK_EN_V 0x00000001
+#define SYSTEM_TWAI_CLK_EN_S 19
/* SYSTEM_I2C_EXT1_CLK_EN : R/W; bitpos: [18]; default: 0;
* Set 1 to enable I2C_EXT1 clock
@@ -698,14 +698,14 @@
#define SYSTEM_PWM1_RST_V 0x00000001
#define SYSTEM_PWM1_RST_S 20
-/* SYSTEM_CAN_RST : R/W; bitpos: [19]; default: 0;
+/* SYSTEM_TWAI_RST : R/W; bitpos: [19]; default: 0;
* Set 1 to let CAN reset
*/
-#define SYSTEM_CAN_RST (BIT(19))
-#define SYSTEM_CAN_RST_M (SYSTEM_CAN_RST_V << SYSTEM_CAN_RST_S)
-#define SYSTEM_CAN_RST_V 0x00000001
-#define SYSTEM_CAN_RST_S 19
+#define SYSTEM_TWAI_RST (BIT(19))
+#define SYSTEM_TWAI_RST_M (SYSTEM_TWAI_RST_V << SYSTEM_TWAI_RST_S)
+#define SYSTEM_TWAI_RST_V 0x00000001
+#define SYSTEM_TWAI_RST_S 19
/* SYSTEM_I2C_EXT1_RST : R/W; bitpos: [18]; default: 0;
* Set 1 to let I2C_EXT1 reset
[nuttx] 09/12: esp32s3/wifi: Enable peripheral interrupt to the same CPU interrupt
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 7d605551cd0b9b3cea686146b693a0f2e8541cf5
Author: Tiago Medicci Serrano <ti...@espressif.com>
AuthorDate: Tue Aug 8 10:20:15 2023 -0300
esp32s3/wifi: Enable peripheral interrupt to the same CPU interrupt
The low-level Wi-Fi driver registers two peripheral interrupts to
the same CPU interrupt. Although the registered ISR is the same for
both peripherals interrupt, it's needed to call `up_enable_irq` to
ensure that the interrupt matrix is being set accordingly.
Please note that the current implementation of the ESP32-S3's IRQ
driver - although allow us to set a callback for each IRQ, which
represents the peripherals interrupt - doesn't allow us to call
both callbacks when these IRQs refers to a same CPU interrupt.
`g_cpu0_intmap` (or `g_cpu1_intmap`) associates each CPU interrupt
to a single IRQ/peripheral and, then, when a CPU interrupt is
triggered, only the last registered IRQ's callback will be called.
This isn't a problem here because 1) the registered callback is the
same for both IRQ's (in fact, it considers the CPU interrupt) and
2) we know in advance which peripheral interrupts will be attached
to which CPU interrupt and, then, we can set them directly.
---
arch/xtensa/include/esp32s3/irq.h | 1 +
arch/xtensa/src/esp32s3/esp32s3_irq.c | 4 +++-
arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c | 19 ++++++++++++++-----
3 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/arch/xtensa/include/esp32s3/irq.h b/arch/xtensa/include/esp32s3/irq.h
index 45d2e0f4ad..ee9e6b799d 100644
--- a/arch/xtensa/include/esp32s3/irq.h
+++ b/arch/xtensa/include/esp32s3/irq.h
@@ -446,6 +446,7 @@
#define ESP32S3_CPUINT_NMISET 0x00004000
#define ESP32S3_CPUINT_MAC 0
+#define ESP32S3_CPUINT_PWR 0
#define ESP32S3_CPUINT_RWBLE 5
#define ESP32S3_CPUINT_TIMER0 6
#define ESP32S3_CPUINT_SOFTWARE0 7
diff --git a/arch/xtensa/src/esp32s3/esp32s3_irq.c b/arch/xtensa/src/esp32s3/esp32s3_irq.c
index 278212c61d..428f8eb31b 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_irq.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_irq.c
@@ -431,6 +431,7 @@ void up_irqinitialize(void)
#ifdef CONFIG_ESP32S3_WIFI
g_irqmap[ESP32S3_IRQ_MAC] = IRQ_MKMAP(0, ESP32S3_CPUINT_MAC);
+ g_irqmap[ESP32S3_IRQ_PWR] = IRQ_MKMAP(0, ESP32S3_CPUINT_PWR);
#endif
#ifdef CONFIG_ESP32S3_BLE
@@ -445,7 +446,8 @@ void up_irqinitialize(void)
/* Reserve CPU0 interrupt for some special drivers */
#ifdef CONFIG_ESP32S3_WIFI
- g_cpu0_intmap[ESP32S3_CPUINT_MAC] = CPUINT_ASSIGN(ESP32S3_IRQ_MAC);
+ g_cpu0_intmap[ESP32S3_CPUINT_MAC] = CPUINT_ASSIGN(ESP32S3_IRQ_MAC);
+ g_cpu0_intmap[ESP32S3_CPUINT_PWR] = CPUINT_ASSIGN(ESP32S3_IRQ_PWR);
xtensa_enable_cpuint(&g_intenable[0], 1 << ESP32S3_CPUINT_MAC);
#endif
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
index ccddf73815..d4fd889910 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
@@ -740,14 +740,14 @@ static void esp_set_isr(int32_t n, void *f, void *arg)
struct irq_adpt *adapter;
int irq = n + XTENSA_IRQ_FIRSTPERIPH;
- wlinfo("n=%d f=%p arg=%p irq=%d\n", n, f, arg, irq);
+ wlinfo("n=%d f=%p arg=%p", n, f, arg);
if (g_irqvector[irq].handler &&
g_irqvector[irq].handler != irq_unexpected_isr)
{
wlinfo("irq=%d has been set handler=%p\n", irq,
g_irqvector[irq].handler);
- return ;
+ return;
}
tmp = sizeof(struct irq_adpt);
@@ -756,18 +756,26 @@ static void esp_set_isr(int32_t n, void *f, void *arg)
{
wlerr("Failed to alloc %d memory\n", tmp);
assert(0);
- return ;
+ return;
}
adapter->func = f;
adapter->arg = arg;
- ret = irq_attach(irq, esp_int_adpt_cb, adapter);
+ ret = irq_attach(ESP32S3_IRQ_MAC, esp_int_adpt_cb, adapter);
if (ret)
{
wlerr("Failed to attach IRQ %d\n", irq);
assert(0);
- return ;
+ return;
+ }
+
+ ret = irq_attach(ESP32S3_IRQ_PWR, esp_int_adpt_cb, adapter);
+ if (ret)
+ {
+ wlerr("Failed to attach IRQ %d\n", irq);
+ assert(0);
+ return;
}
}
@@ -792,6 +800,7 @@ static void esp32s3_ints_on(uint32_t mask)
wlinfo("INFO mask=%08x irq=%d\n", mask, irq);
up_enable_irq(ESP32S3_IRQ_MAC);
+ up_enable_irq(ESP32S3_IRQ_PWR);
}
/****************************************************************************
[nuttx] 05/12: esp32s3/wlan: check if the network device's IOB isn't null
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 6589887284a48b2872e5f792cbfd83aa7a5019ee
Author: Tiago Medicci Serrano <ti...@espressif.com>
AuthorDate: Fri Aug 4 17:12:37 2023 -0300
esp32s3/wlan: check if the network device's IOB isn't null
Before adding the upper layer network device's IOB to the TX queue
of the wireless driver, check if it isn't null.
---
arch/xtensa/src/esp32s3/esp32s3_wlan.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wlan.c b/arch/xtensa/src/esp32s3/esp32s3_wlan.c
index b7742ff9d0..44d8a49c64 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_wlan.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_wlan.c
@@ -269,7 +269,11 @@ static void wlan_ipv6multicast(struct wlan_priv_s *priv);
static inline void wlan_cache_txpkt_tail(struct wlan_priv_s *priv)
{
- iob_tryadd_queue(priv->dev.d_iob, &priv->txb);
+ if (priv->dev.d_iob)
+ {
+ iob_tryadd_queue(priv->dev.d_iob, &priv->txb);
+ }
+
netdev_iob_clear(&priv->dev);
}
[nuttx] 07/12: esp32s3/wlan: Always run `wlan_rxpoll` work queue
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 33f03fc98c0fe5cd5ce2fc99bbd684fb2d8c790b
Author: Tiago Medicci Serrano <ti...@espressif.com>
AuthorDate: Fri Aug 4 17:22:05 2023 -0300
esp32s3/wlan: Always run `wlan_rxpoll` work queue
Even if we were unable to get a free IOB, trigger the work queue
to make sure that no old packet is waiting to be handled by the
network upper layers.
---
arch/xtensa/src/esp32s3/esp32s3_wlan.c | 16 +++++-----------
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wlan.c b/arch/xtensa/src/esp32s3/esp32s3_wlan.c
index 9a27d1dda9..70f0b7f9dc 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_wlan.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_wlan.c
@@ -448,27 +448,21 @@ static int wlan_rx_done(struct wlan_priv_s *priv, void *buffer,
goto out;
}
+out:
+
if (eb != NULL)
{
esp_wifi_free_eb(eb);
}
- if (work_available(&priv->rxwork))
- {
- work_queue(WLAN_WORK, &priv->rxwork, wlan_rxpoll, priv, 0);
- }
-
- return 0;
-
-out:
- if (iob != NULL)
+ if (ret != OK && iob != NULL)
{
iob_free_chain(iob);
}
- if (eb != NULL)
+ if (work_available(&priv->rxwork))
{
- esp_wifi_free_eb(eb);
+ work_queue(WLAN_WORK, &priv->rxwork, wlan_rxpoll, priv, 0);
}
wlan_txavail(&priv->dev);
[nuttx] 06/12: esp32s3/wlan: check for all connections on wlan_txpoll
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 012dddf7c960cc8f96f5fb1b20b25456b45da229
Author: Tiago Medicci Serrano <ti...@espressif.com>
AuthorDate: Fri Aug 4 17:16:49 2023 -0300
esp32s3/wlan: check for all connections on wlan_txpoll
This prevents us from getting stuck while polling the different
network structures in `devif_poll_connections`. This is useful for
Wi-Fi/Bluetooth coexistence, specifically.
---
arch/xtensa/src/esp32s3/esp32s3_wlan.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wlan.c b/arch/xtensa/src/esp32s3/esp32s3_wlan.c
index 44d8a49c64..9a27d1dda9 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_wlan.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_wlan.c
@@ -638,11 +638,7 @@ static int wlan_txpoll(struct net_driver_s *dev)
wlan_cache_txpkt_tail(priv);
wlan_transmit(priv);
- /* If zero is returned, the polling will continue until
- * all connections have been examined.
- */
-
- return 1;
+ return OK;
}
/****************************************************************************
[nuttx] 04/12: esp32s3/hardware: Update `regi2c_ctrl.h` functions name
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit ec4149c61d50d7104cffb699a2bb0d90e5f29ce1
Author: Tiago Medicci Serrano <ti...@espressif.com>
AuthorDate: Tue Aug 8 08:50:58 2023 -0300
esp32s3/hardware: Update `regi2c_ctrl.h` functions name
---
arch/xtensa/src/esp32s3/hardware/regi2c_ctrl.h | 27 ++++++++++++++------------
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/arch/xtensa/src/esp32s3/hardware/regi2c_ctrl.h b/arch/xtensa/src/esp32s3/hardware/regi2c_ctrl.h
index ef6e983c84..180fcc28b4 100644
--- a/arch/xtensa/src/esp32s3/hardware/regi2c_ctrl.h
+++ b/arch/xtensa/src/esp32s3/hardware/regi2c_ctrl.h
@@ -37,17 +37,20 @@
#define I2C_MST_ANA_CONF0_REG 0x6000E040
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
+#define I2C_MST_BBPLL_CAL_DONE (BIT(24))
/* ROM functions which read/write internal control bus */
-extern uint8_t rom_i2c_readreg(uint8_t block, uint8_t host_id,
- uint8_t reg_add);
-extern uint8_t rom_i2c_readreg_mask(uint8_t block, uint8_t host_id,
- uint8_t reg_add, uint8_t msb, uint8_t lsb);
-extern void rom_i2c_writereg(uint8_t block, uint8_t host_id,
- uint8_t reg_add, uint8_t data);
-extern void rom_i2c_writereg_mask(uint8_t block, uint8_t host_id,
- uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
+extern uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id,
+ uint8_t reg_add);
+extern uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id,
+ uint8_t reg_add, uint8_t msb,
+ uint8_t lsb);
+extern void esp_rom_regi2c_write(uint8_t block, uint8_t host_id,
+ uint8_t reg_add, uint8_t data);
+extern void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id,
+ uint8_t reg_add, uint8_t msb,
+ uint8_t lsb, uint8_t data);
/* Convenience macros for the above functions, these use register
* definitions from regi2c_bbpll.h/regi2c_dig_reg.h/regi2c_lp_bias.h/
@@ -55,15 +58,15 @@ extern void rom_i2c_writereg_mask(uint8_t block, uint8_t host_id,
*/
#define REGI2C_WRITE_MASK(block, reg_add, indata) \
- rom_i2c_writereg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
+ esp_rom_regi2c_write_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
#define REGI2C_READ_MASK(block, reg_add) \
- rom_i2c_readreg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
+ esp_rom_regi2c_read_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
#define REGI2C_WRITE(block, reg_add, indata) \
- rom_i2c_writereg(block, block##_HOSTID, reg_add, indata)
+ esp_rom_regi2c_write(block, block##_HOSTID, reg_add, indata)
#define REGI2C_READ(block, reg_add) \
- rom_i2c_readreg(block, block##_HOSTID, reg_add)
+ esp_rom_regi2c_read(block, block##_HOSTID, reg_add)
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_CTRL_H */
[nuttx] 10/12: esp32s3: Implement the Wi-Fi/BLE coexistence
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 01b6c87b15e235dfe71ba2171616241d08b764e9
Author: Tiago Medicci Serrano <ti...@espressif.com>
AuthorDate: Mon Aug 7 14:38:23 2023 -0300
esp32s3: Implement the Wi-Fi/BLE coexistence
ESP32-S3 has only one 2.4 GHz ISM band RF module, which is shared
by Bluetooth and Wi-Fi, so Bluetooth can’t receive or transmit data
while Wi-Fi is receiving or transmitting data and vice versa.
Under such circumstances, ESP32-S3 uses the time-division
multiplexing method to receive and transmit packets.
---
arch/xtensa/src/esp32s3/Kconfig | 44 +-
arch/xtensa/src/esp32s3/Wireless.mk | 7 +
arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c | 4 +
arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c | 667 ++++++++++++++++-----
arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h | 2 +-
.../esp32s3-devkit/configs/blewifi/defconfig | 100 +++
.../esp32s3/esp32s3-devkit/src/esp32s3_bringup.c | 4 +
7 files changed, 674 insertions(+), 154 deletions(-)
diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig
index 389bb7d80e..2e69cf1c0a 100644
--- a/arch/xtensa/src/esp32s3/Kconfig
+++ b/arch/xtensa/src/esp32s3/Kconfig
@@ -472,8 +472,10 @@ endmenu # ESP32-S3 Peripheral Selection
menuconfig ESP32S3_WIFI_BT_COEXIST
bool "Wi-Fi and BT coexist"
+ default y if ESP32S3_WIFI && ESP32S3_BLE
default n
depends on ESP32S3_WIFI && ESP32S3_BLE
+ select ESP32S3_WIFI_STA_DISCONNECT_PM
menu "SPI RAM Configuration"
depends on ESP32S3_SPIRAM
@@ -948,13 +950,51 @@ config ESP32S3_WIFI_SCAN_RESULT_SIZE
config ESP32S3_WIFI_STA_DISCONNECT_PM
bool "Power Management for station when disconnected"
- default n
+ default y
---help---
Select this option to enable power management for station when disconnected.
Chip will do modem-sleep when RF module is not in use anymore.
-config EXAMPLE_WIFI_LISTEN_INTERVAL
+choice ESP32S3_POWER_SAVE_MODE
+ prompt "Wi-Fi Power save mode"
+ default ESP32S3_POWER_SAVE_MIN_MODEM if ESP32S3_WIFI_BT_COEXIST
+ default ESP32S3_POWER_SAVE_NONE
+ ---help---
+ Wi-Fi supports the Modem-sleep mode which refers to the legacy power-saving mode in the IEEE 802.11 protocol.
+ Modem-sleep mode works in station-only mode and the station must connect to the AP first. If the Modem-sleep
+ mode is enabled, station will switch between active and sleep state periodically. In sleep state, RF, PHY and
+ BB are turned off in order to reduce power consumption. Station can keep connection with AP in modem-sleep mode.
+
+ Modem-sleep mode includes minimum and maximum power-saving modes.
+
+ In minimum power-saving mode, station wakes
+ up every DTIM to receive beacon. Broadcast data will not be lost because it is transmitted after DTIM.
+ However, it cannot save much more power if DTIM is short for DTIM is determined by AP.
+
+ In maximum power-saving mode, station wakes up in every listen interval to receive beacon. This listen interval
+ can be set to be longer than the AP DTIM period. Broadcast data may be lost because station may be in sleep
+ state at DTIM time. If listen interval is longer, more power is saved, but broadcast data is more easy to lose.
+ Listen interval can be configured by setting ESP32S3_WIFI_LISTEN_INTERVAL.
+
+ ESP32S3_POWER_SAVE_NONE disables Modem-sleep mode entirely. Disabling it increases power consumption, but
+ minimizes the delay in receiving Wi-Fi data in real time. When Modem-sleep mode is enabled, the delay in
+ receiving Wi-Fi data may be the same as the DTIM cycle (minimum power-saving mode) or the listening interval
+ (maximum power-saving mode). Setting ESP32S3_POWER_SAVE_NONE is suitable when high throughput is required.
+
+config ESP32S3_POWER_SAVE_NONE
+ bool "No power save"
+
+config ESP32S3_POWER_SAVE_MIN_MODEM
+ bool "Minimum modem power saving."
+
+config ESP32S3_POWER_SAVE_MAX_MODEM
+ bool "Maximum modem power saving"
+
+endchoice # ESP32S3_POWER_SAVE_MODE
+
+config ESP32S3_WIFI_LISTEN_INTERVAL
int "Wi-Fi listen interval"
+ depends on ESP32S3_POWER_SAVE_MAX_MODEM
default 3
---help---
Interval for station to listen to beacon from AP. The unit of listen interval is one beacon interval.
diff --git a/arch/xtensa/src/esp32s3/Wireless.mk b/arch/xtensa/src/esp32s3/Wireless.mk
index a9d7749618..987a9257bc 100644
--- a/arch/xtensa/src/esp32s3/Wireless.mk
+++ b/arch/xtensa/src/esp32s3/Wireless.mk
@@ -48,6 +48,7 @@ context:: chip/$(ESP_HAL_3RDPARTY_REPO)
distclean::
$(call DELDIR, chip/$(ESP_HAL_3RDPARTY_REPO))
+INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)include
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)include$(DELIM)esp32c3$(DELIM)include
INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_event$(DELIM)include
@@ -103,13 +104,19 @@ INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
CFLAGS += ${DEFINE_PREFIX}MBEDTLS_CONFIG_FILE="<mbedtls/esp_config.h>"
CHIP_CSRCS += aes.c
+CHIP_CSRCS += aria.c
CHIP_CSRCS += bignum_core.c
CHIP_CSRCS += bignum.c
+CHIP_CSRCS += ccm.c
+CHIP_CSRCS += cipher.c
+CHIP_CSRCS += cipher_wrap.c
+CHIP_CSRCS += cmac.c
CHIP_CSRCS += constant_time.c
CHIP_CSRCS += ctr_drbg.c
CHIP_CSRCS += ecp_curves.c
CHIP_CSRCS += ecp.c
CHIP_CSRCS += entropy.c
+CHIP_CSRCS += gcm.c
CHIP_CSRCS += md.c
CHIP_CSRCS += pkcs5.c
CHIP_CSRCS += platform_util.c
diff --git a/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c
index 5eb7d873f5..1e5c0c2cda 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c
@@ -2663,6 +2663,10 @@ error:
}
#endif
+#if CONFIG_ESP32S3_WIFI_BT_COEXIST
+ coex_disable();
+#endif
+
return ret;
}
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
index d4fd889910..4168a7cf77 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
@@ -70,6 +70,13 @@
# include "esp32s3_pm.h"
#endif
+#ifdef CONFIG_ESP32S3_BLE
+# include "esp32s3_ble_adapter.h"
+# ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+# include "esp_coexist_internal.h"
+# endif
+#endif
+
#include "esp_hal_wifi.h"
/****************************************************************************
@@ -97,6 +104,18 @@
#define ets_timer _ETSTIMER_
+/* CONFIG_POWER_SAVE_MODEM */
+
+#if defined(CONFIG_ESP32S3_POWER_SAVE_MIN_MODEM)
+# define DEFAULT_PS_MODE WIFI_PS_MIN_MODEM
+#elif defined(CONFIG_ESP32S3_POWER_SAVE_MAX_MODEM)
+# define DEFAULT_PS_MODE WIFI_PS_MAX_MODEM
+#elif defined(CONFIG_ESP32S3_POWER_SAVE_NONE)
+# define DEFAULT_PS_MODE WIFI_PS_NONE
+#else
+# define DEFAULT_PS_MODE WIFI_PS_NONE
+#endif
+
/****************************************************************************
* Private Types
****************************************************************************/
@@ -167,6 +186,12 @@ struct nvs_adpt
* Private Function Prototypes
****************************************************************************/
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+static int semphr_take_from_isr_wrapper(void *semphr, void *hptw);
+static int semphr_give_from_isr_wrapper(void *semphr, void *hptw);
+static int is_in_isr_wrapper(void);
+#endif /* CONFIG_ESP32S3_WIFI_BT_COEXIST */
+
static bool wifi_env_is_chip(void);
static void wifi_set_intr(int32_t cpu_no, uint32_t intr_source,
uint32_t intr_num, int32_t intr_prio);
@@ -280,31 +305,30 @@ static void *esp_wifi_calloc(size_t n, size_t size);
static void *esp_wifi_zalloc(size_t size);
static void *esp_wifi_create_queue(int32_t queue_len, int32_t item_size);
static void esp_wifi_delete_queue(void *queue);
-static int wifi_coex_init(void);
-static void wifi_coex_deinit(void);
-static int wifi_coex_enable(void);
-static void wifi_coex_disable(void);
-static uint32_t esp_coex_status_get(void);
-static void esp_coex_condition_set(uint32_t type, bool dissatisfy);
-static int32_t esp_coex_wifi_request(uint32_t event, uint32_t latency,
+static int coex_init_wrapper(void);
+static void coex_deinit_wrapper(void);
+static int coex_enable_wrapper(void);
+static void coex_disable_wrapper(void);
+static uint32_t coex_status_get_wrapper(void);
+static int32_t coex_wifi_request_wrapper(uint32_t event, uint32_t latency,
uint32_t duration);
-static int32_t esp_coex_wifi_release(uint32_t event);
+static int32_t coex_wifi_release_wrapper(uint32_t event);
static unsigned long esp_random_ulong(void);
-static int wifi_coex_wifi_set_channel(uint8_t primary, uint8_t secondary);
-static int wifi_coex_get_event_duration(uint32_t event,
+static int coex_wifi_channel_set_wrapper(uint8_t primary, uint8_t secondary);
+static int coex_event_duration_get_wrapper(uint32_t event,
uint32_t *duration);
-static int wifi_coex_get_pti(uint32_t event, uint8_t *pti);
-static void wifi_coex_clear_schm_status_bit(uint32_t type,
+static int coex_pti_get_wrapper(uint32_t event, uint8_t *pti);
+static void coex_schm_status_bit_clear_wrapper(uint32_t type,
uint32_t status);
-static void wifi_coex_set_schm_status_bit(uint32_t type,
+static void coex_schm_status_bit_set_wrapper(uint32_t type,
uint32_t status);
-static int wifi_coex_set_schm_interval(uint32_t interval);
-static uint32_t wifi_coex_get_schm_interval(void);
-static uint8_t wifi_coex_get_schm_curr_period(void);
-static void *wifi_coex_get_schm_curr_phase(void);
-static int wifi_coex_register_start_cb_wrapper(int (* cb)(void));
-static int wifi_coex_schm_process_restart_wrapper(void);
-static int wifi_coex_schm_register_cb_wrapper(int type, int(*cb)(int));
+static int coex_schm_interval_set_wrapper(uint32_t interval);
+static uint32_t coex_schm_interval_get_wrapper(void);
+static uint8_t coex_schm_curr_period_get_wrapper(void);
+static void *coex_schm_curr_phase_get_wrapper(void);
+static int coex_register_start_cb_wrapper(int (* cb)(void));
+static int coex_schm_process_restart_wrapper(void);
+static int coex_schm_register_cb_wrapper(int type, int(*cb)(int));
/****************************************************************************
* Public Functions declaration
@@ -314,7 +338,6 @@ int64_t esp_timer_get_time(void);
void esp_fill_random(void *buf, size_t len);
uint32_t esp_log_timestamp(void);
uint8_t esp_crc8(const uint8_t *p, uint32_t len);
-void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
/****************************************************************************
* Private Data
@@ -379,6 +402,31 @@ static spinlock_t g_lock;
* Public Data
****************************************************************************/
+/* Wi-Fi and BT coexistence OS adapter data */
+
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+coex_adapter_funcs_t g_coex_adapter_funcs =
+{
+ ._version = COEX_ADAPTER_VERSION,
+ ._task_yield_from_isr = esp_task_yield_from_isr,
+ ._semphr_create = esp_semphr_create,
+ ._semphr_delete = esp_semphr_delete,
+ ._semphr_take_from_isr = semphr_take_from_isr_wrapper,
+ ._semphr_give_from_isr = semphr_give_from_isr_wrapper,
+ ._semphr_take = esp_semphr_take,
+ ._semphr_give = esp_semphr_give,
+ ._is_in_isr = is_in_isr_wrapper,
+ ._malloc_internal = esp_malloc_internal,
+ ._free = esp_free,
+ ._esp_timer_get_time = esp_timer_get_time,
+ ._timer_disarm = esp_timer_disarm,
+ ._timer_done = esp32s3_timer_done,
+ ._timer_setfn = esp_timer_setfn,
+ ._timer_arm_us = esp_timer_arm_us,
+ ._magic = COEX_ADAPTER_MAGIC,
+};
+#endif /* CONFIG_ESP32S3_WIFI_BT_COEXIST */
+
/* Wi-Fi OS adapter data */
wifi_osi_funcs_t g_wifi_osi_funcs =
@@ -481,26 +529,25 @@ wifi_osi_funcs_t g_wifi_osi_funcs =
._wifi_zalloc = esp_wifi_zalloc,
._wifi_create_queue = esp_wifi_create_queue,
._wifi_delete_queue = esp_wifi_delete_queue,
- ._coex_init = wifi_coex_init,
- ._coex_deinit = wifi_coex_deinit,
- ._coex_enable = wifi_coex_enable,
- ._coex_disable = wifi_coex_disable,
- ._coex_status_get = esp_coex_status_get,
- ._coex_condition_set = esp_coex_condition_set,
- ._coex_wifi_request = esp_coex_wifi_request,
- ._coex_wifi_release = esp_coex_wifi_release,
- ._coex_wifi_channel_set = wifi_coex_wifi_set_channel,
- ._coex_event_duration_get = wifi_coex_get_event_duration,
- ._coex_pti_get = wifi_coex_get_pti,
- ._coex_schm_status_bit_clear = wifi_coex_clear_schm_status_bit,
- ._coex_schm_status_bit_set = wifi_coex_set_schm_status_bit,
- ._coex_schm_interval_set = wifi_coex_set_schm_interval,
- ._coex_schm_interval_get = wifi_coex_get_schm_interval,
- ._coex_schm_curr_period_get = wifi_coex_get_schm_curr_period,
- ._coex_schm_curr_phase_get = wifi_coex_get_schm_curr_phase,
- ._coex_register_start_cb = wifi_coex_register_start_cb_wrapper,
- ._coex_schm_process_restart = wifi_coex_schm_process_restart_wrapper,
- ._coex_schm_register_cb = wifi_coex_schm_register_cb_wrapper,
+ ._coex_init = coex_init_wrapper,
+ ._coex_deinit = coex_deinit_wrapper,
+ ._coex_enable = coex_enable_wrapper,
+ ._coex_disable = coex_disable_wrapper,
+ ._coex_status_get = coex_status_get_wrapper,
+ ._coex_wifi_request = coex_wifi_request_wrapper,
+ ._coex_wifi_release = coex_wifi_release_wrapper,
+ ._coex_wifi_channel_set = coex_wifi_channel_set_wrapper,
+ ._coex_event_duration_get = coex_event_duration_get_wrapper,
+ ._coex_pti_get = coex_pti_get_wrapper,
+ ._coex_schm_status_bit_clear = coex_schm_status_bit_clear_wrapper,
+ ._coex_schm_status_bit_set = coex_schm_status_bit_set_wrapper,
+ ._coex_schm_interval_set = coex_schm_interval_set_wrapper,
+ ._coex_schm_interval_get = coex_schm_interval_get_wrapper,
+ ._coex_schm_curr_period_get = coex_schm_curr_period_get_wrapper,
+ ._coex_schm_curr_phase_get = coex_schm_curr_phase_get_wrapper,
+ ._coex_register_start_cb = coex_register_start_cb_wrapper,
+ ._coex_schm_process_restart = coex_schm_process_restart_wrapper,
+ ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
};
@@ -957,7 +1004,7 @@ static void IRAM_ATTR esp_wifi_int_restore(void *wifi_int_mux, uint32_t tmp)
* Name: esp_task_yield_from_isr
*
* Description:
- * Do nothing in NuttX
+ * Perform a solicited context switch on FreeRTOS. Do nothing in NuttX.
*
* Input Parameters:
* None
@@ -969,7 +1016,6 @@ static void IRAM_ATTR esp_wifi_int_restore(void *wifi_int_mux, uint32_t tmp)
static void IRAM_ATTR esp_task_yield_from_isr(void)
{
- /* Do nothing */
}
/****************************************************************************
@@ -1496,7 +1542,7 @@ static int32_t esp_queue_send(void *queue, void *item, uint32_t ticks)
* Input Parameters:
* queue - Message queue data pointer
* item - Message data pointer
- * hptw - No mean
+ * hptw - Unused.
*
* Returned Value:
* True if success or false if fail
@@ -1505,9 +1551,7 @@ static int32_t esp_queue_send(void *queue, void *item, uint32_t ticks)
static int32_t esp_queue_send_from_isr(void *queue, void *item, void *hptw)
{
- /* Force to set the value to be false */
-
- *((int *)hptw) = false;
+ *(int *)hptw = 0;
return esp_queue_send_generic(queue, item, 0, 0);
}
@@ -2064,6 +2108,7 @@ static void esp_evt_work_cb(void *arg)
irqstate_t flags;
struct evt_adpt *evt_adpt;
struct wifi_notify *notify;
+ wifi_ps_type_t ps_type = DEFAULT_PS_MODE;
while (1)
{
@@ -2088,12 +2133,28 @@ static void esp_evt_work_cb(void *arg)
wlinfo("Wi-Fi sta start\n");
g_sta_connected = false;
- ret = esp_wifi_set_ps(WIFI_PS_NONE);
+
+#ifdef CONFIG_ESP32S3_BLE
+ if (esp32s3_bt_controller_get_status() !=
+ ESP_BT_CONTROLLER_STATUS_IDLE)
+ {
+ if (ps_type == WIFI_PS_NONE)
+ {
+ ps_type = WIFI_PS_MIN_MODEM;
+ }
+ }
+#endif
+ ret = esp_wifi_set_ps(ps_type);
+
if (ret)
{
wlerr("Failed to set power save type\n");
break;
}
+ else
+ {
+ wlinfo("INFO: Set ps type=%d\n", ps_type);
+ }
ret = esp_wifi_get_config(WIFI_IF_STA, &g_sta_wifi_cfg);
if (ret)
@@ -2141,6 +2202,29 @@ static void esp_evt_work_cb(void *arg)
#ifdef ESP32S3_WLAN_HAS_SOFTAP
case WIFI_ADPT_EVT_AP_START:
wlinfo("INFO: Wi-Fi softap start\n");
+
+#ifdef CONFIG_ESP32S3_BLE
+ if (esp32s3_bt_controller_get_status() !=
+ ESP_BT_CONTROLLER_STATUS_IDLE)
+ {
+ if (ps_type == WIFI_PS_NONE)
+ {
+ ps_type = WIFI_PS_MIN_MODEM;
+ }
+ }
+#endif
+ ret = esp_wifi_set_ps(ps_type);
+
+ if (ret)
+ {
+ wlerr("Failed to set power save type\n");
+ break;
+ }
+ else
+ {
+ wlinfo("INFO: Set ps type=%d\n", ps_type);
+ }
+
ret = esp_wifi_get_config(WIFI_IF_AP, &g_softap_wifi_cfg);
if (ret)
{
@@ -2184,6 +2268,73 @@ static void esp_evt_work_cb(void *arg)
}
}
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+
+/****************************************************************************
+ * Name: semphr_take_from_isr_wrapper
+ *
+ * Description:
+ * Take a semaphore from an ISR
+ *
+ * Input Parameters:
+ * semphr - Semaphore data pointer.
+ * hptw - Unused.
+ *
+ * Returned Value:
+ * True if success or false if fail
+ *
+ ****************************************************************************/
+
+static int IRAM_ATTR semphr_take_from_isr_wrapper(void *semphr, void *hptw)
+{
+ *(int *)hptw = 0;
+
+ return esp_semphr_take(semphr, 0);
+}
+
+/****************************************************************************
+ * Name: semphr_give_from_isr_wrapper
+ *
+ * Description:
+ * Post semaphore
+ *
+ * Input Parameters:
+ * semphr - Semaphore data pointer
+ * hptw - Unused.
+ *
+ * Returned Value:
+ * True if success or false if fail
+ *
+ ****************************************************************************/
+
+static int IRAM_ATTR semphr_give_from_isr_wrapper(void *semphr, void *hptw)
+{
+ *(int *)hptw = 0;
+
+ return esp_semphr_give(semphr);
+}
+
+/****************************************************************************
+ * Name: is_in_isr_wrapper
+ *
+ * Description:
+ * Check current is in interrupt
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * true if in interrupt or false if not
+ *
+ ****************************************************************************/
+
+static int IRAM_ATTR is_in_isr_wrapper(void)
+{
+ return up_interrupt_context();
+}
+
+#endif /* CONFIG_ESP32S3_WIFI_BT_COEXIST */
+
/****************************************************************************
* Name: wifi_env_is_chip
*
@@ -2223,10 +2374,6 @@ static void wifi_set_intr(int32_t cpu_no, uint32_t intr_source,
wlinfo("cpu_no=%" PRId32 ", intr_source=%" PRIu32
", intr_num=%" PRIu32 ", intr_prio=%" PRId32 "\n",
cpu_no, intr_source, intr_num, intr_prio);
-
- /* Force to bind Wi-Fi interrupt to CPU0 */
-
- intr_matrix_set(0, intr_source, intr_num);
}
/****************************************************************************
@@ -3484,274 +3631,468 @@ static void esp_wifi_delete_queue(void *queue)
}
/****************************************************************************
- * Name: wifi_coex_init
+ * Name: coex_init_wrapper
*
* Description:
- * Don't support
+ * Init software coexist
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-static int wifi_coex_init(void)
+static int coex_init_wrapper(void)
{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ return coex_init();
+#else
return 0;
+#endif
}
/****************************************************************************
- * Name: wifi_coex_deinit
+ * Name: coex_deinit_wrapper
*
* Description:
- * Don't support
+ * De-init software coexist
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * none
*
****************************************************************************/
-static void wifi_coex_deinit(void)
+static void coex_deinit_wrapper(void)
{
- return;
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ coex_deinit();
+#endif
}
/****************************************************************************
- * Name: wifi_coex_enable
+ * Name: coex_enable_wrapper
*
* Description:
- * Don't support
+ * Enable software coexist
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-static int wifi_coex_enable(void)
+static int coex_enable_wrapper(void)
{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ return coex_enable();
+#else
return 0;
+#endif
}
/****************************************************************************
- * Name: wifi_coex_disable
+ * Name: coex_disable_wrapper
*
* Description:
- * Don't support
+ * Disable software coexist
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * none
*
****************************************************************************/
-static void wifi_coex_disable(void)
+static void coex_disable_wrapper(void)
{
- return;
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ coex_disable();
+#endif
}
/****************************************************************************
- * Name: esp_coex_status_get
+ * Name: coex_status_get_wrapper
*
* Description:
- * Don't support
+ * Get software coexist status.
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-static uint32_t esp_coex_status_get(void)
+static IRAM_ATTR uint32_t coex_status_get_wrapper(void)
{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ return coex_status_get();
+#else
return 0;
+#endif
}
/****************************************************************************
- * Name: esp_coex_condition_set
+ * Name: coex_wifi_request_wrapper
*
* Description:
- * Don't support
+ * Request Wi-Fi coexistence.
*
- ****************************************************************************/
-
-static void esp_coex_condition_set(uint32_t type, bool dissatisfy)
-{
- return;
-}
-
-/****************************************************************************
- * Name: esp_coex_wifi_request
+ * Input Parameters:
+ * event - WiFi event
+ * latency - WiFi will request coexistence after latency
+ * duration - duration for WiFi to request coexistence
*
- * Description:
- * Don't support
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-static int32_t esp_coex_wifi_request(uint32_t event, uint32_t latency,
- uint32_t duration)
+static int32_t coex_wifi_request_wrapper(uint32_t event, uint32_t latency,
+ uint32_t duration)
{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ return coex_wifi_request(event, latency, duration);
+#else
return 0;
+#endif
}
/****************************************************************************
- * Name: esp_coex_wifi_release
+ * Name: coex_wifi_release_wrapper
*
* Description:
- * Don't support
+ * Release Wi-Fi coexistence.
+ *
+ * Input Parameters:
+ * event - WiFi event
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-static int32_t esp_coex_wifi_release(uint32_t event)
+static IRAM_ATTR int32_t coex_wifi_release_wrapper(uint32_t event)
{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ return coex_wifi_release(event);
+#else
return 0;
+#endif
}
/****************************************************************************
- * Name: wifi_coex_wifi_set_channel
+ * Name: coex_wifi_channel_set_wrapper
*
* Description:
- * Don't support
+ * Set Wi-Fi channel to coexistence module.
+ *
+ * Input Parameters:
+ * primary - WiFi primary channel
+ * secondary - WiFi secondary channel
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-static int wifi_coex_wifi_set_channel(uint8_t primary, uint8_t secondary)
+static int coex_wifi_channel_set_wrapper(uint8_t primary, uint8_t secondary)
{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ return coex_wifi_channel_set(primary, secondary);
+#else
return 0;
+#endif
}
/****************************************************************************
- * Name: wifi_coex_get_event_duration
+ * Name: coex_event_duration_get_wrapper
*
* Description:
- * Don't support
+ * Get coexistence event duration.
+ *
+ * Input Parameters:
+ * event - Coexistence event
+ * duration - Coexistence event duration
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-static int wifi_coex_get_event_duration(uint32_t event, uint32_t *duration)
+static int coex_event_duration_get_wrapper(uint32_t event,
+ uint32_t *duration)
{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ return coex_event_duration_get(event, duration);
+#else
return 0;
+#endif
}
/****************************************************************************
- * Name: wifi_coex_get_pti
+ * Name: coex_pti_get_wrapper
*
* Description:
- * Don't support
+ * Get coexistence event priority.
+ *
+ * Input Parameters:
+ * event - Coexistence event
+ * pti - Coexistence event priority
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-static int wifi_coex_get_pti(uint32_t event, uint8_t *pti)
+static int coex_pti_get_wrapper(uint32_t event, uint8_t *pti)
{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ return coex_pti_get(event, pti);
+#else
return 0;
+#endif
}
/****************************************************************************
- * Name: wifi_coex_clear_schm_status_bit
+ * Name: coex_schm_status_bit_clear_wrapper
*
* Description:
- * Don't support
+ * Clear coexistence status.
+ *
+ * Input Parameters:
+ * type - Coexistence status type
+ * status - Coexistence status
+ *
+ * Returned Value:
+ * none
*
****************************************************************************/
-static void wifi_coex_clear_schm_status_bit(uint32_t type, uint32_t status)
+static void coex_schm_status_bit_clear_wrapper(uint32_t type,
+ uint32_t status)
{
- return;
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ coex_schm_status_bit_clear(type, status);
+#endif
}
/****************************************************************************
- * Name: wifi_coex_set_schm_status_bit
+ * Name: coex_schm_status_bit_set_wrapper
*
* Description:
- * Don't support
+ * Set coexistence status.
+ *
+ * Input Parameters:
+ * type - Coexistence status type
+ * status - Coexistence status
+ *
+ * Returned Value:
+ * none
*
****************************************************************************/
-static void wifi_coex_set_schm_status_bit(uint32_t type, uint32_t status)
+static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status)
{
- return;
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ coex_schm_status_bit_set(type, status);
+#endif
}
/****************************************************************************
- * Name: wifi_coex_set_schm_interval
+ * Name: coex_schm_interval_set_wrapper
*
* Description:
- * Don't support
+ * Set coexistence scheme interval.
+ *
+ * Input Parameters:
+ * interval - Coexistence scheme interval
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-static int wifi_coex_set_schm_interval(uint32_t interval)
+static IRAM_ATTR int coex_schm_interval_set_wrapper(uint32_t interval)
{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ return coex_schm_interval_set(interval);
+#else
return 0;
+#endif
}
/****************************************************************************
- * Name: wifi_coex_get_schm_interval
+ * Name: coex_schm_interval_get_wrapper
*
* Description:
- * Don't support
+ * Get coexistence scheme interval.
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * Coexistence scheme interval
*
****************************************************************************/
-static uint32_t wifi_coex_get_schm_interval(void)
+static uint32_t coex_schm_interval_get_wrapper(void)
{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ return coex_schm_interval_get();
+#else
return 0;
+#endif
}
/****************************************************************************
- * Name: wifi_coex_get_schm_curr_period
+ * Name: coex_schm_curr_period_get_wrapper
*
* Description:
- * Don't support
+ * Get current coexistence scheme period.
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * Coexistence scheme period
*
****************************************************************************/
-static uint8_t wifi_coex_get_schm_curr_period(void)
+static uint8_t coex_schm_curr_period_get_wrapper(void)
{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ return coex_schm_curr_period_get();
+#else
return 0;
+#endif
}
/****************************************************************************
- * Name: wifi_coex_get_schm_curr_phase
+ * Name: coex_schm_curr_phase_get_wrapper
*
* Description:
- * Don't support
+ * Get current coexistence scheme phase.
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * Coexistence scheme phase
*
****************************************************************************/
-static void *wifi_coex_get_schm_curr_phase(void)
+static void *coex_schm_curr_phase_get_wrapper(void)
{
- DEBUGPANIC();
-
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ return coex_schm_curr_phase_get();
+#else
return NULL;
+#endif
}
/****************************************************************************
- * Name: wifi_coex_register_start_cb_wrapper
+ * Name: coex_register_start_cb_wrapper
*
* Description:
- * Don't support
+ * Register Wi-Fi callback for coexistence starts.
+ *
+ * Input Parameters:
+ * cb - WiFi callback
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-static int wifi_coex_register_start_cb_wrapper(int (* cb)(void))
+static int coex_register_start_cb_wrapper(int (* cb)(void))
{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ return coex_register_start_cb(cb);
+#else
return 0;
+#endif
}
/****************************************************************************
- * Name: wifi_coex_schm_process_restart_wrapper
+ * Name: coex_schm_process_restart_wrapper
*
* Description:
- * Don't support
+ * Restart current coexistence scheme.
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-static int wifi_coex_schm_process_restart_wrapper(void)
+static int coex_schm_process_restart_wrapper(void)
{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ return coex_schm_process_restart();
+#else
return 0;
+#endif
}
/****************************************************************************
- * Name: wifi_coex_schm_register_cb_wrapper
+ * Name: coex_schm_register_cb_wrapper
*
* Description:
- * Don't support
+ * Register callback for coexistence scheme.
+ *
+ * Input Parameters:
+ * type - callback type
+ * callback - callback
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned
+ * on failure.
*
****************************************************************************/
-static int wifi_coex_schm_register_cb_wrapper(int type, int(*cb)(int))
+static int coex_schm_register_cb_wrapper(int type, int(*cb)(int))
{
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ return coex_schm_register_callback(type, cb);
+#else
return 0;
+#endif
}
/****************************************************************************
* Name: esp_random_ulong
*
* Description:
- * A simpler wrapper of esp_random.
- * Just convert the return value from uint32_t to unsigned long.
+ * Get random value and convert to unsigned long.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Random value
*
****************************************************************************/
@@ -3766,6 +4107,16 @@ static unsigned long esp_random_ulong(void)
* Description:
* Wi-Fi TX done callback function.
*
+ * Input Parameters:
+ * ifidx - The interface id that the tx callback has been triggered from
+ * data - Pointer to the data transmitted
+ * data_len - Length of the data transmitted
+ * txstatus - True:if the data was transmitted sucessfully False: if data
+ * transmission failed
+ *
+ * Returned Value:
+ * none
+ *
****************************************************************************/
static IRAM_ATTR void esp_wifi_tx_done_cb(uint8_t ifidx, uint8_t *data,
@@ -3807,7 +4158,7 @@ static IRAM_ATTR void esp_wifi_tx_done_cb(uint8_t ifidx, uint8_t *data,
* wifi_auth - ESP32-S3 authenticate mode
*
* Returned Value:
- * authenticate mode
+ * authenticate mode
*
****************************************************************************/
@@ -3853,7 +4204,7 @@ static int esp_wifi_auth_trans(uint32_t wifi_auth)
* wifi_cipher - ESP32-S3 cipher type
*
* Returned Value:
- * cipher type
+ * cipher type
*
****************************************************************************/
@@ -3973,7 +4324,7 @@ static int esp_freq_to_channel(uint16_t freq)
* format - format string
*
* Returned Value:
- * 0
+ * Zero (OK)
*
****************************************************************************/
@@ -4004,7 +4355,7 @@ int pp_printf(const char *format, ...)
* format - format string
*
* Returned Value:
- * 0
+ * Zero (OK)
*
****************************************************************************/
@@ -4022,22 +4373,34 @@ int net80211_printf(const char *format, ...)
}
/****************************************************************************
- * Functions needed by libmesh.a
+ * Functions needed by libcoexist.a
****************************************************************************/
/****************************************************************************
- * Name: esp_mesh_send_event_internal
+ * Name: coexist_printf
*
* Description:
- * Don't support
+ * Output format string and its arguments
+ *
+ * Input Parameters:
+ * format - format string
+ *
+ * Returned Value:
+ * Zero (OK)
*
****************************************************************************/
-int esp_mesh_send_event_internal(int32_t event_id,
- void *event_data,
- size_t event_data_size)
+int coexist_printf(const char *format, ...)
{
- return -1;
+#ifdef CONFIG_DEBUG_WIRELESS_INFO
+ va_list arg;
+
+ va_start(arg, format);
+ vsyslog(LOG_INFO, format, arg);
+ va_end(arg);
+#endif
+
+ return 0;
}
/****************************************************************************
@@ -4098,14 +4461,14 @@ int32_t esp_wifi_init(const wifi_init_config_t *config)
{
int32_t ret;
- modifyreg32(SYSTEM_WIFI_CLK_EN_REG, 0, SYSTEM_WIFI_CLK_EN);
-
- modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD, 0);
-
- modifyreg32(SYSCON_WIFI_RST_EN_REG, 0, MODEM_RESET_FIELD_WHEN_PU);
- modifyreg32(SYSCON_WIFI_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU, 0);
-
- modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO, 0);
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+ ret = coex_init();
+ if (ret)
+ {
+ wlerr("ERROR: Failed to initialize coex error=%d\n", ret);
+ return ret;
+ }
+#endif
esp_wifi_internal_set_log_level(WIFI_LOG_DEBUG);
@@ -6374,10 +6737,12 @@ int esp_wifi_softap_rssi(struct iwreq *iwr, bool set)
#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
int esp32s3_wifi_bt_coexist_init(void)
{
-#error "BT and WiFi coexst not implemented!!!"
- return ERROR;
+ esp_coex_adapter_register(&g_coex_adapter_funcs);
+ coex_pre_init();
+
+ return 0;
}
-#endif
+#endif /* CONFIG_ESP32S3_WIFI_BT_COEXIST */
/****************************************************************************
* Name: esp_wifi_stop_callback
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h
index c80ba8cbd6..87d62edc88 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h
+++ b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.h
@@ -828,7 +828,7 @@ int esp_wifi_softap_rssi(struct iwreq *iwr, bool set);
* Name: esp32s3_wifi_bt_coexist_init
*
* Description:
- * Initialize ESP32-C3 Wi-Fi and BT coexistance module.
+ * Initialize ESP32-S3 Wi-Fi and BT coexistance module.
*
* Input Parameters:
* None
diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/blewifi/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/blewifi/defconfig
new file mode 100644
index 0000000000..f60ebd4380
--- /dev/null
+++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/blewifi/defconfig
@@ -0,0 +1,100 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_LEDS is not set
+# CONFIG_NDEBUG is not set
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+CONFIG_ALLOW_BSD_COMPONENTS=y
+CONFIG_ARCH="xtensa"
+CONFIG_ARCH_BOARD="esp32s3-devkit"
+CONFIG_ARCH_BOARD_COMMON=y
+CONFIG_ARCH_BOARD_ESP32S3_DEVKIT=y
+CONFIG_ARCH_CHIP="esp32s3"
+CONFIG_ARCH_CHIP_ESP32S3=y
+CONFIG_ARCH_CHIP_ESP32S3WROOM1=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_XTENSA=y
+CONFIG_BLUETOOTH_TXCMD_PRIORITY=120
+CONFIG_BLUETOOTH_TXCONN_PRIORITY=119
+CONFIG_BOARDCTL_RESET=y
+CONFIG_BOARD_LOOPSPERMSEC=16717
+CONFIG_BTSAK=y
+CONFIG_BTSAK_STACKSIZE=8192
+CONFIG_BUILTIN=y
+CONFIG_DEFAULT_TASK_STACKSIZE=4096
+CONFIG_DRIVERS_BLUETOOTH=y
+CONFIG_DRIVERS_IEEE80211=y
+CONFIG_DRIVERS_WIRELESS=y
+CONFIG_ESP32S3_BLE=y
+CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096
+CONFIG_ESP32S3_UART0=y
+CONFIG_ESP32S3_WIFI=y
+CONFIG_ESP32S3_WIFI_STATION_SOFTAP=y
+CONFIG_EXAMPLES_DHCPD=y
+CONFIG_EXAMPLES_RANDOM=y
+CONFIG_FS_LARGEFILE=y
+CONFIG_FS_PROCFS=y
+CONFIG_IDLETHREAD_STACKSIZE=3072
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INIT_STACKSIZE=8192
+CONFIG_INTELHEX_BINARY=y
+CONFIG_IOB_NBUFFERS=124
+CONFIG_IOB_THROTTLE=24
+CONFIG_MTD=y
+CONFIG_MTD_BYTE_WRITE=y
+CONFIG_MTD_PARTITION=y
+CONFIG_NAME_MAX=48
+CONFIG_NETDB_DNSCLIENT=y
+CONFIG_NETDEV_LATEINIT=y
+CONFIG_NETDEV_PHY_IOCTL=y
+CONFIG_NETDEV_WIRELESS_IOCTL=y
+CONFIG_NETINIT_DHCPC=y
+CONFIG_NETUTILS_CJSON=y
+CONFIG_NETUTILS_DHCPD=y
+CONFIG_NETUTILS_IPERF=y
+CONFIG_NET_BLUETOOTH=y
+CONFIG_NET_BROADCAST=y
+CONFIG_NET_ETH_PKTSIZE=1514
+CONFIG_NET_ICMP=y
+CONFIG_NET_ICMP_SOCKET=y
+CONFIG_NET_TCP=y
+CONFIG_NET_TCP_DELAYED_ACK=y
+CONFIG_NET_TCP_WRITE_BUFFERS=y
+CONFIG_NET_UDP=y
+CONFIG_NET_UDP_WRITE_BUFFERS=y
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=2048
+CONFIG_PREALLOC_MQ_MSGS=64
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PTHREAD_MUTEX_TYPES=y
+CONFIG_RAM_SIZE=114688
+CONFIG_RAM_START=0x20000000
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SIG_DEFAULT=y
+CONFIG_SPINLOCK=y
+CONFIG_START_DAY=6
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2011
+CONFIG_SYSTEM_DHCPC_RENEW=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_PING=y
+CONFIG_TIMER=y
+CONFIG_TLS_NELEM=4
+CONFIG_TLS_TASK_NELEM=4
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_BLUETOOTH=y
+CONFIG_WIRELESS_WAPI=y
+CONFIG_WIRELESS_WAPI_CMDTOOL=y
+CONFIG_WIRELESS_WAPI_STACKSIZE=8192
diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c
index 9907a2cf7b..b05512a120 100644
--- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c
+++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c
@@ -50,6 +50,10 @@
# include "esp32s3_ble.h"
#endif
+#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
+# include "esp32s3_wifi_adapter.h"
+#endif
+
#ifdef CONFIG_ESP32S3_RT_TIMER
# include "esp32s3_rt_timer.h"
#endif