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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/04/10 00:27:16 UTC
[incubator-nuttx] branch master updated (c4e2d88e6b -> a132fa38f6)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
from c4e2d88e6b Make top Make.defs symlink to board Make.defs instead
new 875dd46207 riscv/riscv_exception_commin.S: Don't call riscv_hartid in single core mode.
new e8134a8b57 riscv/riscv_exception_common.S: Allow chips to define the exception section.
new 779fc6461f riscv/esp32c3: Use the common exception handler.
new a132fa38f6 riscv/bl602/chip.h: Add assembly guards for standard includes.
The 4 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/risc-v/src/bl602/chip.h | 9 +-
arch/risc-v/src/common/riscv_exception_common.S | 13 +-
arch/risc-v/src/esp32c3/Make.defs | 6 +-
arch/risc-v/src/esp32c3/chip.h | 8 ++
arch/risc-v/src/esp32c3/esp32c3_interrupt.S | 179 ------------------------
arch/risc-v/src/esp32c3/esp32c3_irq.c | 4 +-
arch/risc-v/src/esp32c3/esp32c3_irq.h | 17 ---
arch/risc-v/src/esp32c3/esp32c3_vectors.S | 10 +-
8 files changed, 35 insertions(+), 211 deletions(-)
delete mode 100644 arch/risc-v/src/esp32c3/esp32c3_interrupt.S
[incubator-nuttx] 01/04: riscv/riscv_exception_commin.S: Don't call riscv_hartid in single core mode.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 875dd4620759469edd5aec1ea35328fce8a148ed
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Thu Apr 7 20:23:43 2022 +0200
riscv/riscv_exception_commin.S: Don't call riscv_hartid in single core
mode.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/risc-v/src/common/riscv_exception_common.S | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/risc-v/src/common/riscv_exception_common.S b/arch/risc-v/src/common/riscv_exception_common.S
index bc2cb9be32..4b4a5c57f5 100644
--- a/arch/risc-v/src/common/riscv_exception_common.S
+++ b/arch/risc-v/src/common/riscv_exception_common.S
@@ -95,7 +95,11 @@ exception_common:
/* Offset to hartid */
mv s0, a0 /* save cause */
+#ifdef CONFIG_SMP
jal x1, riscv_mhartid /* get hartid */
+#else
+ li a0, 0
+#endif
/* Switch to interrupt stack */
[incubator-nuttx] 04/04: riscv/bl602/chip.h: Add assembly guards for standard includes.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit a132fa38f60bc1c20db1f66cc36dd61aa15578c7
Author: Ville Juven <vi...@unikie.com>
AuthorDate: Sat Apr 9 22:14:54 2022 +0200
riscv/bl602/chip.h: Add assembly guards for standard includes.
---
arch/risc-v/src/bl602/chip.h | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/risc-v/src/bl602/chip.h b/arch/risc-v/src/bl602/chip.h
index 4af65547e8..970d2080ba 100644
--- a/arch/risc-v/src/bl602/chip.h
+++ b/arch/risc-v/src/bl602/chip.h
@@ -26,9 +26,12 @@
****************************************************************************/
#include <nuttx/config.h>
-#include <sys/types.h>
-#include <stdint.h>
-#include <stdbool.h>
+
+#ifndef __ASSEMBLY__
+# include <sys/types.h>
+# include <stdint.h>
+# include <stdbool.h>
+#endif /* __ASSEMBLY__ */
#include <arch/irq.h>
[incubator-nuttx] 02/04: riscv/riscv_exception_common.S: Allow chips to define the exception section.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit e8134a8b578b9cecf4c40cc9ff1c72462c0c08af
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Thu Apr 7 20:34:55 2022 +0200
riscv/riscv_exception_common.S: Allow chips to define the exception
section.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/risc-v/src/common/riscv_exception_common.S | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/risc-v/src/common/riscv_exception_common.S b/arch/risc-v/src/common/riscv_exception_common.S
index 4b4a5c57f5..d30c3f5adb 100644
--- a/arch/risc-v/src/common/riscv_exception_common.S
+++ b/arch/risc-v/src/common/riscv_exception_common.S
@@ -49,6 +49,12 @@
# endif
#endif
+/* Provide a default section for the exeception handler. */
+
+#ifndef EXCEPTION_SECTION
+# define EXCEPTION_SECTION .text
+#endif
+
/****************************************************************************
* Public Symbols
****************************************************************************/
@@ -62,7 +68,7 @@
*
****************************************************************************/
- .section .text
+ .section EXCEPTION_SECTION
.global exception_common
.align 8
[incubator-nuttx] 03/04: riscv/esp32c3: Use the common exception handler.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 779fc6461f908dfa417b8ce34df4f00404c8f231
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Thu Apr 7 20:42:12 2022 +0200
riscv/esp32c3: Use the common exception handler.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/risc-v/src/common/riscv_exception_common.S | 1 +
arch/risc-v/src/esp32c3/Make.defs | 6 +-
arch/risc-v/src/esp32c3/chip.h | 8 ++
arch/risc-v/src/esp32c3/esp32c3_interrupt.S | 179 ------------------------
arch/risc-v/src/esp32c3/esp32c3_irq.c | 4 +-
arch/risc-v/src/esp32c3/esp32c3_irq.h | 17 ---
arch/risc-v/src/esp32c3/esp32c3_vectors.S | 10 +-
7 files changed, 18 insertions(+), 207 deletions(-)
diff --git a/arch/risc-v/src/common/riscv_exception_common.S b/arch/risc-v/src/common/riscv_exception_common.S
index d30c3f5adb..664c235770 100644
--- a/arch/risc-v/src/common/riscv_exception_common.S
+++ b/arch/risc-v/src/common/riscv_exception_common.S
@@ -28,6 +28,7 @@
#include <arch/irq.h>
#include <arch/mode.h>
+#include "chip.h"
#include "riscv_macros.S"
/****************************************************************************
diff --git a/arch/risc-v/src/esp32c3/Make.defs b/arch/risc-v/src/esp32c3/Make.defs
index 74e83b5923..ea8fcae986 100644
--- a/arch/risc-v/src/esp32c3/Make.defs
+++ b/arch/risc-v/src/esp32c3/Make.defs
@@ -25,7 +25,11 @@ include chip/Bootloader.mk
HEAD_ASRC = esp32c3_head.S
-CHIP_ASRCS = esp32c3_vectors.S esp32c3_interrupt.S
+CHIP_ASRCS = esp32c3_vectors.S
+
+# Specify our general Assembly files
+
+CMN_ASRCS = riscv_exception_common.S
# Specify C code within the common directory to be included
diff --git a/arch/risc-v/src/esp32c3/chip.h b/arch/risc-v/src/esp32c3/chip.h
index 67a6bcf303..2ae947ddae 100644
--- a/arch/risc-v/src/esp32c3/chip.h
+++ b/arch/risc-v/src/esp32c3/chip.h
@@ -28,4 +28,12 @@
#include <nuttx/config.h>
#include "esp32c3_memorymap.h"
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Section for exception handler. */
+
+#define EXCEPTION_SECTION .iram1
+
#endif /* __ARCH_RISCV_SRC_ESP32C3_CHIP_H */
diff --git a/arch/risc-v/src/esp32c3/esp32c3_interrupt.S b/arch/risc-v/src/esp32c3/esp32c3_interrupt.S
deleted file mode 100644
index d86c61944d..0000000000
--- a/arch/risc-v/src/esp32c3/esp32c3_interrupt.S
+++ /dev/null
@@ -1,179 +0,0 @@
-/****************************************************************************
- * arch/risc-v/src/esp32c3/esp32c3_interrupt.S
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-#include <arch/irq.h>
-
-#include "chip.h"
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .global _interrupt_handler
- .global _exception_handler
- .global g_intstackalloc
- .global g_intstacktop
-
-/****************************************************************************
- * Section: .noinit
- ****************************************************************************/
-
- .section .noinit
-
-#if CONFIG_ARCH_INTERRUPTSTACK > 15
- .balign 16
- .type g_intstackalloc, @object
- .type g_intstacktop, @object
-g_intstackalloc:
- .skip ((CONFIG_ARCH_INTERRUPTSTACK + 8) & ~15)
-g_intstacktop:
- .size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~15)
-#endif
-
-/****************************************************************************
- * Section: .iram1
- ****************************************************************************/
-
- .section .iram1
-
-/****************************************************************************
- * Name: _interrupt_handler
- ****************************************************************************/
-
- .type _interrupt_handler, @function
-
-_exception_handler:
-_interrupt_handler:
- addi sp, sp, -XCPTCONTEXT_SIZE
-
- sw x1, 1*4(sp) /* ra */
- sw x3, 3*4(sp) /* gp (For register dumping on exception handler) */
- sw x4, 4*4(sp) /* tp */
- sw x5, 5*4(sp) /* t0 */
- sw x6, 6*4(sp) /* t1 */
- sw x7, 7*4(sp) /* t2 */
- sw x8, 8*4(sp) /* s0 */
- sw x9, 9*4(sp) /* s1 */
- sw x10, 10*4(sp) /* a0 */
- sw x11, 11*4(sp) /* a1 */
- sw x12, 12*4(sp) /* a2 */
- sw x13, 13*4(sp) /* a3 */
- sw x14, 14*4(sp) /* a4 */
- sw x15, 15*4(sp) /* a5 */
- sw x16, 16*4(sp) /* a6 */
- sw x17, 17*4(sp) /* a7 */
- sw x18, 18*4(sp) /* s2 */
- sw x19, 19*4(sp) /* s3 */
- sw x20, 20*4(sp) /* s4 */
- sw x21, 21*4(sp) /* s5 */
- sw x22, 22*4(sp) /* s6 */
- sw x23, 23*4(sp) /* s7 */
- sw x24, 24*4(sp) /* s8 */
- sw x25, 25*4(sp) /* s9 */
- sw x26, 26*4(sp) /* s10 */
- sw x27, 27*4(sp) /* s11 */
- sw x28, 28*4(sp) /* t3 */
- sw x29, 29*4(sp) /* t4 */
- sw x30, 30*4(sp) /* t5 */
- sw x31, 31*4(sp) /* t6 */
-
- addi s0, sp, XCPTCONTEXT_SIZE
- sw s0, 2*4(sp) /* Save original SP */
-
- /* Save MSTATUS (Machine Status Register) */
-
- csrr s0, mstatus
- sw s0, 32*4(sp)
-
- /* Save MEPC (Machine Exception Program Counter) */
-
- csrr s0, mepc
- sw s0, 0(sp)
-
- csrr a0, mcause /* Handler arg0: Exception cause */
- mv a1, sp /* Handler arg1: Context (saved registers on stack) */
-
-#if CONFIG_ARCH_INTERRUPTSTACK > 15
- lui sp, %hi(g_intstacktop)
- addi sp, sp, %lo(g_intstacktop)
-#endif
-
- /* Call interrupt/exception handler in C */
-
- jal x1, esp32c3_dispatch_irq
-
- /* If context switch is needed, return a new SP */
-
- mv sp, a0
-
- /* Restore MEPC (Machine Exception Program Counter) */
-
- lw s0, 0(sp)
- csrw mepc, s0
-
- /* Restore MSTATUS (Machine Status Register) */
-
- lw s0, 32*4(sp)
- csrw mstatus, s0
-
- lw x1, 1*4(sp) /* ra */
-
- /* GP must not be changed after start-up due to relaxing optimization */
-
- lw x4, 4*4(sp) /* tp */
- lw x5, 5*4(sp) /* t0 */
- lw x6, 6*4(sp) /* t1 */
- lw x7, 7*4(sp) /* t2 */
- lw x8, 8*4(sp) /* s0 */
- lw x9, 9*4(sp) /* s1 */
- lw x10, 10*4(sp) /* a0 */
- lw x11, 11*4(sp) /* a1 */
- lw x12, 12*4(sp) /* a2 */
- lw x13, 13*4(sp) /* a3 */
- lw x14, 14*4(sp) /* a4 */
- lw x15, 15*4(sp) /* a5 */
- lw x16, 16*4(sp) /* a6 */
- lw x17, 17*4(sp) /* a7 */
- lw x18, 18*4(sp) /* s2 */
- lw x19, 19*4(sp) /* s3 */
- lw x20, 20*4(sp) /* s4 */
- lw x21, 21*4(sp) /* s5 */
- lw x22, 22*4(sp) /* s6 */
- lw x23, 23*4(sp) /* s7 */
- lw x24, 24*4(sp) /* s8 */
- lw x25, 25*4(sp) /* s9 */
- lw x26, 26*4(sp) /* s10 */
- lw x27, 27*4(sp) /* s11 */
- lw x28, 28*4(sp) /* t3 */
- lw x29, 29*4(sp) /* t4 */
- lw x30, 30*4(sp) /* t5 */
- lw x31, 31*4(sp) /* t6 */
-
- lw sp, 2*4(sp) /* Restore original SP */
-
- /* Return from Machine Interrupt */
-
- mret
-
diff --git a/arch/risc-v/src/esp32c3/esp32c3_irq.c b/arch/risc-v/src/esp32c3/esp32c3_irq.c
index 4b990d71cb..63530261ee 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_irq.c
+++ b/arch/risc-v/src/esp32c3/esp32c3_irq.c
@@ -339,7 +339,7 @@ void esp32c3_free_cpuint(uint8_t periphid)
}
/****************************************************************************
- * Name: esp32c3_dispatch_irq
+ * Name: riscv_dispatch_irq
*
* Description:
* Process interrupt and its callback function.
@@ -353,7 +353,7 @@ void esp32c3_free_cpuint(uint8_t periphid)
*
****************************************************************************/
-IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs)
+IRAM_ATTR uintptr_t *riscv_dispatch_irq(uintptr_t mcause, uintptr_t *regs)
{
int irq;
uint8_t cpuint = mcause & RISCV_IRQ_MASK;
diff --git a/arch/risc-v/src/esp32c3/esp32c3_irq.h b/arch/risc-v/src/esp32c3/esp32c3_irq.h
index 54cd41003c..3290fbf9d5 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_irq.h
+++ b/arch/risc-v/src/esp32c3/esp32c3_irq.h
@@ -95,21 +95,4 @@ int esp32c3_request_irq(uint8_t periphid, uint8_t prio, uint32_t flags);
void esp32c3_free_cpuint(uint8_t periphid);
-/****************************************************************************
- * Name: esp32c3_dispatch_irq
- *
- * Description:
- * Process interrupt and its callback function.
- *
- * Input Parameters:
- * mcause - RISC-V "mcause" register value
- * regs - Saved register value array
- *
- * Returned Value:
- * None.
- *
- ****************************************************************************/
-
-uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs);
-
#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_IRQ_H */
diff --git a/arch/risc-v/src/esp32c3/esp32c3_vectors.S b/arch/risc-v/src/esp32c3/esp32c3_vectors.S
index d26632c64f..25e1620609 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_vectors.S
+++ b/arch/risc-v/src/esp32c3/esp32c3_vectors.S
@@ -51,13 +51,7 @@ _vector_table:
.option push
.option norvc
- /* exception handler, entry 0 */
-
- j _exception_handler
-
- /* 31 identical entries, all pointing to the interrupt handler */
-
- .rept (31)
- j _interrupt_handler
+ .rept (32)
+ j exception_common
.endr