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Posted to commits@nuttx.apache.org by xi...@apache.org on 2026/01/21 11:21:49 UTC
(nuttx) branch master updated: arch/arm: armv8-r PL at startup needs to be checked
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 3448e84a4c1 arch/arm: armv8-r PL at startup needs to be checked
3448e84a4c1 is described below
commit 3448e84a4c1fecec8d41591237cccf0121083205
Author: yukangzhi <yu...@xiaomi.com>
AuthorDate: Fri Aug 8 09:52:08 2025 +0800
arch/arm: armv8-r PL at startup needs to be checked
When the system startup from the PL1 SYS mode, the initialization
of the PL2 HYP register needs to be skipped. Put the Hypervisor
initialization code together and skip it all at once.
Signed-off-by: yukangzhi <yu...@xiaomi.com>
---
arch/arm/src/armv8-r/arm_head.S | 26 ++++++++++++++++----------
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/arch/arm/src/armv8-r/arm_head.S b/arch/arm/src/armv8-r/arm_head.S
index 57d3d5bbcc2..9d842db05fd 100644
--- a/arch/arm/src/armv8-r/arm_head.S
+++ b/arch/arm/src/armv8-r/arm_head.S
@@ -198,10 +198,6 @@ __cpu0_start:
ldr sp, .Lstackpointer
mov fp, #0
- /* Set Hyp/PL2 Vector table base register */
- ldr r0, .Lhypvectorstart
- mcr CP15_HVBAR(r0)
-
/* Invalidate caches and TLBs.
*
* NOTE: "The ARMv7 Virtual Memory System Architecture (VMSA) does not
@@ -223,11 +219,6 @@ __cpu0_start:
bl cp15_dcache_op_level
isb
- bl hsctlr_initialize /* Init Hyp system control register */
-
- ldr r0, =HACTLR_INIT
- mcr CP15_HACTLR(r0) /* Enable EL1 access all IMP DEFINED registers */
-
#ifdef CONFIG_ARCH_FPU
bl arm_fpuconfig
#endif
@@ -238,7 +229,22 @@ __cpu0_start:
/* Platform hook for highest EL */
bl arm_el_init
- /* Move to PL1 SYS with all exceptions masked */
+ /* Skip hypervisor register initializition */
+ mrs r0, CPSR
+ and r0, r0, #PSR_MODE_MASK
+ cmp r0, #PSR_MODE_HYP /* Check the current processor mode */
+ bne 1f
+
+ /* Set Hyp/PL2 Vector table base register */
+ ldr r0, .Lhypvectorstart
+ mcr CP15_HVBAR(r0)
+
+ /* Initialize Hyp system control register */
+ bl hsctlr_initialize /* Init Hyp system control register */
+ ldr r0, =HACTLR_INIT
+ mcr CP15_HACTLR(r0) /* Enable EL1 access all IMP DEFINED registers */
+
+ /* Move to PL1 SYS with all exceptions masked */
mov r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT | PSR_A_BIT)
msr spsr_hyp, r0