You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@mynewt.apache.org by ad...@apache.org on 2016/06/15 22:03:58 UTC
[15/51] [partial] incubator-mynewt-site git commit: Fixed broken
Quick Start link and added OpenOCD option for Arduino Primo debugging
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/stm32l4x.c
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/stm32l4x.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/stm32l4x.c
new file mode 100755
index 0000000..32d5a0e
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/stm32l4x.c
@@ -0,0 +1,918 @@
+/***************************************************************************
+ * Copyright (C) 2015 by Uwe Bonnes *
+ * bon@elektron.ikp.physik.tu-darmstadt.de *
+ *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include <helper/binarybuffer.h>
+#include <target/algorithm.h>
+#include <target/armv7m.h>
+
+/* STM32L4xxx series for reference.
+ *
+ * RM0351
+ * http://www.st.com/st-web-ui/static/active/en/resource/technical/document/reference_manual/DM00083560.pdf
+ *
+ * STM32L476RG Datasheet (for erase timing)
+ * http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00108832.pdf
+ *
+ *
+ * The device has normally two banks, but on 512 and 256 kiB devices an
+ * option byte is available to map all sectors to the first bank.
+ * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
+ * handlers do!
+ *
+ */
+
+/* Erase time can be as high as 25ms, 10x this and assume it's toast... */
+
+#define FLASH_ERASE_TIMEOUT 250
+
+#define STM32_FLASH_BASE 0x40022000
+#define STM32_FLASH_ACR 0x40022000
+#define STM32_FLASH_KEYR 0x40022008
+#define STM32_FLASH_OPTKEYR 0x4002200c
+#define STM32_FLASH_SR 0x40022010
+#define STM32_FLASH_CR 0x40022014
+#define STM32_FLASH_OPTR 0x40022020
+#define STM32_FLASH_WRP1AR 0x4002202c
+#define STM32_FLASH_WRP2AR 0x40022030
+#define STM32_FLASH_WRP1BR 0x4002204c
+#define STM32_FLASH_WRP2BR 0x40022050
+
+/* FLASH_CR register bits */
+
+#define FLASH_PG (1 << 0)
+#define FLASH_PER (1 << 1)
+#define FLASH_MER1 (1 << 2)
+#define FLASH_PAGE_SHIFT 3
+#define FLASH_CR_BKER (1 << 11)
+#define FLASH_MER2 (1 << 15)
+#define FLASH_STRT (1 << 16)
+#define FLASH_EOPIE (1 << 24)
+#define FLASH_ERRIE (1 << 25)
+#define FLASH_OPTLOCK (1 << 30)
+#define FLASH_LOCK (1 << 31)
+
+/* FLASH_SR register bits */
+
+#define FLASH_BSY (1 << 16)
+/* Fast programming not used => related errors not used*/
+#define FLASH_PGSERR (1 << 7) /* Programming sequence error */
+#define FLASH_SIZERR (1 << 6) /* Size error */
+#define FLASH_PGAERR (1 << 5) /* Programming alignment error */
+#define FLASH_WRPERR (1 << 4) /* Write protection error */
+#define FLASH_PROGERR (1 << 3) /* Programming error */
+#define FLASH_OPERR (1 << 1) /* Operation error */
+#define FLASH_EOP (1 << 0) /* End of operation */
+
+#define FLASH_ERROR (FLASH_PGSERR | FLASH_PGSERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
+
+/* STM32_FLASH_OBR bit definitions (reading) */
+
+#define OPT_DUALBANK 21 /* dual flash bank only */
+
+/* register unlock keys */
+
+#define KEY1 0x45670123
+#define KEY2 0xCDEF89AB
+
+/* option register unlock key */
+#define OPTKEY1 0x08192A3B
+#define OPTKEY2 0x4C5D6E7F
+
+
+/* other registers */
+#define DBGMCU_IDCODE 0xE0042000
+#define FLASH_SIZE_REG 0x1FFF75E0
+
+struct stm32l4_options {
+ uint8_t RDP;
+ uint16_t bank_b_start;
+ uint8_t user_options;
+ uint8_t wpr1a_start;
+ uint8_t wpr1a_end;
+ uint8_t wpr1b_start;
+ uint8_t wpr1b_end;
+ uint8_t wpr2a_start;
+ uint8_t wpr2a_end;
+ uint8_t wpr2b_start;
+ uint8_t wpr2b_end;
+ /* Fixme: Handle PCROP */
+};
+
+struct stm32l4_flash_bank {
+ struct stm32l4_options option_bytes;
+ int probed;
+};
+
+/* flash bank stm32l4x <base> <size> 0 0 <target#>
+ */
+FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
+{
+ struct stm32l4_flash_bank *stm32l4_info;
+
+ if (CMD_ARGC < 6)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ stm32l4_info = malloc(sizeof(struct stm32l4_flash_bank));
+ if (!stm32l4_info)
+ return ERROR_FAIL; /* Checkme: What better error to use?*/
+ bank->driver_priv = stm32l4_info;
+
+ stm32l4_info->probed = 0;
+
+ return ERROR_OK;
+}
+
+static inline int stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg)
+{
+ return reg;
+}
+
+static inline int stm32l4_get_flash_status(struct flash_bank *bank, uint32_t *status)
+{
+ struct target *target = bank->target;
+ return target_read_u32(
+ target, stm32l4_get_flash_reg(bank, STM32_FLASH_SR), status);
+}
+
+static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
+{
+ struct target *target = bank->target;
+ uint32_t status;
+ int retval = ERROR_OK;
+
+ /* wait for busy to clear */
+ for (;;) {
+ retval = stm32l4_get_flash_status(bank, &status);
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("status: 0x%" PRIx32 "", status);
+ if ((status & FLASH_BSY) == 0)
+ break;
+ if (timeout-- <= 0) {
+ LOG_ERROR("timed out waiting for flash");
+ return ERROR_FAIL;
+ }
+ alive_sleep(1);
+ }
+
+
+ if (status & FLASH_WRPERR) {
+ LOG_ERROR("stm32x device protected");
+ retval = ERROR_FAIL;
+ }
+
+ /* Clear but report errors */
+ if (status & FLASH_ERROR) {
+ /* If this operation fails, we ignore it and report the original
+ * retval
+ */
+ target_write_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_SR),
+ status & FLASH_ERROR);
+ }
+ return retval;
+}
+
+static int stm32l4_unlock_reg(struct target *target)
+{
+ uint32_t ctrl;
+
+ /* first check if not already unlocked
+ * otherwise writing on STM32_FLASH_KEYR will fail
+ */
+ int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if ((ctrl & FLASH_LOCK) == 0)
+ return ERROR_OK;
+
+ /* unlock flash registers */
+ retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (ctrl & FLASH_LOCK) {
+ LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
+ return ERROR_TARGET_FAILURE;
+ }
+
+ return ERROR_OK;
+}
+
+static int stm32l4_unlock_option_reg(struct target *target)
+{
+ uint32_t ctrl;
+
+ int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if ((ctrl & FLASH_OPTLOCK) == 0)
+ return ERROR_OK;
+
+ /* unlock option registers */
+ retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY2);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (ctrl & FLASH_OPTLOCK) {
+ LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
+ return ERROR_TARGET_FAILURE;
+ }
+
+ return ERROR_OK;
+}
+
+static int stm32l4_read_options(struct flash_bank *bank)
+{
+ uint32_t optiondata;
+ struct stm32l4_flash_bank *stm32l4_info = NULL;
+ struct target *target = bank->target;
+
+ stm32l4_info = bank->driver_priv;
+
+ /* read current option bytes */
+ int retval = target_read_u32(target, STM32_FLASH_OPTR, &optiondata);
+ if (retval != ERROR_OK)
+ return retval;
+
+ stm32l4_info->option_bytes.user_options = (optiondata >> 8) & 0x3ffff;
+ stm32l4_info->option_bytes.RDP = optiondata & 0xff;
+
+ retval = target_read_u32(target, STM32_FLASH_WRP1AR, &optiondata);
+ if (retval != ERROR_OK)
+ return retval;
+ stm32l4_info->option_bytes.wpr1a_start = optiondata & 0xff;
+ stm32l4_info->option_bytes.wpr1a_end = (optiondata >> 16) & 0xff;
+
+ retval = target_read_u32(target, STM32_FLASH_WRP2AR, &optiondata);
+ if (retval != ERROR_OK)
+ return retval;
+ stm32l4_info->option_bytes.wpr2a_start = optiondata & 0xff;
+ stm32l4_info->option_bytes.wpr2a_end = (optiondata >> 16) & 0xff;
+
+ retval = target_read_u32(target, STM32_FLASH_WRP1BR, &optiondata);
+ if (retval != ERROR_OK)
+ return retval;
+ stm32l4_info->option_bytes.wpr1b_start = optiondata & 0xff;
+ stm32l4_info->option_bytes.wpr1b_end = (optiondata >> 16) & 0xff;
+
+ retval = target_read_u32(target, STM32_FLASH_WRP2BR, &optiondata);
+ if (retval != ERROR_OK)
+ return retval;
+ stm32l4_info->option_bytes.wpr2b_start = optiondata & 0xff;
+ stm32l4_info->option_bytes.wpr2b_end = (optiondata >> 16) & 0xff;
+
+ if (stm32l4_info->option_bytes.RDP != 0xAA)
+ LOG_INFO("Device Security Bit Set");
+
+ return ERROR_OK;
+}
+
+static int stm32l4_write_options(struct flash_bank *bank)
+{
+ struct stm32l4_flash_bank *stm32l4_info = NULL;
+ struct target *target = bank->target;
+ uint32_t optiondata;
+
+ stm32l4_info = bank->driver_priv;
+
+ (void) optiondata;
+ (void) stm32l4_info;
+
+ int retval = stm32l4_unlock_option_reg(target);
+ if (retval != ERROR_OK)
+ return retval;
+ /* FIXME: Implement Option writing!*/
+ return ERROR_OK;
+}
+
+static int stm32l4_protect_check(struct flash_bank *bank)
+{
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+
+ /* read write protection settings */
+ int retval = stm32l4_read_options(bank);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("unable to read option bytes");
+ return retval;
+ }
+
+ for (int i = 0; i < bank->num_sectors; i++) {
+ if (i < stm32l4_info->option_bytes.bank_b_start) {
+ if (((i >= stm32l4_info->option_bytes.wpr1a_start) &&
+ (i <= stm32l4_info->option_bytes.wpr1a_end)) ||
+ ((i >= stm32l4_info->option_bytes.wpr2a_start) &&
+ (i <= stm32l4_info->option_bytes.wpr2a_end)))
+ bank->sectors[i].is_protected = 1;
+ else
+ bank->sectors[i].is_protected = 0;
+ } else {
+ uint8_t snb;
+ snb = i - stm32l4_info->option_bytes.bank_b_start + 256;
+ if (((snb >= stm32l4_info->option_bytes.wpr1b_start) &&
+ (snb <= stm32l4_info->option_bytes.wpr1b_end)) ||
+ ((snb >= stm32l4_info->option_bytes.wpr2b_start) &&
+ (snb <= stm32l4_info->option_bytes.wpr2b_end)))
+ bank->sectors[i].is_protected = 1;
+ else
+ bank->sectors[i].is_protected = 0;
+ }
+ }
+ return ERROR_OK;
+}
+
+static int stm32l4_erase(struct flash_bank *bank, int first, int last)
+{
+ struct target *target = bank->target;
+ int i;
+
+ assert(first < bank->num_sectors);
+ assert(last < bank->num_sectors);
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ int retval;
+ retval = stm32l4_unlock_reg(target);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /*
+ Sector Erase
+ To erase a sector, follow the procedure below:
+ 1. Check that no Flash memory operation is ongoing by
+ checking the BSY bit in the FLASH_SR register
+ 2. Set the PER bit and select the page and bank
+ you wish to erase in the FLASH_CR register
+ 3. Set the STRT bit in the FLASH_CR register
+ 4. Wait for the BSY bit to be cleared
+ */
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+
+ for (i = first; i <= last; i++) {
+ uint32_t erase_flags;
+ erase_flags = FLASH_PER | FLASH_STRT;
+
+ if (i >= stm32l4_info->option_bytes.bank_b_start) {
+ uint8_t snb;
+ snb = (i - stm32l4_info->option_bytes.bank_b_start) + 256;
+ erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
+ } else
+ erase_flags |= i << FLASH_PAGE_SHIFT;
+ retval = target_write_u32(target,
+ stm32l4_get_flash_reg(bank, STM32_FLASH_CR), erase_flags);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ bank->sectors[i].is_erased = 1;
+ }
+
+ retval = target_write_u32(
+ target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last)
+{
+ struct target *target = bank->target;
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /* read protection settings */
+ int retval = stm32l4_read_options(bank);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("unable to read option bytes");
+ return retval;
+ }
+
+ (void)stm32l4_info;
+ /* FIXME: Write First and last in a valid WRPxx_start/end combo*/
+ retval = stm32l4_write_options(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+/* Count is in halfwords */
+static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ uint32_t buffer_size = 16384;
+ struct working_area *write_algorithm;
+ struct working_area *source;
+ uint32_t address = bank->base + offset;
+ struct reg_param reg_params[5];
+ struct armv7m_algorithm armv7m_info;
+ int retval = ERROR_OK;
+
+ /* See contrib/loaders/flash/stm32l4x.S for source and
+ * hints how to generate the data!
+ */
+
+ static const uint8_t stm32l4_flash_write_code[] = {
+ 0xd0, 0xf8, 0x00, 0x80, 0xb8, 0xf1, 0x00, 0x0f, 0x21, 0xd0, 0x45, 0x68,
+ 0xb8, 0xeb, 0x05, 0x06, 0x44, 0xbf, 0x76, 0x18, 0x36, 0x1a, 0x08, 0x2e,
+ 0xf2, 0xd3, 0xdf, 0xf8, 0x36, 0x60, 0x66, 0x61, 0xf5, 0xe8, 0x02, 0x67,
+ 0xe2, 0xe8, 0x02, 0x67, 0xbf, 0xf3, 0x4f, 0x8f, 0x26, 0x69, 0x16, 0xf4,
+ 0x80, 0x3f, 0xfb, 0xd1, 0x16, 0xf0, 0xfa, 0x0f, 0x07, 0xd1, 0x8d, 0x42,
+ 0x28, 0xbf, 0x00, 0xf1, 0x08, 0x05, 0x45, 0x60, 0x01, 0x3b, 0x13, 0xb1,
+ 0xda, 0xe7, 0x00, 0x21, 0x41, 0x60, 0x30, 0x46, 0x00, 0xbe, 0x01, 0x00,
+ 0x00, 0x00
+ };
+
+ if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
+ &write_algorithm) != ERROR_OK) {
+ LOG_WARNING("no working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ retval = target_write_buffer(target, write_algorithm->address,
+ sizeof(stm32l4_flash_write_code),
+ stm32l4_flash_write_code);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* memory buffer */
+ while (target_alloc_working_area_try(target, buffer_size, &source) !=
+ ERROR_OK) {
+ buffer_size /= 2;
+ if (buffer_size <= 256) {
+ /* we already allocated the writing code, but failed to get a
+ * buffer, free the algorithm */
+ target_free_working_area(target, write_algorithm);
+
+ LOG_WARNING("no large enough working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+ }
+
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARM_MODE_THREAD;
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
+ init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
+ init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (double word-64bit) */
+ init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* flash base */
+
+ buf_set_u32(reg_params[0].value, 0, 32, source->address);
+ buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
+ buf_set_u32(reg_params[2].value, 0, 32, address);
+ buf_set_u32(reg_params[3].value, 0, 32, count / 4);
+ buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
+
+ retval = target_run_flash_async_algorithm(target, buffer, count, 2,
+ 0, NULL,
+ 5, reg_params,
+ source->address, source->size,
+ write_algorithm->address, 0,
+ &armv7m_info);
+
+ if (retval == ERROR_FLASH_OPERATION_FAILED) {
+ LOG_ERROR("error executing stm32l4 flash write algorithm");
+
+ uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
+
+ if (error & FLASH_WRPERR)
+ LOG_ERROR("flash memory write protected");
+
+ if (error != 0) {
+ LOG_ERROR("flash write failed = %08" PRIx32, error);
+ /* Clear but report errors */
+ target_write_u32(target, STM32_FLASH_SR, error);
+ retval = ERROR_FAIL;
+ }
+ }
+
+ target_free_working_area(target, source);
+ target_free_working_area(target, write_algorithm);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ destroy_reg_param(®_params[3]);
+ destroy_reg_param(®_params[4]);
+
+ return retval;
+}
+
+static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ int retval;
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (offset & 0x7) {
+ LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment",
+ offset);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ if (count & 0x7) {
+ LOG_WARNING("Padding %d bytes to keep 8-byte write size",
+ count & 7);
+ count = (count + 7) & ~7;
+ /* This pads the write chunk with random bytes by overrunning the
+ * write buffer. Padding with the erased pattern 0xff is purely
+ * cosmetical, as 8-byte flash words are ECC secured and the first
+ * write will program the ECC bits. A second write would need
+ * to reprogramm these ECC bits.
+ * But this can only be done after erase!
+ */
+ }
+
+ retval = stm32l4_unlock_reg(target);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Only full double words (8-byte) can be programmed*/
+ retval = stm32l4_write_block(bank, buffer, offset, count / 2);
+ if (retval != ERROR_OK) {
+ LOG_WARNING("block write failed");
+ return retval;
+ }
+
+ LOG_WARNING("block write succeeded");
+ return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
+}
+
+static int stm32l4_probe(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ int i;
+ uint16_t flash_size_in_kb = 0xffff;
+ uint32_t device_id;
+ uint32_t options;
+ uint32_t base_address = 0x08000000;
+
+ stm32l4_info->probed = 0;
+
+ /* read stm32 device id register */
+ int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
+
+ /* set max flash size depending on family */
+ switch (device_id & 0xfff) {
+ case 0x415:
+ break;
+ default:
+ LOG_WARNING("Cannot identify target as a STM32L4 family.");
+ return ERROR_FAIL;
+ }
+
+ /* get flash size from target. */
+ retval = target_read_u16(target, FLASH_SIZE_REG, &flash_size_in_kb);
+
+ /* get options to for DUAL BANK. */
+ retval = target_read_u32(target, STM32_FLASH_OPTR, &options);
+
+ /* only devices with < 1024 kiB may be set to single bank dual banks */
+ if ((flash_size_in_kb == 1024) || !(options & OPT_DUALBANK))
+ stm32l4_info->option_bytes.bank_b_start = 256;
+ else
+ stm32l4_info->option_bytes.bank_b_start = flash_size_in_kb << 9;
+
+ LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
+
+ /* did we assign flash size? */
+ assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
+
+ /* calculate numbers of pages */
+ int num_pages = flash_size_in_kb / 2;
+
+ /* check that calculation result makes sense */
+ assert(num_pages > 0);
+
+ if (bank->sectors) {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
+ bank->base = base_address;
+ bank->size = num_pages * (1 << 11);
+ bank->num_sectors = num_pages;
+ bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
+ if (!bank->sectors)
+ return ERROR_FAIL; /* Checkme: What better error to use?*/
+
+ for (i = 0; i < num_pages; i++) {
+ bank->sectors[i].offset = i << 11;
+ bank->sectors[i].size = 1 << 11;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 1;
+ }
+
+ stm32l4_info->probed = 1;
+
+ return ERROR_OK;
+}
+
+static int stm32l4_auto_probe(struct flash_bank *bank)
+{
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ if (stm32l4_info->probed)
+ return ERROR_OK;
+ return stm32l4_probe(bank);
+}
+
+static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ struct target *target = bank->target;
+ uint32_t dbgmcu_idcode;
+
+ /* read stm32 device id register */
+ int retval = target_read_u32(target, DBGMCU_IDCODE, &dbgmcu_idcode);
+ if (retval != ERROR_OK)
+ return retval;
+
+ uint16_t device_id = dbgmcu_idcode & 0xffff;
+ uint8_t rev_id = dbgmcu_idcode >> 28;
+ uint8_t rev_minor = 0;
+ int i;
+
+ for (i = 16; i < 28; i++) {
+ if (dbgmcu_idcode & (1 << i))
+ rev_minor++;
+ else
+ break;
+ }
+
+ const char *device_str;
+
+ switch (device_id) {
+ case 0x6415:
+ device_str = "STM32L4xx";
+ break;
+
+ default:
+ snprintf(buf, buf_size, "Cannot identify target as a STM32L4\n");
+ return ERROR_FAIL;
+ }
+
+ snprintf(buf, buf_size, "%s - Rev: %1d.%02d",
+ device_str, rev_id, rev_minor);
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(stm32l4_handle_lock_command)
+{
+ struct target *target = NULL;
+ struct stm32l4_flash_bank *stm32l4_info = NULL;
+
+ if (CMD_ARGC < 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ stm32l4_info = bank->driver_priv;
+ target = bank->target;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (stm32l4_read_options(bank) != ERROR_OK) {
+ command_print(CMD_CTX, "%s failed to read options",
+ bank->driver->name);
+ return ERROR_OK;
+ }
+
+ /* set readout protection */
+ stm32l4_info->option_bytes.RDP = 0;
+
+ if (stm32l4_write_options(bank) != ERROR_OK) {
+ command_print(CMD_CTX, "%s failed to lock device", bank->driver->name);
+ return ERROR_OK;
+ }
+
+ command_print(CMD_CTX, "%s locked", bank->driver->name);
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(stm32l4_handle_unlock_command)
+{
+ struct target *target = NULL;
+ struct stm32l4_flash_bank *stm32l4_info = NULL;
+
+ if (CMD_ARGC < 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ stm32l4_info = bank->driver_priv;
+ target = bank->target;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (stm32l4_read_options(bank) != ERROR_OK) {
+ command_print(CMD_CTX, "%s failed to read options", bank->driver->name);
+ return ERROR_OK;
+ }
+
+ /* clear readout protection and complementary option bytes
+ * this will also force a device unlock if set */
+ stm32l4_info->option_bytes.RDP = 0xAA;
+
+ if (stm32l4_write_options(bank) != ERROR_OK) {
+ command_print(CMD_CTX, "%s failed to unlock device",
+ bank->driver->name);
+ return ERROR_OK;
+ }
+
+ command_print(CMD_CTX, "%s unlocked.\n"
+ "INFO: a reset or power cycle is required "
+ "for the new settings to take effect.", bank->driver->name);
+
+ return ERROR_OK;
+}
+
+static int stm32l4_mass_erase(struct flash_bank *bank, uint32_t action)
+{
+ int retval;
+ struct target *target = bank->target;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ retval = stm32l4_unlock_reg(target);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* mass erase flash memory */
+ retval = target_write_u32(
+ target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), action);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(
+ target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR),
+ action | FLASH_STRT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_write_u32(
+ target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
+{
+ int i;
+ uint32_t action;
+
+ if (CMD_ARGC < 1) {
+ command_print(CMD_CTX, "stm32x mass_erase <STM32L4 bank>");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ action = FLASH_MER1 | FLASH_MER2;
+ retval = stm32l4_mass_erase(bank, action);
+ if (retval == ERROR_OK) {
+ /* set all sectors as erased */
+ for (i = 0; i < bank->num_sectors; i++)
+ bank->sectors[i].is_erased = 1;
+
+ command_print(CMD_CTX, "stm32x mass erase complete");
+ } else {
+ command_print(CMD_CTX, "stm32x mass erase failed");
+ }
+
+ return retval;
+}
+
+static const struct command_registration stm32l4_exec_command_handlers[] = {
+ {
+ .name = "lock",
+ .handler = stm32l4_handle_lock_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id",
+ .help = "Lock entire flash device.",
+ },
+ {
+ .name = "unlock",
+ .handler = stm32l4_handle_unlock_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id",
+ .help = "Unlock entire protected flash device.",
+ },
+ {
+ .name = "mass_erase",
+ .handler = stm32l4_handle_mass_erase_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id",
+ .help = "Erase entire flash device.",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration stm32l4_command_handlers[] = {
+ {
+ .name = "stm32l4x",
+ .mode = COMMAND_ANY,
+ .help = "stm32l4x flash command group",
+ .usage = "",
+ .chain = stm32l4_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+struct flash_driver stm32l4x_flash = {
+ .name = "stm32l4x",
+ .commands = stm32l4_command_handlers,
+ .flash_bank_command = stm32l4_flash_bank_command,
+ .erase = stm32l4_erase,
+ .protect = stm32l4_protect,
+ .write = stm32l4_write,
+ .read = default_flash_read,
+ .probe = stm32l4_probe,
+ .auto_probe = stm32l4_auto_probe,
+ .erase_check = default_flash_blank_check,
+ .protect_check = stm32l4_protect_check,
+ .info = get_stm32l4_info,
+};
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/stm32lx.c
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/stm32lx.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/stm32lx.c
new file mode 100755
index 0000000..2ae58cc
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/stm32lx.c
@@ -0,0 +1,1424 @@
+/***************************************************************************
+ * Copyright (C) 2005 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * Copyright (C) 2011 by Clement Burin des Roziers *
+ * clement.burin-des-roziers@hikob.com *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include <helper/binarybuffer.h>
+#include <target/algorithm.h>
+#include <target/armv7m.h>
+#include <target/cortex_m.h>
+
+/* stm32lx flash register locations */
+
+#define FLASH_ACR 0x00
+#define FLASH_PECR 0x04
+#define FLASH_PDKEYR 0x08
+#define FLASH_PEKEYR 0x0C
+#define FLASH_PRGKEYR 0x10
+#define FLASH_OPTKEYR 0x14
+#define FLASH_SR 0x18
+#define FLASH_OBR 0x1C
+#define FLASH_WRPR 0x20
+
+/* FLASH_ACR bites */
+#define FLASH_ACR__LATENCY (1<<0)
+#define FLASH_ACR__PRFTEN (1<<1)
+#define FLASH_ACR__ACC64 (1<<2)
+#define FLASH_ACR__SLEEP_PD (1<<3)
+#define FLASH_ACR__RUN_PD (1<<4)
+
+/* FLASH_PECR bits */
+#define FLASH_PECR__PELOCK (1<<0)
+#define FLASH_PECR__PRGLOCK (1<<1)
+#define FLASH_PECR__OPTLOCK (1<<2)
+#define FLASH_PECR__PROG (1<<3)
+#define FLASH_PECR__DATA (1<<4)
+#define FLASH_PECR__FTDW (1<<8)
+#define FLASH_PECR__ERASE (1<<9)
+#define FLASH_PECR__FPRG (1<<10)
+#define FLASH_PECR__EOPIE (1<<16)
+#define FLASH_PECR__ERRIE (1<<17)
+#define FLASH_PECR__OBL_LAUNCH (1<<18)
+
+/* FLASH_SR bits */
+#define FLASH_SR__BSY (1<<0)
+#define FLASH_SR__EOP (1<<1)
+#define FLASH_SR__ENDHV (1<<2)
+#define FLASH_SR__READY (1<<3)
+#define FLASH_SR__WRPERR (1<<8)
+#define FLASH_SR__PGAERR (1<<9)
+#define FLASH_SR__SIZERR (1<<10)
+#define FLASH_SR__OPTVERR (1<<11)
+
+/* Unlock keys */
+#define PEKEY1 0x89ABCDEF
+#define PEKEY2 0x02030405
+#define PRGKEY1 0x8C9DAEBF
+#define PRGKEY2 0x13141516
+#define OPTKEY1 0xFBEAD9C8
+#define OPTKEY2 0x24252627
+
+/* other registers */
+#define DBGMCU_IDCODE 0xE0042000
+#define DBGMCU_IDCODE_L0 0x40015800
+
+/* Constants */
+#define FLASH_SECTOR_SIZE 4096
+#define FLASH_BANK0_ADDRESS 0x08000000
+
+/* option bytes */
+#define OPTION_BYTES_ADDRESS 0x1FF80000
+
+#define OPTION_BYTE_0_PR1 0xFFFF0000
+#define OPTION_BYTE_0_PR0 0xFF5500AA
+
+static int stm32lx_unlock_program_memory(struct flash_bank *bank);
+static int stm32lx_lock_program_memory(struct flash_bank *bank);
+static int stm32lx_enable_write_half_page(struct flash_bank *bank);
+static int stm32lx_erase_sector(struct flash_bank *bank, int sector);
+static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank);
+static int stm32lx_lock(struct flash_bank *bank);
+static int stm32lx_unlock(struct flash_bank *bank);
+static int stm32lx_mass_erase(struct flash_bank *bank);
+static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout);
+
+struct stm32lx_rev {
+ uint16_t rev;
+ const char *str;
+};
+
+struct stm32lx_part_info {
+ uint16_t id;
+ const char *device_str;
+ const struct stm32lx_rev *revs;
+ size_t num_revs;
+ unsigned int page_size;
+ unsigned int pages_per_sector;
+ uint16_t max_flash_size_kb;
+ uint16_t first_bank_size_kb; /* used when has_dual_banks is true */
+ bool has_dual_banks;
+
+ uint32_t flash_base; /* Flash controller registers location */
+ uint32_t fsize_base; /* Location of FSIZE register */
+};
+
+struct stm32lx_flash_bank {
+ int probed;
+ uint32_t idcode;
+ uint32_t user_bank_size;
+ uint32_t flash_base;
+
+ const struct stm32lx_part_info *part_info;
+};
+
+static const struct stm32lx_rev stm32_416_revs[] = {
+ { 0x1000, "A" }, { 0x1008, "Y" }, { 0x1038, "W" }, { 0x1078, "V" },
+};
+static const struct stm32lx_rev stm32_417_revs[] = {
+ { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" }, { 0x1038, "X" }
+};
+static const struct stm32lx_rev stm32_425_revs[] = {
+ { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Y" },
+};
+static const struct stm32lx_rev stm32_427_revs[] = {
+ { 0x1000, "A" }, { 0x1018, "Y" }, { 0x1038, "X" },
+};
+static const struct stm32lx_rev stm32_429_revs[] = {
+ { 0x1000, "A" }, { 0x1018, "Z" },
+};
+static const struct stm32lx_rev stm32_436_revs[] = {
+ { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" },
+};
+static const struct stm32lx_rev stm32_437_revs[] = {
+ { 0x1000, "A" },
+};
+static const struct stm32lx_rev stm32_447_revs[] = {
+ { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Z" },
+};
+static const struct stm32lx_rev stm32_457_revs[] = {
+ { 0x1000, "A" }, { 0x1008, "Z" },
+};
+
+static const struct stm32lx_part_info stm32lx_parts[] = {
+ {
+ .id = 0x416,
+ .revs = stm32_416_revs,
+ .num_revs = ARRAY_SIZE(stm32_416_revs),
+ .device_str = "STM32L1xx (Cat.1 - Low/Medium Density)",
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .max_flash_size_kb = 128,
+ .has_dual_banks = false,
+ .flash_base = 0x40023C00,
+ .fsize_base = 0x1FF8004C,
+ },
+ {
+ .id = 0x417,
+ .revs = stm32_417_revs,
+ .num_revs = ARRAY_SIZE(stm32_417_revs),
+ .device_str = "STM32L0xx (Cat. 3)",
+ .page_size = 128,
+ .pages_per_sector = 32,
+ .max_flash_size_kb = 64,
+ .has_dual_banks = false,
+ .flash_base = 0x40022000,
+ .fsize_base = 0x1FF8007C,
+ },
+ {
+ .id = 0x425,
+ .revs = stm32_425_revs,
+ .num_revs = ARRAY_SIZE(stm32_425_revs),
+ .device_str = "STM32L0xx (Cat. 2)",
+ .page_size = 128,
+ .pages_per_sector = 32,
+ .max_flash_size_kb = 32,
+ .has_dual_banks = false,
+ .flash_base = 0x40022000,
+ .fsize_base = 0x1FF8007C,
+ },
+ {
+ .id = 0x427,
+ .revs = stm32_427_revs,
+ .num_revs = ARRAY_SIZE(stm32_427_revs),
+ .device_str = "STM32L1xx (Cat.3 - Medium+ Density)",
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .max_flash_size_kb = 256,
+ .first_bank_size_kb = 192,
+ .has_dual_banks = true,
+ .flash_base = 0x40023C00,
+ .fsize_base = 0x1FF800CC,
+ },
+ {
+ .id = 0x429,
+ .revs = stm32_429_revs,
+ .num_revs = ARRAY_SIZE(stm32_429_revs),
+ .device_str = "STM32L1xx (Cat.2)",
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .max_flash_size_kb = 128,
+ .has_dual_banks = false,
+ .flash_base = 0x40023C00,
+ .fsize_base = 0x1FF8004C,
+ },
+ {
+ .id = 0x436,
+ .revs = stm32_436_revs,
+ .num_revs = ARRAY_SIZE(stm32_436_revs),
+ .device_str = "STM32L1xx (Cat.4/Cat.3 - Medium+/High Density)",
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .max_flash_size_kb = 384,
+ .first_bank_size_kb = 192,
+ .has_dual_banks = true,
+ .flash_base = 0x40023C00,
+ .fsize_base = 0x1FF800CC,
+ },
+ {
+ .id = 0x437,
+ .revs = stm32_437_revs,
+ .num_revs = ARRAY_SIZE(stm32_437_revs),
+ .device_str = "STM32L1xx (Cat.5/Cat.6)",
+ .page_size = 256,
+ .pages_per_sector = 16,
+ .max_flash_size_kb = 512,
+ .first_bank_size_kb = 256,
+ .has_dual_banks = true,
+ .flash_base = 0x40023C00,
+ .fsize_base = 0x1FF800CC,
+ },
+ {
+ .id = 0x447,
+ .revs = stm32_447_revs,
+ .num_revs = ARRAY_SIZE(stm32_447_revs),
+ .device_str = "STM32L0xx (Cat.5)",
+ .page_size = 128,
+ .pages_per_sector = 32,
+ .max_flash_size_kb = 192,
+ .first_bank_size_kb = 128,
+ .has_dual_banks = true,
+ .flash_base = 0x40022000,
+ .fsize_base = 0x1FF8007C,
+ },
+ {
+ .id = 0x457,
+ .revs = stm32_457_revs,
+ .num_revs = ARRAY_SIZE(stm32_457_revs),
+ .device_str = "STM32L0xx (Cat.1)",
+ .page_size = 128,
+ .pages_per_sector = 32,
+ .max_flash_size_kb = 16,
+ .has_dual_banks = false,
+ .flash_base = 0x40022000,
+ .fsize_base = 0x1FF8007C,
+ },
+};
+
+/* flash bank stm32lx <base> <size> 0 0 <target#>
+ */
+FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command)
+{
+ struct stm32lx_flash_bank *stm32lx_info;
+ if (CMD_ARGC < 6)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ /* Create the bank structure */
+ stm32lx_info = calloc(1, sizeof(*stm32lx_info));
+
+ /* Check allocation */
+ if (stm32lx_info == NULL) {
+ LOG_ERROR("failed to allocate bank structure");
+ return ERROR_FAIL;
+ }
+
+ bank->driver_priv = stm32lx_info;
+
+ stm32lx_info->probed = 0;
+ stm32lx_info->user_bank_size = bank->size;
+
+ /* the stm32l erased value is 0x00 */
+ bank->default_padded_value = 0x00;
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(stm32lx_handle_mass_erase_command)
+{
+ int i;
+
+ if (CMD_ARGC < 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ retval = stm32lx_mass_erase(bank);
+ if (retval == ERROR_OK) {
+ /* set all sectors as erased */
+ for (i = 0; i < bank->num_sectors; i++)
+ bank->sectors[i].is_erased = 1;
+
+ command_print(CMD_CTX, "stm32lx mass erase complete");
+ } else {
+ command_print(CMD_CTX, "stm32lx mass erase failed");
+ }
+
+ return retval;
+}
+
+COMMAND_HANDLER(stm32lx_handle_lock_command)
+{
+ if (CMD_ARGC < 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ retval = stm32lx_lock(bank);
+
+ if (retval == ERROR_OK)
+ command_print(CMD_CTX, "STM32Lx locked, takes effect after power cycle.");
+ else
+ command_print(CMD_CTX, "STM32Lx lock failed");
+
+ return retval;
+}
+
+COMMAND_HANDLER(stm32lx_handle_unlock_command)
+{
+ if (CMD_ARGC < 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ retval = stm32lx_unlock(bank);
+
+ if (retval == ERROR_OK)
+ command_print(CMD_CTX, "STM32Lx unlocked, takes effect after power cycle.");
+ else
+ command_print(CMD_CTX, "STM32Lx unlock failed");
+
+ return retval;
+}
+
+static int stm32lx_protect_check(struct flash_bank *bank)
+{
+ int retval;
+ struct target *target = bank->target;
+ struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
+
+ uint32_t wrpr;
+
+ /*
+ * Read the WRPR word, and check each bit (corresponding to each
+ * flash sector
+ */
+ retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_WRPR,
+ &wrpr);
+ if (retval != ERROR_OK)
+ return retval;
+
+ for (int i = 0; i < bank->num_sectors; i++) {
+ if (wrpr & (1 << i))
+ bank->sectors[i].is_protected = 1;
+ else
+ bank->sectors[i].is_protected = 0;
+ }
+ return ERROR_OK;
+}
+
+static int stm32lx_erase(struct flash_bank *bank, int first, int last)
+{
+ int retval;
+
+ /*
+ * It could be possible to do a mass erase if all sectors must be
+ * erased, but it is not implemented yet.
+ */
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /*
+ * Loop over the selected sectors and erase them
+ */
+ for (int i = first; i <= last; i++) {
+ retval = stm32lx_erase_sector(bank, i);
+ if (retval != ERROR_OK)
+ return retval;
+ bank->sectors[i].is_erased = 1;
+ }
+ return ERROR_OK;
+}
+
+static int stm32lx_protect(struct flash_bank *bank, int set, int first,
+ int last)
+{
+ LOG_WARNING("protection of the STM32L flash is not implemented");
+ return ERROR_OK;
+}
+
+static int stm32lx_write_half_pages(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
+
+ uint32_t hp_nb = stm32lx_info->part_info->page_size / 2;
+ uint32_t buffer_size = 16384;
+ struct working_area *write_algorithm;
+ struct working_area *source;
+ uint32_t address = bank->base + offset;
+
+ struct reg_param reg_params[3];
+ struct armv7m_algorithm armv7m_info;
+
+ int retval = ERROR_OK;
+
+ /* see contib/loaders/flash/stm32lx.S for src */
+
+ static const uint8_t stm32lx_flash_write_code[] = {
+ /* write_word: */
+ 0x00, 0x23, /* movs r3, #0 */
+ 0x04, 0xe0, /* b test_done */
+
+ /* write_word: */
+ 0x51, 0xf8, 0x04, 0xcb, /* ldr ip, [r1], #4 */
+ 0x40, 0xf8, 0x04, 0xcb, /* str ip, [r0], #4 */
+ 0x01, 0x33, /* adds r3, #1 */
+
+ /* test_done: */
+ 0x93, 0x42, /* cmp r3, r2 */
+ 0xf8, 0xd3, /* bcc write_word */
+ 0x00, 0xbe, /* bkpt 0 */
+ };
+
+ /* Make sure we're performing a half-page aligned write. */
+ if (count % hp_nb) {
+ LOG_ERROR("The byte count must be %" PRIu32 "B-aligned but count is %" PRIi32 "B)", hp_nb, count);
+ return ERROR_FAIL;
+ }
+
+ /* flash write code */
+ if (target_alloc_working_area(target, sizeof(stm32lx_flash_write_code),
+ &write_algorithm) != ERROR_OK) {
+ LOG_DEBUG("no working area for block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ /* Write the flashing code */
+ retval = target_write_buffer(target,
+ write_algorithm->address,
+ sizeof(stm32lx_flash_write_code),
+ stm32lx_flash_write_code);
+ if (retval != ERROR_OK) {
+ target_free_working_area(target, write_algorithm);
+ return retval;
+ }
+
+ /* Allocate half pages memory */
+ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
+ if (buffer_size > 1024)
+ buffer_size -= 1024;
+ else
+ buffer_size /= 2;
+
+ if (buffer_size <= stm32lx_info->part_info->page_size) {
+ /* we already allocated the writing code, but failed to get a
+ * buffer, free the algorithm */
+ target_free_working_area(target, write_algorithm);
+
+ LOG_WARNING("no large enough working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+ }
+
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARM_MODE_THREAD;
+ init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
+ init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
+
+ /* Enable half-page write */
+ retval = stm32lx_enable_write_half_page(bank);
+ if (retval != ERROR_OK) {
+ target_free_working_area(target, source);
+ target_free_working_area(target, write_algorithm);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ return retval;
+ }
+
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ if (armv7m == NULL) {
+
+ /* something is very wrong if armv7m is NULL */
+ LOG_ERROR("unable to get armv7m target");
+ return retval;
+ }
+
+ /* save any DEMCR flags and configure target to catch any Hard Faults */
+ uint32_t demcr_save = armv7m->demcr;
+ armv7m->demcr = VC_HARDERR;
+
+ /* Loop while there are bytes to write */
+ while (count > 0) {
+ uint32_t this_count;
+ this_count = (count > buffer_size) ? buffer_size : count;
+
+ /* Write the next half pages */
+ retval = target_write_buffer(target, source->address, this_count, buffer);
+ if (retval != ERROR_OK)
+ break;
+
+ /* 4: Store useful information in the registers */
+ /* the destination address of the copy (R0) */
+ buf_set_u32(reg_params[0].value, 0, 32, address);
+ /* The source address of the copy (R1) */
+ buf_set_u32(reg_params[1].value, 0, 32, source->address);
+ /* The length of the copy (R2) */
+ buf_set_u32(reg_params[2].value, 0, 32, this_count / 4);
+
+ /* 5: Execute the bunch of code */
+ retval = target_run_algorithm(target, 0, NULL, sizeof(reg_params)
+ / sizeof(*reg_params), reg_params,
+ write_algorithm->address, 0, 10000, &armv7m_info);
+ if (retval != ERROR_OK)
+ break;
+
+ /* check for Hard Fault */
+ if (armv7m->exception_number == 3)
+ break;
+
+ /* 6: Wait while busy */
+ retval = stm32lx_wait_until_bsy_clear(bank);
+ if (retval != ERROR_OK)
+ break;
+
+ buffer += this_count;
+ address += this_count;
+ count -= this_count;
+ }
+
+ /* restore previous flags */
+ armv7m->demcr = demcr_save;
+
+ if (armv7m->exception_number == 3) {
+
+ /* the stm32l15x devices seem to have an issue when blank.
+ * if a ram loader is executed on a blank device it will
+ * Hard Fault, this issue does not happen for a already programmed device.
+ * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
+ * The workaround of handling the Hard Fault exception does work, but makes the
+ * loader more complicated, as a compromise we manually write the pages, programming time
+ * is reduced by 50% using this slower method.
+ */
+
+ LOG_WARNING("couldn't use loader, falling back to page memory writes");
+
+ while (count > 0) {
+ uint32_t this_count;
+ this_count = (count > hp_nb) ? hp_nb : count;
+
+ /* Write the next half pages */
+ retval = target_write_buffer(target, address, this_count, buffer);
+ if (retval != ERROR_OK)
+ break;
+
+ /* Wait while busy */
+ retval = stm32lx_wait_until_bsy_clear(bank);
+ if (retval != ERROR_OK)
+ break;
+
+ buffer += this_count;
+ address += this_count;
+ count -= this_count;
+ }
+ }
+
+ if (retval == ERROR_OK)
+ retval = stm32lx_lock_program_memory(bank);
+
+ target_free_working_area(target, source);
+ target_free_working_area(target, write_algorithm);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+
+ return retval;
+}
+
+static int stm32lx_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
+
+ uint32_t hp_nb = stm32lx_info->part_info->page_size / 2;
+ uint32_t halfpages_number;
+ uint32_t bytes_remaining = 0;
+ uint32_t address = bank->base + offset;
+ uint32_t bytes_written = 0;
+ int retval, retval2;
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (offset & 0x3) {
+ LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ retval = stm32lx_unlock_program_memory(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* first we need to write any unaligned head bytes upto
+ * the next 128 byte page */
+
+ if (offset % hp_nb)
+ bytes_remaining = MIN(count, hp_nb - (offset % hp_nb));
+
+ while (bytes_remaining > 0) {
+ uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
+
+ /* copy remaining bytes into the write buffer */
+ uint32_t bytes_to_write = MIN(4, bytes_remaining);
+ memcpy(value, buffer + bytes_written, bytes_to_write);
+
+ retval = target_write_buffer(target, address, 4, value);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ bytes_written += bytes_to_write;
+ bytes_remaining -= bytes_to_write;
+ address += 4;
+
+ retval = stm32lx_wait_until_bsy_clear(bank);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+ }
+
+ offset += bytes_written;
+ count -= bytes_written;
+
+ /* this should always pass this check here */
+ assert((offset % hp_nb) == 0);
+
+ /* calculate half pages */
+ halfpages_number = count / hp_nb;
+
+ if (halfpages_number) {
+ retval = stm32lx_write_half_pages(bank, buffer + bytes_written, offset, hp_nb * halfpages_number);
+ if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
+ /* attempt slow memory writes */
+ LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
+ halfpages_number = 0;
+ } else {
+ if (retval != ERROR_OK)
+ return ERROR_FAIL;
+ }
+ }
+
+ /* write any remaining bytes */
+ uint32_t page_bytes_written = hp_nb * halfpages_number;
+ bytes_written += page_bytes_written;
+ address += page_bytes_written;
+ bytes_remaining = count - page_bytes_written;
+
+ retval = stm32lx_unlock_program_memory(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ while (bytes_remaining > 0) {
+ uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
+
+ /* copy remaining bytes into the write buffer */
+ uint32_t bytes_to_write = MIN(4, bytes_remaining);
+ memcpy(value, buffer + bytes_written, bytes_to_write);
+
+ retval = target_write_buffer(target, address, 4, value);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ bytes_written += bytes_to_write;
+ bytes_remaining -= bytes_to_write;
+ address += 4;
+
+ retval = stm32lx_wait_until_bsy_clear(bank);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+ }
+
+reset_pg_and_lock:
+ retval2 = stm32lx_lock_program_memory(bank);
+ if (retval == ERROR_OK)
+ retval = retval2;
+
+ return retval;
+}
+
+static int stm32lx_read_id_code(struct target *target, uint32_t *id)
+{
+ /* read stm32 device id register */
+ int retval = target_read_u32(target, DBGMCU_IDCODE, id);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* STM32L0 parts will have 0 there, try reading the L0's location for
+ * DBG_IDCODE in case this is an L0 part. */
+ if (*id == 0)
+ retval = target_read_u32(target, DBGMCU_IDCODE_L0, id);
+
+ return retval;
+}
+
+static int stm32lx_probe(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
+ int i;
+ uint16_t flash_size_in_kb;
+ uint32_t device_id;
+ uint32_t base_address = FLASH_BANK0_ADDRESS;
+ uint32_t second_bank_base;
+
+ stm32lx_info->probed = 0;
+ stm32lx_info->part_info = NULL;
+
+ int retval = stm32lx_read_id_code(bank->target, &device_id);
+ if (retval != ERROR_OK)
+ return retval;
+
+ stm32lx_info->idcode = device_id;
+
+ LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
+
+ for (unsigned int n = 0; n < ARRAY_SIZE(stm32lx_parts); n++) {
+ if ((device_id & 0xfff) == stm32lx_parts[n].id)
+ stm32lx_info->part_info = &stm32lx_parts[n];
+ }
+
+ if (!stm32lx_info->part_info) {
+ LOG_WARNING("Cannot identify target as a STM32L family.");
+ return ERROR_FAIL;
+ } else {
+ LOG_INFO("Device: %s", stm32lx_info->part_info->device_str);
+ }
+
+ stm32lx_info->flash_base = stm32lx_info->part_info->flash_base;
+
+ /* Get the flash size from target. */
+ retval = target_read_u16(target, stm32lx_info->part_info->fsize_base,
+ &flash_size_in_kb);
+
+ /* 0x436 devices report their flash size as a 0 or 1 code indicating 384K
+ * or 256K, respectively. Please see RM0038 r8 or newer and refer to
+ * section 30.1.1. */
+ if (retval == ERROR_OK && (device_id & 0xfff) == 0x436) {
+ if (flash_size_in_kb == 0)
+ flash_size_in_kb = 384;
+ else if (flash_size_in_kb == 1)
+ flash_size_in_kb = 256;
+ }
+
+ /* Failed reading flash size or flash size invalid (early silicon),
+ * default to max target family */
+ if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
+ LOG_WARNING("STM32L flash size failed, probe inaccurate - assuming %dk flash",
+ stm32lx_info->part_info->max_flash_size_kb);
+ flash_size_in_kb = stm32lx_info->part_info->max_flash_size_kb;
+ } else if (flash_size_in_kb > stm32lx_info->part_info->max_flash_size_kb) {
+ LOG_WARNING("STM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flash",
+ flash_size_in_kb, stm32lx_info->part_info->max_flash_size_kb,
+ stm32lx_info->part_info->max_flash_size_kb);
+ flash_size_in_kb = stm32lx_info->part_info->max_flash_size_kb;
+ }
+
+ if (stm32lx_info->part_info->has_dual_banks) {
+ /* Use the configured base address to determine if this is the first or second flash bank.
+ * Verify that the base address is reasonably correct and determine the flash bank size
+ */
+ second_bank_base = base_address +
+ stm32lx_info->part_info->first_bank_size_kb * 1024;
+ if (bank->base == second_bank_base || !bank->base) {
+ /* This is the second bank */
+ base_address = second_bank_base;
+ flash_size_in_kb = flash_size_in_kb -
+ stm32lx_info->part_info->first_bank_size_kb;
+ } else if (bank->base == base_address) {
+ /* This is the first bank */
+ flash_size_in_kb = stm32lx_info->part_info->first_bank_size_kb;
+ } else {
+ LOG_WARNING("STM32L flash bank base address config is incorrect."
+ " 0x%" PRIx32 " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
+ bank->base, base_address, second_bank_base);
+ return ERROR_FAIL;
+ }
+ LOG_INFO("STM32L flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32,
+ bank->bank_number, flash_size_in_kb, base_address);
+ } else {
+ LOG_INFO("STM32L flash size is %dkb, base address is 0x%" PRIx32, flash_size_in_kb, base_address);
+ }
+
+ /* if the user sets the size manually then ignore the probed value
+ * this allows us to work around devices that have a invalid flash size register value */
+ if (stm32lx_info->user_bank_size) {
+ flash_size_in_kb = stm32lx_info->user_bank_size / 1024;
+ LOG_INFO("ignoring flash probed value, using configured bank size: %dkbytes", flash_size_in_kb);
+ }
+
+ /* calculate numbers of sectors (4kB per sector) */
+ int num_sectors = (flash_size_in_kb * 1024) / FLASH_SECTOR_SIZE;
+
+ if (bank->sectors) {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
+ bank->size = flash_size_in_kb * 1024;
+ bank->base = base_address;
+ bank->num_sectors = num_sectors;
+ bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
+ if (bank->sectors == NULL) {
+ LOG_ERROR("failed to allocate bank sectors");
+ return ERROR_FAIL;
+ }
+
+ for (i = 0; i < num_sectors; i++) {
+ bank->sectors[i].offset = i * FLASH_SECTOR_SIZE;
+ bank->sectors[i].size = FLASH_SECTOR_SIZE;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 1;
+ }
+
+ stm32lx_info->probed = 1;
+
+ return ERROR_OK;
+}
+
+static int stm32lx_auto_probe(struct flash_bank *bank)
+{
+ struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
+
+ if (stm32lx_info->probed)
+ return ERROR_OK;
+
+ return stm32lx_probe(bank);
+}
+
+static int stm32lx_erase_check(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ const int buffer_size = 4096;
+ int i;
+ uint32_t nBytes;
+ int retval = ERROR_OK;
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ uint8_t *buffer = malloc(buffer_size);
+ if (buffer == NULL) {
+ LOG_ERROR("failed to allocate read buffer");
+ return ERROR_FAIL;
+ }
+
+ for (i = 0; i < bank->num_sectors; i++) {
+ uint32_t j;
+ bank->sectors[i].is_erased = 1;
+
+ /* Loop chunk by chunk over the sector */
+ for (j = 0; j < bank->sectors[i].size; j += buffer_size) {
+ uint32_t chunk;
+ chunk = buffer_size;
+ if (chunk > (j - bank->sectors[i].size))
+ chunk = (j - bank->sectors[i].size);
+
+ retval = target_read_memory(target, bank->base
+ + bank->sectors[i].offset + j, 4, chunk / 4, buffer);
+ if (retval != ERROR_OK)
+ break;
+
+ for (nBytes = 0; nBytes < chunk; nBytes++) {
+ if (buffer[nBytes] != 0x00) {
+ bank->sectors[i].is_erased = 0;
+ break;
+ }
+ }
+ }
+ if (retval != ERROR_OK)
+ break;
+ }
+ free(buffer);
+
+ return retval;
+}
+
+/* This method must return a string displaying information about the bank */
+static int stm32lx_get_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
+
+ if (!stm32lx_info->probed) {
+ int retval = stm32lx_probe(bank);
+ if (retval != ERROR_OK) {
+ snprintf(buf, buf_size,
+ "Unable to find bank information.");
+ return retval;
+ }
+ }
+
+ const struct stm32lx_part_info *info = stm32lx_info->part_info;
+
+ if (info) {
+ const char *rev_str = NULL;
+ uint16_t rev_id = stm32lx_info->idcode >> 16;
+
+ for (unsigned int i = 0; i < info->num_revs; i++)
+ if (rev_id == info->revs[i].rev)
+ rev_str = info->revs[i].str;
+
+ if (rev_str != NULL) {
+ snprintf(buf, buf_size,
+ "%s - Rev: %s",
+ stm32lx_info->part_info->device_str, rev_str);
+ } else {
+ snprintf(buf, buf_size,
+ "%s - Rev: unknown (0x%04x)",
+ stm32lx_info->part_info->device_str, rev_id);
+ }
+
+ return ERROR_OK;
+ } else {
+ snprintf(buf, buf_size, "Cannot identify target as a STM32Lx");
+
+ return ERROR_FAIL;
+ }
+}
+
+static const struct command_registration stm32lx_exec_command_handlers[] = {
+ {
+ .name = "mass_erase",
+ .handler = stm32lx_handle_mass_erase_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id",
+ .help = "Erase entire flash device. including available EEPROM",
+ },
+ {
+ .name = "lock",
+ .handler = stm32lx_handle_lock_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id",
+ .help = "Increase the readout protection to Level 1.",
+ },
+ {
+ .name = "unlock",
+ .handler = stm32lx_handle_unlock_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id",
+ .help = "Lower the readout protection from Level 1 to 0.",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration stm32lx_command_handlers[] = {
+ {
+ .name = "stm32lx",
+ .mode = COMMAND_ANY,
+ .help = "stm32lx flash command group",
+ .usage = "",
+ .chain = stm32lx_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+struct flash_driver stm32lx_flash = {
+ .name = "stm32lx",
+ .commands = stm32lx_command_handlers,
+ .flash_bank_command = stm32lx_flash_bank_command,
+ .erase = stm32lx_erase,
+ .protect = stm32lx_protect,
+ .write = stm32lx_write,
+ .read = default_flash_read,
+ .probe = stm32lx_probe,
+ .auto_probe = stm32lx_auto_probe,
+ .erase_check = stm32lx_erase_check,
+ .protect_check = stm32lx_protect_check,
+ .info = stm32lx_get_info,
+};
+
+/* Static methods implementation */
+static int stm32lx_unlock_program_memory(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
+ int retval;
+ uint32_t reg32;
+
+ /*
+ * Unlocking the program memory is done by unlocking the PECR,
+ * then by writing the 2 PRGKEY to the PRGKEYR register
+ */
+
+ /* check flash is not already unlocked */
+ retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
+ ®32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if ((reg32 & FLASH_PECR__PRGLOCK) == 0)
+ return ERROR_OK;
+
+ /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
+ retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR,
+ PEKEY1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR,
+ PEKEY2);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Make sure it worked */
+ retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
+ ®32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (reg32 & FLASH_PECR__PELOCK) {
+ LOG_ERROR("PELOCK is not cleared :(");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR,
+ PRGKEY1);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR,
+ PRGKEY2);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Make sure it worked */
+ retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
+ ®32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (reg32 & FLASH_PECR__PRGLOCK) {
+ LOG_ERROR("PRGLOCK is not cleared :(");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ return ERROR_OK;
+}
+
+static int stm32lx_enable_write_half_page(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
+ int retval;
+ uint32_t reg32;
+
+ /**
+ * Unlock the program memory, then set the FPRG bit in the PECR register.
+ */
+ retval = stm32lx_unlock_program_memory(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
+ ®32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ reg32 |= FLASH_PECR__FPRG;
+ retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
+ reg32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
+ ®32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ reg32 |= FLASH_PECR__PROG;
+ retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
+ reg32);
+
+ return retval;
+}
+
+static int stm32lx_lock_program_memory(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
+ int retval;
+ uint32_t reg32;
+
+ /* To lock the program memory, simply set the lock bit and lock PECR */
+
+ retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
+ ®32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ reg32 |= FLASH_PECR__PRGLOCK;
+ retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
+ reg32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
+ ®32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ reg32 |= FLASH_PECR__PELOCK;
+ retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
+ reg32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int stm32lx_erase_sector(struct flash_bank *bank, int sector)
+{
+ struct target *target = bank->target;
+ struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
+ int retval;
+ uint32_t reg32;
+
+ /*
+ * To erase a sector (i.e. stm32lx_info->part_info.pages_per_sector pages),
+ * first unlock the memory, loop over the pages of this sector
+ * and write 0x0 to its first word.
+ */
+
+ retval = stm32lx_unlock_program_memory(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ for (int page = 0; page < (int)stm32lx_info->part_info->pages_per_sector;
+ page++) {
+ reg32 = FLASH_PECR__PROG | FLASH_PECR__ERASE;
+ retval = target_write_u32(target,
+ stm32lx_info->flash_base + FLASH_PECR, reg32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = stm32lx_wait_until_bsy_clear(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ uint32_t addr = bank->base + bank->sectors[sector].offset + (page
+ * stm32lx_info->part_info->page_size);
+ retval = target_write_u32(target, addr, 0x0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = stm32lx_wait_until_bsy_clear(bank);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ retval = stm32lx_lock_program_memory(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static inline int stm32lx_get_flash_status(struct flash_bank *bank, uint32_t *status)
+{
+ struct target *target = bank->target;
+ struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
+
+ return target_read_u32(target, stm32lx_info->flash_base + FLASH_SR, status);
+}
+
+static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank)
+{
+ return stm32lx_wait_until_bsy_clear_timeout(bank, 100);
+}
+
+static int stm32lx_unlock_options_bytes(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
+ int retval;
+ uint32_t reg32;
+
+ /*
+ * Unlocking the options bytes is done by unlocking the PECR,
+ * then by writing the 2 FLASH_PEKEYR to the FLASH_OPTKEYR register
+ */
+
+ /* check flash is not already unlocked */
+ retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, ®32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if ((reg32 & FLASH_PECR__OPTLOCK) == 0)
+ return ERROR_OK;
+
+ if ((reg32 & FLASH_PECR__PELOCK) != 0) {
+
+ retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, PEKEY1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, PEKEY2);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ /* To unlock the PECR write the 2 OPTKEY to the FLASH_OPTKEYR register */
+ retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_OPTKEYR, OPTKEY1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_OPTKEYR, OPTKEY2);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout)
+{
+ struct target *target = bank->target;
+ struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
+ uint32_t status;
+ int retval = ERROR_OK;
+
+ /* wait for busy to clear */
+ for (;;) {
+ retval = stm32lx_get_flash_status(bank, &status);
+ if (retval != ERROR_OK)
+ return retval;
+
+ LOG_DEBUG("status: 0x%" PRIx32 "", status);
+ if ((status & FLASH_SR__BSY) == 0)
+ break;
+
+ if (timeout-- <= 0) {
+ LOG_ERROR("timed out waiting for flash");
+ return ERROR_FAIL;
+ }
+ alive_sleep(1);
+ }
+
+ if (status & FLASH_SR__WRPERR) {
+ LOG_ERROR("access denied / write protected");
+ retval = ERROR_FAIL;
+ }
+
+ if (status & FLASH_SR__PGAERR) {
+ LOG_ERROR("invalid program address");
+ retval = ERROR_FAIL;
+ }
+
+ /* Clear but report errors */
+ if (status & FLASH_SR__OPTVERR) {
+ /* If this operation fails, we ignore it and report the original retval */
+ target_write_u32(target, stm32lx_info->flash_base + FLASH_SR, status & FLASH_SR__OPTVERR);
+ }
+
+ return retval;
+}
+
+static int stm32lx_obl_launch(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
+ int retval;
+
+ /* This will fail as the target gets immediately rebooted */
+ target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
+ FLASH_PECR__OBL_LAUNCH);
+
+ size_t tries = 10;
+ do {
+ target_halt(target);
+ retval = target_poll(target);
+ } while (--tries > 0 &&
+ (retval != ERROR_OK || target->state != TARGET_HALTED));
+
+ return tries ? ERROR_OK : ERROR_FAIL;
+}
+
+static int stm32lx_lock(struct flash_bank *bank)
+{
+ int retval;
+ struct target *target = bank->target;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ retval = stm32lx_unlock_options_bytes(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* set the RDP protection level to 1 */
+ retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int stm32lx_unlock(struct flash_bank *bank)
+{
+ int retval;
+ struct target *target = bank->target;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ retval = stm32lx_unlock_options_bytes(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* set the RDP protection level to 0 */
+ retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = stm32lx_wait_until_bsy_clear_timeout(bank, 30000);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int stm32lx_mass_erase(struct flash_bank *bank)
+{
+ int retval;
+ struct target *target = bank->target;
+ struct stm32lx_flash_bank *stm32lx_info = NULL;
+ uint32_t reg32;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ stm32lx_info = bank->driver_priv;
+
+ retval = stm32lx_lock(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = stm32lx_obl_launch(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = stm32lx_unlock(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = stm32lx_obl_launch(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, ®32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR, reg32 | FLASH_PECR__OPTLOCK);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/stmsmi.c
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/stmsmi.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/stmsmi.c
new file mode 100755
index 0000000..6f73c36
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/stmsmi.c
@@ -0,0 +1,659 @@
+/***************************************************************************
+ * Copyright (C) 2010 by Antonio Borneo <bo...@gmail.com> *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+/* STM Serial Memory Interface (SMI) controller is a SPI bus controller
+ * specifically designed for SPI memories.
+ * Only SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
+ * Two working modes are available:
+ * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
+ * on the bus.
+ * - HW mode: the SPI but is under SMI control. Memory content is directly
+ * accessible in CPU memory space. CPU can read, write and execute memory
+ * content. */
+
+/* ATTENTION:
+ * To have flash memory mapped in CPU memory space, the SMI controller
+ * have to be in "HW mode". This requires following constraints:
+ * 1) The command "reset init" have to initialize SMI controller and put
+ * it in HW mode;
+ * 2) every command in this file have to return to prompt in HW mode. */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include "spi.h"
+#include <jtag/jtag.h>
+#include <helper/time_support.h>
+
+#define SMI_READ_REG(a) (_SMI_READ_REG(a))
+#define _SMI_READ_REG(a) \
+{ \
+ int __a; \
+ uint32_t __v; \
+ \
+ __a = target_read_u32(target, io_base + (a), &__v); \
+ if (__a != ERROR_OK) \
+ return __a; \
+ __v; \
+}
+
+#define SMI_WRITE_REG(a, v) \
+{ \
+ int __r; \
+ \
+ __r = target_write_u32(target, io_base + (a), (v)); \
+ if (__r != ERROR_OK) \
+ return __r; \
+}
+
+#define SMI_POLL_TFF(timeout) \
+{ \
+ int __r; \
+ \
+ __r = poll_tff(target, io_base, timeout); \
+ if (__r != ERROR_OK) \
+ return __r; \
+}
+
+#define SMI_SET_SW_MODE() SMI_WRITE_REG(SMI_CR1, \
+ SMI_READ_REG(SMI_CR1) | SMI_SW_MODE)
+#define SMI_SET_HWWB_MODE() SMI_WRITE_REG(SMI_CR1, \
+ (SMI_READ_REG(SMI_CR1) | SMI_WB_MODE) & ~SMI_SW_MODE)
+#define SMI_SET_HW_MODE() SMI_WRITE_REG(SMI_CR1, \
+ SMI_READ_REG(SMI_CR1) & ~(SMI_SW_MODE | SMI_WB_MODE))
+#define SMI_CLEAR_TFF() SMI_WRITE_REG(SMI_SR, ~SMI_TFF)
+
+#define SMI_BANK_SIZE (0x01000000)
+
+#define SMI_CR1 (0x00) /* Control register 1 */
+#define SMI_CR2 (0x04) /* Control register 2 */
+#define SMI_SR (0x08) /* Status register */
+#define SMI_TR (0x0c) /* TX */
+#define SMI_RR (0x10) /* RX */
+
+/* fields in SMI_CR1 */
+#define SMI_SW_MODE 0x10000000 /* set to enable SW Mode */
+#define SMI_WB_MODE 0x20000000 /* Write Burst Mode */
+
+/* fields in SMI_CR2 */
+#define SMI_TX_LEN_1 0x00000001 /* data length = 1 byte */
+#define SMI_TX_LEN_4 0x00000004 /* data length = 4 byte */
+#define SMI_RX_LEN_3 0x00000030 /* data length = 3 byte */
+#define SMI_SEND 0x00000080 /* Send data */
+#define SMI_RSR 0x00000400 /* reads status reg */
+#define SMI_WE 0x00000800 /* Write Enable */
+#define SMI_SEL_BANK0 0x00000000 /* Select Bank0 */
+#define SMI_SEL_BANK1 0x00001000 /* Select Bank1 */
+#define SMI_SEL_BANK2 0x00002000 /* Select Bank2 */
+#define SMI_SEL_BANK3 0x00003000 /* Select Bank3 */
+
+/* fields in SMI_SR */
+#define SMI_TFF 0x00000100 /* Transfer Finished Flag */
+
+/* Commands */
+#define SMI_READ_ID 0x0000009F /* Read Flash Identification */
+
+/* Timeout in ms */
+#define SMI_CMD_TIMEOUT (100)
+#define SMI_PROBE_TIMEOUT (100)
+#define SMI_MAX_TIMEOUT (3000)
+
+struct stmsmi_flash_bank {
+ int probed;
+ uint32_t io_base;
+ uint32_t bank_num;
+ const struct flash_device *dev;
+};
+
+struct stmsmi_target {
+ char *name;
+ uint32_t tap_idcode;
+ uint32_t smi_base;
+ uint32_t io_base;
+};
+
+static const struct stmsmi_target target_devices[] = {
+ /* name, tap_idcode, smi_base, io_base */
+ { "SPEAr3xx/6xx", 0x07926041, 0xf8000000, 0xfc000000 },
+ { "STR75x", 0x4f1f0041, 0x80000000, 0x90000000 },
+ { NULL, 0, 0, 0 }
+};
+
+FLASH_BANK_COMMAND_HANDLER(stmsmi_flash_bank_command)
+{
+ struct stmsmi_flash_bank *stmsmi_info;
+
+ LOG_DEBUG("%s", __func__);
+
+ if (CMD_ARGC < 6)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ stmsmi_info = malloc(sizeof(struct stmsmi_flash_bank));
+ if (stmsmi_info == NULL) {
+ LOG_ERROR("not enough memory");
+ return ERROR_FAIL;
+ }
+
+ bank->driver_priv = stmsmi_info;
+ stmsmi_info->probed = 0;
+
+ return ERROR_OK;
+}
+
+/* Poll transmit finished flag */
+/* timeout in ms */
+static int poll_tff(struct target *target, uint32_t io_base, int timeout)
+{
+ long long endtime;
+
+ if (SMI_READ_REG(SMI_SR) & SMI_TFF)
+ return ERROR_OK;
+
+ endtime = timeval_ms() + timeout;
+ do {
+ alive_sleep(1);
+ if (SMI_READ_REG(SMI_SR) & SMI_TFF)
+ return ERROR_OK;
+ } while (timeval_ms() < endtime);
+
+ LOG_ERROR("Timeout while polling TFF");
+ return ERROR_FLASH_OPERATION_FAILED;
+}
+
+/* Read the status register of the external SPI flash chip.
+ * The operation is triggered by setting SMI_RSR bit.
+ * SMI sends the proper SPI command (0x05) and returns value in SMI_SR */
+static int read_status_reg(struct flash_bank *bank, uint32_t *status)
+{
+ struct target *target = bank->target;
+ struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
+ uint32_t io_base = stmsmi_info->io_base;
+
+ /* clear transmit finished flag */
+ SMI_CLEAR_TFF();
+
+ /* Read status */
+ SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_RSR);
+
+ /* Poll transmit finished flag */
+ SMI_POLL_TFF(SMI_CMD_TIMEOUT);
+
+ /* clear transmit finished flag */
+ SMI_CLEAR_TFF();
+
+ *status = SMI_READ_REG(SMI_SR) & 0x0000ffff;
+
+ /* clean-up SMI_CR2 */
+ SMI_WRITE_REG(SMI_CR2, 0); /* AB: Required ? */
+
+ return ERROR_OK;
+}
+
+/* check for WIP (write in progress) bit in status register */
+/* timeout in ms */
+static int wait_till_ready(struct flash_bank *bank, int timeout)
+{
+ uint32_t status;
+ int retval;
+ long long endtime;
+
+ endtime = timeval_ms() + timeout;
+ do {
+ /* read flash status register */
+ retval = read_status_reg(bank, &status);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if ((status & SPIFLASH_BSY_BIT) == 0)
+ return ERROR_OK;
+ alive_sleep(1);
+ } while (timeval_ms() < endtime);
+
+ LOG_ERROR("timeout");
+ return ERROR_FAIL;
+}
+
+/* Send "write enable" command to SPI flash chip.
+ * The operation is triggered by setting SMI_WE bit, and SMI sends
+ * the proper SPI command (0x06) */
+static int smi_write_enable(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
+ uint32_t io_base = stmsmi_info->io_base;
+ uint32_t status;
+ int retval;
+
+ /* Enter in HW mode */
+ SMI_SET_HW_MODE(); /* AB: is this correct ?*/
+
+ /* clear transmit finished flag */
+ SMI_CLEAR_TFF();
+
+ /* Send write enable command */
+ SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_WE);
+
+ /* Poll transmit finished flag */
+ SMI_POLL_TFF(SMI_CMD_TIMEOUT);
+
+ /* read flash status register */
+ retval = read_status_reg(bank, &status);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Check write enabled */
+ if ((status & SPIFLASH_WE_BIT) == 0) {
+ LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+static uint32_t erase_command(struct stmsmi_flash_bank *stmsmi_info,
+ uint32_t offset)
+{
+ union {
+ uint32_t command;
+ uint8_t x[4];
+ } cmd;
+
+ cmd.x[0] = stmsmi_info->dev->erase_cmd;
+ cmd.x[1] = offset >> 16;
+ cmd.x[2] = offset >> 8;
+ cmd.x[3] = offset;
+
+ return cmd.command;
+}
+
+static int smi_erase_sector(struct flash_bank *bank, int sector)
+{
+ struct target *target = bank->target;
+ struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
+ uint32_t io_base = stmsmi_info->io_base;
+ uint32_t cmd;
+ int retval;
+
+ retval = smi_write_enable(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Switch to SW mode to send sector erase command */
+ SMI_SET_SW_MODE();
+
+ /* clear transmit finished flag */
+ SMI_CLEAR_TFF();
+
+ /* send SPI command "block erase" */
+ cmd = erase_command(stmsmi_info, bank->sectors[sector].offset);
+ SMI_WRITE_REG(SMI_TR, cmd);
+ SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_SEND | SMI_TX_LEN_4);
+
+ /* Poll transmit finished flag */
+ SMI_POLL_TFF(SMI_CMD_TIMEOUT);
+
+ /* poll WIP for end of self timed Sector Erase cycle */
+ retval = wait_till_ready(bank, SMI_MAX_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int stmsmi_erase(struct flash_bank *bank, int first, int last)
+{
+ struct target *target = bank->target;
+ struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
+ uint32_t io_base = stmsmi_info->io_base;
+ int retval = ERROR_OK;
+ int sector;
+
+ LOG_DEBUG("%s: from sector %d to sector %d", __func__, first, last);
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
+ LOG_ERROR("Flash sector invalid");
+ return ERROR_FLASH_SECTOR_INVALID;
+ }
+
+ if (!(stmsmi_info->probed)) {
+ LOG_ERROR("Flash bank not probed");
+ return ERROR_FLASH_BANK_NOT_PROBED;
+ }
+
+ for (sector = first; sector <= last; sector++) {
+ if (bank->sectors[sector].is_protected) {
+ LOG_ERROR("Flash sector %d protected", sector);
+ return ERROR_FAIL;
+ }
+ }
+
+ for (sector = first; sector <= last; sector++) {
+ retval = smi_erase_sector(bank, sector);
+ if (retval != ERROR_OK)
+ break;
+ keep_alive();
+ }
+
+ /* Switch to HW mode before return to prompt */
+ SMI_SET_HW_MODE();
+ return retval;
+}
+
+static int stmsmi_protect(struct flash_bank *bank, int set,
+ int first, int last)
+{
+ int sector;
+
+ for (sector = first; sector <= last; sector++)
+ bank->sectors[sector].is_protected = set;
+ return ERROR_OK;
+}
+
+static int smi_write_buffer(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t address, uint32_t len)
+{
+ struct target *target = bank->target;
+ struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
+ uint32_t io_base = stmsmi_info->io_base;
+ int retval;
+
+ LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
+ __func__, address, len);
+
+ retval = smi_write_enable(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* HW mode, write burst mode */
+ SMI_SET_HWWB_MODE();
+
+ retval = target_write_buffer(target, address, len, buffer);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int stmsmi_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
+ uint32_t io_base = stmsmi_info->io_base;
+ uint32_t cur_count, page_size, page_offset;
+ int sector;
+ int retval = ERROR_OK;
+
+ LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
+ __func__, offset, count);
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (offset + count > stmsmi_info->dev->size_in_bytes) {
+ LOG_WARNING("Write pasts end of flash. Extra data discarded.");
+ count = stmsmi_info->dev->size_in_bytes - offset;
+ }
+
+ /* Check sector protection */
+ for (sector = 0; sector < bank->num_sectors; sector++) {
+ /* Start offset in or before this sector? */
+ /* End offset in or behind this sector? */
+ if ((offset <
+ (bank->sectors[sector].offset + bank->sectors[sector].size))
+ && ((offset + count - 1) >= bank->sectors[sector].offset)
+ && bank->sectors[sector].is_protected) {
+ LOG_ERROR("Flash sector %d protected", sector);
+ return ERROR_FAIL;
+ }
+ }
+
+ page_size = stmsmi_info->dev->pagesize;
+
+ /* unaligned buffer head */
+ if (count > 0 && (offset & 3) != 0) {
+ cur_count = 4 - (offset & 3);
+ if (cur_count > count)
+ cur_count = count;
+ retval = smi_write_buffer(bank, buffer, bank->base + offset,
+ cur_count);
+ if (retval != ERROR_OK)
+ goto err;
+ offset += cur_count;
+ buffer += cur_count;
+ count -= cur_count;
+ }
+
+ page_offset = offset % page_size;
+ /* central part, aligned words */
+ while (count >= 4) {
+ /* clip block at page boundary */
+ if (page_offset + count > page_size)
+ cur_count = page_size - page_offset;
+ else
+ cur_count = count & ~3;
+
+ retval = smi_write_buffer(bank, buffer, bank->base + offset,
+ cur_count);
+ if (retval != ERROR_OK)
+ goto err;
+
+ page_offset = 0;
+ buffer += cur_count;
+ offset += cur_count;
+ count -= cur_count;
+
+ keep_alive();
+ }
+
+ /* buffer tail */
+ if (count > 0)
+ retval = smi_write_buffer(bank, buffer, bank->base + offset, count);
+
+err:
+ /* Switch to HW mode before return to prompt */
+ SMI_SET_HW_MODE();
+ return retval;
+}
+
+/* Return ID of flash device */
+/* On exit, SW mode is kept */
+static int read_flash_id(struct flash_bank *bank, uint32_t *id)
+{
+ struct target *target = bank->target;
+ struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
+ uint32_t io_base = stmsmi_info->io_base;
+ int retval;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /* poll WIP */
+ retval = wait_till_ready(bank, SMI_PROBE_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* enter in SW mode */
+ SMI_SET_SW_MODE();
+
+ /* clear transmit finished flag */
+ SMI_CLEAR_TFF();
+
+ /* Send SPI command "read ID" */
+ SMI_WRITE_REG(SMI_TR, SMI_READ_ID);
+ SMI_WRITE_REG(SMI_CR2,
+ stmsmi_info->bank_num | SMI_SEND | SMI_RX_LEN_3 | SMI_TX_LEN_1);
+
+ /* Poll transmit finished flag */
+ SMI_POLL_TFF(SMI_CMD_TIMEOUT);
+
+ /* clear transmit finished flag */
+ SMI_CLEAR_TFF();
+
+ /* read ID from Receive Register */
+ *id = SMI_READ_REG(SMI_RR) & 0x00ffffff;
+ return ERROR_OK;
+}
+
+static int stmsmi_probe(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
+ uint32_t io_base;
+ struct flash_sector *sectors;
+ uint32_t id = 0; /* silence uninitialized warning */
+ const struct stmsmi_target *target_device;
+ int retval;
+
+ if (stmsmi_info->probed)
+ free(bank->sectors);
+ stmsmi_info->probed = 0;
+
+ for (target_device = target_devices ; target_device->name ; ++target_device)
+ if (target_device->tap_idcode == target->tap->idcode)
+ break;
+ if (!target_device->name) {
+ LOG_ERROR("Device ID 0x%" PRIx32 " is not known as SMI capable",
+ target->tap->idcode);
+ return ERROR_FAIL;
+ }
+
+ switch (bank->base - target_device->smi_base) {
+ case 0:
+ stmsmi_info->bank_num = SMI_SEL_BANK0;
+ break;
+ case SMI_BANK_SIZE:
+ stmsmi_info->bank_num = SMI_SEL_BANK1;
+ break;
+ case 2*SMI_BANK_SIZE:
+ stmsmi_info->bank_num = SMI_SEL_BANK2;
+ break;
+ case 3*SMI_BANK_SIZE:
+ stmsmi_info->bank_num = SMI_SEL_BANK3;
+ break;
+ default:
+ LOG_ERROR("Invalid SMI base address 0x%" PRIx32, bank->base);
+ return ERROR_FAIL;
+ }
+ io_base = target_device->io_base;
+ stmsmi_info->io_base = io_base;
+
+ LOG_DEBUG("Valid SMI on device %s at address 0x%" PRIx32,
+ target_device->name, bank->base);
+
+ /* read and decode flash ID; returns in SW mode */
+ retval = read_flash_id(bank, &id);
+ SMI_SET_HW_MODE();
+ if (retval != ERROR_OK)
+ return retval;
+
+ stmsmi_info->dev = NULL;
+ for (const struct flash_device *p = flash_devices; p->name ; p++)
+ if (p->device_id == id) {
+ stmsmi_info->dev = p;
+ break;
+ }
+
+ if (!stmsmi_info->dev) {
+ LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
+ return ERROR_FAIL;
+ }
+
+ LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
+ stmsmi_info->dev->name, stmsmi_info->dev->device_id);
+
+ /* Set correct size value */
+ bank->size = stmsmi_info->dev->size_in_bytes;
+
+ /* create and fill sectors array */
+ bank->num_sectors =
+ stmsmi_info->dev->size_in_bytes / stmsmi_info->dev->sectorsize;
+ sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
+ if (sectors == NULL) {
+ LOG_ERROR("not enough memory");
+ return ERROR_FAIL;
+ }
+
+ for (int sector = 0; sector < bank->num_sectors; sector++) {
+ sectors[sector].offset = sector * stmsmi_info->dev->sectorsize;
+ sectors[sector].size = stmsmi_info->dev->sectorsize;
+ sectors[sector].is_erased = -1;
+ sectors[sector].is_protected = 1;
+ }
+
+ bank->sectors = sectors;
+ stmsmi_info->probed = 1;
+ return ERROR_OK;
+}
+
+static int stmsmi_auto_probe(struct flash_bank *bank)
+{
+ struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
+ if (stmsmi_info->probed)
+ return ERROR_OK;
+ return stmsmi_probe(bank);
+}
+
+static int stmsmi_protect_check(struct flash_bank *bank)
+{
+ /* Nothing to do. Protection is only handled in SW. */
+ return ERROR_OK;
+}
+
+static int get_stmsmi_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
+
+ if (!(stmsmi_info->probed)) {
+ snprintf(buf, buf_size,
+ "\nSMI flash bank not probed yet\n");
+ return ERROR_OK;
+ }
+
+ snprintf(buf, buf_size, "\nSMI flash information:\n"
+ " Device \'%s\' (ID 0x%08" PRIx32 ")\n",
+ stmsmi_info->dev->name, stmsmi_info->dev->device_id);
+
+ return ERROR_OK;
+}
+
+struct flash_driver stmsmi_flash = {
+ .name = "stmsmi",
+ .flash_bank_command = stmsmi_flash_bank_command,
+ .erase = stmsmi_erase,
+ .protect = stmsmi_protect,
+ .write = stmsmi_write,
+ .read = default_flash_read,
+ .probe = stmsmi_probe,
+ .auto_probe = stmsmi_auto_probe,
+ .erase_check = default_flash_blank_check,
+ .protect_check = stmsmi_protect_check,
+ .info = get_stmsmi_info,
+};