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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/08/06 07:31:39 UTC
[incubator-nuttx] 10/10: imrt105x:ENET Match Data sheet Naming
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 6ab76bfc7ca86a6bc73811233a73f745ce5d1006
Author: David Sidrane <Da...@NscDg.com>
AuthorDate: Fri Aug 5 09:51:27 2022 -0700
imrt105x:ENET Match Data sheet Naming
---
arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h | 24 +++++++---------------
.../src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h | 2 +-
2 files changed, 8 insertions(+), 18 deletions(-)
diff --git a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h
index f323f20dea..94ec88384b 100644
--- a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h
+++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h
@@ -967,34 +967,24 @@
/* Analog ENET PLL Control Register */
-#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0) /* Bits 0-1: Controls the frequency of the ethernet0 reference clock */
-#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
-# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
-# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
-# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
-# define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
-#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2) /* Bits 0-1: Controls the frequency of the ethernet1 reference clock */
+#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (0) /* Bits 0-1: Controls the frequency of the ethernet0 reference clock */
#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0x3 << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)
# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_25MHZ ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)
# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)
# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_100MHZ ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)
# define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_125MHZ ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)
- /* Bits 4-11: Reserved */
-#define CCM_ANALOG_PLL_ENET_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */
-#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN (1 << 13) /* Bit 13: Enable the PLL providing the ENET1 125 MHz reference clock */
-#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */
+ /* Bits 2-11: Reserved */
+#define CCM_ANALOG_PLL_ENET_POWERDOWN (1 << 12) /* Bit 12: Powers down the PLL */
+#define CCM_ANALOG_PLL_ENET_ENABLE (1 << 13) /* Bit 13: Enable the PLL providing the ENET1 125 MHz reference clock */
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14) /* Bits 14-15: Determines the bypass source */
#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0x3 << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)
# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
# define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_CLK1 ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */
#define CCM_ANALOG_PLL_ENET_BYPASS (1 << 16) /* Bit 16: Bypass the PLL */
- /* Bit 17: Reserved */
-#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN (1 << 18) /* Bit 18: Enables an offset in the phase frequency detector */
-#define CCM_ANALOG_PLL_ENET_ENABLE_125M (1 << 19) /* Bit 19: */
-#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN (1 << 20) /* Bit 20: Enable the PLL providing the ENET2 125 MHz reference clock */
+ /* Bits 17-20: Reserved */
#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN (1 << 21) /* Bit 21: Enable the PLL providing ENET 25 MHz reference clock */
-#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN (1 << 22) /* Bit 22: Enable the PLL providing NET 500 MHz reference clock */
-
+ /* Bits 22-30: Reserved */
#define CCM_ANALOG_PLL_ENET_LOCK (1 << 31) /* Bit 31: PLL is currently locked */
/* 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
diff --git a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h
index 61e725a839..0c32cd4093 100644
--- a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h
+++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h
@@ -1270,7 +1270,7 @@
#define GPR_GPR1_GINT (1 << 12)
#define GPR_GPR1_ENET1_CLK_SEL (1 << 13)
#define GPR_GPR1_USB_EXP_MODE_EN (1 << 15)
-#define GPR_GPR1_ENET1_TX_CLK_OUT_EN (1 << 17)
+#define GPR_GPR1_ENET1_TX_DIR_OUT (1 << 17)
#define GPR_GPR1_SAI1_MCLK_DIR_IN (0 << 19)
#define GPR_GPR1_SAI1_MCLK_DIR_OUT (1 << 19)
#define GPR_GPR1_SAI2_MCLK_DIR_IN (0 << 20)