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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/01/18 10:19:18 UTC
[incubator-nuttx] 02/04: boards/nucleo-g431rb: add option to select HSI or HSE ass PLL source
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit d3841eb753af3cc8d05a518f55b680fdc834d912
Author: raiden00pl <ra...@railab.me>
AuthorDate: Sat Jan 15 13:40:39 2022 +0100
boards/nucleo-g431rb: add option to select HSI or HSE ass PLL source
---
boards/arm/stm32/nucleo-g431rb/Kconfig | 12 ++++
boards/arm/stm32/nucleo-g431rb/include/board.h | 92 +++++++++++++++++++++++++-
2 files changed, 102 insertions(+), 2 deletions(-)
diff --git a/boards/arm/stm32/nucleo-g431rb/Kconfig b/boards/arm/stm32/nucleo-g431rb/Kconfig
index f61cd04..1239f49 100644
--- a/boards/arm/stm32/nucleo-g431rb/Kconfig
+++ b/boards/arm/stm32/nucleo-g431rb/Kconfig
@@ -5,6 +5,18 @@
if ARCH_BOARD_NUCLEO_G431RB
+choice
+ prompt "PLL Clock source"
+ default BOARD_NUCLEO_G431RB_HSI
+
+config BOARD_NUCLEO_G431RB_USE_HSI
+ bool "HSI"
+
+config BOARD_NUCLEO_G431RB_USE_HSE
+ bool "HSE"
+
+endchoice
+
if SENSORS_QENCODER
config NUCLEO_G431RB_QETIMER
diff --git a/boards/arm/stm32/nucleo-g431rb/include/board.h b/boards/arm/stm32/nucleo-g431rb/include/board.h
index 36af6e1..ecadfef 100644
--- a/boards/arm/stm32/nucleo-g431rb/include/board.h
+++ b/boards/arm/stm32/nucleo-g431rb/include/board.h
@@ -33,13 +33,15 @@
/* Clocking *****************************************************************/
-#undef STM32_BOARD_XTAL /* Not installed by default */
+#define STM32_BOARD_XTAL 24000000 /* 8MHz */
#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */
#define STM32_LSI_FREQUENCY 32000 /* 32kHz */
-#undef STM32_HSE_FREQUENCY /* Not installed by default */
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#undef STM32_LSE_FREQUENCY /* Not available on this board */
+#ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSI
+
/* Main PLL Configuration.
*
* PLL source is HSI = 16MHz
@@ -120,6 +122,92 @@
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
+#endif /* CONFIG_BOARD_NUCLEO_G431RB_USE_HSI */
+
+#ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSE
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE = 24MHz
+ * PLLN = 86, PLLM = 6, PLLP = 10, PLLQ = 2, PLLR = 2
+ *
+ * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM)
+ * f(PLL_P) = f(VCO Clock) / PLLP
+ * f(PLL_Q) = f(VCO Clock) / PLLQ
+ * f(PLL_R) = f(VCO Clock) / PLLR
+ *
+ * Where:
+ * 8 <= PLLN <= 127
+ * 1 <= PLLM <= 16
+ * PLLP = 2 through 31
+ * PLLQ = 2, 4, 6, or 8
+ * PLLR = 2, 4, 6, or 8
+ *
+ * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R).
+ * 64MHz <= f(VCO Clock) <= 344MHz.
+ *
+ * Given the above:
+ *
+ * f(VCO Clock) = HSE x PLLN / PLLM
+ * = 24MHz x 86 / 6
+ * = 340MHz
+ *
+ * PLLPCLK = f(VCO Clock) / PLLP
+ * = 340MHz / 10
+ * = 34MHz
+ * (May be used for ADC)
+ *
+ * PLLQCLK = f(VCO Clock) / PLLQ
+ * = 340MHz / 2
+ * = 170MHz
+ * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to
+ * 48MHz, may be used for USB, RNG.)
+ *
+ * PLLRCLK = f(VCO Clock) / PLLR
+ * = 340MHz / 2
+ * = 170MHz
+ * (May be used for SYSCLK and most peripherals.)
+ */
+
+#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSE
+#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \
+ RCC_PLLCFGR_PLLQEN | \
+ RCC_PLLCFGR_PLLREN)
+
+#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(86)
+#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(6)
+#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10)
+#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2
+#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2
+
+#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85)
+#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10)
+#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2)
+#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2)
+
+/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */
+
+#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
+#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
+#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY
+
+/* AHB clock (HCLK) is SYSCLK (170MHz) */
+
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
+#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
+
+/* APB1 clock (PCLK1) is HCLK (170MHz) */
+
+#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
+#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY
+
+/* APB2 clock (PCLK2) is HCLK (170MHz) */
+
+#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
+#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
+
+#endif /* CONFIG_BOARD_NUCLEO_G431RB_USE_HSE */
+
/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */
/* Timers driven from APB2 will be PCLK2 */