You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@nuttx.apache.org by xi...@apache.org on 2021/02/02 05:36:00 UTC
[incubator-nuttx] branch master updated: RV64: add R_RISCV_HI20 and
R_RISCV_LO12_I to elf relocateadd for absolute address loading.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new de8e3a1 RV64: add R_RISCV_HI20 and R_RISCV_LO12_I to elf relocateadd for absolute address loading.
de8e3a1 is described below
commit de8e3a130ce52136d946f689bb2b4ed8c7a05b49
Author: hotislandn <ho...@hotmail.com>
AuthorDate: Mon Feb 1 14:47:14 2021 +0800
RV64: add R_RISCV_HI20 and R_RISCV_LO12_I to elf relocateadd for absolute address loading.
Signed-off-by: hotislandn <ho...@hotmail.com>
---
libs/libc/machine/risc-v/rv64/arch_elf.c | 51 +++++++++++++++++++++++++++++++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/libs/libc/machine/risc-v/rv64/arch_elf.c b/libs/libc/machine/risc-v/rv64/arch_elf.c
index 85a78a0e..247e50b 100644
--- a/libs/libc/machine/risc-v/rv64/arch_elf.c
+++ b/libs/libc/machine/risc-v/rv64/arch_elf.c
@@ -37,7 +37,10 @@
* Pre-processor Definitions
****************************************************************************/
-#define OPCODE_SW 0x23
+#define OPCODE_SW 0x23
+#define OPCODE_LUI 0x37
+
+#define RVI_OPCODE_MASK 0x7F
/****************************************************************************
* Private Data Types
@@ -60,6 +63,8 @@ static struct rname_code_s _rname_table[] =
{"PCREL_LO12_I", R_RISCV_PCREL_LO12_I},
{"PCREL_LO12_S", R_RISCV_PCREL_LO12_S},
{"PCREL_HI20", R_RISCV_PCREL_HI20},
+ {"HI20", R_RISCV_HI20},
+ {"LO12_I", R_RISCV_LO12_I},
{"CALL", R_RISCV_CALL},
{"BRANCH", R_RISCV_BRANCH},
{"RVC_JUMP", R_RISCV_RVC_JUMP},
@@ -373,6 +378,50 @@ int up_relocateadd(FAR const Elf64_Rela *rel, FAR const Elf64_Sym *sym,
}
break;
+ case R_RISCV_HI20:
+ {
+ binfo("%s at %08lx [%08x] to sym=%p st_value=%08lx\n",
+ _get_rname(relotype),
+ (long)addr, _get_val((uint16_t *)addr),
+ sym, (long)sym->st_value);
+
+ /* P.19 LUI */
+
+ offset = (long)sym->st_value;
+ uint32_t insn = _get_val((uint16_t *)addr);
+
+ ASSERT(OPCODE_LUI == (insn & RVI_OPCODE_MASK));
+
+ long imm_hi;
+ long imm_lo;
+ _calc_imm(offset, &imm_hi, &imm_lo);
+ insn = (insn & 0x00000fff) | (imm_hi << 12);
+
+ _set_val((uint16_t *)addr, insn);
+ }
+ break;
+
+ case R_RISCV_LO12_I:
+ {
+ binfo("%s at %08lx [%08x] to sym=%p st_value=%08lx\n",
+ _get_rname(relotype),
+ (long)addr, _get_val((uint16_t *)addr),
+ sym, (long)sym->st_value);
+
+ /* ADDI, FLW, LD, ... : I-type */
+
+ offset = (long)sym->st_value;
+ uint32_t insn = _get_val((uint16_t *)addr);
+
+ long imm_hi;
+ long imm_lo;
+ _calc_imm(offset, &imm_hi, &imm_lo);
+ insn = (insn & 0x000fffff) | (imm_lo << 20);
+
+ _set_val((uint16_t *)addr, insn);
+ }
+ break;
+
case R_RISCV_RVC_JUMP:
{
binfo("%s at %08lx [%04x] to sym=%p st_value=%08lx\n",