You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@mynewt.apache.org by GitBox <gi...@apache.org> on 2020/09/03 07:45:48 UTC
[GitHub] [mynewt-core] andrzej-kaczmarek opened a new pull request #2368: hw: Add MCU and BSP for Dialog CMAC
andrzej-kaczmarek opened a new pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368
Dialog CMAC is a hw block inside DA1469x MCU family that is based on Cortex-M0+ core and has various peripherals, including radio, to allow running a Bluetooth LE controller (e.g. NimBLE).
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] andrzej-kaczmarek commented on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
andrzej-kaczmarek commented on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-694794636
> this is really awesome! but... hw/mcu/dialog/include/CMAC.h and hw/mcu/dialog/include/system_CMAC.h license needs to be sorted out before this can go in.
>
> (hint: eg BSD3, which is license used in hw/mcu/dialog/include/DA1469xAB.h)
Dialog agreed to release both files with BSD license, I'll update soon.
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot commented on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-686343367
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot commented on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-695954842
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] andrzej-kaczmarek commented on a change in pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
andrzej-kaczmarek commented on a change in pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#discussion_r490855480
##########
File path: hw/bsp/dialog_cmac/dialog_cmac_download.sh
##########
@@ -0,0 +1,35 @@
+#!/bin/bash
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+
+/home/andk/tools/dialog/cli_programmer \
Review comment:
I'll remove this file since CMAC image is linked with M33 image so this script is useless - it was used during dev
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] andrzej-kaczmarek merged pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
andrzej-kaczmarek merged pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot commented on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-694821061
<!-- license-bot -->
## RAT Report (2020-09-18 11:44:41)
## New files with unknown licenses
* <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/cmac.ld">hw/mcu/dialog/cmac/cmac.ld</a>
* <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/include/CMAC.h">hw/mcu/dialog/include/CMAC.h</a>
* <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/include/system_CMAC.h">hw/mcu/dialog/include/system_CMAC.h</a>
## 39 new files were excluded from check (.rat-excludes)
<details>
<summary>Detailed analysis</summary>
## New files in this PR
| License | File |
|---------|------|
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/bsp/dialog_cmac/bsp.yml">hw/bsp/dialog_cmac/bsp.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/bsp/dialog_cmac/cmac.ld">hw/bsp/dialog_cmac/cmac.ld</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/bsp/dialog_cmac/dialog_cmac_debug.sh">hw/bsp/dialog_cmac/dialog_cmac_debug.sh</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/bsp/dialog_cmac/pkg.yml">hw/bsp/dialog_cmac/pkg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/bsp/dialog_cmac/syscfg.yml">hw/bsp/dialog_cmac/syscfg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/bsp/dialog_cmac/include/bsp/bsp.h">hw/bsp/dialog_cmac/include/bsp/bsp.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/bsp/dialog_cmac/src/hal_bsp.c">hw/bsp/dialog_cmac/src/hal_bsp.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/bsp/dialog_cmac/src/sbrk.c">hw/bsp/dialog_cmac/src/sbrk.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/bsp/dialog_cmac/src/arch/cortex_m0_cmac/gcc_startup_cmac.S">hw/bsp/dialog_cmac/src/arch/cortex_m0_cmac/gcc_startup_cmac.S</a> |
| ????? | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/cmac.ld">hw/mcu/dialog/cmac/cmac.ld</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/pkg.yml">hw/mcu/dialog/cmac/pkg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/syscfg.yml">hw/mcu/dialog/cmac/syscfg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch.h">hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch_cmac.h">hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch_cmac.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/include/mcu/cmac_hal.h">hw/mcu/dialog/cmac/include/mcu/cmac_hal.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/include/mcu/cmac_pdc.h">hw/mcu/dialog/cmac/include/mcu/cmac_pdc.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/include/mcu/cmac_periph.h">hw/mcu/dialog/cmac/include/mcu/cmac_periph.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/include/mcu/cmac_timer.h">hw/mcu/dialog/cmac/include/mcu/cmac_timer.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/include/mcu/cortex_m0.h">hw/mcu/dialog/cmac/include/mcu/cortex_m0.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/include/mcu/mcu.h">hw/mcu/dialog/cmac/include/mcu/mcu.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/src/cmac_isr.c">hw/mcu/dialog/cmac/src/cmac_isr.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/src/cmac_periph.c">hw/mcu/dialog/cmac/src/cmac_periph.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/src/cmac_priv.h">hw/mcu/dialog/cmac/src/cmac_priv.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/src/cmac_sleep.c">hw/mcu/dialog/cmac/src/cmac_sleep.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/src/cmac_timer.c">hw/mcu/dialog/cmac/src/cmac_timer.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/src/hal_os_tick.c">hw/mcu/dialog/cmac/src/hal_os_tick.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/src/hal_system.c">hw/mcu/dialog/cmac/src/hal_system.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/src/hal_timer.c">hw/mcu/dialog/cmac/src/hal_timer.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/src/hal_watchdog.c">hw/mcu/dialog/cmac/src/hal_watchdog.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/src/system_cmac.c">hw/mcu/dialog/cmac/src/system_cmac.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/cmac_sleep.S">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/cmac_sleep.S</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_arm.c">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_arm.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_cmac.c">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_cmac.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_fault.c">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_fault.c</a> |
| ????? | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/include/CMAC.h">hw/mcu/dialog/include/CMAC.h</a> |
| ????? | <a href="https://github.com/apache/mynewt-core/blob/151ead6cd446181ffb1a0ac2d77f2db796a0f145/hw/mcu/dialog/include/system_CMAC.h">hw/mcu/dialog/include/system_CMAC.h</a> |
</details>
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot removed a comment on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-686441666
<!-- license-bot -->
## RAT Report (2020-09-03 12:01:29)
## New files with unknown licenses
* <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/cmac.ld">hw/mcu/dialog/cmac/cmac.ld</a>
* <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/include/CMAC.h">hw/mcu/dialog/include/CMAC.h</a>
* <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/include/system_CMAC.h">hw/mcu/dialog/include/system_CMAC.h</a>
## 43 new files were excluded from check (.rat-excludes)
<details>
<summary>Detailed analysis</summary>
## New files in this PR
| License | File |
|---------|------|
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/bsp.yml">hw/bsp/dialog_cmac/bsp.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/cmac.ld">hw/bsp/dialog_cmac/cmac.ld</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/dialog_cmac_debug.sh">hw/bsp/dialog_cmac/dialog_cmac_debug.sh</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/dialog_cmac_download.sh">hw/bsp/dialog_cmac/dialog_cmac_download.sh</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/pkg.yml">hw/bsp/dialog_cmac/pkg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/syscfg.yml">hw/bsp/dialog_cmac/syscfg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/include/bsp/bsp.h">hw/bsp/dialog_cmac/include/bsp/bsp.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/src/hal_bsp.c">hw/bsp/dialog_cmac/src/hal_bsp.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/src/sbrk.c">hw/bsp/dialog_cmac/src/sbrk.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/src/arch/cortex_m0_cmac/gcc_startup_cmac.S">hw/bsp/dialog_cmac/src/arch/cortex_m0_cmac/gcc_startup_cmac.S</a> |
| ????? | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/cmac.ld">hw/mcu/dialog/cmac/cmac.ld</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/pkg.yml">hw/mcu/dialog/cmac/pkg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/syscfg.yml">hw/mcu/dialog/cmac/syscfg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch.h">hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch_cmac.h">hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch_cmac.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/cmac_hal.h">hw/mcu/dialog/cmac/include/mcu/cmac_hal.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/cmac_pdc.h">hw/mcu/dialog/cmac/include/mcu/cmac_pdc.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/cmac_periph.h">hw/mcu/dialog/cmac/include/mcu/cmac_periph.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/cmac_timer.h">hw/mcu/dialog/cmac/include/mcu/cmac_timer.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/cortex_m0.h">hw/mcu/dialog/cmac/include/mcu/cortex_m0.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/mcu.h">hw/mcu/dialog/cmac/include/mcu/mcu.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/cmac_isr.c">hw/mcu/dialog/cmac/src/cmac_isr.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/cmac_periph.c">hw/mcu/dialog/cmac/src/cmac_periph.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/cmac_priv.h">hw/mcu/dialog/cmac/src/cmac_priv.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/cmac_sleep.c">hw/mcu/dialog/cmac/src/cmac_sleep.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/cmac_timer.c">hw/mcu/dialog/cmac/src/cmac_timer.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/hal_os_tick.c">hw/mcu/dialog/cmac/src/hal_os_tick.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/hal_system.c">hw/mcu/dialog/cmac/src/hal_system.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/hal_timer.c">hw/mcu/dialog/cmac/src/hal_timer.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/hal_watchdog.c">hw/mcu/dialog/cmac/src/hal_watchdog.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/system_cmac.c">hw/mcu/dialog/cmac/src/system_cmac.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/cmac_sleep.S">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/cmac_sleep.S</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_arm.c">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_arm.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_cmac.c">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_cmac.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_fault.c">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_fault.c</a> |
| ????? | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/include/CMAC.h">hw/mcu/dialog/include/CMAC.h</a> |
| ????? | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/include/system_CMAC.h">hw/mcu/dialog/include/system_CMAC.h</a> |
</details>
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot commented on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-686441790
<!-- style-bot -->
## Style check summary
### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
#### hw/bsp/dialog_cmac/include/bsp/bsp.h
<details>
```diff
@@ -26,17 +26,19 @@
extern "C" {
#endif
-///* Define special stackos sections */
-//#define sec_data_core __attribute__((section(".data.core")))
-//#define sec_bss_core __attribute__((section(".bss.core")))
-//#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
-//
-///* More convenient section placement macros. */
-//#define bssnz_t sec_bss_nz_core
-//
-//extern uint8_t _ram_start;
-//#define RAM_SIZE 0x80000
-//
+/*
+ / * Define special stackos sections * /
+ #define sec_data_core __attribute__((section(".data.core")))
+ #define sec_bss_core __attribute__((section(".bss.core")))
+ #define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+ / * More convenient section placement macros. * /
+ #define bssnz_t sec_bss_nz_core
+
+ extern uint8_t _ram_start;
+ #define RAM_SIZE 0x80000
+
+ */
#define LED_BLINK_PIN 0
```
</details>
#### hw/bsp/dialog_cmac/src/sbrk.c
<details>
```diff
@@ -23,7 +23,8 @@
static char *brk __attribute__ ((section (".data")));
void
-_sbrkInit(char *base, char *limit) {
+_sbrkInit(char *base, char *limit)
+{
sbrkBase = base;
sbrkLimit = limit;
brk = base;
```
</details>
#### hw/mcu/dialog/cmac/include/mcu/mcu.h
<details>
```diff
@@ -35,11 +35,13 @@
#define MCU_DIAG_MAP(_port, _word, _evt) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos);
+ (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos);
#define MCU_DIAG_MAP_BIT(_port, _word, _evt, _bit) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos);
+ ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos);
/* Output diagnostic setial message */
#ifndef MCU_DIAG_SER_DISABLE
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_sleep.c
<details>
```diff
@@ -119,10 +119,10 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory"
- );
+ );
}
static void
@@ -136,10 +136,10 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory"
- );
+ );
}
static void
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_timer.c
<details>
```diff
@@ -37,8 +37,8 @@
#define SYNC_TICK_TICKS_PER_VAL_INTERVAL ((SYNC_TICK_VAL_INTERVAL) / 1000000 * 128)
#define COMP_TICK_HAS_PASSED(_num) \
- (CMAC->CM_EV_LATCHED_REG & \
- (CMAC_CM_EV_LATCHED_REG_EV1C_CLK_1US_X1_Msk << ((_num) - 1)))
+ (CMAC->CM_EV_LATCHED_REG & \
+ (CMAC_CM_EV_LATCHED_REG_EV1C_CLK_1US_X1_Msk << ((_num) - 1)))
struct cmac_timer_slp {
uint32_t freq;
@@ -87,7 +87,7 @@
__WFE();
__WFE();
- CMAC->CM_CTRL2_REG = reg;
+ CMAC->CM_CTRL2_REG = reg;
}
static inline void
@@ -102,7 +102,7 @@
__WFE();
__WFE();
- CMAC->CM_CTRL2_REG = reg;
+ CMAC->CM_CTRL2_REG = reg;
}
static void
@@ -186,7 +186,8 @@
slept_ns_rem = slept_ns % 1000;
- clk_freq_mhz_d2m1 = (CMAC->CM_CTRL_REG & CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Msk) >> CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Pos;
+ clk_freq_mhz_d2m1 = (CMAC->CM_CTRL_REG & CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Msk) >>
+ CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Pos;
clk_freq_mhz = 2 * (clk_freq_mhz_d2m1 + 1);
comp_timer = slept_ns_rem * clk_freq_mhz / 1000;
@@ -222,10 +223,10 @@
* Compiler barrier to make sure calculations are already done prior to
* this line since code below has strict time constraints.
*/
- asm volatile(""
- :
- :"r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
- : "memory");
+ asm volatile (""
+ :
+ : "r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
+ : "memory");
/*
* Normally we should only wait for next 1MHz tick but since prior to
@@ -438,11 +439,13 @@
#endif
/* XXX uncomment if any of these comparators are used */
-// if (mask & (CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_0_SEL_Msk |
-// CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_X_SEL_Msk |
-// CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_Y_SEL_Msk)) {
-// return 0;
-// }
+/*
+ if (mask & (CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_0_SEL_Msk |
+ CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_X_SEL_Msk |
+ CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_Y_SEL_Msk)) {
+ return 0;
+ }
+ */
val32 = cmac_timer_read32();
```
</details>
#### hw/mcu/dialog/cmac/src/hal_os_tick.c
<details>
```diff
@@ -41,7 +41,7 @@
next = g_os_tick_last + delta;
if (g_os_tick_next == next) {
/* Don't waste time calculating the same llt_val again */
- llt_val = g_os_tick_next_val ;
+ llt_val = g_os_tick_next_val;
} else {
/* Round up to next high part ll_timer value */
llt_val = cmac_timer_convert_tck2llt(next);
```
</details>
#### hw/mcu/dialog/cmac/src/hal_system.c
<details>
```diff
@@ -37,12 +37,14 @@
__disable_irq();
if (hal_debugger_connected()) {
- asm("bkpt");
+ asm ("bkpt");
}
CMAC->CM_EXC_STAT_REG = CMAC_CM_EXC_STAT_REG_EXC_FW_ERROR_Msk;
- for (;;);
+ for (;;) {
+ ;
+ }
}
int
```
</details>
#### hw/mcu/dialog/cmac/src/system_cmac.c
<details>
```diff
@@ -28,7 +28,8 @@
#include "cmac_driver/cmac_diag.h"
#include "CMAC.h"
-void SystemInit(void)
+void
+SystemInit(void)
{
#if MYNEWT_VAL(CMAC_DEBUG_DIAG_ENABLE)
cmac_diag_setup_cmac();
@@ -36,7 +37,9 @@
#if MYNEWT_VAL(MCU_DEBUG_SWD_WAIT_FOR_ATTACH)
while (!hal_debugger_connected());
- for (int i = 0; i < 1000000; i++);
+ for (int i = 0; i < 1000000; i++) {
+ ;
+ }
#endif
CMAC->CM_CTRL_REG &= ~CMAC_CM_CTRL_REG_CM_BS_RESET_N_Msk;
```
</details>
#### hw/mcu/dialog/include/CMAC.h
<details>
```diff
@@ -14,13 +14,13 @@
/** @addtogroup Dialog
- * @{
- */
+ * @{
+ */
/** @addtogroup D2763x
- * @{
- */
+ * @{
+ */
#ifndef D2763X_H
@@ -50,13 +50,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -70,8 +70,8 @@
#endif /*CMSIS_STRIP_HEADER*/
/** @addtogroup Device_Peripheral_peripherals
- * @{
- */
+ * @{
+ */
@@ -81,162 +81,162 @@
/**
- * @brief CMAC registers (CMAC)
- */
+ * @brief CMAC registers (CMAC)
+ */
typedef struct { /*!< (@ 0x40000000) CMAC Structure */
- __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
- __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
- __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
- __I uint32_t RESERVED;
- __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
- __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
- __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
- __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
- __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
- __I uint32_t RESERVED1[23];
- __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
- __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
- __I uint32_t RESERVED2[30];
- __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
- __I uint32_t RESERVED3[3];
- __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
- __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
- __I uint32_t RESERVED4[2];
- __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
- __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
- __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
- __I uint32_t RESERVED5[53];
- __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
- __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
- __I uint32_t RESERVED6[2];
- __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
- __I uint32_t RESERVED7[3];
- __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
- __I uint32_t RESERVED8[3];
- __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
- __I uint32_t RESERVED9[51];
- __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
- __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
- __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
- __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
- __I uint32_t RESERVED10[8];
- __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
- __I uint32_t RESERVED11[2];
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
- __I uint32_t RESERVED12[294];
- __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
- __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
- __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
- __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
- __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
- __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
- __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
- __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
- __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
- __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
- __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
- __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
- __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
- __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
- __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
- __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
- __I uint32_t RESERVED13[16];
- __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
- __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
- __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
- __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
- __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
- __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
- __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
- __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
- __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
- __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
- __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
- __I uint32_t RESERVED14[17];
- __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
- __I uint32_t RESERVED15[3];
- __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
- __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
- __I uint32_t RESERVED16[446];
- __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
- __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
- __I uint32_t RESERVED17[2];
- __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
- __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
- __I uint32_t RESERVED18[2];
- __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
- __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
- __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
- __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
- __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
- __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
- __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
- __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
- __I uint32_t RESERVED19[48];
- __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
- __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
- __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
- __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
- __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
- __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
- __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
- __I uint32_t RESERVED20[949];
- __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
- __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
- __I uint32_t RESERVED21[62];
- __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
- __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
- __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
- __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
+ __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
+ __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
+ __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
+ __I uint32_t RESERVED;
+ __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
+ __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
+ __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
+ __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
+ __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
+ __I uint32_t RESERVED1[23];
+ __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
+ __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
+ __I uint32_t RESERVED2[30];
+ __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
+ __I uint32_t RESERVED3[3];
+ __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
+ __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
+ __I uint32_t RESERVED4[2];
+ __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
+ __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
+ __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
+ __I uint32_t RESERVED5[53];
+ __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
+ __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
+ __I uint32_t RESERVED6[2];
+ __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
+ __I uint32_t RESERVED7[3];
+ __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
+ __I uint32_t RESERVED8[3];
+ __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
+ __I uint32_t RESERVED9[51];
+ __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
+ __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
+ __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
+ __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
+ __I uint32_t RESERVED10[8];
+ __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
+ __I uint32_t RESERVED11[2];
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
+ __I uint32_t RESERVED12[294];
+ __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
+ __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
+ __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
+ __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
+ __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
+ __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
+ __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
+ __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
+ __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
+ __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
+ __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
+ __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
+ __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
+ __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
+ __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
+ __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
+ __I uint32_t RESERVED13[16];
+ __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
+ __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
+ __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
+ __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
+ __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
+ __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
+ __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
+ __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
+ __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
+ __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
+ __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
+ __I uint32_t RESERVED14[17];
+ __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
+ __I uint32_t RESERVED15[3];
+ __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
+ __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
+ __I uint32_t RESERVED16[446];
+ __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
+ __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
+ __I uint32_t RESERVED17[2];
+ __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
+ __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
+ __I uint32_t RESERVED18[2];
+ __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
+ __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
+ __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
+ __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
+ __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
+ __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
+ __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
+ __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
+ __I uint32_t RESERVED19[48];
+ __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
+ __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
+ __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
+ __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
+ __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
+ __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
+ __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
+ __I uint32_t RESERVED20[949];
+ __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
+ __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
+ __I uint32_t RESERVED21[62];
+ __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
+ __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
+ __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
+ __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
} CMAC_Type; /*!< Size = 4396 (0x112c) */
typedef struct { /*!< (@ 0x50010400) CMAC_TIMER_SLP Structure */
- __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
- __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
- __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
+ __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
+ __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
+ __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
} CMAC_TIMER_SLP_Type;
typedef struct { /*!< (@ 0x50000200) PDC Structure */
- __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
- __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
- __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
- __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
- __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
- __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
- __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
- __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
- __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
- __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
- __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
- __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
- __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
- __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
- __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
- __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
- __IM uint32_t RESERVED[16];
- __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
- __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
- __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
- __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
+ __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
+ __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
+ __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
+ __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
+ __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
+ __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
+ __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
+ __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
+ __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
+ __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
+ __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
+ __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
+ __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
+ __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
+ __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
+ __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
+ __IM uint32_t RESERVED[16];
+ __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
+ __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
+ __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
+ __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
} PDC_Type; /*!< Size = 152 (0x98) */
@@ -249,8 +249,8 @@
/** @addtogroup Device_Peripheral_peripheralAddr
- * @{
- */
+ * @{
+ */
#define CMAC_BASE 0x40000000UL
#define CMAC_TIMER_SLP_BASE 0x50010400UL
@@ -265,12 +265,12 @@
/** @addtogroup Device_Peripheral_declaration
- * @{
- */
-
-#define CMAC ((CMAC_Type*) CMAC_BASE)
+ * @{
+ */
+
+#define CMAC ((CMAC_Type *) CMAC_BASE)
#define CMAC_TIMER_SLP ((CMAC_TIMER_SLP_Type *) CMAC_TIMER_SLP_BASE)
-#define PDC ((PDC_Type*) PDC_BASE)
+#define PDC ((PDC_Type *) PDC_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
@@ -279,17 +279,17 @@
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
- /* leave anonymous unions enabled */
+/* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#endif
@@ -299,8 +299,8 @@
/** @addtogroup PosMask_peripherals
- * @{
- */
+ * @{
+ */
```
</details>
#### hw/mcu/dialog/include/system_CMAC.h
<details>
```diff
@@ -7,7 +7,7 @@
#ifndef _SYSTEM_D2763_INCLUDED
#define _SYSTEM_D2763_INCLUDED
-// From datasheet.h:
+/* From datasheet.h: */
/*--GPIO PID functions-------------------------------------------------------------------------*/
#define FUNC_GPIO (0)
@@ -77,73 +77,73 @@
#define DIR_PULLDOWN 0x200
#define DIR_OUTPUT 0x300
-// code copied from global_functions.h
+/* code copied from global_functions.h */
#if defined(CORTEX_M33)
typedef enum {
/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */
- Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
- BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
- UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
- SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
- PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
- SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* ========================================== DA1469x Specific Interrupt Numbers =========================================== */
- SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
- DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
- CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
- CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
- CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
- UART_IRQn = 5, /*!< 5 UART interrupt request. */
- UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
- UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
- I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
- I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
- SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
- SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
- RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
- RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
- RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
- USB_IRQn = 15, /*!< 15 USB interrupt request. */
- TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
- TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
- RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
- KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
- PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
- VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
- MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
- DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
- TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
- DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
- XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
- GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
- SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
- CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
- CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
- RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
- RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
- PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
- TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
- TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
- LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
- RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
- GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
- GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
- SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
- RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
- RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
- RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
- RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
- RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
- RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
- RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
+ SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
+ DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
+ CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
+ CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
+ CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
+ UART_IRQn = 5, /*!< 5 UART interrupt request. */
+ UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
+ UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
+ I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
+ I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
+ SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
+ SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
+ RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
+ RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
+ RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
+ USB_IRQn = 15, /*!< 15 USB interrupt request. */
+ TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
+ TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
+ RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
+ KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
+ PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
+ VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
+ MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
+ DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
+ TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
+ DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
+ XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
+ GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
+ SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
+ CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
+ CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
+ RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
+ RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
+ PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
+ TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
+ TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
+ LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
+ RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
+ GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
+ GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
+ SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
+ RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
+ RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
+ RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
+ RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
+ RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
+ RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
+ RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
} IRQn_Type;
@@ -163,45 +163,47 @@
#include "cmsis_mtb.h"
#endif
-#else // if defined(CORTEX_M0PLUS)
+#else /* if defined(CORTEX_M0PLUS) */
typedef enum IRQn {
/****** Cortex-M0 Processor Exceptions Numbers *****************************************/
-NMI_IRQn = -14, /* 2 Non Maskable Interrupt. */
-HardFault_IRQn = -13, /* 3 Cortex-M0 Hard Fault Interrupt. */
-SVCall_IRQn = -5, /* 11 Cortex-M0 SV Call Interrupt. */
-PendSV_IRQn = -2, /* 14 Cortex-M0 Pend SV Interrupt. */
-SysTick_IRQn = -1, /* 15 Cortex-M0 System Tick Interrupt. */
+ NMI_IRQn = -14,/* 2 Non Maskable Interrupt. */
+ HardFault_IRQn = -13,/* 3 Cortex-M0 Hard Fault Interrupt. */
+ SVCall_IRQn = -5,/* 11 Cortex-M0 SV Call Interrupt. */
+ PendSV_IRQn = -2,/* 14 Cortex-M0 Pend SV Interrupt. */
+ SysTick_IRQn = -1,/* 15 Cortex-M0 System Tick Interrupt. */
/****** CMAC CM0P Specific Interrupt Numbers *******************************************/
-FIELD_IRQn = 0,
-CALLBACK_IRQn = 1,
-FRAME_IRQn = 2,
-DIAG_IRQn = 3,
-HW_GEN_IRQn = 4,
-SW_MAC_IRQn = 5,
-LL_TIMER2PRMTV_IRQn = 6,
-LL_TIMER2LLC_IRQn = 7,
-CRYPTO_IRQn = 8,
-SW_LLC_1_IRQn = 9,
-SW_LLC_2_IRQn = 10,
-SW_LLC_3_IRQn = 11,
-SYS2CMAC_IRQn = 12
+ FIELD_IRQn = 0,
+ CALLBACK_IRQn = 1,
+ FRAME_IRQn = 2,
+ DIAG_IRQn = 3,
+ HW_GEN_IRQn = 4,
+ SW_MAC_IRQn = 5,
+ LL_TIMER2PRMTV_IRQn = 6,
+ LL_TIMER2LLC_IRQn = 7,
+ CRYPTO_IRQn = 8,
+ SW_LLC_1_IRQn = 9,
+ SW_LLC_2_IRQn = 10,
+ SW_LLC_3_IRQn = 11,
+ SYS2CMAC_IRQn = 12
} IRQn_Type;
/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
#define __CM0_REV 0x0000 /*!< Core Revision r2p1 */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-//#define __MPU_PRESENT 1 /*!< MPU present or not */
-//#define __VTOR_PRESENT 1 /*!< Cortex-M0+ can support the VTOR */
+/*
+ #define __MPU_PRESENT 1 / *!< MPU present or not * /
+ #define __VTOR_PRESENT 1 / *!< Cortex-M0+ can support the VTOR * /
+ */
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
-//#include "system_CMSDK_CM0plus.h" /* CMSDK_CM0plus System include file */
-
-
-#endif // if defined(CORTEX_M0PLUS)
-
-// non-core specific code:
+/*#include "system_CMSDK_CM0plus.h" / * CMSDK_CM0plus System include file * / */
+
+
+#endif /* if defined(CORTEX_M0PLUS) */
+
+/* non-core specific code: */
#ifndef __IM /*!< Fallback for older CMSIS versions */
#define __IM __I
@@ -227,13 +229,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -243,4 +245,4 @@
-#endif //_SYSTEM_D2763_INCLUDED
+#endif /*_SYSTEM_D2763_INCLUDED */
```
</details>
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot commented on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-694821227
<!-- style-bot -->
## Style check summary
### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
#### hw/bsp/dialog_cmac/include/bsp/bsp.h
<details>
```diff
@@ -26,17 +26,19 @@
extern "C" {
#endif
-///* Define special stackos sections */
-//#define sec_data_core __attribute__((section(".data.core")))
-//#define sec_bss_core __attribute__((section(".bss.core")))
-//#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
-//
-///* More convenient section placement macros. */
-//#define bssnz_t sec_bss_nz_core
-//
-//extern uint8_t _ram_start;
-//#define RAM_SIZE 0x80000
-//
+/*
+ / * Define special stackos sections * /
+ #define sec_data_core __attribute__((section(".data.core")))
+ #define sec_bss_core __attribute__((section(".bss.core")))
+ #define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+ / * More convenient section placement macros. * /
+ #define bssnz_t sec_bss_nz_core
+
+ extern uint8_t _ram_start;
+ #define RAM_SIZE 0x80000
+
+ */
#define LED_BLINK_PIN 0
```
</details>
#### hw/bsp/dialog_cmac/src/sbrk.c
<details>
```diff
@@ -23,7 +23,8 @@
static char *brk __attribute__ ((section (".data")));
void
-_sbrkInit(char *base, char *limit) {
+_sbrkInit(char *base, char *limit)
+{
sbrkBase = base;
sbrkLimit = limit;
brk = base;
```
</details>
#### hw/mcu/dialog/cmac/include/mcu/mcu.h
<details>
```diff
@@ -35,11 +35,13 @@
#define MCU_DIAG_MAP(_port, _word, _evt) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
+ (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
#define MCU_DIAG_MAP_BIT(_port, _word, _evt, _bit) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
+ ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
/* Output diagnostic setial message */
#ifndef MCU_DIAG_SER_DISABLE
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_sleep.c
<details>
```diff
@@ -119,10 +119,10 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory"
- );
+ );
}
static void
@@ -136,10 +136,10 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory"
- );
+ );
}
static void
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_timer.c
<details>
```diff
@@ -37,8 +37,8 @@
#define SYNC_TICK_TICKS_PER_VAL_INTERVAL ((SYNC_TICK_VAL_INTERVAL) / 1000000 * 128)
#define COMP_TICK_HAS_PASSED(_num) \
- (CMAC->CM_EV_LATCHED_REG & \
- (CMAC_CM_EV_LATCHED_REG_EV1C_CLK_1US_X1_Msk << ((_num) - 1)))
+ (CMAC->CM_EV_LATCHED_REG & \
+ (CMAC_CM_EV_LATCHED_REG_EV1C_CLK_1US_X1_Msk << ((_num) - 1)))
struct cmac_timer_slp {
uint32_t freq;
@@ -87,7 +87,7 @@
__WFE();
__WFE();
- CMAC->CM_CTRL2_REG = reg;
+ CMAC->CM_CTRL2_REG = reg;
}
static inline void
@@ -102,7 +102,7 @@
__WFE();
__WFE();
- CMAC->CM_CTRL2_REG = reg;
+ CMAC->CM_CTRL2_REG = reg;
}
static void
@@ -186,7 +186,8 @@
slept_ns_rem = slept_ns % 1000;
- clk_freq_mhz_d2m1 = (CMAC->CM_CTRL_REG & CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Msk) >> CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Pos;
+ clk_freq_mhz_d2m1 = (CMAC->CM_CTRL_REG & CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Msk) >>
+ CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Pos;
clk_freq_mhz = 2 * (clk_freq_mhz_d2m1 + 1);
comp_timer = slept_ns_rem * clk_freq_mhz / 1000;
@@ -222,10 +223,10 @@
* Compiler barrier to make sure calculations are already done prior to
* this line since code below has strict time constraints.
*/
- asm volatile(""
- :
- :"r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
- : "memory");
+ asm volatile (""
+ :
+ : "r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
+ : "memory");
/*
* Normally we should only wait for next 1MHz tick but since prior to
@@ -438,11 +439,13 @@
#endif
/* XXX uncomment if any of these comparators are used */
-// if (mask & (CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_0_SEL_Msk |
-// CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_X_SEL_Msk |
-// CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_Y_SEL_Msk)) {
-// return 0;
-// }
+/*
+ if (mask & (CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_0_SEL_Msk |
+ CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_X_SEL_Msk |
+ CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_Y_SEL_Msk)) {
+ return 0;
+ }
+ */
val32 = cmac_timer_read32();
```
</details>
#### hw/mcu/dialog/cmac/src/hal_os_tick.c
<details>
```diff
@@ -41,7 +41,7 @@
next = g_os_tick_last + delta;
if (g_os_tick_next == next) {
/* Don't waste time calculating the same llt_val again */
- llt_val = g_os_tick_next_val ;
+ llt_val = g_os_tick_next_val;
} else {
/* Round up to next high part ll_timer value */
llt_val = cmac_timer_convert_tck2llt(next);
```
</details>
#### hw/mcu/dialog/cmac/src/hal_system.c
<details>
```diff
@@ -37,12 +37,14 @@
__disable_irq();
if (hal_debugger_connected()) {
- asm("bkpt");
+ asm ("bkpt");
}
CMAC->CM_EXC_STAT_REG = CMAC_CM_EXC_STAT_REG_EXC_FW_ERROR_Msk;
- for (;;);
+ for (;;) {
+ ;
+ }
}
int
```
</details>
#### hw/mcu/dialog/cmac/src/system_cmac.c
<details>
```diff
@@ -28,7 +28,8 @@
#include "cmac_driver/cmac_diag.h"
#include "CMAC.h"
-void SystemInit(void)
+void
+SystemInit(void)
{
#if MYNEWT_VAL(CMAC_DEBUG_DIAG_ENABLE)
cmac_diag_setup_cmac();
@@ -36,7 +37,9 @@
#if MYNEWT_VAL(MCU_DEBUG_SWD_WAIT_FOR_ATTACH)
while (!hal_debugger_connected());
- for (int i = 0; i < 1000000; i++);
+ for (int i = 0; i < 1000000; i++) {
+ ;
+ }
#endif
CMAC->CM_CTRL_REG &= ~CMAC_CM_CTRL_REG_CM_BS_RESET_N_Msk;
```
</details>
#### hw/mcu/dialog/include/CMAC.h
<details>
```diff
@@ -35,13 +35,13 @@
/** @addtogroup Dialog
- * @{
- */
+ * @{
+ */
/** @addtogroup D2763x
- * @{
- */
+ * @{
+ */
#ifndef D2763X_H
@@ -71,13 +71,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -91,8 +91,8 @@
#endif /*CMSIS_STRIP_HEADER*/
/** @addtogroup Device_Peripheral_peripherals
- * @{
- */
+ * @{
+ */
@@ -102,162 +102,162 @@
/**
- * @brief CMAC registers (CMAC)
- */
+ * @brief CMAC registers (CMAC)
+ */
typedef struct { /*!< (@ 0x40000000) CMAC Structure */
- __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
- __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
- __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
- __I uint32_t RESERVED;
- __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
- __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
- __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
- __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
- __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
- __I uint32_t RESERVED1[23];
- __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
- __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
- __I uint32_t RESERVED2[30];
- __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
- __I uint32_t RESERVED3[3];
- __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
- __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
- __I uint32_t RESERVED4[2];
- __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
- __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
- __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
- __I uint32_t RESERVED5[53];
- __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
- __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
- __I uint32_t RESERVED6[2];
- __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
- __I uint32_t RESERVED7[3];
- __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
- __I uint32_t RESERVED8[3];
- __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
- __I uint32_t RESERVED9[51];
- __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
- __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
- __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
- __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
- __I uint32_t RESERVED10[8];
- __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
- __I uint32_t RESERVED11[2];
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
- __I uint32_t RESERVED12[294];
- __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
- __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
- __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
- __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
- __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
- __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
- __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
- __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
- __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
- __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
- __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
- __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
- __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
- __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
- __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
- __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
- __I uint32_t RESERVED13[16];
- __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
- __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
- __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
- __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
- __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
- __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
- __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
- __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
- __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
- __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
- __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
- __I uint32_t RESERVED14[17];
- __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
- __I uint32_t RESERVED15[3];
- __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
- __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
- __I uint32_t RESERVED16[446];
- __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
- __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
- __I uint32_t RESERVED17[2];
- __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
- __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
- __I uint32_t RESERVED18[2];
- __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
- __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
- __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
- __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
- __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
- __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
- __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
- __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
- __I uint32_t RESERVED19[48];
- __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
- __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
- __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
- __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
- __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
- __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
- __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
- __I uint32_t RESERVED20[949];
- __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
- __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
- __I uint32_t RESERVED21[62];
- __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
- __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
- __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
- __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
+ __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
+ __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
+ __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
+ __I uint32_t RESERVED;
+ __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
+ __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
+ __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
+ __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
+ __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
+ __I uint32_t RESERVED1[23];
+ __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
+ __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
+ __I uint32_t RESERVED2[30];
+ __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
+ __I uint32_t RESERVED3[3];
+ __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
+ __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
+ __I uint32_t RESERVED4[2];
+ __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
+ __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
+ __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
+ __I uint32_t RESERVED5[53];
+ __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
+ __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
+ __I uint32_t RESERVED6[2];
+ __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
+ __I uint32_t RESERVED7[3];
+ __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
+ __I uint32_t RESERVED8[3];
+ __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
+ __I uint32_t RESERVED9[51];
+ __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
+ __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
+ __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
+ __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
+ __I uint32_t RESERVED10[8];
+ __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
+ __I uint32_t RESERVED11[2];
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
+ __I uint32_t RESERVED12[294];
+ __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
+ __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
+ __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
+ __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
+ __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
+ __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
+ __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
+ __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
+ __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
+ __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
+ __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
+ __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
+ __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
+ __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
+ __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
+ __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
+ __I uint32_t RESERVED13[16];
+ __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
+ __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
+ __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
+ __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
+ __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
+ __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
+ __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
+ __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
+ __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
+ __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
+ __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
+ __I uint32_t RESERVED14[17];
+ __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
+ __I uint32_t RESERVED15[3];
+ __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
+ __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
+ __I uint32_t RESERVED16[446];
+ __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
+ __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
+ __I uint32_t RESERVED17[2];
+ __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
+ __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
+ __I uint32_t RESERVED18[2];
+ __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
+ __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
+ __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
+ __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
+ __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
+ __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
+ __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
+ __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
+ __I uint32_t RESERVED19[48];
+ __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
+ __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
+ __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
+ __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
+ __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
+ __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
+ __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
+ __I uint32_t RESERVED20[949];
+ __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
+ __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
+ __I uint32_t RESERVED21[62];
+ __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
+ __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
+ __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
+ __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
} CMAC_Type; /*!< Size = 4396 (0x112c) */
typedef struct { /*!< (@ 0x50010400) CMAC_TIMER_SLP Structure */
- __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
- __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
- __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
+ __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
+ __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
+ __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
} CMAC_TIMER_SLP_Type;
typedef struct { /*!< (@ 0x50000200) PDC Structure */
- __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
- __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
- __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
- __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
- __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
- __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
- __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
- __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
- __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
- __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
- __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
- __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
- __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
- __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
- __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
- __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
- __IM uint32_t RESERVED[16];
- __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
- __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
- __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
- __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
+ __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
+ __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
+ __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
+ __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
+ __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
+ __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
+ __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
+ __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
+ __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
+ __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
+ __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
+ __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
+ __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
+ __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
+ __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
+ __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
+ __IM uint32_t RESERVED[16];
+ __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
+ __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
+ __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
+ __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
} PDC_Type; /*!< Size = 152 (0x98) */
@@ -270,8 +270,8 @@
/** @addtogroup Device_Peripheral_peripheralAddr
- * @{
- */
+ * @{
+ */
#define CMAC_BASE 0x40000000UL
#define CMAC_TIMER_SLP_BASE 0x50010400UL
@@ -286,12 +286,12 @@
/** @addtogroup Device_Peripheral_declaration
- * @{
- */
-
-#define CMAC ((CMAC_Type*) CMAC_BASE)
+ * @{
+ */
+
+#define CMAC ((CMAC_Type *) CMAC_BASE)
#define CMAC_TIMER_SLP ((CMAC_TIMER_SLP_Type *) CMAC_TIMER_SLP_BASE)
-#define PDC ((PDC_Type*) PDC_BASE)
+#define PDC ((PDC_Type *) PDC_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
@@ -300,17 +300,17 @@
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
- /* leave anonymous unions enabled */
+/* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#endif
@@ -320,8 +320,8 @@
/** @addtogroup PosMask_peripherals
- * @{
- */
+ * @{
+ */
```
</details>
#### hw/mcu/dialog/include/system_CMAC.h
<details>
```diff
@@ -28,7 +28,7 @@
#ifndef _SYSTEM_D2763_INCLUDED
#define _SYSTEM_D2763_INCLUDED
-// From datasheet.h:
+/* From datasheet.h: */
/*--GPIO PID functions-------------------------------------------------------------------------*/
#define FUNC_GPIO (0)
@@ -98,73 +98,73 @@
#define DIR_PULLDOWN 0x200
#define DIR_OUTPUT 0x300
-// code copied from global_functions.h
+/* code copied from global_functions.h */
#if defined(CORTEX_M33)
typedef enum {
/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */
- Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
- BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
- UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
- SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
- PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
- SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* ========================================== DA1469x Specific Interrupt Numbers =========================================== */
- SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
- DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
- CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
- CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
- CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
- UART_IRQn = 5, /*!< 5 UART interrupt request. */
- UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
- UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
- I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
- I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
- SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
- SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
- RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
- RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
- RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
- USB_IRQn = 15, /*!< 15 USB interrupt request. */
- TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
- TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
- RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
- KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
- PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
- VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
- MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
- DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
- TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
- DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
- XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
- GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
- SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
- CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
- CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
- RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
- RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
- PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
- TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
- TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
- LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
- RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
- GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
- GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
- SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
- RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
- RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
- RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
- RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
- RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
- RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
- RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
+ SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
+ DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
+ CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
+ CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
+ CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
+ UART_IRQn = 5, /*!< 5 UART interrupt request. */
+ UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
+ UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
+ I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
+ I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
+ SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
+ SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
+ RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
+ RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
+ RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
+ USB_IRQn = 15, /*!< 15 USB interrupt request. */
+ TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
+ TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
+ RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
+ KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
+ PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
+ VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
+ MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
+ DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
+ TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
+ DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
+ XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
+ GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
+ SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
+ CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
+ CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
+ RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
+ RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
+ PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
+ TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
+ TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
+ LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
+ RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
+ GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
+ GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
+ SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
+ RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
+ RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
+ RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
+ RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
+ RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
+ RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
+ RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
} IRQn_Type;
@@ -184,45 +184,47 @@
#include "cmsis_mtb.h"
#endif
-#else // if defined(CORTEX_M0PLUS)
+#else /* if defined(CORTEX_M0PLUS) */
typedef enum IRQn {
/****** Cortex-M0 Processor Exceptions Numbers *****************************************/
-NMI_IRQn = -14, /* 2 Non Maskable Interrupt. */
-HardFault_IRQn = -13, /* 3 Cortex-M0 Hard Fault Interrupt. */
-SVCall_IRQn = -5, /* 11 Cortex-M0 SV Call Interrupt. */
-PendSV_IRQn = -2, /* 14 Cortex-M0 Pend SV Interrupt. */
-SysTick_IRQn = -1, /* 15 Cortex-M0 System Tick Interrupt. */
+ NMI_IRQn = -14,/* 2 Non Maskable Interrupt. */
+ HardFault_IRQn = -13,/* 3 Cortex-M0 Hard Fault Interrupt. */
+ SVCall_IRQn = -5,/* 11 Cortex-M0 SV Call Interrupt. */
+ PendSV_IRQn = -2,/* 14 Cortex-M0 Pend SV Interrupt. */
+ SysTick_IRQn = -1,/* 15 Cortex-M0 System Tick Interrupt. */
/****** CMAC CM0P Specific Interrupt Numbers *******************************************/
-FIELD_IRQn = 0,
-CALLBACK_IRQn = 1,
-FRAME_IRQn = 2,
-DIAG_IRQn = 3,
-HW_GEN_IRQn = 4,
-SW_MAC_IRQn = 5,
-LL_TIMER2PRMTV_IRQn = 6,
-LL_TIMER2LLC_IRQn = 7,
-CRYPTO_IRQn = 8,
-SW_LLC_1_IRQn = 9,
-SW_LLC_2_IRQn = 10,
-SW_LLC_3_IRQn = 11,
-SYS2CMAC_IRQn = 12
+ FIELD_IRQn = 0,
+ CALLBACK_IRQn = 1,
+ FRAME_IRQn = 2,
+ DIAG_IRQn = 3,
+ HW_GEN_IRQn = 4,
+ SW_MAC_IRQn = 5,
+ LL_TIMER2PRMTV_IRQn = 6,
+ LL_TIMER2LLC_IRQn = 7,
+ CRYPTO_IRQn = 8,
+ SW_LLC_1_IRQn = 9,
+ SW_LLC_2_IRQn = 10,
+ SW_LLC_3_IRQn = 11,
+ SYS2CMAC_IRQn = 12
} IRQn_Type;
/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
#define __CM0_REV 0x0000 /*!< Core Revision r2p1 */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-//#define __MPU_PRESENT 1 /*!< MPU present or not */
-//#define __VTOR_PRESENT 1 /*!< Cortex-M0+ can support the VTOR */
+/*
+ #define __MPU_PRESENT 1 / *!< MPU present or not * /
+ #define __VTOR_PRESENT 1 / *!< Cortex-M0+ can support the VTOR * /
+ */
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
-//#include "system_CMSDK_CM0plus.h" /* CMSDK_CM0plus System include file */
-
-
-#endif // if defined(CORTEX_M0PLUS)
-
-// non-core specific code:
+/*#include "system_CMSDK_CM0plus.h" / * CMSDK_CM0plus System include file * / */
+
+
+#endif /* if defined(CORTEX_M0PLUS) */
+
+/* non-core specific code: */
#ifndef __IM /*!< Fallback for older CMSIS versions */
#define __IM __I
@@ -248,13 +250,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -264,4 +266,4 @@
-#endif //_SYSTEM_D2763_INCLUDED
+#endif /*_SYSTEM_D2763_INCLUDED */
```
</details>
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] andrzej-kaczmarek merged pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
andrzej-kaczmarek merged pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot commented on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-695964529
<!-- style-bot -->
## Style check summary
### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
#### hw/mcu/dialog/cmac/include/mcu/mcu.h
<details>
```diff
@@ -35,11 +35,13 @@
#define MCU_DIAG_MAP(_port, _word, _evt) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
+ (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
#define MCU_DIAG_MAP_BIT(_port, _word, _evt, _bit) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
+ ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
/* Output diagnostic setial message */
#ifndef MCU_DIAG_SER_DISABLE
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_sleep.c
<details>
```diff
@@ -119,8 +119,8 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory");
}
@@ -135,8 +135,8 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory");
}
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_timer.c
<details>
```diff
@@ -224,10 +224,10 @@
* Compiler barrier to make sure calculations are already done prior to
* this line since code below has strict time constraints.
*/
- asm volatile(""
- :
- :"r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
- : "memory");
+ asm volatile (""
+ :
+ : "r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
+ : "memory");
/*
* Normally we should only wait for next 1MHz tick but since prior to
```
</details>
#### hw/mcu/dialog/cmac/src/hal_system.c
<details>
```diff
@@ -37,12 +37,14 @@
__disable_irq();
if (hal_debugger_connected()) {
- asm("bkpt");
+ asm ("bkpt");
}
CMAC->CM_EXC_STAT_REG = CMAC_CM_EXC_STAT_REG_EXC_FW_ERROR_Msk;
- for (;;);
+ for (;;) {
+ ;
+ }
}
int
```
</details>
#### hw/mcu/dialog/cmac/src/system_cmac.c
<details>
```diff
@@ -37,7 +37,9 @@
#if MYNEWT_VAL(MCU_DEBUG_SWD_WAIT_FOR_ATTACH)
while (!hal_debugger_connected());
- for (int i = 0; i < 1000000; i++);
+ for (int i = 0; i < 1000000; i++) {
+ ;
+ }
#endif
CMAC->CM_CTRL_REG &= ~CMAC_CM_CTRL_REG_CM_BS_RESET_N_Msk;
```
</details>
#### hw/mcu/dialog/include/CMAC.h
<details>
```diff
@@ -35,13 +35,13 @@
/** @addtogroup Dialog
- * @{
- */
+ * @{
+ */
/** @addtogroup D2763x
- * @{
- */
+ * @{
+ */
#ifndef D2763X_H
@@ -71,13 +71,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -91,8 +91,8 @@
#endif /*CMSIS_STRIP_HEADER*/
/** @addtogroup Device_Peripheral_peripherals
- * @{
- */
+ * @{
+ */
@@ -102,162 +102,162 @@
/**
- * @brief CMAC registers (CMAC)
- */
+ * @brief CMAC registers (CMAC)
+ */
typedef struct { /*!< (@ 0x40000000) CMAC Structure */
- __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
- __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
- __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
- __I uint32_t RESERVED;
- __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
- __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
- __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
- __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
- __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
- __I uint32_t RESERVED1[23];
- __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
- __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
- __I uint32_t RESERVED2[30];
- __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
- __I uint32_t RESERVED3[3];
- __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
- __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
- __I uint32_t RESERVED4[2];
- __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
- __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
- __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
- __I uint32_t RESERVED5[53];
- __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
- __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
- __I uint32_t RESERVED6[2];
- __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
- __I uint32_t RESERVED7[3];
- __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
- __I uint32_t RESERVED8[3];
- __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
- __I uint32_t RESERVED9[51];
- __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
- __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
- __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
- __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
- __I uint32_t RESERVED10[8];
- __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
- __I uint32_t RESERVED11[2];
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
- __I uint32_t RESERVED12[294];
- __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
- __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
- __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
- __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
- __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
- __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
- __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
- __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
- __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
- __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
- __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
- __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
- __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
- __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
- __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
- __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
- __I uint32_t RESERVED13[16];
- __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
- __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
- __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
- __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
- __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
- __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
- __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
- __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
- __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
- __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
- __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
- __I uint32_t RESERVED14[17];
- __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
- __I uint32_t RESERVED15[3];
- __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
- __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
- __I uint32_t RESERVED16[446];
- __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
- __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
- __I uint32_t RESERVED17[2];
- __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
- __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
- __I uint32_t RESERVED18[2];
- __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
- __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
- __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
- __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
- __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
- __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
- __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
- __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
- __I uint32_t RESERVED19[48];
- __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
- __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
- __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
- __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
- __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
- __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
- __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
- __I uint32_t RESERVED20[949];
- __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
- __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
- __I uint32_t RESERVED21[62];
- __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
- __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
- __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
- __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
+ __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
+ __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
+ __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
+ __I uint32_t RESERVED;
+ __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
+ __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
+ __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
+ __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
+ __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
+ __I uint32_t RESERVED1[23];
+ __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
+ __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
+ __I uint32_t RESERVED2[30];
+ __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
+ __I uint32_t RESERVED3[3];
+ __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
+ __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
+ __I uint32_t RESERVED4[2];
+ __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
+ __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
+ __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
+ __I uint32_t RESERVED5[53];
+ __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
+ __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
+ __I uint32_t RESERVED6[2];
+ __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
+ __I uint32_t RESERVED7[3];
+ __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
+ __I uint32_t RESERVED8[3];
+ __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
+ __I uint32_t RESERVED9[51];
+ __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
+ __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
+ __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
+ __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
+ __I uint32_t RESERVED10[8];
+ __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
+ __I uint32_t RESERVED11[2];
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
+ __I uint32_t RESERVED12[294];
+ __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
+ __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
+ __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
+ __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
+ __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
+ __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
+ __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
+ __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
+ __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
+ __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
+ __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
+ __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
+ __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
+ __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
+ __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
+ __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
+ __I uint32_t RESERVED13[16];
+ __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
+ __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
+ __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
+ __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
+ __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
+ __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
+ __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
+ __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
+ __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
+ __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
+ __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
+ __I uint32_t RESERVED14[17];
+ __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
+ __I uint32_t RESERVED15[3];
+ __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
+ __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
+ __I uint32_t RESERVED16[446];
+ __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
+ __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
+ __I uint32_t RESERVED17[2];
+ __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
+ __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
+ __I uint32_t RESERVED18[2];
+ __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
+ __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
+ __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
+ __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
+ __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
+ __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
+ __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
+ __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
+ __I uint32_t RESERVED19[48];
+ __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
+ __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
+ __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
+ __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
+ __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
+ __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
+ __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
+ __I uint32_t RESERVED20[949];
+ __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
+ __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
+ __I uint32_t RESERVED21[62];
+ __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
+ __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
+ __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
+ __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
} CMAC_Type; /*!< Size = 4396 (0x112c) */
typedef struct { /*!< (@ 0x50010400) CMAC_TIMER_SLP Structure */
- __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
- __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
- __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
+ __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
+ __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
+ __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
} CMAC_TIMER_SLP_Type;
typedef struct { /*!< (@ 0x50000200) PDC Structure */
- __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
- __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
- __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
- __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
- __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
- __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
- __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
- __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
- __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
- __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
- __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
- __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
- __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
- __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
- __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
- __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
- __IM uint32_t RESERVED[16];
- __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
- __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
- __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
- __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
+ __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
+ __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
+ __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
+ __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
+ __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
+ __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
+ __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
+ __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
+ __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
+ __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
+ __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
+ __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
+ __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
+ __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
+ __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
+ __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
+ __IM uint32_t RESERVED[16];
+ __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
+ __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
+ __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
+ __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
} PDC_Type; /*!< Size = 152 (0x98) */
@@ -270,8 +270,8 @@
/** @addtogroup Device_Peripheral_peripheralAddr
- * @{
- */
+ * @{
+ */
#define CMAC_BASE 0x40000000UL
#define CMAC_TIMER_SLP_BASE 0x50010400UL
@@ -286,12 +286,12 @@
/** @addtogroup Device_Peripheral_declaration
- * @{
- */
-
-#define CMAC ((CMAC_Type*) CMAC_BASE)
+ * @{
+ */
+
+#define CMAC ((CMAC_Type *) CMAC_BASE)
#define CMAC_TIMER_SLP ((CMAC_TIMER_SLP_Type *) CMAC_TIMER_SLP_BASE)
-#define PDC ((PDC_Type*) PDC_BASE)
+#define PDC ((PDC_Type *) PDC_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
@@ -300,17 +300,17 @@
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
- /* leave anonymous unions enabled */
+/* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#endif
@@ -320,8 +320,8 @@
/** @addtogroup PosMask_peripherals
- * @{
- */
+ * @{
+ */
```
</details>
#### hw/mcu/dialog/include/system_CMAC.h
<details>
```diff
@@ -28,7 +28,7 @@
#ifndef _SYSTEM_D2763_INCLUDED
#define _SYSTEM_D2763_INCLUDED
-// From datasheet.h:
+/* From datasheet.h: */
/*--GPIO PID functions-------------------------------------------------------------------------*/
#define FUNC_GPIO (0)
@@ -98,73 +98,73 @@
#define DIR_PULLDOWN 0x200
#define DIR_OUTPUT 0x300
-// code copied from global_functions.h
+/* code copied from global_functions.h */
#if defined(CORTEX_M33)
typedef enum {
/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */
- Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
- BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
- UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
- SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
- PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
- SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* ========================================== DA1469x Specific Interrupt Numbers =========================================== */
- SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
- DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
- CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
- CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
- CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
- UART_IRQn = 5, /*!< 5 UART interrupt request. */
- UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
- UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
- I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
- I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
- SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
- SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
- RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
- RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
- RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
- USB_IRQn = 15, /*!< 15 USB interrupt request. */
- TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
- TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
- RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
- KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
- PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
- VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
- MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
- DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
- TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
- DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
- XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
- GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
- SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
- CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
- CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
- RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
- RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
- PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
- TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
- TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
- LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
- RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
- GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
- GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
- SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
- RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
- RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
- RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
- RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
- RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
- RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
- RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
+ SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
+ DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
+ CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
+ CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
+ CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
+ UART_IRQn = 5, /*!< 5 UART interrupt request. */
+ UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
+ UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
+ I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
+ I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
+ SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
+ SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
+ RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
+ RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
+ RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
+ USB_IRQn = 15, /*!< 15 USB interrupt request. */
+ TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
+ TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
+ RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
+ KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
+ PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
+ VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
+ MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
+ DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
+ TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
+ DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
+ XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
+ GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
+ SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
+ CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
+ CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
+ RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
+ RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
+ PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
+ TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
+ TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
+ LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
+ RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
+ GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
+ GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
+ SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
+ RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
+ RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
+ RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
+ RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
+ RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
+ RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
+ RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
} IRQn_Type;
@@ -184,45 +184,47 @@
#include "cmsis_mtb.h"
#endif
-#else // if defined(CORTEX_M0PLUS)
+#else /* if defined(CORTEX_M0PLUS) */
typedef enum IRQn {
/****** Cortex-M0 Processor Exceptions Numbers *****************************************/
-NMI_IRQn = -14, /* 2 Non Maskable Interrupt. */
-HardFault_IRQn = -13, /* 3 Cortex-M0 Hard Fault Interrupt. */
-SVCall_IRQn = -5, /* 11 Cortex-M0 SV Call Interrupt. */
-PendSV_IRQn = -2, /* 14 Cortex-M0 Pend SV Interrupt. */
-SysTick_IRQn = -1, /* 15 Cortex-M0 System Tick Interrupt. */
+ NMI_IRQn = -14,/* 2 Non Maskable Interrupt. */
+ HardFault_IRQn = -13,/* 3 Cortex-M0 Hard Fault Interrupt. */
+ SVCall_IRQn = -5,/* 11 Cortex-M0 SV Call Interrupt. */
+ PendSV_IRQn = -2,/* 14 Cortex-M0 Pend SV Interrupt. */
+ SysTick_IRQn = -1,/* 15 Cortex-M0 System Tick Interrupt. */
/****** CMAC CM0P Specific Interrupt Numbers *******************************************/
-FIELD_IRQn = 0,
-CALLBACK_IRQn = 1,
-FRAME_IRQn = 2,
-DIAG_IRQn = 3,
-HW_GEN_IRQn = 4,
-SW_MAC_IRQn = 5,
-LL_TIMER2PRMTV_IRQn = 6,
-LL_TIMER2LLC_IRQn = 7,
-CRYPTO_IRQn = 8,
-SW_LLC_1_IRQn = 9,
-SW_LLC_2_IRQn = 10,
-SW_LLC_3_IRQn = 11,
-SYS2CMAC_IRQn = 12
+ FIELD_IRQn = 0,
+ CALLBACK_IRQn = 1,
+ FRAME_IRQn = 2,
+ DIAG_IRQn = 3,
+ HW_GEN_IRQn = 4,
+ SW_MAC_IRQn = 5,
+ LL_TIMER2PRMTV_IRQn = 6,
+ LL_TIMER2LLC_IRQn = 7,
+ CRYPTO_IRQn = 8,
+ SW_LLC_1_IRQn = 9,
+ SW_LLC_2_IRQn = 10,
+ SW_LLC_3_IRQn = 11,
+ SYS2CMAC_IRQn = 12
} IRQn_Type;
/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
#define __CM0_REV 0x0000 /*!< Core Revision r2p1 */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-//#define __MPU_PRESENT 1 /*!< MPU present or not */
-//#define __VTOR_PRESENT 1 /*!< Cortex-M0+ can support the VTOR */
+/*
+ #define __MPU_PRESENT 1 / *!< MPU present or not * /
+ #define __VTOR_PRESENT 1 / *!< Cortex-M0+ can support the VTOR * /
+ */
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
-//#include "system_CMSDK_CM0plus.h" /* CMSDK_CM0plus System include file */
-
-
-#endif // if defined(CORTEX_M0PLUS)
-
-// non-core specific code:
+/*#include "system_CMSDK_CM0plus.h" / * CMSDK_CM0plus System include file * / */
+
+
+#endif /* if defined(CORTEX_M0PLUS) */
+
+/* non-core specific code: */
#ifndef __IM /*!< Fallback for older CMSIS versions */
#define __IM __I
@@ -248,13 +250,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -264,4 +266,4 @@
-#endif //_SYSTEM_D2763_INCLUDED
+#endif /*_SYSTEM_D2763_INCLUDED */
```
</details>
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot removed a comment on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-686343479
<!-- style-bot -->
## Style check summary
### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
#### hw/bsp/dialog_cmac/include/bsp/bsp.h
<details>
```diff
@@ -26,17 +26,19 @@
extern "C" {
#endif
-///* Define special stackos sections */
-//#define sec_data_core __attribute__((section(".data.core")))
-//#define sec_bss_core __attribute__((section(".bss.core")))
-//#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
-//
-///* More convenient section placement macros. */
-//#define bssnz_t sec_bss_nz_core
-//
-//extern uint8_t _ram_start;
-//#define RAM_SIZE 0x80000
-//
+/*
+ / * Define special stackos sections * /
+ #define sec_data_core __attribute__((section(".data.core")))
+ #define sec_bss_core __attribute__((section(".bss.core")))
+ #define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+ / * More convenient section placement macros. * /
+ #define bssnz_t sec_bss_nz_core
+
+ extern uint8_t _ram_start;
+ #define RAM_SIZE 0x80000
+
+ */
#define LED_BLINK_PIN 0
```
</details>
#### hw/bsp/dialog_cmac/src/sbrk.c
<details>
```diff
@@ -23,7 +23,8 @@
static char *brk __attribute__ ((section (".data")));
void
-_sbrkInit(char *base, char *limit) {
+_sbrkInit(char *base, char *limit)
+{
sbrkBase = base;
sbrkLimit = limit;
brk = base;
```
</details>
#### hw/mcu/dialog/cmac/include/mcu/mcu.h
<details>
```diff
@@ -35,11 +35,13 @@
#define MCU_DIAG_MAP(_port, _word, _evt) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos);
+ (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos);
#define MCU_DIAG_MAP_BIT(_port, _word, _evt, _bit) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos);
+ ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos);
/* Output diagnostic setial message */
#ifndef MCU_DIAG_SER_DISABLE
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_sleep.c
<details>
```diff
@@ -119,10 +119,10 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory"
- );
+ );
}
static void
@@ -136,10 +136,10 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory"
- );
+ );
}
static void
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_timer.c
<details>
```diff
@@ -37,8 +37,8 @@
#define SYNC_TICK_TICKS_PER_VAL_INTERVAL ((SYNC_TICK_VAL_INTERVAL) / 1000000 * 128)
#define COMP_TICK_HAS_PASSED(_num) \
- (CMAC->CM_EV_LATCHED_REG & \
- (CMAC_CM_EV_LATCHED_REG_EV1C_CLK_1US_X1_Msk << ((_num) - 1)))
+ (CMAC->CM_EV_LATCHED_REG & \
+ (CMAC_CM_EV_LATCHED_REG_EV1C_CLK_1US_X1_Msk << ((_num) - 1)))
struct cmac_timer_slp {
uint32_t freq;
@@ -87,7 +87,7 @@
__WFE();
__WFE();
- CMAC->CM_CTRL2_REG = reg;
+ CMAC->CM_CTRL2_REG = reg;
}
static inline void
@@ -102,7 +102,7 @@
__WFE();
__WFE();
- CMAC->CM_CTRL2_REG = reg;
+ CMAC->CM_CTRL2_REG = reg;
}
static void
@@ -186,7 +186,8 @@
slept_ns_rem = slept_ns % 1000;
- clk_freq_mhz_d2m1 = (CMAC->CM_CTRL_REG & CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Msk) >> CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Pos;
+ clk_freq_mhz_d2m1 = (CMAC->CM_CTRL_REG & CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Msk) >>
+ CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Pos;
clk_freq_mhz = 2 * (clk_freq_mhz_d2m1 + 1);
comp_timer = slept_ns_rem * clk_freq_mhz / 1000;
@@ -222,10 +223,10 @@
* Compiler barrier to make sure calculations are already done prior to
* this line since code below has strict time constraints.
*/
- asm volatile(""
- :
- :"r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
- : "memory");
+ asm volatile (""
+ :
+ : "r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
+ : "memory");
/*
* Normally we should only wait for next 1MHz tick but since prior to
@@ -438,11 +439,13 @@
#endif
/* XXX uncomment if any of these comparators are used */
-// if (mask & (CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_0_SEL_Msk |
-// CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_X_SEL_Msk |
-// CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_Y_SEL_Msk)) {
-// return 0;
-// }
+/*
+ if (mask & (CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_0_SEL_Msk |
+ CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_X_SEL_Msk |
+ CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_Y_SEL_Msk)) {
+ return 0;
+ }
+ */
val32 = cmac_timer_read32();
```
</details>
#### hw/mcu/dialog/cmac/src/hal_os_tick.c
<details>
```diff
@@ -41,7 +41,7 @@
next = g_os_tick_last + delta;
if (g_os_tick_next == next) {
/* Don't waste time calculating the same llt_val again */
- llt_val = g_os_tick_next_val ;
+ llt_val = g_os_tick_next_val;
} else {
/* Round up to next high part ll_timer value */
llt_val = cmac_timer_convert_tck2llt(next);
```
</details>
#### hw/mcu/dialog/cmac/src/hal_system.c
<details>
```diff
@@ -37,12 +37,14 @@
__disable_irq();
if (hal_debugger_connected()) {
- asm("bkpt");
+ asm ("bkpt");
}
CMAC->CM_EXC_STAT_REG = CMAC_CM_EXC_STAT_REG_EXC_FW_ERROR_Msk;
- for (;;);
+ for (;;) {
+ ;
+ }
}
int
```
</details>
#### hw/mcu/dialog/cmac/src/system_cmac.c
<details>
```diff
@@ -28,7 +28,8 @@
#include "cmac_driver/cmac_diag.h"
#include "CMAC.h"
-void SystemInit(void)
+void
+SystemInit(void)
{
#if MYNEWT_VAL(CMAC_DEBUG_DIAG_ENABLE)
cmac_diag_setup_cmac();
@@ -36,7 +37,9 @@
#if MYNEWT_VAL(MCU_DEBUG_SWD_WAIT_FOR_ATTACH)
while (!hal_debugger_connected());
- for (int i = 0; i < 1000000; i++);
+ for (int i = 0; i < 1000000; i++) {
+ ;
+ }
#endif
CMAC->CM_CTRL_REG &= ~CMAC_CM_CTRL_REG_CM_BS_RESET_N_Msk;
```
</details>
#### hw/mcu/dialog/include/CMAC.h
<details>
```diff
@@ -14,13 +14,13 @@
/** @addtogroup Dialog
- * @{
- */
+ * @{
+ */
/** @addtogroup D2763x
- * @{
- */
+ * @{
+ */
#ifndef D2763X_H
@@ -50,13 +50,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -70,8 +70,8 @@
#endif /*CMSIS_STRIP_HEADER*/
/** @addtogroup Device_Peripheral_peripherals
- * @{
- */
+ * @{
+ */
@@ -81,162 +81,162 @@
/**
- * @brief CMAC registers (CMAC)
- */
+ * @brief CMAC registers (CMAC)
+ */
typedef struct { /*!< (@ 0x40000000) CMAC Structure */
- __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
- __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
- __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
- __I uint32_t RESERVED;
- __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
- __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
- __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
- __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
- __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
- __I uint32_t RESERVED1[23];
- __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
- __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
- __I uint32_t RESERVED2[30];
- __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
- __I uint32_t RESERVED3[3];
- __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
- __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
- __I uint32_t RESERVED4[2];
- __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
- __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
- __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
- __I uint32_t RESERVED5[53];
- __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
- __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
- __I uint32_t RESERVED6[2];
- __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
- __I uint32_t RESERVED7[3];
- __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
- __I uint32_t RESERVED8[3];
- __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
- __I uint32_t RESERVED9[51];
- __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
- __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
- __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
- __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
- __I uint32_t RESERVED10[8];
- __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
- __I uint32_t RESERVED11[2];
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
- __I uint32_t RESERVED12[294];
- __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
- __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
- __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
- __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
- __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
- __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
- __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
- __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
- __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
- __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
- __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
- __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
- __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
- __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
- __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
- __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
- __I uint32_t RESERVED13[16];
- __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
- __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
- __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
- __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
- __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
- __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
- __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
- __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
- __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
- __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
- __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
- __I uint32_t RESERVED14[17];
- __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
- __I uint32_t RESERVED15[3];
- __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
- __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
- __I uint32_t RESERVED16[446];
- __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
- __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
- __I uint32_t RESERVED17[2];
- __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
- __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
- __I uint32_t RESERVED18[2];
- __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
- __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
- __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
- __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
- __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
- __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
- __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
- __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
- __I uint32_t RESERVED19[48];
- __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
- __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
- __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
- __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
- __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
- __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
- __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
- __I uint32_t RESERVED20[949];
- __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
- __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
- __I uint32_t RESERVED21[62];
- __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
- __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
- __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
- __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
+ __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
+ __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
+ __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
+ __I uint32_t RESERVED;
+ __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
+ __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
+ __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
+ __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
+ __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
+ __I uint32_t RESERVED1[23];
+ __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
+ __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
+ __I uint32_t RESERVED2[30];
+ __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
+ __I uint32_t RESERVED3[3];
+ __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
+ __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
+ __I uint32_t RESERVED4[2];
+ __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
+ __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
+ __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
+ __I uint32_t RESERVED5[53];
+ __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
+ __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
+ __I uint32_t RESERVED6[2];
+ __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
+ __I uint32_t RESERVED7[3];
+ __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
+ __I uint32_t RESERVED8[3];
+ __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
+ __I uint32_t RESERVED9[51];
+ __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
+ __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
+ __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
+ __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
+ __I uint32_t RESERVED10[8];
+ __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
+ __I uint32_t RESERVED11[2];
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
+ __I uint32_t RESERVED12[294];
+ __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
+ __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
+ __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
+ __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
+ __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
+ __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
+ __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
+ __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
+ __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
+ __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
+ __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
+ __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
+ __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
+ __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
+ __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
+ __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
+ __I uint32_t RESERVED13[16];
+ __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
+ __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
+ __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
+ __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
+ __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
+ __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
+ __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
+ __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
+ __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
+ __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
+ __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
+ __I uint32_t RESERVED14[17];
+ __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
+ __I uint32_t RESERVED15[3];
+ __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
+ __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
+ __I uint32_t RESERVED16[446];
+ __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
+ __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
+ __I uint32_t RESERVED17[2];
+ __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
+ __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
+ __I uint32_t RESERVED18[2];
+ __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
+ __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
+ __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
+ __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
+ __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
+ __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
+ __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
+ __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
+ __I uint32_t RESERVED19[48];
+ __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
+ __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
+ __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
+ __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
+ __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
+ __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
+ __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
+ __I uint32_t RESERVED20[949];
+ __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
+ __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
+ __I uint32_t RESERVED21[62];
+ __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
+ __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
+ __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
+ __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
} CMAC_Type; /*!< Size = 4396 (0x112c) */
typedef struct { /*!< (@ 0x50010400) CMAC_TIMER_SLP Structure */
- __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
- __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
- __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
+ __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
+ __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
+ __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
} CMAC_TIMER_SLP_Type;
typedef struct { /*!< (@ 0x50000200) PDC Structure */
- __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
- __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
- __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
- __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
- __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
- __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
- __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
- __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
- __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
- __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
- __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
- __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
- __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
- __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
- __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
- __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
- __IM uint32_t RESERVED[16];
- __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
- __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
- __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
- __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
+ __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
+ __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
+ __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
+ __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
+ __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
+ __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
+ __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
+ __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
+ __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
+ __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
+ __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
+ __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
+ __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
+ __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
+ __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
+ __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
+ __IM uint32_t RESERVED[16];
+ __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
+ __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
+ __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
+ __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
} PDC_Type; /*!< Size = 152 (0x98) */
@@ -249,8 +249,8 @@
/** @addtogroup Device_Peripheral_peripheralAddr
- * @{
- */
+ * @{
+ */
#define CMAC_BASE 0x40000000UL
#define CMAC_TIMER_SLP_BASE 0x50010400UL
@@ -265,12 +265,12 @@
/** @addtogroup Device_Peripheral_declaration
- * @{
- */
-
-#define CMAC ((CMAC_Type*) CMAC_BASE)
+ * @{
+ */
+
+#define CMAC ((CMAC_Type *) CMAC_BASE)
#define CMAC_TIMER_SLP ((CMAC_TIMER_SLP_Type *) CMAC_TIMER_SLP_BASE)
-#define PDC ((PDC_Type*) PDC_BASE)
+#define PDC ((PDC_Type *) PDC_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
@@ -279,17 +279,17 @@
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
- /* leave anonymous unions enabled */
+/* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#endif
@@ -299,8 +299,8 @@
/** @addtogroup PosMask_peripherals
- * @{
- */
+ * @{
+ */
```
</details>
#### hw/mcu/dialog/include/system_CMAC.h
<details>
```diff
@@ -7,7 +7,7 @@
#ifndef _SYSTEM_D2763_INCLUDED
#define _SYSTEM_D2763_INCLUDED
-// From datasheet.h:
+/* From datasheet.h: */
/*--GPIO PID functions-------------------------------------------------------------------------*/
#define FUNC_GPIO (0)
@@ -77,73 +77,73 @@
#define DIR_PULLDOWN 0x200
#define DIR_OUTPUT 0x300
-// code copied from global_functions.h
+/* code copied from global_functions.h */
#if defined(CORTEX_M33)
typedef enum {
/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */
- Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
- BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
- UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
- SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
- PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
- SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* ========================================== DA1469x Specific Interrupt Numbers =========================================== */
- SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
- DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
- CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
- CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
- CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
- UART_IRQn = 5, /*!< 5 UART interrupt request. */
- UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
- UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
- I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
- I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
- SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
- SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
- RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
- RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
- RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
- USB_IRQn = 15, /*!< 15 USB interrupt request. */
- TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
- TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
- RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
- KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
- PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
- VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
- MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
- DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
- TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
- DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
- XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
- GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
- SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
- CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
- CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
- RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
- RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
- PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
- TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
- TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
- LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
- RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
- GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
- GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
- SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
- RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
- RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
- RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
- RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
- RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
- RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
- RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
+ SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
+ DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
+ CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
+ CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
+ CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
+ UART_IRQn = 5, /*!< 5 UART interrupt request. */
+ UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
+ UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
+ I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
+ I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
+ SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
+ SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
+ RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
+ RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
+ RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
+ USB_IRQn = 15, /*!< 15 USB interrupt request. */
+ TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
+ TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
+ RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
+ KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
+ PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
+ VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
+ MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
+ DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
+ TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
+ DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
+ XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
+ GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
+ SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
+ CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
+ CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
+ RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
+ RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
+ PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
+ TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
+ TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
+ LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
+ RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
+ GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
+ GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
+ SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
+ RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
+ RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
+ RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
+ RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
+ RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
+ RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
+ RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
} IRQn_Type;
@@ -163,45 +163,47 @@
#include "cmsis_mtb.h"
#endif
-#else // if defined(CORTEX_M0PLUS)
+#else /* if defined(CORTEX_M0PLUS) */
typedef enum IRQn {
/****** Cortex-M0 Processor Exceptions Numbers *****************************************/
-NMI_IRQn = -14, /* 2 Non Maskable Interrupt. */
-HardFault_IRQn = -13, /* 3 Cortex-M0 Hard Fault Interrupt. */
-SVCall_IRQn = -5, /* 11 Cortex-M0 SV Call Interrupt. */
-PendSV_IRQn = -2, /* 14 Cortex-M0 Pend SV Interrupt. */
-SysTick_IRQn = -1, /* 15 Cortex-M0 System Tick Interrupt. */
+ NMI_IRQn = -14,/* 2 Non Maskable Interrupt. */
+ HardFault_IRQn = -13,/* 3 Cortex-M0 Hard Fault Interrupt. */
+ SVCall_IRQn = -5,/* 11 Cortex-M0 SV Call Interrupt. */
+ PendSV_IRQn = -2,/* 14 Cortex-M0 Pend SV Interrupt. */
+ SysTick_IRQn = -1,/* 15 Cortex-M0 System Tick Interrupt. */
/****** CMAC CM0P Specific Interrupt Numbers *******************************************/
-FIELD_IRQn = 0,
-CALLBACK_IRQn = 1,
-FRAME_IRQn = 2,
-DIAG_IRQn = 3,
-HW_GEN_IRQn = 4,
-SW_MAC_IRQn = 5,
-LL_TIMER2PRMTV_IRQn = 6,
-LL_TIMER2LLC_IRQn = 7,
-CRYPTO_IRQn = 8,
-SW_LLC_1_IRQn = 9,
-SW_LLC_2_IRQn = 10,
-SW_LLC_3_IRQn = 11,
-SYS2CMAC_IRQn = 12
+ FIELD_IRQn = 0,
+ CALLBACK_IRQn = 1,
+ FRAME_IRQn = 2,
+ DIAG_IRQn = 3,
+ HW_GEN_IRQn = 4,
+ SW_MAC_IRQn = 5,
+ LL_TIMER2PRMTV_IRQn = 6,
+ LL_TIMER2LLC_IRQn = 7,
+ CRYPTO_IRQn = 8,
+ SW_LLC_1_IRQn = 9,
+ SW_LLC_2_IRQn = 10,
+ SW_LLC_3_IRQn = 11,
+ SYS2CMAC_IRQn = 12
} IRQn_Type;
/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
#define __CM0_REV 0x0000 /*!< Core Revision r2p1 */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-//#define __MPU_PRESENT 1 /*!< MPU present or not */
-//#define __VTOR_PRESENT 1 /*!< Cortex-M0+ can support the VTOR */
+/*
+ #define __MPU_PRESENT 1 / *!< MPU present or not * /
+ #define __VTOR_PRESENT 1 / *!< Cortex-M0+ can support the VTOR * /
+ */
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
-//#include "system_CMSDK_CM0plus.h" /* CMSDK_CM0plus System include file */
-
-
-#endif // if defined(CORTEX_M0PLUS)
-
-// non-core specific code:
+/*#include "system_CMSDK_CM0plus.h" / * CMSDK_CM0plus System include file * / */
+
+
+#endif /* if defined(CORTEX_M0PLUS) */
+
+/* non-core specific code: */
#ifndef __IM /*!< Fallback for older CMSIS versions */
#define __IM __I
@@ -227,13 +229,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -243,4 +245,4 @@
-#endif //_SYSTEM_D2763_INCLUDED
+#endif /*_SYSTEM_D2763_INCLUDED */
```
</details>
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] kasjer commented on a change in pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
kasjer commented on a change in pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#discussion_r482973309
##########
File path: hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_arm.c
##########
@@ -0,0 +1,250 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "mcu/mcu.h"
+#include "hal/hal_os_tick.h"
+#include "os/os_arch_cmac.h"
+/* XXX fix this... */
+#include "../../../../../../apache-mynewt-core/kernel/os/src/os_priv.h"
+
+/* Initial program status register */
+#define INITIAL_xPSR 0x01000000
+
+/* Stack frame structure */
+struct stack_frame {
+ uint32_t r4;
+ uint32_t r5;
+ uint32_t r6;
+ uint32_t r7;
+ uint32_t r8;
+ uint32_t r9;
+ uint32_t r10;
+ uint32_t r11;
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r12;
+ uint32_t lr;
+ uint32_t pc;
+ uint32_t xpsr;
+};
+
+#define SVC_ArgN(n) \
+ register int __r##n __asm("r"#n);
+
+#define SVC_Arg0() \
+ SVC_ArgN(0) \
+ SVC_ArgN(1) \
+ SVC_ArgN(2) \
+ SVC_ArgN(3)
+
+#define SVC_Call(f) \
+ __asm volatile \
+ ( \
+ "ldr r7,="#f"\n\t" \
+ "mov r12,r7\n\t" \
+ "svc 0" \
+ : "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3) \
+ : "r" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) \
+ : "r7", "r12", "lr", "cc" \
+ );
+
+/* XXX: determine how we will deal with running un-privileged */
+uint32_t os_flags = OS_RUN_PRIV;
+
+void
+os_arch_ctx_sw(struct os_task *t)
+{
+ os_sched_ctx_sw_hook(t);
+
+ /* Set PendSV interrupt pending bit to force context switch */
+ os_arch_cmac_pendsvset();
+}
+
+os_stack_t *
+os_arch_task_stack_init(struct os_task *t, os_stack_t *stack_top, int size)
+{
+ int i;
+ os_stack_t *s;
+ struct stack_frame *sf;
+
+ /* Get stack frame pointer */
+ s = (os_stack_t *) ((uint8_t *) stack_top - sizeof(*sf));
Review comment:
space in cast unlike other places few line down
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] kasjer commented on a change in pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
kasjer commented on a change in pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#discussion_r482947246
##########
File path: hw/mcu/dialog/cmac/include/mcu/cmac_timer.h
##########
@@ -0,0 +1,177 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_CMAC_TIMER_H_
+#define __MCU_CMAC_TIMER_H_
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef void (cmac_timer_int_func_t)(void);
+
+extern volatile uint32_t cm_ll_int_stat_reg;
+
+void cmac_timer_init(void);
+void cmac_timer_slp_enable(uint32_t ticks);
+void cmac_timer_slp_disable(uint32_t exp_ticks);
+bool cmac_timer_slp_update(void);
+bool cmac_timer_slp_is_ready(void);
+#if MYNEWT_VAL(MCU_SLP_TIMER_32K_ONLY)
+static inline uint32_t
+cmac_timer_slp_tick_us(void)
+{
+ return 31;
+}
+#else
+uint32_t cmac_timer_slp_tick_us(void);
+#endif
+void cmac_timer_int_hal_timer_register(cmac_timer_int_func_t func);
+void cmac_timer_int_os_tick_register(cmac_timer_int_func_t func);
+void cmac_timer_int_os_tick_clear(void);
+
+uint32_t cmac_timer_next_at(void);
+uint32_t cmac_timer_usecs_to_lp_ticks(uint32_t usecs);
+
+uint32_t cmac_timer_get_hal_os_tick(void);
+
+static inline uint32_t
+cmac_timer_read_lo(void)
+{
+ return CMAC->CM_LL_TIMER1_9_0_REG;
+}
+
+static inline uint32_t
+cmac_timer_read_hi(void)
+{
+ return CMAC->CM_LL_TIMER1_36_10_REG;
+}
+
+/* Reads lsb 32-bit value of LL Timer */
+static inline uint32_t
+cmac_timer_read32(void)
+{
+ uint32_t hi;
+ uint32_t lo;
+
+ do {
+ hi = cmac_timer_read_hi();
+ lo = cmac_timer_read_lo();
+ } while (hi != cmac_timer_read_hi());
+
+ return (hi << 10) | lo;
+}
+
+/* Reads full 37-bit value of LL Timer */
+static inline uint64_t
+cmac_timer_read64(void)
+{
+ uint32_t hi;
+ uint32_t lo;
+
+ do {
+ hi = cmac_timer_read_hi();
+ lo = cmac_timer_read_lo();
+ } while (hi != cmac_timer_read_hi());
+
+ return ((uint64_t)hi << 10) | lo;
+}
+
+static inline void
+cmac_timer_trigger_hal(void)
+{
+ cm_ll_int_stat_reg = CMAC_CM_LL_INT_STAT_REG_LL_TIMER1_EQ_X_SEL_Msk;
+ NVIC_SetPendingIRQ(LL_TIMER2LLC_IRQn);
+}
+
+/* Write comparator value for hal_timer callback */
+static inline void
+cmac_timer_write_eq_hal_timer(uint64_t val)
+{
+ CMAC->CM_LL_TIMER1_EQ_X_HI_REG = val >> 10;
+ CMAC->CM_LL_TIMER1_EQ_X_LO_REG = val;
+ CMAC->CM_LL_INT_MSK_SET_REG = CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_EQ_X_SEL_Msk;
+
+ /*
+ * Need to check if we set comparator in the past (e.g. when trying to set
+ * it at "now" and force interrupt. Note that we cannot mark particular
+ * comparator as triggered so we just use local variable as a "shadow"
+ * register.
+ */
+ if ((int64_t)(val - cmac_timer_read64()) <= 0) {
+ cm_ll_int_stat_reg = CMAC_CM_LL_INT_STAT_REG_LL_TIMER1_EQ_X_SEL_Msk;
+ NVIC_SetPendingIRQ(LL_TIMER2LLC_IRQn);
+ }
+}
+
+/* Disable comparator value for hal_timer callback */
+static inline void
+cmac_timer_disable_eq_hal_timer(void)
+{
+ CMAC->CM_LL_INT_MSK_CLR_REG = CMAC_CM_LL_INT_MSK_CLR_REG_LL_TIMER1_EQ_X_SEL_Msk;
+}
+
+/* Write comparator value for hal_os_tick callback */
+static inline void
+cmac_timer_write_eq_hal_os_tick(uint64_t val)
+{
+ CMAC->CM_LL_TIMER1_36_10_EQ_Y_REG = val >> 10;
+
+ if (((val >> 10) - cmac_timer_read_hi()) <= 0) {
Review comment:
This is unsigned comparison < is never true, change to == or add cast to signed type if val>>10 can be lower then what function returns
##########
File path: hw/mcu/dialog/cmac/src/system_cmac.c
##########
@@ -0,0 +1,53 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include "syscfg/syscfg.h"
+#include "mcu/cmac_hal.h"
+#include "mcu/cmac_pdc.h"
+#include "mcu/cmac_timer.h"
+#include "mcu/cmsis_nvic.h"
+#include "mcu/mcu.h"
+#include "hal/hal_system.h"
+#include "cmac_driver/cmac_diag.h"
+#include "CMAC.h"
+
+void SystemInit(void)
+{
+#if MYNEWT_VAL(CMAC_DEBUG_DIAG_ENABLE)
+ cmac_diag_setup_cmac();
+#endif
+
+#if MYNEWT_VAL(MCU_DEBUG_SWD_WAIT_FOR_ATTACH)
+ while (!hal_debugger_connected());
+ for (int i = 0; i < 1000000; i++);
+#endif
+
+ CMAC->CM_CTRL_REG &= ~CMAC_CM_CTRL_REG_CM_BS_RESET_N_Msk;
+ CMAC->CM_CTRL_REG |= CMAC_CM_CTRL_REG_CM_BS_RESET_N_Msk;
+
+ CMAC->CM_CTRL_REG = (CMAC->CM_CTRL_REG &
+ ~CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Msk) |
+ (15 << CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Pos);
+ CMAC->CM_CTRL2_REG = CMAC_CM_CTRL2_REG_LL_TIMER1_9_0_LIMITED_N_Msk;
+
+ CMAC->CM_CTRL_REG |= CMAC_CM_CTRL_REG_CM_BS_ENABLE_Msk;
+
+ cmac_timer_init();
+};
Review comment:
``;`` after function body
##########
File path: hw/mcu/dialog/cmac/include/mcu/mcu.h
##########
@@ -0,0 +1,64 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_MCU_H_
+#define __MCU_MCU_H_
+
+#include "CMAC.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SVC_IRQ_NUMBER SVCall_IRQn
+
+#define MCU_MEM_SYSRAM_START_ADDRESS (0x20000000)
+#define MCU_MEM_SYSRAM_END_ADDRESS (0x20080000)
+
+/* Map diagnostic signal to diagnostic port (output) */
+#define MCU_DIAG_MAP(_port, _word, _evt) \
Review comment:
MCU_DIAG_MAP and MCU_DIAG_MAP_BIT are never used, but if they were ``;`` would be more expected on the lines that use those macros like in next macros in this file.
##########
File path: hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_arm.c
##########
@@ -0,0 +1,250 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "mcu/mcu.h"
+#include "hal/hal_os_tick.h"
+#include "os/os_arch_cmac.h"
+/* XXX fix this... */
+#include "../../../../../../apache-mynewt-core/kernel/os/src/os_priv.h"
+
+/* Initial program status register */
+#define INITIAL_xPSR 0x01000000
+
+/* Stack frame structure */
+struct stack_frame {
+ uint32_t r4;
+ uint32_t r5;
+ uint32_t r6;
+ uint32_t r7;
+ uint32_t r8;
+ uint32_t r9;
+ uint32_t r10;
+ uint32_t r11;
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r12;
+ uint32_t lr;
+ uint32_t pc;
+ uint32_t xpsr;
+};
+
+#define SVC_ArgN(n) \
+ register int __r##n __asm("r"#n);
+
+#define SVC_Arg0() \
+ SVC_ArgN(0) \
+ SVC_ArgN(1) \
+ SVC_ArgN(2) \
+ SVC_ArgN(3)
+
+#define SVC_Call(f) \
+ __asm volatile \
+ ( \
+ "ldr r7,="#f"\n\t" \
+ "mov r12,r7\n\t" \
+ "svc 0" \
+ : "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3) \
+ : "r" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) \
+ : "r7", "r12", "lr", "cc" \
+ );
+
+/* XXX: determine how we will deal with running un-privileged */
+uint32_t os_flags = OS_RUN_PRIV;
+
+void
+os_arch_ctx_sw(struct os_task *t)
+{
+ os_sched_ctx_sw_hook(t);
+
+ /* Set PendSV interrupt pending bit to force context switch */
+ os_arch_cmac_pendsvset();
+}
+
+os_stack_t *
+os_arch_task_stack_init(struct os_task *t, os_stack_t *stack_top, int size)
+{
+ int i;
+ os_stack_t *s;
+ struct stack_frame *sf;
+
+ /* Get stack frame pointer */
+ s = (os_stack_t *) ((uint8_t *) stack_top - sizeof(*sf));
+
+ /* Zero out R1-R3, R12, LR */
+ for (i = 9; i < 14; ++i) {
+ s[i] = 0;
+ }
+
+ /* Set registers R4 - R11 on stack. */
+ os_arch_init_task_stack(s);
+
+ /* Set remaining portions of stack frame */
+ sf = (struct stack_frame *) s;
+ sf->xpsr = INITIAL_xPSR;
+ sf->pc = (uint32_t)t->t_func;
+ sf->r0 = (uint32_t)t->t_arg;
+
+ return (s);
Review comment:
other places in this file do not use ``()`` for return values
##########
File path: hw/mcu/dialog/cmac/include/mcu/mcu.h
##########
@@ -0,0 +1,64 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_MCU_H_
+#define __MCU_MCU_H_
+
+#include "CMAC.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SVC_IRQ_NUMBER SVCall_IRQn
+
+#define MCU_MEM_SYSRAM_START_ADDRESS (0x20000000)
+#define MCU_MEM_SYSRAM_END_ADDRESS (0x20080000)
+
+/* Map diagnostic signal to diagnostic port (output) */
+#define MCU_DIAG_MAP(_port, _word, _evt) \
+ CMAC->CM_DIAG_PORT ## _port ## _REG = \
+ (_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
+ (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos);
+#define MCU_DIAG_MAP_BIT(_port, _word, _evt, _bit) \
+ CMAC->CM_DIAG_PORT ## _port ## _REG = \
+ (_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
+ ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos);
+
+/* Output diagnostic setial message */
+#ifndef MCU_DIAG_SER_DISABLE
+#define MCU_DIAG_SER(_ch) \
Review comment:
other macros with similar functionality here don't use ``do {} while (0)``.
##########
File path: hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_arm.c
##########
@@ -0,0 +1,250 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "mcu/mcu.h"
+#include "hal/hal_os_tick.h"
+#include "os/os_arch_cmac.h"
+/* XXX fix this... */
+#include "../../../../../../apache-mynewt-core/kernel/os/src/os_priv.h"
+
+/* Initial program status register */
+#define INITIAL_xPSR 0x01000000
+
+/* Stack frame structure */
+struct stack_frame {
+ uint32_t r4;
+ uint32_t r5;
+ uint32_t r6;
+ uint32_t r7;
+ uint32_t r8;
+ uint32_t r9;
+ uint32_t r10;
+ uint32_t r11;
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r12;
+ uint32_t lr;
+ uint32_t pc;
+ uint32_t xpsr;
+};
+
+#define SVC_ArgN(n) \
+ register int __r##n __asm("r"#n);
+
+#define SVC_Arg0() \
+ SVC_ArgN(0) \
+ SVC_ArgN(1) \
+ SVC_ArgN(2) \
+ SVC_ArgN(3)
+
+#define SVC_Call(f) \
+ __asm volatile \
+ ( \
+ "ldr r7,="#f"\n\t" \
+ "mov r12,r7\n\t" \
+ "svc 0" \
+ : "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3) \
+ : "r" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) \
+ : "r7", "r12", "lr", "cc" \
+ );
+
+/* XXX: determine how we will deal with running un-privileged */
+uint32_t os_flags = OS_RUN_PRIV;
+
+void
+os_arch_ctx_sw(struct os_task *t)
+{
+ os_sched_ctx_sw_hook(t);
+
+ /* Set PendSV interrupt pending bit to force context switch */
+ os_arch_cmac_pendsvset();
+}
+
+os_stack_t *
+os_arch_task_stack_init(struct os_task *t, os_stack_t *stack_top, int size)
+{
+ int i;
+ os_stack_t *s;
+ struct stack_frame *sf;
+
+ /* Get stack frame pointer */
+ s = (os_stack_t *) ((uint8_t *) stack_top - sizeof(*sf));
Review comment:
space in case unlike other places few line down
##########
File path: hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_cmac.c
##########
@@ -0,0 +1,321 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "mcu/mcu.h"
+#include "hal/hal_os_tick.h"
+#include "CMAC.h"
+
+/*
+ * Interrupts handling on CMAC needs to be a bit different than in generic M0+
+ * arch. We need FIELD, FRAME and CALLBACK interrupts to be handled in real-time
+ * as otherwise PHY will fail due to interrupt latency. For this reason we need
+ * to have BASEPRI-like behavior but since M0+ does not support BASEPRI in hw,
+ * this is emulated in sw.
+ *
+ * CMAC.h includes os_arm_cmac.h which redefines NVIC_Enable/Disable to make
+ * sure ICER/ISER is not accessed directly outside this file.
+ *
+ * Configured state for ISER is kept in shadow register (g_cmac_iser_shadow)
+ * and is applied only when not in critical section or when exiting critical
+ * section.
+ *
+ * When entering critical section all standard (i.e. other than those we need
+ * to keep always enabled) interrupts are disabled via ICER and flag is set to
+ * mimic PRIMASK behavior.
+ *
+ * Additional handling is required for PendSV since it cannot be disabled from
+ * NVIC so there is another flag which indicates that PendSV should be set. This
+ * is done when exiting critical section - we assume that PendSV is being set to
+ * pending only when in critical section (which is true for Mynewt since it's
+ * done on context switch and we do not expect our controller on CMAC to work
+ * with any other OS ever).
+ *
+ * Finally, before execuing 'wfi' we need to globally disable all interrupts but
+ * so we can restore ISER for all interrupts and thus 'wfi' will wakeup on any
+ * configured interrupt. After 'wfi', ICER is used to restore pre-wfi state and
+ * interrupts and globally unlocked .
+ */
+
+/* XXX temporary, for dev only */
+#define CMAC_ARCH_SANITY_CHECK (1)
+
+/*
+ * There are 3 groups of interrupts:
+ * - BS_CTRL -> bistream controller (FIELD/FRAME/CALLBACK) interrupts which
+ * are not disabled while in critical section and can be only
+ * disabled explicitly using NVIC_DisableIRQ or blocked using
+ * os_arch_cmac_bs_ctrl_irq_block()
+ * these interrupts cannot call functions that access OS or other
+ * shared data
+ * - HI_PRIO -> SW_MAC interrupt which is disabled in critical section like
+ * other interrupts, but will be enabled when executing idle
+ * entry/exit code so it is not affected by increased latency
+ * introduced by that code
+ * this interrupt can safely access OS and other shared data,
+ * except for functions that need accurate os_time since system
+ * tick may be not up to date
+ * - OTHER -> all other interrupts
+ */
+
+/*
+ * XXX for now add crypto to bs_ctrl although it probably should have separate
+ * group since it's perfectly fine for it to be enabled during handover
+ */
+#define CMAC_ARCH_I_BS_CTRL (0x0107)
+#define CMAC_ARCH_I_HI_PRIO (0x0020)
+#define CMAC_ARCH_I_OTHER (0x1ed8)
+#define CMAC_ARCH_I_NON_BS_CTRL (CMAC_ARCH_I_HI_PRIO | \
+ CMAC_ARCH_I_OTHER)
+#define CMAC_ARCH_I_ALL (CMAC_ARCH_I_BS_CTRL | \
+ CMAC_ARCH_I_HI_PRIO | \
+ CMAC_ARCH_I_OTHER)
+#define CMAC_ARCH_F_PRIMASK (0x0001)
+#define CMAC_ARCH_F_PENDSV (0x0002)
+#define CMAC_ARCH_F_IDLE_SECTION (0x0004)
+#define CMAC_ARCH_F_BS_CTRL_BLOCKED (0x0008)
+
+static uint16_t g_cmac_arch_flags;
+static uint16_t g_cmac_arch_iser_shadow;
+
+extern int cmac_sleep_do_sleep(void) __attribute__((naked));
+
+os_sr_t
+os_arch_save_sr(void)
+{
+ uint32_t ctx;
+
+ __disable_irq();
+
+ ctx = g_cmac_arch_flags & CMAC_ARCH_F_PRIMASK;
+
+#if CMAC_ARCH_SANITY_CHECK
+ assert(!ctx ||
+ (!(g_cmac_arch_flags & CMAC_ARCH_F_IDLE_SECTION) && !(NVIC->ISER[0] & CMAC_ARCH_I_NON_BS_CTRL)) ||
+ ((g_cmac_arch_flags & CMAC_ARCH_F_IDLE_SECTION) && !(NVIC->ISER[0] & CMAC_ARCH_I_OTHER)));
+#endif
+
+ if (g_cmac_arch_flags & CMAC_ARCH_F_IDLE_SECTION) {
+ NVIC->ICER[0] = CMAC_ARCH_I_OTHER;
+ } else {
+ NVIC->ICER[0] = CMAC_ARCH_I_NON_BS_CTRL;
+ }
+ g_cmac_arch_flags |= CMAC_ARCH_F_PRIMASK;
+
+ __enable_irq();
+
+ return ctx;
+}
+
+void
+os_arch_restore_sr(os_sr_t ctx)
+{
+ if (ctx) {
+ return;
+ }
+
+#if CMAC_ARCH_SANITY_CHECK
+ assert(g_cmac_arch_flags & CMAC_ARCH_F_PRIMASK);
+ assert(!(NVIC->ISER[0] & CMAC_ARCH_I_NON_BS_CTRL));
+#endif
+
+ __disable_irq();
+
+ if (g_cmac_arch_flags & CMAC_ARCH_F_PENDSV) {
+ SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
+ }
+ g_cmac_arch_flags &= ~(CMAC_ARCH_F_PRIMASK | CMAC_ARCH_F_PENDSV);
+
+ NVIC->ISER[0] = g_cmac_arch_iser_shadow & CMAC_ARCH_I_NON_BS_CTRL;
+
+ __enable_irq();
+}
+
+int
+os_arch_in_critical(void)
+{
+ return g_cmac_arch_flags & CMAC_ARCH_F_PRIMASK;
+}
+
+void
+os_arch_cmac_enable_irq(IRQn_Type irqn)
+{
+ uint32_t irqm = 1 << irqn;
+
+ __disable_irq();
+
+ g_cmac_arch_iser_shadow |= irqm;
+
+ /*
+ * Enable interrupt in NVIC if either::
Review comment:
double double colon
##########
File path: hw/mcu/dialog/cmac/src/hal_timer.c
##########
@@ -0,0 +1,214 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdint.h>
+#include "syscfg/syscfg.h"
+#include "mcu/mcu.h"
+#include "mcu/cmac_hal.h"
+#include "mcu/cmac_timer.h"
+#include "hal/hal_timer.h"
+#include "sys/queue.h"
+#include "defs/error.h"
+#include "os/os_arch.h"
+#include "os/util.h"
+
+#define TICKS_GT(_t1, _t2) ((int64_t)((_t1) - (_t2)) > 0)
+#define TICKS_GTE(_t1, _t2) ((int64_t)((_t1) - (_t2)) >= 0)
+#define TICKS_LT(_t1, _t2) ((int64_t)((_t1) - (_t2)) < 0)
+#define TICKS_LTE(_t1, _t2) ((int64_t)((_t1) - (_t2)) <= 0)
+
+static TAILQ_HEAD(hal_timer_qhead, hal_timer) g_hal_timer_queue;
+
+/*
+ * To avoid converting back and forth between uint64_t values returned by
+ * cmac_timer and uint32_t representing hal_timer ticks, we compare cmac_timer
+ * ticks everywhere. For this we need to store expiry value as uint64_t, so we
+ * use bsp_timer (which is not used here since we only have one timer) pointer
+ * to store high word of value.
+ */
+
+static inline uint64_t
+hal_timer_expiry_get(struct hal_timer *timer)
+{
+ uint64_t ret;
+
+ ret = (uint64_t)POINTER_TO_UINT(timer->bsp_timer) << 10;
+ ret |= timer->expiry;
+
+ return ret;
+}
+
+static inline void
+hal_timer_expiry_set(struct hal_timer *timer, uint64_t val)
+{
+ timer->expiry = val & 0x3ff;
+ timer->bsp_timer = UINT_TO_POINTER(val >> 10);
+}
+
+static void
+hal_timer_check_queue(void)
+{
+ os_sr_t sr;
+ struct hal_timer *e;
+ uint64_t ll_timer_val;
+
+ OS_ENTER_CRITICAL(sr);
+
+ while ((e = TAILQ_FIRST(&g_hal_timer_queue)) != NULL) {
+ ll_timer_val = cmac_timer_read64();
+ if (TICKS_GT(hal_timer_expiry_get(e), ll_timer_val)) {
+ break;
+ }
+
+ TAILQ_REMOVE(&g_hal_timer_queue, e, link);
+ e->link.tqe_prev = NULL;
+ e->cb_func(e->cb_arg);
+ }
+
+ if (e != NULL) {
+ cmac_timer_write_eq_hal_timer(hal_timer_expiry_get(e));
+ } else {
+ cmac_timer_disable_eq_hal_timer();
+ }
+
+ OS_EXIT_CRITICAL(sr);
+}
+
+static void
+hal_timer_cmac_timer_cb(void)
+{
+#if MYNEWT_VAL(TIMER_0)
+ hal_timer_check_queue();
+#endif
+}
+
+int
+hal_timer_init(int timer_num, void *cfg)
+{
+ assert(timer_num == 0);
+
+ cmac_timer_int_hal_timer_register(hal_timer_cmac_timer_cb);
+
+ TAILQ_INIT(&g_hal_timer_queue);
+
+ return 0;
+}
+
+int
+hal_timer_config(int timer_num, uint32_t freq_hz)
+{
+ assert(timer_num == 0);
+ assert(freq_hz == 32768);
+
+ return 0;
+}
+
+int
+hal_timer_set_cb(int timer_num, struct hal_timer *timer, hal_timer_cb func,
+ void *arg)
+{
+ assert(timer_num == 0);
+
+ timer->cb_func = func;
+ timer->cb_arg = arg;
+ timer->link.tqe_prev = NULL;
+
+ return 0;
+}
+
+int
+hal_timer_start_at(struct hal_timer *timer, uint32_t tick)
+{
+ struct hal_timer *e;
Review comment:
``e`` is strange choice of a name :)
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot removed a comment on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-694821227
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot removed a comment on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-694821227
<!-- style-bot -->
## Style check summary
### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
#### hw/bsp/dialog_cmac/include/bsp/bsp.h
<details>
```diff
@@ -26,17 +26,19 @@
extern "C" {
#endif
-///* Define special stackos sections */
-//#define sec_data_core __attribute__((section(".data.core")))
-//#define sec_bss_core __attribute__((section(".bss.core")))
-//#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
-//
-///* More convenient section placement macros. */
-//#define bssnz_t sec_bss_nz_core
-//
-//extern uint8_t _ram_start;
-//#define RAM_SIZE 0x80000
-//
+/*
+ / * Define special stackos sections * /
+ #define sec_data_core __attribute__((section(".data.core")))
+ #define sec_bss_core __attribute__((section(".bss.core")))
+ #define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+ / * More convenient section placement macros. * /
+ #define bssnz_t sec_bss_nz_core
+
+ extern uint8_t _ram_start;
+ #define RAM_SIZE 0x80000
+
+ */
#define LED_BLINK_PIN 0
```
</details>
#### hw/bsp/dialog_cmac/src/sbrk.c
<details>
```diff
@@ -23,7 +23,8 @@
static char *brk __attribute__ ((section (".data")));
void
-_sbrkInit(char *base, char *limit) {
+_sbrkInit(char *base, char *limit)
+{
sbrkBase = base;
sbrkLimit = limit;
brk = base;
```
</details>
#### hw/mcu/dialog/cmac/include/mcu/mcu.h
<details>
```diff
@@ -35,11 +35,13 @@
#define MCU_DIAG_MAP(_port, _word, _evt) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
+ (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
#define MCU_DIAG_MAP_BIT(_port, _word, _evt, _bit) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
+ ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
/* Output diagnostic setial message */
#ifndef MCU_DIAG_SER_DISABLE
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_sleep.c
<details>
```diff
@@ -119,10 +119,10 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory"
- );
+ );
}
static void
@@ -136,10 +136,10 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory"
- );
+ );
}
static void
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_timer.c
<details>
```diff
@@ -37,8 +37,8 @@
#define SYNC_TICK_TICKS_PER_VAL_INTERVAL ((SYNC_TICK_VAL_INTERVAL) / 1000000 * 128)
#define COMP_TICK_HAS_PASSED(_num) \
- (CMAC->CM_EV_LATCHED_REG & \
- (CMAC_CM_EV_LATCHED_REG_EV1C_CLK_1US_X1_Msk << ((_num) - 1)))
+ (CMAC->CM_EV_LATCHED_REG & \
+ (CMAC_CM_EV_LATCHED_REG_EV1C_CLK_1US_X1_Msk << ((_num) - 1)))
struct cmac_timer_slp {
uint32_t freq;
@@ -87,7 +87,7 @@
__WFE();
__WFE();
- CMAC->CM_CTRL2_REG = reg;
+ CMAC->CM_CTRL2_REG = reg;
}
static inline void
@@ -102,7 +102,7 @@
__WFE();
__WFE();
- CMAC->CM_CTRL2_REG = reg;
+ CMAC->CM_CTRL2_REG = reg;
}
static void
@@ -186,7 +186,8 @@
slept_ns_rem = slept_ns % 1000;
- clk_freq_mhz_d2m1 = (CMAC->CM_CTRL_REG & CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Msk) >> CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Pos;
+ clk_freq_mhz_d2m1 = (CMAC->CM_CTRL_REG & CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Msk) >>
+ CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Pos;
clk_freq_mhz = 2 * (clk_freq_mhz_d2m1 + 1);
comp_timer = slept_ns_rem * clk_freq_mhz / 1000;
@@ -222,10 +223,10 @@
* Compiler barrier to make sure calculations are already done prior to
* this line since code below has strict time constraints.
*/
- asm volatile(""
- :
- :"r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
- : "memory");
+ asm volatile (""
+ :
+ : "r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
+ : "memory");
/*
* Normally we should only wait for next 1MHz tick but since prior to
@@ -438,11 +439,13 @@
#endif
/* XXX uncomment if any of these comparators are used */
-// if (mask & (CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_0_SEL_Msk |
-// CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_X_SEL_Msk |
-// CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_Y_SEL_Msk)) {
-// return 0;
-// }
+/*
+ if (mask & (CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_0_SEL_Msk |
+ CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_X_SEL_Msk |
+ CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_Y_SEL_Msk)) {
+ return 0;
+ }
+ */
val32 = cmac_timer_read32();
```
</details>
#### hw/mcu/dialog/cmac/src/hal_os_tick.c
<details>
```diff
@@ -41,7 +41,7 @@
next = g_os_tick_last + delta;
if (g_os_tick_next == next) {
/* Don't waste time calculating the same llt_val again */
- llt_val = g_os_tick_next_val ;
+ llt_val = g_os_tick_next_val;
} else {
/* Round up to next high part ll_timer value */
llt_val = cmac_timer_convert_tck2llt(next);
```
</details>
#### hw/mcu/dialog/cmac/src/hal_system.c
<details>
```diff
@@ -37,12 +37,14 @@
__disable_irq();
if (hal_debugger_connected()) {
- asm("bkpt");
+ asm ("bkpt");
}
CMAC->CM_EXC_STAT_REG = CMAC_CM_EXC_STAT_REG_EXC_FW_ERROR_Msk;
- for (;;);
+ for (;;) {
+ ;
+ }
}
int
```
</details>
#### hw/mcu/dialog/cmac/src/system_cmac.c
<details>
```diff
@@ -28,7 +28,8 @@
#include "cmac_driver/cmac_diag.h"
#include "CMAC.h"
-void SystemInit(void)
+void
+SystemInit(void)
{
#if MYNEWT_VAL(CMAC_DEBUG_DIAG_ENABLE)
cmac_diag_setup_cmac();
@@ -36,7 +37,9 @@
#if MYNEWT_VAL(MCU_DEBUG_SWD_WAIT_FOR_ATTACH)
while (!hal_debugger_connected());
- for (int i = 0; i < 1000000; i++);
+ for (int i = 0; i < 1000000; i++) {
+ ;
+ }
#endif
CMAC->CM_CTRL_REG &= ~CMAC_CM_CTRL_REG_CM_BS_RESET_N_Msk;
```
</details>
#### hw/mcu/dialog/include/CMAC.h
<details>
```diff
@@ -35,13 +35,13 @@
/** @addtogroup Dialog
- * @{
- */
+ * @{
+ */
/** @addtogroup D2763x
- * @{
- */
+ * @{
+ */
#ifndef D2763X_H
@@ -71,13 +71,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -91,8 +91,8 @@
#endif /*CMSIS_STRIP_HEADER*/
/** @addtogroup Device_Peripheral_peripherals
- * @{
- */
+ * @{
+ */
@@ -102,162 +102,162 @@
/**
- * @brief CMAC registers (CMAC)
- */
+ * @brief CMAC registers (CMAC)
+ */
typedef struct { /*!< (@ 0x40000000) CMAC Structure */
- __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
- __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
- __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
- __I uint32_t RESERVED;
- __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
- __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
- __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
- __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
- __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
- __I uint32_t RESERVED1[23];
- __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
- __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
- __I uint32_t RESERVED2[30];
- __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
- __I uint32_t RESERVED3[3];
- __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
- __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
- __I uint32_t RESERVED4[2];
- __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
- __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
- __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
- __I uint32_t RESERVED5[53];
- __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
- __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
- __I uint32_t RESERVED6[2];
- __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
- __I uint32_t RESERVED7[3];
- __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
- __I uint32_t RESERVED8[3];
- __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
- __I uint32_t RESERVED9[51];
- __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
- __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
- __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
- __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
- __I uint32_t RESERVED10[8];
- __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
- __I uint32_t RESERVED11[2];
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
- __I uint32_t RESERVED12[294];
- __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
- __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
- __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
- __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
- __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
- __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
- __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
- __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
- __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
- __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
- __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
- __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
- __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
- __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
- __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
- __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
- __I uint32_t RESERVED13[16];
- __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
- __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
- __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
- __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
- __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
- __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
- __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
- __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
- __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
- __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
- __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
- __I uint32_t RESERVED14[17];
- __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
- __I uint32_t RESERVED15[3];
- __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
- __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
- __I uint32_t RESERVED16[446];
- __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
- __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
- __I uint32_t RESERVED17[2];
- __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
- __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
- __I uint32_t RESERVED18[2];
- __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
- __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
- __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
- __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
- __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
- __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
- __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
- __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
- __I uint32_t RESERVED19[48];
- __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
- __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
- __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
- __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
- __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
- __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
- __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
- __I uint32_t RESERVED20[949];
- __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
- __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
- __I uint32_t RESERVED21[62];
- __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
- __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
- __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
- __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
+ __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
+ __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
+ __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
+ __I uint32_t RESERVED;
+ __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
+ __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
+ __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
+ __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
+ __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
+ __I uint32_t RESERVED1[23];
+ __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
+ __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
+ __I uint32_t RESERVED2[30];
+ __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
+ __I uint32_t RESERVED3[3];
+ __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
+ __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
+ __I uint32_t RESERVED4[2];
+ __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
+ __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
+ __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
+ __I uint32_t RESERVED5[53];
+ __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
+ __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
+ __I uint32_t RESERVED6[2];
+ __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
+ __I uint32_t RESERVED7[3];
+ __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
+ __I uint32_t RESERVED8[3];
+ __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
+ __I uint32_t RESERVED9[51];
+ __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
+ __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
+ __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
+ __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
+ __I uint32_t RESERVED10[8];
+ __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
+ __I uint32_t RESERVED11[2];
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
+ __I uint32_t RESERVED12[294];
+ __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
+ __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
+ __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
+ __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
+ __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
+ __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
+ __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
+ __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
+ __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
+ __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
+ __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
+ __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
+ __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
+ __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
+ __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
+ __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
+ __I uint32_t RESERVED13[16];
+ __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
+ __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
+ __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
+ __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
+ __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
+ __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
+ __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
+ __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
+ __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
+ __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
+ __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
+ __I uint32_t RESERVED14[17];
+ __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
+ __I uint32_t RESERVED15[3];
+ __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
+ __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
+ __I uint32_t RESERVED16[446];
+ __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
+ __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
+ __I uint32_t RESERVED17[2];
+ __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
+ __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
+ __I uint32_t RESERVED18[2];
+ __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
+ __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
+ __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
+ __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
+ __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
+ __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
+ __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
+ __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
+ __I uint32_t RESERVED19[48];
+ __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
+ __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
+ __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
+ __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
+ __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
+ __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
+ __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
+ __I uint32_t RESERVED20[949];
+ __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
+ __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
+ __I uint32_t RESERVED21[62];
+ __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
+ __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
+ __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
+ __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
} CMAC_Type; /*!< Size = 4396 (0x112c) */
typedef struct { /*!< (@ 0x50010400) CMAC_TIMER_SLP Structure */
- __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
- __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
- __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
+ __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
+ __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
+ __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
} CMAC_TIMER_SLP_Type;
typedef struct { /*!< (@ 0x50000200) PDC Structure */
- __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
- __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
- __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
- __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
- __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
- __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
- __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
- __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
- __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
- __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
- __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
- __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
- __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
- __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
- __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
- __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
- __IM uint32_t RESERVED[16];
- __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
- __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
- __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
- __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
+ __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
+ __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
+ __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
+ __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
+ __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
+ __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
+ __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
+ __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
+ __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
+ __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
+ __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
+ __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
+ __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
+ __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
+ __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
+ __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
+ __IM uint32_t RESERVED[16];
+ __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
+ __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
+ __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
+ __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
} PDC_Type; /*!< Size = 152 (0x98) */
@@ -270,8 +270,8 @@
/** @addtogroup Device_Peripheral_peripheralAddr
- * @{
- */
+ * @{
+ */
#define CMAC_BASE 0x40000000UL
#define CMAC_TIMER_SLP_BASE 0x50010400UL
@@ -286,12 +286,12 @@
/** @addtogroup Device_Peripheral_declaration
- * @{
- */
-
-#define CMAC ((CMAC_Type*) CMAC_BASE)
+ * @{
+ */
+
+#define CMAC ((CMAC_Type *) CMAC_BASE)
#define CMAC_TIMER_SLP ((CMAC_TIMER_SLP_Type *) CMAC_TIMER_SLP_BASE)
-#define PDC ((PDC_Type*) PDC_BASE)
+#define PDC ((PDC_Type *) PDC_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
@@ -300,17 +300,17 @@
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
- /* leave anonymous unions enabled */
+/* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#endif
@@ -320,8 +320,8 @@
/** @addtogroup PosMask_peripherals
- * @{
- */
+ * @{
+ */
```
</details>
#### hw/mcu/dialog/include/system_CMAC.h
<details>
```diff
@@ -28,7 +28,7 @@
#ifndef _SYSTEM_D2763_INCLUDED
#define _SYSTEM_D2763_INCLUDED
-// From datasheet.h:
+/* From datasheet.h: */
/*--GPIO PID functions-------------------------------------------------------------------------*/
#define FUNC_GPIO (0)
@@ -98,73 +98,73 @@
#define DIR_PULLDOWN 0x200
#define DIR_OUTPUT 0x300
-// code copied from global_functions.h
+/* code copied from global_functions.h */
#if defined(CORTEX_M33)
typedef enum {
/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */
- Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
- BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
- UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
- SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
- PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
- SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* ========================================== DA1469x Specific Interrupt Numbers =========================================== */
- SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
- DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
- CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
- CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
- CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
- UART_IRQn = 5, /*!< 5 UART interrupt request. */
- UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
- UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
- I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
- I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
- SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
- SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
- RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
- RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
- RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
- USB_IRQn = 15, /*!< 15 USB interrupt request. */
- TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
- TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
- RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
- KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
- PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
- VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
- MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
- DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
- TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
- DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
- XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
- GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
- SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
- CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
- CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
- RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
- RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
- PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
- TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
- TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
- LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
- RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
- GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
- GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
- SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
- RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
- RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
- RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
- RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
- RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
- RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
- RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
+ SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
+ DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
+ CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
+ CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
+ CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
+ UART_IRQn = 5, /*!< 5 UART interrupt request. */
+ UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
+ UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
+ I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
+ I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
+ SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
+ SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
+ RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
+ RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
+ RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
+ USB_IRQn = 15, /*!< 15 USB interrupt request. */
+ TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
+ TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
+ RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
+ KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
+ PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
+ VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
+ MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
+ DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
+ TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
+ DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
+ XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
+ GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
+ SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
+ CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
+ CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
+ RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
+ RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
+ PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
+ TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
+ TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
+ LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
+ RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
+ GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
+ GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
+ SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
+ RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
+ RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
+ RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
+ RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
+ RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
+ RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
+ RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
} IRQn_Type;
@@ -184,45 +184,47 @@
#include "cmsis_mtb.h"
#endif
-#else // if defined(CORTEX_M0PLUS)
+#else /* if defined(CORTEX_M0PLUS) */
typedef enum IRQn {
/****** Cortex-M0 Processor Exceptions Numbers *****************************************/
-NMI_IRQn = -14, /* 2 Non Maskable Interrupt. */
-HardFault_IRQn = -13, /* 3 Cortex-M0 Hard Fault Interrupt. */
-SVCall_IRQn = -5, /* 11 Cortex-M0 SV Call Interrupt. */
-PendSV_IRQn = -2, /* 14 Cortex-M0 Pend SV Interrupt. */
-SysTick_IRQn = -1, /* 15 Cortex-M0 System Tick Interrupt. */
+ NMI_IRQn = -14,/* 2 Non Maskable Interrupt. */
+ HardFault_IRQn = -13,/* 3 Cortex-M0 Hard Fault Interrupt. */
+ SVCall_IRQn = -5,/* 11 Cortex-M0 SV Call Interrupt. */
+ PendSV_IRQn = -2,/* 14 Cortex-M0 Pend SV Interrupt. */
+ SysTick_IRQn = -1,/* 15 Cortex-M0 System Tick Interrupt. */
/****** CMAC CM0P Specific Interrupt Numbers *******************************************/
-FIELD_IRQn = 0,
-CALLBACK_IRQn = 1,
-FRAME_IRQn = 2,
-DIAG_IRQn = 3,
-HW_GEN_IRQn = 4,
-SW_MAC_IRQn = 5,
-LL_TIMER2PRMTV_IRQn = 6,
-LL_TIMER2LLC_IRQn = 7,
-CRYPTO_IRQn = 8,
-SW_LLC_1_IRQn = 9,
-SW_LLC_2_IRQn = 10,
-SW_LLC_3_IRQn = 11,
-SYS2CMAC_IRQn = 12
+ FIELD_IRQn = 0,
+ CALLBACK_IRQn = 1,
+ FRAME_IRQn = 2,
+ DIAG_IRQn = 3,
+ HW_GEN_IRQn = 4,
+ SW_MAC_IRQn = 5,
+ LL_TIMER2PRMTV_IRQn = 6,
+ LL_TIMER2LLC_IRQn = 7,
+ CRYPTO_IRQn = 8,
+ SW_LLC_1_IRQn = 9,
+ SW_LLC_2_IRQn = 10,
+ SW_LLC_3_IRQn = 11,
+ SYS2CMAC_IRQn = 12
} IRQn_Type;
/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
#define __CM0_REV 0x0000 /*!< Core Revision r2p1 */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-//#define __MPU_PRESENT 1 /*!< MPU present or not */
-//#define __VTOR_PRESENT 1 /*!< Cortex-M0+ can support the VTOR */
+/*
+ #define __MPU_PRESENT 1 / *!< MPU present or not * /
+ #define __VTOR_PRESENT 1 / *!< Cortex-M0+ can support the VTOR * /
+ */
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
-//#include "system_CMSDK_CM0plus.h" /* CMSDK_CM0plus System include file */
-
-
-#endif // if defined(CORTEX_M0PLUS)
-
-// non-core specific code:
+/*#include "system_CMSDK_CM0plus.h" / * CMSDK_CM0plus System include file * / */
+
+
+#endif /* if defined(CORTEX_M0PLUS) */
+
+/* non-core specific code: */
#ifndef __IM /*!< Fallback for older CMSIS versions */
#define __IM __I
@@ -248,13 +250,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -264,4 +266,4 @@
-#endif //_SYSTEM_D2763_INCLUDED
+#endif /*_SYSTEM_D2763_INCLUDED */
```
</details>
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot commented on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-695954842
<!-- style-bot -->
## Style check summary
### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
#### hw/mcu/dialog/cmac/include/mcu/mcu.h
<details>
```diff
@@ -35,11 +35,13 @@
#define MCU_DIAG_MAP(_port, _word, _evt) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
+ (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
#define MCU_DIAG_MAP_BIT(_port, _word, _evt, _bit) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
+ ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
/* Output diagnostic setial message */
#ifndef MCU_DIAG_SER_DISABLE
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_sleep.c
<details>
```diff
@@ -119,8 +119,8 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory");
}
@@ -135,8 +135,8 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory");
}
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_timer.c
<details>
```diff
@@ -224,10 +224,10 @@
* Compiler barrier to make sure calculations are already done prior to
* this line since code below has strict time constraints.
*/
- asm volatile(""
- :
- :"r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
- : "memory");
+ asm volatile (""
+ :
+ : "r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
+ : "memory");
/*
* Normally we should only wait for next 1MHz tick but since prior to
```
</details>
#### hw/mcu/dialog/cmac/src/hal_system.c
<details>
```diff
@@ -37,12 +37,14 @@
__disable_irq();
if (hal_debugger_connected()) {
- asm("bkpt");
+ asm ("bkpt");
}
CMAC->CM_EXC_STAT_REG = CMAC_CM_EXC_STAT_REG_EXC_FW_ERROR_Msk;
- for (;;);
+ for (;;) {
+ ;
+ }
}
int
```
</details>
#### hw/mcu/dialog/cmac/src/system_cmac.c
<details>
```diff
@@ -37,7 +37,9 @@
#if MYNEWT_VAL(MCU_DEBUG_SWD_WAIT_FOR_ATTACH)
while (!hal_debugger_connected());
- for (int i = 0; i < 1000000; i++);
+ for (int i = 0; i < 1000000; i++) {
+ ;
+ }
#endif
CMAC->CM_CTRL_REG &= ~CMAC_CM_CTRL_REG_CM_BS_RESET_N_Msk;
```
</details>
#### hw/mcu/dialog/include/CMAC.h
<details>
```diff
@@ -35,13 +35,13 @@
/** @addtogroup Dialog
- * @{
- */
+ * @{
+ */
/** @addtogroup D2763x
- * @{
- */
+ * @{
+ */
#ifndef D2763X_H
@@ -71,13 +71,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -91,8 +91,8 @@
#endif /*CMSIS_STRIP_HEADER*/
/** @addtogroup Device_Peripheral_peripherals
- * @{
- */
+ * @{
+ */
@@ -102,162 +102,162 @@
/**
- * @brief CMAC registers (CMAC)
- */
+ * @brief CMAC registers (CMAC)
+ */
typedef struct { /*!< (@ 0x40000000) CMAC Structure */
- __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
- __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
- __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
- __I uint32_t RESERVED;
- __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
- __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
- __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
- __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
- __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
- __I uint32_t RESERVED1[23];
- __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
- __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
- __I uint32_t RESERVED2[30];
- __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
- __I uint32_t RESERVED3[3];
- __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
- __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
- __I uint32_t RESERVED4[2];
- __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
- __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
- __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
- __I uint32_t RESERVED5[53];
- __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
- __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
- __I uint32_t RESERVED6[2];
- __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
- __I uint32_t RESERVED7[3];
- __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
- __I uint32_t RESERVED8[3];
- __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
- __I uint32_t RESERVED9[51];
- __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
- __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
- __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
- __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
- __I uint32_t RESERVED10[8];
- __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
- __I uint32_t RESERVED11[2];
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
- __I uint32_t RESERVED12[294];
- __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
- __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
- __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
- __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
- __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
- __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
- __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
- __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
- __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
- __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
- __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
- __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
- __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
- __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
- __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
- __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
- __I uint32_t RESERVED13[16];
- __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
- __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
- __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
- __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
- __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
- __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
- __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
- __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
- __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
- __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
- __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
- __I uint32_t RESERVED14[17];
- __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
- __I uint32_t RESERVED15[3];
- __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
- __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
- __I uint32_t RESERVED16[446];
- __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
- __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
- __I uint32_t RESERVED17[2];
- __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
- __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
- __I uint32_t RESERVED18[2];
- __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
- __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
- __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
- __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
- __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
- __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
- __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
- __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
- __I uint32_t RESERVED19[48];
- __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
- __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
- __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
- __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
- __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
- __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
- __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
- __I uint32_t RESERVED20[949];
- __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
- __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
- __I uint32_t RESERVED21[62];
- __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
- __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
- __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
- __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
+ __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
+ __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
+ __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
+ __I uint32_t RESERVED;
+ __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
+ __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
+ __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
+ __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
+ __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
+ __I uint32_t RESERVED1[23];
+ __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
+ __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
+ __I uint32_t RESERVED2[30];
+ __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
+ __I uint32_t RESERVED3[3];
+ __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
+ __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
+ __I uint32_t RESERVED4[2];
+ __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
+ __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
+ __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
+ __I uint32_t RESERVED5[53];
+ __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
+ __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
+ __I uint32_t RESERVED6[2];
+ __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
+ __I uint32_t RESERVED7[3];
+ __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
+ __I uint32_t RESERVED8[3];
+ __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
+ __I uint32_t RESERVED9[51];
+ __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
+ __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
+ __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
+ __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
+ __I uint32_t RESERVED10[8];
+ __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
+ __I uint32_t RESERVED11[2];
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
+ __I uint32_t RESERVED12[294];
+ __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
+ __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
+ __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
+ __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
+ __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
+ __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
+ __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
+ __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
+ __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
+ __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
+ __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
+ __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
+ __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
+ __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
+ __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
+ __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
+ __I uint32_t RESERVED13[16];
+ __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
+ __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
+ __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
+ __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
+ __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
+ __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
+ __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
+ __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
+ __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
+ __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
+ __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
+ __I uint32_t RESERVED14[17];
+ __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
+ __I uint32_t RESERVED15[3];
+ __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
+ __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
+ __I uint32_t RESERVED16[446];
+ __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
+ __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
+ __I uint32_t RESERVED17[2];
+ __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
+ __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
+ __I uint32_t RESERVED18[2];
+ __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
+ __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
+ __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
+ __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
+ __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
+ __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
+ __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
+ __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
+ __I uint32_t RESERVED19[48];
+ __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
+ __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
+ __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
+ __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
+ __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
+ __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
+ __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
+ __I uint32_t RESERVED20[949];
+ __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
+ __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
+ __I uint32_t RESERVED21[62];
+ __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
+ __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
+ __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
+ __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
} CMAC_Type; /*!< Size = 4396 (0x112c) */
typedef struct { /*!< (@ 0x50010400) CMAC_TIMER_SLP Structure */
- __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
- __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
- __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
+ __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
+ __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
+ __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
} CMAC_TIMER_SLP_Type;
typedef struct { /*!< (@ 0x50000200) PDC Structure */
- __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
- __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
- __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
- __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
- __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
- __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
- __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
- __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
- __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
- __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
- __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
- __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
- __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
- __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
- __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
- __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
- __IM uint32_t RESERVED[16];
- __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
- __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
- __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
- __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
+ __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
+ __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
+ __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
+ __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
+ __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
+ __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
+ __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
+ __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
+ __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
+ __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
+ __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
+ __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
+ __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
+ __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
+ __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
+ __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
+ __IM uint32_t RESERVED[16];
+ __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
+ __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
+ __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
+ __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
} PDC_Type; /*!< Size = 152 (0x98) */
@@ -270,8 +270,8 @@
/** @addtogroup Device_Peripheral_peripheralAddr
- * @{
- */
+ * @{
+ */
#define CMAC_BASE 0x40000000UL
#define CMAC_TIMER_SLP_BASE 0x50010400UL
@@ -286,12 +286,12 @@
/** @addtogroup Device_Peripheral_declaration
- * @{
- */
-
-#define CMAC ((CMAC_Type*) CMAC_BASE)
+ * @{
+ */
+
+#define CMAC ((CMAC_Type *) CMAC_BASE)
#define CMAC_TIMER_SLP ((CMAC_TIMER_SLP_Type *) CMAC_TIMER_SLP_BASE)
-#define PDC ((PDC_Type*) PDC_BASE)
+#define PDC ((PDC_Type *) PDC_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
@@ -300,17 +300,17 @@
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
- /* leave anonymous unions enabled */
+/* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#endif
@@ -320,8 +320,8 @@
/** @addtogroup PosMask_peripherals
- * @{
- */
+ * @{
+ */
```
</details>
#### hw/mcu/dialog/include/system_CMAC.h
<details>
```diff
@@ -28,7 +28,7 @@
#ifndef _SYSTEM_D2763_INCLUDED
#define _SYSTEM_D2763_INCLUDED
-// From datasheet.h:
+/* From datasheet.h: */
/*--GPIO PID functions-------------------------------------------------------------------------*/
#define FUNC_GPIO (0)
@@ -98,73 +98,73 @@
#define DIR_PULLDOWN 0x200
#define DIR_OUTPUT 0x300
-// code copied from global_functions.h
+/* code copied from global_functions.h */
#if defined(CORTEX_M33)
typedef enum {
/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */
- Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
- BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
- UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
- SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
- PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
- SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* ========================================== DA1469x Specific Interrupt Numbers =========================================== */
- SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
- DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
- CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
- CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
- CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
- UART_IRQn = 5, /*!< 5 UART interrupt request. */
- UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
- UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
- I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
- I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
- SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
- SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
- RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
- RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
- RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
- USB_IRQn = 15, /*!< 15 USB interrupt request. */
- TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
- TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
- RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
- KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
- PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
- VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
- MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
- DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
- TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
- DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
- XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
- GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
- SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
- CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
- CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
- RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
- RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
- PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
- TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
- TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
- LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
- RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
- GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
- GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
- SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
- RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
- RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
- RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
- RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
- RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
- RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
- RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
+ SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
+ DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
+ CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
+ CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
+ CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
+ UART_IRQn = 5, /*!< 5 UART interrupt request. */
+ UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
+ UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
+ I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
+ I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
+ SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
+ SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
+ RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
+ RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
+ RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
+ USB_IRQn = 15, /*!< 15 USB interrupt request. */
+ TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
+ TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
+ RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
+ KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
+ PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
+ VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
+ MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
+ DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
+ TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
+ DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
+ XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
+ GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
+ SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
+ CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
+ CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
+ RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
+ RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
+ PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
+ TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
+ TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
+ LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
+ RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
+ GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
+ GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
+ SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
+ RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
+ RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
+ RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
+ RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
+ RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
+ RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
+ RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
} IRQn_Type;
@@ -184,45 +184,47 @@
#include "cmsis_mtb.h"
#endif
-#else // if defined(CORTEX_M0PLUS)
+#else /* if defined(CORTEX_M0PLUS) */
typedef enum IRQn {
/****** Cortex-M0 Processor Exceptions Numbers *****************************************/
-NMI_IRQn = -14, /* 2 Non Maskable Interrupt. */
-HardFault_IRQn = -13, /* 3 Cortex-M0 Hard Fault Interrupt. */
-SVCall_IRQn = -5, /* 11 Cortex-M0 SV Call Interrupt. */
-PendSV_IRQn = -2, /* 14 Cortex-M0 Pend SV Interrupt. */
-SysTick_IRQn = -1, /* 15 Cortex-M0 System Tick Interrupt. */
+ NMI_IRQn = -14,/* 2 Non Maskable Interrupt. */
+ HardFault_IRQn = -13,/* 3 Cortex-M0 Hard Fault Interrupt. */
+ SVCall_IRQn = -5,/* 11 Cortex-M0 SV Call Interrupt. */
+ PendSV_IRQn = -2,/* 14 Cortex-M0 Pend SV Interrupt. */
+ SysTick_IRQn = -1,/* 15 Cortex-M0 System Tick Interrupt. */
/****** CMAC CM0P Specific Interrupt Numbers *******************************************/
-FIELD_IRQn = 0,
-CALLBACK_IRQn = 1,
-FRAME_IRQn = 2,
-DIAG_IRQn = 3,
-HW_GEN_IRQn = 4,
-SW_MAC_IRQn = 5,
-LL_TIMER2PRMTV_IRQn = 6,
-LL_TIMER2LLC_IRQn = 7,
-CRYPTO_IRQn = 8,
-SW_LLC_1_IRQn = 9,
-SW_LLC_2_IRQn = 10,
-SW_LLC_3_IRQn = 11,
-SYS2CMAC_IRQn = 12
+ FIELD_IRQn = 0,
+ CALLBACK_IRQn = 1,
+ FRAME_IRQn = 2,
+ DIAG_IRQn = 3,
+ HW_GEN_IRQn = 4,
+ SW_MAC_IRQn = 5,
+ LL_TIMER2PRMTV_IRQn = 6,
+ LL_TIMER2LLC_IRQn = 7,
+ CRYPTO_IRQn = 8,
+ SW_LLC_1_IRQn = 9,
+ SW_LLC_2_IRQn = 10,
+ SW_LLC_3_IRQn = 11,
+ SYS2CMAC_IRQn = 12
} IRQn_Type;
/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
#define __CM0_REV 0x0000 /*!< Core Revision r2p1 */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-//#define __MPU_PRESENT 1 /*!< MPU present or not */
-//#define __VTOR_PRESENT 1 /*!< Cortex-M0+ can support the VTOR */
+/*
+ #define __MPU_PRESENT 1 / *!< MPU present or not * /
+ #define __VTOR_PRESENT 1 / *!< Cortex-M0+ can support the VTOR * /
+ */
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
-//#include "system_CMSDK_CM0plus.h" /* CMSDK_CM0plus System include file */
-
-
-#endif // if defined(CORTEX_M0PLUS)
-
-// non-core specific code:
+/*#include "system_CMSDK_CM0plus.h" / * CMSDK_CM0plus System include file * / */
+
+
+#endif /* if defined(CORTEX_M0PLUS) */
+
+/* non-core specific code: */
#ifndef __IM /*!< Fallback for older CMSIS versions */
#define __IM __I
@@ -248,13 +250,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -264,4 +266,4 @@
-#endif //_SYSTEM_D2763_INCLUDED
+#endif /*_SYSTEM_D2763_INCLUDED */
```
</details>
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] wes3 commented on a change in pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
wes3 commented on a change in pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#discussion_r487420917
##########
File path: hw/bsp/dialog_cmac/dialog_cmac_download.sh
##########
@@ -0,0 +1,35 @@
+#!/bin/bash
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+
+/home/andk/tools/dialog/cli_programmer \
Review comment:
Should this point to this directory structure?
##########
File path: hw/bsp/dialog_cmac/dialog_cmac_download.sh
##########
@@ -0,0 +1,35 @@
+#!/bin/bash
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+
+/home/andk/tools/dialog/cli_programmer \
Review comment:
Should this point to this directory structure?
##########
File path: hw/bsp/dialog_cmac/dialog_cmac_download.sh
##########
@@ -0,0 +1,35 @@
+#!/bin/bash
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+
+/home/andk/tools/dialog/cli_programmer \
Review comment:
Should this point to this directory structure?
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] andrzej-kaczmarek commented on a change in pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
andrzej-kaczmarek commented on a change in pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#discussion_r490857621
##########
File path: hw/mcu/dialog/cmac/src/hal_timer.c
##########
@@ -0,0 +1,214 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdint.h>
+#include "syscfg/syscfg.h"
+#include "mcu/mcu.h"
+#include "mcu/cmac_hal.h"
+#include "mcu/cmac_timer.h"
+#include "hal/hal_timer.h"
+#include "sys/queue.h"
+#include "defs/error.h"
+#include "os/os_arch.h"
+#include "os/util.h"
+
+#define TICKS_GT(_t1, _t2) ((int64_t)((_t1) - (_t2)) > 0)
+#define TICKS_GTE(_t1, _t2) ((int64_t)((_t1) - (_t2)) >= 0)
+#define TICKS_LT(_t1, _t2) ((int64_t)((_t1) - (_t2)) < 0)
+#define TICKS_LTE(_t1, _t2) ((int64_t)((_t1) - (_t2)) <= 0)
+
+static TAILQ_HEAD(hal_timer_qhead, hal_timer) g_hal_timer_queue;
+
+/*
+ * To avoid converting back and forth between uint64_t values returned by
+ * cmac_timer and uint32_t representing hal_timer ticks, we compare cmac_timer
+ * ticks everywhere. For this we need to store expiry value as uint64_t, so we
+ * use bsp_timer (which is not used here since we only have one timer) pointer
+ * to store high word of value.
+ */
+
+static inline uint64_t
+hal_timer_expiry_get(struct hal_timer *timer)
+{
+ uint64_t ret;
+
+ ret = (uint64_t)POINTER_TO_UINT(timer->bsp_timer) << 10;
+ ret |= timer->expiry;
+
+ return ret;
+}
+
+static inline void
+hal_timer_expiry_set(struct hal_timer *timer, uint64_t val)
+{
+ timer->expiry = val & 0x3ff;
+ timer->bsp_timer = UINT_TO_POINTER(val >> 10);
+}
+
+static void
+hal_timer_check_queue(void)
+{
+ os_sr_t sr;
+ struct hal_timer *e;
+ uint64_t ll_timer_val;
+
+ OS_ENTER_CRITICAL(sr);
+
+ while ((e = TAILQ_FIRST(&g_hal_timer_queue)) != NULL) {
+ ll_timer_val = cmac_timer_read64();
+ if (TICKS_GT(hal_timer_expiry_get(e), ll_timer_val)) {
+ break;
+ }
+
+ TAILQ_REMOVE(&g_hal_timer_queue, e, link);
+ e->link.tqe_prev = NULL;
+ e->cb_func(e->cb_arg);
+ }
+
+ if (e != NULL) {
+ cmac_timer_write_eq_hal_timer(hal_timer_expiry_get(e));
+ } else {
+ cmac_timer_disable_eq_hal_timer();
+ }
+
+ OS_EXIT_CRITICAL(sr);
+}
+
+static void
+hal_timer_cmac_timer_cb(void)
+{
+#if MYNEWT_VAL(TIMER_0)
+ hal_timer_check_queue();
+#endif
+}
+
+int
+hal_timer_init(int timer_num, void *cfg)
+{
+ assert(timer_num == 0);
+
+ cmac_timer_int_hal_timer_register(hal_timer_cmac_timer_cb);
+
+ TAILQ_INIT(&g_hal_timer_queue);
+
+ return 0;
+}
+
+int
+hal_timer_config(int timer_num, uint32_t freq_hz)
+{
+ assert(timer_num == 0);
+ assert(freq_hz == 32768);
+
+ return 0;
+}
+
+int
+hal_timer_set_cb(int timer_num, struct hal_timer *timer, hal_timer_cb func,
+ void *arg)
+{
+ assert(timer_num == 0);
+
+ timer->cb_func = func;
+ timer->cb_arg = arg;
+ timer->link.tqe_prev = NULL;
+
+ return 0;
+}
+
+int
+hal_timer_start_at(struct hal_timer *timer, uint32_t tick)
+{
+ struct hal_timer *e;
Review comment:
**E**entry :-)
##########
File path: hw/mcu/dialog/cmac/src/hal_timer.c
##########
@@ -0,0 +1,214 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdint.h>
+#include "syscfg/syscfg.h"
+#include "mcu/mcu.h"
+#include "mcu/cmac_hal.h"
+#include "mcu/cmac_timer.h"
+#include "hal/hal_timer.h"
+#include "sys/queue.h"
+#include "defs/error.h"
+#include "os/os_arch.h"
+#include "os/util.h"
+
+#define TICKS_GT(_t1, _t2) ((int64_t)((_t1) - (_t2)) > 0)
+#define TICKS_GTE(_t1, _t2) ((int64_t)((_t1) - (_t2)) >= 0)
+#define TICKS_LT(_t1, _t2) ((int64_t)((_t1) - (_t2)) < 0)
+#define TICKS_LTE(_t1, _t2) ((int64_t)((_t1) - (_t2)) <= 0)
+
+static TAILQ_HEAD(hal_timer_qhead, hal_timer) g_hal_timer_queue;
+
+/*
+ * To avoid converting back and forth between uint64_t values returned by
+ * cmac_timer and uint32_t representing hal_timer ticks, we compare cmac_timer
+ * ticks everywhere. For this we need to store expiry value as uint64_t, so we
+ * use bsp_timer (which is not used here since we only have one timer) pointer
+ * to store high word of value.
+ */
+
+static inline uint64_t
+hal_timer_expiry_get(struct hal_timer *timer)
+{
+ uint64_t ret;
+
+ ret = (uint64_t)POINTER_TO_UINT(timer->bsp_timer) << 10;
+ ret |= timer->expiry;
+
+ return ret;
+}
+
+static inline void
+hal_timer_expiry_set(struct hal_timer *timer, uint64_t val)
+{
+ timer->expiry = val & 0x3ff;
+ timer->bsp_timer = UINT_TO_POINTER(val >> 10);
+}
+
+static void
+hal_timer_check_queue(void)
+{
+ os_sr_t sr;
+ struct hal_timer *e;
+ uint64_t ll_timer_val;
+
+ OS_ENTER_CRITICAL(sr);
+
+ while ((e = TAILQ_FIRST(&g_hal_timer_queue)) != NULL) {
+ ll_timer_val = cmac_timer_read64();
+ if (TICKS_GT(hal_timer_expiry_get(e), ll_timer_val)) {
+ break;
+ }
+
+ TAILQ_REMOVE(&g_hal_timer_queue, e, link);
+ e->link.tqe_prev = NULL;
+ e->cb_func(e->cb_arg);
+ }
+
+ if (e != NULL) {
+ cmac_timer_write_eq_hal_timer(hal_timer_expiry_get(e));
+ } else {
+ cmac_timer_disable_eq_hal_timer();
+ }
+
+ OS_EXIT_CRITICAL(sr);
+}
+
+static void
+hal_timer_cmac_timer_cb(void)
+{
+#if MYNEWT_VAL(TIMER_0)
+ hal_timer_check_queue();
+#endif
+}
+
+int
+hal_timer_init(int timer_num, void *cfg)
+{
+ assert(timer_num == 0);
+
+ cmac_timer_int_hal_timer_register(hal_timer_cmac_timer_cb);
+
+ TAILQ_INIT(&g_hal_timer_queue);
+
+ return 0;
+}
+
+int
+hal_timer_config(int timer_num, uint32_t freq_hz)
+{
+ assert(timer_num == 0);
+ assert(freq_hz == 32768);
+
+ return 0;
+}
+
+int
+hal_timer_set_cb(int timer_num, struct hal_timer *timer, hal_timer_cb func,
+ void *arg)
+{
+ assert(timer_num == 0);
+
+ timer->cb_func = func;
+ timer->cb_arg = arg;
+ timer->link.tqe_prev = NULL;
+
+ return 0;
+}
+
+int
+hal_timer_start_at(struct hal_timer *timer, uint32_t tick)
+{
+ struct hal_timer *e;
Review comment:
**E**ntry :-)
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] wes3 commented on a change in pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
wes3 commented on a change in pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#discussion_r487420917
##########
File path: hw/bsp/dialog_cmac/dialog_cmac_download.sh
##########
@@ -0,0 +1,35 @@
+#!/bin/bash
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+
+/home/andk/tools/dialog/cli_programmer \
Review comment:
Should this point to this directory structure?
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot removed a comment on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-686343367
<!-- license-bot -->
## RAT Report (2020-09-03 08:37:42)
## New files with unknown licenses
* <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/cmac.ld">hw/mcu/dialog/cmac/cmac.ld</a>
* <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/include/CMAC.h">hw/mcu/dialog/include/CMAC.h</a>
* <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/include/system_CMAC.h">hw/mcu/dialog/include/system_CMAC.h</a>
## 43 new files were excluded from check (.rat-excludes)
<details>
<summary>Detailed analysis</summary>
## New files in this PR
| License | File |
|---------|------|
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/bsp.yml">hw/bsp/dialog_cmac/bsp.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/cmac.ld">hw/bsp/dialog_cmac/cmac.ld</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/dialog_cmac_debug.sh">hw/bsp/dialog_cmac/dialog_cmac_debug.sh</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/dialog_cmac_download.sh">hw/bsp/dialog_cmac/dialog_cmac_download.sh</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/pkg.yml">hw/bsp/dialog_cmac/pkg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/syscfg.yml">hw/bsp/dialog_cmac/syscfg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/include/bsp/bsp.h">hw/bsp/dialog_cmac/include/bsp/bsp.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/src/hal_bsp.c">hw/bsp/dialog_cmac/src/hal_bsp.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/src/sbrk.c">hw/bsp/dialog_cmac/src/sbrk.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/src/arch/cortex_m0_cmac/gcc_startup_cmac.S">hw/bsp/dialog_cmac/src/arch/cortex_m0_cmac/gcc_startup_cmac.S</a> |
| ????? | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/cmac.ld">hw/mcu/dialog/cmac/cmac.ld</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/pkg.yml">hw/mcu/dialog/cmac/pkg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/syscfg.yml">hw/mcu/dialog/cmac/syscfg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch.h">hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch_cmac.h">hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch_cmac.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/cmac_hal.h">hw/mcu/dialog/cmac/include/mcu/cmac_hal.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/cmac_pdc.h">hw/mcu/dialog/cmac/include/mcu/cmac_pdc.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/cmac_periph.h">hw/mcu/dialog/cmac/include/mcu/cmac_periph.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/cmac_timer.h">hw/mcu/dialog/cmac/include/mcu/cmac_timer.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/cortex_m0.h">hw/mcu/dialog/cmac/include/mcu/cortex_m0.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/mcu.h">hw/mcu/dialog/cmac/include/mcu/mcu.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/cmac_isr.c">hw/mcu/dialog/cmac/src/cmac_isr.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/cmac_periph.c">hw/mcu/dialog/cmac/src/cmac_periph.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/cmac_priv.h">hw/mcu/dialog/cmac/src/cmac_priv.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/cmac_sleep.c">hw/mcu/dialog/cmac/src/cmac_sleep.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/cmac_timer.c">hw/mcu/dialog/cmac/src/cmac_timer.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/hal_os_tick.c">hw/mcu/dialog/cmac/src/hal_os_tick.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/hal_system.c">hw/mcu/dialog/cmac/src/hal_system.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/hal_timer.c">hw/mcu/dialog/cmac/src/hal_timer.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/hal_watchdog.c">hw/mcu/dialog/cmac/src/hal_watchdog.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/system_cmac.c">hw/mcu/dialog/cmac/src/system_cmac.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/cmac_sleep.S">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/cmac_sleep.S</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_arm.c">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_arm.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_cmac.c">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_cmac.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_fault.c">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_fault.c</a> |
| ????? | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/include/CMAC.h">hw/mcu/dialog/include/CMAC.h</a> |
| ????? | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/include/system_CMAC.h">hw/mcu/dialog/include/system_CMAC.h</a> |
</details>
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] wes3 commented on a change in pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
wes3 commented on a change in pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#discussion_r487420917
##########
File path: hw/bsp/dialog_cmac/dialog_cmac_download.sh
##########
@@ -0,0 +1,35 @@
+#!/bin/bash
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+
+/home/andk/tools/dialog/cli_programmer \
Review comment:
Should this point to this directory structure?
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot removed a comment on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-695954842
<!-- style-bot -->
## Style check summary
### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
#### hw/mcu/dialog/cmac/include/mcu/mcu.h
<details>
```diff
@@ -35,11 +35,13 @@
#define MCU_DIAG_MAP(_port, _word, _evt) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
+ (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
#define MCU_DIAG_MAP_BIT(_port, _word, _evt, _bit) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
+ ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos)
/* Output diagnostic setial message */
#ifndef MCU_DIAG_SER_DISABLE
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_sleep.c
<details>
```diff
@@ -119,8 +119,8 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory");
}
@@ -135,8 +135,8 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory");
}
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_timer.c
<details>
```diff
@@ -224,10 +224,10 @@
* Compiler barrier to make sure calculations are already done prior to
* this line since code below has strict time constraints.
*/
- asm volatile(""
- :
- :"r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
- : "memory");
+ asm volatile (""
+ :
+ : "r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
+ : "memory");
/*
* Normally we should only wait for next 1MHz tick but since prior to
```
</details>
#### hw/mcu/dialog/cmac/src/hal_system.c
<details>
```diff
@@ -37,12 +37,14 @@
__disable_irq();
if (hal_debugger_connected()) {
- asm("bkpt");
+ asm ("bkpt");
}
CMAC->CM_EXC_STAT_REG = CMAC_CM_EXC_STAT_REG_EXC_FW_ERROR_Msk;
- for (;;);
+ for (;;) {
+ ;
+ }
}
int
```
</details>
#### hw/mcu/dialog/cmac/src/system_cmac.c
<details>
```diff
@@ -37,7 +37,9 @@
#if MYNEWT_VAL(MCU_DEBUG_SWD_WAIT_FOR_ATTACH)
while (!hal_debugger_connected());
- for (int i = 0; i < 1000000; i++);
+ for (int i = 0; i < 1000000; i++) {
+ ;
+ }
#endif
CMAC->CM_CTRL_REG &= ~CMAC_CM_CTRL_REG_CM_BS_RESET_N_Msk;
```
</details>
#### hw/mcu/dialog/include/CMAC.h
<details>
```diff
@@ -35,13 +35,13 @@
/** @addtogroup Dialog
- * @{
- */
+ * @{
+ */
/** @addtogroup D2763x
- * @{
- */
+ * @{
+ */
#ifndef D2763X_H
@@ -71,13 +71,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -91,8 +91,8 @@
#endif /*CMSIS_STRIP_HEADER*/
/** @addtogroup Device_Peripheral_peripherals
- * @{
- */
+ * @{
+ */
@@ -102,162 +102,162 @@
/**
- * @brief CMAC registers (CMAC)
- */
+ * @brief CMAC registers (CMAC)
+ */
typedef struct { /*!< (@ 0x40000000) CMAC Structure */
- __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
- __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
- __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
- __I uint32_t RESERVED;
- __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
- __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
- __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
- __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
- __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
- __I uint32_t RESERVED1[23];
- __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
- __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
- __I uint32_t RESERVED2[30];
- __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
- __I uint32_t RESERVED3[3];
- __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
- __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
- __I uint32_t RESERVED4[2];
- __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
- __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
- __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
- __I uint32_t RESERVED5[53];
- __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
- __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
- __I uint32_t RESERVED6[2];
- __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
- __I uint32_t RESERVED7[3];
- __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
- __I uint32_t RESERVED8[3];
- __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
- __I uint32_t RESERVED9[51];
- __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
- __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
- __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
- __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
- __I uint32_t RESERVED10[8];
- __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
- __I uint32_t RESERVED11[2];
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
- __I uint32_t RESERVED12[294];
- __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
- __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
- __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
- __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
- __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
- __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
- __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
- __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
- __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
- __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
- __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
- __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
- __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
- __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
- __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
- __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
- __I uint32_t RESERVED13[16];
- __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
- __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
- __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
- __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
- __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
- __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
- __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
- __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
- __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
- __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
- __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
- __I uint32_t RESERVED14[17];
- __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
- __I uint32_t RESERVED15[3];
- __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
- __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
- __I uint32_t RESERVED16[446];
- __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
- __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
- __I uint32_t RESERVED17[2];
- __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
- __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
- __I uint32_t RESERVED18[2];
- __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
- __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
- __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
- __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
- __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
- __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
- __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
- __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
- __I uint32_t RESERVED19[48];
- __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
- __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
- __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
- __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
- __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
- __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
- __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
- __I uint32_t RESERVED20[949];
- __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
- __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
- __I uint32_t RESERVED21[62];
- __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
- __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
- __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
- __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
+ __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
+ __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
+ __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
+ __I uint32_t RESERVED;
+ __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
+ __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
+ __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
+ __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
+ __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
+ __I uint32_t RESERVED1[23];
+ __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
+ __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
+ __I uint32_t RESERVED2[30];
+ __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
+ __I uint32_t RESERVED3[3];
+ __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
+ __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
+ __I uint32_t RESERVED4[2];
+ __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
+ __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
+ __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
+ __I uint32_t RESERVED5[53];
+ __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
+ __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
+ __I uint32_t RESERVED6[2];
+ __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
+ __I uint32_t RESERVED7[3];
+ __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
+ __I uint32_t RESERVED8[3];
+ __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
+ __I uint32_t RESERVED9[51];
+ __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
+ __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
+ __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
+ __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
+ __I uint32_t RESERVED10[8];
+ __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
+ __I uint32_t RESERVED11[2];
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
+ __I uint32_t RESERVED12[294];
+ __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
+ __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
+ __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
+ __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
+ __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
+ __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
+ __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
+ __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
+ __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
+ __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
+ __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
+ __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
+ __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
+ __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
+ __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
+ __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
+ __I uint32_t RESERVED13[16];
+ __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
+ __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
+ __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
+ __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
+ __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
+ __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
+ __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
+ __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
+ __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
+ __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
+ __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
+ __I uint32_t RESERVED14[17];
+ __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
+ __I uint32_t RESERVED15[3];
+ __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
+ __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
+ __I uint32_t RESERVED16[446];
+ __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
+ __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
+ __I uint32_t RESERVED17[2];
+ __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
+ __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
+ __I uint32_t RESERVED18[2];
+ __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
+ __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
+ __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
+ __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
+ __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
+ __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
+ __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
+ __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
+ __I uint32_t RESERVED19[48];
+ __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
+ __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
+ __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
+ __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
+ __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
+ __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
+ __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
+ __I uint32_t RESERVED20[949];
+ __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
+ __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
+ __I uint32_t RESERVED21[62];
+ __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
+ __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
+ __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
+ __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
} CMAC_Type; /*!< Size = 4396 (0x112c) */
typedef struct { /*!< (@ 0x50010400) CMAC_TIMER_SLP Structure */
- __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
- __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
- __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
+ __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
+ __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
+ __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
} CMAC_TIMER_SLP_Type;
typedef struct { /*!< (@ 0x50000200) PDC Structure */
- __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
- __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
- __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
- __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
- __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
- __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
- __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
- __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
- __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
- __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
- __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
- __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
- __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
- __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
- __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
- __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
- __IM uint32_t RESERVED[16];
- __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
- __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
- __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
- __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
+ __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
+ __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
+ __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
+ __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
+ __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
+ __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
+ __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
+ __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
+ __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
+ __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
+ __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
+ __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
+ __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
+ __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
+ __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
+ __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
+ __IM uint32_t RESERVED[16];
+ __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
+ __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
+ __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
+ __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
} PDC_Type; /*!< Size = 152 (0x98) */
@@ -270,8 +270,8 @@
/** @addtogroup Device_Peripheral_peripheralAddr
- * @{
- */
+ * @{
+ */
#define CMAC_BASE 0x40000000UL
#define CMAC_TIMER_SLP_BASE 0x50010400UL
@@ -286,12 +286,12 @@
/** @addtogroup Device_Peripheral_declaration
- * @{
- */
-
-#define CMAC ((CMAC_Type*) CMAC_BASE)
+ * @{
+ */
+
+#define CMAC ((CMAC_Type *) CMAC_BASE)
#define CMAC_TIMER_SLP ((CMAC_TIMER_SLP_Type *) CMAC_TIMER_SLP_BASE)
-#define PDC ((PDC_Type*) PDC_BASE)
+#define PDC ((PDC_Type *) PDC_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
@@ -300,17 +300,17 @@
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
- /* leave anonymous unions enabled */
+/* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#endif
@@ -320,8 +320,8 @@
/** @addtogroup PosMask_peripherals
- * @{
- */
+ * @{
+ */
```
</details>
#### hw/mcu/dialog/include/system_CMAC.h
<details>
```diff
@@ -28,7 +28,7 @@
#ifndef _SYSTEM_D2763_INCLUDED
#define _SYSTEM_D2763_INCLUDED
-// From datasheet.h:
+/* From datasheet.h: */
/*--GPIO PID functions-------------------------------------------------------------------------*/
#define FUNC_GPIO (0)
@@ -98,73 +98,73 @@
#define DIR_PULLDOWN 0x200
#define DIR_OUTPUT 0x300
-// code copied from global_functions.h
+/* code copied from global_functions.h */
#if defined(CORTEX_M33)
typedef enum {
/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */
- Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
- BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
- UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
- SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
- PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
- SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* ========================================== DA1469x Specific Interrupt Numbers =========================================== */
- SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
- DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
- CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
- CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
- CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
- UART_IRQn = 5, /*!< 5 UART interrupt request. */
- UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
- UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
- I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
- I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
- SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
- SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
- RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
- RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
- RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
- USB_IRQn = 15, /*!< 15 USB interrupt request. */
- TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
- TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
- RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
- KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
- PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
- VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
- MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
- DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
- TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
- DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
- XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
- GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
- SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
- CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
- CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
- RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
- RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
- PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
- TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
- TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
- LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
- RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
- GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
- GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
- SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
- RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
- RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
- RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
- RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
- RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
- RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
- RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
+ SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
+ DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
+ CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
+ CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
+ CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
+ UART_IRQn = 5, /*!< 5 UART interrupt request. */
+ UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
+ UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
+ I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
+ I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
+ SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
+ SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
+ RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
+ RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
+ RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
+ USB_IRQn = 15, /*!< 15 USB interrupt request. */
+ TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
+ TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
+ RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
+ KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
+ PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
+ VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
+ MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
+ DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
+ TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
+ DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
+ XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
+ GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
+ SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
+ CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
+ CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
+ RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
+ RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
+ PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
+ TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
+ TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
+ LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
+ RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
+ GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
+ GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
+ SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
+ RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
+ RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
+ RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
+ RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
+ RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
+ RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
+ RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
} IRQn_Type;
@@ -184,45 +184,47 @@
#include "cmsis_mtb.h"
#endif
-#else // if defined(CORTEX_M0PLUS)
+#else /* if defined(CORTEX_M0PLUS) */
typedef enum IRQn {
/****** Cortex-M0 Processor Exceptions Numbers *****************************************/
-NMI_IRQn = -14, /* 2 Non Maskable Interrupt. */
-HardFault_IRQn = -13, /* 3 Cortex-M0 Hard Fault Interrupt. */
-SVCall_IRQn = -5, /* 11 Cortex-M0 SV Call Interrupt. */
-PendSV_IRQn = -2, /* 14 Cortex-M0 Pend SV Interrupt. */
-SysTick_IRQn = -1, /* 15 Cortex-M0 System Tick Interrupt. */
+ NMI_IRQn = -14,/* 2 Non Maskable Interrupt. */
+ HardFault_IRQn = -13,/* 3 Cortex-M0 Hard Fault Interrupt. */
+ SVCall_IRQn = -5,/* 11 Cortex-M0 SV Call Interrupt. */
+ PendSV_IRQn = -2,/* 14 Cortex-M0 Pend SV Interrupt. */
+ SysTick_IRQn = -1,/* 15 Cortex-M0 System Tick Interrupt. */
/****** CMAC CM0P Specific Interrupt Numbers *******************************************/
-FIELD_IRQn = 0,
-CALLBACK_IRQn = 1,
-FRAME_IRQn = 2,
-DIAG_IRQn = 3,
-HW_GEN_IRQn = 4,
-SW_MAC_IRQn = 5,
-LL_TIMER2PRMTV_IRQn = 6,
-LL_TIMER2LLC_IRQn = 7,
-CRYPTO_IRQn = 8,
-SW_LLC_1_IRQn = 9,
-SW_LLC_2_IRQn = 10,
-SW_LLC_3_IRQn = 11,
-SYS2CMAC_IRQn = 12
+ FIELD_IRQn = 0,
+ CALLBACK_IRQn = 1,
+ FRAME_IRQn = 2,
+ DIAG_IRQn = 3,
+ HW_GEN_IRQn = 4,
+ SW_MAC_IRQn = 5,
+ LL_TIMER2PRMTV_IRQn = 6,
+ LL_TIMER2LLC_IRQn = 7,
+ CRYPTO_IRQn = 8,
+ SW_LLC_1_IRQn = 9,
+ SW_LLC_2_IRQn = 10,
+ SW_LLC_3_IRQn = 11,
+ SYS2CMAC_IRQn = 12
} IRQn_Type;
/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
#define __CM0_REV 0x0000 /*!< Core Revision r2p1 */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-//#define __MPU_PRESENT 1 /*!< MPU present or not */
-//#define __VTOR_PRESENT 1 /*!< Cortex-M0+ can support the VTOR */
+/*
+ #define __MPU_PRESENT 1 / *!< MPU present or not * /
+ #define __VTOR_PRESENT 1 / *!< Cortex-M0+ can support the VTOR * /
+ */
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
-//#include "system_CMSDK_CM0plus.h" /* CMSDK_CM0plus System include file */
-
-
-#endif // if defined(CORTEX_M0PLUS)
-
-// non-core specific code:
+/*#include "system_CMSDK_CM0plus.h" / * CMSDK_CM0plus System include file * / */
+
+
+#endif /* if defined(CORTEX_M0PLUS) */
+
+/* non-core specific code: */
#ifndef __IM /*!< Fallback for older CMSIS versions */
#define __IM __I
@@ -248,13 +250,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -264,4 +266,4 @@
-#endif //_SYSTEM_D2763_INCLUDED
+#endif /*_SYSTEM_D2763_INCLUDED */
```
</details>
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] apache-mynewt-bot commented on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot commented on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-686441666
<!-- license-bot -->
## RAT Report (2020-09-03 12:01:29)
## New files with unknown licenses
* <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/cmac.ld">hw/mcu/dialog/cmac/cmac.ld</a>
* <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/include/CMAC.h">hw/mcu/dialog/include/CMAC.h</a>
* <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/include/system_CMAC.h">hw/mcu/dialog/include/system_CMAC.h</a>
## 43 new files were excluded from check (.rat-excludes)
<details>
<summary>Detailed analysis</summary>
## New files in this PR
| License | File |
|---------|------|
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/bsp.yml">hw/bsp/dialog_cmac/bsp.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/cmac.ld">hw/bsp/dialog_cmac/cmac.ld</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/dialog_cmac_debug.sh">hw/bsp/dialog_cmac/dialog_cmac_debug.sh</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/dialog_cmac_download.sh">hw/bsp/dialog_cmac/dialog_cmac_download.sh</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/pkg.yml">hw/bsp/dialog_cmac/pkg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/syscfg.yml">hw/bsp/dialog_cmac/syscfg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/include/bsp/bsp.h">hw/bsp/dialog_cmac/include/bsp/bsp.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/src/hal_bsp.c">hw/bsp/dialog_cmac/src/hal_bsp.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/src/sbrk.c">hw/bsp/dialog_cmac/src/sbrk.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/bsp/dialog_cmac/src/arch/cortex_m0_cmac/gcc_startup_cmac.S">hw/bsp/dialog_cmac/src/arch/cortex_m0_cmac/gcc_startup_cmac.S</a> |
| ????? | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/cmac.ld">hw/mcu/dialog/cmac/cmac.ld</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/pkg.yml">hw/mcu/dialog/cmac/pkg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/syscfg.yml">hw/mcu/dialog/cmac/syscfg.yml</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch.h">hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch_cmac.h">hw/mcu/dialog/cmac/include/cmac/arch/cortex_m0_cmac/os/os_arch_cmac.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/cmac_hal.h">hw/mcu/dialog/cmac/include/mcu/cmac_hal.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/cmac_pdc.h">hw/mcu/dialog/cmac/include/mcu/cmac_pdc.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/cmac_periph.h">hw/mcu/dialog/cmac/include/mcu/cmac_periph.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/cmac_timer.h">hw/mcu/dialog/cmac/include/mcu/cmac_timer.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/cortex_m0.h">hw/mcu/dialog/cmac/include/mcu/cortex_m0.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/include/mcu/mcu.h">hw/mcu/dialog/cmac/include/mcu/mcu.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/cmac_isr.c">hw/mcu/dialog/cmac/src/cmac_isr.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/cmac_periph.c">hw/mcu/dialog/cmac/src/cmac_periph.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/cmac_priv.h">hw/mcu/dialog/cmac/src/cmac_priv.h</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/cmac_sleep.c">hw/mcu/dialog/cmac/src/cmac_sleep.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/cmac_timer.c">hw/mcu/dialog/cmac/src/cmac_timer.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/hal_os_tick.c">hw/mcu/dialog/cmac/src/hal_os_tick.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/hal_system.c">hw/mcu/dialog/cmac/src/hal_system.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/hal_timer.c">hw/mcu/dialog/cmac/src/hal_timer.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/hal_watchdog.c">hw/mcu/dialog/cmac/src/hal_watchdog.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/system_cmac.c">hw/mcu/dialog/cmac/src/system_cmac.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/cmac_sleep.S">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/cmac_sleep.S</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_arm.c">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_arm.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_cmac.c">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_arch_cmac.c</a> |
| AL | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_fault.c">hw/mcu/dialog/cmac/src/arch/cortex_m0_cmac/os_fault.c</a> |
| ????? | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/include/CMAC.h">hw/mcu/dialog/include/CMAC.h</a> |
| ????? | <a href="https://github.com/apache/mynewt-core/blob/d7a14a7b93ddc64eded09f739074923460bfbe53/hw/mcu/dialog/include/system_CMAC.h">hw/mcu/dialog/include/system_CMAC.h</a> |
</details>
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] apache-mynewt-bot removed a comment on pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
apache-mynewt-bot removed a comment on pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-686441790
<!-- style-bot -->
## Style check summary
### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md)
#### hw/bsp/dialog_cmac/include/bsp/bsp.h
<details>
```diff
@@ -26,17 +26,19 @@
extern "C" {
#endif
-///* Define special stackos sections */
-//#define sec_data_core __attribute__((section(".data.core")))
-//#define sec_bss_core __attribute__((section(".bss.core")))
-//#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
-//
-///* More convenient section placement macros. */
-//#define bssnz_t sec_bss_nz_core
-//
-//extern uint8_t _ram_start;
-//#define RAM_SIZE 0x80000
-//
+/*
+ / * Define special stackos sections * /
+ #define sec_data_core __attribute__((section(".data.core")))
+ #define sec_bss_core __attribute__((section(".bss.core")))
+ #define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+ / * More convenient section placement macros. * /
+ #define bssnz_t sec_bss_nz_core
+
+ extern uint8_t _ram_start;
+ #define RAM_SIZE 0x80000
+
+ */
#define LED_BLINK_PIN 0
```
</details>
#### hw/bsp/dialog_cmac/src/sbrk.c
<details>
```diff
@@ -23,7 +23,8 @@
static char *brk __attribute__ ((section (".data")));
void
-_sbrkInit(char *base, char *limit) {
+_sbrkInit(char *base, char *limit)
+{
sbrkBase = base;
sbrkLimit = limit;
brk = base;
```
</details>
#### hw/mcu/dialog/cmac/include/mcu/mcu.h
<details>
```diff
@@ -35,11 +35,13 @@
#define MCU_DIAG_MAP(_port, _word, _evt) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos);
+ (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos);
#define MCU_DIAG_MAP_BIT(_port, _word, _evt, _bit) \
CMAC->CM_DIAG_PORT ## _port ## _REG = \
(_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \
- ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos);
+ ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << \
+ CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos);
/* Output diagnostic setial message */
#ifndef MCU_DIAG_SER_DISABLE
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_sleep.c
<details>
```diff
@@ -119,10 +119,10 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory"
- );
+ );
}
static void
@@ -136,10 +136,10 @@
" bne 1b \n"
:
: [reg] "l" (retained_regs),
- [val] "l" (g_retained_regs_val),
- [idx] "l" (sizeof(retained_regs))
+ [val] "l" (g_retained_regs_val),
+ [idx] "l" (sizeof(retained_regs))
: "r3", "r4", "memory"
- );
+ );
}
static void
```
</details>
#### hw/mcu/dialog/cmac/src/cmac_timer.c
<details>
```diff
@@ -37,8 +37,8 @@
#define SYNC_TICK_TICKS_PER_VAL_INTERVAL ((SYNC_TICK_VAL_INTERVAL) / 1000000 * 128)
#define COMP_TICK_HAS_PASSED(_num) \
- (CMAC->CM_EV_LATCHED_REG & \
- (CMAC_CM_EV_LATCHED_REG_EV1C_CLK_1US_X1_Msk << ((_num) - 1)))
+ (CMAC->CM_EV_LATCHED_REG & \
+ (CMAC_CM_EV_LATCHED_REG_EV1C_CLK_1US_X1_Msk << ((_num) - 1)))
struct cmac_timer_slp {
uint32_t freq;
@@ -87,7 +87,7 @@
__WFE();
__WFE();
- CMAC->CM_CTRL2_REG = reg;
+ CMAC->CM_CTRL2_REG = reg;
}
static inline void
@@ -102,7 +102,7 @@
__WFE();
__WFE();
- CMAC->CM_CTRL2_REG = reg;
+ CMAC->CM_CTRL2_REG = reg;
}
static void
@@ -186,7 +186,8 @@
slept_ns_rem = slept_ns % 1000;
- clk_freq_mhz_d2m1 = (CMAC->CM_CTRL_REG & CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Msk) >> CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Pos;
+ clk_freq_mhz_d2m1 = (CMAC->CM_CTRL_REG & CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Msk) >>
+ CMAC_CM_CTRL_REG_CM_CLK_FREQ_MHZ_D2M1_Pos;
clk_freq_mhz = 2 * (clk_freq_mhz_d2m1 + 1);
comp_timer = slept_ns_rem * clk_freq_mhz / 1000;
@@ -222,10 +223,10 @@
* Compiler barrier to make sure calculations are already done prior to
* this line since code below has strict time constraints.
*/
- asm volatile(""
- :
- :"r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
- : "memory");
+ asm volatile (""
+ :
+ : "r" (comp_ll_timer_36), "r" (comp_ll_timer_09)
+ : "memory");
/*
* Normally we should only wait for next 1MHz tick but since prior to
@@ -438,11 +439,13 @@
#endif
/* XXX uncomment if any of these comparators are used */
-// if (mask & (CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_0_SEL_Msk |
-// CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_X_SEL_Msk |
-// CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_Y_SEL_Msk)) {
-// return 0;
-// }
+/*
+ if (mask & (CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_0_SEL_Msk |
+ CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_X_SEL_Msk |
+ CMAC_CM_LL_INT_MSK_SET_REG_LL_TIMER1_9_0_EQ_Y_SEL_Msk)) {
+ return 0;
+ }
+ */
val32 = cmac_timer_read32();
```
</details>
#### hw/mcu/dialog/cmac/src/hal_os_tick.c
<details>
```diff
@@ -41,7 +41,7 @@
next = g_os_tick_last + delta;
if (g_os_tick_next == next) {
/* Don't waste time calculating the same llt_val again */
- llt_val = g_os_tick_next_val ;
+ llt_val = g_os_tick_next_val;
} else {
/* Round up to next high part ll_timer value */
llt_val = cmac_timer_convert_tck2llt(next);
```
</details>
#### hw/mcu/dialog/cmac/src/hal_system.c
<details>
```diff
@@ -37,12 +37,14 @@
__disable_irq();
if (hal_debugger_connected()) {
- asm("bkpt");
+ asm ("bkpt");
}
CMAC->CM_EXC_STAT_REG = CMAC_CM_EXC_STAT_REG_EXC_FW_ERROR_Msk;
- for (;;);
+ for (;;) {
+ ;
+ }
}
int
```
</details>
#### hw/mcu/dialog/cmac/src/system_cmac.c
<details>
```diff
@@ -28,7 +28,8 @@
#include "cmac_driver/cmac_diag.h"
#include "CMAC.h"
-void SystemInit(void)
+void
+SystemInit(void)
{
#if MYNEWT_VAL(CMAC_DEBUG_DIAG_ENABLE)
cmac_diag_setup_cmac();
@@ -36,7 +37,9 @@
#if MYNEWT_VAL(MCU_DEBUG_SWD_WAIT_FOR_ATTACH)
while (!hal_debugger_connected());
- for (int i = 0; i < 1000000; i++);
+ for (int i = 0; i < 1000000; i++) {
+ ;
+ }
#endif
CMAC->CM_CTRL_REG &= ~CMAC_CM_CTRL_REG_CM_BS_RESET_N_Msk;
```
</details>
#### hw/mcu/dialog/include/CMAC.h
<details>
```diff
@@ -14,13 +14,13 @@
/** @addtogroup Dialog
- * @{
- */
+ * @{
+ */
/** @addtogroup D2763x
- * @{
- */
+ * @{
+ */
#ifndef D2763X_H
@@ -50,13 +50,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -70,8 +70,8 @@
#endif /*CMSIS_STRIP_HEADER*/
/** @addtogroup Device_Peripheral_peripherals
- * @{
- */
+ * @{
+ */
@@ -81,162 +81,162 @@
/**
- * @brief CMAC registers (CMAC)
- */
+ * @brief CMAC registers (CMAC)
+ */
typedef struct { /*!< (@ 0x40000000) CMAC Structure */
- __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
- __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
- __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
- __I uint32_t RESERVED;
- __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
- __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
- __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
- __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
- __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
- __I uint32_t RESERVED1[23];
- __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
- __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
- __I uint32_t RESERVED2[30];
- __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
- __I uint32_t RESERVED3[3];
- __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
- __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
- __I uint32_t RESERVED4[2];
- __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
- __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
- __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
- __I uint32_t RESERVED5[53];
- __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
- __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
- __I uint32_t RESERVED6[2];
- __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
- __I uint32_t RESERVED7[3];
- __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
- __I uint32_t RESERVED8[3];
- __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
- __I uint32_t RESERVED9[51];
- __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
- __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
- __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
- __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
- __I uint32_t RESERVED10[8];
- __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
- __I uint32_t RESERVED11[2];
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
- __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
- __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
- __I uint32_t RESERVED12[294];
- __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
- __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
- __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
- __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
- __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
- __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
- __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
- __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
- __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
- __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
- __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
- __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
- __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
- __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
- __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
- __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
- __I uint32_t RESERVED13[16];
- __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
- __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
- __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
- __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
- __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
- __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
- __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
- __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
- __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
- __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
- __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
- __I uint32_t RESERVED14[17];
- __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
- __I uint32_t RESERVED15[3];
- __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
- __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
- __I uint32_t RESERVED16[446];
- __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
- __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
- __I uint32_t RESERVED17[2];
- __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
- __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
- __I uint32_t RESERVED18[2];
- __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
- __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
- __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
- __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
- __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
- __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
- __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
- __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
- __I uint32_t RESERVED19[48];
- __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
- __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
- __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
- __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
- __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
- __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
- __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
- __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
- __I uint32_t RESERVED20[949];
- __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
- __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
- __I uint32_t RESERVED21[62];
- __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
- __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
- __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
- __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
+ __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */
+ __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */
+ __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */
+ __I uint32_t RESERVED;
+ __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */
+ __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */
+ __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */
+ __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */
+ __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */
+ __I uint32_t RESERVED1[23];
+ __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */
+ __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */
+ __I uint32_t RESERVED2[30];
+ __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */
+ __I uint32_t RESERVED3[3];
+ __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */
+ __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */
+ __I uint32_t RESERVED4[2];
+ __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */
+ __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */
+ __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */
+ __I uint32_t RESERVED5[53];
+ __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */
+ __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */
+ __I uint32_t RESERVED6[2];
+ __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */
+ __I uint32_t RESERVED7[3];
+ __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */
+ __I uint32_t RESERVED8[3];
+ __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */
+ __I uint32_t RESERVED9[51];
+ __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */
+ __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */
+ __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */
+ __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */
+ __I uint32_t RESERVED10[8];
+ __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */
+ __I uint32_t RESERVED11[2];
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */
+ __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */
+ __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */
+ __I uint32_t RESERVED12[294];
+ __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */
+ __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */
+ __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */
+ __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */
+ __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */
+ __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */
+ __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */
+ __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */
+ __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */
+ __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */
+ __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */
+ __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */
+ __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */
+ __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */
+ __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */
+ __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */
+ __I uint32_t RESERVED13[16];
+ __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */
+ __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */
+ __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */
+ __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */
+ __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */
+ __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */
+ __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */
+ __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */
+ __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */
+ __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */
+ __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */
+ __I uint32_t RESERVED14[17];
+ __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */
+ __I uint32_t RESERVED15[3];
+ __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */
+ __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */
+ __I uint32_t RESERVED16[446];
+ __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */
+ __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */
+ __I uint32_t RESERVED17[2];
+ __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */
+ __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */
+ __I uint32_t RESERVED18[2];
+ __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */
+ __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */
+ __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */
+ __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */
+ __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */
+ __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */
+ __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */
+ __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */
+ __I uint32_t RESERVED19[48];
+ __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */
+ __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */
+ __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */
+ __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */
+ __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */
+ __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */
+ __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */
+ __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */
+ __I uint32_t RESERVED20[949];
+ __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */
+ __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */
+ __I uint32_t RESERVED21[62];
+ __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */
+ __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */
+ __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */
+ __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */
} CMAC_Type; /*!< Size = 4396 (0x112c) */
typedef struct { /*!< (@ 0x50010400) CMAC_TIMER_SLP Structure */
- __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
- __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
- __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
+ __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */
+ __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */
+ __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */
} CMAC_TIMER_SLP_Type;
typedef struct { /*!< (@ 0x50000200) PDC Structure */
- __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
- __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
- __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
- __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
- __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
- __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
- __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
- __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
- __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
- __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
- __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
- __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
- __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
- __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
- __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
- __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
- __IM uint32_t RESERVED[16];
- __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
- __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
- __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
- __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
- __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
+ __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */
+ __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */
+ __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */
+ __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */
+ __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */
+ __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */
+ __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */
+ __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */
+ __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */
+ __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */
+ __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */
+ __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */
+ __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */
+ __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */
+ __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */
+ __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */
+ __IM uint32_t RESERVED[16];
+ __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */
+ __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */
+ __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */
+ __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */
+ __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */
} PDC_Type; /*!< Size = 152 (0x98) */
@@ -249,8 +249,8 @@
/** @addtogroup Device_Peripheral_peripheralAddr
- * @{
- */
+ * @{
+ */
#define CMAC_BASE 0x40000000UL
#define CMAC_TIMER_SLP_BASE 0x50010400UL
@@ -265,12 +265,12 @@
/** @addtogroup Device_Peripheral_declaration
- * @{
- */
-
-#define CMAC ((CMAC_Type*) CMAC_BASE)
+ * @{
+ */
+
+#define CMAC ((CMAC_Type *) CMAC_BASE)
#define CMAC_TIMER_SLP ((CMAC_TIMER_SLP_Type *) CMAC_TIMER_SLP_BASE)
-#define PDC ((PDC_Type*) PDC_BASE)
+#define PDC ((PDC_Type *) PDC_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
@@ -279,17 +279,17 @@
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
- /* leave anonymous unions enabled */
+/* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#endif
@@ -299,8 +299,8 @@
/** @addtogroup PosMask_peripherals
- * @{
- */
+ * @{
+ */
```
</details>
#### hw/mcu/dialog/include/system_CMAC.h
<details>
```diff
@@ -7,7 +7,7 @@
#ifndef _SYSTEM_D2763_INCLUDED
#define _SYSTEM_D2763_INCLUDED
-// From datasheet.h:
+/* From datasheet.h: */
/*--GPIO PID functions-------------------------------------------------------------------------*/
#define FUNC_GPIO (0)
@@ -77,73 +77,73 @@
#define DIR_PULLDOWN 0x200
#define DIR_OUTPUT 0x300
-// code copied from global_functions.h
+/* code copied from global_functions.h */
#if defined(CORTEX_M33)
typedef enum {
/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */
- Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
- BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
- UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
- SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
- PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
- SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* ========================================== DA1469x Specific Interrupt Numbers =========================================== */
- SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
- DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
- CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
- CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
- CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
- UART_IRQn = 5, /*!< 5 UART interrupt request. */
- UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
- UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
- I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
- I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
- SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
- SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
- RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
- RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
- RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
- USB_IRQn = 15, /*!< 15 USB interrupt request. */
- TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
- TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
- RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
- KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
- PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
- VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
- MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
- DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
- TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
- DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
- XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
- GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
- SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
- CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
- CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
- RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
- RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
- PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
- TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
- TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
- LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
- RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
- GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
- GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
- SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
- RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
- RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
- RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
- RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
- RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
- RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
- RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
+ SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */
+ DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */
+ CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */
+ CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */
+ CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */
+ UART_IRQn = 5, /*!< 5 UART interrupt request. */
+ UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */
+ UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */
+ I2C_IRQn = 8, /*!< 8 I2C interrupt request. */
+ I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */
+ SPI_IRQn = 10, /*!< 10 SPI interrupt request. */
+ SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */
+ RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */
+ RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */
+ RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */
+ USB_IRQn = 15, /*!< 15 USB interrupt request. */
+ TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */
+ TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */
+ RTC_IRQn = 18, /*!< 18 RTC interrupt request. */
+ KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */
+ PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */
+ VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */
+ MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */
+ DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */
+ TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */
+ DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */
+ XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */
+ GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */
+ SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */
+ CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */
+ CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */
+ RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */
+ RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */
+ PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */
+ TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */
+ TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */
+ LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */
+ RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */
+ GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */
+ GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */
+ SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */
+ RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */
+ RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */
+ RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */
+ RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */
+ RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */
+ RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */
+ RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */
} IRQn_Type;
@@ -163,45 +163,47 @@
#include "cmsis_mtb.h"
#endif
-#else // if defined(CORTEX_M0PLUS)
+#else /* if defined(CORTEX_M0PLUS) */
typedef enum IRQn {
/****** Cortex-M0 Processor Exceptions Numbers *****************************************/
-NMI_IRQn = -14, /* 2 Non Maskable Interrupt. */
-HardFault_IRQn = -13, /* 3 Cortex-M0 Hard Fault Interrupt. */
-SVCall_IRQn = -5, /* 11 Cortex-M0 SV Call Interrupt. */
-PendSV_IRQn = -2, /* 14 Cortex-M0 Pend SV Interrupt. */
-SysTick_IRQn = -1, /* 15 Cortex-M0 System Tick Interrupt. */
+ NMI_IRQn = -14,/* 2 Non Maskable Interrupt. */
+ HardFault_IRQn = -13,/* 3 Cortex-M0 Hard Fault Interrupt. */
+ SVCall_IRQn = -5,/* 11 Cortex-M0 SV Call Interrupt. */
+ PendSV_IRQn = -2,/* 14 Cortex-M0 Pend SV Interrupt. */
+ SysTick_IRQn = -1,/* 15 Cortex-M0 System Tick Interrupt. */
/****** CMAC CM0P Specific Interrupt Numbers *******************************************/
-FIELD_IRQn = 0,
-CALLBACK_IRQn = 1,
-FRAME_IRQn = 2,
-DIAG_IRQn = 3,
-HW_GEN_IRQn = 4,
-SW_MAC_IRQn = 5,
-LL_TIMER2PRMTV_IRQn = 6,
-LL_TIMER2LLC_IRQn = 7,
-CRYPTO_IRQn = 8,
-SW_LLC_1_IRQn = 9,
-SW_LLC_2_IRQn = 10,
-SW_LLC_3_IRQn = 11,
-SYS2CMAC_IRQn = 12
+ FIELD_IRQn = 0,
+ CALLBACK_IRQn = 1,
+ FRAME_IRQn = 2,
+ DIAG_IRQn = 3,
+ HW_GEN_IRQn = 4,
+ SW_MAC_IRQn = 5,
+ LL_TIMER2PRMTV_IRQn = 6,
+ LL_TIMER2LLC_IRQn = 7,
+ CRYPTO_IRQn = 8,
+ SW_LLC_1_IRQn = 9,
+ SW_LLC_2_IRQn = 10,
+ SW_LLC_3_IRQn = 11,
+ SYS2CMAC_IRQn = 12
} IRQn_Type;
/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
#define __CM0_REV 0x0000 /*!< Core Revision r2p1 */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-//#define __MPU_PRESENT 1 /*!< MPU present or not */
-//#define __VTOR_PRESENT 1 /*!< Cortex-M0+ can support the VTOR */
+/*
+ #define __MPU_PRESENT 1 / *!< MPU present or not * /
+ #define __VTOR_PRESENT 1 / *!< Cortex-M0+ can support the VTOR * /
+ */
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
-//#include "system_CMSDK_CM0plus.h" /* CMSDK_CM0plus System include file */
-
-
-#endif // if defined(CORTEX_M0PLUS)
-
-// non-core specific code:
+/*#include "system_CMSDK_CM0plus.h" / * CMSDK_CM0plus System include file * / */
+
+
+#endif /* if defined(CORTEX_M0PLUS) */
+
+/* non-core specific code: */
#ifndef __IM /*!< Fallback for older CMSIS versions */
#define __IM __I
@@ -227,13 +229,13 @@
#pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
#pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
- /* anonymous unions are enabled by default */
+/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
@@ -243,4 +245,4 @@
-#endif //_SYSTEM_D2763_INCLUDED
+#endif /*_SYSTEM_D2763_INCLUDED */
```
</details>
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [mynewt-core] wes3 commented on a change in pull request #2368: hw: Add MCU and BSP for Dialog CMAC
Posted by GitBox <gi...@apache.org>.
wes3 commented on a change in pull request #2368:
URL: https://github.com/apache/mynewt-core/pull/2368#discussion_r487420917
##########
File path: hw/bsp/dialog_cmac/dialog_cmac_download.sh
##########
@@ -0,0 +1,35 @@
+#!/bin/bash
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+
+/home/andk/tools/dialog/cli_programmer \
Review comment:
Should this point to this directory structure?
##########
File path: hw/bsp/dialog_cmac/dialog_cmac_download.sh
##########
@@ -0,0 +1,35 @@
+#!/bin/bash
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+
+/home/andk/tools/dialog/cli_programmer \
Review comment:
Should this point to this directory structure?
##########
File path: hw/bsp/dialog_cmac/dialog_cmac_download.sh
##########
@@ -0,0 +1,35 @@
+#!/bin/bash
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+
+/home/andk/tools/dialog/cli_programmer \
Review comment:
Should this point to this directory structure?
##########
File path: hw/bsp/dialog_cmac/dialog_cmac_download.sh
##########
@@ -0,0 +1,35 @@
+#!/bin/bash
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+
+/home/andk/tools/dialog/cli_programmer \
Review comment:
Should this point to this directory structure?
##########
File path: hw/bsp/dialog_cmac/dialog_cmac_download.sh
##########
@@ -0,0 +1,35 @@
+#!/bin/bash
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+
+/home/andk/tools/dialog/cli_programmer \
Review comment:
Should this point to this directory structure?
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org