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Posted to commits@nuttx.apache.org by ag...@apache.org on 2020/11/28 11:20:42 UTC
[incubator-nuttx] 04/06: style/code: remove unnecessary trailing
whitespace
This is an automated email from the ASF dual-hosted git repository.
aguettouche pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 32ba1943728e7796251b8b728bbfd5ce38c89629
Author: chao.an <an...@xiaomi.com>
AuthorDate: Sat Nov 28 11:51:54 2020 +0800
style/code: remove unnecessary trailing whitespace
N/A
Signed-off-by: chao.an <an...@xiaomi.com>
---
arch/arm/src/stm32l4/hardware/stm32l4_adc.h | 6 +++---
arch/mips/src/pic32mz/pic32mz_head.S | 6 +++---
arch/x86_64/src/intel64/intel64_head.S | 12 ++++++------
arch/x86_64/src/intel64/intel64_saveusercontext.S | 6 +++---
arch/x86_64/src/intel64/intel64_vectors.S | 2 +-
arch/xtensa/src/common/xtensa_backtrace.S | 2 +-
arch/xtensa/src/esp32/esp32_wtd.c | 2 +-
arch/xtensa/src/esp32/esp32_wtd_lowerhalf.c | 8 ++++----
boards/xtensa/esp32/esp32-core/include/board.h | 2 +-
boards/xtensa/esp32/esp32-core/src/esp32_bringup.c | 2 +-
10 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h
index 5fa3e9a..80aebb2 100644
--- a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h
@@ -269,7 +269,7 @@
#define ADC_CFGR_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */
#define ADC_CFGR_DISCNUM_SHIFT (17) /* Bits 17-19: Discontinuous mode channel count */
#define ADC_CFGR_DISCNUM_MASK (7 << ADC_CFGR_DISCNUM_SHIFT)
-# define ADC_CFGR_DISCNUM(n) (((n) - 1) << ADC_CFGR_DISCNUM_SHIFT)
+# define ADC_CFGR_DISCNUM(n) (((n) - 1) << ADC_CFGR_DISCNUM_SHIFT)
/* n = 1..8 channels */
#define ADC_CFGR_JDISCEN (1 << 20) /* Bit 20: Discontinuous mode on injected channels */
@@ -457,7 +457,7 @@
/* n=1..4 */
#define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */
#define ADC_JSQR_JEXTSEL_MASK (15 << ADC_JSQR_JEXTSEL_SHIFT)
-# define ADC_JSQR_JEXTSEL(event) ((event) << ADC_JSQR_JEXTSEL_SHIFT)
+# define ADC_JSQR_JEXTSEL(event) ((event) << ADC_JSQR_JEXTSEL_SHIFT)
/* Event = 0..15 */
# define ADC_JEXTSEL_T1TRGO ADC_JSQR_JEXTSEL(0) /* 0000 TIM1_TRGO */
# define ADC_JEXTSEL_T1CC4 ADC_JSQR_JEXTSEL(1) /* 0001 TIM1_CH4 */
@@ -577,7 +577,7 @@
# define ADC_CCR_DUAL_ALT (9 << ADC_CCR_DUAL_SHIFT) /* Alternate trigger mode only */
# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */
# define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT)
-# define ADC_CCR_DELAY(n) (((n)-1) << ADC_CCR_DELAY_SHIFT)
+# define ADC_CCR_DELAY(n) (((n)-1) << ADC_CCR_DELAY_SHIFT)
/* n * TADCCLK, 1-13 */
# define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */
# define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */
diff --git a/arch/mips/src/pic32mz/pic32mz_head.S b/arch/mips/src/pic32mz/pic32mz_head.S
index b8f5447..77bac48 100644
--- a/arch/mips/src/pic32mz/pic32mz_head.S
+++ b/arch/mips/src/pic32mz/pic32mz_head.S
@@ -84,13 +84,13 @@
* End(+1): _ebss + CONFIG_IDLETHREAD_STACKSIZE
* 6) Optional interrupt stack
* Start: _ebss + CONFIG_IDLETHREAD_STACKSIZE
- * End(+1): _ebss + CONFIG_IDLETHREAD_STACKSIZE +
+ * End(+1): _ebss + CONFIG_IDLETHREAD_STACKSIZE +
(CONFIG_ARCH_INTERRUPTSTACK & ~3)
* 6a) Heap (without interrupt stack)
* Start: _ebss + CONFIG_IDLETHREAD_STACKSIZE
* End(+1): to the end of memory
* 6b) Heap (with interrupt stack)
- * Start: _ebss + CONFIG_IDLETHREAD_STACKSIZE +
+ * Start: _ebss + CONFIG_IDLETHREAD_STACKSIZE +
(CONFIG_ARCH_INTERRUPTSTACK & ~3)
* End(+1): to the end of memory
*/
@@ -472,7 +472,7 @@ __start:
ehb
la t0, pic32mz_consoleinit
- jalr ra, t0
+ jalr ra, t0
nop
showprogress 'A'
diff --git a/arch/x86_64/src/intel64/intel64_head.S b/arch/x86_64/src/intel64/intel64_head.S
index 3297bc8..d43839e 100644
--- a/arch/x86_64/src/intel64/intel64_head.S
+++ b/arch/x86_64/src/intel64/intel64_head.S
@@ -172,7 +172,7 @@ start32:
// Popluate the lower 4GB as non-present
// for ecx = 0...512 * 4 : Loop and setup the page directories
mov $0x800, %ecx // 512 * 4
-epd_loop:
+epd_loop:
mov %esi, %edx
or $(X86_PAGE_WR | X86_PAGE_PRESENT), %edx
mov %edx, 0(%edi)
@@ -198,7 +198,7 @@ ept_loop:
// for ecx = 0...64 : Loop and setup 64x 2MB page directories
mov $64, %ecx
-pd_loop:
+pd_loop:
mov %eax, 0(%edi)
add $(HUGE_PAGE_SIZE), %eax
add $(X86_PAGE_ENTRY_SIZE), %edi
@@ -221,7 +221,7 @@ pd_loop:
mov %eax, %cr4
// Load the 4 level page table
- // Level 1 and 2 were preset at build time in assembly for this loading
+ // Level 1 and 2 were preset at build time in assembly for this loading
// process
// 4KiB page table is used
// Kernel mapped to 1GB HiMem
@@ -323,7 +323,7 @@ __revoke_low_memory:
// for ecx = 0...64 : Loop and setup 64x 2MB page directories
mov $64, %ecx
-npd_loop:
+npd_loop:
mov %esi, %edx
or $(X86_PAGE_WR | X86_PAGE_PRESENT), %edx
mov %edx, 0(%edi)
@@ -354,12 +354,12 @@ __enable_sse_avx:
mov $(X86_CR0_EM), %rbx
not %rbx
and %rbx, %rax
- or $(X86_CR0_MP), %rax
+ or $(X86_CR0_MP), %rax
mov %rax, %cr0
// Enable Saving XMM context
mov %cr4, %rax
- or $(X86_CR4_OSXFSR | X86_CR4_XMMEXCPT), %rax
+ or $(X86_CR4_OSXFSR | X86_CR4_XMMEXCPT), %rax
mov %rax, %cr4
// Setup MXCSR, masking all SSE precision exception
diff --git a/arch/x86_64/src/intel64/intel64_saveusercontext.S b/arch/x86_64/src/intel64/intel64_saveusercontext.S
index d16e0ef..fd51be0 100644
--- a/arch/x86_64/src/intel64/intel64_saveusercontext.S
+++ b/arch/x86_64/src/intel64/intel64_saveusercontext.S
@@ -74,8 +74,8 @@
* modified upon return from a subroutine call. On a context switch
* back to user mode, it will appear as a return from this function.
*
- * According to the SysV x86_64 ABI, the RAX, RDI, RSI, RDX, RCX, r8 and r9
- * are to be free for use within a procedure or function, and need not
+ * According to the SysV x86_64 ABI, the RAX, RDI, RSI, RDX, RCX, r8 and r9
+ * are to be free for use within a procedure or function, and need not
* be preserved.
*
* On entry,
@@ -87,7 +87,7 @@
.globl up_saveusercontext
.type up_saveusercontext, @function
up_saveusercontext:
-
+
// callee saved regs
movq %rbx, (8*REG_RBX)(%rdi)
movq %r12, (8*REG_R12)(%rdi)
diff --git a/arch/x86_64/src/intel64/intel64_vectors.S b/arch/x86_64/src/intel64/intel64_vectors.S
index f7d703d..c67a715 100644
--- a/arch/x86_64/src/intel64/intel64_vectors.S
+++ b/arch/x86_64/src/intel64/intel64_vectors.S
@@ -268,7 +268,7 @@ isr_common:
/* save xmm registers */
leaq -512(%rsp), %rsp
fxsaveq (%rsp)
-
+
/* The current value of the SP points to the beginning of the state save
* structure. Save that in RDI as the input parameter to isr_handler.
diff --git a/arch/xtensa/src/common/xtensa_backtrace.S b/arch/xtensa/src/common/xtensa_backtrace.S
index f436046..e5204b4 100644
--- a/arch/xtensa/src/common/xtensa_backtrace.S
+++ b/arch/xtensa/src/common/xtensa_backtrace.S
@@ -89,7 +89,7 @@ xtensa_backtrace_start:
/* a2, a3, a4 should be out arguments for i SP, i PC, i-1 PC respectively.
* Use a5 and a6 as scratch.
*/
-
+
l32e a5, sp, -16 /* Get i PC, which is ret addres of i+1 */
s32i a5, a2, 0 /* Store i PC to arg *pc */
l32e a6, sp, -12 /* Get i+1 SP. Used to access i BS */
diff --git a/arch/xtensa/src/esp32/esp32_wtd.c b/arch/xtensa/src/esp32/esp32_wtd.c
index 080bffb..e86c7dd 100644
--- a/arch/xtensa/src/esp32/esp32_wtd.c
+++ b/arch/xtensa/src/esp32/esp32_wtd.c
@@ -26,7 +26,7 @@
#include <nuttx/irq.h>
#include <stdbool.h>
#include "xtensa.h"
-#include "hardware/esp32_tim.h"
+#include "hardware/esp32_tim.h"
#include "hardware/esp32_rtccntl.h"
#include "esp32_wtd.h"
#include "esp32_cpuint.h"
diff --git a/arch/xtensa/src/esp32/esp32_wtd_lowerhalf.c b/arch/xtensa/src/esp32/esp32_wtd_lowerhalf.c
index ca05afa..35ca89e 100644
--- a/arch/xtensa/src/esp32/esp32_wtd_lowerhalf.c
+++ b/arch/xtensa/src/esp32/esp32_wtd_lowerhalf.c
@@ -49,15 +49,15 @@
*/
#define MS_CYCLES_TIMER 2 /* 1 ms/(12.5 ns*PRE_VALUE) */
-#define STAGE_0 0
+#define STAGE_0 0
#define STAGE_1 1
#define STAGE_2 2
-#define STAGE_3 3
+#define STAGE_3 3
#define RESET_SYSTEM_RTC 4 /* Reset Main System + RTC */
-#define RESET_SYSTEM_TIMER 3 /* Reset Main System */
+#define RESET_SYSTEM_TIMER 3 /* Reset Main System */
#define INTERRUPT_ON_TIMEOUT 1
#define STAGES 4
-#define FULL_STAGE 0xffffffff /* ((2^32)-1) */
+#define FULL_STAGE 0xffffffff /* ((2^32)-1) */
#define MAX_MWDT_TIMEOUT_MS 0x7fffffff /* ((2^32)-1)/cycles */
/****************************************************************************
diff --git a/boards/xtensa/esp32/esp32-core/include/board.h b/boards/xtensa/esp32/esp32-core/include/board.h
index ce90452..094eed1 100644
--- a/boards/xtensa/esp32/esp32-core/include/board.h
+++ b/boards/xtensa/esp32/esp32-core/include/board.h
@@ -90,6 +90,6 @@
/* Define how many LEDs this board has (needed by userleds) */
#define BOARD_NLEDS 1
-#define GPIO_LED1 2
+#define GPIO_LED1 2
#endif /* __BOARDS_XTENSA_ESP32_ESP32_CORE_INCLUDE_BOARD_H */
diff --git a/boards/xtensa/esp32/esp32-core/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-core/src/esp32_bringup.c
index 5ba1c71..d3caff8 100644
--- a/boards/xtensa/esp32/esp32-core/src/esp32_bringup.c
+++ b/boards/xtensa/esp32/esp32-core/src/esp32_bringup.c
@@ -175,7 +175,7 @@ int esp32_bringup(void)
#ifdef CONFIG_ESP32_SPIFLASH_ENCRYPTION_TEST
esp32_spiflash_encrypt_test();
-#endif
+#endif
ret = esp32_spiflash_init();
if (ret)