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Posted to commits@nuttx.apache.org by xi...@apache.org on 2024/04/09 02:45:18 UTC
(nuttx) branch master updated: stm32f76xx77xx_rcc: Fix PLLI2S factor divisors
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 67dbdb18e3 stm32f76xx77xx_rcc: Fix PLLI2S factor divisors
67dbdb18e3 is described below
commit 67dbdb18e316259bb3d8d1a291abc77408045486
Author: Alan Carvalho de Assis <ac...@gmail.com>
AuthorDate: Mon Apr 8 17:42:48 2024 -0300
stm32f76xx77xx_rcc: Fix PLLI2S factor divisors
Value was set with PLLSAI factor divisors instead of
PLLI2S factor divisors.
Signed-off-by: Alan C Assis <ac...@gmail.com>
---
arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
index 32f2a62eb6..21024b93cd 100644
--- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
+++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
@@ -913,7 +913,10 @@ static void stm32_stdclockconfig(void)
{
}
#endif
-#if defined(CONFIG_STM32F7_PLLI2S) || (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1))
+
+#if defined(CONFIG_STM32F7_PLLI2S) || \
+ (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \
+ (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1))
/* Configure PLLI2S */
@@ -922,10 +925,10 @@ static void stm32_stdclockconfig(void)
| RCC_PLLI2SCFGR_PLLI2SP_MASK
| RCC_PLLI2SCFGR_PLLI2SQ_MASK
| RCC_PLLI2SCFGR_PLLI2SR_MASK);
- regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
- | STM32_RCC_PLLSAICFGR_PLLSAIP
- | STM32_RCC_PLLSAICFGR_PLLSAIQ
- | STM32_RCC_PLLSAICFGR_PLLSAIR);
+ regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SN
+ | STM32_RCC_PLLI2SCFGR_PLLI2SP
+ | STM32_RCC_PLLI2SCFGR_PLLI2SQ
+ | STM32_RCC_PLLI2SCFGR_PLLI2SR);
putreg32(regval, STM32_RCC_PLLI2SCFGR);
/* Enable PLLI2S */