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Posted to commits@mynewt.apache.org by je...@apache.org on 2019/05/11 07:01:49 UTC
[mynewt-core] branch master updated (1c53275 -> 884de8b)
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git.
from 1c53275 mcu/fe310: Add tickles sleep support
new a44f571 bsp/black_vet6: Reduce size of NFFS flash area
new 884de8b bsp/black_vet6: Add USART2 and USART3
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
hw/bsp/black_vet6/bsp.yml | 2 +-
hw/bsp/black_vet6/include/bsp/bsp.h | 2 +-
hw/bsp/black_vet6/src/hal_bsp.c | 46 +++++++++++++++++++++++++++++++++++++
hw/bsp/black_vet6/syscfg.yml | 40 ++++++++++++++++++++++++++++----
4 files changed, 84 insertions(+), 6 deletions(-)
[mynewt-core] 01/02: bsp/black_vet6: Reduce size of NFFS flash area
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit a44f5711e3afce4555ba39c800080123687fdd53
Author: Jerzy Kasenberg <je...@gmail.com>
AuthorDate: Fri May 10 22:40:52 2019 +0200
bsp/black_vet6: Reduce size of NFFS flash area
This flash area is used by config fcb which does not need
area that big.
---
hw/bsp/black_vet6/bsp.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/bsp/black_vet6/bsp.yml b/hw/bsp/black_vet6/bsp.yml
index 4521bd1..ea06a91 100644
--- a/hw/bsp/black_vet6/bsp.yml
+++ b/hw/bsp/black_vet6/bsp.yml
@@ -62,5 +62,5 @@ bsp.flash_map:
user_id: 1
device: 1
offset: 0x00040000
- size: 256kB
+ size: 32kB
[mynewt-core] 02/02: bsp/black_vet6: Add USART2 and USART3
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 884de8bfbeede730e2e65f3fc521b15448986458
Author: Jerzy Kasenberg <je...@gmail.com>
AuthorDate: Fri May 10 22:48:12 2019 +0200
bsp/black_vet6: Add USART2 and USART3
Board has planty of pins this exposes two additional
UARTs.
It allows to use console and newtmgr over serial.
---
hw/bsp/black_vet6/include/bsp/bsp.h | 2 +-
hw/bsp/black_vet6/src/hal_bsp.c | 46 +++++++++++++++++++++++++++++++++++++
hw/bsp/black_vet6/syscfg.yml | 40 ++++++++++++++++++++++++++++----
3 files changed, 83 insertions(+), 5 deletions(-)
diff --git a/hw/bsp/black_vet6/include/bsp/bsp.h b/hw/bsp/black_vet6/include/bsp/bsp.h
index 11ec3ac..84ec2e9 100644
--- a/hw/bsp/black_vet6/include/bsp/bsp.h
+++ b/hw/bsp/black_vet6/include/bsp/bsp.h
@@ -44,7 +44,7 @@ extern uint8_t _ccram_start;
#define LED_BLINK_PIN MCU_GPIO_PORTA(6)
/* UART */
-#define UART_CNT 1
+#define UART_CNT 3
#define SPI_SS_PIN (4)
#ifdef __cplusplus
diff --git a/hw/bsp/black_vet6/src/hal_bsp.c b/hw/bsp/black_vet6/src/hal_bsp.c
index ea0214b..fd7eca0 100644
--- a/hw/bsp/black_vet6/src/hal_bsp.c
+++ b/hw/bsp/black_vet6/src/hal_bsp.c
@@ -80,6 +80,14 @@ static struct trng_dev os_bsp_trng;
struct uart_dev hal_uart0;
#endif
+#if MYNEWT_VAL(UART_1)
+struct uart_dev hal_uart1;
+#endif
+
+#if MYNEWT_VAL(UART_2)
+struct uart_dev hal_uart2;
+#endif
+
#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE) || \
MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
#include <hal/hal_spi.h>
@@ -332,6 +340,32 @@ static const struct stm32_uart_cfg uart_cfg0 = {
.suc_irqn = USART1_IRQn
};
#endif
+#if MYNEWT_VAL(UART_1)
+static const struct stm32_uart_cfg uart_cfg1 = {
+ .suc_uart = USART2,
+ .suc_rcc_reg = &RCC->APB2ENR,
+ .suc_rcc_dev = RCC_APB1ENR_USART2EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_1_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_1_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_1_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_1_CTS),
+ .suc_pin_af = GPIO_AF7_USART2,
+ .suc_irqn = USART2_IRQn
+};
+#endif
+#if MYNEWT_VAL(UART_2)
+static const struct stm32_uart_cfg uart_cfg2 = {
+ .suc_uart = USART3,
+ .suc_rcc_reg = &RCC->APB2ENR,
+ .suc_rcc_dev = RCC_APB1ENR_USART3EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_2_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_2_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_2_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_2_CTS),
+ .suc_pin_af = GPIO_AF7_USART3,
+ .suc_irqn = USART3_IRQn
+};
+#endif
#if MYNEWT_VAL(ETH_0)
static const struct stm32_eth_cfg eth_cfg = {
/*
@@ -462,6 +496,18 @@ hal_bsp_init(void)
assert(rc == 0);
#endif
+#if MYNEWT_VAL(UART_1)
+ rc = os_dev_create((struct os_dev *) &hal_uart1, "uart1",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart_cfg1);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_2)
+ rc = os_dev_create((struct os_dev *) &hal_uart2, "uart2",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart_cfg2);
+ assert(rc == 0);
+#endif
+
#if MYNEWT_VAL(ADC_1)
rc = os_dev_create((struct os_dev *) &my_dev_adc1, "adc1",
OS_DEV_INIT_KERNEL, OS_DEV_INIT_PRIO_DEFAULT,
diff --git a/hw/bsp/black_vet6/syscfg.yml b/hw/bsp/black_vet6/syscfg.yml
index 9d2e9b9..a2134af 100644
--- a/hw/bsp/black_vet6/syscfg.yml
+++ b/hw/bsp/black_vet6/syscfg.yml
@@ -39,16 +39,48 @@ syscfg.defs:
description: 'Whether to enable UART0'
value: 1
UART_0_TX:
- description: 'UART 0 TX pin. TX from J6 connector'
+ description: 'USART1 TX pin. TX from J6 connector'
value: 'MCU_GPIO_PORTA(9)'
UART_0_RX:
- description: 'UART 0 RX pin. RX from J6 connector'
+ description: 'USART1 RX pin. RX from J6 connector'
value: 'MCU_GPIO_PORTA(10)'
UART_0_RTS:
- description: 'UART 0 RTS pin.'
+ description: 'USART1 RTS pin.'
value: -1
UART_0_CTS:
- description: 'UART 0 CTS pin.'
+ description: 'USART1 CTS pin.'
+ value: -1
+
+ UART_1:
+ description: 'Whether to enable UART0'
+ value: 1
+ UART_1_TX:
+ description: 'USART2 TX pin. PA2, PD5'
+ value: 'MCU_GPIO_PORTD(5)'
+ UART_1_RX:
+ description: 'USART2 RX pin. PA3, PD6'
+ value: 'MCU_GPIO_PORTD(6)'
+ UART_1_RTS:
+ description: 'USART2 RTS pin.'
+ value: -1
+ UART_1_CTS:
+ description: 'USART2 CTS pin.'
+ value: -1
+
+ UART_2:
+ description: 'Whether to enable UART0'
+ value: 1
+ UART_2_TX:
+ description: 'USART3 TX pin. PB10, PC10, PD8'
+ value: 'MCU_GPIO_PORTD(8)'
+ UART_2_RX:
+ description: 'USART3 RX pin. PB11, PC11, PD9'
+ value: 'MCU_GPIO_PORTD(9)'
+ UART_2_RTS:
+ description: 'USART3 RTS pin.'
+ value: -1
+ UART_2_CTS:
+ description: 'USART3 CTS pin.'
value: -1
SPI_0_SCK: