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Posted to commits@nuttx.apache.org by xi...@apache.org on 2026/03/28 16:33:17 UTC
(nuttx) branch master updated (c64b95ccbf7 -> 9028fe72c7b)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
from c64b95ccbf7 ci: split xtensa jobs into three separate jobs (instead of two)
new c17e16eaed8 xtensa/espressif: Update common-source integration for Xtensa devices
new 9028fe72c7b ci: split xtensa jobs into three separate jobs (instead of two)
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/risc-v/src/common/espressif/Make.defs | 2 +-
arch/xtensa/Kconfig | 3 +
arch/xtensa/include/esp32/irq.h | 37 +-
arch/xtensa/include/esp32s2/irq.h | 28 +-
arch/xtensa/include/esp32s3/irq.h | 31 +-
arch/xtensa/src/common/espressif/Kconfig | 263 +-
arch/xtensa/src/common/espressif/Make.defs | 17 +-
arch/xtensa/src/common/espressif/Wireless.mk | 66 +-
arch/xtensa/src/common/espressif/esp_adc.c | 11 +-
arch/xtensa/src/common/espressif/esp_dedic_gpio.c | 67 +-
arch/xtensa/src/common/espressif/esp_efuse.c | 14 +-
.../src/common/espressif/esp_espnow_pktradio.c | 2 +-
.../src/common/espressif/esp_gpio.c | 13 +-
.../esp32s3_gpio.h => common/espressif/esp_gpio.h} | 229 +-
.../src/common/espressif/esp_hr_timer.h} | 12 +-
arch/xtensa/src/common/espressif/esp_i2c_bitbang.c | 38 +-
arch/xtensa/src/common/espressif/esp_i2c_slave.c | 73 +-
arch/xtensa/src/common/espressif/esp_i2s.c | 118 +-
.../src/common/espressif/esp_irq.c | 488 +-
.../src/common/espressif/esp_irq.h | 75 +-
arch/xtensa/src/common/espressif/esp_ledc.c | 36 +-
arch/xtensa/src/common/espressif/esp_loader.c | 2 +-
arch/xtensa/src/common/espressif/esp_mcpwm.c | 121 +-
arch/xtensa/src/common/espressif/esp_openeth.c | 9 +-
arch/xtensa/src/common/espressif/esp_pcnt.c | 129 +-
arch/xtensa/src/common/espressif/esp_pm.c | 360 +-
arch/xtensa/src/common/espressif/esp_pm.h | 52 +-
arch/xtensa/src/common/espressif/esp_rmt.c | 1964 +------
arch/xtensa/src/common/espressif/esp_rmt.h | 24 +-
.../src/common/espressif/esp_rtc.c | 102 +-
.../src/common/espressif/esp_rtc.h} | 20 +-
arch/xtensa/src/common/espressif/esp_sdm.c | 62 +-
arch/xtensa/src/common/espressif/esp_sha.c | 23 +-
arch/xtensa/src/common/espressif/esp_spi_bitbang.c | 24 +-
arch/xtensa/src/common/espressif/esp_spi_bitbang.h | 16 +-
arch/xtensa/src/common/espressif/esp_spiflash.c | 178 +-
arch/xtensa/src/common/espressif/esp_spiflash.h | 16 -
.../src/common/espressif/esp_temperature_sensor.c | 12 +-
.../src/common/espressif/esp_timer_adapter.c | 492 ++
.../src/common/espressif/esp_timer_adapter.h} | 120 +-
arch/xtensa/src/common/espressif/esp_ulp.mk | 9 +-
arch/xtensa/src/common/espressif/esp_wireless.c | 206 +-
arch/xtensa/src/common/espressif/esp_wireless.h | 10 +-
arch/xtensa/src/common/espressif/esp_wlan_netdev.c | 4 +-
arch/xtensa/src/common/espressif/esp_ws2812.c | 35 +-
.../src/common/espressif/esp_xtensa_intr.c} | 133 +-
arch/xtensa/src/esp32/Kconfig | 51 +-
arch/xtensa/src/esp32/Make.defs | 29 +-
arch/xtensa/src/esp32/chip.h | 6 +-
arch/xtensa/src/esp32/esp32_ble_adapter.c | 192 +-
arch/xtensa/src/esp32/esp32_clockconfig.c | 218 -
arch/xtensa/src/esp32/esp32_clockconfig.h | 82 -
arch/xtensa/src/esp32/esp32_cpustart.c | 47 +-
arch/xtensa/src/esp32/esp32_emac.c | 53 +-
arch/xtensa/src/esp32/esp32_freerun.c | 1 -
arch/xtensa/src/esp32/esp32_gpio.c | 625 ---
arch/xtensa/src/esp32/esp32_gpio.h | 273 -
arch/xtensa/src/esp32/esp32_i2c.c | 68 +-
arch/xtensa/src/esp32/esp32_i2s.c | 83 +-
arch/xtensa/src/esp32/esp32_idle.c | 77 +-
arch/xtensa/src/esp32/esp32_irq.c | 1335 -----
arch/xtensa/src/esp32/esp32_irq.h | 263 -
arch/xtensa/src/esp32/esp32_ledc.c | 8 +-
arch/xtensa/src/esp32/esp32_libc_stubs.c | 51 +
arch/xtensa/src/esp32/esp32_oneshot.c | 2 +-
arch/xtensa/src/esp32/esp32_pm.c | 1167 ----
arch/xtensa/src/esp32/esp32_pm.h | 248 -
arch/xtensa/src/esp32/esp32_pminitialize.c | 2 +-
arch/xtensa/src/esp32/esp32_psram.c | 89 +-
arch/xtensa/src/esp32/esp32_qencoder.c | 16 +-
arch/xtensa/src/esp32/esp32_resetcause.c | 2 +-
arch/xtensa/src/esp32/esp32_rng.c | 3 +-
arch/xtensa/src/esp32/esp32_rt_timer.c | 768 ---
arch/xtensa/src/esp32/esp32_rt_timer.h | 244 -
arch/xtensa/src/esp32/esp32_rtc.c | 2277 --------
arch/xtensa/src/esp32/esp32_rtc.h | 713 ---
arch/xtensa/src/esp32/esp32_rtc_gpio.c | 130 +-
arch/xtensa/src/esp32/esp32_rtc_gpio.h | 96 +-
arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c | 559 --
arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h | 56 -
arch/xtensa/src/esp32/esp32_serial.c | 90 +-
arch/xtensa/src/esp32/esp32_sha.c | 15 +-
arch/xtensa/src/esp32/esp32_spi.c | 71 +-
arch/xtensa/src/esp32/esp32_spi_slave.c | 83 +-
arch/xtensa/src/esp32/esp32_spicache.c | 1 -
arch/xtensa/src/esp32/esp32_spicache.h | 2 -
arch/xtensa/src/esp32/esp32_spiflash.c | 12 +-
arch/xtensa/src/esp32/esp32_spiflash.h | 2 -
arch/xtensa/src/esp32/esp32_spiram.c | 2 +-
arch/xtensa/src/esp32/esp32_spiram.h | 2 +-
arch/xtensa/src/esp32/esp32_start.c | 153 +-
arch/xtensa/src/esp32/esp32_start.h | 20 +
arch/xtensa/src/esp32/esp32_systemreset.c | 2 +-
arch/xtensa/src/esp32/esp32_tickless.c | 12 +-
arch/xtensa/src/esp32/esp32_tim.c | 22 +-
arch/xtensa/src/esp32/esp32_tim_lowerhalf.c | 2 +-
arch/xtensa/src/esp32/esp32_timerisr.c | 12 +-
arch/xtensa/src/esp32/esp32_touch.c | 201 +-
arch/xtensa/src/esp32/esp32_touch.h | 46 +
arch/xtensa/src/esp32/esp32_touch_lowerhalf.h | 4 +-
arch/xtensa/src/esp32/esp32_twai.c | 39 +-
arch/xtensa/src/esp32/esp32_userspace.c | 1 -
arch/xtensa/src/esp32/esp32_wdt.c | 104 +-
arch/xtensa/src/esp32/esp32_wifi_adapter.c | 231 +-
arch/xtensa/src/esp32/hal.mk | 221 +-
arch/xtensa/src/esp32/hardware/esp32_rtccntl.h | 3075 ----------
arch/xtensa/src/esp32/hardware/esp32_soc.h | 59 +-
arch/xtensa/src/esp32s2/Kconfig | 16 +-
arch/xtensa/src/esp32s2/Make.defs | 36 +-
arch/xtensa/src/esp32s2/esp32s2_clockconfig.c | 283 -
arch/xtensa/src/esp32s2/esp32s2_clockconfig.h | 82 -
arch/xtensa/src/esp32s2/esp32s2_freerun.c | 2 -
arch/xtensa/src/esp32s2/esp32s2_gpio.c | 582 --
arch/xtensa/src/esp32s2/esp32s2_gpio.h | 325 --
arch/xtensa/src/esp32s2/esp32s2_i2c.c | 37 +-
arch/xtensa/src/esp32s2/esp32s2_i2s.c | 94 +-
arch/xtensa/src/esp32s2/esp32s2_irq.c | 868 ---
arch/xtensa/src/esp32s2/esp32s2_irq.h | 203 -
arch/xtensa/src/esp32s2/esp32s2_libc_stubs.c | 51 +
arch/xtensa/src/esp32s2/esp32s2_lowputc.c | 28 +-
arch/xtensa/src/esp32s2/esp32s2_oneshot.c | 12 +-
arch/xtensa/src/esp32s2/esp32s2_psram.c | 3 +-
arch/xtensa/src/esp32s2/esp32s2_rng.c | 1 -
arch/xtensa/src/esp32s2/esp32s2_rt_timer.c | 839 ---
arch/xtensa/src/esp32s2/esp32s2_rt_timer.h | 244 -
arch/xtensa/src/esp32s2/esp32s2_rtc.c | 2777 ---------
arch/xtensa/src/esp32s2/esp32s2_rtc.h | 755 ---
arch/xtensa/src/esp32s2/esp32s2_rtc_gpio.c | 137 +-
arch/xtensa/src/esp32s2/esp32s2_rtc_gpio.h | 52 +-
arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.c | 558 --
arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.h | 56 -
arch/xtensa/src/esp32s2/esp32s2_serial.c | 40 +-
arch/xtensa/src/esp32s2/esp32s2_spi.c | 76 +-
arch/xtensa/src/esp32s2/esp32s2_spi_slave.c | 80 +-
arch/xtensa/src/esp32s2/esp32s2_start.c | 132 +-
arch/xtensa/src/esp32s2/esp32s2_start.h | 20 +
arch/xtensa/src/esp32s2/esp32s2_systemreset.c | 2 +-
arch/xtensa/src/esp32s2/esp32s2_tim.c | 56 +-
arch/xtensa/src/esp32s2/esp32s2_tim_lowerhalf.c | 2 +-
arch/xtensa/src/esp32s2/esp32s2_timerisr.c | 12 +-
arch/xtensa/src/esp32s2/esp32s2_touch.c | 176 +-
arch/xtensa/src/esp32s2/esp32s2_touch.h | 46 +
arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h | 41 +-
arch/xtensa/src/esp32s2/esp32s2_twai.c | 39 +-
arch/xtensa/src/esp32s2/esp32s2_wdt.c | 84 +-
arch/xtensa/src/esp32s2/esp32s2_wdt.h | 26 +-
arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.c | 14 +-
arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.h | 12 +-
arch/xtensa/src/esp32s2/esp32s2_wifi_adapter.c | 215 +-
arch/xtensa/src/esp32s2/hal.mk | 221 +-
arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h | 3305 -----------
arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h | 5087 -----------------
arch/xtensa/src/esp32s3/Kconfig | 51 +-
arch/xtensa/src/esp32s3/Make.defs | 26 +-
arch/xtensa/src/esp32s3/chip.h | 6 +-
arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c | 280 +-
arch/xtensa/src/esp32s3/esp32s3_cam.c | 87 +-
arch/xtensa/src/esp32s3/esp32s3_clockconfig.c | 271 -
arch/xtensa/src/esp32s3/esp32s3_clockconfig.h | 90 -
arch/xtensa/src/esp32s3/esp32s3_cpustart.c | 56 +-
arch/xtensa/src/esp32s3/esp32s3_dma.c | 2 +-
arch/xtensa/src/esp32s3/esp32s3_freerun.c | 4 +-
arch/xtensa/src/esp32s3/esp32s3_gpio.c | 626 ---
arch/xtensa/src/esp32s3/esp32s3_i2c.c | 39 +-
arch/xtensa/src/esp32s3/esp32s3_irq.c | 1265 -----
arch/xtensa/src/esp32s3/esp32s3_irq.h | 263 -
arch/xtensa/src/esp32s3/esp32s3_lcd.c | 26 +-
arch/xtensa/src/esp32s3/esp32s3_lowputc.c | 57 +-
arch/xtensa/src/esp32s3/esp32s3_lowputc.h | 3 +-
arch/xtensa/src/esp32s3/esp32s3_oneshot.c | 2 +-
arch/xtensa/src/esp32s3/esp32s3_otg_device.c | 33 +-
arch/xtensa/src/esp32s3/esp32s3_psram_octal.c | 2 +-
arch/xtensa/src/esp32s3/esp32s3_psram_quad.c | 8 +-
arch/xtensa/src/esp32s3/esp32s3_qspi.c | 90 +-
arch/xtensa/src/esp32s3/esp32s3_reset_reasons.c | 4 +-
arch/xtensa/src/esp32s3/esp32s3_rng.c | 2 +-
arch/xtensa/src/esp32s3/esp32s3_rt_timer.c | 1054 ----
arch/xtensa/src/esp32s3/esp32s3_rt_timer.h | 244 -
arch/xtensa/src/esp32s3/esp32s3_rtc.c | 3112 ----------
arch/xtensa/src/esp32s3/esp32s3_rtc.h | 807 ---
arch/xtensa/src/esp32s3/esp32s3_rtc_gpio.c | 138 +-
arch/xtensa/src/esp32s3/esp32s3_rtc_gpio.h | 57 +-
arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.c | 559 --
arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h | 56 -
arch/xtensa/src/esp32s3/esp32s3_sdmmc.c | 64 +-
arch/xtensa/src/esp32s3/esp32s3_serial.c | 31 +-
arch/xtensa/src/esp32s3/esp32s3_spi.c | 80 +-
arch/xtensa/src/esp32s3/esp32s3_spi_slave.c | 114 +-
arch/xtensa/src/esp32s3/esp32s3_spi_timing.c | 2 +-
arch/xtensa/src/esp32s3/esp32s3_spiflash.c | 12 +-
arch/xtensa/src/esp32s3/esp32s3_start.c | 79 +-
arch/xtensa/src/esp32s3/esp32s3_start.h | 20 +
arch/xtensa/src/esp32s3/esp32s3_systemreset.c | 4 +-
arch/xtensa/src/esp32s3/esp32s3_tickless.c | 10 +-
arch/xtensa/src/esp32s3/esp32s3_tim.c | 23 +-
arch/xtensa/src/esp32s3/esp32s3_tim_lowerhalf.c | 2 +-
arch/xtensa/src/esp32s3/esp32s3_timerisr.c | 29 +-
arch/xtensa/src/esp32s3/esp32s3_touch.c | 144 +-
arch/xtensa/src/esp32s3/esp32s3_touch.h | 46 +
arch/xtensa/src/esp32s3/esp32s3_touch_lowerhalf.h | 224 +-
arch/xtensa/src/esp32s3/esp32s3_twai.c | 45 +-
arch/xtensa/src/esp32s3/esp32s3_usbserial.c | 24 +-
arch/xtensa/src/esp32s3/esp32s3_userspace.c | 28 +-
arch/xtensa/src/esp32s3/esp32s3_wdt.c | 113 +-
arch/xtensa/src/esp32s3/esp32s3_wdt.h | 26 +-
arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c | 37 +-
arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.h | 12 +-
arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c | 212 +-
arch/xtensa/src/esp32s3/hal.mk | 240 +-
arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h | 3245 -----------
arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h | 5914 --------------------
arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h | 5 +-
boards/Kconfig | 48 +-
.../xtensa/esp32/common/include/esp32_board_rmt.h | 6 +-
.../xtensa/esp32/common/scripts/esp32_sections.ld | 93 +-
boards/xtensa/esp32/common/scripts/flat_memory.ld | 21 +-
boards/xtensa/esp32/common/scripts/kernel-space.ld | 119 +-
.../xtensa/esp32/common/scripts/legacy_sections.ld | 4 +-
.../esp32/common/scripts/mcuboot_sections.ld | 2 +
.../esp32/common/scripts/protected_memory.ld | 35 +
boards/xtensa/esp32/common/src/esp32_backlight.c | 8 +-
.../esp32/common/src/esp32_board_apa102_lcd.c | 3 +-
.../xtensa/esp32/common/src/esp32_board_apds9960.c | 11 +-
boards/xtensa/esp32/common/src/esp32_board_rmt.c | 10 +-
boards/xtensa/esp32/common/src/esp32_board_spi.c | 4 +-
.../xtensa/esp32/common/src/esp32_board_spiflash.c | 9 +-
boards/xtensa/esp32/common/src/esp32_gc9a01.c | 16 +-
boards/xtensa/esp32/common/src/esp32_ili9341.c | 18 +-
boards/xtensa/esp32/common/src/esp32_mcp2515.c | 14 +-
boards/xtensa/esp32/common/src/esp32_rgbled.c | 3 +-
boards/xtensa/esp32/common/src/esp32_ssd1306.c | 10 +-
boards/xtensa/esp32/common/src/esp32_ssd1680.c | 16 +-
boards/xtensa/esp32/common/src/esp32_st7789.c | 16 +-
boards/xtensa/esp32/common/src/esp32_zerocross.c | 11 +-
.../esp32/esp32-2432S028/configs/lvgl/defconfig | 3 +
.../esp32/esp32-2432S028/configs/nsh/defconfig | 3 +
.../esp32/esp32-2432S028/src/esp32_bringup.c | 32 +-
.../esp32/esp32-audio-kit/configs/audio/defconfig | 3 +
.../esp32/esp32-audio-kit/configs/nsh/defconfig | 3 +
.../esp32/esp32-audio-kit/configs/wifi/defconfig | 3 +
.../esp32/esp32-audio-kit/src/esp32_bringup.c | 39 +-
.../esp32/esp32-audio-kit/src/esp32_buttons.c | 42 +-
.../xtensa/esp32/esp32-audio-kit/src/esp32_gpio.c | 44 +-
.../esp32/esp32-audio-kit/src/esp32_userleds.c | 9 +-
.../esp32/esp32-devkitc/configs/adc/defconfig | 3 +
.../esp32/esp32-devkitc/configs/audio/defconfig | 3 +
.../esp32/esp32-devkitc/configs/autopm/defconfig | 3 +
.../esp32/esp32-devkitc/configs/ble/defconfig | 3 +
.../esp32/esp32-devkitc/configs/blewifi/defconfig | 4 +-
.../esp32/esp32-devkitc/configs/bmp280/defconfig | 5 +-
.../esp32-devkitc/configs/brickmatch/defconfig | 3 +
.../esp32/esp32-devkitc/configs/buttons/defconfig | 6 +-
.../esp32/esp32-devkitc/configs/capture/defconfig | 3 +
.../esp32/esp32-devkitc/configs/coremark/defconfig | 3 +
.../esp32/esp32-devkitc/configs/crypto/defconfig | 4 +
.../esp32/esp32-devkitc/configs/cxx/defconfig | 3 +
.../esp32/esp32-devkitc/configs/dac/defconfig | 3 +
.../esp32/esp32-devkitc/configs/efuse/defconfig | 5 +
.../esp32/esp32-devkitc/configs/elf/defconfig | 3 +
.../esp32/esp32-devkitc/configs/espnow/defconfig | 3 +
.../esp32/esp32-devkitc/configs/gpio/defconfig | 3 +
.../esp32/esp32-devkitc/configs/i2c/defconfig | 3 +
.../esp32/esp32-devkitc/configs/i2schar/defconfig | 3 +
.../esp32/esp32-devkitc/configs/knsh/defconfig | 3 +
.../esp32/esp32-devkitc/configs/leds/defconfig | 3 +
.../esp32/esp32-devkitc/configs/match4/defconfig | 5 +-
.../esp32/esp32-devkitc/configs/max6675/defconfig | 3 +
.../esp32/esp32-devkitc/configs/mcp2515/defconfig | 3 +
.../esp32-devkitc/configs/mcuboot_nsh/defconfig | 3 +
.../configs/mcuboot_slot_confirm/defconfig | 3 +
.../configs/mcuboot_update_agent/defconfig | 3 +
.../esp32/esp32-devkitc/configs/modbus/defconfig | 3 +
.../esp32/esp32-devkitc/configs/module/defconfig | 3 +
.../esp32/esp32-devkitc/configs/motor/defconfig | 3 +
.../esp32/esp32-devkitc/configs/mqttc/defconfig | 3 +
.../esp32/esp32-devkitc/configs/ms5611/defconfig | 5 +-
.../esp32/esp32-devkitc/configs/nsh/defconfig | 3 +
.../esp32/esp32-devkitc/configs/nvblk/defconfig | 3 +
.../esp32/esp32-devkitc/configs/nxdiag/defconfig | 3 +
.../esp32/esp32-devkitc/configs/nxlooper/defconfig | 3 +
.../esp32/esp32-devkitc/configs/oneshot/defconfig | 5 +-
.../esp32/esp32-devkitc/configs/ostest/defconfig | 3 +
.../esp32/esp32-devkitc/configs/pm/defconfig | 3 +
.../esp32/esp32-devkitc/configs/psram/defconfig | 3 +
.../esp32-devkitc/configs/psram_usrheap/defconfig | 3 +
.../esp32/esp32-devkitc/configs/pwm/defconfig | 3 +
.../esp32-devkitc/configs/qemu_openeth/defconfig | 3 +
.../esp32/esp32-devkitc/configs/qencoder/defconfig | 3 +
.../esp32/esp32-devkitc/configs/random/defconfig | 3 +
.../esp32/esp32-devkitc/configs/rmt/defconfig | 3 +
.../esp32/esp32-devkitc/configs/romfs/defconfig | 3 +
.../esp32/esp32-devkitc/configs/rtc/defconfig | 4 +-
.../esp32/esp32-devkitc/configs/sdm/defconfig | 3 +
.../esp32-devkitc/configs/sdmmc_spi/defconfig | 3 +
.../esp32/esp32-devkitc/configs/smp/defconfig | 3 +
.../esp32/esp32-devkitc/configs/snake/defconfig | 5 +-
.../esp32/esp32-devkitc/configs/softap/defconfig | 3 +
.../esp32/esp32-devkitc/configs/sotest/defconfig | 3 +
.../esp32/esp32-devkitc/configs/spi/defconfig | 3 +
.../esp32/esp32-devkitc/configs/spiflash/defconfig | 3 +
.../esp32-devkitc/configs/sta_softap/defconfig | 3 +
.../esp32/esp32-devkitc/configs/tickless/defconfig | 3 +
.../esp32/esp32-devkitc/configs/timer/defconfig | 4 +-
.../esp32/esp32-devkitc/configs/twai/defconfig | 3 +
.../configs/wamr_wasi_debug/defconfig | 3 +
.../esp32/esp32-devkitc/configs/watchdog/defconfig | 3 +
.../esp32/esp32-devkitc/configs/watcher/defconfig | 3 +
.../esp32/esp32-devkitc/configs/wifi/defconfig | 3 +
.../esp32/esp32-devkitc/configs/wifi_smp/defconfig | 3 +
.../esp32/esp32-devkitc/configs/wifinsh/defconfig | 3 +
.../esp32-devkitc/configs/wifishare/defconfig | 3 +
.../xtensa/esp32/esp32-devkitc/src/esp32_bringup.c | 50 +-
.../xtensa/esp32/esp32-devkitc/src/esp32_buttons.c | 42 +-
boards/xtensa/esp32/esp32-devkitc/src/esp32_gpio.c | 50 +-
.../esp32/esp32-devkitc/src/esp32_userleds.c | 9 +-
.../xtensa/esp32/esp32-devkitc/src/esp32_w5500.c | 25 +-
.../esp32-ethernet-kit/configs/autopm/defconfig | 3 +
.../esp32-ethernet-kit/configs/buttons/defconfig | 5 +-
.../esp32-ethernet-kit/configs/ethernet/defconfig | 3 +
.../esp32/esp32-ethernet-kit/configs/nsh/defconfig | 3 +
.../esp32-ethernet-kit/configs/oneshot/defconfig | 5 +-
.../esp32/esp32-ethernet-kit/configs/rtc/defconfig | 4 +-
.../esp32-ethernet-kit/configs/wifi/defconfig | 3 +
.../esp32/esp32-ethernet-kit/src/esp32_bringup.c | 32 +-
.../esp32/esp32-ethernet-kit/src/esp32_buttons.c | 42 +-
.../esp32/esp32-lyrat/configs/audio/defconfig | 3 +
.../esp32/esp32-lyrat/configs/buttons/defconfig | 5 +-
.../xtensa/esp32/esp32-lyrat/configs/nsh/defconfig | 3 +
.../esp32/esp32-lyrat/configs/nxrecorder/defconfig | 3 +
.../esp32/esp32-lyrat/configs/rtptools/defconfig | 3 +
.../esp32/esp32-lyrat/configs/sdmmc_spi/defconfig | 3 +
.../esp32/esp32-lyrat/configs/wifi/defconfig | 3 +
.../xtensa/esp32/esp32-lyrat/src/esp32_bringup.c | 37 +-
.../xtensa/esp32/esp32-lyrat/src/esp32_buttons.c | 51 +-
boards/xtensa/esp32/esp32-lyrat/src/esp32_gpio.c | 44 +-
.../xtensa/esp32/esp32-lyrat/src/esp32_userleds.c | 9 +-
.../esp32/esp32-pico-kit/configs/nsh/defconfig | 3 +
.../esp32/esp32-pico-kit/src/esp32_bringup.c | 32 +-
.../esp32/esp32-pico-kit/src/esp32_buttons.c | 42 +-
.../xtensa/esp32/esp32-pico-kit/src/esp32_gpio.c | 44 +-
.../esp32/esp32-sparrow-kit/configs/ble/defconfig | 4 +-
.../esp32-sparrow-kit/configs/mqttc/defconfig | 4 +-
.../esp32/esp32-sparrow-kit/configs/nsh/defconfig | 4 +-
.../esp32/esp32-sparrow-kit/configs/wifi/defconfig | 4 +-
.../esp32/esp32-sparrow-kit/src/esp32_autoleds.c | 32 +-
.../esp32/esp32-sparrow-kit/src/esp32_bringup.c | 32 +-
.../esp32/esp32-sparrow-kit/src/esp32_buttons.c | 42 +-
.../esp32/esp32-sparrow-kit/src/esp32_gpio.c | 44 +-
.../esp32/esp32-sparrow-kit/src/esp32_userleds.c | 8 +-
.../esp32-wrover-kit/configs/autopm/defconfig | 3 +
.../esp32-wrover-kit/configs/bmp180/defconfig | 3 +
.../esp32-wrover-kit/configs/buttons/defconfig | 5 +-
.../esp32/esp32-wrover-kit/configs/gpio/defconfig | 5 +-
.../esp32-wrover-kit/configs/lcd1602/defconfig | 3 +
.../esp32/esp32-wrover-kit/configs/leds/defconfig | 3 +
.../esp32/esp32-wrover-kit/configs/lua/defconfig | 3 +
.../esp32/esp32-wrover-kit/configs/lvgl/defconfig | 3 +
.../esp32/esp32-wrover-kit/configs/nsh/defconfig | 3 +
.../esp32/esp32-wrover-kit/configs/nx/defconfig | 3 +
.../esp32-wrover-kit/configs/oneshot/defconfig | 5 +-
.../esp32/esp32-wrover-kit/configs/rtc/defconfig | 4 +-
.../esp32-wrover-kit/configs/sdmmc_spi/defconfig | 3 +
.../esp32/esp32-wrover-kit/configs/wifi/defconfig | 3 +
.../esp32/esp32-wrover-kit/src/esp32_autoleds.c | 32 +-
.../esp32/esp32-wrover-kit/src/esp32_bringup.c | 32 +-
.../esp32/esp32-wrover-kit/src/esp32_buttons.c | 42 +-
.../xtensa/esp32/esp32-wrover-kit/src/esp32_gpio.c | 44 +-
.../esp32/esp32-wrover-kit/src/esp32_userleds.c | 9 +-
.../esp32/heltec_wifi_lora32/configs/nsh/defconfig | 3 +
.../heltec_wifi_lora32/configs/sx1276/defconfig | 3 +
.../esp32/heltec_wifi_lora32/src/esp32_bringup.c | 14 +
.../esp32/heltec_wifi_lora32/src/esp32_sx127x.c | 18 +-
.../lilygo_tbeam_lora_gps/configs/gps/defconfig | 3 +
.../lilygo_tbeam_lora_gps/configs/nsh/defconfig | 3 +
.../lilygo_tbeam_lora_gps/configs/sx127x/defconfig | 3 +
.../lilygo_tbeam_lora_gps/src/esp32_bringup.c | 32 +-
.../lilygo_tbeam_lora_gps/src/esp32_buttons.c | 42 +-
.../esp32/lilygo_tbeam_lora_gps/src/esp32_gpio.c | 44 +-
.../esp32/lilygo_tbeam_lora_gps/src/esp32_sx127x.c | 18 +-
.../lilygo_tbeam_lora_gps/src/esp32_userleds.c | 9 +-
.../esp32/ttgo_eink5_v2/configs/fb/defconfig | 3 +
.../xtensa/esp32/ttgo_eink5_v2/src/esp32_bringup.c | 32 +-
.../xtensa/esp32/ttgo_eink5_v2/src/esp32_buttons.c | 46 +-
boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_gpio.c | 44 +-
.../esp32/ttgo_eink5_v2/src/esp32_userleds.c | 9 +-
.../esp32/ttgo_lora_esp32/configs/nsh/defconfig | 3 +
.../esp32/ttgo_lora_esp32/configs/sx127x/defconfig | 3 +
.../esp32/ttgo_lora_esp32/src/esp32_bringup.c | 32 +-
.../esp32/ttgo_lora_esp32/src/esp32_buttons.c | 42 +-
.../xtensa/esp32/ttgo_lora_esp32/src/esp32_gpio.c | 44 +-
.../esp32/ttgo_lora_esp32/src/esp32_sx127x.c | 18 +-
.../esp32/ttgo_lora_esp32/src/esp32_userleds.c | 9 +-
.../ttgo_t_display_esp32/configs/lvgl_fb/defconfig | 3 +
.../configs/lvgl_lcd/defconfig | 3 +
.../ttgo_t_display_esp32/configs/nsh/defconfig | 3 +
.../esp32/ttgo_t_display_esp32/src/esp32_bringup.c | 32 +-
.../esp32/ttgo_t_display_esp32/src/esp32_buttons.c | 42 +-
.../esp32/ttgo_t_display_esp32/src/esp32_gpio.c | 44 +-
.../ttgo_t_display_esp32/src/esp32_userleds.c | 9 +-
.../esp32s2/common/include/esp32s2_board_rmt.h | 6 +-
.../esp32s2/common/scripts/esp32s2_sections.ld | 34 +-
.../xtensa/esp32s2/common/scripts/flat_memory.ld | 4 +-
.../esp32s2/common/scripts/mcuboot_sections.ld | 3 +
.../xtensa/esp32s2/common/src/esp32s2_board_rmt.c | 16 +-
.../xtensa/esp32s2/common/src/esp32s2_board_spi.c | 6 +-
.../esp32s2/common/src/esp32s2_board_spiflash.c | 9 +-
.../xtensa/esp32s2/common/src/esp32s2_board_wdt.c | 1 -
boards/xtensa/esp32s2/common/src/esp32s2_ili9341.c | 18 +-
boards/xtensa/esp32s2/common/src/esp32s2_st7789.c | 16 +-
.../esp32s2-kaluga-1/configs/audio/defconfig | 3 +
.../esp32s2-kaluga-1/configs/buttons/defconfig | 5 +-
.../esp32s2/esp32s2-kaluga-1/configs/i2c/defconfig | 3 +
.../configs/lvgl_ili9341/defconfig | 3 +
.../esp32s2-kaluga-1/configs/lvgl_st7789/defconfig | 3 +
.../esp32s2/esp32s2-kaluga-1/configs/nsh/defconfig | 3 +
.../esp32s2-kaluga-1/configs/nxlooper/defconfig | 3 +
.../esp32s2/esp32s2-kaluga-1/configs/rtc/defconfig | 4 +-
.../esp32s2-kaluga-1/configs/twai/defconfig | 3 +
.../esp32s2-kaluga-1/configs/watchdog/defconfig | 3 +
.../esp32s2/esp32s2-kaluga-1/src/esp32s2_bringup.c | 35 +-
.../esp32s2/esp32s2-kaluga-1/src/esp32s2_buttons.c | 49 +-
.../esp32s2/esp32s2-kaluga-1/src/esp32s2_gpio.c | 62 +-
.../esp32s2/esp32s2-saola-1/configs/adc/defconfig | 3 +
.../esp32s2-saola-1/configs/audio/defconfig | 3 +
.../esp32s2-saola-1/configs/buttons/defconfig | 5 +-
.../esp32s2-saola-1/configs/coremark/defconfig | 3 +
.../esp32s2-saola-1/configs/crypto/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/cxx/defconfig | 3 +
.../esp32s2-saola-1/configs/efuse/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/gpio/defconfig | 5 +-
.../esp32s2/esp32s2-saola-1/configs/i2c/defconfig | 3 +
.../esp32s2-saola-1/configs/i2schar/defconfig | 3 +
.../esp32s2-saola-1/configs/mcuboot_nsh/defconfig | 3 +
.../configs/mcuboot_update_agent/defconfig | 6 +-
.../esp32s2/esp32s2-saola-1/configs/nsh/defconfig | 3 +
.../esp32s2-saola-1/configs/nxlooper/defconfig | 3 +
.../esp32s2-saola-1/configs/oneshot/defconfig | 3 +
.../esp32s2-saola-1/configs/ostest/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/pm/defconfig | 5 +
.../esp32s2/esp32s2-saola-1/configs/pwm/defconfig | 3 +
.../esp32s2-saola-1/configs/qencoder/defconfig | 3 +
.../esp32s2-saola-1/configs/random/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/rmt/defconfig | 3 +
.../esp32s2-saola-1/configs/romfs/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/rtc/defconfig | 4 +-
.../esp32s2/esp32s2-saola-1/configs/sdm/defconfig | 3 +
.../esp32s2-saola-1/configs/sdmmc_spi/defconfig | 3 +
.../esp32s2-saola-1/configs/sotest/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/spi/defconfig | 3 +
.../esp32s2-saola-1/configs/spiflash/defconfig | 3 +
.../esp32s2-saola-1/configs/sta_softap/defconfig | 5 +
.../configs/temperature_sensor/defconfig | 4 +
.../esp32s2-saola-1/configs/timer/defconfig | 4 +-
.../esp32s2/esp32s2-saola-1/configs/twai/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/ulp/defconfig | 5 +-
.../esp32s2-saola-1/configs/watchdog/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/wifi/defconfig | 5 +
.../esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c | 35 +-
.../esp32s2/esp32s2-saola-1/src/esp32s2_buttons.c | 48 +-
.../esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c | 65 +-
.../esp32s2/franzininho-wifi/configs/nsh/defconfig | 3 +
.../esp32s2/franzininho-wifi/src/esp32s2_bringup.c | 26 +-
boards/xtensa/esp32s3/common/Makefile | 1 +
.../esp32s3/common/include/esp32s3_board_rmt.h | 6 +-
.../esp32s3/common/scripts/esp32s3_sections.ld | 31 +-
.../xtensa/esp32s3/common/scripts/kernel-space.ld | 7 +
.../esp32s3/common/scripts/legacy_sections.ld | 4 +-
.../esp32s3/common/scripts/mcuboot_sections.ld | 4 +-
.../esp32s3/common/scripts/protected_memory.ld | 2 -
.../xtensa/esp32s3/common/src/esp32s3_board_rmt.c | 10 +-
.../esp32s3/common/src/esp32s3_board_spiflash.c | 5 +-
.../xtensa/esp32s3/common/src/esp32s3_board_wdt.c | 2 -
boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c | 26 +-
.../esp32s3-8048S043/configs/gpio/defconfig | 3 +
.../esp32s3/esp32s3-8048S043/configs/i2c/defconfig | 3 +
.../esp32s3/esp32s3-8048S043/configs/lcd/defconfig | 3 +
.../esp32s3/esp32s3-8048S043/configs/nsh/defconfig | 3 +
.../esp32s3-8048S043/configs/sdmmc/defconfig | 3 +
.../esp32s3/esp32s3-8048S043/configs/spi/defconfig | 3 +
.../esp32s3-8048S043/configs/touchscreen/defconfig | 3 +
.../esp32s3-8048S043/src/esp32s3_board_spi.c | 2 +-
.../src/esp32s3_board_touchsceen.c | 2 +-
.../esp32s3/esp32s3-8048S043/src/esp32s3_bringup.c | 19 +-
.../esp32s3/esp32s3-8048S043/src/esp32s3_buttons.c | 42 +-
.../esp32s3/esp32s3-8048S043/src/esp32s3_gpio.c | 50 +-
.../esp32s3/esp32s3-8048S043/src/esp32s3_lcd.c | 6 +-
.../esp32s3/esp32s3-box/configs/buttons/defconfig | 3 +
.../esp32s3/esp32s3-box/configs/lvgl-3/defconfig | 3 +
.../esp32s3/esp32s3-box/configs/lvgl/defconfig | 3 +
.../esp32s3/esp32s3-box/configs/nsh/defconfig | 3 +
.../esp32s3-box/configs/touchscreen/defconfig | 3 +
.../esp32s3-box/src/esp32s3_board_lcd_ili9342c.c | 21 +-
.../esp32s3-box/src/esp32s3_board_lcd_st7789.c | 14 +-
.../esp32s3/esp32s3-box/src/esp32s3_board_spi.c | 6 +-
.../src/esp32s3_board_touchsceen_gt911.c | 2 +-
.../src/esp32s3_board_touchsceen_tt21100.c | 2 +-
.../esp32s3/esp32s3-box/src/esp32s3_bringup.c | 31 +-
.../esp32s3/esp32s3-box/src/esp32s3_buttons.c | 42 +-
.../esp32s3/esp32s3-devkit/configs/adc/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/audio/defconfig | 5 +
.../esp32s3/esp32s3-devkit/configs/ble/defconfig | 6 +-
.../esp32s3-devkit/configs/blewifi/defconfig | 6 +-
.../esp32s3-devkit/configs/buttons/defconfig | 3 +
.../esp32s3-devkit/configs/capture/defconfig | 3 +
.../esp32s3-devkit/configs/coremark/defconfig | 3 +
.../esp32s3-devkit/configs/crypto/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/cxx/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/efuse/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/elf/defconfig | 3 +
.../esp32s3-devkit/configs/eth_lan9250/defconfig | 3 +
.../esp32s3-devkit/configs/fastboot/defconfig | 6 +-
.../esp32s3-devkit/configs/fastboot_tcp/defconfig | 6 +-
.../esp32s3/esp32s3-devkit/configs/gpio/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/i2c/defconfig | 3 +
.../esp32s3-devkit/configs/i2schar/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/knsh/defconfig | 3 +
.../esp32s3-devkit/configs/ksta_softap/defconfig | 6 +-
.../esp32s3-devkit/configs/mbedtls/defconfig | 7 +-
.../esp32s3-devkit/configs/mcuboot_nsh/defconfig | 3 +
.../configs/mcuboot_update_agent/defconfig | 6 +-
.../esp32s3/esp32s3-devkit/configs/motor/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/nsh/defconfig | 3 +
.../esp32s3-devkit/configs/nxlooper/defconfig | 3 +
.../esp32s3-devkit/configs/oneshot/defconfig | 5 +-
.../esp32s3-devkit/configs/ostest/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/pm/defconfig | 5 +
.../esp32s3-devkit/configs/psram_octal/defconfig | 3 +
.../esp32s3-devkit/configs/psram_quad/defconfig | 3 +
.../esp32s3-devkit/configs/psram_usrheap/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/pwm/defconfig | 3 +
.../esp32s3-devkit/configs/python/defconfig | 6 +-
.../esp32s3-devkit/configs/qemu_debug/defconfig | 7 +-
.../esp32s3-devkit/configs/qemu_openeth/defconfig | 3 +
.../esp32s3-devkit/configs/qemu_toywasm/defconfig | 7 +-
.../esp32s3-devkit/configs/qencoder/defconfig | 3 +
.../esp32s3-devkit/configs/random/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/rmt/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/romfs/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/rtc/defconfig | 4 +-
.../esp32s3/esp32s3-devkit/configs/sdm/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/sdmmc/defconfig | 3 +
.../esp32s3-devkit/configs/sdmmc_spi/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/smp/defconfig | 3 +
.../esp32s3-devkit/configs/sotest/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/spi/defconfig | 3 +
.../esp32s3-devkit/configs/spiflash/defconfig | 3 +
.../esp32s3-devkit/configs/spislv/defconfig | 3 +
.../esp32s3-devkit/configs/sta_softap/defconfig | 5 +
.../esp32s3/esp32s3-devkit/configs/stack/defconfig | 5 +
.../configs/temperature_sensor/defconfig | 3 +
.../esp32s3-devkit/configs/tickless/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/timer/defconfig | 3 +
.../esp32s3-devkit/configs/toywasm/defconfig | 6 +-
.../esp32s3/esp32s3-devkit/configs/twai/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/ulp/defconfig | 3 +
.../esp32s3-devkit/configs/usb_device/defconfig | 3 +
.../esp32s3-devkit/configs/usbnsh/defconfig | 3 +
.../esp32s3-devkit/configs/watchdog/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/wifi/defconfig | 5 +
boards/xtensa/esp32s3/esp32s3-devkit/src/Make.defs | 8 +
.../esp32s3/esp32s3-devkit/src/esp32s3_board_spi.c | 6 +-
.../esp32s3/esp32s3-devkit/src/esp32s3_bringup.c | 39 +-
.../esp32s3/esp32s3-devkit/src/esp32s3_buttons.c | 42 +-
.../esp32s3/esp32s3-devkit/src/esp32s3_djoystick.c | 32 +-
.../esp32s3/esp32s3-devkit/src/esp32s3_gpio.c | 61 +-
.../esp32s3/esp32s3-devkit/src/esp32s3_st7735.c | 12 +-
.../esp32s3/esp32s3-eye/configs/gpio/defconfig | 3 +
.../esp32s3/esp32s3-eye/configs/i2c/defconfig | 3 +
.../esp32s3/esp32s3-eye/configs/lcd/defconfig | 3 +
.../esp32s3/esp32s3-eye/configs/nsh/defconfig | 3 +
.../esp32s3/esp32s3-eye/configs/usbnsh/defconfig | 3 +
.../esp32s3/esp32s3-eye/configs/wifi/defconfig | 6 +-
.../esp32s3/esp32s3-eye/src/esp32s3_board_lcd.c | 8 +-
.../esp32s3/esp32s3-eye/src/esp32s3_board_spi.c | 6 +-
.../esp32s3/esp32s3-eye/src/esp32s3_bringup.c | 27 +-
.../esp32s3/esp32s3-eye/src/esp32s3_buttons.c | 42 +-
.../xtensa/esp32s3/esp32s3-eye/src/esp32s3_gpio.c | 46 +-
.../esp32s3-korvo-2/configs/audio/defconfig | 5 +
.../esp32s3/esp32s3-korvo-2/configs/nsh/defconfig | 3 +
.../esp32s3-korvo-2/configs/rtptools/defconfig | 5 +
.../esp32s3-korvo-2/configs/sdmmc/defconfig | 3 +
.../esp32s3-korvo-2/src/esp32s3_board_spi.c | 6 +-
.../esp32s3/esp32s3-korvo-2/src/esp32s3_bringup.c | 40 +-
.../esp32s3/esp32s3-korvo-2/src/esp32s3_buttons.c | 42 +-
.../esp32s3/esp32s3-lcd-ev/configs/audio/defconfig | 5 +
.../esp32s3-lcd-ev/configs/buttons/defconfig | 3 +
.../esp32s3/esp32s3-lcd-ev/configs/lcd/defconfig | 3 +
.../esp32s3/esp32s3-lcd-ev/configs/lvgl/defconfig | 3 +
.../esp32s3/esp32s3-lcd-ev/configs/nsh/defconfig | 3 +
.../esp32s3-lcd-ev/configs/ws2812/defconfig | 3 +
.../esp32s3/esp32s3-lcd-ev/src/esp32s3_board_spi.c | 6 +-
.../esp32s3/esp32s3-lcd-ev/src/esp32s3_bringup.c | 36 +-
.../esp32s3/esp32s3-lcd-ev/src/esp32s3_buttons.c | 42 +-
.../esp32s3/esp32s3-lcd-ev/src/esp32s3_lcd.c | 10 +-
.../esp32s3-lhcbit/configs/usbnsh/defconfig | 3 +
.../esp32s3/esp32s3-lhcbit/src/esp32s3_bringup.c | 15 +
.../esp32s3/esp32s3-meadow/configs/nsh/defconfig | 3 +
.../esp32s3-meadow/configs/usbnsh/defconfig | 3 +
.../esp32s3/esp32s3-meadow/src/esp32s3_bringup.c | 27 +-
.../esp32s3/esp32s3-xiao/configs/combo/defconfig | 3 +
.../esp32s3/esp32s3-xiao/configs/usbnsh/defconfig | 3 +
.../esp32s3/esp32s3-xiao/src/esp32s3_autoleds.c | 10 +-
.../esp32s3/esp32s3-xiao/src/esp32s3_bringup.c | 15 +
.../xtensa/esp32s3/esp32s3-xiao/src/esp32s3_gpio.c | 43 +-
.../esp32s3/esp32s3-xiao/src/esp32s3_userleds.c | 9 +-
.../lckfb-szpi-esp32s3/configs/camera/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/fastboot/defconfig | 6 +-
.../configs/fastboot_tcp/defconfig | 6 +-
.../lckfb-szpi-esp32s3/configs/gc0308/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/gpio/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/lcd/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/lvgl/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/nsh/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/pca9557/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/psram/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/pwm/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/qmi8658/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/sdmmc/defconfig | 3 +
.../configs/usb_device/defconfig | 3 +
.../lckfb-szpi-esp32s3/src/esp32s3_board_lcd.c | 2 +-
.../lckfb-szpi-esp32s3/src/esp32s3_board_spi.c | 6 +-
.../lckfb-szpi-esp32s3/src/esp32s3_bringup.c | 32 +-
.../esp32s3/lckfb-szpi-esp32s3/src/esp32s3_gpio.c | 49 +-
623 files changed, 8779 insertions(+), 53587 deletions(-)
copy arch/{risc-v => xtensa}/src/common/espressif/esp_gpio.c (97%)
rename arch/xtensa/src/{esp32s3/esp32s3_gpio.h => common/espressif/esp_gpio.h} (69%)
copy arch/{arm/src/stm32f7/stm32_dbgmcu.h => xtensa/src/common/espressif/esp_hr_timer.h} (77%)
copy arch/{risc-v => xtensa}/src/common/espressif/esp_irq.c (69%)
copy arch/{risc-v => xtensa}/src/common/espressif/esp_irq.h (83%)
copy arch/{risc-v => xtensa}/src/common/espressif/esp_rtc.c (90%)
copy arch/{risc-v/src/common/espressif/esp_oneshot.h => xtensa/src/common/espressif/esp_rtc.h} (81%)
create mode 100644 arch/xtensa/src/common/espressif/esp_timer_adapter.c
copy arch/{risc-v/src/common/espressif/esp_hr_timer.h => xtensa/src/common/espressif/esp_timer_adapter.h} (71%)
copy arch/{risc-v/src/common/espressif/esp_systemreset.c => xtensa/src/common/espressif/esp_xtensa_intr.c} (58%)
delete mode 100644 arch/xtensa/src/esp32/esp32_clockconfig.c
delete mode 100644 arch/xtensa/src/esp32/esp32_clockconfig.h
delete mode 100644 arch/xtensa/src/esp32/esp32_gpio.c
delete mode 100644 arch/xtensa/src/esp32/esp32_gpio.h
delete mode 100644 arch/xtensa/src/esp32/esp32_irq.c
delete mode 100644 arch/xtensa/src/esp32/esp32_irq.h
delete mode 100644 arch/xtensa/src/esp32/esp32_pm.c
delete mode 100644 arch/xtensa/src/esp32/esp32_pm.h
delete mode 100644 arch/xtensa/src/esp32/esp32_rt_timer.c
delete mode 100644 arch/xtensa/src/esp32/esp32_rt_timer.h
delete mode 100644 arch/xtensa/src/esp32/esp32_rtc.c
delete mode 100644 arch/xtensa/src/esp32/esp32_rtc.h
delete mode 100644 arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c
delete mode 100644 arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h
delete mode 100644 arch/xtensa/src/esp32/hardware/esp32_rtccntl.h
delete mode 100644 arch/xtensa/src/esp32s2/esp32s2_clockconfig.c
delete mode 100644 arch/xtensa/src/esp32s2/esp32s2_clockconfig.h
delete mode 100644 arch/xtensa/src/esp32s2/esp32s2_gpio.c
delete mode 100644 arch/xtensa/src/esp32s2/esp32s2_gpio.h
delete mode 100644 arch/xtensa/src/esp32s2/esp32s2_irq.c
delete mode 100644 arch/xtensa/src/esp32s2/esp32s2_irq.h
delete mode 100644 arch/xtensa/src/esp32s2/esp32s2_rt_timer.c
delete mode 100644 arch/xtensa/src/esp32s2/esp32s2_rt_timer.h
delete mode 100644 arch/xtensa/src/esp32s2/esp32s2_rtc.c
delete mode 100644 arch/xtensa/src/esp32s2/esp32s2_rtc.h
delete mode 100644 arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.c
delete mode 100644 arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.h
delete mode 100644 arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h
delete mode 100644 arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h
delete mode 100644 arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
delete mode 100644 arch/xtensa/src/esp32s3/esp32s3_clockconfig.h
delete mode 100644 arch/xtensa/src/esp32s3/esp32s3_gpio.c
delete mode 100644 arch/xtensa/src/esp32s3/esp32s3_irq.c
delete mode 100644 arch/xtensa/src/esp32s3/esp32s3_irq.h
delete mode 100644 arch/xtensa/src/esp32s3/esp32s3_rt_timer.c
delete mode 100644 arch/xtensa/src/esp32s3/esp32s3_rt_timer.h
delete mode 100644 arch/xtensa/src/esp32s3/esp32s3_rtc.c
delete mode 100644 arch/xtensa/src/esp32s3/esp32s3_rtc.h
delete mode 100644 arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.c
delete mode 100644 arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h
delete mode 100644 arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h
delete mode 100644 arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h
(nuttx) 01/02: xtensa/espressif: Update common-source integration for Xtensa devices
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit c17e16eaed8e710c424fae23c5e98c362849e528
Author: Tiago Medicci Serrano <ti...@espressif.com>
AuthorDate: Fri Feb 27 15:06:57 2026 -0300
xtensa/espressif: Update common-source integration for Xtensa devices
This commit updates the common-source integration for Xtensa-based
Espressif devices (ESP32, ESP32-S2, and ESP32-S3). This is part of a larger
common-source update split by architecture for better maintainability.
Major components updated:
- IRQ allocator refactoring with intr_alloc integration
- Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.)
- Espressif components upgrade to release/master.b-test
- Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.)
- Wireless adapters (Wi-Fi and BLE)
- esp_timer migration to the common-source path for Xtensa devices
- Common-source power management implementation (auto-sleep and wakeup paths)
- Board defconfigs for all Xtensa Espressif boards
- SMP support improvements for ESP32-S3
- Critical section handling improvements
Key architectural changes:
- IRQ Allocator: The new interrupt allocator enables multiple mapping
options from interrupt sources to CPU interrupts, providing flexibility
required by modern peripherals. Although this introduces breaking changes
to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE
Kconfig option is explicitly checked during startup to ensure proper
configuration. This validation prevents runtime issues from configuration
mismatches.
- Xtensa-specific interrupt handling via esp_xtensa_intr.c providing
NuttX-native implementations of xt_ints_on/off and interrupt handlers,
avoiding conflicts with NuttX's core Xtensa macros.
- Timer/RTC unification: ESP32/ESP32-S2/ESP32-S3 move from chip-specific
RTC/RT-timer code to common-source Espressif integration, including
esp_timer_adapter/esp_rtc paths and the required bringup/defconfig updates.
- Power management consolidation: Xtensa PM follows the common-source
implementation, including common-source auto-sleep behavior, UART/Wi-Fi
wakeup coordination, and tickless-safe sleep flow compatibility.
Note: This is a large commit to maintain bisectability. Breaking the
changes into smaller commits would result in non-building intermediate
states across the common-source infrastructure update.
Tested configurations:
- All defconfigs were tested, including `ostest`.
Signed-off-by: Tiago Medicci Serrano <ti...@espressif.com>
---
arch/risc-v/src/common/espressif/Make.defs | 2 +-
arch/xtensa/Kconfig | 3 +
arch/xtensa/include/esp32/irq.h | 37 +-
arch/xtensa/include/esp32s2/irq.h | 28 +-
arch/xtensa/include/esp32s3/irq.h | 31 +-
arch/xtensa/src/common/espressif/Kconfig | 263 +-
arch/xtensa/src/common/espressif/Make.defs | 17 +-
arch/xtensa/src/common/espressif/Wireless.mk | 66 +-
arch/xtensa/src/common/espressif/esp_adc.c | 11 +-
arch/xtensa/src/common/espressif/esp_dedic_gpio.c | 67 +-
arch/xtensa/src/common/espressif/esp_efuse.c | 14 +-
.../src/common/espressif/esp_espnow_pktradio.c | 2 +-
arch/xtensa/src/common/espressif/esp_gpio.c | 457 ++
.../esp32s3_gpio.h => common/espressif/esp_gpio.h} | 229 +-
.../espressif/esp_hr_timer.h} | 38 +-
arch/xtensa/src/common/espressif/esp_i2c_bitbang.c | 38 +-
arch/xtensa/src/common/espressif/esp_i2c_slave.c | 73 +-
arch/xtensa/src/common/espressif/esp_i2s.c | 118 +-
arch/xtensa/src/common/espressif/esp_irq.c | 955 ++++
arch/xtensa/src/common/espressif/esp_irq.h | 296 +
arch/xtensa/src/common/espressif/esp_ledc.c | 36 +-
arch/xtensa/src/common/espressif/esp_loader.c | 2 +-
arch/xtensa/src/common/espressif/esp_mcpwm.c | 121 +-
arch/xtensa/src/common/espressif/esp_openeth.c | 9 +-
arch/xtensa/src/common/espressif/esp_pcnt.c | 129 +-
arch/xtensa/src/common/espressif/esp_pm.c | 360 +-
arch/xtensa/src/common/espressif/esp_pm.h | 52 +-
arch/xtensa/src/common/espressif/esp_rmt.c | 1964 +------
arch/xtensa/src/common/espressif/esp_rmt.h | 24 +-
arch/xtensa/src/common/espressif/esp_rtc.c | 895 +++
.../espressif/esp_rtc.h} | 27 +-
arch/xtensa/src/common/espressif/esp_sdm.c | 62 +-
arch/xtensa/src/common/espressif/esp_sha.c | 23 +-
arch/xtensa/src/common/espressif/esp_spi_bitbang.c | 24 +-
arch/xtensa/src/common/espressif/esp_spi_bitbang.h | 16 +-
arch/xtensa/src/common/espressif/esp_spiflash.c | 178 +-
arch/xtensa/src/common/espressif/esp_spiflash.h | 16 -
.../src/common/espressif/esp_temperature_sensor.c | 12 +-
.../src/common/espressif/esp_timer_adapter.c | 492 ++
.../src/common/espressif/esp_timer_adapter.h | 324 ++
arch/xtensa/src/common/espressif/esp_ulp.mk | 9 +-
arch/xtensa/src/common/espressif/esp_wireless.c | 206 +-
arch/xtensa/src/common/espressif/esp_wireless.h | 10 +-
arch/xtensa/src/common/espressif/esp_wlan_netdev.c | 4 +-
arch/xtensa/src/common/espressif/esp_ws2812.c | 35 +-
.../xtensa/src/common/espressif/esp_xtensa_intr.c | 141 +-
arch/xtensa/src/esp32/Kconfig | 51 +-
arch/xtensa/src/esp32/Make.defs | 29 +-
arch/xtensa/src/esp32/chip.h | 6 +-
arch/xtensa/src/esp32/esp32_ble_adapter.c | 192 +-
arch/xtensa/src/esp32/esp32_clockconfig.c | 218 -
arch/xtensa/src/esp32/esp32_clockconfig.h | 82 -
arch/xtensa/src/esp32/esp32_cpustart.c | 47 +-
arch/xtensa/src/esp32/esp32_emac.c | 53 +-
arch/xtensa/src/esp32/esp32_freerun.c | 1 -
arch/xtensa/src/esp32/esp32_gpio.c | 625 ---
arch/xtensa/src/esp32/esp32_gpio.h | 273 -
arch/xtensa/src/esp32/esp32_i2c.c | 68 +-
arch/xtensa/src/esp32/esp32_i2s.c | 83 +-
arch/xtensa/src/esp32/esp32_idle.c | 77 +-
arch/xtensa/src/esp32/esp32_irq.c | 1335 -----
arch/xtensa/src/esp32/esp32_irq.h | 263 -
arch/xtensa/src/esp32/esp32_ledc.c | 8 +-
arch/xtensa/src/esp32/esp32_libc_stubs.c | 51 +
arch/xtensa/src/esp32/esp32_oneshot.c | 2 +-
arch/xtensa/src/esp32/esp32_pm.c | 1167 ----
arch/xtensa/src/esp32/esp32_pm.h | 248 -
arch/xtensa/src/esp32/esp32_pminitialize.c | 2 +-
arch/xtensa/src/esp32/esp32_psram.c | 89 +-
arch/xtensa/src/esp32/esp32_qencoder.c | 16 +-
arch/xtensa/src/esp32/esp32_resetcause.c | 2 +-
arch/xtensa/src/esp32/esp32_rng.c | 3 +-
arch/xtensa/src/esp32/esp32_rt_timer.c | 768 ---
arch/xtensa/src/esp32/esp32_rt_timer.h | 244 -
arch/xtensa/src/esp32/esp32_rtc.c | 2277 --------
arch/xtensa/src/esp32/esp32_rtc.h | 713 ---
arch/xtensa/src/esp32/esp32_rtc_gpio.c | 130 +-
arch/xtensa/src/esp32/esp32_rtc_gpio.h | 96 +-
arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c | 559 --
arch/xtensa/src/esp32/esp32_serial.c | 90 +-
arch/xtensa/src/esp32/esp32_sha.c | 15 +-
arch/xtensa/src/esp32/esp32_spi.c | 71 +-
arch/xtensa/src/esp32/esp32_spi_slave.c | 83 +-
arch/xtensa/src/esp32/esp32_spicache.c | 1 -
arch/xtensa/src/esp32/esp32_spicache.h | 2 -
arch/xtensa/src/esp32/esp32_spiflash.c | 12 +-
arch/xtensa/src/esp32/esp32_spiflash.h | 2 -
arch/xtensa/src/esp32/esp32_spiram.c | 2 +-
arch/xtensa/src/esp32/esp32_spiram.h | 2 +-
arch/xtensa/src/esp32/esp32_start.c | 153 +-
arch/xtensa/src/esp32/esp32_start.h | 20 +
arch/xtensa/src/esp32/esp32_systemreset.c | 2 +-
arch/xtensa/src/esp32/esp32_tickless.c | 12 +-
arch/xtensa/src/esp32/esp32_tim.c | 22 +-
arch/xtensa/src/esp32/esp32_tim_lowerhalf.c | 2 +-
arch/xtensa/src/esp32/esp32_timerisr.c | 12 +-
arch/xtensa/src/esp32/esp32_touch.c | 201 +-
arch/xtensa/src/esp32/esp32_touch.h | 46 +
arch/xtensa/src/esp32/esp32_touch_lowerhalf.h | 4 +-
arch/xtensa/src/esp32/esp32_twai.c | 39 +-
arch/xtensa/src/esp32/esp32_userspace.c | 1 -
arch/xtensa/src/esp32/esp32_wdt.c | 104 +-
arch/xtensa/src/esp32/esp32_wifi_adapter.c | 231 +-
arch/xtensa/src/esp32/hal.mk | 221 +-
arch/xtensa/src/esp32/hardware/esp32_rtccntl.h | 3075 ----------
arch/xtensa/src/esp32/hardware/esp32_soc.h | 59 +-
arch/xtensa/src/esp32s2/Kconfig | 16 +-
arch/xtensa/src/esp32s2/Make.defs | 36 +-
arch/xtensa/src/esp32s2/esp32s2_clockconfig.c | 283 -
arch/xtensa/src/esp32s2/esp32s2_clockconfig.h | 82 -
arch/xtensa/src/esp32s2/esp32s2_freerun.c | 2 -
arch/xtensa/src/esp32s2/esp32s2_gpio.c | 582 --
arch/xtensa/src/esp32s2/esp32s2_gpio.h | 325 --
arch/xtensa/src/esp32s2/esp32s2_i2c.c | 37 +-
arch/xtensa/src/esp32s2/esp32s2_i2s.c | 94 +-
arch/xtensa/src/esp32s2/esp32s2_irq.c | 868 ---
arch/xtensa/src/esp32s2/esp32s2_irq.h | 203 -
arch/xtensa/src/esp32s2/esp32s2_libc_stubs.c | 51 +
arch/xtensa/src/esp32s2/esp32s2_lowputc.c | 28 +-
arch/xtensa/src/esp32s2/esp32s2_oneshot.c | 12 +-
arch/xtensa/src/esp32s2/esp32s2_psram.c | 3 +-
arch/xtensa/src/esp32s2/esp32s2_rng.c | 1 -
arch/xtensa/src/esp32s2/esp32s2_rt_timer.c | 839 ---
arch/xtensa/src/esp32s2/esp32s2_rt_timer.h | 244 -
arch/xtensa/src/esp32s2/esp32s2_rtc.c | 2777 ---------
arch/xtensa/src/esp32s2/esp32s2_rtc.h | 755 ---
arch/xtensa/src/esp32s2/esp32s2_rtc_gpio.c | 137 +-
arch/xtensa/src/esp32s2/esp32s2_rtc_gpio.h | 52 +-
arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.c | 558 --
arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.h | 56 -
arch/xtensa/src/esp32s2/esp32s2_serial.c | 40 +-
arch/xtensa/src/esp32s2/esp32s2_spi.c | 76 +-
arch/xtensa/src/esp32s2/esp32s2_spi_slave.c | 80 +-
arch/xtensa/src/esp32s2/esp32s2_start.c | 132 +-
arch/xtensa/src/esp32s2/esp32s2_start.h | 20 +
arch/xtensa/src/esp32s2/esp32s2_systemreset.c | 2 +-
arch/xtensa/src/esp32s2/esp32s2_tim.c | 56 +-
arch/xtensa/src/esp32s2/esp32s2_tim_lowerhalf.c | 2 +-
arch/xtensa/src/esp32s2/esp32s2_timerisr.c | 12 +-
arch/xtensa/src/esp32s2/esp32s2_touch.c | 176 +-
arch/xtensa/src/esp32s2/esp32s2_touch.h | 46 +
arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h | 41 +-
arch/xtensa/src/esp32s2/esp32s2_twai.c | 39 +-
arch/xtensa/src/esp32s2/esp32s2_wdt.c | 84 +-
arch/xtensa/src/esp32s2/esp32s2_wdt.h | 26 +-
arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.c | 14 +-
arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.h | 12 +-
arch/xtensa/src/esp32s2/esp32s2_wifi_adapter.c | 215 +-
arch/xtensa/src/esp32s2/hal.mk | 221 +-
arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h | 3305 -----------
arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h | 5087 -----------------
arch/xtensa/src/esp32s3/Kconfig | 51 +-
arch/xtensa/src/esp32s3/Make.defs | 26 +-
arch/xtensa/src/esp32s3/chip.h | 6 +-
arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c | 280 +-
arch/xtensa/src/esp32s3/esp32s3_cam.c | 87 +-
arch/xtensa/src/esp32s3/esp32s3_clockconfig.c | 271 -
arch/xtensa/src/esp32s3/esp32s3_clockconfig.h | 90 -
arch/xtensa/src/esp32s3/esp32s3_cpustart.c | 56 +-
arch/xtensa/src/esp32s3/esp32s3_dma.c | 2 +-
arch/xtensa/src/esp32s3/esp32s3_freerun.c | 4 +-
arch/xtensa/src/esp32s3/esp32s3_gpio.c | 626 ---
arch/xtensa/src/esp32s3/esp32s3_i2c.c | 39 +-
arch/xtensa/src/esp32s3/esp32s3_irq.c | 1265 -----
arch/xtensa/src/esp32s3/esp32s3_irq.h | 263 -
arch/xtensa/src/esp32s3/esp32s3_lcd.c | 26 +-
arch/xtensa/src/esp32s3/esp32s3_lowputc.c | 57 +-
arch/xtensa/src/esp32s3/esp32s3_lowputc.h | 3 +-
arch/xtensa/src/esp32s3/esp32s3_oneshot.c | 2 +-
arch/xtensa/src/esp32s3/esp32s3_otg_device.c | 33 +-
arch/xtensa/src/esp32s3/esp32s3_psram_octal.c | 2 +-
arch/xtensa/src/esp32s3/esp32s3_psram_quad.c | 8 +-
arch/xtensa/src/esp32s3/esp32s3_qspi.c | 90 +-
arch/xtensa/src/esp32s3/esp32s3_reset_reasons.c | 4 +-
arch/xtensa/src/esp32s3/esp32s3_rng.c | 2 +-
arch/xtensa/src/esp32s3/esp32s3_rt_timer.c | 1054 ----
arch/xtensa/src/esp32s3/esp32s3_rt_timer.h | 244 -
arch/xtensa/src/esp32s3/esp32s3_rtc.c | 3112 ----------
arch/xtensa/src/esp32s3/esp32s3_rtc.h | 807 ---
arch/xtensa/src/esp32s3/esp32s3_rtc_gpio.c | 138 +-
arch/xtensa/src/esp32s3/esp32s3_rtc_gpio.h | 57 +-
arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.c | 559 --
arch/xtensa/src/esp32s3/esp32s3_sdmmc.c | 64 +-
arch/xtensa/src/esp32s3/esp32s3_serial.c | 31 +-
arch/xtensa/src/esp32s3/esp32s3_spi.c | 80 +-
arch/xtensa/src/esp32s3/esp32s3_spi_slave.c | 114 +-
arch/xtensa/src/esp32s3/esp32s3_spi_timing.c | 2 +-
arch/xtensa/src/esp32s3/esp32s3_spiflash.c | 12 +-
arch/xtensa/src/esp32s3/esp32s3_start.c | 79 +-
arch/xtensa/src/esp32s3/esp32s3_start.h | 20 +
arch/xtensa/src/esp32s3/esp32s3_systemreset.c | 4 +-
arch/xtensa/src/esp32s3/esp32s3_tickless.c | 10 +-
arch/xtensa/src/esp32s3/esp32s3_tim.c | 23 +-
arch/xtensa/src/esp32s3/esp32s3_tim_lowerhalf.c | 2 +-
arch/xtensa/src/esp32s3/esp32s3_timerisr.c | 29 +-
arch/xtensa/src/esp32s3/esp32s3_touch.c | 144 +-
arch/xtensa/src/esp32s3/esp32s3_touch.h | 46 +
arch/xtensa/src/esp32s3/esp32s3_touch_lowerhalf.h | 224 +-
arch/xtensa/src/esp32s3/esp32s3_twai.c | 45 +-
arch/xtensa/src/esp32s3/esp32s3_usbserial.c | 24 +-
arch/xtensa/src/esp32s3/esp32s3_userspace.c | 28 +-
arch/xtensa/src/esp32s3/esp32s3_wdt.c | 113 +-
arch/xtensa/src/esp32s3/esp32s3_wdt.h | 26 +-
arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c | 37 +-
arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.h | 12 +-
arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c | 212 +-
arch/xtensa/src/esp32s3/hal.mk | 240 +-
arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h | 3245 -----------
arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h | 5914 --------------------
arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h | 5 +-
boards/Kconfig | 48 +-
.../xtensa/esp32/common/include/esp32_board_rmt.h | 6 +-
.../xtensa/esp32/common/scripts/esp32_sections.ld | 93 +-
boards/xtensa/esp32/common/scripts/flat_memory.ld | 21 +-
boards/xtensa/esp32/common/scripts/kernel-space.ld | 119 +-
.../xtensa/esp32/common/scripts/legacy_sections.ld | 4 +-
.../esp32/common/scripts/mcuboot_sections.ld | 2 +
.../esp32/common/scripts/protected_memory.ld | 35 +
boards/xtensa/esp32/common/src/esp32_backlight.c | 8 +-
.../esp32/common/src/esp32_board_apa102_lcd.c | 3 +-
.../xtensa/esp32/common/src/esp32_board_apds9960.c | 11 +-
boards/xtensa/esp32/common/src/esp32_board_rmt.c | 10 +-
boards/xtensa/esp32/common/src/esp32_board_spi.c | 4 +-
.../xtensa/esp32/common/src/esp32_board_spiflash.c | 9 +-
boards/xtensa/esp32/common/src/esp32_gc9a01.c | 16 +-
boards/xtensa/esp32/common/src/esp32_ili9341.c | 18 +-
boards/xtensa/esp32/common/src/esp32_mcp2515.c | 14 +-
boards/xtensa/esp32/common/src/esp32_rgbled.c | 3 +-
boards/xtensa/esp32/common/src/esp32_ssd1306.c | 10 +-
boards/xtensa/esp32/common/src/esp32_ssd1680.c | 16 +-
boards/xtensa/esp32/common/src/esp32_st7789.c | 16 +-
boards/xtensa/esp32/common/src/esp32_zerocross.c | 11 +-
.../esp32/esp32-2432S028/configs/lvgl/defconfig | 3 +
.../esp32/esp32-2432S028/configs/nsh/defconfig | 3 +
.../esp32/esp32-2432S028/src/esp32_bringup.c | 32 +-
.../esp32/esp32-audio-kit/configs/audio/defconfig | 3 +
.../esp32/esp32-audio-kit/configs/nsh/defconfig | 3 +
.../esp32/esp32-audio-kit/configs/wifi/defconfig | 3 +
.../esp32/esp32-audio-kit/src/esp32_bringup.c | 39 +-
.../esp32/esp32-audio-kit/src/esp32_buttons.c | 42 +-
.../xtensa/esp32/esp32-audio-kit/src/esp32_gpio.c | 44 +-
.../esp32/esp32-audio-kit/src/esp32_userleds.c | 9 +-
.../esp32/esp32-devkitc/configs/adc/defconfig | 3 +
.../esp32/esp32-devkitc/configs/audio/defconfig | 3 +
.../esp32/esp32-devkitc/configs/autopm/defconfig | 3 +
.../esp32/esp32-devkitc/configs/ble/defconfig | 3 +
.../esp32/esp32-devkitc/configs/blewifi/defconfig | 4 +-
.../esp32/esp32-devkitc/configs/bmp280/defconfig | 5 +-
.../esp32-devkitc/configs/brickmatch/defconfig | 3 +
.../esp32/esp32-devkitc/configs/buttons/defconfig | 6 +-
.../esp32/esp32-devkitc/configs/capture/defconfig | 3 +
.../esp32/esp32-devkitc/configs/coremark/defconfig | 3 +
.../esp32/esp32-devkitc/configs/crypto/defconfig | 4 +
.../esp32/esp32-devkitc/configs/cxx/defconfig | 3 +
.../esp32/esp32-devkitc/configs/dac/defconfig | 3 +
.../esp32/esp32-devkitc/configs/efuse/defconfig | 5 +
.../esp32/esp32-devkitc/configs/elf/defconfig | 3 +
.../esp32/esp32-devkitc/configs/espnow/defconfig | 3 +
.../esp32/esp32-devkitc/configs/gpio/defconfig | 3 +
.../esp32/esp32-devkitc/configs/i2c/defconfig | 3 +
.../esp32/esp32-devkitc/configs/i2schar/defconfig | 3 +
.../esp32/esp32-devkitc/configs/knsh/defconfig | 3 +
.../esp32/esp32-devkitc/configs/leds/defconfig | 3 +
.../esp32/esp32-devkitc/configs/match4/defconfig | 5 +-
.../esp32/esp32-devkitc/configs/max6675/defconfig | 3 +
.../esp32/esp32-devkitc/configs/mcp2515/defconfig | 3 +
.../esp32-devkitc/configs/mcuboot_nsh/defconfig | 3 +
.../configs/mcuboot_slot_confirm/defconfig | 3 +
.../configs/mcuboot_update_agent/defconfig | 3 +
.../esp32/esp32-devkitc/configs/modbus/defconfig | 3 +
.../esp32/esp32-devkitc/configs/module/defconfig | 3 +
.../esp32/esp32-devkitc/configs/motor/defconfig | 3 +
.../esp32/esp32-devkitc/configs/mqttc/defconfig | 3 +
.../esp32/esp32-devkitc/configs/ms5611/defconfig | 5 +-
.../esp32/esp32-devkitc/configs/nsh/defconfig | 3 +
.../esp32/esp32-devkitc/configs/nvblk/defconfig | 3 +
.../esp32/esp32-devkitc/configs/nxdiag/defconfig | 3 +
.../esp32/esp32-devkitc/configs/nxlooper/defconfig | 3 +
.../esp32/esp32-devkitc/configs/oneshot/defconfig | 5 +-
.../esp32/esp32-devkitc/configs/ostest/defconfig | 3 +
.../esp32/esp32-devkitc/configs/pm/defconfig | 3 +
.../esp32/esp32-devkitc/configs/psram/defconfig | 3 +
.../esp32-devkitc/configs/psram_usrheap/defconfig | 3 +
.../esp32/esp32-devkitc/configs/pwm/defconfig | 3 +
.../esp32-devkitc/configs/qemu_openeth/defconfig | 3 +
.../esp32/esp32-devkitc/configs/qencoder/defconfig | 3 +
.../esp32/esp32-devkitc/configs/random/defconfig | 3 +
.../esp32/esp32-devkitc/configs/rmt/defconfig | 3 +
.../esp32/esp32-devkitc/configs/romfs/defconfig | 3 +
.../esp32/esp32-devkitc/configs/rtc/defconfig | 4 +-
.../esp32/esp32-devkitc/configs/sdm/defconfig | 3 +
.../esp32-devkitc/configs/sdmmc_spi/defconfig | 3 +
.../esp32/esp32-devkitc/configs/smp/defconfig | 3 +
.../esp32/esp32-devkitc/configs/snake/defconfig | 5 +-
.../esp32/esp32-devkitc/configs/softap/defconfig | 3 +
.../esp32/esp32-devkitc/configs/sotest/defconfig | 3 +
.../esp32/esp32-devkitc/configs/spi/defconfig | 3 +
.../esp32/esp32-devkitc/configs/spiflash/defconfig | 3 +
.../esp32-devkitc/configs/sta_softap/defconfig | 3 +
.../esp32/esp32-devkitc/configs/tickless/defconfig | 3 +
.../esp32/esp32-devkitc/configs/timer/defconfig | 4 +-
.../esp32/esp32-devkitc/configs/twai/defconfig | 3 +
.../configs/wamr_wasi_debug/defconfig | 3 +
.../esp32/esp32-devkitc/configs/watchdog/defconfig | 3 +
.../esp32/esp32-devkitc/configs/watcher/defconfig | 3 +
.../esp32/esp32-devkitc/configs/wifi/defconfig | 3 +
.../esp32/esp32-devkitc/configs/wifi_smp/defconfig | 3 +
.../esp32/esp32-devkitc/configs/wifinsh/defconfig | 3 +
.../esp32-devkitc/configs/wifishare/defconfig | 3 +
.../xtensa/esp32/esp32-devkitc/src/esp32_bringup.c | 50 +-
.../xtensa/esp32/esp32-devkitc/src/esp32_buttons.c | 42 +-
boards/xtensa/esp32/esp32-devkitc/src/esp32_gpio.c | 50 +-
.../esp32/esp32-devkitc/src/esp32_userleds.c | 9 +-
.../xtensa/esp32/esp32-devkitc/src/esp32_w5500.c | 25 +-
.../esp32-ethernet-kit/configs/autopm/defconfig | 3 +
.../esp32-ethernet-kit/configs/buttons/defconfig | 5 +-
.../esp32-ethernet-kit/configs/ethernet/defconfig | 3 +
.../esp32/esp32-ethernet-kit/configs/nsh/defconfig | 3 +
.../esp32-ethernet-kit/configs/oneshot/defconfig | 5 +-
.../esp32/esp32-ethernet-kit/configs/rtc/defconfig | 4 +-
.../esp32-ethernet-kit/configs/wifi/defconfig | 3 +
.../esp32/esp32-ethernet-kit/src/esp32_bringup.c | 32 +-
.../esp32/esp32-ethernet-kit/src/esp32_buttons.c | 42 +-
.../esp32/esp32-lyrat/configs/audio/defconfig | 3 +
.../esp32/esp32-lyrat/configs/buttons/defconfig | 5 +-
.../xtensa/esp32/esp32-lyrat/configs/nsh/defconfig | 3 +
.../esp32/esp32-lyrat/configs/nxrecorder/defconfig | 3 +
.../esp32/esp32-lyrat/configs/rtptools/defconfig | 3 +
.../esp32/esp32-lyrat/configs/sdmmc_spi/defconfig | 3 +
.../esp32/esp32-lyrat/configs/wifi/defconfig | 3 +
.../xtensa/esp32/esp32-lyrat/src/esp32_bringup.c | 37 +-
.../xtensa/esp32/esp32-lyrat/src/esp32_buttons.c | 51 +-
boards/xtensa/esp32/esp32-lyrat/src/esp32_gpio.c | 44 +-
.../xtensa/esp32/esp32-lyrat/src/esp32_userleds.c | 9 +-
.../esp32/esp32-pico-kit/configs/nsh/defconfig | 3 +
.../esp32/esp32-pico-kit/src/esp32_bringup.c | 32 +-
.../esp32/esp32-pico-kit/src/esp32_buttons.c | 42 +-
.../xtensa/esp32/esp32-pico-kit/src/esp32_gpio.c | 44 +-
.../esp32/esp32-sparrow-kit/configs/ble/defconfig | 4 +-
.../esp32-sparrow-kit/configs/mqttc/defconfig | 4 +-
.../esp32/esp32-sparrow-kit/configs/nsh/defconfig | 4 +-
.../esp32/esp32-sparrow-kit/configs/wifi/defconfig | 4 +-
.../esp32/esp32-sparrow-kit/src/esp32_autoleds.c | 32 +-
.../esp32/esp32-sparrow-kit/src/esp32_bringup.c | 32 +-
.../esp32/esp32-sparrow-kit/src/esp32_buttons.c | 42 +-
.../esp32/esp32-sparrow-kit/src/esp32_gpio.c | 44 +-
.../esp32/esp32-sparrow-kit/src/esp32_userleds.c | 8 +-
.../esp32-wrover-kit/configs/autopm/defconfig | 3 +
.../esp32-wrover-kit/configs/bmp180/defconfig | 3 +
.../esp32-wrover-kit/configs/buttons/defconfig | 5 +-
.../esp32/esp32-wrover-kit/configs/gpio/defconfig | 5 +-
.../esp32-wrover-kit/configs/lcd1602/defconfig | 3 +
.../esp32/esp32-wrover-kit/configs/leds/defconfig | 3 +
.../esp32/esp32-wrover-kit/configs/lua/defconfig | 3 +
.../esp32/esp32-wrover-kit/configs/lvgl/defconfig | 3 +
.../esp32/esp32-wrover-kit/configs/nsh/defconfig | 3 +
.../esp32/esp32-wrover-kit/configs/nx/defconfig | 3 +
.../esp32-wrover-kit/configs/oneshot/defconfig | 5 +-
.../esp32/esp32-wrover-kit/configs/rtc/defconfig | 4 +-
.../esp32-wrover-kit/configs/sdmmc_spi/defconfig | 3 +
.../esp32/esp32-wrover-kit/configs/wifi/defconfig | 3 +
.../esp32/esp32-wrover-kit/src/esp32_autoleds.c | 32 +-
.../esp32/esp32-wrover-kit/src/esp32_bringup.c | 32 +-
.../esp32/esp32-wrover-kit/src/esp32_buttons.c | 42 +-
.../xtensa/esp32/esp32-wrover-kit/src/esp32_gpio.c | 44 +-
.../esp32/esp32-wrover-kit/src/esp32_userleds.c | 9 +-
.../esp32/heltec_wifi_lora32/configs/nsh/defconfig | 3 +
.../heltec_wifi_lora32/configs/sx1276/defconfig | 3 +
.../esp32/heltec_wifi_lora32/src/esp32_bringup.c | 14 +
.../esp32/heltec_wifi_lora32/src/esp32_sx127x.c | 8 +-
.../lilygo_tbeam_lora_gps/configs/gps/defconfig | 3 +
.../lilygo_tbeam_lora_gps/configs/nsh/defconfig | 3 +
.../lilygo_tbeam_lora_gps/configs/sx127x/defconfig | 3 +
.../lilygo_tbeam_lora_gps/src/esp32_bringup.c | 32 +-
.../lilygo_tbeam_lora_gps/src/esp32_buttons.c | 42 +-
.../esp32/lilygo_tbeam_lora_gps/src/esp32_gpio.c | 44 +-
.../esp32/lilygo_tbeam_lora_gps/src/esp32_sx127x.c | 18 +-
.../lilygo_tbeam_lora_gps/src/esp32_userleds.c | 9 +-
.../esp32/ttgo_eink5_v2/configs/fb/defconfig | 3 +
.../xtensa/esp32/ttgo_eink5_v2/src/esp32_bringup.c | 32 +-
.../xtensa/esp32/ttgo_eink5_v2/src/esp32_buttons.c | 46 +-
boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_gpio.c | 44 +-
.../esp32/ttgo_eink5_v2/src/esp32_userleds.c | 9 +-
.../esp32/ttgo_lora_esp32/configs/nsh/defconfig | 3 +
.../esp32/ttgo_lora_esp32/configs/sx127x/defconfig | 3 +
.../esp32/ttgo_lora_esp32/src/esp32_bringup.c | 32 +-
.../esp32/ttgo_lora_esp32/src/esp32_buttons.c | 42 +-
.../xtensa/esp32/ttgo_lora_esp32/src/esp32_gpio.c | 44 +-
.../esp32/ttgo_lora_esp32/src/esp32_sx127x.c | 18 +-
.../esp32/ttgo_lora_esp32/src/esp32_userleds.c | 9 +-
.../ttgo_t_display_esp32/configs/lvgl_fb/defconfig | 3 +
.../configs/lvgl_lcd/defconfig | 3 +
.../ttgo_t_display_esp32/configs/nsh/defconfig | 3 +
.../esp32/ttgo_t_display_esp32/src/esp32_bringup.c | 32 +-
.../esp32/ttgo_t_display_esp32/src/esp32_buttons.c | 42 +-
.../esp32/ttgo_t_display_esp32/src/esp32_gpio.c | 44 +-
.../ttgo_t_display_esp32/src/esp32_userleds.c | 9 +-
.../esp32s2/common/include/esp32s2_board_rmt.h | 6 +-
.../esp32s2/common/scripts/esp32s2_sections.ld | 34 +-
.../xtensa/esp32s2/common/scripts/flat_memory.ld | 4 +-
.../esp32s2/common/scripts/mcuboot_sections.ld | 3 +
.../xtensa/esp32s2/common/src/esp32s2_board_rmt.c | 16 +-
.../xtensa/esp32s2/common/src/esp32s2_board_spi.c | 6 +-
.../esp32s2/common/src/esp32s2_board_spiflash.c | 9 +-
.../xtensa/esp32s2/common/src/esp32s2_board_wdt.c | 1 -
boards/xtensa/esp32s2/common/src/esp32s2_ili9341.c | 18 +-
boards/xtensa/esp32s2/common/src/esp32s2_st7789.c | 16 +-
.../esp32s2-kaluga-1/configs/audio/defconfig | 3 +
.../esp32s2-kaluga-1/configs/buttons/defconfig | 5 +-
.../esp32s2/esp32s2-kaluga-1/configs/i2c/defconfig | 3 +
.../configs/lvgl_ili9341/defconfig | 3 +
.../esp32s2-kaluga-1/configs/lvgl_st7789/defconfig | 3 +
.../esp32s2/esp32s2-kaluga-1/configs/nsh/defconfig | 3 +
.../esp32s2-kaluga-1/configs/nxlooper/defconfig | 3 +
.../esp32s2/esp32s2-kaluga-1/configs/rtc/defconfig | 4 +-
.../esp32s2-kaluga-1/configs/twai/defconfig | 3 +
.../esp32s2-kaluga-1/configs/watchdog/defconfig | 3 +
.../esp32s2/esp32s2-kaluga-1/src/esp32s2_bringup.c | 35 +-
.../esp32s2/esp32s2-kaluga-1/src/esp32s2_buttons.c | 49 +-
.../esp32s2/esp32s2-kaluga-1/src/esp32s2_gpio.c | 62 +-
.../esp32s2/esp32s2-saola-1/configs/adc/defconfig | 3 +
.../esp32s2-saola-1/configs/audio/defconfig | 3 +
.../esp32s2-saola-1/configs/buttons/defconfig | 5 +-
.../esp32s2-saola-1/configs/coremark/defconfig | 3 +
.../esp32s2-saola-1/configs/crypto/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/cxx/defconfig | 3 +
.../esp32s2-saola-1/configs/efuse/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/gpio/defconfig | 5 +-
.../esp32s2/esp32s2-saola-1/configs/i2c/defconfig | 3 +
.../esp32s2-saola-1/configs/i2schar/defconfig | 3 +
.../esp32s2-saola-1/configs/mcuboot_nsh/defconfig | 3 +
.../configs/mcuboot_update_agent/defconfig | 6 +-
.../esp32s2/esp32s2-saola-1/configs/nsh/defconfig | 3 +
.../esp32s2-saola-1/configs/nxlooper/defconfig | 3 +
.../esp32s2-saola-1/configs/oneshot/defconfig | 3 +
.../esp32s2-saola-1/configs/ostest/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/pm/defconfig | 5 +
.../esp32s2/esp32s2-saola-1/configs/pwm/defconfig | 3 +
.../esp32s2-saola-1/configs/qencoder/defconfig | 3 +
.../esp32s2-saola-1/configs/random/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/rmt/defconfig | 3 +
.../esp32s2-saola-1/configs/romfs/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/rtc/defconfig | 4 +-
.../esp32s2/esp32s2-saola-1/configs/sdm/defconfig | 3 +
.../esp32s2-saola-1/configs/sdmmc_spi/defconfig | 3 +
.../esp32s2-saola-1/configs/sotest/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/spi/defconfig | 3 +
.../esp32s2-saola-1/configs/spiflash/defconfig | 3 +
.../esp32s2-saola-1/configs/sta_softap/defconfig | 5 +
.../configs/temperature_sensor/defconfig | 4 +
.../esp32s2-saola-1/configs/timer/defconfig | 4 +-
.../esp32s2/esp32s2-saola-1/configs/twai/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/ulp/defconfig | 5 +-
.../esp32s2-saola-1/configs/watchdog/defconfig | 3 +
.../esp32s2/esp32s2-saola-1/configs/wifi/defconfig | 5 +
.../esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c | 35 +-
.../esp32s2/esp32s2-saola-1/src/esp32s2_buttons.c | 48 +-
.../esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c | 65 +-
.../esp32s2/franzininho-wifi/configs/nsh/defconfig | 3 +
.../esp32s2/franzininho-wifi/src/esp32s2_bringup.c | 26 +-
boards/xtensa/esp32s3/common/Makefile | 1 +
.../esp32s3/common/include/esp32s3_board_rmt.h | 6 +-
.../esp32s3/common/scripts/esp32s3_sections.ld | 31 +-
.../xtensa/esp32s3/common/scripts/kernel-space.ld | 7 +
.../esp32s3/common/scripts/legacy_sections.ld | 4 +-
.../esp32s3/common/scripts/mcuboot_sections.ld | 4 +-
.../esp32s3/common/scripts/protected_memory.ld | 2 -
.../xtensa/esp32s3/common/src/esp32s3_board_rmt.c | 10 +-
.../esp32s3/common/src/esp32s3_board_spiflash.c | 5 +-
.../xtensa/esp32s3/common/src/esp32s3_board_wdt.c | 2 -
boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c | 26 +-
.../esp32s3-8048S043/configs/gpio/defconfig | 3 +
.../esp32s3/esp32s3-8048S043/configs/i2c/defconfig | 3 +
.../esp32s3/esp32s3-8048S043/configs/lcd/defconfig | 3 +
.../esp32s3/esp32s3-8048S043/configs/nsh/defconfig | 3 +
.../esp32s3-8048S043/configs/sdmmc/defconfig | 3 +
.../esp32s3/esp32s3-8048S043/configs/spi/defconfig | 3 +
.../esp32s3-8048S043/configs/touchscreen/defconfig | 3 +
.../esp32s3-8048S043/src/esp32s3_board_spi.c | 2 +-
.../src/esp32s3_board_touchsceen.c | 2 +-
.../esp32s3/esp32s3-8048S043/src/esp32s3_bringup.c | 19 +-
.../esp32s3/esp32s3-8048S043/src/esp32s3_buttons.c | 42 +-
.../esp32s3/esp32s3-8048S043/src/esp32s3_gpio.c | 50 +-
.../esp32s3/esp32s3-8048S043/src/esp32s3_lcd.c | 6 +-
.../esp32s3/esp32s3-box/configs/buttons/defconfig | 3 +
.../esp32s3/esp32s3-box/configs/lvgl-3/defconfig | 3 +
.../esp32s3/esp32s3-box/configs/lvgl/defconfig | 3 +
.../esp32s3/esp32s3-box/configs/nsh/defconfig | 3 +
.../esp32s3-box/configs/touchscreen/defconfig | 3 +
.../esp32s3-box/src/esp32s3_board_lcd_ili9342c.c | 21 +-
.../esp32s3-box/src/esp32s3_board_lcd_st7789.c | 14 +-
.../esp32s3/esp32s3-box/src/esp32s3_board_spi.c | 6 +-
.../src/esp32s3_board_touchsceen_gt911.c | 2 +-
.../src/esp32s3_board_touchsceen_tt21100.c | 2 +-
.../esp32s3/esp32s3-box/src/esp32s3_bringup.c | 31 +-
.../esp32s3/esp32s3-box/src/esp32s3_buttons.c | 42 +-
.../esp32s3/esp32s3-devkit/configs/adc/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/audio/defconfig | 5 +
.../esp32s3/esp32s3-devkit/configs/ble/defconfig | 6 +-
.../esp32s3-devkit/configs/blewifi/defconfig | 6 +-
.../esp32s3-devkit/configs/buttons/defconfig | 3 +
.../esp32s3-devkit/configs/capture/defconfig | 3 +
.../esp32s3-devkit/configs/coremark/defconfig | 3 +
.../esp32s3-devkit/configs/crypto/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/cxx/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/efuse/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/elf/defconfig | 3 +
.../esp32s3-devkit/configs/eth_lan9250/defconfig | 3 +
.../esp32s3-devkit/configs/fastboot/defconfig | 6 +-
.../esp32s3-devkit/configs/fastboot_tcp/defconfig | 6 +-
.../esp32s3/esp32s3-devkit/configs/gpio/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/i2c/defconfig | 3 +
.../esp32s3-devkit/configs/i2schar/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/knsh/defconfig | 3 +
.../esp32s3-devkit/configs/ksta_softap/defconfig | 6 +-
.../esp32s3-devkit/configs/mbedtls/defconfig | 7 +-
.../esp32s3-devkit/configs/mcuboot_nsh/defconfig | 3 +
.../configs/mcuboot_update_agent/defconfig | 6 +-
.../esp32s3/esp32s3-devkit/configs/motor/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/nsh/defconfig | 3 +
.../esp32s3-devkit/configs/nxlooper/defconfig | 3 +
.../esp32s3-devkit/configs/oneshot/defconfig | 5 +-
.../esp32s3-devkit/configs/ostest/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/pm/defconfig | 5 +
.../esp32s3-devkit/configs/psram_octal/defconfig | 3 +
.../esp32s3-devkit/configs/psram_quad/defconfig | 3 +
.../esp32s3-devkit/configs/psram_usrheap/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/pwm/defconfig | 3 +
.../esp32s3-devkit/configs/python/defconfig | 6 +-
.../esp32s3-devkit/configs/qemu_debug/defconfig | 7 +-
.../esp32s3-devkit/configs/qemu_openeth/defconfig | 3 +
.../esp32s3-devkit/configs/qemu_toywasm/defconfig | 7 +-
.../esp32s3-devkit/configs/qencoder/defconfig | 3 +
.../esp32s3-devkit/configs/random/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/rmt/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/romfs/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/rtc/defconfig | 4 +-
.../esp32s3/esp32s3-devkit/configs/sdm/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/sdmmc/defconfig | 3 +
.../esp32s3-devkit/configs/sdmmc_spi/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/smp/defconfig | 3 +
.../esp32s3-devkit/configs/sotest/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/spi/defconfig | 3 +
.../esp32s3-devkit/configs/spiflash/defconfig | 3 +
.../esp32s3-devkit/configs/spislv/defconfig | 3 +
.../esp32s3-devkit/configs/sta_softap/defconfig | 5 +
.../esp32s3/esp32s3-devkit/configs/stack/defconfig | 5 +
.../configs/temperature_sensor/defconfig | 3 +
.../esp32s3-devkit/configs/tickless/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/timer/defconfig | 3 +
.../esp32s3-devkit/configs/toywasm/defconfig | 6 +-
.../esp32s3/esp32s3-devkit/configs/twai/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/ulp/defconfig | 3 +
.../esp32s3-devkit/configs/usb_device/defconfig | 3 +
.../esp32s3-devkit/configs/usbnsh/defconfig | 3 +
.../esp32s3-devkit/configs/watchdog/defconfig | 3 +
.../esp32s3/esp32s3-devkit/configs/wifi/defconfig | 5 +
boards/xtensa/esp32s3/esp32s3-devkit/src/Make.defs | 8 +
.../esp32s3/esp32s3-devkit/src/esp32s3_board_spi.c | 6 +-
.../esp32s3/esp32s3-devkit/src/esp32s3_bringup.c | 39 +-
.../esp32s3/esp32s3-devkit/src/esp32s3_buttons.c | 42 +-
.../esp32s3/esp32s3-devkit/src/esp32s3_djoystick.c | 32 +-
.../esp32s3/esp32s3-devkit/src/esp32s3_gpio.c | 61 +-
.../esp32s3/esp32s3-devkit/src/esp32s3_st7735.c | 12 +-
.../esp32s3/esp32s3-eye/configs/gpio/defconfig | 3 +
.../esp32s3/esp32s3-eye/configs/i2c/defconfig | 3 +
.../esp32s3/esp32s3-eye/configs/lcd/defconfig | 3 +
.../esp32s3/esp32s3-eye/configs/nsh/defconfig | 3 +
.../esp32s3/esp32s3-eye/configs/usbnsh/defconfig | 3 +
.../esp32s3/esp32s3-eye/configs/wifi/defconfig | 6 +-
.../esp32s3/esp32s3-eye/src/esp32s3_board_lcd.c | 8 +-
.../esp32s3/esp32s3-eye/src/esp32s3_board_spi.c | 6 +-
.../esp32s3/esp32s3-eye/src/esp32s3_bringup.c | 27 +-
.../esp32s3/esp32s3-eye/src/esp32s3_buttons.c | 42 +-
.../xtensa/esp32s3/esp32s3-eye/src/esp32s3_gpio.c | 46 +-
.../esp32s3-korvo-2/configs/audio/defconfig | 5 +
.../esp32s3/esp32s3-korvo-2/configs/nsh/defconfig | 3 +
.../esp32s3-korvo-2/configs/rtptools/defconfig | 5 +
.../esp32s3-korvo-2/configs/sdmmc/defconfig | 3 +
.../esp32s3-korvo-2/src/esp32s3_board_spi.c | 6 +-
.../esp32s3/esp32s3-korvo-2/src/esp32s3_bringup.c | 40 +-
.../esp32s3/esp32s3-korvo-2/src/esp32s3_buttons.c | 42 +-
.../esp32s3/esp32s3-lcd-ev/configs/audio/defconfig | 5 +
.../esp32s3-lcd-ev/configs/buttons/defconfig | 3 +
.../esp32s3/esp32s3-lcd-ev/configs/lcd/defconfig | 3 +
.../esp32s3/esp32s3-lcd-ev/configs/lvgl/defconfig | 3 +
.../esp32s3/esp32s3-lcd-ev/configs/nsh/defconfig | 3 +
.../esp32s3-lcd-ev/configs/ws2812/defconfig | 3 +
.../esp32s3/esp32s3-lcd-ev/src/esp32s3_board_spi.c | 6 +-
.../esp32s3/esp32s3-lcd-ev/src/esp32s3_bringup.c | 36 +-
.../esp32s3/esp32s3-lcd-ev/src/esp32s3_buttons.c | 42 +-
.../esp32s3/esp32s3-lcd-ev/src/esp32s3_lcd.c | 10 +-
.../esp32s3-lhcbit/configs/usbnsh/defconfig | 3 +
.../esp32s3/esp32s3-lhcbit/src/esp32s3_bringup.c | 15 +
.../esp32s3/esp32s3-meadow/configs/nsh/defconfig | 3 +
.../esp32s3-meadow/configs/usbnsh/defconfig | 3 +
.../esp32s3/esp32s3-meadow/src/esp32s3_bringup.c | 27 +-
.../esp32s3/esp32s3-xiao/configs/combo/defconfig | 3 +
.../esp32s3/esp32s3-xiao/configs/usbnsh/defconfig | 3 +
.../esp32s3/esp32s3-xiao/src/esp32s3_autoleds.c | 10 +-
.../esp32s3/esp32s3-xiao/src/esp32s3_bringup.c | 15 +
.../xtensa/esp32s3/esp32s3-xiao/src/esp32s3_gpio.c | 43 +-
.../esp32s3/esp32s3-xiao/src/esp32s3_userleds.c | 9 +-
.../lckfb-szpi-esp32s3/configs/camera/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/fastboot/defconfig | 6 +-
.../configs/fastboot_tcp/defconfig | 6 +-
.../lckfb-szpi-esp32s3/configs/gc0308/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/gpio/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/lcd/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/lvgl/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/nsh/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/pca9557/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/psram/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/pwm/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/qmi8658/defconfig | 3 +
.../lckfb-szpi-esp32s3/configs/sdmmc/defconfig | 3 +
.../configs/usb_device/defconfig | 3 +
.../lckfb-szpi-esp32s3/src/esp32s3_board_lcd.c | 2 +-
.../lckfb-szpi-esp32s3/src/esp32s3_board_spi.c | 6 +-
.../lckfb-szpi-esp32s3/src/esp32s3_bringup.c | 32 +-
.../esp32s3/lckfb-szpi-esp32s3/src/esp32s3_gpio.c | 49 +-
621 files changed, 11279 insertions(+), 53135 deletions(-)
diff --git a/arch/risc-v/src/common/espressif/Make.defs b/arch/risc-v/src/common/espressif/Make.defs
index 83b63741cfb..f1d10a6439c 100644
--- a/arch/risc-v/src/common/espressif/Make.defs
+++ b/arch/risc-v/src/common/espressif/Make.defs
@@ -207,7 +207,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
- ESP_HAL_3RDPARTY_VERSION = a85ce2f1bad9f745090146eb30a18d91b8ddd309
+ ESP_HAL_3RDPARTY_VERSION = 6c272b562a73107a852d44b9c6fb5df57245cbd7
endif
ifndef ESP_HAL_3RDPARTY_URL
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index bc148aec073..5f25569d866 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -22,6 +22,7 @@ config ARCH_CHIP_ESP32
select ARCH_HAVE_TESTSET
select ARCH_HAVE_TEXT_HEAP
select ARCH_VECNOTIRQ
+ select ARCH_MINIMAL_VECTORTABLE
select LIBC_PREVENT_STRING_KERNEL
select LIBC_ARCH_MEMCPY if BUILD_FLAT
select LIBC_ARCH_MEMCHR if BUILD_FLAT
@@ -56,6 +57,7 @@ config ARCH_CHIP_ESP32S2
select ARCH_HAVE_RESET
select ARCH_HAVE_TEXT_HEAP
select ARCH_VECNOTIRQ
+ select ARCH_MINIMAL_VECTORTABLE
select LIBC_ARCH_MEMCPY
select LIBC_ARCH_MEMCHR
select LIBC_ARCH_MEMCMP
@@ -92,6 +94,7 @@ config ARCH_CHIP_ESP32S3
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_VECNOTIRQ
+ select ARCH_MINIMAL_VECTORTABLE
select LIBC_PREVENT_STRING_KERNEL
select LIBC_ARCH_MEMCPY if BUILD_FLAT
select LIBC_ARCH_MEMCHR if BUILD_FLAT
diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h
index 3bc5270d6a6..6d603dbb555 100644
--- a/arch/xtensa/include/esp32/irq.h
+++ b/arch/xtensa/include/esp32/irq.h
@@ -39,7 +39,7 @@
/* CPU interrupt flags:
* These flags can be used to specify which interrupt qualities the
- * code calling esp32_setup_irq needs.
+ * code calling esp_setup_irq needs.
*/
#define ESP32_CPUINT_FLAG_LEVEL (1 << 0) /* Level-triggered interrupt */
@@ -190,24 +190,39 @@
*/
/* IRQ numbers for internal interrupts that are dispatched like peripheral
- * interrupts
+ * interrupts. These use negative source IDs for internal CPU interrupts.
*/
+#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Platform timer 0 interrupt source */
+#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Platform timer 1 interrupt source */
+#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Platform timer 2 interrupt source */
+#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */
+#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */
+#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */
+
+#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)
+
+#define XTENSA_NIRQ_INTERNAL ETS_INTERNAL_INTR_SOURCE_OFF /* Number of dispatch internal interrupts */
+#define XTENSA_IRQ_DEMUX ETS_INTERNAL_INTR_SOURCE_OFF + 0 /* Demultiplexing IRQ for peripheral interrupts */
+#define XTENSA_IRQ_SYSCALL ETS_INTERNAL_INTR_SOURCE_OFF + 1 /* User interrupt w/EXCCAUSE=syscall */
+#define XTENSA_IRQ_FIRSTPERIPH ETS_INTERNAL_INTR_SOURCE_OFF + 2 /* First peripheral IRQ number */
+
+/* Legacy definitions for compatibility */
+
#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
-#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_SWINT 4 /* Software interrupt */
-#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */
-#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */
-
/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.
*/
-#define ESP32_IRQ2PERIPH(irq) ((irq)-XTENSA_IRQ_FIRSTPERIPH)
-#define ESP32_PERIPH2IRQ(id) ((id)+XTENSA_IRQ_FIRSTPERIPH)
+#define ESP32_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
+#define ESP32_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)
+
+#define ESP_IRQ2SOURCE(irq) ESP32_IRQ2PERIPH(irq)
+#define ESP_SOURCE2IRQ(id) ESP32_PERIPH2IRQ(id)
/* PRO_INTR_STATUS_REG_0 / APP_INTR_STATUS_REG_0 */
@@ -299,7 +314,7 @@
#define ESP32_NIRQ_PERIPH ESP32_NPERIPHERALS
-#ifdef CONFIG_ESP32_GPIO_IRQ
+#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
/* The PRO and APP CPU have different interrupts sources for the GPIO
* peripheral. Each CPU needs to allocate a separate interrupt and attach
@@ -325,6 +340,8 @@
# define ESP32_LAST_GPIOIRQ (ESP32_FIRST_GPIOIRQ+ESP32_NIRQ_GPIO-1)
# define ESP32_PIN2IRQ(p) ((p) + ESP32_FIRST_GPIOIRQ)
# define ESP32_IRQ2PIN(i) ((i) - ESP32_FIRST_GPIOIRQ)
+# define ESP_PIN2IRQ(p) ESP32_PIN2IRQ(p)
+# define ESP_IRQ2PIN(i) ESP32_IRQ2PIN(i)
#else
# define ESP32_NIRQ_GPIO 0
#endif
@@ -477,7 +494,7 @@
* Inline functions
****************************************************************************/
-#ifdef CONFIG_ESP32_GPIO_IRQ
+#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
#ifdef CONFIG_SMP
static inline_function int esp32_irq_gpio(int cpu)
{
diff --git a/arch/xtensa/include/esp32s2/irq.h b/arch/xtensa/include/esp32s2/irq.h
index 8a96597f211..d5b31d268c6 100644
--- a/arch/xtensa/include/esp32s2/irq.h
+++ b/arch/xtensa/include/esp32s2/irq.h
@@ -197,14 +197,19 @@
* interrupts
*/
-#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
-#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
-#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
-#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
-#define XTENSA_IRQ_SWINT 4 /* Software interrupt */
+#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Platform timer 0 interrupt source */
+#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Platform timer 1 interrupt source */
+#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Platform timer 2 interrupt source */
+#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */
+#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */
+#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */
-#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */
-#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */
+#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)
+
+#define XTENSA_NIRQ_INTERNAL ETS_INTERNAL_INTR_SOURCE_OFF /* Number of dispatch internal interrupts */
+#define XTENSA_IRQ_DEMUX ETS_INTERNAL_INTR_SOURCE_OFF + 0 /* Demultiplexing IRQ for peripheral interrupts */
+#define XTENSA_IRQ_SYSCALL ETS_INTERNAL_INTR_SOURCE_OFF + 1 /* User interrupt w/EXCCAUSE=syscall */
+#define XTENSA_IRQ_FIRSTPERIPH ETS_INTERNAL_INTR_SOURCE_OFF + 2 /* First peripheral IRQ number */
/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.
@@ -213,6 +218,9 @@
#define ESP32S2_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
#define ESP32S2_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)
+#define ESP_IRQ2SOURCE(irq) ESP32S2_IRQ2PERIPH(irq)
+#define ESP_SOURCE2IRQ(id) ESP32S2_PERIPH2IRQ(id)
+
#define ESP32S2_IRQ_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_MAC)
#define ESP32S2_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_MAC_NMI)
@@ -304,12 +312,14 @@
* interrupt handler. The second to the decoded GPIO interrupt handler.
*/
-#ifdef CONFIG_ESP32S2_GPIO_IRQ
+#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
# define ESP32S2_NIRQ_GPIO 47
# define ESP32S2_FIRST_GPIOIRQ (XTENSA_NIRQ_INTERNAL + ESP32S2_NIRQ_PERIPH)
# define ESP32S2_LAST_GPIOIRQ (ESP32S2_FIRST_GPIOIRQ + ESP32S2_NIRQ_GPIO - 1)
# define ESP32S2_PIN2IRQ(p) ((p) + ESP32S2_FIRST_GPIOIRQ)
# define ESP32S2_IRQ2PIN(i) ((i) - ESP32S2_FIRST_GPIOIRQ)
+# define ESP_PIN2IRQ(p) ESP32S2_PIN2IRQ(p)
+# define ESP_IRQ2PIN(i) ESP32S2_IRQ2PIN(i)
#else
# define ESP32S2_NIRQ_GPIO 0
#endif
@@ -360,7 +370,7 @@
/* Total number of interrupts */
-#define NR_IRQS (XTENSA_NIRQ_INTERNAL + ESP32S2_NIRQ_PERIPH + ESP32S2_NIRQ_GPIO + ESP32S2_NIRQ_RTCIO)
+#define NR_IRQS (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_NIRQ_PERIPH + ESP32S2_NIRQ_GPIO + ESP32S2_NIRQ_RTCIO)
/* Xtensa CPU Interrupts.
*
diff --git a/arch/xtensa/include/esp32s3/irq.h b/arch/xtensa/include/esp32s3/irq.h
index 06de3c37e71..efa7dd878dd 100644
--- a/arch/xtensa/include/esp32s3/irq.h
+++ b/arch/xtensa/include/esp32s3/irq.h
@@ -41,7 +41,7 @@
/* CPU interrupt flags:
* These flags can be used to specify which interrupt qualities the
- * code calling esp32s3_setup_irq needs.
+ * code calling esp_setup_irq needs.
*/
#define ESP32S3_CPUINT_FLAG_LEVEL (1 << 0) /* Level-triggered interrupt */
@@ -156,7 +156,6 @@
#define ESP32S3_PERIPH_AES 77
#define ESP32S3_PERIPH_SHA 78
#define ESP32S3_PERIPH_INT_FROM_CPU0 79
-
#define ESP32S3_PERIPH_INT_FROM_CPU1 80
#define ESP32S3_PERIPH_INT_FROM_CPU2 81
#define ESP32S3_PERIPH_INT_FROM_CPU3 82
@@ -201,14 +200,19 @@
* interrupts.
*/
-#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
-#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
-#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
-#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
-#define XTENSA_IRQ_SWINT 4 /* Software interrupt */
+#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Platform timer 0 interrupt source */
+#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Platform timer 1 interrupt source */
+#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Platform timer 2 interrupt source */
+#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */
+#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */
+#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */
+
+#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)
-#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */
-#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */
+#define XTENSA_NIRQ_INTERNAL ETS_INTERNAL_INTR_SOURCE_OFF /* Number of dispatch internal interrupts */
+#define XTENSA_IRQ_DEMUX ETS_INTERNAL_INTR_SOURCE_OFF + 0 /* Demultiplexing IRQ for peripheral interrupts */
+#define XTENSA_IRQ_SYSCALL ETS_INTERNAL_INTR_SOURCE_OFF + 1 /* User interrupt w/EXCCAUSE=syscall */
+#define XTENSA_IRQ_FIRSTPERIPH ETS_INTERNAL_INTR_SOURCE_OFF + 2 /* First peripheral IRQ number */
/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.
@@ -217,6 +221,9 @@
#define ESP32S3_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
#define ESP32S3_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)
+#define ESP_IRQ2SOURCE(irq) ESP32S3_IRQ2PERIPH(irq)
+#define ESP_SOURCE2IRQ(id) ESP32S3_PERIPH2IRQ(id)
+
#define ESP32S3_IRQ_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC)
#define ESP32S3_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC_NMI)
#define ESP32S3_IRQ_PWR (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PWR)
@@ -329,7 +336,7 @@
#define ESP32S3_NIRQ_PERIPH ESP32S3_NPERIPHERALS
-#ifdef CONFIG_ESP32S3_GPIO_IRQ
+#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched
* as a second level of decoding: The first level dispatches to the GPIO
@@ -341,6 +348,8 @@
# define ESP32S3_LAST_GPIOIRQ (ESP32S3_FIRST_GPIOIRQ + ESP32S3_NIRQ_GPIO - 1)
# define ESP32S3_PIN2IRQ(p) ((p) + ESP32S3_FIRST_GPIOIRQ)
# define ESP32S3_IRQ2PIN(i) ((i) - ESP32S3_FIRST_GPIOIRQ)
+# define ESP_PIN2IRQ(p) ESP32S3_PIN2IRQ(p)
+# define ESP_IRQ2PIN(i) ESP32S3_IRQ2PIN(i)
#else
# define ESP32S3_NIRQ_GPIO 0
#endif
@@ -392,7 +401,7 @@
/* Total number of interrupts */
-#define NR_IRQS (XTENSA_NIRQ_INTERNAL + ESP32S3_NIRQ_PERIPH + ESP32S3_NIRQ_GPIO + ESP32S3_NIRQ_RTCIO)
+#define NR_IRQS (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_NIRQ_PERIPH + ESP32S3_NIRQ_GPIO + ESP32S3_NIRQ_RTCIO)
/* Xtensa CPU Interrupts.
*
diff --git a/arch/xtensa/src/common/espressif/Kconfig b/arch/xtensa/src/common/espressif/Kconfig
index 9e3171aee12..91c097d614e 100644
--- a/arch/xtensa/src/common/espressif/Kconfig
+++ b/arch/xtensa/src/common/espressif/Kconfig
@@ -1,3 +1,73 @@
+menu "Espressif Log Level"
+ visible if DEBUG_FEATURES
+
+config ESPRESSIF_LOG_LEVEL_NONE
+ bool "NONE"
+ depends on !DEBUG_FEATURES && !DEBUG_ERROR && !DEBUG_WARN && !DEBUG_INFO
+ default y
+ ---help---
+ No log output from Espressif log messages.
+
+config ESPRESSIF_LOG_LEVEL_ERROR
+ bool "ERROR"
+ depends on DEBUG_ERROR
+ default y
+ ---help---
+ Display critical errors from Espressif log messages.
+
+config ESPRESSIF_LOG_LEVEL_WARN
+ bool "WARN"
+ depends on DEBUG_WARN
+ default y
+ ---help---
+ Display warning messages from Espressif log messages.
+
+config ESPRESSIF_LOG_LEVEL_INFO
+ bool "INFO"
+ depends on DEBUG_INFO
+ default y
+ ---help---
+ Display information messages from Espressif log messages.
+
+config ESPRESSIF_LOG_LEVEL_DEBUG
+ bool "DEBUG"
+ depends on DEBUG_INFO
+ default n
+ ---help---
+ Display extra information from Espressif log messages.
+
+config ESPRESSIF_LOG_LEVEL_VERBOSE
+ bool "VERBOSE"
+ depends on DEBUG_INFO
+ default n
+ ---help---
+ Display bigger chunks of debugging information, or frequent messages
+ which can potentially flood the output from Espressif log messages.
+
+config ESPRESSIF_LOG_LEVEL
+ int
+ default 5 if ESPRESSIF_LOG_LEVEL_VERBOSE
+ default 4 if ESPRESSIF_LOG_LEVEL_DEBUG
+ default 3 if ESPRESSIF_LOG_LEVEL_INFO
+ default 2 if ESPRESSIF_LOG_LEVEL_WARN
+ default 1 if ESPRESSIF_LOG_LEVEL_ERROR
+ default 0 if ESPRESSIF_LOG_LEVEL_NONE
+
+endmenu # Espressif Log Level
+
+menu "Interrupt Configuration"
+
+config ESPRESSIF_IRAM_ISR_DEBUG
+ bool "Enable debugging of the IRAM-enabled interrupts"
+ default n
+ ---help---
+ This option enables keeping track of the IRAM-enabled interrupts by
+ registering its execution when non-IRAM interrupts are disabled. It
+ keeps track of the IRQ executed and register how many times since
+ boot it was executed.
+
+endmenu # Interrupt Configuration
+
config ESP_RMT
bool "Remote Control Module (RMT)"
default n
@@ -132,9 +202,9 @@ config ESPRESSIF_I2S0
select ESPRESSIF_I2S
select I2S
select ESP32S3_DMA if ARCH_CHIP_ESP32S3
- select ESP32S3_GPIO_IRQ if ARCH_CHIP_ESP32S3
- select ESP32S2_GPIO_IRQ if ARCH_CHIP_ESP32S2
- select ESP32_GPIO_IRQ if ARCH_CHIP_ESP32
+ select ESPRESSIF_GPIO_IRQ if ARCH_CHIP_ESP32S3
+ select ESPRESSIF_GPIO_IRQ if ARCH_CHIP_ESP32S2
+ select ESPRESSIF_GPIO_IRQ if ARCH_CHIP_ESP32
select SCHED_HPWORK
select ARCH_DMA
@@ -145,8 +215,8 @@ config ESPRESSIF_I2S1
select ESPRESSIF_I2S
select I2S
select ESP32S3_DMA if ARCH_CHIP_ESP32S3
- select ESP32S3_GPIO_IRQ if ARCH_CHIP_ESP32S3
- select ESP32_GPIO_IRQ if ARCH_CHIP_ESP32
+ select ESPRESSIF_GPIO_IRQ if ARCH_CHIP_ESP32S3
+ select ESPRESSIF_GPIO_IRQ if ARCH_CHIP_ESP32
select SCHED_HPWORK
select ARCH_DMA
@@ -219,6 +289,12 @@ config ESPRESSIF_DEDICATED_GPIO
It can work as pin grouping and you can use any pin up to 8 pins for
input and 8 pins for output for dedicated gpio in total.
+config ESPRESSIF_GPIO_IRQ
+ bool "GPIO pin interrupts"
+ default n
+ ---help---
+ Enable support for interrupting GPIO pins.
+
config ESPRESSIF_DEDICATED_GPIO_IRQ
bool "Dedicated GPIO IRQ"
depends on ESPRESSIF_DEDICATED_GPIO && ARCH_CHIP_ESP32S2
@@ -520,7 +596,17 @@ endmenu # LP Core (Low-power core) Coprocessor Configuration
menu "PM Configuration"
-if PM && !ARCH_CHIP_ESP32
+config ESPRESSIF_AUTO_SLEEP
+ bool "Auto-sleep"
+ depends on !ARCH_CHIP_ESP32H2
+ default n
+ select PM
+ select ESPRESSIF_HR_TIMER
+ select ESP32_TICKLESS if ARCH_CHIP_ESP32
+ ---help---
+ Enable Auto-sleep
+
+if PM
config PM_EXT1_WAKEUP
bool "PM EXT1 Wakeup"
@@ -643,18 +729,28 @@ config PM_EXT1_WAKEUP_RTC_GPIO17
config PM_EXT1_WAKEUP_RTC_GPIO18
bool "RTC_GPIO18"
+ depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
default n
---help---
Enable RTC GPIO18 as an EXT1 wakeup source.
config PM_EXT1_WAKEUP_RTC_GPIO19
bool "RTC_GPIO19"
+ depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
default n
---help---
Enable RTC GPIO19 as an EXT1 wakeup source.
config PM_EXT1_WAKEUP_RTC_GPIO20
bool "RTC_GPIO20"
+ depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
+ default n
+ ---help---
+ Enable RTC GPIO20 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO21
+ bool "RTC_GPIO21"
+ depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
default n
---help---
Enable RTC GPIO20 as an EXT1 wakeup source.
@@ -688,7 +784,8 @@ config PM_EXT0_WAKEUP_GPIO
int "EXT0 Wakeup GPIO"
depends on PM_EXT0_WAKEUP
default 0
- range 0 20
+ range 0 17 if ARCH_CHIP_ESP32
+ range 0 21 if ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
---help---
GPIO to wake the device up from PM_STANDBY or PM_SLEEP using as EXT0 wakeup GPIO
@@ -708,6 +805,7 @@ endmenu # PM_EXT0_WAKEUP_SOURCES
config PM_ULP_WAKEUP
bool "PM ULP Wakeup"
+ depends on !ARCH_CHIP_ESP32
default n
---help---
Enable ULP coprocessor wakeup functionality.
@@ -726,6 +824,12 @@ config PM_GPIO_WAKEUP
menu "PM GPIO Wakeup Sources"
depends on PM_GPIO_WAKEUP
+config PM_GPIO_WAKEUP_GPIO0
+ bool "GPIO0"
+ default n
+ ---help---
+ Enable GPIO0 as an GPIO wakeup source.
+
config PM_GPIO_WAKEUP_GPIO1
bool "GPIO1"
default n
@@ -854,67 +958,175 @@ config PM_GPIO_WAKEUP_GPIO21
config PM_GPIO_WAKEUP_GPIO22
bool "GPIO22"
- depends on !ARCH_CHIP_ESP32C3_GENERIC
default n
---help---
Enable GPIO22 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO23
bool "GPIO23"
- depends on !ARCH_CHIP_ESP32C3_GENERIC
default n
---help---
Enable GPIO23 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO24
bool "GPIO24"
- depends on !ARCH_CHIP_ESP32C3_GENERIC
default n
---help---
Enable GPIO24 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO25
bool "GPIO25"
- depends on !ARCH_CHIP_ESP32C3_GENERIC
default n
---help---
Enable GPIO25 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO26
bool "GPIO26"
- depends on !ARCH_CHIP_ESP32C3_GENERIC
default n
---help---
Enable GPIO26 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO27
bool "GPIO27"
- depends on !ARCH_CHIP_ESP32C3_GENERIC
default n
---help---
Enable GPIO27 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO28
bool "GPIO28"
- depends on ARCH_CHIP_ESP32C6
default n
---help---
Enable GPIO28 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO29
bool "GPIO29"
- depends on ARCH_CHIP_ESP32C6
default n
---help---
Enable GPIO29 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO30
bool "GPIO30"
- depends on ARCH_CHIP_ESP32C6
default n
---help---
Enable GPIO30 as an GPIO wakeup source.
+config PM_GPIO_WAKEUP_GPIO31
+ bool "GPIO31"
+ default n
+ ---help---
+ Enable GPIO31 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO32
+ bool "GPIO32"
+ default n
+ ---help---
+ Enable GPIO32 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO33
+ bool "GPIO33"
+ default n
+ ---help---
+ Enable GPIO33 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO34
+ bool "GPIO34"
+ default n
+ ---help---
+ Enable GPIO34 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO35
+ bool "GPIO35"
+ default n
+ ---help---
+ Enable GPIO35 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO36
+ bool "GPIO36"
+ default n
+ ---help---
+ Enable GPIO36 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO37
+ bool "GPIO37"
+ default n
+ ---help---
+ Enable GPIO37 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO38
+ bool "GPIO38"
+ default n
+ ---help---
+ Enable GPIO38 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO39
+ bool "GPIO39"
+ default n
+ ---help---
+ Enable GPIO39 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO40
+ bool "GPIO40"
+ depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
+ default n
+ ---help---
+ Enable GPIO40 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO41
+ bool "GPIO41"
+ depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
+ default n
+ ---help---
+ Enable GPIO41 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO42
+ bool "GPIO42"
+ depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
+ default n
+ ---help---
+ Enable GPIO42 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO43
+ bool "GPIO43"
+ depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
+ default n
+ ---help---
+ Enable GPIO43 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO44
+ bool "GPIO44"
+ depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
+ default n
+ ---help---
+ Enable GPIO44 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO45
+ bool "GPIO45"
+ depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
+ default n
+ ---help---
+ Enable GPIO45 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO46
+ bool "GPIO46"
+ depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
+ default n
+ ---help---
+ Enable GPIO46 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO47
+ bool "GPIO47"
+ depends on ARCH_CHIP_ESP32S3
+ default n
+ ---help---
+ Enable GPIO47 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO48
+ bool "GPIO48"
+ depends on ARCH_CHIP_ESP32S3
+ default n
+ ---help---
+ Enable GPIO48 as an GPIO wakeup source.
+
choice PM_GPIO_WAKEUP_TRIGGER_MODE
prompt "PM GPIO Wakeup Trigger Mode"
default PM_GPIO_WAKEUP_TRIGGER_ANY_LOW
@@ -931,7 +1143,7 @@ endmenu # PM_GPIO_WAKEUP_SOURCES
config PM_UART_WAKEUP
bool "PM UART Wakeup"
- depends on ESP32S3_UART0 || ESP32S3_UART1
+ depends on ESP32_UART0 || ESP32_UART1 || ESP32S3_UART0 || ESP32S3_UART1
default n
---help---
Enable UART wakeup functionality.
@@ -943,15 +1155,17 @@ menu "PM UART Wakeup Sources"
choice PM_UART_WAKEUP_UART_NUM
prompt "PM UART Wakeup UART Number"
+ default PM_UART_WAKEUP_UART0 if ESP32_UART0
+ default PM_UART_WAKEUP_UART1 if ESP32_UART1
default PM_UART_WAKEUP_UART0 if ESP32S3_UART0
default PM_UART_WAKEUP_UART1 if ESP32S3_UART1
config PM_UART_WAKEUP_UART0
- depends on ESP32S3_UART0
+ depends on ESP32_UART0 || ESP32S3_UART0
bool "Wake the chip up when UART0 gets a data"
config PM_UART_WAKEUP_UART1
- depends on ESP32S3_UART1
+ depends on ESP32_UART1 || ESP32S3_UART1
bool "Wake the chip up when UART1 gets a data"
endchoice # PM_UART_WAKEUP_UART_NUM
@@ -986,7 +1200,7 @@ config PM_SLEEP_WAKEUP_NSEC
---help---
Number of additional nanoseconds to wait in PM_SLEEP.
-endif # PM && !ARCH_CHIP_ESP32
+endif # PM
endmenu # PM Configuration
@@ -2262,3 +2476,12 @@ config ESPRESSIF_BLE_INTERRUPT_SAVE_STATUS
Number of interrupt save status variables to keep track. Increase it if any related bug is found.
endmenu # BLE Configuration
+
+config ESPRESSIF_HR_TIMER
+ bool
+ default RTC_DRIVER
+ ---help---
+ A high-resolution hardware timer for supporting the management of
+ kernel events.
+ The HR Timer is built on top of the System Timer (SYSTIMER) peripheral.
+ Timer callbacks are dispatched from a high-priority kernel task.
diff --git a/arch/xtensa/src/common/espressif/Make.defs b/arch/xtensa/src/common/espressif/Make.defs
index 1b1a63efc7a..2b6f5161a80 100644
--- a/arch/xtensa/src/common/espressif/Make.defs
+++ b/arch/xtensa/src/common/espressif/Make.defs
@@ -20,6 +20,10 @@
#
############################################################################
+# Silent preprocessor warnings
+
+CFLAGS += -Wno-shadow -Wno-undef
+
ifeq ($(CONFIG_ESP_RMT),y)
CHIP_CSRCS += esp_rmt.c
ifeq ($(CONFIG_WS2812_NON_SPI_DRIVER),y)
@@ -124,19 +128,26 @@ ifeq ($(CONFIG_ESPRESSIF_ADC),y)
CHIP_CSRCS += esp_adc.c
endif
-ifneq ($(CONFIG_ARCH_CHIP_ESP32),y)
ifeq ($(CONFIG_PM),y)
ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
CHIP_CSRCS += esp_pm_initialize.c
endif
CHIP_CSRCS += esp_pm.c
-LDFLAGS += -u esp_timer_init_include_func
endif
+
+CHIP_CSRCS += esp_efuse.c esp_irq.c esp_xtensa_intr.c esp_gpio.c
+
+ifeq ($(CONFIG_RTC_DRIVER),y)
+CHIP_CSRCS += esp_rtc.c
endif
-CHIP_CSRCS += esp_efuse.c
+ifeq ($(CONFIG_ESPRESSIF_HR_TIMER),y)
+CHIP_CSRCS += esp_timer_adapter.c
+endif
LDFLAGS += -u esp_system_include_startup_funcs
+LDFLAGS += -u esp_timer_init_include_func
+
ifeq ($(CONFIG_ESPRESSIF_EFUSE),y)
LDFLAGS += -u esp_efuse_startup_include_func
endif
diff --git a/arch/xtensa/src/common/espressif/Wireless.mk b/arch/xtensa/src/common/espressif/Wireless.mk
index e8dfa5cc850..2cab205f302 100644
--- a/arch/xtensa/src/common/espressif/Wireless.mk
+++ b/arch/xtensa/src/common/espressif/Wireless.mk
@@ -20,6 +20,8 @@
#
############################################################################
+WIFI_WPA_SUPPLICANT = chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)wpa_supplicant
+
ifeq ($(CONFIG_ARCH_CHIP_ESP32),y)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)include$(DELIM)$(CHIP_SERIES)$(DELIM)include
endif
@@ -27,6 +29,7 @@ ifeq ($(CONFIG_ARCH_CHIP_ESP32S3),y)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)include$(DELIM)esp32c3$(DELIM)include
endif
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)$(DELIM)wifi_apps$(DELIM)roaming_app$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)esp_wifi
@@ -59,21 +62,32 @@ ifeq ($(CONFIG_WPA_WAPI_PSK),y)
EXTRA_LIBS += -lwapi
endif
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)include
+
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)src$(DELIM)wifi_init.c
+
ifeq ($(CONFIG_ESPRESSIF_WIFI),y)
## ESP-IDF's mbedTLS
-
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library
-INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include$(DELIM)aes
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)src
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls
### Define Espressif's configs for mbedTLS
CFLAGS += $(DEFINE_PREFIX)MBEDTLS_CONFIG_FILE="<mbedtls/esp_config.h>"
+VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)src
+
CHIP_CSRCS += aes.c
CHIP_CSRCS += aria.c
CHIP_CSRCS += bignum_core.c
@@ -110,20 +124,47 @@ CHIP_CSRCS += hmac_drbg.c
CHIP_CSRCS += rsa_alt_helpers.c
CHIP_CSRCS += ecdh.c
CHIP_CSRCS += pk_ecc.c
+CHIP_CSRCS += pk_rsa.c
+CHIP_CSRCS += psa_util.c
+CHIP_CSRCS += psa_crypto_ffdh.c
+CHIP_CSRCS += psa_crypto_ecp.c
+CHIP_CSRCS += psa_crypto_rsa.c
+CHIP_CSRCS += psa_crypto_cipher.c
+CHIP_CSRCS += psa_crypto_mac.c
+CHIP_CSRCS += psa_crypto_hash.c
+
+VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)core
+
+CHIP_CSRCS += psa_crypto_client.c
+CHIP_CSRCS += psa_crypto_driver_wrappers_no_static.c
+CHIP_CSRCS += psa_crypto_slot_management.c
+CHIP_CSRCS += psa_crypto_storage.c
+CHIP_CSRCS += psa_crypto.c
+CHIP_CSRCS += psa_its_file.c
+CHIP_CSRCS += tf_psa_crypto_config.c
+CHIP_CSRCS += tf_psa_crypto_version.c
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port
+CHIP_CSRCS += esp_psa_crypto_init.c
+
CHIP_CSRCS += esp_hardware.c
CHIP_CSRCS += esp_mem.c
CHIP_CSRCS += esp_timing.c
-VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)md
+# Ensure PSA crypto initialization is included in the build
-CHIP_CSRCS += esp_md.c
+LDFLAGS += -u mbedtls_psa_crypto_init_include_impl
-## WPA Supplicant
+VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)esp_mac
+ifneq ($(CONFIG_ARCH_CHIP_ESP32),y)
+CHIP_CSRCS += psa_crypto_driver_esp_hmac_opaque.c
+endif
-WIFI_WPA_SUPPLICANT = chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)wpa_supplicant
+VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)esp_md
+CHIP_CSRCS += psa_crypto_driver_esp_md5.c
+
+## WPA Supplicant
CFLAGS += $(DEFINE_PREFIX)__ets__
CFLAGS += $(DEFINE_PREFIX)CONFIG_CRYPTO_MBEDTLS
@@ -132,14 +173,18 @@ CFLAGS += $(DEFINE_PREFIX)CONFIG_IEEE80211W
CFLAGS += $(DEFINE_PREFIX)CONFIG_WPA3_SAE
CFLAGS += $(DEFINE_PREFIX)EAP_PEER_METHOD
CFLAGS += $(DEFINE_PREFIX)ESP_PLATFORM=1
+CFLAGS += $(DEFINE_PREFIX)TF_PSA_CRYPTO_USER_CONFIG_FILE=\"mbedtls/esp_config.h\"
CFLAGS += $(DEFINE_PREFIX)ESP_SUPPLICANT
CFLAGS += $(DEFINE_PREFIX)ESPRESSIF_USE
CFLAGS += $(DEFINE_PREFIX)IEEE8021X_EAPOL
CFLAGS += $(DEFINE_PREFIX)USE_WPA2_TASK
CFLAGS += $(DEFINE_PREFIX)CONFIG_SHA256
-CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE
CFLAGS += $(DEFINE_PREFIX)USE_WPS_TASK
+ifeq ($(CONFIG_ESPRESSIF_WIFI_SOFTAP_SAE_SUPPORT),y)
+CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE
+endif
+
ifeq ($(CONFIG_ESPRESSIF_WIFI_ENABLE_SAE_PK),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE_PK
endif
@@ -160,9 +205,6 @@ ifeq ($(CONFIG_ESPRESSIF_WIFI_GMAC_SUPPORT),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_GMAC
endif
-INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)include
-INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src
-
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)ap
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)ap
@@ -193,7 +235,6 @@ VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)crypto
CHIP_CSRCS += aes-ccm.c
CHIP_CSRCS += aes-gcm.c
-CHIP_CSRCS += aes-omac1.c
CHIP_CSRCS += aes-unwrap.c
CHIP_CSRCS += aes-wrap.c
CHIP_CSRCS += ccmp.c
@@ -246,8 +287,6 @@ CHIP_CSRCS += os_xtensa.c
## ESP Supplicant (Espressif's WPA supplicant extension)
-INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)include
-
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src
@@ -272,7 +311,6 @@ CHIP_CSRCS += crypto_mbedtls.c
CHIP_CSRCS += tls_mbedtls.c
CHIP_CSRCS += aes-siv.c
-CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)src$(DELIM)wifi_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)src$(DELIM)lib_printf.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)regulatory$(DELIM)esp_wifi_regulatory.c
diff --git a/arch/xtensa/src/common/espressif/esp_adc.c b/arch/xtensa/src/common/espressif/esp_adc.c
index 756f652f806..f1e669a8a81 100644
--- a/arch/xtensa/src/common/espressif/esp_adc.c
+++ b/arch/xtensa/src/common/espressif/esp_adc.c
@@ -45,16 +45,16 @@
#include "hal/adc_oneshot_hal.h"
#include "hal/adc_ll.h"
#include "hal/sar_ctrl_ll.h"
-#include "soc/adc_periph.h"
+#include "hal/adc_periph.h"
#include "soc/periph_defs.h"
#include "esp_clk_tree.h"
#ifdef CONFIG_ARCH_CHIP_ESP32
-#include "esp32_gpio.h"
+#include "esp_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#include "esp32s2_gpio.h"
+#include "espressif/esp_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
-#include "esp32s3_gpio.h"
+#include "esp_gpio.h"
#endif
/****************************************************************************
@@ -66,15 +66,12 @@
#endif
#ifdef CONFIG_ARCH_CHIP_ESP32
-# define esp_configgpio esp32_configgpio
# define GPIO_ADC_FUNCTION FUNCTION_3
#endif
#ifdef CONFIG_ARCH_CHIP_ESP32S2
-# define esp_configgpio esp32s2_configgpio
# define GPIO_ADC_FUNCTION FUNCTION_2
#endif
#ifdef CONFIG_ARCH_CHIP_ESP32S3
-# define esp_configgpio esp32s3_configgpio
# define GPIO_ADC_FUNCTION FUNCTION_2
#endif
diff --git a/arch/xtensa/src/common/espressif/esp_dedic_gpio.c b/arch/xtensa/src/common/espressif/esp_dedic_gpio.c
index a1780a54d26..3dde327b956 100644
--- a/arch/xtensa/src/common/espressif/esp_dedic_gpio.c
+++ b/arch/xtensa/src/common/espressif/esp_dedic_gpio.c
@@ -46,19 +46,14 @@
#include "chip.h"
#include "esp_dedic_gpio.h"
-#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#include "esp32s3_gpio.h"
-#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#include "esp32s2_irq.h"
-#include "esp32s2_gpio.h"
-#endif
-
+#include "espressif/esp_gpio.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "soc/dedic_gpio_struct.h"
#endif
#include "hal/dedic_gpio_ll.h"
#include "hal/dedic_gpio_cpu_ll.h"
-#include "soc/dedic_gpio_periph.h"
+#include "hal/dedic_gpio_periph.h"
+#include "hal/dedic_gpio_caps.h"
#include "soc/gpio_sig_map.h"
#include "periph_ctrl.h"
#include "soc/soc_caps.h"
@@ -71,19 +66,11 @@
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#define esp_configgpio esp32s3_configgpio
-#define esp_gpio_matrix_in esp32s3_gpio_matrix_in
-#define esp_gpio_matrix_out esp32s3_gpio_matrix_out
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S3_INT_PRIO_DEF
-#define ESP_IRQ_TRIGGER_LEVEL ESP32S3_CPUINT_LEVEL
+#define ESP_IRQ_TRIGGER_LEVEL ESP_IRQ_TRIGGER_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#define esp_setup_irq esp32s2_setup_irq
-#define esp_teardown_irq esp32s2_teardown_irq
-#define esp_configgpio esp32s2_configgpio
-#define esp_gpio_matrix_in esp32s2_gpio_matrix_in
-#define esp_gpio_matrix_out esp32s2_gpio_matrix_out
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S2_INT_PRIO_DEF
-#define ESP_IRQ_TRIGGER_LEVEL ESP32S2_CPUINT_LEVEL
+#define ESP_IRQ_TRIGGER_LEVEL ESP_IRQ_TRIGGER_LEVEL
#endif
/****************************************************************************
@@ -252,7 +239,7 @@ static int IRAM_ATTR esp_dedic_gpio_isr_default(int irq, void *context,
}
/****************************************************************************
- * Name: esp_pcnt_isr_register
+ * Name: esp_dedic_gpio_isr_register
*
* Description:
* This function registers an interrupt service routine (ISR) for the
@@ -271,29 +258,23 @@ static int IRAM_ATTR esp_dedic_gpio_isr_default(int irq, void *context,
static int esp_dedic_gpio_isr_register(void)
{
int cpuint;
+#ifndef CONFIG_ARCH_CHIP_ESP32S2
int ret;
+#endif
int cpu = this_cpu();
uint32_t status;
cpuint = esp_setup_irq(dedic_gpio_periph_signals.irq,
ESP_IRQ_PRIORITY_DEFAULT,
- ESP_IRQ_TRIGGER_LEVEL);
+ ESP_IRQ_TRIGGER_LEVEL,
+ esp_dedic_gpio_isr_default,
+ &dedic_gpio_common[cpu]);
if (cpuint < 0)
{
cperr("Failed to allocate a CPU interrupt.\n");
return ERROR;
}
- ret = irq_attach(dedic_gpio_periph_signals.irq + XTENSA_IRQ_FIRSTPERIPH,
- esp_dedic_gpio_isr_default,
- &dedic_gpio_common[cpu]);
- if (ret < 0)
- {
- cperr("Couldn't attach IRQ to handler.\n");
- esp_teardown_irq(dedic_gpio_periph_signals.irq, cpuint);
- return ERROR;
- }
-
status = dedic_gpio_ll_get_interrupt_status(dedic_gpio_common[cpu].dev);
dedic_gpio_ll_clear_interrupt_status(dedic_gpio_common[cpu].dev, status);
up_enable_irq(dedic_gpio_periph_signals.irq + XTENSA_IRQ_FIRSTPERIPH);
@@ -538,9 +519,9 @@ struct file *esp_dedic_gpio_new_bundle(
}
dedic_gpio_common[cpu].out_occupied_mask =
- UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) - 1);
+ UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)) - 1);
dedic_gpio_common[cpu].in_occupied_mask =
- UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_IN_CHANNELS_NUM) - 1);
+ UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)) - 1);
spin_unlock_irqrestore(&dedic_gpio_common[cpu].spinlock, flags);
}
@@ -557,11 +538,12 @@ struct file *esp_dedic_gpio_new_bundle(
out_offset = 0;
if (config->flags->output_enable)
{
- if (config->array_size > SOC_DEDIC_GPIO_OUT_CHANNELS_NUM)
+ if (config->array_size > DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU))
{
- gpioerr("ERROR: array size(%d) exceeds maximum supported out\
+ gpioerr("ERROR: array size(%d) exceeds maximum supported out \
channels(%d)\n",
- config->array_size, SOC_DEDIC_GPIO_OUT_CHANNELS_NUM);
+ config->array_size,
+ DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU));
free(priv);
return NULL;
}
@@ -569,8 +551,9 @@ struct file *esp_dedic_gpio_new_bundle(
flags = spin_lock_irqsave(&dedic_gpio_common[cpu].spinlock);
for (int i = 0;
- i <= SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - config->array_size;
- i++)
+ i <= (DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) - \
+ config->array_size);
+ i++)
{
if ((dedic_gpio_common[cpu].out_occupied_mask & (pattern << i))
== 0)
@@ -608,11 +591,12 @@ struct file *esp_dedic_gpio_new_bundle(
if (config->flags->input_enable)
{
- if (config->array_size > SOC_DEDIC_GPIO_IN_CHANNELS_NUM)
+ if (config->array_size > DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU))
{
gpioerr("ERROR: array size(%d) exceeds maximum supported in\
channels(%d)\n",
- config->array_size, SOC_DEDIC_GPIO_IN_CHANNELS_NUM);
+ config->array_size,
+ DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU));
free(priv);
return NULL;
}
@@ -620,8 +604,9 @@ struct file *esp_dedic_gpio_new_bundle(
flags = spin_lock_irqsave(&dedic_gpio_common[cpu].spinlock);
for (int i = 0;
- i <= SOC_DEDIC_GPIO_IN_CHANNELS_NUM - config->array_size;
- i++)
+ i <= (DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU) - \
+ config->array_size);
+ i++)
{
if ((dedic_gpio_common[cpu].in_occupied_mask &
(pattern << i)) == 0)
diff --git a/arch/xtensa/src/common/espressif/esp_efuse.c b/arch/xtensa/src/common/espressif/esp_efuse.c
index 813a7a29106..a964feccf8a 100644
--- a/arch/xtensa/src/common/espressif/esp_efuse.c
+++ b/arch/xtensa/src/common/espressif/esp_efuse.c
@@ -42,6 +42,7 @@
#include "xtensa.h"
#include "soc/syscon_reg.h"
#include "esp_efuse_table.h"
+#include "hal/efuse_ll.h"
#endif
/****************************************************************************
@@ -345,16 +346,9 @@ uint32_t esp_efuse_hal_chip_revision(void)
uint32_t combine_value;
uint32_t chip_ver = 0;
- esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV1,
- &eco_bit0,
- ESP_EFUSE_CHIP_VER_REV1[0]->bit_count);
- esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV2,
- &eco_bit1,
- ESP_EFUSE_CHIP_VER_REV2[0]->bit_count);
- esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION_MINOR,
- &minor_chip_version,
- ESP_EFUSE_WAFER_VERSION_MINOR[0]->bit_count);
-
+ eco_bit0 = efuse_ll_get_chip_ver_rev1();
+ eco_bit1 = efuse_ll_get_chip_ver_rev2();
+ minor_chip_version = efuse_ll_get_chip_wafer_version_minor();
eco_bit2 = (getreg32(SYSCON_DATE_REG) & 0x80000000) >> 31;
combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
diff --git a/arch/xtensa/src/common/espressif/esp_espnow_pktradio.c b/arch/xtensa/src/common/espressif/esp_espnow_pktradio.c
index 541299cdf95..da5156f675c 100644
--- a/arch/xtensa/src/common/espressif/esp_espnow_pktradio.c
+++ b/arch/xtensa/src/common/espressif/esp_espnow_pktradio.c
@@ -47,7 +47,7 @@
#include <nuttx/wdog.h>
#include "xtensa.h"
-#include "xtensa_attr.h"
+
#include "esp_now.h"
#include "esp_mac.h"
#include "esp_espnow_pktradio.h"
diff --git a/arch/xtensa/src/common/espressif/esp_gpio.c b/arch/xtensa/src/common/espressif/esp_gpio.c
new file mode 100644
index 00000000000..a7387a4dd39
--- /dev/null
+++ b/arch/xtensa/src/common/espressif/esp_gpio.c
@@ -0,0 +1,457 @@
+/****************************************************************************
+ * arch/xtensa/src/common/espressif/esp_gpio.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Config */
+
+#include <nuttx/config.h>
+
+/* Libc */
+
+#include <assert.h>
+#include <debug.h>
+#include <stdint.h>
+#include <sys/types.h>
+
+/* NuttX */
+
+#include <arch/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/kmalloc.h>
+
+/* Arch */
+
+#include "xtensa.h"
+
+#include "esp_gpio.h"
+#include "esp_irq.h"
+
+/* HAL */
+
+#include "esp_err.h"
+#include "soc/interrupts.h"
+#include "esp_rom_gpio.h"
+#include "hal/gpio_hal.h"
+#include "driver/gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define ESP_INTR_FLAG_DEFAULT 0
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static gpio_hal_context_t g_gpio_hal =
+{
+ .dev = GPIO_HAL_GET_HW(GPIO_PORT_0)
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp_intr_handler_adapter
+ *
+ * Description:
+ * This function acts as an adapter to bridge interrupt service routines
+ * between NuttX and the Espressif's interrupt service routine. It is
+ * called when a GPIO interrupt occurs, retrieves the function pointer and
+ * associated data from the 'intr_adapter_from_nuttx' structure passed as
+ * an argument, and invokes the original user-provided interrupt handler
+ * with the IRQ number and user argument.
+ *
+ * Input Parameters:
+ * arg - Pointer to a structure of type 'intr_adapter_from_nuttx' that
+ * holds the handler function, the associated IRQ, the context, and
+ * the user argument.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
+static void esp_intr_handler_adapter(void *arg)
+{
+ struct intr_adapter_from_nuttx *adapter;
+
+ adapter = (struct intr_adapter_from_nuttx *)arg;
+
+ adapter->func(adapter->irq, adapter->context, adapter->arg);
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp_configgpio
+ *
+ * Description:
+ * Configure a GPIO pin based on encoded pin attributes.
+ *
+ * Input Parameters:
+ * pin - GPIO pin to be configured.
+ * attr - Attributes to be configured for the selected GPIO pin.
+ * The following attributes are accepted:
+ * - Direction (OUTPUT or INPUT)
+ * - Pull (PULLUP, PULLDOWN or OPENDRAIN)
+ * - Function (if not provided, assume function GPIO by
+ * default)
+ * - Drive strength (if not provided, assume DRIVE_2 by
+ * default)
+ *
+ * Returned Value:
+ * Zero (OK) on success, or -1 (ERROR) in case of failure.
+ *
+ ****************************************************************************/
+
+int esp_configgpio(int pin, gpio_pinattr_t attr)
+{
+ DEBUGASSERT(pin >= 0 && pin < SOC_GPIO_PIN_COUNT);
+
+ /* Handle input pins */
+
+ if ((attr & INPUT) != 0)
+ {
+ gpio_hal_input_enable(&g_gpio_hal, pin);
+ }
+ else
+ {
+ gpio_hal_input_disable(&g_gpio_hal, pin);
+ }
+
+ if ((attr & OPEN_DRAIN) != 0)
+ {
+ gpio_hal_od_enable(&g_gpio_hal, pin);
+ }
+ else
+ {
+ gpio_hal_od_disable(&g_gpio_hal, pin);
+ }
+
+ if ((attr & OUTPUT) != 0)
+ {
+ gpio_hal_output_enable(&g_gpio_hal, pin);
+ }
+ else
+ {
+ gpio_hal_output_disable(&g_gpio_hal, pin);
+ }
+
+ if ((attr & PULLUP) != 0)
+ {
+ gpio_pullup_en(pin);
+ }
+ else
+ {
+ gpio_pullup_dis(pin);
+ }
+
+ if ((attr & PULLDOWN) != 0)
+ {
+ gpio_pulldown_en(pin);
+ }
+ else
+ {
+ gpio_pulldown_dis(pin);
+ }
+
+ gpio_hal_set_intr_type(&g_gpio_hal, pin,
+ (attr & INTR_TYPE_MASK) >> INTR_TYPE_SHIFT);
+
+ if ((attr & DRIVE_MASK) != 0)
+ {
+ uint32_t val = ((attr & DRIVE_MASK) >> DRIVE_SHIFT) - 1;
+ gpio_hal_set_drive_capability(&g_gpio_hal, pin, val);
+ }
+ else
+ {
+ gpio_hal_set_drive_capability(&g_gpio_hal, pin,
+ GPIO_DRIVE_CAP_DEFAULT);
+ }
+
+ if ((attr & FUNCTION_MASK) != 0)
+ {
+ uint32_t val = ((attr & FUNCTION_MASK) >> FUNCTION_SHIFT) - 1;
+ gpio_hal_func_sel(&g_gpio_hal, pin, val);
+ }
+ else
+ {
+ gpio_hal_func_sel(&g_gpio_hal, pin, PIN_FUNC_GPIO);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp_gpio_matrix_in
+ *
+ * Description:
+ * Set GPIO input to a signal.
+ * NOTE: one GPIO can receive inputs from several signals.
+ *
+ * Input Parameters:
+ * pin - GPIO pin to be configured.
+ * - If pin == 0x3c, cancel input to the signal, input 0
+ * to signal.
+ * - If pin == 0x3a, input nothing to signal.
+ * - If pin == 0x38, cancel input to the signal, input 1
+ * to signal.
+ * signal_idx - Signal index.
+ * inv - Flag indicating whether the signal is inverted.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp_gpio_matrix_in(uint32_t pin, uint32_t signal_idx, bool inv)
+{
+ esp_rom_gpio_connect_in_signal(pin, signal_idx, inv);
+}
+
+/****************************************************************************
+ * Name: esp_gpio_matrix_out
+ *
+ * Description:
+ * Set signal output to GPIO.
+ * NOTE: one signal can output to several GPIOs.
+ *
+ * Input Parameters:
+ * pin - GPIO pin to be configured.
+ * signal_idx - Signal index.
+ * - If signal_idx == 0x100, cancel output to the GPIO.
+ * out_inv - Flag indicating whether the signal output is inverted.
+ * oen_inv - Flag indicating whether the signal output enable is
+ * inverted.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, bool out_inv,
+ bool oen_inv)
+{
+ esp_rom_gpio_connect_out_signal(pin, signal_idx, out_inv, oen_inv);
+}
+
+/****************************************************************************
+ * Name: esp_gpiowrite
+ *
+ * Description:
+ * Write one or zero to the selected GPIO pin
+ *
+ * Input Parameters:
+ * pin - GPIO pin to be modified.
+ * value - The value to be written (0 or 1).
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp_gpiowrite(int pin, bool value)
+{
+ DEBUGASSERT(pin >= 0 && pin <= SOC_GPIO_PIN_COUNT);
+
+ gpio_hal_set_level(&g_gpio_hal, pin, value);
+}
+
+/****************************************************************************
+ * Name: esp_gpioread
+ *
+ * Description:
+ * Read one or zero from the selected GPIO pin
+ *
+ * Input Parameters:
+ * pin - GPIO pin to be read.
+ *
+ * Returned Value:
+ * The boolean representation of the input value (true/false).
+ *
+ ****************************************************************************/
+
+bool esp_gpioread(int pin)
+{
+ DEBUGASSERT(pin >= 0 && pin <= SOC_GPIO_PIN_COUNT);
+
+ return gpio_hal_get_level(&g_gpio_hal, pin) != 0;
+}
+
+/****************************************************************************
+ * Name: esp_gpioirqinitialize
+ *
+ * Description:
+ * Initialize logic to support a second level of interrupt decoding for
+ * GPIO pins.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
+void esp_gpioirqinitialize(void)
+{
+ /* Setup the GPIO interrupt. */
+
+ gpio_install_isr_service(ESP_INTR_FLAG_DEFAULT);
+}
+#endif
+
+/****************************************************************************
+ * Name: esp_gpioirqenable
+ *
+ * Description:
+ * Enable the interrupt for specified GPIO
+ *
+ * Input Parameters:
+ * id - GPIO to be enabled.
+ *
+ * Returned Value:
+ * Zero (OK) on success, or -1 (ERROR) in case of failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
+int esp_gpioirqenable(int id)
+{
+ esp_err_t esp_ret;
+
+ esp_ret = gpio_intr_enable(id);
+ if (esp_ret != ESP_OK)
+ {
+ gpioerr("gpio_intr_enable() failed: %d\n", esp_ret);
+ return -ERROR;
+ }
+
+ return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: esp_gpioirqdisable
+ *
+ * Description:
+ * Disable the interrupt for specified GPIO
+ *
+ * Input Parameters:
+ * id - GPIO to be disabled.
+ *
+ * Returned Value:
+ * Zero (OK) on success, or -1 (ERROR) in case of failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
+int esp_gpioirqdisable(int id)
+{
+ esp_err_t esp_ret;
+
+ esp_ret = gpio_intr_disable(id);
+ if (esp_ret != ESP_OK)
+ {
+ gpioerr("gpio_intr_disable() failed: %d\n", esp_ret);
+ return -ERROR;
+ }
+
+ return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: esp_gpio_irq
+ *
+ * Description:
+ * Register or unregister a button interrupt handler for the specified
+ * button ID. Passing a non-NULL handler attaches and enables the ISR for
+ * the button; passing NULL disables the interrupt and removes any
+ * previously registered handler.
+ *
+ * Input Parameters:
+ * id - Identifies the button to be monitored.
+ * irqhandler - The handler to be called when the interrupt occurs.
+ * Set to NULL to disable the interrupt.
+ * arg - Pointer to the argument that will be provided to the
+ * interrupt handler.
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
+int esp_gpio_irq(int id, xcpt_t irqhandler, void *arg)
+{
+ int ret;
+ int irq = ESP_PIN2IRQ(id);
+
+ if (NULL != irqhandler)
+ {
+ esp_err_t esp_ret;
+ struct intr_adapter_from_nuttx *adapter;
+
+ gpioinfo("Attach %p\n", irqhandler);
+
+ adapter = kmm_calloc(1, sizeof(struct intr_adapter_from_nuttx));
+ if (adapter == NULL)
+ {
+ gpioerr("kmm_calloc() failed\n");
+ return -ERROR;
+ }
+
+ adapter->func = irqhandler;
+ adapter->irq = irq;
+ adapter->context = NULL;
+ adapter->arg = arg;
+
+ esp_ret = gpio_isr_handler_add(id, esp_intr_handler_adapter,
+ (void *)adapter);
+ if (esp_ret != ESP_OK)
+ {
+ gpioerr("gpio_isr_handler_add() failed: %d\n", ret);
+ return -ERROR;
+ }
+ }
+ else
+ {
+ gpioinfo("Disable the interrupt\n");
+ gpio_isr_handler_remove(id);
+ }
+
+ return OK;
+}
+#endif
diff --git a/arch/xtensa/src/esp32s3/esp32s3_gpio.h b/arch/xtensa/src/common/espressif/esp_gpio.h
similarity index 69%
rename from arch/xtensa/src/esp32s3/esp32s3_gpio.h
rename to arch/xtensa/src/common/espressif/esp_gpio.h
index 8bcdafba85f..a046eb72583 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_gpio.h
+++ b/arch/xtensa/src/common/espressif/esp_gpio.h
@@ -1,5 +1,7 @@
/****************************************************************************
- * arch/xtensa/src/esp32s3/esp32s3_gpio.h
+ * arch/xtensa/src/common/espressif/esp_gpio.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,33 +20,34 @@
*
****************************************************************************/
-#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_GPIO_H
-#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_GPIO_H
+#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_GPIO_H
+#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
+#include <nuttx/irq.h>
-#include <stdint.h>
#include <stdbool.h>
+#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
-#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */
-#define MATRIX_DETACH_IN_LOW_PIN 0x3c /* Detach non-inverted INPUT signal */
-#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */
+ #define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */
+ #define MATRIX_DETACH_IN_LOW_PIN 0x3c /* Detach non-inverted INPUT signal */
+ #define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */
-/* Bit-encoded input to esp32s3_configgpio() ********************************/
+/* Bit-encoded input to esp_configgpio() ************************************/
-/* Encoded pin attributes used with esp32s3_configgpio()
+/* Encoded pin attributes used with esp_configgpio()
*
- * 8 7 6 5 4 3 2 1 0
- * -- -- -- -- -- -- -- -- --
- * FN FN FN OD PD PU F O I
+ * 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+ * -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ * IT IT IT DR DR DR FN FN FN OD PD PU F O I
*/
#define MODE_SHIFT 0
@@ -75,6 +78,15 @@
# define DRIVE_2 (3 << DRIVE_SHIFT)
# define DRIVE_3 (4 << DRIVE_SHIFT)
+#define INTR_TYPE_SHIFT 12
+#define INTR_TYPE_MASK (7 << INTR_TYPE_SHIFT)
+# define DISABLED (0 << INTR_TYPE_SHIFT)
+# define RISING (1 << INTR_TYPE_SHIFT)
+# define FALLING (2 << INTR_TYPE_SHIFT)
+# define CHANGE (3 << INTR_TYPE_SHIFT)
+# define ONLOW (4 << INTR_TYPE_SHIFT)
+# define ONHIGH (5 << INTR_TYPE_SHIFT)
+
#define INPUT_PULLUP (INPUT | PULLUP)
#define INPUT_PULLDOWN (INPUT | PULLDOWN)
#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN)
@@ -93,33 +105,6 @@
# define OUTPUT_FUNCTION_5 (OUTPUT_FUNCTION | FUNCTION_5)
# define OUTPUT_FUNCTION_6 (OUTPUT_FUNCTION | FUNCTION_6)
-/* Interrupt type used with esp32s3_gpioirqenable() */
-
-#define DISABLED 0x00
-#define RISING 0x01
-#define FALLING 0x02
-#define CHANGE 0x03
-#define ONLOW 0x04
-#define ONHIGH 0x05
-
-/* Check whether it is a valid GPIO number */
-
-#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num >= 0) && \
- (((1ULL << (gpio_num)) & \
- SOC_GPIO_VALID_GPIO_MASK) != 0))
-
-/* Check whether it can be a valid GPIO number of output mode */
-
-#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) \
- ((gpio_num >= 0) && \
- (((1ULL << (gpio_num)) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0))
-
-/* Check whether it can be a valid digital I/O pad */
-
-#define GPIO_IS_VALID_DIGITAL_IO_PAD(gpio_num) \
- ((gpio_num >= 0) && \
- (((1ULL << (gpio_num)) & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK) != 0))
-
/****************************************************************************
* Public Types
****************************************************************************/
@@ -149,172 +134,194 @@ extern "C"
****************************************************************************/
/****************************************************************************
- * Name: esp32s3_gpioirqinitialize
+ * Name: esp_configgpio
*
* Description:
- * Initialize logic to support a second level of interrupt decoding for
- * GPIO pins.
+ * Configure a GPIO pin based on encoded pin attributes.
*
* Input Parameters:
- * None.
+ * pin - GPIO pin to be configured.
+ * attr - Attributes to be configured for the selected GPIO pin.
+ * The following attributes are accepted:
+ * - Direction (OUTPUT or INPUT)
+ * - Pull (PULLUP, PULLDOWN or OPENDRAIN)
+ * - Function (if not provided, assume function GPIO by
+ * default)
+ * - Drive strength (if not provided, assume DRIVE_2 by
+ * default)
+ *
+ * Returned Value:
+ * Zero (OK) on success, or -1 (ERROR) in case of failure.
+ *
+ ****************************************************************************/
+
+int esp_configgpio(int pin, gpio_pinattr_t attr);
+
+/****************************************************************************
+ * Name: esp_gpio_matrix_in
+ *
+ * Description:
+ * Set GPIO input to a signal.
+ * NOTE: one GPIO can receive inputs from several signals.
+ *
+ * Input Parameters:
+ * pin - GPIO pin to be configured.
+ * - If pin == 0x3c, cancel input to the signal, input 0
+ * to signal.
+ * - If pin == 0x3a, input nothing to signal.
+ * - If pin == 0x38, cancel input to the signal, input 1
+ * to signal.
+ * signal_idx - Signal index.
+ * inv - Flag indicating whether the signal is inverted.
*
* Returned Value:
* None.
*
****************************************************************************/
-#ifdef CONFIG_ESP32S3_GPIO_IRQ
-void esp32s3_gpioirqinitialize(void);
-#else
-# define esp32s3_gpioirqinitialize()
-#endif
+void esp_gpio_matrix_in(uint32_t pin, uint32_t signal_idx, bool inv);
/****************************************************************************
- * Name: esp32s3_configgpio
+ * Name: esp_gpio_matrix_out
*
* Description:
- * Configure a GPIO pin based on encoded pin attributes.
+ * Set signal output to GPIO.
+ * NOTE: one signal can output to several GPIOs.
*
* Input Parameters:
* pin - GPIO pin to be configured.
- * attr - Attributes to be configured for the selected GPIO pin.
- * The following attributes are accepted:
- * - Direction (OUTPUT or INPUT)
- * - Pull (PULLUP, PULLDOWN or OPENDRAIN)
- * - Function (if not provided, assume function GPIO by
- * default)
- * - Drive strength (if not provided, assume DRIVE_2 by
- * default)
+ * signal_idx - Signal index.
+ * - If signal_idx == 0x100, cancel output to the GPIO.
+ * out_inv - Flag indicating whether the signal output is inverted.
+ * oen_inv - Flag indicating whether the signal output enable is
+ * inverted.
*
* Returned Value:
- * Zero (OK) on success, or -1 (ERROR) in case of failure.
+ * None.
*
****************************************************************************/
-int esp32s3_configgpio(uint32_t pin, gpio_pinattr_t attr);
+void esp_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, bool out_inv,
+ bool oen_inv);
/****************************************************************************
- * Name: esp32s3_gpiowrite
+ * Name: esp_gpiowrite
*
* Description:
- * Write one or zero to the selected GPIO pin.
+ * Write one or zero to the selected GPIO pin
*
* Input Parameters:
- * pin - GPIO pin to be written.
- * value - Value to be written to the GPIO pin. True will output
- * 1 (one) to the GPIO, while false will output 0 (zero).
+ * pin - GPIO pin to be modified.
+ * value - The value to be written (0 or 1).
*
* Returned Value:
* None.
*
****************************************************************************/
-void esp32s3_gpiowrite(int pin, bool value);
+void esp_gpiowrite(int pin, bool value);
/****************************************************************************
- * Name: esp32s3_gpioread
+ * Name: esp_gpioread
*
* Description:
- * Read one or zero from the selected GPIO pin.
+ * Read one or zero from the selected GPIO pin
*
* Input Parameters:
* pin - GPIO pin to be read.
*
* Returned Value:
- * True in case the read value is 1 (one). If 0 (zero), then false will be
- * returned.
+ * The boolean representation of the input value (true/false).
*
****************************************************************************/
-bool esp32s3_gpioread(int pin);
+bool esp_gpioread(int pin);
/****************************************************************************
- * Name: esp32s3_gpioirqenable
+ * Name: esp_gpioirqinitialize
*
* Description:
- * Enable the interrupt for the specified GPIO IRQ.
+ * Initialize logic to support a second level of interrupt decoding for
+ * GPIO pins.
*
* Input Parameters:
- * irq - Identifier of the interrupt request.
- * intrtype - Interrupt type, select from gpio_intrtype_t.
+ * None.
*
* Returned Value:
* None.
*
****************************************************************************/
-#ifdef CONFIG_ESP32S3_GPIO_IRQ
-void esp32s3_gpioirqenable(int irq, gpio_intrtype_t intrtype);
+#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
+void esp_gpioirqinitialize(void);
#else
-# define esp32s3_gpioirqenable(irq,intrtype)
+# define esp_gpioirqinitialize()
#endif
/****************************************************************************
- * Name: esp32s3_gpioirqdisable
+ * Name: esp_gpioirqenable
*
* Description:
- * Disable the interrupt for the specified GPIO IRQ.
+ * Enable the interrupt for specified GPIO
*
* Input Parameters:
- * irq - Identifier of the interrupt request.
+ * id - GPIO to be enabled.
*
* Returned Value:
- * None.
+ * Zero (OK) on success, or -1 (ERROR) in case of failure.
*
****************************************************************************/
-#ifdef CONFIG_ESP32S3_GPIO_IRQ
-void esp32s3_gpioirqdisable(int irq);
+#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
+int esp_gpioirqenable(int id);
#else
-# define esp32s3_gpioirqdisable(irq)
+# define esp_gpioirqenable(id)
#endif
/****************************************************************************
- * Name: esp32s3_gpio_matrix_in
+ * Name: esp_gpioirqdisable
*
* Description:
- * Set GPIO input to a signal.
- * NOTE: one GPIO can receive inputs from several signals.
+ * Disable the interrupt for specified GPIO
*
* Input Parameters:
- * pin - GPIO pin to be configured.
- * - If pin == 0x3c, cancel input to the signal, input 0
- * to signal.
- * - If pin == 0x3a, input nothing to signal.
- * - If pin == 0x38, cancel input to the signal, input 1
- * to signal.
- * signal_idx - Signal index.
- * inv - Flag indicating whether the signal is inverted.
+ * id - GPIO to be disabled.
*
* Returned Value:
- * None.
+ * Zero (OK) on success, or -1 (ERROR) in case of failure.
*
****************************************************************************/
-void esp32s3_gpio_matrix_in(uint32_t pin, uint32_t signal_idx, bool inv);
+#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
+int esp_gpioirqdisable(int id);
+#else
+# define esp_gpioirqdisable(id)
+#endif
/****************************************************************************
- * Name: esp32s3_gpio_matrix_out
+ * Name: esp_gpio_irq
*
* Description:
- * Set signal output to GPIO.
- * NOTE: one signal can output to several GPIOs.
+ * Register or unregister a button interrupt handler for the specified
+ * button ID. Passing a non-NULL handler attaches and enables the ISR for
+ * the button; passing NULL disables the interrupt and removes any
+ * previously registered handler.
*
* Input Parameters:
- * pin - GPIO pin to be configured.
- * signal_idx - Signal index.
- * - If signal_idx == 0x100, cancel output to the GPIO.
- * out_inv - Flag indicating whether the signal output is inverted.
- * oen_inv - Flag indicating whether the signal output enable is
- * inverted.
+ * id - Identifies the button to be monitored.
+ * irqhandler - The handler to be called when the interrupt occurs.
+ * Set to NULL to disable the interrupt.
+ * arg - Pointer to the argument that will be provided to the
+ * interrupt handler.
*
* Returned Value:
- * None.
+ * Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/
-void esp32s3_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, bool out_inv,
- bool oen_inv);
+#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
+int esp_gpio_irq(int id, xcpt_t irqhandler, void *arg);
+#endif
#ifdef __cplusplus
}
@@ -322,4 +329,4 @@ void esp32s3_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, bool out_inv,
#undef EXTERN
#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_GPIO_H */
+#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_GPIO_H */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h b/arch/xtensa/src/common/espressif/esp_hr_timer.h
similarity index 52%
rename from arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h
rename to arch/xtensa/src/common/espressif/esp_hr_timer.h
index 3546c0474fa..2443db8dccd 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h
+++ b/arch/xtensa/src/common/espressif/esp_hr_timer.h
@@ -1,5 +1,7 @@
/****************************************************************************
- * arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h
+ * arch/xtensa/src/common/espressif/esp_hr_timer.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,39 +20,15 @@
*
****************************************************************************/
-#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_LOWERHALF_H
-#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_LOWERHALF_H
+#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_HR_TIMER_H
+#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_HR_TIMER_H
/****************************************************************************
* Included Files
****************************************************************************/
-#include <nuttx/config.h>
-
-#ifdef CONFIG_RTC_DRIVER
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: esp32s3_rtc_driverinit
- *
- * Description:
- * Bind the configuration timer to a timer lower half instance and register
- * the timer drivers at 'devpath'
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * Zero (OK) is returned on success; A negated errno value is returned
- * to indicate the nature of any failure.
- *
- ****************************************************************************/
-
-int esp32s3_rtc_driverinit(void);
+/* This is a compatibility wrapper for the new ESP-HAL timer adapter */
-#endif /* CONFIG_RTC_DRIVER */
+#include "esp_timer_adapter.h"
-#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_LOWERHALF_H */
+#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_HR_TIMER_H */
diff --git a/arch/xtensa/src/common/espressif/esp_i2c_bitbang.c b/arch/xtensa/src/common/espressif/esp_i2c_bitbang.c
index e1f117e4b66..dcf098b259c 100644
--- a/arch/xtensa/src/common/espressif/esp_i2c_bitbang.c
+++ b/arch/xtensa/src/common/espressif/esp_i2c_bitbang.c
@@ -33,16 +33,16 @@
#include <nuttx/kmalloc.h>
#include "espressif/esp_i2c_bitbang.h"
+#include "espressif/esp_gpio.h"
-#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#include "esp32s3_gpio.h"
-#include "hardware/esp32s3_gpio_sigmap.h"
+#if defined(CONFIG_ARCH_CHIP_ESP32)
+# include "esp32_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#include "esp32s2_gpio.h"
-#include "esp32s2_gpio_sigmap.h"
+# include "esp32s2_gpio_sigmap.h"
+#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
+# include "esp32s3_gpio_sigmap.h"
#else
-#include "esp32_gpio.h"
-#include "esp32_gpio_sigmap.h"
+# error "Unsupported chip"
#endif
/****************************************************************************
@@ -50,23 +50,23 @@
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#define CONFIG_GPIO(pin, attr) esp32s3_configgpio(pin, attr)
-#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s3_gpio_matrix_out(pin, \
+#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
+#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
-#define GPIO_WRITE(pin, value) esp32s3_gpiowrite(pin, value)
-#define GPIO_READ(pin) esp32s3_gpioread(pin)
+#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
+#define GPIO_READ(pin) esp_gpioread(pin)
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#define CONFIG_GPIO(pin, attr) esp32s2_configgpio(pin, attr)
-#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s2_gpio_matrix_out(pin, \
+#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
+#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
-#define GPIO_WRITE(pin, value) esp32s2_gpiowrite(pin, value)
-#define GPIO_READ(pin) esp32s2_gpioread(pin)
+#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
+#define GPIO_READ(pin) esp_gpioread(pin)
#else
-#define CONFIG_GPIO(pin, attr) esp32_configgpio(pin, attr)
-#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32_gpio_matrix_out(pin, \
+#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
+#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
-#define GPIO_WRITE(pin, value) esp32_gpiowrite(pin, value)
-#define GPIO_READ(pin) esp3_gpioread(pin)
+#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
+#define GPIO_READ(pin) esp_gpioread(pin)
#endif
/****************************************************************************
diff --git a/arch/xtensa/src/common/espressif/esp_i2c_slave.c b/arch/xtensa/src/common/espressif/esp_i2c_slave.c
index 59a6db001c7..f2d8a15a1cb 100644
--- a/arch/xtensa/src/common/espressif/esp_i2c_slave.c
+++ b/arch/xtensa/src/common/espressif/esp_i2c_slave.c
@@ -54,16 +54,16 @@
#include "esp_i2c_slave.h"
#include "xtensa.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#include "esp32s3_gpio.h"
-#include "esp32s3_irq.h"
+#include "esp_gpio.h"
+#include "esp_irq.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#include "esp32s2_gpio.h"
-#include "esp32s2_irq.h"
+#include "espressif/esp_gpio.h"
+#include "espressif/esp_irq.h"
#include "esp32s2_gpio_sigmap.h"
#else
-#include "esp32_gpio.h"
-#include "esp32_irq.h"
+#include "esp_gpio.h"
+#include "esp_irq.h"
#include "esp32_gpio_sigmap.h"
#endif
@@ -73,7 +73,7 @@
#include "hal/i2c_ll.h"
#include "soc/system_reg.h"
#include "soc/gpio_sig_map.h"
-#include "soc/i2c_periph.h"
+#include "hal/i2c_periph.h"
/****************************************************************************
* Pre-processor Definitions
@@ -85,48 +85,21 @@
#define CONFIG_ESPRESSIF_I2C1_SCLPIN CONFIG_ESP32S3_I2C1_SCLPIN
#define CONFIG_ESPRESSIF_I2C1_SDAPIN CONFIG_ESP32S3_I2C1_SDAPIN
#define ESP_IRQ_I2C_EXT0 ESP32S3_IRQ_I2C_EXT0
-#define ESP_IRQ_TRIGGER_LEVEL ESP32S3_CPUINT_LEVEL
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S3_INT_PRIO_DEF
-#define esp_setup_irq esp32s3_setup_irq
-#define esp_teardown_irq esp32s3_teardown_irq
-#define esp_gpiowrite(pin, value) esp32s3_gpiowrite(pin, value)
-#define esp_configgpio(pin, attr) esp32s3_configgpio(pin, attr)
-#define esp_gpio_matrix_in(pin, idx, inv) esp32s3_gpio_matrix_in(pin, \
- idx, inv)
-#define esp_gpio_matrix_out(pin, idx, inv, en_inv) esp32s3_gpio_matrix_out(pin, \
- idx, inv, en_inv)
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define CONFIG_ESPRESSIF_I2C0_SCLPIN CONFIG_ESP32S2_I2C0_SCLPIN
#define CONFIG_ESPRESSIF_I2C0_SDAPIN CONFIG_ESP32S2_I2C0_SDAPIN
#define CONFIG_ESPRESSIF_I2C1_SCLPIN CONFIG_ESP32S2_I2C1_SCLPIN
#define CONFIG_ESPRESSIF_I2C1_SDAPIN CONFIG_ESP32S2_I2C1_SDAPIN
#define ESP_IRQ_I2C_EXT0 ESP32S2_IRQ_I2C_EXT0
-#define ESP_IRQ_TRIGGER_LEVEL ESP32S2_CPUINT_LEVEL
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S2_INT_PRIO_DEF
-#define esp_setup_irq esp32s2_setup_irq
-#define esp_teardown_irq esp32s2_teardown_irq
-#define esp_gpiowrite(pin, value) esp32s2_gpiowrite(pin, value)
-#define esp_configgpio(pin, attr) esp32s2_configgpio(pin, attr)
-#define esp_gpio_matrix_in(pin, idx, inv, en_inv) esp32s2_gpio_matrix_in(pin, \
- idx, inv, en_inv)
-#define esp_gpio_matrix_out(pin, idx, inv, en_inv) esp32s2_gpio_matrix_out(pin, \
- idx, inv, en_inv)
#else
#define CONFIG_ESPRESSIF_I2C0_SCLPIN CONFIG_ESP32_I2C0_SCLPIN
#define CONFIG_ESPRESSIF_I2C0_SDAPIN CONFIG_ESP32_I2C0_SDAPIN
#define CONFIG_ESPRESSIF_I2C1_SCLPIN CONFIG_ESP32_I2C1_SCLPIN
#define CONFIG_ESPRESSIF_I2C1_SDAPIN CONFIG_ESP32_I2C1_SDAPIN
#define ESP_IRQ_I2C_EXT0 ESP32_IRQ_I2C_EXT0
-#define ESP_IRQ_TRIGGER_LEVEL ESP32_CPUINT_LEVEL
#define ESP_IRQ_PRIORITY_DEFAULT 1
-#define esp_setup_irq esp32_setup_irq
-#define esp_teardown_irq esp32_teardown_irq
-#define esp_gpiowrite(pin, value) esp32_gpiowrite(pin, value)
-#define esp_configgpio(pin, attr) esp32_configgpio(pin, attr)
-#define esp_gpio_matrix_in(pin, idx, inv) esp32_gpio_matrix_in(pin, \
- idx, inv)
-#define esp_gpio_matrix_out(pin, idx, inv) esp32_gpio_matrix_out(pin, \
- idx, inv)
#endif
#define I2C_FIFO_FULL_THRESH_VAL 28
@@ -935,20 +908,13 @@ struct i2c_slave_s *esp_i2cbus_slave_initialize(int port, int addr)
/* Disable the previous IRQ */
up_disable_irq(config->irq);
- esp_teardown_irq(
-#ifndef CONFIG_ARCH_CHIP_ESP32S2
- this_cpu(),
-#endif
- config->periph, priv->cpuint);
+ esp_teardown_irq(config->periph, priv->cpuint);
}
- priv->cpuint = esp_setup_irq(
-#ifndef CONFIG_ARCH_CHIP_ESP32S2
- this_cpu(),
-#endif
- config->periph,
+ priv->cpuint = esp_setup_irq(config->periph,
ESP_IRQ_PRIORITY_DEFAULT,
- ESP_IRQ_TRIGGER_LEVEL);
+ ESP_IRQ_TRIGGER_LEVEL,
+ esp_i2c_slave_irq, priv);
if (priv->cpuint < 0)
{
/* Failed to allocate a CPU interrupt of this type. */
@@ -959,23 +925,6 @@ struct i2c_slave_s *esp_i2cbus_slave_initialize(int port, int addr)
return NULL;
}
- ret = irq_attach(config->irq, esp_i2c_slave_irq, priv);
- if (ret != OK)
- {
- /* Failed to attach IRQ, free the allocated CPU interrupt */
-
- esp_teardown_irq(
-#ifndef CONFIG_ARCH_CHIP_ESP32S2
- this_cpu(),
-#endif
- config->periph, priv->cpuint);
- priv->cpuint = -ENOMEM;
- priv->refs--;
- nxmutex_unlock(&priv->lock);
-
- return NULL;
- }
-
/* Enable the CPU interrupt that is linked to the I2C device. */
up_enable_irq(config->irq);
diff --git a/arch/xtensa/src/common/espressif/esp_i2s.c b/arch/xtensa/src/common/espressif/esp_i2s.c
index 40f4ea45113..a506d753ee3 100644
--- a/arch/xtensa/src/common/espressif/esp_i2s.c
+++ b/arch/xtensa/src/common/espressif/esp_i2s.c
@@ -39,34 +39,32 @@
#include <arch/irq.h>
#include "xtensa.h"
+#include "esp_gpio.h"
+#include "esp_irq.h"
#include "esp_i2s.h"
-#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#include "esp32s3_gpio.h"
-#include "hardware/esp32s3_gpio_sigmap.h"
-#include "esp32s3_dma.h"
-#include "hardware/esp32s3_dma.h"
-#include "esp32s3_irq.h"
+
+#if defined(CONFIG_ARCH_CHIP_ESP32)
+# include "esp32_dma.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#include "esp32s2_gpio.h"
-#include "hardware/esp32s2_gpio_sigmap.h"
-#include "esp32s2_dma.h"
-#include "esp32s2_irq.h"
-#else
-#include "esp32_gpio.h"
-#include "esp32_dma.h"
-#include "esp32_irq.h"
+# include "espressif/esp_gpio.h"
+# include "hardware/esp32s2_gpio_sigmap.h"
+# include "esp32s2_dma.h"
+#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
+# include "hardware/esp32s3_gpio_sigmap.h"
+# include "esp32s3_dma.h"
+# include "hardware/esp32s3_dma.h"
#endif
#include "hal/i2s_hal.h"
#include "hal/i2s_ll.h"
-#include "soc/i2s_periph.h"
+#include "hal/i2s_periph.h"
#include "soc/i2s_reg.h"
#include "hal/i2s_types.h"
#include "soc/gpio_sig_map.h"
#include "periph_ctrl.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
# include "soc/gdma_reg.h"
-# include "soc/gdma_periph.h"
+# include "hal/gdma_periph.h"
# include "hal/gdma_ll.h"
#endif
@@ -82,49 +80,27 @@
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#define esp_setup_irq esp32s3_setup_irq
-#define esp_teardown_irq esp32s3_teardown_irq
-#define esp_configgpio esp32s3_configgpio
-#define esp_gpio_matrix_in esp32s3_gpio_matrix_in
-#define esp_gpio_matrix_out esp32s3_gpio_matrix_out
-#define esp_gpiowrite esp32s3_gpiowrite
#define esp_dma_init esp32s3_dma_init
#define esp_dma_request esp32s3_dma_request
#define esp_dma_setup esp32s3_dma_setup
#define esp_dma_load esp32s3_dma_load
#define esp_dma_enable esp32s3_dma_enable
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S3_INT_PRIO_DEF
-#define ESP_IRQ_TRIGGER_LEVEL ESP32S3_CPUINT_LEVEL
+#define ESP_IRQ_TRIGGER_LEVEL ESP_IRQ_TRIGGER_LEVEL
#define ESPRESSIF_DMA_BUFLEN_MAX ESP32S3_DMA_BUFLEN_MAX
#define ESPRESSIF_DMA_PERIPH_I2S ESP32S3_DMA_PERIPH_I2S1
-#define ESP_SOURCE2IRQ ESP32S3_PERIPH2IRQ
#define esp_dmadesc_s esp32s3_dmadesc_s
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#define esp_setup_irq esp32s2_setup_irq
-#define esp_teardown_irq esp32s2_teardown_irq
-#define esp_configgpio esp32s2_configgpio
-#define esp_gpio_matrix_in esp32s2_gpio_matrix_in
-#define esp_gpio_matrix_out esp32s2_gpio_matrix_out
-#define esp_gpiowrite esp32s2_gpiowrite
#define esp_dma_setup esp32s2_dma_init
-#define ESP_SOURCE2IRQ ESP32S2_PERIPH2IRQ
#define esp_dmadesc_s esp32s2_dmadesc_s
#define ESPRESSIF_DMA_BUFLEN_MAX ESP32S2_DMA_DATALEN_MAX
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S2_INT_PRIO_DEF
-#define ESP_IRQ_TRIGGER_LEVEL ESP32S2_CPUINT_LEVEL
#define I2S0O_SD_OUT_IDX I2S0O_DATA_OUT23_IDX
#define I2S0I_SD_IN_IDX I2S0I_DATA_IN15_IDX
#define I2S0_MCLK_OUT_IDX CLK_I2S_MUX_IDX
#elif defined(CONFIG_ARCH_CHIP_ESP32)
-#define esp_setup_irq esp32_setup_irq
-#define esp_teardown_irq esp32_teardown_irq
-#define esp_configgpio esp32_configgpio
-#define esp_gpio_matrix_in esp32_gpio_matrix_in
-#define esp_gpio_matrix_out esp32_gpio_matrix_out
-#define esp_gpiowrite esp32_gpiowrite
#define esp_dma_setup esp32_dma_init
#define esp_dmadesc_s esp32_dmadesc_s
-#define ESP_SOURCE2IRQ ESP32_PERIPH2IRQ
#define ESPRESSIF_DMA_BUFLEN_MAX ESP32_DMA_DATALEN_MAX
#define I2S0O_SD_OUT_IDX I2S0O_DATA_OUT23_IDX
#define I2S0I_SD_IN_IDX I2S0I_DATA_IN15_IDX
@@ -133,7 +109,6 @@
#define I2S1I_SD_IN_IDX I2S1I_DATA_IN15_IDX
#define I2S1_MCLK_OUT_IDX -1
#define ESP_IRQ_PRIORITY_DEFAULT 1
-#define ESP_IRQ_TRIGGER_LEVEL ESP32_CPUINT_LEVEL
#endif
#if defined(CONFIG_ESPRESSIF_I2S0_DATA_BIT_WIDTH_8BIT) || \
@@ -343,7 +318,6 @@ typedef enum
struct esp_i2s_config_s
{
uint32_t port; /* I2S port */
- periph_module_t module; /* I2S peripheral module */
uint32_t role; /* I2S port role (master or slave) */
uint8_t data_width; /* I2S sample data width */
uint32_t rate; /* I2S sample-rate */
@@ -588,7 +562,6 @@ i2s_hal_clock_info_t clk_info_i2s0 =
static const struct esp_i2s_config_s esp_i2s0_config =
{
.port = 0,
- .module = PERIPH_I2S0_MODULE,
#ifdef CONFIG_ESPRESSIF_I2S0_ROLE_MASTER
.role = I2S_ROLE_MASTER,
#else
@@ -662,7 +635,6 @@ i2s_hal_clock_info_t clk_info_i2s1 =
static const struct esp_i2s_config_s esp_i2s1_config =
{
.port = 1,
- .module = PERIPH_I2S1_MODULE,
#ifdef CONFIG_ESPRESSIF_I2S1_ROLE_MASTER
.role = I2S_ROLE_MASTER,
#else
@@ -1584,8 +1556,6 @@ static void i2s_configure(struct esp_i2s_s *priv)
/* Set peripheral clock and clear reset */
- periph_module_enable(priv->config->module);
-
i2s_hal_init(priv->config->ctx, priv->config->port);
I2S_RCC_ATOMIC()
{
@@ -3094,9 +3064,11 @@ static int i2s_dma_setup(struct esp_i2s_s *priv)
{
periph =
gdma_periph_signals.groups[0].pairs[priv->dma_channel].tx_irq_id;
- int cpuint = esp_setup_irq(priv->cpu,
- periph, 1,
- ESP_IRQ_TRIGGER_LEVEL);
+
+ ASSERT(this_cpu() == priv->cpu);
+ int cpuint = esp_setup_irq(periph, 1,
+ ESP_IRQ_TRIGGER_LEVEL,
+ i2s_interrupt, priv);
if (cpuint < 0)
{
i2serr("Failed to allocate a CPU interrupt.\n");
@@ -3104,15 +3076,6 @@ static int i2s_dma_setup(struct esp_i2s_s *priv)
}
priv->tx_irq = ESP_SOURCE2IRQ(periph);
- ret = irq_attach(priv->tx_irq, i2s_interrupt, priv);
- if (ret != OK)
- {
- i2serr("Couldn't attach IRQ to handler.\n");
- esp_teardown_irq(priv->cpu,
- periph,
- cpuint);
- return ret;
- }
}
# endif /* I2S_HAVE_TX */
@@ -3121,9 +3084,11 @@ static int i2s_dma_setup(struct esp_i2s_s *priv)
{
periph =
gdma_periph_signals.groups[0].pairs[priv->dma_channel].rx_irq_id;
- int cpuint = esp_setup_irq(priv->cpu,
- periph, 1,
- ESP_IRQ_TRIGGER_LEVEL);
+
+ ASSERT(this_cpu() == priv->cpu);
+ int cpuint = esp_setup_irq(periph, 1,
+ ESP_IRQ_TRIGGER_LEVEL,
+ i2s_interrupt, priv);
if (cpuint < 0)
{
i2serr("Failed to allocate a CPU interrupt.\n");
@@ -3131,15 +3096,6 @@ static int i2s_dma_setup(struct esp_i2s_s *priv)
}
priv->rx_irq = ESP_SOURCE2IRQ(periph);
- ret = irq_attach(priv->rx_irq, i2s_interrupt, priv);
- if (ret != OK)
- {
- i2serr("Couldn't attach IRQ to handler.\n");
- esp_teardown_irq(priv->cpu,
- periph,
- cpuint);
- return ret;
- }
}
# endif /* I2S_HAVE_RX */
#else
@@ -3153,31 +3109,15 @@ static int i2s_dma_setup(struct esp_i2s_s *priv)
priv->cpu = this_cpu();
periph = i2s_periph_signal[priv->config->port].irq;
- int cpuint = esp_setup_irq(
-# ifndef CONFIG_ARCH_CHIP_ESP32S2
- priv->cpu,
-# endif
- periph, 1,
- ESP_IRQ_TRIGGER_LEVEL);
+ int cpuint = esp_setup_irq(periph,
+ ESP_IRQ_PRIORITY_DEFAULT,
+ ESP_IRQ_TRIGGER_LEVEL,
+ i2s_interrupt, priv);
if (cpuint < 0)
{
i2serr("Failed to allocate a CPU interrupt.\n");
return ERROR;
}
-
- int irq = ESP_SOURCE2IRQ(periph);
- ret = irq_attach(irq, i2s_interrupt, priv);
- if (ret != OK)
- {
- i2serr("Couldn't attach IRQ to handler.\n");
- esp_teardown_irq(
-#ifndef CONFIG_ARCH_CHIP_ESP32S2
- priv->cpu,
-#endif
- periph,
- cpuint);
- return ret;
- }
#endif
return OK;
diff --git a/arch/xtensa/src/common/espressif/esp_irq.c b/arch/xtensa/src/common/espressif/esp_irq.c
new file mode 100644
index 00000000000..618f7074319
--- /dev/null
+++ b/arch/xtensa/src/common/espressif/esp_irq.c
@@ -0,0 +1,955 @@
+/****************************************************************************
+ * arch/xtensa/src/common/espressif/esp_irq.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <assert.h>
+#include <debug.h>
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/irq.h>
+#include <arch/board/board.h>
+#include <irq/irq.h>
+
+#include "xtensa.h"
+
+#include "esp_irq.h"
+
+#include "esp_intr_alloc.h"
+#include "esp_attr.h"
+#include "esp_bit_defs.h"
+#include "esp_cpu.h"
+#include "esp_rom_sys.h"
+#include "rom/ets_sys.h"
+
+#if defined(CONFIG_ARCH_CHIP_ESP32)
+# include "hardware/esp32_soc.h"
+# include "esp_gpio.h"
+# include "esp32_rtc_gpio.h"
+# ifdef CONFIG_SMP
+# include "esp32_smp.h"
+# define ESP_FROMCPU1_PERIPH ESP32_PERIPH_CPU_CPU1
+# define ESP_FROMCPU1_IRQ ESP32_IRQ_CPU_CPU1
+# define esp_fromcpu1_interrupt esp32_fromcpu1_interrupt
+# endif
+# define ESP_NCPUINTS ESP32_NCPUINTS
+# define ESP_NPERIPHERALS ESP32_NPERIPHERALS
+# define ESP_CPUINT_PERIPHSET ESP32_CPUINT_PERIPHSET
+# define ESP_IRQ_DEMUX XTENSA_IRQ_DEMUX - ETS_INTERNAL_INTR_SOURCE_OFF
+# define ESP_IRQ_SYSCALL XTENSA_IRQ_SYSCALL - ETS_INTERNAL_INTR_SOURCE_OFF
+# define ESP_IRQ_FIRSTPERIPH XTENSA_IRQ_FIRSTPERIPH
+#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
+# include "hardware/esp32s2_soc.h"
+# include "esp_gpio.h"
+# include "esp32s2_rtc_gpio.h"
+# define ESP_NCPUINTS ESP32S2_NCPUINTS
+# define ESP_NPERIPHERALS ESP32S2_NPERIPHERALS
+# define ESP_CPUINT_PERIPHSET ESP32S2_CPUINT_PERIPHSET
+# define ESP_IRQ_DEMUX XTENSA_IRQ_DEMUX - ETS_INTERNAL_INTR_SOURCE_OFF
+# define ESP_IRQ_SYSCALL XTENSA_IRQ_SYSCALL - ETS_INTERNAL_INTR_SOURCE_OFF
+# define ESP_IRQ_FIRSTPERIPH XTENSA_IRQ_FIRSTPERIPH
+#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
+# include "hardware/esp32s3_soc.h"
+# include "esp_gpio.h"
+# include "esp32s3_rtc_gpio.h"
+# include "esp32s3_userspace.h"
+# ifdef CONFIG_SMP
+# include "esp32s3_smp.h"
+# define ESP_FROMCPU1_PERIPH ESP32S3_PERIPH_INT_FROM_CPU1
+# define ESP_FROMCPU1_IRQ ESP32S3_IRQ_INT_FROM_CPU1
+# define esp_fromcpu1_interrupt esp32s3_fromcpu1_interrupt
+# endif
+# define ESP_NCPUINTS ESP32S3_NCPUINTS
+# define ESP_NPERIPHERALS ESP32S3_NPERIPHERALS
+# define ESP_CPUINT_PERIPHSET ESP32S3_CPUINT_PERIPHSET
+# define ESP_IRQ_DEMUX XTENSA_IRQ_DEMUX - ETS_INTERNAL_INTR_SOURCE_OFF
+# define ESP_IRQ_SYSCALL XTENSA_IRQ_SYSCALL - ETS_INTERNAL_INTR_SOURCE_OFF
+# define ESP_IRQ_FIRSTPERIPH XTENSA_IRQ_FIRSTPERIPH
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP_NCPUS
+# define ESP_NCPUS CONFIG_SMP_NCPUS
+#else
+# define ESP_NCPUS 1
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_ESP32S3) && defined(CONFIG_BUILD_PROTECTED)
+# define esp_pmsirqinitialize() esp32s3_pmsirqinitialize()
+#else
+# define esp_pmsirqinitialize()
+#endif
+
+#ifdef CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC
+# ifndef CONFIG_ARCH_IRQ_TO_NDX
+# error "CONFIG_ARCH_IRQ_TO_NDX must be enabled for Xtensa-based \
+ Espressif SoCs. Run 'make menuconfig' to select it."
+# endif
+# if CONFIG_ARCH_NUSER_INTERRUPTS != 2
+# error "CONFIG_ARCH_NUSER_INTERRUPTS must be 2 for Xtensa-based \
+ Espressif SoCs. Run 'make menuconfig' to set it."
+# endif
+#else
+# error "CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC must be enabled for \
+ Xtensa-based Espressif SoCs. Additionally, enable \
+ CONFIG_ARCH_IRQ_TO_NDX and set CONFIG_ARCH_NUSER_INTERRUPTS to 2.\
+ Run 'make menuconfig' to select and set these options."
+#endif
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static void esp_clear_handle(int cpu, int irq);
+
+/* External functions from esp_xtensa_intr.c */
+
+extern void esp_xtensa_intr_init(void);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Map an IRQ to a handle to which the interrupt source is attached to. */
+
+static volatile intr_handle_t g_handle_map[CONFIG_SMP_NCPUS][NR_IRQS];
+
+#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG
+/* The g_iram_count keeps track of how many times such an IRQ ran when the
+ * non-IRAM interrupts were disabled.
+ */
+
+static uint64_t g_iram_count[CONFIG_SMP_NCPUS][NR_IRQS];
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
+/* In the SMP configuration, we will need custom interrupt stacks.
+ * These definitions provide the aligned stack allocations.
+ */
+
+# define INTSTACK_ALLOC (CONFIG_SMP_NCPUS * INTSTACK_SIZE)
+
+static uint32_t g_intstackalloc[INTSTACK_ALLOC >> 2];
+
+/* These definitions provide the "top" of the push-down stacks. */
+
+uintptr_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] =
+{
+ (uintptr_t)g_intstackalloc + INTSTACK_SIZE,
+#if CONFIG_SMP_NCPUS > 1
+ (uintptr_t)g_intstackalloc + (2 * INTSTACK_SIZE),
+#endif /* CONFIG_SMP_NCPUS > 1 */
+};
+#endif /* defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp_cpuint_initialize
+ *
+ * Description:
+ * Initialize CPU interrupts.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp_cpuint_initialize(void)
+{
+ uintptr_t regaddr;
+ int i;
+#ifdef CONFIG_SMP
+ int cpu;
+#endif
+
+#ifdef CONFIG_SMP
+ /* Which CPU are we initializing */
+
+ cpu = this_cpu();
+ DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS);
+#endif
+
+ /* Initialize the Xtensa interrupt handler table first.
+ * This MUST be called before any interrupt can fire to ensure
+ * all handlers are properly initialized to the default handler.
+ */
+
+ esp_xtensa_intr_init();
+
+ /* Disable all CPU interrupts on this CPU */
+
+ xtensa_disable_all();
+}
+
+#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG
+
+/****************************************************************************
+ * Name: esp_iram_interrupt_record
+ *
+ * Description:
+ * This function keeps track of the IRQs that ran when non-IRAM interrupts
+ * are disabled and enables debugging of the IRAM-enabled interrupts.
+ *
+ * Input Parameters:
+ * irq - The IRQ associated with a CPU interrupt
+ * cpu - The CPU associated with the CPU interrupt
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+IRAM_ATTR static void esp_irq_iram_interrupt_record(int irq, int cpu)
+{
+ irqstate_t flags = enter_critical_section();
+
+ g_iram_count[cpu][irq]++;
+
+ leave_critical_section(flags);
+}
+#endif
+
+IRAM_ATTR static void isr_adapter_func(void *arg)
+{
+ struct intr_adapter_from_nuttx *isr_adapter_args;
+
+ isr_adapter_args = (struct intr_adapter_from_nuttx *)arg;
+
+ isr_adapter_args->func(isr_adapter_args->irq,
+ isr_adapter_args->context,
+ isr_adapter_args->arg);
+}
+
+/****************************************************************************
+ * Name: esp_cpuint_to_irq
+ *
+ * Description:
+ * Find an IRQ associated with a given CPU interrupt by searching through
+ * g_handle_map. For shared interrupts, multiple IRQs may map to the same
+ * CPU interrupt - this function returns the first one found.
+ *
+ * Input Parameters:
+ * cpuint - The CPU interrupt number
+ * cpu - The CPU core
+ *
+ * Returned Value:
+ * The IRQ number, or -1 if not found.
+ *
+ ****************************************************************************/
+
+IRAM_ATTR static int esp_cpuint_to_irq(int cpuint, int cpu)
+{
+ int irq;
+ intr_handle_t handle;
+
+ for (irq = 0; irq < NR_IRQS; irq++)
+ {
+ handle = g_handle_map[cpu][irq];
+ if (handle != IRQ_UNMAPPED && handle != NULL)
+ {
+ if (esp_intr_get_intno(handle) == cpuint &&
+ esp_intr_get_cpu(handle) == cpu)
+ {
+ return irq;
+ }
+ }
+ }
+
+ return -1;
+}
+
+/****************************************************************************
+ * Name: esp_isr_demultiplexing
+ *
+ * Description:
+ * Demultiplexing interrupt handler. All peripheral interrupts are
+ * dispatched through this single handler, which then calls the
+ * appropriate peripheral handler registered via esp_setup_irq.
+ *
+ * Input Parameters:
+ * irq - The IRQ number (XTENSA_IRQ_DEMUX)
+ * context - Saved processor state
+ * arg - Unused
+ *
+ * Returned Value:
+ * Always returns OK.
+ *
+ ****************************************************************************/
+
+IRAM_ATTR static int esp_isr_demultiplexing(int irq, void *context,
+ void *arg)
+{
+ int cpuint = esp_get_cpuint(this_cpu(), irq);
+ intr_handler_t handler;
+ struct intr_adapter_from_nuttx *handler_arg;
+
+ /* Validate cpuint - if invalid, the interrupt was not properly
+ * registered via esp_setup_irq. This is a bug that needs to be fixed.
+ */
+
+ if (cpuint < 0 || cpuint >= SOC_CPU_INTR_NUM)
+ {
+ irqwarn("IRQ %d has invalid cpuint=%d (not registered)", irq, cpuint);
+ return OK;
+ }
+
+ handler = (intr_handler_t)esp_cpu_intr_get_handler(cpuint);
+ handler_arg = (struct intr_adapter_from_nuttx *)
+ esp_cpu_intr_get_handler_arg(cpuint);
+
+ /* If the handler is the isr_adapter_func, then we need to set the irq
+ * and context to the handler_arg. This is true for all interrupts set via
+ * esp_setup_irq. Exceptions are the interrupts set directly by the
+ * underlying hardware, like Wi-Fi.
+ */
+
+ if (handler == &isr_adapter_func)
+ {
+ handler_arg->irq = irq;
+ handler_arg->context = context;
+ }
+
+ if (handler)
+ {
+ (*handler)(handler_arg);
+ }
+ else
+ {
+ /* Handler not found in _xt_interrupt_table.
+ * This happens when irq_attach was used instead of esp_setup_irq
+ * with a non-NULL handler. Peripheral handlers must be set via
+ * esp_setup_irq() when using ARCH_MINIMAL_VECTORTABLE.
+ */
+
+ irqwarn("No handler for irq=%d cpuint=%d\n", irq, cpuint);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: xtensa_attach_fromcpu1_interrupt
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+static inline void xtensa_attach_fromcpu1_interrupt(void)
+{
+ int cpuint;
+
+ /* Connect all CPU peripheral source to allocated CPU interrupt */
+
+ cpuint = esp_setup_irq(ESP_FROMCPU1_PERIPH, 1,
+ ESP_IRQ_TRIGGER_LEVEL,
+ esp_fromcpu1_interrupt, NULL);
+ DEBUGASSERT(cpuint >= 0);
+
+ /* Enable the inter-CPU interrupt. */
+
+ up_enable_irq(ESP_FROMCPU1_IRQ);
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irq_to_ndx
+ *
+ * Description:
+ * Irq to ndx
+ *
+ ****************************************************************************/
+
+IRAM_ATTR int up_irq_to_ndx(int irq)
+{
+ return irq == XTENSA_IRQ_SYSCALL ? ESP_IRQ_SYSCALL : ESP_IRQ_DEMUX;
+}
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ *
+ * Description:
+ * Complete initialization of the interrupt system and enable normal,
+ * interrupt processing.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+ int i;
+ int j;
+
+ /* Indicate that no interrupt sources are assigned to CPU interrupts */
+
+ for (i = 0; i < NR_IRQS; i++)
+ {
+ for (j = 0; j < CONFIG_SMP_NCPUS; j++)
+ {
+ g_handle_map[j][i] = IRQ_UNMAPPED;
+ }
+ }
+
+ /* Initialize CPU interrupts */
+
+ esp_cpuint_initialize();
+
+#ifdef CONFIG_SMP
+ /* Attach and enable the inter-CPU interrupt */
+
+ xtensa_attach_fromcpu1_interrupt();
+#endif
+
+ /* Initialize GPIO interrupt support */
+
+#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
+ esp_gpioirqinitialize();
+#endif
+
+ /* Initialize RTCIO interrupt support */
+
+ esp_rtcioirqinitialize();
+
+ /* Initialize interrupt handler for the PMS violation ISR */
+
+ esp_pmsirqinitialize();
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+ /* Attach the demultiplexing interrupt handler */
+
+ irq_attach(XTENSA_IRQ_DEMUX, esp_isr_demultiplexing, NULL);
+
+ /* Attach the software interrupt - must be done before enabling interrupts
+ * to avoid unexpected interrupt errors if a syscall happens early.
+ */
+
+ irq_attach(XTENSA_IRQ_SYSCALL, xtensa_swint, NULL);
+
+ /* And finally, enable interrupts. Also clears PS.EXCM */
+
+ xtensa_color_intstack();
+ up_irq_enable();
+#endif
+}
+
+/****************************************************************************
+ * Name: xtensa_int_decode
+ *
+ * Description:
+ * Determine the peripheral that generated the interrupt and dispatch
+ * handling to the registered interrupt handler via xtensa_irq_dispatch().
+ *
+ * Input Parameters:
+ * cpuints - Set of pending interrupts valid for this level
+ * regs - Saves processor state on the stack
+ *
+ * Returned Value:
+ * Normally the same value as regs is returned. But, in the event of an
+ * interrupt level context switch, the returned value will, instead point
+ * to the saved processor state in the TCB of the newly started task.
+ *
+ ****************************************************************************/
+
+IRAM_ATTR uint32_t *xtensa_int_decode(uint32_t *cpuints, uint32_t *regs)
+{
+ uint32_t mask;
+ int bit;
+ int cpu = this_cpu();
+
+#ifdef CONFIG_ARCH_LEDS_CPU_ACTIVITY
+ board_autoled_on(LED_CPU);
+#endif
+
+ /* Skip over zero bits, eight at a time */
+
+ for (bit = 0, mask = 0xff;
+ bit < ESP_NCPUINTS && (cpuints[0] & mask) == 0;
+ bit += 8, mask <<= 8);
+
+ /* Process each pending CPU interrupt */
+
+ for (; bit < ESP_NCPUINTS && cpuints[0] != 0; bit++)
+ {
+ mask = 1 << bit;
+ if ((cpuints[0] & mask) != 0)
+ {
+ /* Extract the IRQ number from the handle map.
+ * For shared interrupts, multiple IRQs may share the same CPU
+ * interrupt - we get the first one found. The actual dispatch
+ * happens through the handler in _xt_interrupt_table.
+ */
+
+ int irq = esp_cpuint_to_irq(bit, cpu);
+
+ if (irq < 0)
+ {
+ /* No handle found for this CPU interrupt. This can happen
+ * if the interrupt was triggered but not properly registered.
+ */
+
+ irqwarn("No IRQ found for cpuint=%d cpu=%d\n", bit, cpu);
+ xtensa_intclear(bit);
+ cpuints[0] &= ~mask;
+ continue;
+ }
+
+#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG
+ /* Check if non-IRAM interrupts are disabled */
+
+ if (esp_intr_noniram_is_disabled(cpu))
+ {
+ /* Sum-up the IRAM-enabled counter associated with the IRQ */
+
+ esp_irq_iram_interrupt_record(irq, cpu);
+ }
+#endif
+
+ /* Clear software or edge-triggered interrupt */
+
+ xtensa_intclear(bit);
+
+ /* Dispatch the CPU interrupt.
+ *
+ * NOTE that regs may be altered in the case of an interrupt
+ * level context switch.
+ */
+
+ regs = xtensa_irq_dispatch(irq, regs);
+
+ /* Clear the bit in the pending interrupt so that perhaps
+ * we can exit the look early.
+ */
+
+ cpuints[0] &= ~mask;
+ }
+ }
+
+ return regs;
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ * Enable the interrupt specified by 'irq'.
+ *
+ * Input Parameters:
+ * irq - IRQ number.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+ esp_err_t ret;
+ intr_handle_t intr_handle = esp_get_handle(this_cpu(), irq);
+
+ if (intr_handle == IRQ_UNMAPPED)
+ {
+ irqwarn("IRQ %d not mapped to handle\n", irq);
+ return;
+ }
+
+ ret = esp_intr_enable(intr_handle);
+ if (ret != ESP_OK)
+ {
+ irqerr("Failed to enable interrupt %d\n", irq);
+ }
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ * Disable the interrupt specified by 'irq'.
+ *
+ * Input Parameters:
+ * irq - IRQ number.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+ esp_err_t ret;
+ intr_handle_t intr_handle;
+
+ if (irq < XTENSA_IRQ_FIRSTPERIPH)
+ {
+ /* Internal interrupt - these are handled differently */
+
+ return;
+ }
+
+ intr_handle = esp_get_handle(this_cpu(), irq);
+ if (intr_handle == IRQ_UNMAPPED)
+ {
+ return;
+ }
+
+ ret = esp_intr_disable(intr_handle);
+ if (ret != ESP_OK)
+ {
+ irqerr("Failed to disable interrupt %d\n", irq);
+ }
+}
+
+/****************************************************************************
+ * Name: esp_setup_irq
+ *
+ * Description:
+ * Configure an IRQ. It allocates a CPU interrupt of the given
+ * priority and type and attaches a given interrupt source to it.
+ *
+ * Input Parameters:
+ * source - Interrupt source (see irq.h) to be assigned to
+ * a CPU interrupt.
+ * priority - Interrupt priority.
+ * type - Interrupt trigger type.
+ * handler - Interrupt handler.
+ * arg - Interrupt handler argument.
+ *
+ * Returned Value:
+ * Allocated CPU interrupt or a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int esp_setup_irq(int source,
+ irq_priority_t priority,
+ int type,
+ xcpt_t handler,
+ void *arg)
+{
+ return esp_setup_irq_intrstatus(source, priority, type, 0, 0,
+ handler, arg);
+}
+
+int esp_setup_irq_with_flags(int source,
+ int flags,
+ xcpt_t handler,
+ void *arg)
+{
+ return esp_setup_irq_with_flags_intrstatus(source, flags, 0, 0,
+ handler, arg);
+}
+
+int esp_setup_irq_intrstatus(int source,
+ irq_priority_t priority,
+ int type,
+ uint32_t intrstatusreg,
+ uint32_t intrstatusmask,
+ xcpt_t handler,
+ void *arg)
+{
+ int flags;
+
+ flags = (1 << priority);
+ flags |= type == ESP_IRQ_TRIGGER_EDGE ? ESP_INTR_FLAG_EDGE : 0;
+ flags |= ESP_INTR_FLAG_INTRDISABLED;
+
+ return esp_setup_irq_with_flags_intrstatus(source,
+ flags,
+ intrstatusreg,
+ intrstatusmask,
+ handler,
+ arg);
+}
+
+int esp_setup_irq_with_flags_intrstatus(int source,
+ int flags,
+ uint32_t intrstatusreg,
+ uint32_t intrstatusmask,
+ xcpt_t handler,
+ void *arg)
+{
+ struct intr_adapter_from_nuttx *isr_adapter_args;
+ esp_err_t ret;
+ intr_handle_t ret_handle;
+ int cpuint;
+ int irq;
+
+ irqinfo("source = %d\n", source);
+
+ isr_adapter_args = kmm_calloc(1, sizeof(struct intr_adapter_from_nuttx));
+ if (isr_adapter_args == NULL)
+ {
+ irqerr("Failed to kmm_calloc\n");
+ return -EINVAL;
+ }
+
+ isr_adapter_args->func = handler;
+ isr_adapter_args->arg = arg;
+
+ ret = esp_intr_alloc_intrstatus(source,
+ flags,
+ intrstatusreg,
+ intrstatusmask,
+ isr_adapter_func,
+ isr_adapter_args,
+ &ret_handle);
+ if (ret != ESP_OK)
+ {
+ irqerr("Failed to allocate interrupt for source %d\n", source);
+ kmm_free(isr_adapter_args);
+ return -EINVAL;
+ }
+
+ cpuint = esp_intr_get_intno(ret_handle);
+
+ if (source < 0)
+ {
+ irq = source + ETS_INTERNAL_INTR_SOURCE_OFF;
+ }
+ else
+ {
+ irq = ESP_SOURCE2IRQ(source);
+ }
+
+ /* Store the handle. The handle already contains the CPU interrupt and
+ * CPU information, so no additional mapping is needed.
+ */
+
+ esp_set_handle(this_cpu(), irq, ret_handle);
+
+ return cpuint;
+}
+
+/****************************************************************************
+ * Name: esp_teardown_irq
+ *
+ * Description:
+ * This function undoes the operations done by esp_setup_irq.
+ * It detaches an interrupt source from a CPU interrupt and frees the
+ * CPU interrupt.
+ *
+ * Input Parameters:
+ * source - Interrupt source (see irq.h) to be detached from the
+ * CPU interrupt.
+ * cpuint - CPU interrupt from which the interrupt source will
+ * be detached.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp_teardown_irq(int source, int cpuint)
+{
+ esp_err_t ret;
+ int cpu = this_cpu();
+ int irq = ESP_SOURCE2IRQ(source);
+ intr_handle_t intr_handle = esp_get_handle(cpu, irq);
+
+ UNUSED(cpuint);
+
+ if (intr_handle == IRQ_UNMAPPED)
+ {
+ irqwarn("No handle found for source %d\n", source);
+ return;
+ }
+
+ ret = esp_intr_free(intr_handle);
+ if (ret != ESP_OK)
+ {
+ irqerr("Failed to free interrupt %d\n", source);
+ }
+
+ esp_clear_handle(cpu, irq);
+}
+
+/****************************************************************************
+ * Name: esp_set_handle
+ *
+ * Description:
+ * This function sets the handle associated with an IRQ
+ *
+ * Input Parameters:
+ * cpu - The CPU associated with the IRQ
+ * irq - The IRQ associated with a CPU interrupt
+ * handle - The handle to be associated with the IRQ
+ *
+ * Returned Value:
+ * OK on success; A negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int esp_set_handle(int cpu, int irq, intr_handle_t handle)
+{
+ intr_handle_t current_handle = g_handle_map[cpu][irq];
+
+ if (current_handle != IRQ_UNMAPPED)
+ {
+ irqinfo("IRQ %d already has a handle\n", irq);
+ return -EINVAL;
+ }
+
+ g_handle_map[cpu][irq] = handle;
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp_get_handle
+ *
+ * Description:
+ * This function gets the handle associated with an IRQ
+ *
+ * Input Parameters:
+ * cpu - The CPU associated with the IRQ
+ * irq - The IRQ associated with a CPU interrupt
+ *
+ * Returned Value:
+ * The handle associated with the IRQ or IRQ_UNMAPPED if no handle is
+ * associated with the IRQ.
+ *
+ ****************************************************************************/
+
+intr_handle_t esp_get_handle(int cpu, int irq)
+{
+ return g_handle_map[cpu][irq];
+}
+
+/****************************************************************************
+ * Name: esp_clear_handle
+ *
+ * Description:
+ * This function clears the handle associated with an IRQ
+ *
+ * Input Parameters:
+ * irq - The IRQ associated with a CPU interrupt
+ *
+ * Returned Value:
+ * The handle associated with the IRQ or IRQ_UNMAPPED if no handle is
+ * associated with the IRQ.
+ *
+ ****************************************************************************/
+
+static void esp_clear_handle(int cpu, int irq)
+{
+ g_handle_map[cpu][irq] = IRQ_UNMAPPED;
+}
+
+/****************************************************************************
+ * Name: esp_get_cpuint
+ *
+ * Description:
+ * This function returns the CPU interrupt associated with an IRQ
+ *
+ * Input Parameters:
+ * cpu - The CPU associated with the IRQ
+ * irq - The IRQ associated with a CPU interrupt
+ *
+ * Returned Value:
+ * The CPU interrupt associated with such IRQ or a negated errno value on
+ * failure.
+ *
+ ****************************************************************************/
+
+IRAM_ATTR int esp_get_cpuint(int cpu, int irq)
+{
+ intr_handle_t intr_handle = esp_get_handle(cpu, irq);
+
+ if (intr_handle != IRQ_UNMAPPED && intr_handle != NULL)
+ {
+ return esp_intr_get_intno(intr_handle);
+ }
+
+ return -EINVAL;
+}
+
+/****************************************************************************
+ * Name: up_get_intstackbase
+ *
+ * Description:
+ * Return a pointer to the "alloc" the correct interrupt stack allocation
+ * for the current CPU.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
+uintptr_t up_get_intstackbase(int cpu)
+{
+ return g_cpu_intstack_top[cpu] - INTSTACK_SIZE;
+}
+#endif
+
+/****************************************************************************
+ * Name: esp_get_iram_interrupt_records
+ *
+ * Description:
+ * This function copies the vector that keeps track of the IRQs that ran
+ * when non-IRAM interrupts were disabled.
+ *
+ * Input Parameters:
+ *
+ * irq_count - A previously allocated pointer to store the counter of the
+ * interrupts that ran when non-IRAM interrupts were disabled.
+ * cpu - The CPU to retrieve the interrupt records for
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG
+void esp_get_iram_interrupt_records(uint64_t *irq_count, int cpu)
+{
+ irqstate_t flags = enter_critical_section();
+
+ memcpy(irq_count, &g_iram_count[cpu], sizeof(uint64_t) * NR_IRQS);
+
+ leave_critical_section(flags);
+}
+#endif
diff --git a/arch/xtensa/src/common/espressif/esp_irq.h b/arch/xtensa/src/common/espressif/esp_irq.h
new file mode 100644
index 00000000000..5197d68d73b
--- /dev/null
+++ b/arch/xtensa/src/common/espressif/esp_irq.h
@@ -0,0 +1,296 @@
+/****************************************************************************
+ * arch/xtensa/src/common/espressif/esp_irq.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_IRQ_H
+#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include "esp_intr_types.h"
+#include "esp_intr_alloc.h"
+#include "soc/interrupts.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define IRQ_UNMAPPED (intr_handle_t)NULL
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* CPU interrupt flags.
+ * esp_setup_irq() will check bit 1 for IRAM requirement and
+ * bit 0 for trigger type.
+ *
+ * OR'ed values of irq_trigger_e and irq_iram_e define interrupt type.
+ * | IRAM | TRIGGER |
+ * Bits | 1 | 0 |
+ */
+
+/* CPU interrupt trigger types */
+
+typedef enum irq_trigger_e
+{
+ ESP_IRQ_TRIGGER_LEVEL = 0, /* Level-triggered interrupts */
+ ESP_IRQ_TRIGGER_EDGE = 1, /* Edge-triggered interrupts */
+} irq_trigger_t;
+
+/* CPU interrupt IRAM enabled */
+
+typedef enum irq_iram_e
+{
+ ESP_IRQ_NON_IRAM = (0 << 1), /* Non-IRAM interrupt */
+ ESP_IRQ_IRAM = (1 << 1), /* IRAM interrupt */
+} irq_iram_t;
+
+/* CPU interrupt priority levels */
+
+typedef enum irq_priority_e
+{
+ ESP_IRQ_PRIORITY_1 = 1, /* Priority Level 1 */
+ ESP_IRQ_PRIORITY_2 = 2, /* Priority Level 2 */
+ ESP_IRQ_PRIORITY_3 = 3, /* Priority Level 3 */
+ ESP_IRQ_PRIORITY_4 = 4, /* Priority Level 4 */
+ ESP_IRQ_PRIORITY_5 = 5, /* Priority Level 5 */
+ ESP_IRQ_PRIORITY_DEFAULT = ESP_IRQ_PRIORITY_1 /* Default Priority */
+} irq_priority_t;
+
+/* Adapter from NuttX to Espressif's interrupt handler */
+
+struct intr_adapter_from_nuttx
+{
+ int (*func)(int irq, void *context, void *arg); /* Interrupt callback function */
+ int irq; /* Interrupt number */
+ void *context; /* Interrupt context */
+ void *arg; /* Interrupt private data */
+};
+
+struct intr_adapter_to_nuttx
+{
+ void (*handler)(void *arg); /* Interrupt handler */
+ void *arg; /* Interrupt handler argument */
+};
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp_setup_irq
+ *
+ * Description:
+ * This function sets up the IRQ. It allocates a CPU interrupt of the given
+ * priority and type and attaches it to a given interrupt source.
+ *
+ * Input Parameters:
+ * source - The interrupt source from irq.h to be assigned to
+ * a CPU interrupt.
+ * priority - Interrupt priority.
+ * type - Interrupt trigger type.
+ * handler - Interrupt handler.
+ * arg - Interrupt handler argument.
+ *
+ * Returned Value:
+ * Allocated CPU interrupt on success, or a negated errno on failure.
+ *
+ ****************************************************************************/
+
+int esp_setup_irq(int source,
+ irq_priority_t priority,
+ int type,
+ xcpt_t handler,
+ void *arg);
+
+int esp_setup_irq_with_flags(int source,
+ int flags,
+ xcpt_t handler,
+ void *arg);
+
+int esp_setup_irq_intrstatus(int source,
+ irq_priority_t priority,
+ int type,
+ uint32_t intrstatusreg,
+ uint32_t intrstatusmask,
+ xcpt_t handler,
+ void *arg);
+
+int esp_setup_irq_with_flags_intrstatus(int source,
+ int flags,
+ uint32_t intrstatusreg,
+ uint32_t intrstatusmask,
+ xcpt_t handler,
+ void *arg);
+
+/****************************************************************************
+ * Name: esp_teardown_irq
+ *
+ * Description:
+ * This function undoes the operations done by esp_setup_irq.
+ * It detaches an interrupt source from a CPU interrupt and frees the
+ * CPU interrupt.
+ *
+ * Input Parameters:
+ * source - The interrupt source from irq.h to be detached from the
+ * CPU interrupt.
+ * cpuint - The CPU interrupt from which the interrupt source will
+ * be detached.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp_teardown_irq(int source, int cpuint);
+
+/****************************************************************************
+ * Name: esp_get_cpuint
+ *
+ * Description:
+ * This function returns the CPU interrupt associated with an IRQ
+ *
+ * Input Parameters:
+ * cpu - The CPU associated with the IRQ
+ * irq - The IRQ associated with a CPU interrupt
+ *
+ * Returned Value:
+ * The CPU interrupt associated with such IRQ or a negated errno value on
+ * failure.
+ *
+ ****************************************************************************/
+
+int esp_get_cpuint(int cpu, int irq);
+
+/****************************************************************************
+ * Name: esp_set_handle
+ *
+ * Description:
+ * This function sets the handle associated with an IRQ
+ *
+ * Input Parameters:
+ * cpu - The CPU associated with the IRQ
+ * irq - The IRQ associated with a CPU interrupt
+ * handle - The handle to be associated with the IRQ
+ *
+ * Returned Value:
+ * OK on success; A negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int esp_set_handle(int cpu, int irq, intr_handle_t handle);
+
+/****************************************************************************
+ * Name: esp_get_handle
+ *
+ * Description:
+ * This function gets the handle associated with an IRQ
+ *
+ * Input Parameters:
+ * cpu - The CPU associated with the IRQ
+ * irq - The IRQ associated with a CPU interrupt
+ *
+ * Returned Value:
+ * The handle associated with the IRQ or IRQ_UNMAPPED if no handle is
+ * associated with the IRQ.
+ *
+ ****************************************************************************/
+
+intr_handle_t esp_get_handle(int cpu, int irq);
+
+/****************************************************************************
+ * Name: esp_cpuint_initialize
+ *
+ * Description:
+ * Initialize CPU interrupts.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; A negated errno value is returned on
+ * any failure.
+ *
+ ****************************************************************************/
+
+void esp_cpuint_initialize(void);
+
+/****************************************************************************
+ * Name: esp_get_iram_interrupt_records
+ *
+ * Description:
+ * This function copies the vector that keeps track of the IRQs that ran
+ * when non-IRAM interrupts were disabled.
+ *
+ * Input Parameters:
+ *
+ * irq_count - A previously allocated pointer to store the counter of the
+ * interrupts that ran when non-IRAM interrupts were disabled.
+ * cpu - The CPU to retrieve the interrupt records for
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG
+void esp_get_iram_interrupt_records(uint64_t *irq_count, int cpu);
+#endif
+
+/****************************************************************************
+ * Name: esp_dump_cpuint_map
+ *
+ * Description:
+ * Dump the contents of g_handle_map for debugging purposes.
+ * This function is useful when debugging unexpected interrupt handlers.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp_dump_cpuint_map(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_IRQ_H */
diff --git a/arch/xtensa/src/common/espressif/esp_ledc.c b/arch/xtensa/src/common/espressif/esp_ledc.c
index 172d89936f6..fca32117c9c 100644
--- a/arch/xtensa/src/common/espressif/esp_ledc.c
+++ b/arch/xtensa/src/common/espressif/esp_ledc.c
@@ -37,15 +37,15 @@
#include "esp_ledc.h"
#include "xtensa.h"
-#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#include "esp32s3_gpio.h"
-#include "hardware/esp32s3_gpio_sigmap.h"
+#if defined(CONFIG_ARCH_CHIP_ESP32)
+# include "esp_gpio.h"
+# include "hardware/esp32_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#include "esp32s2_gpio.h"
-#include "hardware/esp32s2_gpio_sigmap.h"
-#else
-#include "esp32_gpio.h"
-#include "hardware/esp32_gpio_sigmap.h"
+# include "espressif/esp_gpio.h"
+# include "hardware/esp32s2_gpio_sigmap.h"
+#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
+# include "esp_gpio.h"
+# include "hardware/esp32s3_gpio_sigmap.h"
#endif
#include "esp_private/periph_ctrl.h"
@@ -61,8 +61,6 @@
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-# define esp_configgpio esp32s3_configgpio
-# define esp_gpio_matrix_out esp32s3_gpio_matrix_out
# ifdef CONFIG_ESP32S3_LEDC
# define CONFIG_ESPRESSIF_LEDC_CHANNEL0_PIN CONFIG_ESP32S3_LEDC_CHANNEL0_PIN
# define CONFIG_ESPRESSIF_LEDC_CHANNEL1_PIN CONFIG_ESP32S3_LEDC_CHANNEL1_PIN
@@ -94,8 +92,6 @@
# endif /* CONFIG_ESP32S3_LEDC_TIM3 */
# endif /* CONFIG_ESP32S3_LEDC */
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-# define esp_configgpio esp32s2_configgpio
-# define esp_gpio_matrix_out esp32s2_gpio_matrix_out
# ifdef CONFIG_ESP32S2_LEDC
# define CONFIG_ESPRESSIF_LEDC_CHANNEL0_PIN CONFIG_ESP32S2_LEDC_CHANNEL0_PIN
# define CONFIG_ESPRESSIF_LEDC_CHANNEL1_PIN CONFIG_ESP32S2_LEDC_CHANNEL1_PIN
@@ -540,7 +536,6 @@ static bool ledc_ctx_create(void)
ledc_hal_init(&(ledc_new_mode_obj->ledc_hal), LEDC_LOW_SPEED_MODE);
ledc_new_mode_obj->glb_clk = LEDC_SLOW_CLK_UNINIT;
p_ledc_obj = ledc_new_mode_obj;
- periph_module_enable(PERIPH_LEDC_MODULE);
}
}
@@ -1235,7 +1230,7 @@ static int ledc_channel_output_enable(ledc_channel_t channel)
}
ledc_hal_set_sig_out_en(&(p_ledc_obj->ledc_hal), channel, true);
- ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel, true);
+ ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel);
return OK;
}
@@ -1270,7 +1265,7 @@ static int ledc_channel_output_disable(ledc_channel_t channel)
ledc_hal_set_idle_level(&(p_ledc_obj->ledc_hal), channel, 0);
ledc_hal_set_sig_out_en(&(p_ledc_obj->ledc_hal), channel, false);
- ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel, false);
+ ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel);
leave_critical_section(flags);
return OK;
@@ -1532,10 +1527,19 @@ static int pwm_shutdown(struct pwm_lowerhalf_s *dev)
if (p_ledc_obj != NULL)
{
- periph_module_disable(PERIPH_LEDC_MODULE);
kmm_free(p_ledc_obj);
p_ledc_obj = NULL;
s_ledc_slow_clk_rc_fast_freq = 0;
+ LEDC_BUS_CLOCK_ATOMIC()
+ {
+ ledc_ll_enable_bus_clock(false);
+ ledc_ll_enable_reset_reg(true);
+ }
+
+ LEDC_FUNC_CLOCK_ATOMIC()
+ {
+ ledc_ll_enable_clock(LEDC_LL_GET_HW(), false);
+ }
}
else
{
diff --git a/arch/xtensa/src/common/espressif/esp_loader.c b/arch/xtensa/src/common/espressif/esp_loader.c
index 62223322502..f35720f36d9 100644
--- a/arch/xtensa/src/common/espressif/esp_loader.c
+++ b/arch/xtensa/src/common/espressif/esp_loader.c
@@ -47,7 +47,7 @@
# include "bootloader_flash_priv.h"
#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
# include "bootloader_init.h"
-# include "esp_rom_uart.h"
+# include "esp_rom_serial_output.h"
# include "esp_rom_sys.h"
# include "esp_app_format.h"
#endif
diff --git a/arch/xtensa/src/common/espressif/esp_mcpwm.c b/arch/xtensa/src/common/espressif/esp_mcpwm.c
index 1f1995fcc77..01857285946 100644
--- a/arch/xtensa/src/common/espressif/esp_mcpwm.c
+++ b/arch/xtensa/src/common/espressif/esp_mcpwm.c
@@ -46,21 +46,22 @@
#include "xtensa.h"
#ifdef CONFIG_ARCH_CHIP_ESP32
#include "hardware/esp32_soc.h"
-#include "esp32_gpio.h"
-#include "esp32_irq.h"
+#include "esp_gpio.h"
+#include "esp_irq.h"
#elif CONFIG_ARCH_CHIP_ESP32S3
#include "hardware/esp32s3_soc.h"
-#include "esp32s3_gpio.h"
-#include "esp32s3_irq.h"
+#include "esp_gpio.h"
+#include "esp_irq.h"
#endif
#include "hal/mcpwm_hal.h"
#include "hal/mcpwm_ll.h"
#include "hal/mcpwm_types.h"
-#include "soc/mcpwm_periph.h"
+#include "hal/mcpwm_periph.h"
#include "periph_ctrl.h"
#include "esp_clk_tree.h"
-#include "hal/clk_tree_hal.h"
+#include "esp_private/esp_clk_tree_common.h"
+#include "soc/clk_tree_defs.h"
#ifdef CONFIG_ESP_MCPWM
@@ -68,22 +69,10 @@
* Pre-processor Definitions
****************************************************************************/
+#define MCPWM_DEV_CLK_PRESCALE 1
+
#define MCPWM_CAPTURE_DEFAULT_GROUP 0
-#ifdef CONFIG_ARCH_CHIP_ESP32
-# define esp_configgpio esp32_configgpio
-# define esp_gpio_matrix_in esp32_gpio_matrix_in
-# define esp_gpio_matrix_out esp32_gpio_matrix_out
-# define esp_setup_irq esp32_setup_irq
-# define esp_teardown_irq esp32_teardown_irq
-# define ESP_CPUINT_LEVEL ESP32_CPUINT_LEVEL
-#elif CONFIG_ARCH_CHIP_ESP32S3
-# define esp_configgpio esp32s3_configgpio
-# define esp_gpio_matrix_in esp32s3_gpio_matrix_in
-# define esp_gpio_matrix_out esp32s3_gpio_matrix_out
-# define esp_setup_irq esp32s3_setup_irq
-# define esp_teardown_irq esp32s3_teardown_irq
-# define ESP_CPUINT_LEVEL ESP32S3_CPUINT_LEVEL
-#endif
+
#ifdef CONFIG_ESP_MCPWM_MOTOR_BDC
/* Peak counter at 13330 in up-down mode allows frequencies at a prescale
* of: 2 kHz @ 2; 1.5 kHz @ 3; 1.2 kHz @ 4; 1 kHz @ 5.
@@ -154,6 +143,7 @@ struct mcpwm_dev_common_s
spinlock_t mcpwm_spinlock;
bool initialized; /* MCPWM periph. and HAL has been initialized */
bool isr_initialized; /* Shared ISR has been initialized */
+ int group_prescale;
};
#ifdef CONFIG_ESP_MCPWM_MOTOR
@@ -233,7 +223,7 @@ static void esp_mcpwm_group_start(void);
static int esp_mcpwm_capture_set_gpio(
struct mcpwm_cap_channel_lowerhalf_s *lower);
-/* Upper-half functions required by capture driver */
+/* Lower half methods required by capture driver */
static int esp_capture_start(struct cap_lowerhalf_s *lower);
static int esp_capture_stop(struct cap_lowerhalf_s *lower);
@@ -309,6 +299,7 @@ static struct mcpwm_dev_common_s g_mcpwm_common =
.group.group_id = 0,
.initialized = false,
.isr_initialized = false,
+ .group_prescale = MCPWM_DEV_CLK_PRESCALE,
};
/* Motor specific data structures */
@@ -419,8 +410,31 @@ static struct mcpwm_cap_channel_lowerhalf_s mcpwm_cap_ch2_lowerhalf =
static void esp_mcpwm_group_start(void)
{
- periph_module_enable(PERIPH_PWM0_MODULE);
- mcpwm_hal_init(&g_mcpwm_common.hal, &g_mcpwm_common.group);
+ mcpwm_hal_context_t *hal = &g_mcpwm_common.hal;
+
+ /* HAL and MCPWM Initialization */
+
+ PERIPH_RCC_ATOMIC()
+ {
+ mcpwm_ll_enable_bus_clock(g_mcpwm_common.group.group_id, true);
+ mcpwm_ll_reset_register(g_mcpwm_common.group.group_id);
+ mcpwm_ll_group_enable_clock(g_mcpwm_common.group.group_id, true);
+ }
+
+ mcpwm_hal_init(hal, &g_mcpwm_common.group);
+
+ esp_clk_tree_enable_src(
+ (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT, true);
+
+ PERIPH_RCC_ATOMIC()
+ {
+ mcpwm_ll_group_set_clock_source(g_mcpwm_common.group.group_id,
+ MCPWM_CAPTURE_CLK_SRC_DEFAULT);
+
+ mcpwm_ll_group_set_clock_prescale(g_mcpwm_common.group.group_id,
+ g_mcpwm_common.group_prescale);
+ }
+
g_mcpwm_common.initialized = true;
}
@@ -465,7 +479,7 @@ static int esp_motor_setup(struct motor_lowerhalf_s *dev)
mtrinfo("State: %d\n", priv->state.state);
- esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_PLL_F160M,
+ esp_clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
&base_clock);
@@ -1320,7 +1334,7 @@ static int esp_mcpwm_fault_gpio_config(struct mcpwm_motor_lowerhalf_s *lower,
if (!enable)
{
esp_gpio_matrix_in(0x3a,
- mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\
+ soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
gpio_faults[lower->fault_id].fault_sig,
false);
return OK;
@@ -1335,7 +1349,7 @@ static int esp_mcpwm_fault_gpio_config(struct mcpwm_motor_lowerhalf_s *lower,
esp_gpio_matrix_in(
lower->fault_pin,
- mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\
+ soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
gpio_faults[lower->fault_id].fault_sig,
false);
@@ -1397,13 +1411,13 @@ static int esp_mcpwm_motor_set_gpio(struct mcpwm_motor_lowerhalf_s *lower,
esp_gpio_matrix_out(
lower->generator_pins[MCPWM_GENERATOR_0],
- mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\
+ soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
operators[lower->channel_id].generators[MCPWM_GENERATOR_0].pwm_sig,
false, false);
esp_gpio_matrix_out(
lower->generator_pins[MCPWM_GENERATOR_1],
- mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\
+ soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
operators[lower->channel_id].generators[MCPWM_GENERATOR_1].pwm_sig,
false, false);
@@ -1411,14 +1425,12 @@ static int esp_mcpwm_motor_set_gpio(struct mcpwm_motor_lowerhalf_s *lower,
#ifdef CONFIG_ESP_MCPWM_TEST_LOOPBACK
esp_gpio_matrix_out(CONFIG_ESP_MCPWM_CAPTURE_CH0_GPIO,
- mcpwm_periph_signals.\
- groups[MCPWM_CAPTURE_DEFAULT_GROUP].\
+ soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
operators[lower->channel_id].\
generators[MCPWM_GENERATOR_0].pwm_sig,
0, 0);
esp_gpio_matrix_out(CONFIG_ESP_MCPWM_CAPTURE_CH1_GPIO,
- mcpwm_periph_signals.\
- groups[MCPWM_CAPTURE_DEFAULT_GROUP].\
+ soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
operators[lower->channel_id].\
generators[MCPWM_GENERATOR_1].pwm_sig,
0, 0);
@@ -1554,6 +1566,9 @@ static int esp_capture_getduty(struct cap_lowerhalf_s *lower,
{
struct mcpwm_cap_channel_lowerhalf_s *priv = (
struct mcpwm_cap_channel_lowerhalf_s *)lower;
+
+ DEBUGASSERT(priv != NULL);
+
*duty = priv->duty;
cpinfo("Get duty called from channel %d\n", priv->channel_id);
return OK;
@@ -1582,6 +1597,9 @@ static int esp_capture_getfreq(struct cap_lowerhalf_s *lower,
{
struct mcpwm_cap_channel_lowerhalf_s *priv = (
struct mcpwm_cap_channel_lowerhalf_s *)lower;
+
+ DEBUGASSERT(priv != NULL);
+
*freq = priv->freq;
cpinfo("Get freq called from channel %d\n", priv->channel_id);
return OK;
@@ -1641,7 +1659,7 @@ static int esp_mcpwm_capture_set_gpio(
mcpwm_hal_context_t *hal = &lower->common->hal;
int ret;
- ret = esp_configgpio(lower->gpio_pin, INPUT_FUNCTION | INPUT_PULLUP);
+ ret = esp_configgpio(lower->gpio_pin, INPUT | PULLUP);
if (ret < 0)
{
cperr("Failed configuring GPIO pin\n");
@@ -1650,7 +1668,7 @@ static int esp_mcpwm_capture_set_gpio(
esp_gpio_matrix_in(
lower->gpio_pin,
- mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\
+ soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
captures[lower->channel_id].cap_sig,
false);
@@ -1681,26 +1699,22 @@ static int esp_mcpwm_isr_register(int (*fn)(int, void *, void *), void *arg)
{
int cpuint;
int ret;
- int cpu = this_cpu();
DEBUGASSERT(fn);
- cpuint = esp_setup_irq(cpu, mcpwm_periph_signals.groups[0].irq_id,
- 1, ESP_CPUINT_LEVEL);
+ cpuint = esp_setup_irq(soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
+ irq_id,
+ 1, ESP_IRQ_TRIGGER_LEVEL,
+ fn,
+ arg);
if (cpuint < 0)
{
cperr("Failed to allocate a CPU interrupt.\n");
return -ENOMEM;
}
- ret = irq_attach(mcpwm_periph_signals.groups[0].irq_id +
- XTENSA_IRQ_FIRSTPERIPH, fn, arg);
- if (ret < 0)
- {
- cperr("Couldn't attach IRQ to handler.\n");
- esp_teardown_irq(cpu, mcpwm_periph_signals.groups[0].irq_id, cpuint);
- return ret;
- }
+ up_enable_irq(ESP_SOURCE2IRQ(
+ soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].irq_id));
return ret;
}
@@ -1989,6 +2003,7 @@ struct motor_lowerhalf_s *esp_motor_bdc_initialize(int channel,
struct cap_lowerhalf_s *esp_mcpwm_capture_initialize(int channel, int pin)
{
struct mcpwm_cap_channel_lowerhalf_s *lower = NULL;
+ uint32_t group_clock;
if (!g_mcpwm_common.initialized)
{
@@ -1997,8 +2012,7 @@ struct cap_lowerhalf_s *esp_mcpwm_capture_initialize(int channel, int pin)
if (!g_mcpwm_common.isr_initialized)
{
- esp_mcpwm_isr_register(mcpwm_driver_isr_default,
- &g_mcpwm_common);
+ esp_mcpwm_isr_register(mcpwm_driver_isr_default, &g_mcpwm_common);
g_mcpwm_common.isr_initialized = true;
}
@@ -2024,8 +2038,17 @@ struct cap_lowerhalf_s *esp_mcpwm_capture_initialize(int channel, int pin)
return NULL;
}
- lower->clock = clk_hal_apb_get_freq_hz();
+ esp_clk_tree_src_get_freq_hz(MCPWM_CAPTURE_CLK_SRC_DEFAULT,
+ ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
+ &group_clock);
+
+ /* Set the clock to be used when calculating frequency */
+
lower->gpio_pin = pin;
+ lower->clock = group_clock / g_mcpwm_common.group_prescale;
+
+ /* Configure GPIO pin */
+
esp_mcpwm_capture_set_gpio(lower);
return (struct cap_lowerhalf_s *) lower;
diff --git a/arch/xtensa/src/common/espressif/esp_openeth.c b/arch/xtensa/src/common/espressif/esp_openeth.c
index 130a458f434..35019588b8e 100644
--- a/arch/xtensa/src/common/espressif/esp_openeth.c
+++ b/arch/xtensa/src/common/espressif/esp_openeth.c
@@ -514,8 +514,9 @@ int esp_openeth_initialize(void)
/* Setup interrupts */
- priv->cpuint = OPENETH_SETUP_IRQ(0, OPENETH_PERIPH_MAC,
- 1, OPENETH_CPUINT_LEVEL);
+ priv->cpuint = OPENETH_SETUP_IRQ(OPENETH_PERIPH_MAC,
+ 1, OPENETH_CPUINT_LEVEL,
+ openeth_isr_handler, priv);
if (priv->cpuint < 0)
{
nerr("ERROR: Failed allocate interrupt\n");
@@ -531,10 +532,6 @@ int esp_openeth_initialize(void)
"\x00\x02\x03\x04\x05\x06\x07\x08", ETH_ALEN);
openeth_set_addr(priv->dev.netdev.d_mac.ether.ether_addr_octet);
- /* Attach the interrupt */
-
- ret = irq_attach(OPENETH_IRQ_MAC, openeth_isr_handler, priv);
-
/* Register the device with the OS so that socket IOCTLs can be
* performed.
*/
diff --git a/arch/xtensa/src/common/espressif/esp_pcnt.c b/arch/xtensa/src/common/espressif/esp_pcnt.c
index 2a8d42e7620..1f594738ade 100644
--- a/arch/xtensa/src/common/espressif/esp_pcnt.c
+++ b/arch/xtensa/src/common/espressif/esp_pcnt.c
@@ -47,20 +47,20 @@
#include "esp_pcnt.h"
#include "chip.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#include "esp32s3_irq.h"
-#include "esp32s3_gpio.h"
+#include "esp_irq.h"
+#include "esp_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#include "esp32s2_irq.h"
-#include "esp32s2_gpio.h"
+#include "espressif/esp_irq.h"
+#include "espressif/esp_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32)
-#include "esp32_irq.h"
-#include "esp32_gpio.h"
+#include "esp_irq.h"
+#include "esp_gpio.h"
#endif
#include "hal/pcnt_hal.h"
#include "hal/pcnt_ll.h"
#include "periph_ctrl.h"
-#include "soc/pcnt_periph.h"
+#include "hal/pcnt_periph.h"
#include "soc/pcnt_reg.h"
#include "soc/pcnt_struct.h"
#include "soc/gpio_pins.h"
@@ -70,32 +70,23 @@
* Pre-processor Definitions
****************************************************************************/
-#define PCNT_UNIT_COUNT SOC_PCNT_GROUPS * SOC_PCNT_UNITS_PER_GROUP
-#define GET_UNIT_ID_FROM_RET_CHAN(chan_id) (int)(chan_id/SOC_PCNT_CHANNELS_PER_UNIT)
-#define GET_CHAN_ID_FROM_RET_CHAN(unit_id, chan_id) (chan_id - (SOC_PCNT_CHANNELS_PER_UNIT * unit_id))
-#define CREATE_RET_CHAN_ID(unit_id, chan_id) ((SOC_PCNT_CHANNELS_PER_UNIT * unit_id) + chan_id)
+#define PCNT_UNIT_COUNT PCNT_LL_GET(INST_NUM) * PCNT_LL_GET(UNITS_PER_INST)
+#define GET_UNIT_ID_FROM_RET_CHAN(chan_id) (int)(chan_id / PCNT_LL_GET(CHANS_PER_UNIT))
+#define GET_CHAN_ID_FROM_RET_CHAN(unit_id, chan_id) (chan_id - (PCNT_LL_GET(CHANS_PER_UNIT) * unit_id))
+#define CREATE_RET_CHAN_ID(unit_id, chan_id) ((PCNT_LL_GET(CHANS_PER_UNIT) * unit_id) + chan_id)
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#define esp_setup_irq esp32s3_setup_irq
-#define esp_teardown_irq esp32s3_teardown_irq
-#define esp_configgpio esp32s3_configgpio
-#define esp_gpio_matrix_in esp32s3_gpio_matrix_in
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S3_INT_PRIO_DEF
-#define ESP_IRQ_TRIGGER_LEVEL ESP32S3_CPUINT_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#define esp_setup_irq esp32s2_setup_irq
-#define esp_teardown_irq esp32s2_teardown_irq
-#define esp_configgpio esp32s2_configgpio
-#define esp_gpio_matrix_in esp32s2_gpio_matrix_in
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S2_INT_PRIO_DEF
-#define ESP_IRQ_TRIGGER_LEVEL ESP32S2_CPUINT_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32)
-#define esp_setup_irq esp32_setup_irq
-#define esp_teardown_irq esp32_teardown_irq
-#define esp_configgpio esp32_configgpio
-#define esp_gpio_matrix_in esp32_gpio_matrix_in
#define ESP_IRQ_PRIORITY_DEFAULT 1
-#define ESP_IRQ_TRIGGER_LEVEL ESP32_CPUINT_LEVEL
+#endif
+
+#if !SOC_RCC_IS_INDEPENDENT
+# define PCNT_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
+#else
+# define PCNT_RCC_ATOMIC()
#endif
/****************************************************************************
@@ -136,7 +127,7 @@ struct esp_pcnt_priv_s
spinlock_t lock; /* Device specific lock. */
int (*cb)(int, void *, void *); /* User defined callback */
uint32_t accum_value; /* Accumulator value of overflowed PCNT unit */
- bool channels[SOC_PCNT_CHANNELS_PER_UNIT]; /* Channel information of PCNT unit */
+ bool channels[PCNT_LL_GET(CHANS_PER_UNIT)]; /* Channel information of PCNT unit */
struct esp_pcnt_watch_point_priv_s watchers[PCNT_LL_WATCH_EVENT_MAX]; /* array of PCNT watchers */
};
@@ -148,8 +139,7 @@ static int esp_pcnt_open(struct cap_lowerhalf_s *dev);
static int esp_pcnt_close(struct cap_lowerhalf_s *dev);
static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context,
void *arg);
-static int esp_pcnt_isr_register(int (*fn)(int, void *, void *),
- int intr_alloc_flags);
+static int esp_pcnt_isr_register(int (*fn)(int, void *, void *), void *arg);
static int esp_pcnt_ioctl(struct cap_lowerhalf_s *dev, int cmd,
unsigned long arg);
static int esp_pcnt_unit_enable(struct cap_lowerhalf_s *dev);
@@ -405,13 +395,13 @@ static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context,
struct esp_pcnt_watch_event_data_s data;
irqstate_t flags;
- for (unit_id = 0; unit_id < SOC_PCNT_UNITS_PER_GROUP; unit_id++)
+ for (unit_id = 0; unit_id < PCNT_LL_GET(UNITS_PER_INST); unit_id++)
{
if (intr_status & PCNT_LL_UNIT_WATCH_EVENT(unit_id))
break;
}
- if (unit_id < SOC_PCNT_UNITS_PER_GROUP)
+ if (unit_id < PCNT_LL_GET(UNITS_PER_INST))
{
unit = &pcnt_units[unit_id];
pcnt_ll_clear_intr_status(ctx.dev, PCNT_LL_UNIT_WATCH_EVENT(unit_id));
@@ -461,7 +451,7 @@ static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context,
*
* Input Parameters:
* fn - Pointer to the ISR function.
- * intr_alloc_flags - Flags for the interrupt allocation.
+ * arg - Pointer to the argument to be passed to the ISR.
*
* Returned Value:
* Returns OK on successful registration of the ISR; a negated errno value
@@ -469,44 +459,29 @@ static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context,
*
****************************************************************************/
-static int esp_pcnt_isr_register(int (*fn)(int, void *, void *),
- int intr_alloc_flags)
+static int esp_pcnt_isr_register(int (*fn)(int, void *, void *), void *arg)
{
+ struct intr_adapter_from_nuttx *adapter;
int cpuint;
+#ifndef CONFIG_ARCH_CHIP_ESP32S2
int ret;
int cpu = this_cpu();
+#endif
DEBUGASSERT(fn);
-
- cpuint = esp_setup_irq(
-#ifndef CONFIG_ARCH_CHIP_ESP32S2
- cpu,
-#endif
- pcnt_periph_signals.groups[0].irq,
+ cpuint = esp_setup_irq(soc_pcnt_signals[0].irq_id,
ESP_IRQ_PRIORITY_DEFAULT,
- ESP_IRQ_TRIGGER_LEVEL);
+ ESP_IRQ_TRIGGER_LEVEL,
+ fn,
+ arg);
+
if (cpuint < 0)
{
cperr("Failed to allocate a CPU interrupt.\n");
return ERROR;
}
- ret = irq_attach((pcnt_periph_signals.groups[0].irq +
- XTENSA_IRQ_FIRSTPERIPH),
- fn,
- 0);
- if (ret < 0)
- {
- cperr("Couldn't attach IRQ to handler.\n");
- esp_teardown_irq(
-#ifndef CONFIG_ARCH_CHIP_ESP32S2
- cpu,
-#endif
- pcnt_periph_signals.groups[0].irq, cpuint);
- return ERROR;
- }
-
- up_enable_irq(pcnt_periph_signals.groups[0].irq + XTENSA_IRQ_FIRSTPERIPH);
+ up_enable_irq(soc_pcnt_signals[0].irq_id + XTENSA_IRQ_FIRSTPERIPH);
return OK;
}
@@ -878,8 +853,12 @@ struct cap_lowerhalf_s *esp_pcnt_new_unit(
if (g_pcnt_refs++ == 0)
{
- periph_module_enable(PERIPH_PCNT_MODULE);
- periph_module_reset(PERIPH_PCNT_MODULE);
+ PCNT_RCC_ATOMIC()
+ {
+ pcnt_ll_enable_bus_clock(0, true);
+ pcnt_ll_reset_register(0);
+ }
+
pcnt_hal_init(&ctx, 0);
}
@@ -985,7 +964,7 @@ int esp_pcnt_del_unit(struct cap_lowerhalf_s *dev)
return ERROR;
}
- for (i = 0; i < SOC_PCNT_CHANNELS_PER_UNIT; i++)
+ for (i = 0; i < PCNT_LL_GET(CHANS_PER_UNIT); i++)
{
if (!priv->channels[i])
{
@@ -1009,12 +988,12 @@ int esp_pcnt_del_unit(struct cap_lowerhalf_s *dev)
g_pcnt_refs--;
if (g_pcnt_refs == 0)
{
- periph_module_disable(PERIPH_PCNT_MODULE);
- esp_teardown_irq(
-#ifndef CONFIG_ARCH_CHIP_ESP32S2
- cpu,
-#endif
- pcnt_periph_signals.groups[0].irq, -ENOMEM);
+ PCNT_RCC_ATOMIC()
+ {
+ pcnt_ll_enable_bus_clock(0, false);
+ }
+
+ esp_teardown_irq(soc_pcnt_signals[0].irq_id, -ENOMEM);
}
spin_unlock_irqrestore(&priv->lock, flags);
@@ -1124,7 +1103,7 @@ int esp_pcnt_unit_add_watch_point(struct cap_lowerhalf_s *dev,
else
{
- int thres_num = SOC_PCNT_THRES_POINT_PER_UNIT - 1;
+ int thres_num = PCNT_LL_GET(THRES_POINT_PER_UNIT) - 1;
switch (thres_num)
{
case 1:
@@ -1279,7 +1258,6 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev,
int gpio_mode;
int virt_gpio;
int ret_id = 0;
- const pcnt_signal_conn_t *chan;
if (!config)
{
@@ -1299,7 +1277,7 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev,
return ERROR;
}
- for (int i = 0; i < SOC_PCNT_CHANNELS_PER_UNIT; i++)
+ for (int i = 0; i < PCNT_LL_GET(CHANS_PER_UNIT); i++)
{
if (!priv->channels[i])
{
@@ -1318,13 +1296,13 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev,
(config->flags && ESP_PCNT_CHAN_IO_LOOPBACK ? OUTPUT_FUNCTION : 0);
virt_gpio = (config->flags && ESP_PCNT_CHAN_VIRT_LVL_IO_LVL) ?
GPIO_MATRIX_CONST_ONE_INPUT : GPIO_MATRIX_CONST_ZERO_INPUT;
- chan = &pcnt_periph_signals;
if (config->edge_gpio_num >= 0)
{
esp_configgpio(config->edge_gpio_num, gpio_mode);
esp_gpio_matrix_in(config->edge_gpio_num,
- chan->groups[0].units[unit_id].channels[channel_id].pulse_sig,
+ soc_pcnt_signals[0].units[unit_id].channels[channel_id].\
+ pulse_sig_id_matrix,
(config->flags && ESP_PCNT_CHAN_INVERT_EDGE_IN));
}
else
@@ -1332,7 +1310,8 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev,
/* using virtual IO */
esp_gpio_matrix_in(virt_gpio,
- chan->groups[0].units[unit_id].channels[channel_id].pulse_sig,
+ soc_pcnt_signals[0].units[unit_id].channels[channel_id].\
+ pulse_sig_id_matrix,
(config->flags && ESP_PCNT_CHAN_INVERT_EDGE_IN));
}
@@ -1340,7 +1319,8 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev,
{
esp_configgpio(config->level_gpio_num, gpio_mode);
esp_gpio_matrix_in(config->level_gpio_num,
- chan->groups[0].units[unit_id].channels[channel_id].control_sig,
+ soc_pcnt_signals[0].units[unit_id].channels[channel_id].\
+ ctl_sig_id_matrix,
(config->flags && ESP_PCNT_CHAN_INVERT_LVL_IN));
}
else
@@ -1348,7 +1328,8 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev,
/* using virtual IO */
esp_gpio_matrix_in(virt_gpio,
- chan->groups[0].units[unit_id].channels[channel_id].control_sig,
+ soc_pcnt_signals[0].units[unit_id].channels[channel_id].\
+ ctl_sig_id_matrix,
(config->flags && ESP_PCNT_CHAN_INVERT_LVL_IN));
}
diff --git a/arch/xtensa/src/common/espressif/esp_pm.c b/arch/xtensa/src/common/espressif/esp_pm.c
index 639dd3b737d..e161dc0dc9a 100644
--- a/arch/xtensa/src/common/espressif/esp_pm.c
+++ b/arch/xtensa/src/common/espressif/esp_pm.c
@@ -31,24 +31,30 @@
#include <debug.h>
#include "esp_pm.h"
+#include "esp_hr_timer.h"
+
#ifdef CONFIG_SCHED_TICKLESS
-# include "esp_tickless.h"
+# if defined(CONFIG_ARCH_CHIP_ESP32)
+# include "esp32_tickless.h"
+# elif defined(CONFIG_ARCH_CHIP_ESP32S2)
+# include "esp32s2_tickless.h"
+# elif defined(CONFIG_ARCH_CHIP_ESP32S3)
+# include "esp32s3_tickless.h"
+# endif
#endif
#include "esp_sleep.h"
#include "soc/rtc.h"
#include "esp_sleep_internal.h"
#include "esp_pmu.h"
+#include "esp_attr.h"
+#include "esp_private/pm_impl.h"
#ifdef CONFIG_PM_EXT1_WAKEUP
# include "driver/rtc_io.h"
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP
# include "driver/gpio.h"
# include "hal/gpio_types.h"
-# if defined(CONFIG_ARCH_CHIP_ESP32S3)
-# include "esp32s3_gpio.h"
-# elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-# include "esp32s2_gpio.h"
-#endif
+# include "esp_gpio.h"
#endif
#ifdef CONFIG_PM_UART_WAKEUP
# include "driver/uart_wakeup.h"
@@ -60,11 +66,17 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
-
-#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#define esp_configgpio esp32s3_configgpio
-#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#define esp_configgpio esp32s2_configgpio
+#ifdef CONFIG_PM_EXT0_WAKEUP
+# define EXT0_WAIT_TIME_US 5000000
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP
+# define EXT1_WAIT_TIME_US 5000000
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP
+# define GPIO_WAIT_TIME_US 5000000
+#endif
+#ifdef CONFIG_PM_UART_WAKEUP
+# define UART_WAIT_TIME_US 5000000
#endif
/****************************************************************************
@@ -92,7 +104,9 @@ const char *g_wakeup_reasons[] =
""
};
-static _Atomic uint32_t pm_wakelock = 0;
+static esp_sleep_wakeup_cause_t g_last_wakeup_reason =
+ ESP_SLEEP_WAKEUP_UNDEFINED;
+static uint64_t g_last_wakeup_time = 0;
/****************************************************************************
* Private Functions
@@ -360,7 +374,60 @@ static uint64_t IRAM_ATTR esp_pm_get_gpio_mask(void)
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO30
io_mask |= BIT(30);
#endif
-
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO31
+ io_mask |= BIT(31);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO32
+ io_mask |= BIT(32);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO33
+ io_mask |= BIT(33);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO34
+ io_mask |= BIT(34);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO35
+ io_mask |= BIT(35);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO36
+ io_mask |= BIT(36);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO37
+ io_mask |= BIT(37);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO38
+ io_mask |= BIT(38);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO39
+ io_mask |= BIT(39);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO40
+ io_mask |= BIT(40);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO41
+ io_mask |= BIT(41);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO42
+ io_mask |= BIT(42);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO43
+ io_mask |= BIT(43);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO44
+ io_mask |= BIT(44);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO45
+ io_mask |= BIT(45);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO46
+ io_mask |= BIT(46);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO47
+ io_mask |= BIT(47);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO48
+ io_mask |= BIT(48);
+#endif
return io_mask;
}
@@ -435,6 +502,161 @@ static void IRAM_ATTR esp_pm_uart_wakeup_prepare(void)
}
#endif /* CONFIG_PM_UART_WAKEUP */
+#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP
+
+/****************************************************************************
+ * Name: esp_pm_skip_light_sleep
+ *
+ * Description:
+ * Callback for the power manager's "skip light sleep" hook. This function
+ * checks if the system should defer entering light sleep after waking up
+ * from any supported wakeup source (EXT0, EXT1, GPIO, UART). It compares
+ * the current time to the last wakeup time for each source. If the system
+ * is still within the configured guard window for any wakeup source, it
+ * returns true to skip light sleep and let peripheral activity finish. If
+ * the guard window has elapsed or there was no wakeup, it returns false
+ * and allows light sleep to proceed.
+ *
+ * Placed in IRAM because it runs in timing-critical power management
+ * decision paths.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * true - Skip light sleep (recent EXT0, EXT1, GPIO, or UART wakeup still
+ * within the configured guard window).
+ * false - Allow light sleep (no relevant wakeup or guard window elapsed).
+ *
+ ****************************************************************************/
+
+static bool IRAM_ATTR esp_pm_skip_light_sleep(void)
+{
+ bool skip = false;
+#if defined(CONFIG_PM_EXT0_WAKEUP) || \
+ defined(CONFIG_PM_EXT1_WAKEUP) || \
+ defined(CONFIG_PM_GPIO_WAKEUP) || \
+ defined(CONFIG_PM_UART_WAKEUP)
+ uint64_t current_time = esp_hr_timer_time_us();
+#endif
+
+#ifdef CONFIG_PM_EXT0_WAKEUP
+ if (g_last_wakeup_reason == ESP_SLEEP_WAKEUP_EXT0 &&
+ current_time < (g_last_wakeup_time + EXT0_WAIT_TIME_US))
+ {
+ pwrinfo("EXT0 wakeup still within guard window\n");
+ skip = true;
+ }
+#endif
+
+#ifdef CONFIG_PM_EXT1_WAKEUP
+ if (g_last_wakeup_reason == ESP_SLEEP_WAKEUP_EXT1 &&
+ current_time < (g_last_wakeup_time + EXT1_WAIT_TIME_US))
+ {
+ pwrinfo("EXT1 wakeup still within guard window\n");
+ skip = true;
+ }
+#endif
+
+#ifdef CONFIG_PM_GPIO_WAKEUP
+ if (g_last_wakeup_reason == ESP_SLEEP_WAKEUP_GPIO &&
+ current_time < (g_last_wakeup_time + GPIO_WAIT_TIME_US))
+ {
+ pwrinfo("GPIO wakeup still within guard window\n");
+ skip = true;
+ }
+#endif
+
+#ifdef CONFIG_PM_UART_WAKEUP
+ if (g_last_wakeup_reason == ESP_SLEEP_WAKEUP_UART &&
+ current_time < (g_last_wakeup_time + UART_WAIT_TIME_US))
+ {
+ pwrinfo("UART wakeup still within guard window\n");
+ skip = true;
+ }
+#endif
+
+ return skip;
+}
+
+/****************************************************************************
+ * Name: esp_pm_light_sleep_exit_cb
+ *
+ * Description:
+ * Store wakeup reason and timestamp on light sleep exit.
+ *
+ * Input Parameters:
+ * sleep_time_us - Actual sleep time in microseconds (unused).
+ * arg - User callback argument (unused).
+ *
+ * Returned Value:
+ * ESP_OK
+ *
+ ****************************************************************************/
+
+static esp_err_t IRAM_ATTR esp_pm_light_sleep_exit_cb(int64_t sleep_time_us,
+ void *arg)
+{
+ esp_sleep_wakeup_cause_t wc;
+ uint64_t tw;
+
+ UNUSED(sleep_time_us);
+ UNUSED(arg);
+
+ wc = esp_sleep_get_wakeup_cause();
+ tw = esp_hr_timer_time_us();
+
+ esp_pm_wakeup_set_last_reason((int32_t)wc);
+ esp_pm_wakeup_set_last_time(tw);
+
+ return ESP_OK;
+}
+#endif /* CONFIG_ESPRESSIF_AUTO_SLEEP */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp_pm_wakeup_set_last_reason
+ *
+ * Description:
+ * Store the sleep exit wakeup cause after light sleep.
+ *
+ * Input Parameters:
+ * reason - Value from esp_sleep_get_wakeup_cause().
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp_pm_wakeup_set_last_reason(int32_t reason)
+{
+ g_last_wakeup_reason = reason;
+}
+
+/****************************************************************************
+ * Name: esp_pm_wakeup_set_last_time
+ *
+ * Description:
+ * Store the high-resolution timestamp (microseconds) for the last light
+ * sleep exit, together with the cause from
+ * esp_pm_wakeup_set_last_reason().
+ *
+ * Input Parameters:
+ * time_us - Time from esp_hr_timer_time_us() at exit from light sleep.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp_pm_wakeup_set_last_time(uint64_t time_us)
+{
+ g_last_wakeup_time = time_us;
+}
+
/****************************************************************************
* Name: esp_pm_sleep_enable_timer_wakeup
*
@@ -449,15 +671,11 @@ static void IRAM_ATTR esp_pm_uart_wakeup_prepare(void)
*
****************************************************************************/
-static void esp_pm_sleep_enable_timer_wakeup(uint64_t time_in_us)
+void esp_pm_sleep_enable_timer_wakeup(uint64_t time_in_us)
{
esp_sleep_enable_timer_wakeup(time_in_us);
}
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
/****************************************************************************
* Name: esp_pm_light_sleep_start
*
@@ -601,59 +819,85 @@ void esp_pmsleep(uint64_t time_in_us)
esp_pm_deep_sleep_start();
}
+#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP
+
/****************************************************************************
- * Name: esp_pm_lockacquire
+ * Name: esp_pmconfigure
*
* Description:
- * Take a power management lock
+ * Configure power manager.
*
* Input Parameters:
- * None
+ * None.
*
* Returned Value:
- * None
+ * Returns OK on success; a negated errno value on failure.
*
****************************************************************************/
-void IRAM_ATTR esp_pm_lockacquire(void)
+int esp_pmconfigure(void)
{
- ++pm_wakelock;
-}
+ int ret;
+ esp_err_t err = ESP_OK;
+#ifdef CONFIG_PM_EXT1_WAKEUP
+ int64_t ext1_mask;
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP
+ int64_t gpio_mask;
+#endif
+ esp_pm_config_t pm_config =
+ {
+ .max_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ,
+ .min_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ,
+#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP
+ .light_sleep_enable = true
+#endif
+ };
-/****************************************************************************
- * Name: esp_pm_lockrelease
- *
- * Description:
- * Release the lock taken using esp_pm_lockacquire.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
+ ret = esp_pm_configure(&pm_config);
+ if (ret != OK)
+ {
+ return ret;
+ }
-void IRAM_ATTR esp_pm_lockrelease(void)
-{
- --pm_wakelock;
-}
+#ifdef CONFIG_PM_EXT0_WAKEUP
+ esp_pm_ext0_wakeup_prepare();
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP
+ esp_pm_ext1_wakeup_prepare();
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP
+ esp_pm_gpio_wakeup_prepare();
+#endif
+#ifdef CONFIG_PM_UART_WAKEUP
+ esp_pm_uart_wakeup_prepare();
+#endif /* CONFIG_PM_UART_WAKEUP */
-/****************************************************************************
- * Name: esp_pm_lockstatus
- *
- * Description:
- * Return power management lock status.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * Current pm_wakelock count
- *
- ****************************************************************************/
+ err = esp_pm_register_skip_light_sleep_callback(
+ esp_pm_skip_light_sleep);
+ if (err != ESP_OK)
+ {
+ pwrerr("Failed to register skip light sleep callback: %d\n", err);
+ return -ENOMEM;
+ }
-uint32_t IRAM_ATTR esp_pm_lockstatus(void)
-{
- return pm_wakelock;
+ esp_pm_sleep_cbs_register_config_t sleep_cbs =
+ {
+ .enter_cb = NULL,
+ .exit_cb = esp_pm_light_sleep_exit_cb,
+ .enter_cb_user_arg = NULL,
+ .exit_cb_user_arg = NULL,
+ .enter_cb_prior = 0,
+ .exit_cb_prior = 0,
+ };
+
+ err = esp_pm_light_sleep_register_cbs(&sleep_cbs);
+ if (err != ESP_OK)
+ {
+ pwrerr("Failed to register light sleep callbacks: %d\n", err);
+ return -ENOMEM;
+ }
+
+ return ret;
}
+#endif /* CONFIG_ESPRESSIF_AUTO_SLEEP */
diff --git a/arch/xtensa/src/common/espressif/esp_pm.h b/arch/xtensa/src/common/espressif/esp_pm.h
index c12cff991c8..7c3c1dfe569 100644
--- a/arch/xtensa/src/common/espressif/esp_pm.h
+++ b/arch/xtensa/src/common/espressif/esp_pm.h
@@ -44,11 +44,32 @@ extern "C"
#endif
#ifdef CONFIG_PM
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+typedef bool (*skip_light_sleep_cb_t)(void);
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
+/****************************************************************************
+ * Name: esp_pm_sleep_enable_timer_wakeup
+ *
+ * Description:
+ * Configure wakeup interval
+ *
+ * Input Parameters:
+ * time_in_us - Sleep duration in microseconds.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp_pm_sleep_enable_timer_wakeup(uint64_t time_in_us);
+
/****************************************************************************
* Name: esp_pm_light_sleep_start
*
@@ -115,52 +136,57 @@ void esp_pmstandby(uint64_t time_in_us);
void esp_pmsleep(uint64_t time_in_us);
/****************************************************************************
- * Name: esp_pm_lockacquire
+ * Name: esp_pmconfigure
*
* Description:
- * Take a power management lock
+ * Configure power manager.
*
* Input Parameters:
* None
*
* Returned Value:
- * None
+ * Returns OK on success; a negated errno value on failure.
*
****************************************************************************/
-void esp_pm_lockacquire(void);
+#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP
+int esp_pmconfigure(void);
+#endif
/****************************************************************************
- * Name: esp_pm_lockrelease
+ * Name: esp_pm_wakeup_set_last_reason
*
* Description:
- * Release the lock taken using esp_pm_lockacquire.
+ * Store the sleep exit wakeup cause after light sleep. Used with
+ * esp_pm_wakeup_set_last_time() so the skip-light-sleep hook can
+ * detect a recent UART wakeup.
*
* Input Parameters:
- * None
+ * reason - Value from esp_sleep_get_wakeup_cause().
*
* Returned Value:
* None
*
****************************************************************************/
-void esp_pm_lockrelease(void);
+void esp_pm_wakeup_set_last_reason(int32_t reason);
/****************************************************************************
- * Name: esp_pm_lockstatus
+ * Name: esp_pm_wakeup_set_last_time
*
* Description:
- * Return power management lock status.
+ * Store the high-resolution timestamp (microseconds) aligned with
+ * the wakeup cause set by esp_pm_wakeup_set_last_reason().
*
* Input Parameters:
- * None
+ * time_us - Time from esp_hr_timer_time_us() at exit from light sleep.
*
* Returned Value:
- * Current pm_wakelock count
+ * None
*
****************************************************************************/
-uint32_t esp_pm_lockstatus(void);
+void esp_pm_wakeup_set_last_time(uint64_t time_us);
#endif /* CONFIG_PM */
diff --git a/arch/xtensa/src/common/espressif/esp_rmt.c b/arch/xtensa/src/common/espressif/esp_rmt.c
index 7e7a9ccb7cc..2108962474a 100644
--- a/arch/xtensa/src/common/espressif/esp_rmt.c
+++ b/arch/xtensa/src/common/espressif/esp_rmt.c
@@ -43,29 +43,16 @@
#include <nuttx/spinlock.h>
#include <nuttx/circbuf.h>
-#include "xtensa.h"
-#ifdef CONFIG_ARCH_CHIP_ESP32
-#include "hardware/esp32_soc.h"
-#include "esp32_gpio.h"
-#include "esp32_irq.h"
-#elif CONFIG_ARCH_CHIP_ESP32S2
-#include "hardware/esp32s2_soc.h"
-#include "esp32s2_gpio.h"
-#include "esp32s2_irq.h"
-#elif CONFIG_ARCH_CHIP_ESP32S3
-#include "hardware/esp32s3_soc.h"
-#include "esp32s3_gpio.h"
-#include "esp32s3_irq.h"
-#endif
+#include "esp_irq.h"
-#include "hal/gpio_types.h"
-#include "hal/rmt_hal.h"
-#include "hal/rmt_ll.h"
-#include "periph_ctrl.h"
-#include "soc/gpio_sig_map.h"
-#include "soc/rmt_periph.h"
-#include "soc/soc_caps.h"
-#include "esp_clk_tree.h"
+#include "esp_err.h"
+#include "driver/rmt_types.h"
+#include "driver/rmt_rx.h"
+#include "driver/rmt_tx.h"
+#include "driver/rmt_encoder.h"
+#include "driver/rmt_common.h"
+#include "esp_private/rmt.h"
+#include "rmt_private.h"
#include "esp_rmt.h"
@@ -88,186 +75,22 @@
#define RMT_ENCODE_RX_CHANNEL(decode_chan) \
((decode_chan + RMT_RX_CHANNEL_ENCODING_START))
-/* Default configuration for TX channel */
-
-#define RMT_DEFAULT_CONFIG_TX(gpio, channel_id) \
- { \
- .rmt_mode = RMT_MODE_TX, \
- .channel = channel_id, \
- .gpio_num = gpio, \
- .clk_div = RMT_DEFAULT_CLK_DIV, \
- .mem_block_num = 1, \
- .flags = 0, \
- .tx_config = { \
- .carrier_freq_hz = 38000, \
- .carrier_level = RMT_CARRIER_LEVEL_HIGH, \
- .idle_level = RMT_IDLE_LEVEL_LOW, \
- .carrier_duty_percent = 33, \
- .loop_count = 0, \
- .carrier_en = false, \
- .loop_en = false, \
- .idle_output_en = true, \
- } \
- }
-
-/* Default configuration for RX channel */
-
-#define RMT_DEFAULT_CONFIG_RX(gpio, channel_id) \
- { \
- .rmt_mode = RMT_MODE_RX, \
- .channel = channel_id, \
- .gpio_num = gpio, \
- .clk_div = RMT_DEFAULT_CLK_DIV, \
- .mem_block_num = 1, \
- .flags = 0, \
- .rx_config = { \
- .idle_threshold = 12000, \
- .filter_ticks_thresh = 100, \
- .filter_en = true, \
- } \
- }
-
-#define rmt_item32_t rmt_symbol_word_t
-
-#ifdef CONFIG_ARCH_CHIP_ESP32
-# define esp_configgpio esp32_configgpio
-# define esp_gpio_matrix_out esp32_gpio_matrix_out
-# define esp_gpio_matrix_in esp32_gpio_matrix_in
-# define esp_setup_irq esp32_setup_irq
-# define esp_teardown_irq esp32_teardown_irq
-
-# define GPIO_OUT_FUNC OUTPUT_FUNCTION_3
-# define GPIO_IN_FUNC INPUT_FUNCTION_3
-# define ESP_CPUINT_LEVEL ESP32_CPUINT_LEVEL
-
-#elif CONFIG_ARCH_CHIP_ESP32S2
-# define esp_configgpio esp32s2_configgpio
-# define esp_gpio_matrix_out esp32s2_gpio_matrix_out
-# define esp_gpio_matrix_in esp32s2_gpio_matrix_in
-# define esp_setup_irq esp32s2_setup_irq
-# define esp_teardown_irq esp32s2_teardown_irq
-
-# define GPIO_OUT_FUNC OUTPUT_FUNCTION_2
-# define GPIO_IN_FUNC INPUT_FUNCTION_2
-# define ESP_CPUINT_LEVEL ESP32S2_CPUINT_LEVEL
-
-#elif CONFIG_ARCH_CHIP_ESP32S3
-# define esp_configgpio esp32s3_configgpio
-# define esp_gpio_matrix_out esp32s3_gpio_matrix_out
-# define esp_gpio_matrix_in esp32s3_gpio_matrix_in
-# define esp_setup_irq esp32s3_setup_irq
-# define esp_teardown_irq esp32s3_teardown_irq
-
-# define GPIO_OUT_FUNC OUTPUT_FUNCTION_2
-# define GPIO_IN_FUNC INPUT_FUNCTION_2
-# define ESP_CPUINT_LEVEL ESP32S3_CPUINT_LEVEL
+#if SOC_PERIPH_CLK_CTRL_SHARED
+#define RMT_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
+#else
+#define RMT_CLOCK_SRC_ATOMIC()
+#endif
+#if !SOC_RCC_IS_INDEPENDENT
+#define RMT_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
+#else
+#define RMT_RCC_ATOMIC()
#endif
/****************************************************************************
* Private Types
****************************************************************************/
-/* RMT channel ID */
-
-enum rmt_channel_e
-{
- RMT_CHANNEL_0, /* RMT channel number 0 */
- RMT_CHANNEL_1, /* RMT channel number 1 */
- RMT_CHANNEL_2, /* RMT channel number 2 */
- RMT_CHANNEL_3, /* RMT channel number 3 */
-#if SOC_RMT_CHANNELS_PER_GROUP > 4
- RMT_CHANNEL_4, /* RMT channel number 4 */
- RMT_CHANNEL_5, /* RMT channel number 5 */
- RMT_CHANNEL_6, /* RMT channel number 6 */
- RMT_CHANNEL_7, /* RMT channel number 7 */
-#endif
- RMT_CHANNEL_MAX /* Number of RMT channels */
-};
-
-typedef enum rmt_channel_e rmt_channel_t;
-
-/* RMT Channel Working Mode (TX or RX) */
-
-enum rmt_mode_e
-{
- RMT_MODE_TX, /* RMT TX mode */
- RMT_MODE_RX, /* RMT RX mode */
- RMT_MODE_MAX
-};
-
-typedef enum rmt_mode_e rmt_mode_t;
-
-/* RMT Idle Level */
-
-enum rmt_idle_level_e
-{
- RMT_IDLE_LEVEL_LOW, /* RMT TX idle level: low Level */
- RMT_IDLE_LEVEL_HIGH, /* RMT TX idle level: high Level */
- RMT_IDLE_LEVEL_MAX,
-};
-
-typedef enum rmt_idle_level_e rmt_idle_level_t;
-
-/* RMT Carrier Level */
-
-enum rmt_carrier_level_e
-{
- RMT_CARRIER_LEVEL_LOW, /* RMT carrier wave is modulated for low Level output */
- RMT_CARRIER_LEVEL_HIGH, /* RMT carrier wave is modulated for high Level output */
- RMT_CARRIER_LEVEL_MAX
-};
-
-typedef enum rmt_carrier_level_e rmt_carrier_level_t;
-
-/* RMT Channel Status */
-
-enum rmt_channel_status_e
-{
- RMT_CHANNEL_UNINIT, /* RMT channel uninitialized */
- RMT_CHANNEL_IDLE, /* RMT channel status idle */
- RMT_CHANNEL_BUSY, /* RMT channel status busy */
-};
-
-typedef enum rmt_channel_status_e rmt_channel_status_t;
-
-/* RMT hardware memory layout */
-
-struct rmt_channel_data_s
-{
- volatile rmt_item32_t data32[SOC_RMT_MEM_WORDS_PER_CHANNEL];
-};
-
-struct rmt_mem_s
-{
- struct rmt_channel_data_s chan[SOC_RMT_CHANNELS_PER_GROUP];
-};
-
-typedef struct rmt_mem_s rmt_mem_t;
-
-struct rmt_dev_common_s
-{
- rmt_hal_context_t hal; /* HAL context */
- rmutex_t rmt_driver_isr_lock;
-
- /* Mutex lock for protecting concurrent register/unregister of the RMT
- * channels' ISR.
- */
-
- spinlock_t rmt_spinlock;
-
- /* Bitmask of installed drivers' channels, used to protect concurrent
- * register/unregister of the RMT channels' ISR.
- */
-
- uint8_t rmt_driver_channels;
- bool rmt_module_enabled;
-
- /* Bitmap of channels already added in the synchronous group */
-
- uint32_t synchro_channel_mask;
-};
-
struct rmt_dev_lowerhalf_s
{
/* The following block is part of the upper-half device struct */
@@ -279,118 +102,19 @@ struct rmt_dev_lowerhalf_s
/* The following is private to the ESP32 RMT driver */
- rmt_mode_t mode;
- struct rmt_dev_common_s *common; /* RMT peripheral common parameters */
-};
-
-struct rmt_obj_s
-{
- size_t tx_offset;
- size_t tx_len_rem;
- size_t tx_sub_len;
- bool wait_done; /* Mark whether wait tx done */
- bool loop_autostop; /* Mark whether loop auto-stop is enabled */
- rmt_channel_t channel;
- const rmt_item32_t *tx_data;
- sem_t tx_sem;
-#ifdef CONFIG_SPIRAM_USE_MALLOC
- int intr_alloc_flags;
- sem_t tx_sem_buffer;
-#endif
- rmt_item32_t *tx_buf;
- struct circbuf_s rx_buf;
- sem_t rx_sem;
-#ifdef SOC_RMT_SUPPORT_RX_PINGPONG
- rmt_item32_t *rx_item_buf;
- uint32_t rx_item_buf_size;
- uint32_t rx_item_len;
- int rx_item_start_idx;
-#endif
- void *tx_context;
- size_t sample_size_remain;
- const uint8_t *sample_cur;
-};
-
-typedef struct rmt_obj_s rmt_obj_t;
-
-/* Data struct of RMT TX configure parameters */
-
-struct rmt_tx_config_s
-{
- uint32_t carrier_freq_hz; /* RMT carrier frequency */
- rmt_carrier_level_t carrier_level; /* Level of the RMT output, when the carrier is applied */
- rmt_idle_level_t idle_level; /* RMT idle level */
- uint8_t carrier_duty_percent; /* RMT carrier duty (%) */
- uint32_t loop_count; /* Maximum loop count, only take effect for chips that is capable of `SOC_RMT_SUPPORT_TX_LOOP_COUNT` */
- bool carrier_en; /* RMT carrier enable */
- bool loop_en; /* Enable sending RMT items in a loop */
- bool idle_output_en; /* RMT idle level output enable */
-};
-
-/* Data struct of RMT RX configure parameters */
-
-struct rmt_rx_config_s
-{
- uint16_t idle_threshold; /* RMT RX idle threshold */
- uint8_t filter_ticks_thresh; /* RMT filter tick number */
- bool filter_en; /* RMT receiver filter enable */
-#if SOC_RMT_SUPPORT_RX_DEMODULATION
- bool rm_carrier; /* RMT receiver remove carrier enable */
- uint32_t carrier_freq_hz; /* RMT carrier frequency */
- uint8_t carrier_duty_percent; /* RMT carrier duty (%) */
- rmt_carrier_level_t carrier_level; /* The level to remove the carrier */
-#endif
-};
-
-struct rmt_channel_config_s
-{
- rmt_mode_t rmt_mode; /* RMT mode: transmitter or receiver */
- rmt_channel_t channel; /* RMT channel */
- int gpio_num; /* RMT GPIO number */
- uint8_t clk_div; /* RMT channel counter divider */
- uint8_t mem_block_num; /* RMT memory block number */
- uint32_t flags; /* RMT channel extra configurations, OR'd with RMT_CHANNEL_FLAGS_[*] */
- union
- {
- struct rmt_tx_config_s tx_config; /* RMT TX parameter */
- struct rmt_rx_config_s rx_config; /* RMT RX parameter */
- };
+ rmt_channel_handle_t handle;
+ rmt_encoder_handle_t encoder;
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
-static void rmt_module_enable(void);
-static int rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst);
-static int rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst);
-static int rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en);
-static int rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en,
- uint16_t evt_thresh);
-static int rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode,
- gpio_num_t gpio_num, bool invert_signal);
-static bool rmt_is_channel_number_valid(rmt_channel_t channel, uint8_t mode);
-static int rmt_internal_config(rmt_dev_t *dev,
- const struct rmt_channel_config_s *rmt_param);
-static int rmt_config(const struct rmt_channel_config_s *rmt_param);
-static void rmt_fill_memory(rmt_channel_t channel, const rmt_item32_t *item,
- uint16_t item_num, uint16_t mem_offset);
-static int rmt_isr_register(int (*fn)(int, void *, void *), void *arg,
- int intr_alloc_flags);
-static int rmt_driver_isr_default(int irq, void *context, void *arg);
-static int rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size,
- int intr_alloc_flags);
-static int rmt_write_items(rmt_channel_t channel,
- const rmt_item32_t *rmt_item,
- int item_num,
- bool wait_tx_done);
static ssize_t esp_rmt_read(struct rmt_dev_s *dev, char *buffer,
- size_t buflen);
+ size_t buflen);
static ssize_t esp_rmt_write(struct rmt_dev_s *dev,
const char *buffer,
size_t buflen);
-static struct rmt_dev_s
- *esp_rmtinitialize(struct rmt_channel_config_s config);
/****************************************************************************
* Private Data
@@ -402,1592 +126,334 @@ static const struct rmt_ops_s g_rmtops =
.write = esp_rmt_write,
};
-static struct rmt_dev_common_s g_rmtdev_common =
-{
- .hal.regs = &RMT,
- .rmt_driver_isr_lock = NXRMUTEX_INITIALIZER,
- .rmt_driver_channels = 0,
- .rmt_module_enabled = false,
- .synchro_channel_mask = 0
-};
-
-static struct rmt_obj_s *p_rmt_obj[RMT_CHANNEL_MAX];
-
-#ifdef CONFIG_RMT_LOOP_TEST_MODE
-static rmt_channel_t g_tx_channel = RMT_CHANNEL_MAX;
-static rmt_channel_t g_rx_channel = RMT_CHANNEL_MAX;
-#endif
-
-#if SOC_RMT_CHANNEL_CLK_INDEPENDENT
-uint32_t g_rmt_source_clock_hz[RMT_CHANNEL_MAX];
-#else
-uint32_t g_rmt_source_clock_hz;
-#endif
-
-/* RMTMEM address is declared in <target>.peripherals.ld */
-
-extern rmt_mem_t RMTMEM;
-
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
- * Name: rmt_module_enable
+ * Name: esp_rmt_read
*
* Description:
- * This function enables the RMT (Remote Control) module if it's not
- * already enabled.
+ * This function reads data from the RMT device.
+ * It starts the RMT module in receiving mode for a specific channel and
+ * checks for any errors. If an error occurs during the start of the RMT
+ * module, it returns the error code. Please note that this function
+ * starts the receiver, but the actual data is read from the ring buffer
+ * by the upper half driver.
*
* Input Parameters:
- * None.
+ * dev - Pointer to the RMT device structure.
+ * buffer - Pointer to the buffer where the read data should be stored.
+ * buflen - The maximum amount of data to be read.
*
* Returned Value:
- * None.
+ * Returns the number of bytes read from the RMT device; a negated errno
+ * value is returned on any failure.
*
****************************************************************************/
-static void rmt_module_enable(void)
+static ssize_t esp_rmt_read(struct rmt_dev_s *dev, char *buffer,
+ size_t buflen)
{
- irqstate_t flags;
+ esp_err_t esp_ret;
+ struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev;
+ rmt_receive_config_t receive_config =
+ {
+ .signal_range_min_ns = 1250,
+ .signal_range_max_ns = 3000000,
+ };
- flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock);
+ DEBUGASSERT((buflen % 4) == 0);
- if (g_rmtdev_common.rmt_module_enabled == false)
+ if ((buflen / 4) > (CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE / 4))
{
- periph_module_reset(PERIPH_RMT_MODULE);
- periph_module_enable(PERIPH_RMT_MODULE);
- g_rmtdev_common.rmt_module_enabled = true;
+ rmtwarn("WARN: RMT RX buffer (%d bytes) is smaller than requested "
+ "read bytes (%d bytes). A partial read will take place!\n",
+ CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE,
+ buflen);
}
- spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags);
-}
-
-/****************************************************************************
- * Name: rmt_set_rx_thr_intr_en
- *
- * Description:
- * This function enables or disables the RMT RX threshold interrupt. When
- * the number of received items reaches the threshold, an interrupt is
- * triggered if this feature is enabled.
- *
- * Input Parameters:
- * channel - The RMT channel.
- * en - Enable (true) or disable (false) the RX threshold int.
- * evt_thresh - The number of received items that triggers the interrupt.
- *
- * Returned Value:
- * Returns 0 on success; a negated errno value is returned on any failure.
- *
- ****************************************************************************/
-
-#ifdef SOC_RMT_SUPPORT_RX_PINGPONG
-static int rmt_set_rx_thr_intr_en(rmt_channel_t channel, bool en,
- uint16_t evt_thresh)
-{
- irqstate_t flags;
- uint32_t mask;
-
- DEBUGASSERT(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX);
-
- if (en)
+#ifndef SOC_RMT_SUPPORT_RX_PINGPONG
+ if ((buflen / 4) > RMT_MEM_ITEM_NUM)
{
- uint32_t item_block_len =
- rmt_ll_rx_get_mem_blocks(g_rmtdev_common.hal.regs,
- RMT_DECODE_RX_CHANNEL(channel)) *
- RMT_MEM_ITEM_NUM;
-
- if (evt_thresh >= item_block_len)
- {
- rmterr("Invalid threshold value %d\n", evt_thresh);
- return -EINVAL;
- }
-
- flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock);
- rmt_ll_rx_set_limit(g_rmtdev_common.hal.regs,
- RMT_DECODE_RX_CHANNEL(channel), evt_thresh);
- mask = RMT_LL_EVENT_RX_THRES(RMT_DECODE_RX_CHANNEL(channel));
- rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, mask, true);
- spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags);
+ rmtwarn("WARN: RMT RX channel is able to receive up to "
+ "%d RMT items (%d bytes)!",
+ RMT_MEM_ITEM_NUM, RMT_MEM_ITEM_NUM * 4);
}
- else
+#endif
+
+ esp_ret = rmt_receive(priv->handle, buffer,
+ buflen, &receive_config);
+ if (esp_ret != ESP_OK)
{
- flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock);
- mask = RMT_LL_EVENT_RX_THRES(RMT_DECODE_RX_CHANNEL(channel));
- rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, mask, false);
- spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags);
+ rmterr("Failed to Receive RMT data");
+ return -ERROR;
}
- return OK;
+ return (ssize_t)0;
}
-#endif
/****************************************************************************
- * Name: rmt_rx_start
+ * Name: esp_rmt_write
*
* Description:
- * This function starts the RMT module in receiving mode for a specific
- * channel.
+ * This function writes data to the RMT memory for a specific channel. It
+ * asserts that the length of the data is a multiple of 4, then calls the
+ * rmt_write_items function to write the items to the RMT memory.
*
* Input Parameters:
- * channel - The RMT peripheral channel number.
- * rx_idx_rst - If true, the RX index for the channel is reset, which means
- * the receiving process will start from the beginning of the
- * RMT memory block.
+ * dev - Pointer to the RMT device structure.
+ * buffer - Pointer to the data to be written to the RMT memory.
+ * buflen - The length of the data to be written.
*
* Returned Value:
- * Returns OK on successful start of the RMT module in receiving mode; a
- * negated errno value is returned on any failure.
+ * Returns the number of items written to the RMT memory.
*
****************************************************************************/
-static int rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst)
+static ssize_t esp_rmt_write(struct rmt_dev_s *dev, const char *buffer,
+ size_t buflen)
{
- irqstate_t flags;
- rmt_channel_t ch = RMT_DECODE_RX_CHANNEL(channel);
-#ifdef SOC_RMT_SUPPORT_RX_PINGPONG
- const uint32_t item_block_len =
- rmt_ll_rx_get_mem_blocks(g_rmtdev_common.hal.regs, ch) *
- RMT_MEM_ITEM_NUM;
-#endif
-
- DEBUGASSERT(RMT_IS_RX_CHANNEL(channel));
-
- flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock);
-
- rmt_ll_rx_enable(g_rmtdev_common.hal.regs, ch, false);
- if (rx_idx_rst)
+ struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev;
+ rmt_transmit_config_t tx_config =
{
- rmt_ll_rx_reset_pointer(g_rmtdev_common.hal.regs, ch);
- }
-
- rmt_ll_clear_interrupt_status(g_rmtdev_common.hal.regs,
- RMT_LL_EVENT_RX_DONE(ch));
- rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs,
- RMT_LL_EVENT_RX_DONE(ch), true);
-
-#ifdef SOC_RMT_SUPPORT_RX_PINGPONG
- p_rmt_obj[channel]->rx_item_start_idx = 0;
- p_rmt_obj[channel]->rx_item_len = 0;
- rmt_set_rx_thr_intr_en(channel, true, item_block_len / 2);
-#endif
+ .loop_count = 0,
+ };
- rmt_ll_rx_enable(g_rmtdev_common.hal.regs, ch, true);
+ DEBUGASSERT((buflen % 4) == 0);
- spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags);
+ rmt_transmit(priv->handle, priv->encoder, buffer, buflen, &tx_config);
+ rmt_tx_wait_all_done(priv->handle, -1);
- return OK;
+ return (ssize_t)buflen;
}
-/****************************************************************************
- * Name: rmt_tx_start
- *
- * Description:
- * This function starts sending RMT items from the specific channel.
- *
- * Input Parameters:
- * channel - The RMT peripheral channel number.
- * tx_idx_rst - Set it true to reset memory index for TX.
- *
- * Returned Value:
- * Returns OK on successful start of transmission.
- *
- ****************************************************************************/
-
-static int rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst)
+static size_t encoder_callback(const void *data, size_t data_size,
+ size_t symbols_written, size_t symbols_free,
+ rmt_symbol_word_t *symbols, bool *done,
+ void *arg)
{
- irqstate_t flags;
+ size_t data_pos = symbols_written;
+ rmt_symbol_word_t data_bytes =
+ (rmt_symbol_word_t)((uint32_t *)data)[data_pos];
+
+ /* Encode a single symbol */
- DEBUGASSERT(RMT_IS_TX_CHANNEL(channel));
+ symbols[0] = data_bytes;
- flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock);
- if (tx_idx_rst)
+ if (((symbols_written + 1) * 4) == data_size)
{
- rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel);
+ *done = true;
}
- rmt_ll_clear_interrupt_status(g_rmtdev_common.hal.regs,
- RMT_LL_EVENT_TX_DONE(channel));
+ return 1;
+}
- /* Enable tx end interrupt in non-loop mode */
+static bool rmt_rx_done_callback(rmt_channel_handle_t channel,
+ const rmt_rx_done_event_data_t *edata,
+ void *user_data)
+{
+ struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)user_data;
- if (!rmt_ll_tx_is_loop_enabled(g_rmtdev_common.hal.regs, channel))
- {
- rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs,
- RMT_LL_EVENT_TX_DONE(channel), true);
- }
- else
+ int bytes = circbuf_write(priv->circbuf,
+ edata->received_symbols,
+ edata->num_symbols * 4);
+
+ nxsem_post(priv->recvsem);
+ if (bytes < (edata->num_symbols * 4))
{
-#if SOC_RMT_SUPPORT_TX_LOOP_COUNT
- rmt_ll_tx_reset_loop_count(g_rmtdev_common.hal.regs, channel);
- rmt_ll_tx_enable_loop_count(g_rmtdev_common.hal.regs, channel, true);
- rmt_ll_clear_interrupt_status(g_rmtdev_common.hal.regs,
- RMT_LL_EVENT_TX_LOOP_END(channel));
- rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs,
- RMT_LL_EVENT_TX_LOOP_END(channel), true);
-#endif
+ rmterr("RMT RX BUFFER FULL");
}
- rmt_ll_tx_start(g_rmtdev_common.hal.regs, channel);
- spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags);
-
- return OK;
+ return 0;
}
/****************************************************************************
- * Name: rmt_set_tx_loop_mode
- *
- * Description:
- * This function enables or disables the loop mode for RMT transmission on
- * the specified channel. The loop mode, when enabled, allows the RMT
- * transmitter to continuously send items.
- *
- * Input Parameters:
- * channel - The RMT peripheral channel number.
- * loop_en - A boolean indicating whether to enable (true) or disable
- * (false) the loop mode.
- *
- * Returned Value:
- * Returns OK on successful setting of the loop mode.
- *
+ * Public Functions
****************************************************************************/
-static int rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en)
-{
- irqstate_t flags;
-
- DEBUGASSERT(RMT_IS_TX_CHANNEL(channel));
-
- flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock);
- rmt_ll_tx_enable_loop(g_rmtdev_common.hal.regs, channel, loop_en);
- spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags);
-
- return OK;
-}
-
/****************************************************************************
- * Name: rmt_set_tx_thr_intr_en
+ * Name: esp_rmt_tx_init
*
* Description:
- * This function enables or disables the RMT TX threshold interrupt for the
- * specified channel. The threshold is set to trigger an interrupt when the
- * number of transmitted items reaches the specified value.
+ * Initialize the selected RMT device in TX mode
*
* Input Parameters:
- * channel - The RMT peripheral channel number.
- * en - A boolean indicating whether to enable (true) or disable
- * (false) the TX threshold interrupt.
- * evt_thresh - The number of transmitted items at which to trigger the
- * interrupt.
+ * tx_pin - The pin used for the TX channel
*
* Returned Value:
- * Returns OK on successful setting of the interrupt.
+ * Valid RMT device structure reference on success; NULL, otherwise.
*
****************************************************************************/
-static int rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en,
- uint16_t evt_thresh)
+struct rmt_dev_s *esp_rmt_tx_init(int tx_pin)
{
- irqstate_t flags;
-
- DEBUGASSERT(RMT_IS_TX_CHANNEL(channel));
+ int channel_id;
+ esp_err_t ret;
+ struct rmt_dev_lowerhalf_s *priv;
+ rmt_channel_handle_t tx_chan = NULL;
+ rmt_encoder_handle_t simple_encoder = NULL;
+ rmt_tx_channel_config_t tx_chan_config =
+ {
+ .clk_src = RMT_CLK_SRC_DEFAULT, /* select source clock */
+ .gpio_num = tx_pin,
+ .mem_block_symbols = 64, /* increase the block size can make the LED less flickering */
+ .resolution_hz = 10000000,
+ .trans_queue_depth = 4, /* set the number of transactions that can be pending in the background */
+ };
- if (en)
+ const rmt_simple_encoder_config_t simple_encoder_cfg =
{
- uint32_t item_block_len =
- rmt_ll_tx_get_mem_blocks(g_rmtdev_common.hal.regs, channel) * \
- RMT_MEM_ITEM_NUM;
-
- DEBUGASSERT(evt_thresh <= item_block_len);
+ .callback = encoder_callback
+ };
- flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock);
- rmt_ll_tx_set_limit(g_rmtdev_common.hal.regs, channel, evt_thresh);
- rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs,
- RMT_LL_EVENT_TX_THRES(channel), true);
- spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags);
- }
- else
+ ret = rmt_new_tx_channel(&tx_chan_config, &tx_chan);
+ if (ret != ESP_OK)
{
- flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock);
- rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs,
- RMT_LL_EVENT_TX_THRES(channel), false);
- spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags);
+ rmterr("Failed to Initialize RMT TX channel");
+ return NULL;
}
- return OK;
-}
-
-/****************************************************************************
- * Name: rmt_set_gpio
- *
- * Description:
- * This function configures the GPIO for the specified RMT (Remote Control)
- * channel and mode. It sets the GPIO to the appropriate input or output
- * function based on the mode, and configures the signal inversion if
- * necessary.
- *
- * Input Parameters:
- * channel - The RMT peripheral channel number.
- * mode - The mode of operation for the RMT channel (RMT_MODE_TX
- * for transmission, RMT_MODE_RX for reception).
- * gpio_num - The GPIO number to configure for the RMT channel.
- * invert_signal - A boolean indicating whether to invert the signal.
- *
- * Returned Value:
- * Returns OK on successful configuration of the GPIO.
- *
- ****************************************************************************/
-
-static int rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode,
- gpio_num_t gpio_num, bool invert_signal)
-{
- int ret;
+ ret = rmt_new_simple_encoder(&simple_encoder_cfg, &simple_encoder);
+ if (ret != ESP_OK)
+ {
+ rmterr("Failed to Initialize RMT Simple Encoder");
+ return NULL;
+ }
- DEBUGASSERT(channel < RMT_CHANNEL_MAX);
- DEBUGASSERT(mode < RMT_MODE_MAX);
- DEBUGASSERT((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) ||
- (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) &&
- (mode == RMT_MODE_TX)));
+ ret = rmt_enable(tx_chan);
+ if (ret != ESP_OK)
+ {
+ rmterr("Failed to Enable RMT TX channel");
+ return NULL;
+ }
- if (mode == RMT_MODE_TX)
+ priv = kmm_zalloc(sizeof(struct rmt_dev_lowerhalf_s));
+ if (priv)
{
- DEBUGASSERT(RMT_IS_TX_CHANNEL(channel));
- esp_configgpio(gpio_num, GPIO_OUT_FUNC);
- esp_gpio_matrix_out(
- gpio_num,
- rmt_periph_signals.groups[0].channels[channel].tx_sig,
- invert_signal, 0);
+ priv->ops = &g_rmtops;
+ priv->handle = tx_chan;
+ priv->encoder = simple_encoder;
}
else
{
- DEBUGASSERT(RMT_IS_RX_CHANNEL(channel));
- esp_configgpio(gpio_num, GPIO_IN_FUNC);
- esp_gpio_matrix_in(
- gpio_num,
- rmt_periph_signals.groups[0].channels[channel].rx_sig,
- invert_signal);
+ rmterr("ERROR: memory allocation failed\n");
+ return NULL;
}
- return OK;
-}
-
-/****************************************************************************
- * Name: rmt_is_channel_number_valid
- *
- * Description:
- * This function checks if the provided RMT channel number is valid for the
- * specified mode (TX or RX). For RX mode, it checks if the channel number
- * is within the range of valid RX channels and less than the maximum
- * channel number. For TX mode, it checks if the channel number is a valid
- * TX channel.
- *
- * Input Parameters:
- * channel - The RMT peripheral channel number.
- * mode - The mode of operation for the RMT channel (RMT_MODE_TX for
- * transmission, RMT_MODE_RX for reception).
- *
- * Returned Value:
- * Returns true if the channel number is valid, false otherwise.
- *
- ****************************************************************************/
-
-static bool rmt_is_channel_number_valid(rmt_channel_t channel, uint8_t mode)
-{
- if (mode == RMT_MODE_RX)
+ ret = rmt_get_channel_id(tx_chan, &channel_id);
+ if (ret != ESP_OK)
{
- return RMT_IS_RX_CHANNEL(channel) && (channel < RMT_CHANNEL_MAX);
+ rmterr("Failed to Get RMT RX channel ID");
+ return NULL;
}
- return (channel >= 0) && RMT_IS_TX_CHANNEL(channel);
+ priv->minor = channel_id + RMT_TX_CHANNEL_OFFSET_IN_GROUP;
+
+ return (struct rmt_dev_s *)priv;
}
/****************************************************************************
- * Name: rmt_internal_config
+ * Name: esp_rmt_rx_init
*
* Description:
- * This function configures the RMT peripheral with provided parameters.
- * It sets the mode (TX or RX), channel, GPIO number, memory block number,
- * clock divider, carrier frequency, and carrier enable flag. It also
- * configures the clock source, memory access, idle level, carrier
- * modulation, and other settings based on the mode and parameters.
+ * Initialize the selected RMT device in RX mode
*
* Input Parameters:
- * dev - Pointer to the RMT peripheral device structure.
- * rmt_param - Pointer to the structure containing the RMT channel
- * configuration parameters.
+ * rx_pin - The pin used for the RX channel
*
* Returned Value:
- * Returns OK on successful configuration of the RMT peripheral.
+ * Valid RMT device structure reference on success; NULL, otherwise.
*
****************************************************************************/
-static int rmt_internal_config(rmt_dev_t *dev,
- const struct rmt_channel_config_s *rmt_param)
+struct rmt_dev_s *esp_rmt_rx_init(int rx_pin)
{
- uint8_t mode = rmt_param->rmt_mode;
- uint8_t channel = rmt_param->channel;
- uint8_t gpio_num = rmt_param->gpio_num;
- uint8_t mem_cnt = rmt_param->mem_block_num;
- uint8_t clk_div = rmt_param->clk_div;
- uint32_t carrier_freq_hz = rmt_param->tx_config.carrier_freq_hz;
- bool carrier_en = rmt_param->tx_config.carrier_en;
- uint32_t rmt_source_clk_hz;
- irqstate_t flags;
-
- if (!rmt_is_channel_number_valid(channel, mode))
+ int channel_id;
+ esp_err_t esp_ret;
+ int ret;
+ struct rmt_dev_lowerhalf_s *priv;
+ rmt_channel_handle_t rx_chan = NULL;
+ rmt_rx_channel_config_t rx_channel_cfg =
{
- rmterr("Invalid channel number %u for %s mode!",
- channel, mode == RMT_MODE_TX ? "transmitter" : "receiver");
- return -EINVAL;
- }
+ .clk_src = RMT_CLK_SRC_DEFAULT,
+ .resolution_hz = 10000000,
+ .mem_block_symbols = SOC_RMT_MEM_WORDS_PER_CHANNEL, /* amount of RMT symbols that the channel can store at a time */
+ .gpio_num = rx_pin,
+ };
- DEBUGASSERT(mem_cnt + channel <= SOC_RMT_CHANNELS_PER_GROUP &&
- mem_cnt > 0);
- DEBUGASSERT(clk_div > 0);
+ rmt_rx_event_callbacks_t cbs =
+ {
+ .on_recv_done = rmt_rx_done_callback,
+ };
- if (mode == RMT_MODE_TX && carrier_en && carrier_freq_hz <= 0)
+ esp_ret = rmt_new_rx_channel(&rx_channel_cfg, &rx_chan);
+ if (esp_ret != ESP_OK)
{
- return -EINVAL;
+ rmterr("Failed to Initialize RMT RX channel");
+ return NULL;
}
- flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock);
-
- rmt_ll_enable_mem_access_nonfifo(dev, true);
-
- if (rmt_param->flags & RMT_CHANNEL_FLAGS_AWARE_DFS)
+ priv = kmm_zalloc(sizeof(struct rmt_dev_lowerhalf_s));
+ if (priv)
{
-#if SOC_RMT_SUPPORT_XTAL
-
- /* clock src: XTAL_CLK */
-
- esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_XTAL,
- ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
- &rmt_source_clk_hz);
- rmt_ll_set_group_clock_src(dev, channel,
- (rmt_clock_source_t)RMT_BASECLK_XTAL,
- 1, 0, 0);
-#elif SOC_RMT_SUPPORT_REF_TICK
-
- /* clock src: REF_CLK */
-
- esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_REF,
- ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
- &rmt_source_clk_hz);
- rmt_ll_set_group_clock_src(dev, channel,
- (rmt_clock_source_t)RMT_BASECLK_REF,
- 1, 0, 0);
-#else
-#error "No clock source is aware of DFS"
-#endif
+ priv->ops = &g_rmtops;
+ priv->handle = rx_chan;
}
else
{
- /* fallback to use default clock source */
-
- esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_DEFAULT,
- ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
- &rmt_source_clk_hz);
- rmt_ll_set_group_clock_src(dev, channel,
- (rmt_clock_source_t)RMT_BASECLK_DEFAULT,
- 1, 0, 0);
+ rmterr("ERROR: memory allocation failed\n");
+ return NULL;
}
- spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags);
-
-#if SOC_RMT_CHANNEL_CLK_INDEPENDENT
- g_rmt_source_clock_hz[channel] = rmt_source_clk_hz;
-#else
- if (g_rmt_source_clock_hz && rmt_source_clk_hz != g_rmt_source_clock_hz)
+ esp_ret = rmt_get_channel_id(rx_chan, &channel_id);
+ if (esp_ret != ESP_OK)
{
- rmterr("RMT clock source has been configured to %"PRIu32" by other "
- "channel, now reconfigure it to %"PRIu32"",
- g_rmt_source_clock_hz, rmt_source_clk_hz);
+ rmterr("Failed to Get RMT RX channel ID");
+ return NULL;
}
- g_rmt_source_clock_hz = rmt_source_clk_hz;
-#endif
- rmtinfo("rmt_source_clk_hz: %"PRIu32, rmt_source_clk_hz);
+ priv->minor = channel_id + RMT_RX_CHANNEL_OFFSET_IN_GROUP;
- if (mode == RMT_MODE_TX)
+ priv->recvsem = kmm_zalloc(sizeof(sem_t));
+ if (priv->recvsem == NULL)
{
- uint16_t carrier_duty_percent =
- rmt_param->tx_config.carrier_duty_percent;
- uint8_t carrier_level = rmt_param->tx_config.carrier_level;
- uint8_t idle_level = rmt_param->tx_config.idle_level;
-
- flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock);
- rmt_ll_tx_set_channel_clock_div(dev, channel, clk_div);
- rmt_ll_tx_set_mem_blocks(dev, channel, mem_cnt);
- rmt_ll_tx_reset_pointer(dev, channel);
- rmt_ll_tx_enable_loop(dev, channel, rmt_param->tx_config.loop_en);
-#if SOC_RMT_SUPPORT_TX_LOOP_COUNT
- if (rmt_param->tx_config.loop_en)
- {
- rmt_ll_tx_set_loop_count(dev, channel,
- rmt_param->tx_config.loop_count);
- }
-#endif
+ rmterr("ERROR: memory allocation failed\n");
+ return NULL;
+ }
- /* always enable tx ping-pong */
+ nxsem_init(priv->recvsem, 0, 0);
- rmt_ll_tx_enable_wrap(dev, channel, true);
-
- /* Set idle level */
-
- rmt_ll_tx_fix_idle_level(dev, channel, idle_level,
- rmt_param->tx_config.idle_output_en);
-
- /* Set carrier */
-
- rmt_ll_tx_enable_carrier_modulation(dev, channel, carrier_en);
- if (carrier_en)
- {
- uint32_t duty_div;
- uint32_t duty_h;
- uint32_t duty_l;
- duty_div = rmt_source_clk_hz / carrier_freq_hz;
- duty_h = duty_div * carrier_duty_percent / 100;
- duty_l = duty_div - duty_h;
- rmt_ll_tx_set_carrier_level(dev, channel, carrier_level);
- rmt_ll_tx_set_carrier_high_low_ticks(dev, channel, duty_h, duty_l);
- }
- else
- {
- rmt_ll_tx_set_carrier_level(dev, channel, 0);
- }
-
- spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags);
-
- rmtinfo("Rmt Tx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Carrier_Hz"
- " %"PRIu32"|Duty %u", channel, gpio_num, rmt_source_clk_hz,
- clk_div, carrier_freq_hz, carrier_duty_percent);
- }
- else if (RMT_MODE_RX == mode)
- {
- uint8_t filter_cnt = rmt_param->rx_config.filter_ticks_thresh;
- uint16_t threshold = rmt_param->rx_config.idle_threshold;
-
- flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock);
- rmt_ll_rx_set_channel_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel),
- clk_div);
- rmt_ll_rx_set_mem_blocks(dev, RMT_DECODE_RX_CHANNEL(channel), mem_cnt);
- rmt_ll_rx_reset_pointer(dev, RMT_DECODE_RX_CHANNEL(channel));
- rmt_ll_rx_set_mem_owner(dev, RMT_DECODE_RX_CHANNEL(channel),
- RMT_LL_MEM_OWNER_HW);
-
- /* Set idle threshold */
-
- rmt_ll_rx_set_idle_thres(dev, RMT_DECODE_RX_CHANNEL(channel),
- threshold);
-
- /* Set RX filter */
-
- rmt_ll_rx_set_filter_thres(dev, RMT_DECODE_RX_CHANNEL(channel),
- filter_cnt);
- rmt_ll_rx_enable_filter(dev, RMT_DECODE_RX_CHANNEL(channel),
- rmt_param->rx_config.filter_en);
-
-#ifdef SOC_RMT_SUPPORT_RX_PINGPONG
-
- /* always enable rx ping-pong */
-
- rmt_ll_rx_enable_wrap(dev, RMT_DECODE_RX_CHANNEL(channel), true);
-#endif
-
-#if SOC_RMT_SUPPORT_RX_DEMODULATION
- rmt_ll_rx_enable_carrier_demodulation(dev,
- RMT_DECODE_RX_CHANNEL(channel),
- rmt_param->rx_config.rm_carrier);
- if (rmt_param->rx_config.rm_carrier)
- {
- uint32_t duty_total;
- uint32_t duty_high;
- uint32_t ch_clk_div =
- rmt_ll_rx_get_channel_clock_div(dev,
- RMT_DECODE_RX_CHANNEL(channel));
- duty_total = rmt_source_clk_hz / \
- ch_clk_div / \
- rmt_param->rx_config.carrier_freq_hz;
- duty_high = duty_total *
- rmt_param->rx_config.carrier_duty_percent / 100;
-
- /* there could be residual in timing the carrier pulse, so double
- * enlarge the theoretical value.
- */
-
- rmt_ll_rx_set_carrier_high_low_ticks(
- dev, RMT_DECODE_RX_CHANNEL(channel), duty_high * 2,
- (duty_total - duty_high) * 2);
- rmt_ll_rx_set_carrier_level(dev, RMT_DECODE_RX_CHANNEL(channel),
- rmt_param->rx_config.carrier_level);
- }
-#endif
-
- spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags);
-
- rmtinfo("Rmt Rx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Threshold "
- "%u|Filter %u", channel, gpio_num, rmt_source_clk_hz, clk_div,
- threshold, filter_cnt);
- }
-
- return OK;
-}
-
-/****************************************************************************
- * Name: rmt_config
- *
- * Description:
- * This function configures the RMT channel with the provided parameters.
- * It enables the RMT module, sets the GPIO for the RMT channel, and
- * configures the RMT peripheral using the internal configuration function.
- *
- * Input Parameters:
- * rmt_param - Pointer to the structure containing the RMT channel
- * configuration parameters.
- *
- * Returned Value:
- * Returns OK on successful configuration of the RMT channel; a negated
- * errno value is returned on any failure.
- *
- ****************************************************************************/
-
-static int rmt_config(const struct rmt_channel_config_s *rmt_param)
-{
- int ret = ERROR;
-
- rmt_module_enable();
-
- rmt_set_gpio(rmt_param->channel, rmt_param->rmt_mode, rmt_param->gpio_num,
- rmt_param->flags & RMT_CHANNEL_FLAGS_INVERT_SIG);
-
- ret = rmt_internal_config(&RMT, rmt_param);
-
- return ret;
-}
-
-/****************************************************************************
- * Name: rmt_fill_memory
- *
- * Description:
- * This function fills the RMT memory with the provided items. It copies
- * the items from the source to the RMT memory for the specified channel,
- * starting at the specified memory offset.
- *
- * Input Parameters:
- * channel - The RMT peripheral channel number.
- * item - Pointer to the items to be copied to the RMT memory.
- * item_num - The number of items to be copied.
- * mem_offset - The memory offset at which to start copying.
- *
- * Returned Value:
- * None.
- *
- ****************************************************************************/
-
-static void IRAM_ATTR rmt_fill_memory(rmt_channel_t channel,
- const rmt_item32_t *item,
- uint16_t item_num,
- uint16_t mem_offset)
-{
- uint32_t *from = (uint32_t *)item;
- volatile uint32_t *to =
- (volatile uint32_t *)&RMTMEM.chan[channel].data32[0].val;
-
- to += mem_offset;
-
- while (item_num--)
- {
- *to++ = *from++;
- }
-}
-
-/****************************************************************************
- * Name: rmt_isr_register
- *
- * Description:
- * This function registers an interrupt service routine (ISR) for the RMT
- * peripheral. It allocates a CPU interrupt, attaches the ISR to the
- * interrupt, and returns the status of the operation.
- *
- * Input Parameters:
- * fn - Pointer to the ISR function.
- * arg - Pointer to the argument to be passed to the ISR.
- * intr_alloc_flags - Flags for the interrupt allocation.
- *
- * Returned Value:
- * Returns OK on successful registration of the ISR; a negated errno value
- * is returned on any failure.
- *
- ****************************************************************************/
-
-static int rmt_isr_register(int (*fn)(int, void *, void *), void *arg,
- int intr_alloc_flags)
-{
- int cpuint;
- int ret;
- int cpu = this_cpu();
-
- DEBUGASSERT(fn);
- DEBUGASSERT(g_rmtdev_common.rmt_driver_channels == 0);
-
- cpuint = esp_setup_irq(
-#ifndef CONFIG_ARCH_CHIP_ESP32S2
- cpu,
-#endif
- rmt_periph_signals.groups[0].irq, 1, ESP_CPUINT_LEVEL);
- if (cpuint < 0)
- {
- rmterr("Failed to allocate a CPU interrupt.\n");
- return -ENOMEM;
- }
-
- ret = irq_attach(rmt_periph_signals.groups[0].irq + XTENSA_IRQ_FIRSTPERIPH,
- fn, &g_rmtdev_common.hal);
- if (ret < 0)
- {
- rmterr("Couldn't attach IRQ to handler.\n");
- esp_teardown_irq(
-#ifndef CONFIG_ARCH_CHIP_ESP32S2
- cpu,
-#endif
- rmt_periph_signals.groups[0].irq, cpuint);
- return ret;
- }
-
- return ret;
-}
-
-/****************************************************************************
- * Name: rmt_driver_isr_default
- *
- * Description:
- * This function is the default interrupt service routine (ISR) for the RMT
- * peripheral. It handles TX end, TX threshold, RX end, RX threshold, loop
- * count, RX error, and TX error interrupts. For each interrupt type, it
- * checks the status, clears the interrupt, and performs the appropriate
- * actions based on the RMT object associated with the channel.
- *
- * Input Parameters:
- * irq - The interrupt request number.
- * context - Pointer to the interrupt context.
- * arg - Pointer to the argument to be passed to the ISR.
- *
- * Returned Value:
- * Returns OK after handling all active interrupts.
- *
- ****************************************************************************/
-
-static int IRAM_ATTR rmt_driver_isr_default(int irq, void *context,
- void *arg)
-{
- uint32_t status = 0;
- rmt_item32_t *addr = NULL;
- uint8_t channel = 0;
- rmt_hal_context_t *hal = (rmt_hal_context_t *)arg;
-
- /* Tx end interrupt */
-
- status = rmt_ll_get_tx_end_interrupt_status(hal->regs);
- while (status)
- {
- channel = __builtin_ffs(status) - 1;
- status &= ~(1 << channel);
- rmt_obj_t *p_rmt = p_rmt_obj[channel];
- if (p_rmt)
- {
- nxsem_post(&p_rmt->tx_sem);
- rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel);
- p_rmt->tx_data = NULL;
- p_rmt->tx_len_rem = 0;
- p_rmt->tx_offset = 0;
- p_rmt->tx_sub_len = 0;
- p_rmt->sample_cur = NULL;
- }
-
- rmt_ll_clear_interrupt_status(hal->regs,
- RMT_LL_EVENT_TX_DONE(channel));
- }
-
- /* Tx thres interrupt */
-
- status = rmt_ll_get_tx_thres_interrupt_status(hal->regs);
- while (status)
- {
- channel = __builtin_ffs(status) - 1;
- status &= ~(1 << channel);
- rmt_obj_t *p_rmt = p_rmt_obj[channel];
- if (p_rmt)
- {
- const rmt_item32_t *pdata = p_rmt->tx_data;
- size_t len_rem = p_rmt->tx_len_rem;
- rmt_idle_level_t idle_level =
- rmt_ll_tx_get_idle_level(hal->regs, channel);
- rmt_item32_t stop_data = (rmt_item32_t)
- {
- .level0 = idle_level,
- .duration0 = 0,
- };
-
- if (len_rem >= p_rmt->tx_sub_len)
- {
- rmt_fill_memory(channel, pdata, p_rmt->tx_sub_len,
- p_rmt->tx_offset);
- p_rmt->tx_data += p_rmt->tx_sub_len;
- p_rmt->tx_len_rem -= p_rmt->tx_sub_len;
- }
- else if (len_rem == 0)
- {
- rmt_fill_memory(channel, &stop_data, 1, p_rmt->tx_offset);
- }
- else
- {
- rmt_fill_memory(channel, pdata, len_rem, p_rmt->tx_offset);
- rmt_fill_memory(channel, &stop_data, 1,
- p_rmt->tx_offset + len_rem);
- p_rmt->tx_data += len_rem;
- p_rmt->tx_len_rem -= len_rem;
- }
-
- if (p_rmt->tx_offset == 0)
- {
- p_rmt->tx_offset = p_rmt->tx_sub_len;
- }
- else
- {
- p_rmt->tx_offset = 0;
- }
- }
-
- rmt_ll_clear_interrupt_status(hal->regs,
- RMT_LL_EVENT_TX_THRES(channel));
- }
-
- /* Rx end interrupt */
-
- status = rmt_ll_get_rx_end_interrupt_status(hal->regs);
- while (status)
- {
- channel = __builtin_ffs(status) - 1;
- status &= ~(1 << channel);
- rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
- if (p_rmt)
- {
- int item_len;
- rmt_ll_rx_enable(g_rmtdev_common.hal.regs, channel, false);
- item_len =
- rmt_ll_rx_get_memory_writer_offset(g_rmtdev_common.hal.regs,
- channel);
- rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel,
- RMT_LL_MEM_OWNER_SW);
- if (circbuf_is_init(&p_rmt->rx_buf))
- {
- int bytes;
-
- addr = (rmt_item32_t *)
- RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32;
-#ifdef SOC_RMT_SUPPORT_RX_PINGPONG
- if (item_len > p_rmt->rx_item_start_idx)
- {
- item_len = item_len - p_rmt->rx_item_start_idx;
- }
-
- /* Check for RX buffer max length */
-
- if ((p_rmt->rx_item_len + item_len) > \
- (p_rmt->rx_item_buf_size / 4))
- {
- int remaining_len = (p_rmt->rx_item_buf_size / 4) - \
- p_rmt->rx_item_len;
- rmterr("ERROR: RX buffer too small: %d items dropped\n",
- item_len - remaining_len);
- item_len = remaining_len;
- }
-
- memcpy((void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len),
- (void *)(addr + p_rmt->rx_item_start_idx),
- item_len * 4);
- p_rmt->rx_item_len += item_len;
- bytes = circbuf_write(&p_rmt->rx_buf,
- (void *)(p_rmt->rx_item_buf),
- p_rmt->rx_item_len * 4);
-#else
- bytes = circbuf_write(&p_rmt->rx_buf, (void *)addr,
- item_len * 4);
-#endif
- nxsem_post(&p_rmt->rx_sem);
- if (bytes < (item_len * 4))
- {
- rmterr("RMT RX BUFFER FULL");
- }
- }
- else
- {
- rmterr("RMT RX BUFFER ERROR");
- }
-
-#ifdef SOC_RMT_SUPPORT_RX_PINGPONG
- p_rmt->rx_item_start_idx = 0;
- p_rmt->rx_item_len = 0;
- memset((void *)p_rmt->rx_item_buf, 0, p_rmt->rx_item_buf_size);
-#endif
- rmt_ll_rx_reset_pointer(g_rmtdev_common.hal.regs, channel);
- rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel,
- RMT_LL_MEM_OWNER_HW);
- rmt_ll_rx_enable(g_rmtdev_common.hal.regs, channel, true);
- }
-
- rmt_ll_clear_interrupt_status(hal->regs,
- RMT_LL_EVENT_RX_DONE(channel));
- }
-
-#ifdef SOC_RMT_SUPPORT_RX_PINGPONG
-
- /* Rx thres interrupt */
-
- status = rmt_ll_get_rx_thres_interrupt_status(hal->regs);
- while (status)
- {
- int mem_item_size;
- int rx_thres_lim;
- int item_len;
-
- channel = __builtin_ffs(status) - 1;
- status &= ~(1 << channel);
- rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
- mem_item_size = rmt_ll_rx_get_mem_blocks(g_rmtdev_common.hal.regs,
- channel) * RMT_MEM_ITEM_NUM;
- rx_thres_lim = rmt_ll_rx_get_limit(g_rmtdev_common.hal.regs, channel);
- item_len = (p_rmt->rx_item_start_idx == 0) ? rx_thres_lim : \
- (mem_item_size - rx_thres_lim);
- if ((p_rmt->rx_item_len + item_len) > (p_rmt->rx_item_buf_size / 4))
- {
- int remaining_len = (p_rmt->rx_item_buf_size / 4) - \
- p_rmt->rx_item_len;
- rmterr("ERROR: RX buffer too small!\n");
- item_len = remaining_len;
- }
-
- rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel,
- RMT_LL_MEM_OWNER_SW);
- memcpy(
- (void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len),
- (void *)(RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32 \
- + p_rmt->rx_item_start_idx), item_len * 4);
- rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel,
- RMT_LL_MEM_OWNER_HW);
- p_rmt->rx_item_len += item_len;
- p_rmt->rx_item_start_idx += item_len;
- if (p_rmt->rx_item_start_idx >= mem_item_size)
- {
- p_rmt->rx_item_start_idx = 0;
- }
-
- rmt_ll_clear_interrupt_status(hal->regs,
- RMT_LL_EVENT_RX_THRES(channel));
- }
-#endif
-
-#if SOC_RMT_SUPPORT_TX_LOOP_COUNT
-
- /* loop count interrupt */
-
- status = rmt_ll_get_tx_loop_interrupt_status(hal->regs);
- while (status)
- {
- channel = __builtin_ffs(status) - 1;
- status &= ~(1 << channel);
- rmt_obj_t *p_rmt = p_rmt_obj[channel];
- if (p_rmt)
- {
- if (p_rmt->loop_autostop)
- {
-#ifndef SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP
-
- /* hardware doesn't support automatically stop output so driver
- * should stop output here (possibility already overshotted
- * several us).
- */
-
- rmt_ll_tx_stop(g_rmtdev_common.hal.regs, channel);
- rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel);
-#endif
- }
-
- nxsem_post(&p_rmt->tx_sem);
- }
-
- rmt_ll_clear_interrupt_status(hal->regs,
- RMT_LL_EVENT_TX_LOOP_END(channel));
- }
-#endif
-
- /* RX Err interrupt */
-
- status = rmt_ll_get_rx_err_interrupt_status(hal->regs);
- while (status)
- {
- channel = __builtin_ffs(status) - 1;
- status &= ~(1 << channel);
- rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
- if (p_rmt)
- {
- /* Reset the receiver's write/read addresses to prevent endless
- * err interrupts.
- */
-
- rmt_ll_rx_reset_pointer(g_rmtdev_common.hal.regs, channel);
- rmtinfo("RMT RX channel %d error", channel);
- rmtinfo("status: 0x%08" PRIx32 "",
- rmt_ll_rx_get_status_word(g_rmtdev_common.hal.regs,
- channel));
- }
-
- rmt_ll_clear_interrupt_status(hal->regs,
- RMT_LL_EVENT_RX_ERROR(channel));
- }
-
- /* TX Err interrupt */
-
- status = rmt_ll_get_tx_err_interrupt_status(hal->regs);
- while (status)
- {
- channel = __builtin_ffs(status) - 1;
- status &= ~(1 << channel);
- rmt_obj_t *p_rmt = p_rmt_obj[channel];
- if (p_rmt)
- {
- /* Reset the transmitter's write/read addresses to prevent
- * endless err interrupts.
- */
-
- rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel);
- rmtinfo("RMT TX channel %d error", channel);
- rmtinfo("status: 0x%08" PRIx32 "",
- rmt_ll_tx_get_status_word(g_rmtdev_common.hal.regs,
- channel));
- }
-
- rmt_ll_clear_interrupt_status(hal->regs,
- RMT_LL_EVENT_TX_ERROR(channel));
- }
-
- return OK;
-}
-
-/****************************************************************************
- * Name: rmt_driver_install
- *
- * Description:
- * This function installs the RMT driver for a specific channel. It
- * allocates memory for the RMT object, initializes the object properties,
- * and sets up the RX buffer if specified. It also registers the default
- * ISR if this is the first RMT channel using the driver, and resets the
- * RMT channel.
- *
- * Input Parameters:
- * channel - The RMT peripheral channel number.
- * rx_buf_size - The size of the RX buffer.
- * intr_alloc_flags - Flags for the interrupt allocation.
- *
- * Returned Value:
- * Returns OK on successful installation of the RMT driver; a negated errno
- * value is returned on any failure.
- *
- ****************************************************************************/
-
-static int rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size,
- int intr_alloc_flags)
-{
- DEBUGASSERT(channel < RMT_CHANNEL_MAX);
-
- int ret = OK;
-
- if (p_rmt_obj[channel])
- {
- rmtwarn("RMT driver already installed");
- return ERROR;
- }
-
-#if CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH
- if (intr_alloc_flags & ESP_INTR_FLAG_IRAM)
- {
- rmterr("ringbuf ISR functions in flash, but used in IRAM interrupt");
- return -EINVAL;
- }
-#endif
-
-#ifndef CONFIG_SPIRAM_USE_MALLOC
- p_rmt_obj[channel] = kmm_calloc(1, sizeof(rmt_obj_t));
-#else
- if (!(intr_alloc_flags & ESP_INTR_FLAG_IRAM))
- {
- p_rmt_obj[channel] = calloc(1, sizeof(rmt_obj_t));
- }
- else
- {
- p_rmt_obj[channel] = kmm_calloc(1, sizeof(rmt_obj_t));
- }
-#endif
-
- if (p_rmt_obj[channel] == NULL)
- {
- rmterr("RMT driver malloc error");
- return -ENOMEM;
- }
-
- p_rmt_obj[channel]->tx_len_rem = 0;
- p_rmt_obj[channel]->tx_data = NULL;
- p_rmt_obj[channel]->channel = channel;
- p_rmt_obj[channel]->tx_offset = 0;
- p_rmt_obj[channel]->tx_sub_len = 0;
- p_rmt_obj[channel]->wait_done = false;
- p_rmt_obj[channel]->loop_autostop = false;
-
-#ifndef CONFIG_SPIRAM_USE_MALLOC
- nxsem_init(&p_rmt_obj[channel]->tx_sem, 0, 0);
- nxsem_init(&p_rmt_obj[channel]->rx_sem, 0, 0);
-#endif
-
- nxsem_post(&p_rmt_obj[channel]->tx_sem);
-
- if (!circbuf_is_init(&p_rmt_obj[channel]->rx_buf) && rx_buf_size > 0)
- {
- circbuf_init(&p_rmt_obj[channel]->rx_buf, NULL, rx_buf_size);
- }
-
-#ifdef SOC_RMT_SUPPORT_RX_PINGPONG
- if (p_rmt_obj[channel]->rx_item_buf == NULL && rx_buf_size > 0)
- {
-# ifndef CONFIG_SPIRAM_USE_MALLOC
- p_rmt_obj[channel]->rx_item_buf = kmm_calloc(1, rx_buf_size);
-# else
- if (!(p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM))
- {
- p_rmt_obj[channel]->rx_item_buf = calloc(1, rx_buf_size);
- }
- else
- {
- p_rmt_obj[channel]->rx_item_buf = kmm_calloc(1, rx_buf_size);
- }
-
-# endif
- if (p_rmt_obj[channel]->rx_item_buf == NULL)
- {
- rmterr("RMT malloc fail");
- nxsem_destroy(&p_rmt_obj[channel]->rx_sem);
- return -ENOMEM;
- }
-
- p_rmt_obj[channel]->rx_item_buf_size = rx_buf_size;
- }
-#endif
-
- nxrmutex_lock(&(g_rmtdev_common.rmt_driver_isr_lock));
-
- if (g_rmtdev_common.rmt_driver_channels == 0)
- {
- /* first RMT channel using driver */
-
- ret = rmt_isr_register(rmt_driver_isr_default, &g_rmtdev_common.hal,
- intr_alloc_flags);
- }
-
- if (ret == OK)
- {
- g_rmtdev_common.rmt_driver_channels |= BIT(channel);
- }
-
- nxrmutex_unlock(&(g_rmtdev_common.rmt_driver_isr_lock));
-
- rmt_module_enable();
-
- if (RMT_IS_RX_CHANNEL(channel))
- {
- rmt_hal_rx_channel_reset(&g_rmtdev_common.hal,
- RMT_DECODE_RX_CHANNEL(channel));
- }
- else
- {
- rmt_hal_tx_channel_reset(&g_rmtdev_common.hal, channel);
- }
-
- return OK;
-}
-
-/****************************************************************************
- * Name: rmt_write_items
- *
- * Description:
- * This function writes items to the RMT memory for a specific channel. It
- * checks the validity of the parameters, calculates the memory blocks and
- * item lengths, and fills the memory with the items. If the number of
- * items is greater than the memory block length, it enables the TX
- * threshold interrupt and sets up the remaining items to be sent. If the
- * number of items is less than the memory block length, it fills the
- * remaining memory with idle level items. It then starts the TX process
- * and waits for it to finish if specified.
- *
- * Input Parameters:
- * channel - The RMT peripheral channel number.
- * rmt_item - Pointer to the items to be written to the RMT memory.
- * item_num - The number of items to be written.
- * wait_tx_done - Flag to indicate whether to wait for the TX process to
- * finish.
- *
- * Returned Value:
- * Returns OK on successful writing of the items to the RMT memory; a
- * negated errno value is returned on any failure.
- *
- ****************************************************************************/
-
-static int rmt_write_items(rmt_channel_t channel,
- const rmt_item32_t *rmt_item,
- int item_num,
- bool wait_tx_done)
-{
- DEBUGASSERT(RMT_IS_TX_CHANNEL(channel));
- DEBUGASSERT(p_rmt_obj[channel]);
- DEBUGASSERT(rmt_item);
- DEBUGASSERT(item_num > 0);
-
- uint32_t mem_blocks = rmt_ll_tx_get_mem_blocks(g_rmtdev_common.hal.regs,
- channel);
-
- DEBUGASSERT(mem_blocks + channel <= SOC_RMT_CHANNELS_PER_GROUP);
-#ifdef CONFIG_SPIRAM_USE_MALLOC
- if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM)
- {
- if (!esp_ptr_internal(rmt_item))
- {
- rmterr(RMT_PSRAM_BUFFER_WARN_STR);
- return ESP_ERR_INVALID_ARG;
- }
- }
-#endif
-
- rmt_obj_t *p_rmt = p_rmt_obj[channel];
- int item_block_len = mem_blocks * RMT_MEM_ITEM_NUM;
- int item_sub_len = mem_blocks * RMT_MEM_ITEM_NUM / 2;
- int len_rem = item_num;
- nxsem_wait(&p_rmt->tx_sem);
-
- /* fill the memory block first */
-
- if (item_num >= item_block_len)
- {
- rmt_fill_memory(channel, rmt_item, item_block_len, 0);
- len_rem -= item_block_len;
- rmt_set_tx_loop_mode(channel, false);
- rmt_set_tx_thr_intr_en(channel, 1, item_sub_len);
- p_rmt->tx_data = rmt_item + item_block_len;
- p_rmt->tx_len_rem = len_rem;
- p_rmt->tx_offset = 0;
- p_rmt->tx_sub_len = item_sub_len;
- }
- else
- {
- rmt_idle_level_t idle_level;
- rmt_fill_memory(channel, rmt_item, len_rem, 0);
- idle_level = rmt_ll_tx_get_idle_level(g_rmtdev_common.hal.regs,
- channel);
- rmt_item32_t stop_data = (rmt_item32_t)
- {
- .level0 = idle_level,
- .duration0 = 0,
- };
-
- rmt_fill_memory(channel, &stop_data, 1, len_rem);
- p_rmt->tx_len_rem = 0;
- }
-
- rmt_tx_start(channel, true);
- p_rmt->wait_done = wait_tx_done;
- if (wait_tx_done)
- {
- /* wait loop done */
-
- if (rmt_ll_tx_is_loop_enabled(g_rmtdev_common.hal.regs, channel))
- {
-#if SOC_RMT_SUPPORT_TX_LOOP_COUNT
- nxsem_wait(&p_rmt->tx_sem);
- nxsem_post(&p_rmt->tx_sem);
-#endif
- }
- else
- {
- /* wait tx end */
-
- nxsem_wait(&p_rmt->tx_sem);
- nxsem_post(&p_rmt->tx_sem);
- }
- }
-
- return OK;
-}
-
-/****************************************************************************
- * Name: esp_rmt_read
- *
- * Description:
- * This function reads data from the RMT device.
- * It starts the RMT module in receiving mode for a specific channel and
- * checks for any errors. If an error occurs during the start of the RMT
- * module, it returns the error code. Please note that this function
- * starts the receiver, but the actual data is read from the ring buffer
- * by the upper half driver.
- *
- * Input Parameters:
- * dev - Pointer to the RMT device structure.
- * buffer - Pointer to the buffer where the read data should be stored.
- * buflen - The maximum amount of data to be read.
- *
- * Returned Value:
- * Returns the number of bytes read from the RMT device; a negated errno
- * value is returned on any failure.
- *
- ****************************************************************************/
-
-static ssize_t esp_rmt_read(struct rmt_dev_s *dev, char *buffer,
- size_t buflen)
-{
- struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev;
- rmt_mode_t mode = priv->mode;
- int channel = priv->minor;
- int ret;
- ssize_t nread;
-
- if (mode != RMT_MODE_RX)
+ priv->circbuf = kmm_zalloc(sizeof(struct circbuf_s));
+ if (priv->circbuf == NULL)
{
- rmterr("ERROR: RMT channel %d is not in RX mode\n", channel);
- return -EINVAL;
- }
-
- DEBUGASSERT((buflen % 4) == 0);
-
- if ((buflen / 4) > (CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE / 4))
- {
- rmtwarn("WARN: RMT RX buffer (%d bytes) is smaller than requested "
- "read bytes (%d bytes). A partial read will take place!\n",
- CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE,
- buflen);
- }
-
-#ifndef SOC_RMT_SUPPORT_RX_PINGPONG
- if ((buflen / 4) > RMT_MEM_ITEM_NUM)
- {
- rmtwarn("WARN: RMT RX channel is able to receive up to "
- "%d RMT items (%d bytes)!",
- RMT_MEM_ITEM_NUM, RMT_MEM_ITEM_NUM * 4);
- }
-#endif
-
- ret = rmt_rx_start(channel, true);
- if (ret < 0)
- {
- rmterr("ERROR: rmt_rx_start failed: %d\n", ret);
- return (ssize_t)ret;
+ rmterr("ERROR: memory allocation failed\n");
+ return NULL;
}
- return (ssize_t)ret;
-}
-
-/****************************************************************************
- * Name: esp_rmt_write
- *
- * Description:
- * This function writes data to the RMT memory for a specific channel. It
- * asserts that the length of the data is a multiple of 4, then calls the
- * rmt_write_items function to write the items to the RMT memory.
- *
- * Input Parameters:
- * dev - Pointer to the RMT device structure.
- * buffer - Pointer to the data to be written to the RMT memory.
- * buflen - The length of the data to be written.
- *
- * Returned Value:
- * Returns the number of items written to the RMT memory.
- *
- ****************************************************************************/
-
-static ssize_t esp_rmt_write(struct rmt_dev_s *dev, const char *buffer,
- size_t buflen)
-{
- struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev;
- rmt_mode_t mode = priv->mode;
- int channel = priv->minor;
- int ret;
- struct timespec timeout;
-
- if (mode != RMT_MODE_TX)
+ ret = circbuf_init(priv->circbuf, NULL,
+ CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE);
+ if (ret != OK)
{
- rmterr("ERROR: RMT channel %d is not in TX mode\n", channel);
- return -EINVAL;
+ rmterr("Failed to Initialize RMT RX buffer");
+ return NULL;
}
- DEBUGASSERT((buflen % 4) == 0);
-
- ret = rmt_write_items(channel, (const rmt_item32_t *)buffer,
- (buflen / 4), true);
-
- if (ret < 0)
+ esp_ret = rmt_rx_register_event_callbacks(rx_chan, &cbs, priv);
+ if (esp_ret != ESP_OK)
{
- rmterr("ERROR: rmt_write_items failed: %d\n", ret);
- return (ssize_t)0;
+ rmterr("Failed to Register RMT RX event callbacks");
+ return NULL;
}
- return (ssize_t)buflen;
-}
-
-/****************************************************************************
- * Name: esp_rmtinitialize
- *
- * Description:
- * This function initializes the specified RMT (Remote Control) device
- * with the provided configuration.
- *
- * Input Parameters:
- * config - A structure containing the configuration settings for the
- * RMT channel to be initialized.
- *
- * Returned Value:
- * On success, this function returns a valid pointer to the RMT device
- * structure. If the initialization fails, it returns NULL.
- *
- ****************************************************************************/
-
-static struct rmt_dev_s
- *esp_rmtinitialize(struct rmt_channel_config_s config)
-{
- struct rmt_dev_lowerhalf_s *priv;
- int ret;
-#ifdef CONFIG_RMT_LOOP_TEST_MODE
- uint8_t channel;
-#endif
-
-#if (CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE % 4) != 0
-# error "CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE must be a multiple of 4"
-#endif
-
- priv = kmm_zalloc(sizeof(struct rmt_dev_lowerhalf_s));
- if (priv)
- {
- ret = rmt_config(&config);
- if (ret < 0)
- {
- rmterr("ERROR: rmt_config failed: %d\n", ret);
- return NULL;
- }
-
-#ifdef CONFIG_RMT_LOOP_TEST_MODE
- if (config.rmt_mode == RMT_MODE_TX)
- {
- if (g_tx_channel != RMT_CHANNEL_MAX)
- {
- rmterr("ERROR: only one TX channel can be used in loop test "
- "mode\n");
- PANIC();
- }
-
- g_tx_channel = config.channel;
- }
- else
- {
- if (g_rx_channel != RMT_CHANNEL_MAX)
- {
- rmterr("ERROR: only one RX channel can be used in loop test "
- "mode\n");
- PANIC();
- }
-
- g_rx_channel = config.channel;
- }
-
- if (g_rx_channel != RMT_CHANNEL_MAX && g_tx_channel != RMT_CHANNEL_MAX)
- {
- esp_configgpio(config.gpio_num, GPIO_OUT_FUNC | GPIO_IN_FUNC);
- esp_gpio_matrix_out(config.gpio_num,
- RMT_SIG_OUT0_IDX + g_tx_channel,
- 0, 0);
- esp_gpio_matrix_in(config.gpio_num,
- RMT_SIG_IN0_IDX + g_rx_channel,
- 0);
- rmtwarn("RX channel %d and TX channel %d are used in loop test "
- "mode\n", g_rx_channel, g_tx_channel);
- }
-#endif
-
- ret = rmt_driver_install(config.channel,
- config.rmt_mode == RMT_MODE_RX ? \
- CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE : 0, 0);
- if (ret < 0)
- {
- rmterr("ERROR: rmt_driver_install failed: %d\n", ret);
- return NULL;
- }
-
- priv->ops = &g_rmtops;
- priv->recvsem = &p_rmt_obj[config.channel]->rx_sem;
- priv->circbuf = &p_rmt_obj[config.channel]->rx_buf;
- priv->minor = config.channel;
-
- priv->common = &g_rmtdev_common;
- priv->mode = config.rmt_mode;
- }
- else
+ esp_ret = rmt_enable(rx_chan);
+ if (esp_ret != ESP_OK)
{
- rmterr("ERROR: memory allocation failed\n");
+ rmterr("Failed to Enable RMT RX channel");
return NULL;
}
return (struct rmt_dev_s *)priv;
}
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: esp_rmt_tx_init
- *
- * Description:
- * Initialize the selected RMT device in TX mode
- *
- * Input Parameters:
- * ch - The RMT's channel that will be used
- * pin - The pin used for the TX channel
- *
- * Returned Value:
- * Valid RMT device structure reference on success; NULL, otherwise.
- *
- ****************************************************************************/
-
-struct rmt_dev_s *esp_rmt_tx_init(int ch, int pin)
-{
- struct rmt_channel_config_s config = RMT_DEFAULT_CONFIG_TX(pin, ch);
-
- return esp_rmtinitialize(config);
-}
-
-/****************************************************************************
- * Name: esp_rmt_rx_init
- *
- * Description:
- * Initialize the selected RMT device in RC mode
- *
- * Input Parameters:
- * ch - The RMT's channel that will be used
- * pin - The pin used for the RX channel
- *
- * Returned Value:
- * Valid RMT device structure reference on success; NULL, otherwise.
- *
- ****************************************************************************/
-
-struct rmt_dev_s *esp_rmt_rx_init(int ch, int pin)
-{
- struct rmt_channel_config_s config = RMT_DEFAULT_CONFIG_RX(pin, ch);
-
- return esp_rmtinitialize(config);
-}
-
#endif
diff --git a/arch/xtensa/src/common/espressif/esp_rmt.h b/arch/xtensa/src/common/espressif/esp_rmt.h
index a58988a73d7..943db6a88ba 100644
--- a/arch/xtensa/src/common/espressif/esp_rmt.h
+++ b/arch/xtensa/src/common/espressif/esp_rmt.h
@@ -20,8 +20,8 @@
*
****************************************************************************/
-#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_H
-#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_H
+#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_NEW_H
+#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_NEW_H
/****************************************************************************
* Included Files
@@ -68,38 +68,36 @@ extern "C"
#if defined(CONFIG_ESP_RMT)
/****************************************************************************
- * Name: esp_rmt_tx_init
+ * Name: esp_rmt_rx_init
*
* Description:
- * Initialize the selected RMT device in TX mode
+ * Initialize the selected RMT device in RX mode
*
* Input Parameters:
- * ch - The RMT's channel that will be used
- * pin - The pin used for the TX channel
+ * rx_pin - The pin used for the RX channel
*
* Returned Value:
* Valid RMT device structure reference on success; NULL, otherwise.
*
****************************************************************************/
-struct rmt_dev_s *esp_rmt_tx_init(int ch, int pin);
+struct rmt_dev_s *esp_rmt_rx_init(int rx_pin);
/****************************************************************************
- * Name: esp_rmt_rx_init
+ * Name: esp_rmt_tx_init
*
* Description:
- * Initialize the selected RMT device in RC mode
+ * Initialize the selected RMT device in TX mode
*
* Input Parameters:
- * ch - The RMT's channel that will be used
- * pin - The pin used for the RX channel
+ * tx_pin - The pin used for the TX channel
*
* Returned Value:
* Valid RMT device structure reference on success; NULL, otherwise.
*
****************************************************************************/
-struct rmt_dev_s *esp_rmt_rx_init(int ch, int pin);
+struct rmt_dev_s *esp_rmt_tx_init(int tx_pin);
#endif
@@ -108,4 +106,4 @@ struct rmt_dev_s *esp_rmt_rx_init(int ch, int pin);
#endif
#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_H */
+#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_NEW_H */
diff --git a/arch/xtensa/src/common/espressif/esp_rtc.c b/arch/xtensa/src/common/espressif/esp_rtc.c
new file mode 100644
index 00000000000..63ea7a54f65
--- /dev/null
+++ b/arch/xtensa/src/common/espressif/esp_rtc.c
@@ -0,0 +1,895 @@
+/****************************************************************************
+ * arch/xtensa/src/common/espressif/esp_rtc.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <assert.h>
+#include <debug.h>
+#include <errno.h>
+#include <stdbool.h>
+#include <string.h>
+#include <sys/types.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/timers/rtc.h>
+
+#include "clock/clock.h"
+
+#include "esp_timer_adapter.h"
+#include "esp_rtc.h"
+#include "esp_rtc_time.h"
+#include "xtensa.h"
+
+#include "esp_attr.h"
+#include "soc/rtc.h"
+
+#include "rom/rtc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The magic data for the struct esp_rtc_backup_s that is in RTC slow
+ * memory.
+ */
+
+#define MAGIC_RTC_SAVE (UINT64_C(0x11223344556677))
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_DRIVER
+
+#ifdef CONFIG_RTC_ALARM
+struct alm_cbinfo_s
+{
+ struct esp_hr_timer_s *alarm_hdl; /* Timer id point to here */
+ rtc_alarm_callback_t ac_cb; /* Client callback function */
+ volatile void *ac_arg; /* Argument to pass with the callback function */
+ uint64_t deadline_us;
+ uint8_t index;
+};
+#endif /* CONFIG_RTC_ALARM */
+
+/* This is the private type for the RTC state. It must be cast compatible
+ * with struct rtc_lowerhalf_s.
+ */
+
+struct esp_rtc_lowerhalf_s
+{
+ /* This is the contained reference to the read-only, lower-half
+ * operations vtable (which may lie in FLASH or ROM)
+ */
+
+ const struct rtc_ops_s *ops;
+#ifdef CONFIG_RTC_ALARM
+ /* Alarm callback information */
+
+ struct alm_cbinfo_s alarmcb[CONFIG_RTC_NALARMS];
+#endif /* CONFIG_RTC_ALARM */
+
+ spinlock_t lock;
+};
+
+#endif/* CONFIG_RTC_DRIVER */
+
+struct esp_rtc_backup_s
+{
+ uint64_t magic;
+ int64_t offset; /* Offset time from RTC HW value */
+ int64_t reserved0;
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Prototypes for static methods in struct rtc_ops_s */
+
+#ifdef CONFIG_RTC_DRIVER
+static int esp_rtc_rdtime(struct rtc_lowerhalf_s *lower,
+ struct rtc_time *rtctime);
+static int esp_rtc_settime(struct rtc_lowerhalf_s *lower,
+ const struct rtc_time *rtctime);
+static bool esp_rtc_havesettime(struct rtc_lowerhalf_s *lower);
+
+#ifdef CONFIG_RTC_ALARM
+static void IRAM_ATTR rtc_hr_timer_cb(void *arg);
+static int esp_rtc_setalarm(struct rtc_lowerhalf_s *lower,
+ const struct lower_setalarm_s *alarminfo);
+static int esp_rtc_setrelative(struct rtc_lowerhalf_s *lower,
+ const struct lower_setrelative_s *alarminfo);
+static int esp_rtc_cancelalarm(struct rtc_lowerhalf_s *lower,
+ int alarmid);
+static int esp_rtc_rdalarm(struct rtc_lowerhalf_s *lower,
+ struct lower_rdalarm_s *alarminfo);
+#endif /* CONFIG_RTC_ALARM */
+#endif /* CONFIG_RTC_DRIVER */
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_DRIVER
+/* RTC driver operations */
+
+static const struct rtc_ops_s g_rtc_ops =
+{
+ .rdtime = esp_rtc_rdtime,
+ .settime = esp_rtc_settime,
+ .havesettime = esp_rtc_havesettime,
+#ifdef CONFIG_RTC_ALARM
+ .setalarm = esp_rtc_setalarm,
+ .setrelative = esp_rtc_setrelative,
+ .cancelalarm = esp_rtc_cancelalarm,
+ .rdalarm = esp_rtc_rdalarm,
+#endif /* CONFIG_RTC_ALARM */
+};
+
+/* RTC device state */
+
+static struct esp_rtc_lowerhalf_s g_rtc_lowerhalf =
+{
+ .ops = &g_rtc_ops
+};
+
+/* Flag for tracking HR Timer enable status */
+
+static bool g_hr_timer_enabled = false;
+
+#endif /* CONFIG_RTC_DRIVER */
+
+/* Saved data for persistent RTC time */
+
+static RTC_DATA_ATTR struct esp_rtc_backup_s g_rtc_saved_data;
+static struct esp_rtc_backup_s *g_rtc_save;
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+volatile bool g_rtc_enabled = false;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp_rtc_set_boot_time
+ *
+ * Description:
+ * Set time to RTC register to replace the original boot time.
+ *
+ * Input Parameters:
+ * time_us - set time in microseconds.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+static void IRAM_ATTR esp_rtc_set_boot_time(uint64_t time_us)
+{
+ putreg32((uint32_t)(time_us & UINT32_MAX), RTC_BOOT_TIME_LOW_REG);
+ putreg32((uint32_t)(time_us >> 32), RTC_BOOT_TIME_HIGH_REG);
+}
+
+/****************************************************************************
+ * Name: esp_rtc_get_boot_time
+ *
+ * Description:
+ * Get time of RTC register to indicate the original boot time.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * Boot time in microseconds.
+ *
+ ****************************************************************************/
+
+static uint64_t IRAM_ATTR esp_rtc_get_boot_time(void)
+{
+ return ((uint64_t)getreg32(RTC_BOOT_TIME_LOW_REG))
+ + (((uint64_t)getreg32(RTC_BOOT_TIME_HIGH_REG)) << 32);
+}
+
+/****************************************************************************
+ * Name: rtc_hr_timer_cb
+ *
+ * Description:
+ * Callback to be called upon HR-Timer expiration.
+ *
+ * Input Parameters:
+ * arg - Information about the HR-Timer configuration.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_RTC_DRIVER) && defined(CONFIG_RTC_ALARM)
+static void IRAM_ATTR rtc_hr_timer_cb(void *arg)
+{
+ struct alm_cbinfo_s *cbinfo = (struct alm_cbinfo_s *)arg;
+ rtc_alarm_callback_t cb;
+ void *cb_arg;
+ int alminfo_id;
+
+ DEBUGASSERT(cbinfo != NULL);
+
+ alminfo_id = cbinfo->index;
+
+ if (cbinfo->ac_cb != NULL)
+ {
+ /* Alarm callback */
+
+ cb = cbinfo->ac_cb;
+ cb_arg = (void *)cbinfo->ac_arg;
+ cbinfo->ac_cb = NULL;
+ cbinfo->ac_arg = NULL;
+ cbinfo->deadline_us = 0;
+ cb(cb_arg, alminfo_id);
+ }
+}
+#endif /* CONFIG_RTC_DRIVER */
+
+/****************************************************************************
+ * Name: esp_rtc_rdtime
+ *
+ * Description:
+ * Return the current RTC time.
+ *
+ * Input Parameters:
+ * lower - A reference to RTC lower half driver state structure.
+ * rcttime - The location in which to return the current RTC time.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on any failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_DRIVER
+
+#ifdef CONFIG_RTC_HIRES
+static int esp_rtc_rdtime(struct rtc_lowerhalf_s *lower,
+ struct rtc_time *rtctime)
+{
+ struct timespec ts;
+ int ret;
+
+ /* Get the higher resolution time */
+
+ ret = up_rtc_gettime(&ts);
+ if (ret < 0)
+ {
+ goto errout;
+ }
+
+ /* Convert the one second epoch time to a struct tmThis operation
+ * depends on the fact that struct rtc_time and struct tm are cast
+ * compatible.
+ */
+
+ if (!gmtime_r(&ts.tv_sec, (struct tm *)rtctime))
+ {
+ ret = -get_errno();
+ goto errout;
+ }
+
+ return OK;
+
+errout:
+ rtcerr("Failed to get RTC time: %d\n", ret);
+ return ret;
+}
+
+#else /* !CONFIG_RTC_HIRES */
+
+static int esp_rtc_rdtime(struct rtc_lowerhalf_s *lower,
+ struct rtc_time *rtctime)
+{
+ time_t timer;
+
+ /* The resolution of time is only 1 second */
+
+ timer = up_rtc_time();
+
+ /* Convert the one second epoch time to a struct tm */
+
+ if (gmtime_r(&timer, (struct tm *)rtctime) == 0)
+ {
+ int errcode = get_errno();
+ DEBUGASSERT(errcode > 0);
+
+ rtcerr("gmtime_r failed: %d\n", errcode);
+ return -errcode;
+ }
+
+ return OK;
+}
+#endif /* CONFIG_RTC_HIRES */
+
+#endif /* CONFIG_RTC_DRIVER */
+
+/****************************************************************************
+ * Name: esp_rtc_settime
+ *
+ * Description:
+ * Implement the settime() method of the RTC driver interface.
+ *
+ * Input Parameters:
+ * lower - A reference to RTC lower half driver state structure.
+ * rcttime - The new time to set.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on any failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_DRIVER
+static int esp_rtc_settime(struct rtc_lowerhalf_s *lower,
+ const struct rtc_time *rtctime)
+{
+ struct timespec ts;
+
+ /* Convert the struct rtc_time to a time_t. Here we assume that struct
+ * rtc_time is cast compatible with struct tm.
+ */
+
+ ts.tv_sec = mktime((struct tm *)rtctime);
+ ts.tv_nsec = 0;
+
+ /* Now set the time (with a accuracy of seconds) */
+
+ return up_rtc_settime(&ts);
+}
+#endif /* CONFIG_RTC_DRIVER */
+
+/****************************************************************************
+ * Name: esp_rtc_havesettime
+ *
+ * Description:
+ * Implement the havesettime() method of the RTC driver interface.
+ *
+ * Input Parameters:
+ * lower - A reference to RTC lower half driver state structure.
+ *
+ * Returned Value:
+ * True if RTC date-time have been previously set, false otherwise.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_DRIVER
+static bool esp_rtc_havesettime(struct rtc_lowerhalf_s *lower)
+{
+ return esp_rtc_get_boot_time() != 0;
+}
+#endif /* CONFIG_RTC_DRIVER */
+
+/****************************************************************************
+ * Name: esp_rtc_setalarm
+ *
+ * Description:
+ * Set a new alarm. This function implements the setalarm() method of the
+ * RTC driver interface.
+ *
+ * Input Parameters:
+ * lower - A reference to RTC lower half driver state structure.
+ * alarminfo - Provided information needed to set the alarm.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on any failure.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_RTC_DRIVER) && defined(CONFIG_RTC_ALARM)
+static int esp_rtc_setalarm_nolock(struct rtc_lowerhalf_s *lower,
+ const struct lower_setalarm_s *alarminfo)
+{
+ struct esp_rtc_lowerhalf_s *priv = (struct esp_rtc_lowerhalf_s *)lower;
+ struct alm_cbinfo_s *cbinfo;
+ uint64_t timeout;
+ int id;
+
+ DEBUGASSERT(priv != NULL);
+ DEBUGASSERT(alarminfo != NULL);
+
+ timeout = mktime((struct tm *)&alarminfo->time);
+
+ /* Set the alarm in RT-Timer */
+
+ id = alarminfo->id;
+ cbinfo = &priv->alarmcb[id];
+
+ if (cbinfo->ac_cb != NULL)
+ {
+ return -EBUSY;
+ }
+
+ /* Create the RT-Timer alarm */
+
+ if (cbinfo->alarm_hdl == NULL)
+ {
+ struct esp_hr_timer_args_s hr_timer_args;
+ int ret;
+
+ cbinfo->index = id;
+ hr_timer_args.arg = cbinfo;
+ hr_timer_args.callback = rtc_hr_timer_cb;
+
+ ret = esp_hr_timer_create(&hr_timer_args, &cbinfo->alarm_hdl);
+ if (ret < 0)
+ {
+ rtcerr("Failed to create HR Timer=%d\n", ret);
+
+ return ret;
+ }
+ }
+
+ cbinfo->ac_cb = alarminfo->cb;
+ cbinfo->ac_arg = alarminfo->priv;
+ cbinfo->deadline_us = timeout * USEC_PER_SEC;
+
+ rtcinfo("Starting alarm ID %d\n", id);
+
+ esp_hr_timer_start(cbinfo->alarm_hdl, cbinfo->deadline_us, false);
+
+ return OK;
+}
+
+static int esp_rtc_setalarm(struct rtc_lowerhalf_s *lower,
+ const struct lower_setalarm_s *alarminfo)
+{
+ struct esp_rtc_lowerhalf_s *priv = (struct esp_rtc_lowerhalf_s *)lower;
+ irqstate_t flags;
+ int ret;
+
+ flags = spin_lock_irqsave(&priv->lock);
+ ret = esp_rtc_setalarm_nolock(lower, alarminfo);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return ret;
+}
+#endif /* CONFIG_RTC_DRIVER && CONFIG_RTC_ALARM */
+
+/****************************************************************************
+ * Name: esp_rtc_setrelative
+ *
+ * Description:
+ * Set a new alarm relative to the current time. This function implements
+ * the setrelative() method of the RTC driver interface.
+ *
+ * Input Parameters:
+ * lower - A reference to RTC lower half driver state structure.
+ * alarminfo - Provided information needed to set the alarm.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on any failure.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_RTC_DRIVER) && defined(CONFIG_RTC_ALARM)
+static int esp_rtc_setrelative(struct rtc_lowerhalf_s *lower,
+ const struct lower_setrelative_s *alarminfo)
+{
+ struct esp_rtc_lowerhalf_s *priv = (struct esp_rtc_lowerhalf_s *)lower;
+ struct lower_setalarm_s setalarm;
+ time_t seconds;
+ int ret = -EINVAL;
+ irqstate_t flags;
+
+ DEBUGASSERT(lower != NULL && alarminfo != NULL);
+
+ if (alarminfo->reltime > 0)
+ {
+ flags = spin_lock_irqsave(&priv->lock);
+
+ seconds = alarminfo->reltime;
+ gmtime_r(&seconds, (struct tm *)&setalarm.time);
+
+ /* The set the alarm using this absolute time */
+
+ setalarm.id = alarminfo->id;
+ setalarm.cb = alarminfo->cb;
+ setalarm.priv = alarminfo->priv;
+ ret = esp_rtc_setalarm_nolock(lower, &setalarm);
+
+ spin_unlock_irqrestore(&priv->lock, flags);
+ }
+
+ return ret;
+}
+#endif /* CONFIG_RTC_DRIVER && CONFIG_RTC_ALARM */
+
+/****************************************************************************
+ * Name: esp_rtc_cancelalarm
+ *
+ * Description:
+ * Cancel the current alarm. This function implements the cancelalarm()
+ * method of the RTC driver interface.
+ *
+ * Input Parameters:
+ * lower - A reference to RTC lower half driver state structure.
+ * alarmid - ID of the alarm to be cancelled.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on any failure.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_RTC_DRIVER) && defined(CONFIG_RTC_ALARM)
+static int esp_rtc_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid)
+{
+ struct esp_rtc_lowerhalf_s *priv;
+ struct alm_cbinfo_s *cbinfo;
+ irqstate_t flags;
+
+ DEBUGASSERT(lower != NULL);
+
+ priv = (struct esp_rtc_lowerhalf_s *)lower;
+
+ /* Set the alarm in hardware and enable interrupts */
+
+ cbinfo = &priv->alarmcb[alarmid];
+
+ if (cbinfo->ac_cb == NULL)
+ {
+ return -ENODATA;
+ }
+
+ flags = spin_lock_irqsave(&priv->lock);
+
+ /* Stop and delete the alarm */
+
+ rtcinfo("Cancelling alarm ID %d\n", alarmid);
+
+ esp_hr_timer_stop(cbinfo->alarm_hdl);
+ esp_hr_timer_delete(cbinfo->alarm_hdl);
+
+ cbinfo->ac_cb = NULL;
+ cbinfo->deadline_us = 0;
+ cbinfo->alarm_hdl = NULL;
+
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return OK;
+}
+#endif /* CONFIG_RTC_DRIVER && CONFIG_RTC_ALARM */
+
+/****************************************************************************
+ * Name: esp_rtc_rdalarm
+ *
+ * Description:
+ * Query the RTC alarm.
+ *
+ * Input Parameters:
+ * lower - A reference to RTC lower half driver state structure.
+ * alarminfo - Provided information needed to query the alarm.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on any failure.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_RTC_DRIVER) && defined(CONFIG_RTC_ALARM)
+static int esp_rtc_rdalarm(struct rtc_lowerhalf_s *lower,
+ struct lower_rdalarm_s *alarminfo)
+{
+ struct esp_rtc_lowerhalf_s *priv;
+ struct timespec ts;
+ struct alm_cbinfo_s *cbinfo;
+ irqstate_t flags;
+
+ DEBUGASSERT(lower != NULL);
+ DEBUGASSERT(alarminfo != NULL);
+ DEBUGASSERT(alarminfo->time != NULL);
+
+ priv = (struct esp_rtc_lowerhalf_s *)lower;
+
+ flags = spin_lock_irqsave(&priv->lock);
+
+ /* Get the alarm according to the alarm ID */
+
+ cbinfo = &priv->alarmcb[alarminfo->id];
+
+ ts.tv_sec = (esp_hr_timer_time_us() + g_rtc_save->offset +
+ cbinfo->deadline_us) / USEC_PER_SEC;
+ ts.tv_nsec = ((esp_hr_timer_time_us() + g_rtc_save->offset +
+ cbinfo->deadline_us) % USEC_PER_SEC) * NSEC_PER_USEC;
+
+ localtime_r((const time_t *)&ts.tv_sec,
+ (struct tm *)alarminfo->time);
+
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return OK;
+}
+#endif /* CONFIG_RTC_DRIVER && CONFIG_RTC_ALARM */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_rtc_time
+ *
+ * Description:
+ * Get the current time in seconds. This is similar to the standard time()
+ * function. This interface is only required if the low-resolution
+ * RTC/counter hardware implementation is selected. It is only used by the
+ * RTOS during initialization to set up the system time when CONFIG_RTC is
+ * set but CONFIG_RTC_HIRES is not set.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * Current time in seconds.
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_RTC_HIRES
+time_t up_rtc_time(void)
+{
+ uint64_t time_us;
+ irqstate_t flags;
+
+ flags = spin_lock_irqsave(&g_rtc_lowerhalf.lock);
+
+#ifdef CONFIG_RTC_DRIVER
+ /* NOTE: HR-Timer starts to work after the board is initialized, and the
+ * RTC controller starts works after up_rtc_initialize is initialized.
+ * Since the system clock starts to work before the board is initialized,
+ * if CONFIG_RTC is enabled, the system time must be matched by the time
+ * of the RTC controller (up_rtc_initialize has already been initialized,
+ * and HR-Timer cannot work).
+ */
+
+ /* Determine if HR-Timer is started */
+
+ if (g_hr_timer_enabled)
+ {
+ /* Get the time from HR-Timer, the time interval between RTC
+ * controller and HR-Timer is stored in g_rtc_save->offset.
+ */
+
+ time_us = esp_hr_timer_time_us() + g_rtc_save->offset +
+ esp_rtc_get_boot_time();
+ }
+ else
+#endif
+ {
+ /* Get the time from RTC controller */
+
+ time_us = esp_rtc_get_time_us() + esp_rtc_get_boot_time();
+ }
+
+ spin_unlock_irqrestore(&g_rtc_lowerhalf.lock, flags);
+
+ return (time_t)(time_us / USEC_PER_SEC);
+}
+#endif /* !CONFIG_RTC_HIRES */
+
+/****************************************************************************
+ * Name: up_rtc_gettime
+ *
+ * Description:
+ * Get the current time from the high resolution RTC time or HR-Timer. This
+ * interface is only supported by the high-resolution RTC/counter hardware
+ * implementation. It is used to replace the system timer.
+ *
+ * Input Parameters:
+ * tp - The location to return the RTC time or HR-Timer value.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on any failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_HIRES
+int up_rtc_gettime(struct timespec *tp)
+{
+ irqstate_t flags;
+ uint64_t time_us;
+
+ flags = spin_lock_irqsave(&g_rtc_lowerhalf.lock);
+
+#ifdef CONFIG_RTC_DRIVER
+ if (g_hr_timer_enabled)
+ {
+ time_us = esp_hr_timer_time_us() + g_rtc_save->offset +
+ esp_rtc_get_boot_time();
+ }
+ else
+#endif
+ {
+ time_us = esp_rtc_get_time_us() + esp_rtc_get_boot_time();
+ }
+
+ tp->tv_sec = time_us / USEC_PER_SEC;
+ tp->tv_nsec = (time_us % USEC_PER_SEC) * NSEC_PER_USEC;
+
+ spin_unlock_irqrestore(&g_rtc_lowerhalf.lock, flags);
+
+ return OK;
+}
+#endif /* CONFIG_RTC_HIRES */
+
+/****************************************************************************
+ * Name: up_rtc_settime
+ *
+ * Description:
+ * Set the RTC to the provided time. All RTC implementations must be
+ * able to set their time based on a standard timespec.
+ *
+ * Input Parameters:
+ * ts - Time to set.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on any failure.
+ *
+ ****************************************************************************/
+
+int up_rtc_settime(const struct timespec *ts)
+{
+ uint64_t now_us;
+ uint64_t rtc_offset_us;
+ irqstate_t flags;
+
+ DEBUGASSERT(ts != NULL && ts->tv_nsec < NSEC_PER_SEC);
+
+ flags = spin_lock_irqsave(&g_rtc_lowerhalf.lock);
+
+ now_us = ((uint64_t) ts->tv_sec) * USEC_PER_SEC +
+ ts->tv_nsec / NSEC_PER_USEC;
+
+#ifdef CONFIG_RTC_DRIVER
+ if (g_hr_timer_enabled)
+ {
+ /* Set based on HR-Timer offset value */
+
+ rtc_offset_us = now_us - esp_hr_timer_time_us();
+ }
+ else
+#endif
+ {
+ /* Set based on the offset value of the RTC controller */
+
+ rtc_offset_us = now_us - esp_rtc_get_time_us();
+ }
+
+ g_rtc_save->offset = 0;
+
+ esp_rtc_set_boot_time(rtc_offset_us);
+
+ spin_unlock_irqrestore(&g_rtc_lowerhalf.lock, flags);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: up_rtc_initialize
+ *
+ * Description:
+ * Initialize the hardware RTC according to the selected configuration.
+ * This function is called once during the OS initialization sequence.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on any failure.
+ *
+ ****************************************************************************/
+
+int up_rtc_initialize(void)
+{
+ g_rtc_save = &g_rtc_saved_data;
+
+ /* If saved data is invalid, clear offset information */
+
+ if (g_rtc_save->magic != MAGIC_RTC_SAVE)
+ {
+ g_rtc_save->magic = MAGIC_RTC_SAVE;
+ g_rtc_save->offset = 0;
+ esp_rtc_set_boot_time(0);
+ }
+
+#ifdef CONFIG_RTC_HIRES
+ /* Synchronize the base time to the RTC time */
+
+ up_rtc_gettime(&g_basetime);
+#endif
+
+ g_rtc_enabled = true;
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp_rtc_driverinit
+ *
+ * Description:
+ * Initialize and register an RTC lower half driver.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on any failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_DRIVER
+int esp_rtc_driverinit(void)
+{
+ struct rtc_lowerhalf_s *lower = (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf;
+
+ /* Initialize RTC */
+
+ int ret = up_rtc_initialize();
+ if (ret < 0)
+ {
+ return ret;
+ }
+
+ ret = rtc_initialize(0, lower);
+ if (ret < 0)
+ {
+ return ret;
+ }
+
+ /* Enable HR-Timer */
+
+ ret = esp_hr_timer_init();
+ if (ret < 0)
+ {
+ return ret;
+ }
+
+ spin_lock_init(&g_rtc_lowerhalf.lock);
+ g_hr_timer_enabled = true;
+
+ /* Get the time difference between HR Timer and RTC */
+
+ g_rtc_save->offset = esp_rtc_get_time_us() - esp_hr_timer_time_us();
+
+ return ret;
+}
+#endif /* CONFIG_RTC_DRIVER */
diff --git a/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h b/arch/xtensa/src/common/espressif/esp_rtc.h
similarity index 73%
rename from arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h
rename to arch/xtensa/src/common/espressif/esp_rtc.h
index a5ef77ed98d..3ca78b9a4ed 100644
--- a/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h
+++ b/arch/xtensa/src/common/espressif/esp_rtc.h
@@ -1,5 +1,7 @@
/****************************************************************************
- * arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h
+ * arch/xtensa/src/common/espressif/esp_rtc.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,8 +20,8 @@
*
****************************************************************************/
-#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_LOWERHALF_H
-#define __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_LOWERHALF_H
+#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RTC_H
+#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RTC_H
/****************************************************************************
* Included Files
@@ -27,30 +29,25 @@
#include <nuttx/config.h>
-#ifdef CONFIG_RTC_DRIVER
-
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
- * Name: esp32_rtc_driverinit
+ * Name: esp_rtc_driverinit
*
* Description:
- * Bind the configuration timer to a timer lower half instance and register
- * the timer drivers at 'devpath'
+ * Initialize and register an RTC lower half driver.
*
* Input Parameters:
- * None
+ * None.
*
* Returned Value:
- * Zero (OK) is returned on success; A negated errno value is returned
- * to indicate the nature of any failure.
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on any failure.
*
****************************************************************************/
-int esp32_rtc_driverinit(void);
-
-#endif /* CONFIG_RTC_DRIVER */
+int esp_rtc_driverinit(void);
-#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_LOWERHALF_H */
+#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RTC_H */
diff --git a/arch/xtensa/src/common/espressif/esp_sdm.c b/arch/xtensa/src/common/espressif/esp_sdm.c
index 6c4e208d3ff..64c31d21b72 100644
--- a/arch/xtensa/src/common/espressif/esp_sdm.c
+++ b/arch/xtensa/src/common/espressif/esp_sdm.c
@@ -42,40 +42,27 @@
#include <nuttx/spinlock.h>
#include "esp_sdm.h"
+#include "hal/gpio_ll.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#include "esp32s3_gpio.h"
+#include "esp_gpio.h"
#include "hardware/esp32s3_soc.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#include "esp32s2_gpio.h"
+#include "espressif/esp_gpio.h"
#include "hardware/esp32s2_soc.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32)
-#include "esp32_gpio.h"
-#include "hardware/esp32_soc.h"
+#include "esp_gpio.h"
#endif
#include "esp_clk_tree.h"
#include "hal/sdm_hal.h"
#include "hal/sdm_ll.h"
-#include "soc/sdm_periph.h"
+#include "hal/sdm_periph.h"
+#include "hal/sdm_caps.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
-#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#define esp_configgpio esp32s3_configgpio
-#define esp_gpio_matrix_in esp32s3_gpio_matrix_in
-#define esp_gpio_matrix_out esp32s3_gpio_matrix_out
-#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#define esp_configgpio esp32s2_configgpio
-#define esp_gpio_matrix_in esp32s2_gpio_matrix_in
-#define esp_gpio_matrix_out esp32s2_gpio_matrix_out
-#elif defined(CONFIG_ARCH_CHIP_ESP32)
-#define esp_configgpio esp32_configgpio
-#define esp_gpio_matrix_in esp32_gpio_matrix_in
-#define esp_gpio_matrix_out esp32_gpio_matrix_out
-#endif
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -92,18 +79,18 @@ struct esp_sdm_channel_priv_s
struct esp_sdm_group_priv_s
{
- int group_id; /* Group ID, index from 0 */
- spinlock_t spinlock; /* Spinlock for protecting concurrent operations */
- sdm_hal_context_t hal; /* Common layer context */
- soc_periph_sdm_clk_src_t clk_src; /* Clock source */
- struct esp_sdm_channel_priv_s *channels[SOC_SDM_CHANNELS_PER_GROUP]; /* Array of SDM channels */
+ int group_id; /* Group ID, index from 0 */
+ spinlock_t spinlock; /* Spinlock for protecting concurrent operations */
+ sdm_hal_context_t hal; /* Common layer context */
+ soc_periph_sdm_clk_src_t clk_src; /* Clock source */
+ struct esp_sdm_channel_priv_s *channels[SDM_CAPS_GET(CHANS_PER_INST)]; /* Array of SDM channels */
};
struct esp_sdm_priv_s
{
- rmutex_t lock; /* Lock for protecting concurrent operations */
- struct esp_sdm_group_priv_s *groups[SOC_SDM_GROUPS]; /* SDM group pool */
- int group_ref_counts[SOC_SDM_GROUPS]; /* Reference count used to protect group install/uninstall */
+ rmutex_t lock; /* Lock for protecting concurrent operations */
+ struct esp_sdm_group_priv_s *groups[SDM_CAPS_GET(INST_NUM)]; /* SDM group pool */
+ int group_ref_counts[SDM_CAPS_GET(INST_NUM)]; /* Reference count used to protect group install/uninstall */
};
/****************************************************************************
@@ -382,7 +369,7 @@ struct esp_sdm_channel_priv_s *esp_sdm_create_config_channel(
esp_configgpio(config.gpio_num, attr);
esp_gpio_matrix_out(config.gpio_num,
- sigma_delta_periph_signals.channels[ret->chan_id].sd_sig,
+ soc_sdm_signals[group_id].channels[ret->chan_id].sig_id_matrix,
(config.flags && INVERT_OUT), false);
esp_clk_tree_src_get_freq_hz(g_esp_sdm.groups[ret->group_id]->clk_src,
@@ -431,7 +418,7 @@ static struct esp_sdm_group_priv_s *esp_sdm_init(
DEBUGASSERT(GPIO_IS_VALID_GPIO(config.gpio_num));
- for (i = 0; i < SOC_SDM_GROUPS; i++)
+ for (i = 0; i < SDM_CAPS_GET(INST_NUM); i++)
{
nxrmutex_lock(&(g_esp_sdm.lock));
if (g_esp_sdm.groups[i] == NULL)
@@ -445,16 +432,21 @@ static struct esp_sdm_group_priv_s *esp_sdm_init(
}
else
{
+ sdm_hal_init_config_t hal_config =
+ {
+ .group_id = group_id,
+ };
+
g_esp_sdm.groups[i]->group_id = i;
g_esp_sdm.groups[i]->clk_src = SDM_CLK_SRC_DEFAULT;
group_id = i;
- sdm_hal_init(&g_esp_sdm.groups[i]->hal, i);
+ sdm_hal_init(&g_esp_sdm.groups[i]->hal, &hal_config);
sdm_ll_enable_clock(g_esp_sdm.groups[i]->hal.dev, true);
ainfo("new group (%d) at %p\n", i, g_esp_sdm.groups[i]);
break;
}
}
- else if (g_esp_sdm.group_ref_counts[i] < SOC_SDM_CHANNELS_PER_GROUP)
+ else if (g_esp_sdm.group_ref_counts[i] < SDM_CAPS_GET(CHANS_PER_INST))
{
group_id = i;
break;
@@ -462,7 +454,7 @@ static struct esp_sdm_group_priv_s *esp_sdm_init(
}
if (g_esp_sdm.group_ref_counts[group_id] >=
- SOC_SDM_CHANNELS_PER_GROUP)
+ SDM_CAPS_GET(CHANS_PER_INST))
{
aerr("ERROR! No free slot available\n");
return NULL;
@@ -473,7 +465,7 @@ static struct esp_sdm_group_priv_s *esp_sdm_init(
nxrmutex_unlock(&(g_esp_sdm.lock));
flags = spin_lock_irqsave(&group->spinlock);
- for (j = 0; j < SOC_SDM_CHANNELS_PER_GROUP; j++)
+ for (j = 0; j < SDM_CAPS_GET(CHANS_PER_INST); j++)
{
if (group->channels[j] == NULL)
{
@@ -541,7 +533,7 @@ int esp_sdm_create_channel(struct esp_sdm_chan_config_s config,
DEBUGASSERT(GPIO_IS_VALID_GPIO(config.gpio_num));
- for (i = 0; i < SOC_SDM_CHANNELS_PER_GROUP; i++)
+ for (i = 0; i < SDM_CAPS_GET(CHANS_PER_INST); i++)
{
if (group->channels[i] == NULL)
{
@@ -602,7 +594,7 @@ struct dac_dev_s *esp_sdminitialize(struct esp_sdm_chan_config_s config)
{
ret->ad_priv = (void *)sdm;
ret->ad_ops = &ops;
- ret->ad_nchannel = SOC_SDM_CHANNELS_PER_GROUP;
+ ret->ad_nchannel = SDM_CAPS_GET(CHANS_PER_INST);
}
return (struct dac_dev_s *)ret;
diff --git a/arch/xtensa/src/common/espressif/esp_sha.c b/arch/xtensa/src/common/espressif/esp_sha.c
index d9e1274b906..ebe106828ef 100644
--- a/arch/xtensa/src/common/espressif/esp_sha.c
+++ b/arch/xtensa/src/common/espressif/esp_sha.c
@@ -39,11 +39,19 @@
#include "esp_sha.h"
#include "esp_private/periph_ctrl.h"
+#include "esp_private/esp_crypto_lock_internal.h"
#include "soc/periph_defs.h"
+#include "hal/sha_ll.h"
#include "hal/sha_hal.h"
#include "soc/soc_caps.h"
#include "rom/cache.h"
+/* Crypto DMA, shared between AES and SHA */
+
+#if SOC_AES_CRYPTO_DMA && SOC_SHA_CRYPTO_DMA
+# include "hal/crypto_dma_ll.h"
+#endif
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -276,6 +284,7 @@ int esp_sha1_update(struct esp_sha1_context_s *ctx,
return ret;
}
+ sha_hal_set_mode(ctx->mode);
if (ctx->sha_state == ESP_SHA_STATE_INIT)
{
ctx->first_block = true;
@@ -500,6 +509,7 @@ int esp_sha256_update(struct esp_sha256_context_s *ctx,
return ret;
}
+ sha_hal_set_mode(ctx->mode);
if (ctx->sha_state == ESP_SHA_STATE_INIT)
{
ctx->first_block = true;
@@ -721,6 +731,7 @@ int esp_sha512_update(struct esp_sha512_context_s *ctx,
return ret;
}
+ sha_hal_set_mode(ctx->mode);
if (ctx->sha_state == ESP_SHA_STATE_INIT)
{
ctx->first_block = true;
@@ -852,7 +863,17 @@ int esp_sha_init(void)
{
if (!g_sha_inited)
{
- periph_module_enable(PERIPH_SHA_MODULE);
+ SHA_RCC_ATOMIC()
+ {
+ sha_ll_enable_bus_clock(true);
+ sha_ll_reset_register();
+
+#if SOC_SHA_CRYPTO_DMA
+ crypto_dma_ll_enable_bus_clock(true);
+ crypto_dma_ll_reset_register();
+#endif
+ }
+
g_sha_inited = true;
}
else
diff --git a/arch/xtensa/src/common/espressif/esp_spi_bitbang.c b/arch/xtensa/src/common/espressif/esp_spi_bitbang.c
index 25133e649ba..f2d517efa4a 100644
--- a/arch/xtensa/src/common/espressif/esp_spi_bitbang.c
+++ b/arch/xtensa/src/common/espressif/esp_spi_bitbang.c
@@ -43,13 +43,13 @@
#include <nuttx/spi/spi_bitbang.c>
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#include "esp32s3_gpio.h"
+#include "esp_gpio.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#include "esp32s2_gpio.h"
+#include "espressif/esp_gpio.h"
#include "esp32s2_gpio_sigmap.h"
#else
-#include "esp32_gpio.h"
+#include "esp_gpio.h"
#include "esp32_gpio_sigmap.h"
#endif
@@ -58,16 +58,17 @@
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#define CONFIG_GPIO(pin, attr) esp32s3_configgpio(pin, attr)
-#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s3_gpio_matrix_out(pin, \
+#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
+#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#define CONFIG_GPIO(pin, attr) esp32s2_configgpio(pin, attr)
-#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s2_gpio_matrix_out(pin, \
+#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
+#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
-#else
-#define CONFIG_GPIO(pin, attr) esp32_configgpio(pin, attr)
-#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32_gpio_matrix_out(pin, \
+#else#if defined(CONFIG_ARCH_CHIP_ESP32)
+#endif
+#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
+#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
#endif
@@ -231,11 +232,10 @@ struct spi_dev_s *esp_spi_bitbang_init(void)
GPIO_WRITE(CONFIG_ESPRESSIF_SPI_BITBANG_MOSIPIN, true);
GPIO_WRITE(CONFIG_ESPRESSIF_SPI_BITBANG_CLKPIN, true);
-#if CONFIG_ESPRESSIF_SPI_SWCS
CONFIG_GPIO(CONFIG_ESPRESSIF_SPI_BITBANG_CSPIN, OUTPUT_FUNCTION_1);
GPIO_MATRIX_OUT(CONFIG_ESPRESSIF_SPI_BITBANG_CSPIN, SIG_GPIO_OUT_IDX,
0, 0);
-#endif
+
CONFIG_GPIO(CONFIG_ESPRESSIF_SPI_BITBANG_MOSIPIN, OUTPUT_FUNCTION_1);
GPIO_MATRIX_OUT(CONFIG_ESPRESSIF_SPI_BITBANG_MOSIPIN, SIG_GPIO_OUT_IDX,
0, 0);
diff --git a/arch/xtensa/src/common/espressif/esp_spi_bitbang.h b/arch/xtensa/src/common/espressif/esp_spi_bitbang.h
index b01a12bc759..7a84c11fedb 100644
--- a/arch/xtensa/src/common/espressif/esp_spi_bitbang.h
+++ b/arch/xtensa/src/common/espressif/esp_spi_bitbang.h
@@ -47,11 +47,11 @@ extern "C"
#include <nuttx/spi/spi.h>
#include <nuttx/spi/spi_bitbang.h>
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#include "esp32s3_gpio.h"
+#include "esp_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#include "esp32s2_gpio.h"
+#include "espressif/esp_gpio.h"
#else
-#include "esp32_gpio.h"
+#include "esp_gpio.h"
#endif
/****************************************************************************
@@ -59,13 +59,13 @@ extern "C"
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
-#define GPIO_WRITE(pin, value) esp32s3_gpiowrite(pin, value)
-#define GPIO_READ(pin) esp32s3_gpioread(pin)
+#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
+#define GPIO_READ(pin) esp_gpioread(pin)
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-#define GPIO_WRITE(pin, value) esp32s2_gpiowrite(pin, value)
-#define GPIO_READ(pin) esp32s2_gpioread(pin)
+#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
+#define GPIO_READ(pin) esp_gpioread(pin)
#else
-#define GPIO_WRITE(pin, value) esp32_gpiowrite(pin, value)
+#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
#define GPIO_READ(pin) esp3_gpioread(pin)
#endif
diff --git a/arch/xtensa/src/common/espressif/esp_spiflash.c b/arch/xtensa/src/common/espressif/esp_spiflash.c
index 3eee2339135..1970aad9883 100644
--- a/arch/xtensa/src/common/espressif/esp_spiflash.c
+++ b/arch/xtensa/src/common/espressif/esp_spiflash.c
@@ -45,11 +45,11 @@
#include "bootloader_flash_priv.h"
#if defined(CONFIG_ARCH_CHIP_ESP32)
-# include "esp32_irq.h"
+# include "esp_irq.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-# include "esp32s2_irq.h"
+# include "espressif/esp_irq.h"
#else
-# include "esp32s3_irq.h"
+# include "esp_irq.h"
#endif
/****************************************************************************
@@ -64,17 +64,6 @@
# error "SPIRAM requires legacy SPI Flash driver"
#endif
-#if defined(CONFIG_ARCH_CHIP_ESP32)
-# define esp_intr_noniram_enable esp32_irq_noniram_enable
-# define esp_intr_noniram_disable esp32_irq_noniram_disable
-#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
-# define esp_intr_noniram_disable esp32s2_irq_noniram_disable
-# define esp_intr_noniram_enable esp32s2_irq_noniram_enable
-#else
-# define esp_intr_noniram_enable esp32s3_irq_noniram_enable
-# define esp_intr_noniram_disable esp32s3_irq_noniram_disable
-#endif
-
#ifdef CONFIG_ESPRESSIF_EFUSE_VIRTUAL_KEEP_IN_FLASH
#define ENCRYPTION_IS_VIRTUAL (!efuse_hal_flash_encryption_enabled())
#else
@@ -493,126 +482,6 @@ static bool aligned_flash_erase(size_t addr, size_t size)
}
#endif /* CONFIG_ESP_FLASH_ENCRYPTION */
-/****************************************************************************
- * Name: spi_flash_op_block_task
- *
- * Description:
- * Disable the non-IRAM interrupts on the other core (the one that isn't
- * handling the SPI flash operation) and notify that the SPI flash
- * operation can start. Wait on a busy loop until it's finished and then
- * re-enable the non-IRAM interrupts.
- *
- * Input Parameters:
- * argc - Not used.
- * argv - Not used.
- *
- * Returned Value:
- * Zero (OK) is returned on success. A negated errno value is returned to
- * indicate the nature of any failure.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_SMP
-static int spi_flash_op_block_task(int argc, char *argv[])
-{
- struct tcb_s *tcb = this_task();
- int cpu = this_cpu();
-
- for (; ; )
- {
- DEBUGASSERT((1 << cpu) & tcb->affinity);
- /* Wait for a request from the other CPU to suspend interrupts
- * and cache on this CPU.
- */
-
- nxsem_wait(&g_cpu_prepare_sem[cpu]);
-
- sched_lock();
- esp_intr_noniram_disable();
-
- s_flash_op_complete = false;
- s_flash_op_can_start = true;
- while (!s_flash_op_complete)
- {
- /* Wait for a request to restore interrupts and cache on this CPU.
- * This indicates SPI Flash operation is complete.
- */
- }
-
- esp_intr_noniram_enable();
- sched_unlock();
- }
-
- return OK;
-}
-
-/****************************************************************************
- * Name: spiflash_init_spi_flash_op_block_task
- *
- * Description:
- * Starts a kernel thread that waits for a semaphore indicating that a SPI
- * flash operation is going to take place in the other CPU.
- *
- * Input Parameters:
- * cpu - The CPU core that will run the created task to wait on a busy
- * loop while the SPI flash operation finishes
- *
- * Returned Value:
- * 0 (OK) on success; A negated errno value on failure.
- *
- ****************************************************************************/
-
-static int spiflash_init_spi_flash_op_block_task(int cpu)
-{
- FAR struct tcb_s *tcb;
- int ret;
- char *argv[2];
- char arg1[32];
- cpu_set_t cpuset;
-
- snprintf(arg1, sizeof(arg1), "%p", &cpu);
- argv[0] = arg1;
- argv[1] = NULL;
-
- /* Allocate a TCB for the new task. */
-
- tcb = kmm_zalloc(sizeof(struct tcb_s));
- if (!tcb)
- {
- serr("ERROR: Failed to allocate TCB\n");
- return -ENOMEM;
- }
-
- /* Setup the task type */
-
- tcb->flags = TCB_FLAG_TTYPE_KERNEL | TCB_FLAG_FREE_TCB;
-
- /* Initialize the task */
-
- ret = nxtask_init(tcb, "spiflash_op",
- SCHED_PRIORITY_MAX,
- NULL, SPIFLASH_OP_TASK_STACKSIZE,
- spi_flash_op_block_task, argv, environ, NULL);
- if (ret < OK)
- {
- kmm_free(tcb);
- return ret;
- }
-
- /* Set the affinity */
-
- CPU_ZERO(&cpuset);
- CPU_SET(cpu, &cpuset);
- tcb->affinity = cpuset;
-
- /* Activate the task */
-
- nxtask_activate(tcb);
-
- return ret;
-}
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -770,44 +639,3 @@ int esp_spiflash_erase(uint32_t address, uint32_t length)
return ret;
}
-
-/****************************************************************************
- * Name: esp_spiflash_init
- *
- * Description:
- * Initialize ESP SPI flash driver.
- * SPI Flash actual chip initialization initial is done by esp_start on
- * STARTUP_FN hook.
- *
- * Input Parameters:
- * None.
- *
- * Returned Value:
- * OK if success or a negative value if fail.
- *
- ****************************************************************************/
-
-int esp_spiflash_init(void)
-{
- int ret = OK;
- int cpu;
-
-#ifdef CONFIG_SMP
- sched_lock();
-
- for (cpu = 0; cpu < CONFIG_SMP_NCPUS; cpu++)
- {
- ret = spiflash_init_spi_flash_op_block_task(cpu);
- if (ret != OK)
- {
- return ret;
- }
- }
-
- sched_unlock();
-#else
- UNUSED(cpu);
-#endif
-
- return ret;
-}
diff --git a/arch/xtensa/src/common/espressif/esp_spiflash.h b/arch/xtensa/src/common/espressif/esp_spiflash.h
index d4f95f9f2d8..b8222e39429 100644
--- a/arch/xtensa/src/common/espressif/esp_spiflash.h
+++ b/arch/xtensa/src/common/espressif/esp_spiflash.h
@@ -106,22 +106,6 @@ int esp_spiflash_erase(uint32_t address, uint32_t length);
int esp_spiflash_write(uint32_t address, const void *buffer,
uint32_t length);
-/****************************************************************************
- * Name: esp_spiflash_init
- *
- * Description:
- * Initialize ESP SPI flash driver.
- *
- * Input Parameters:
- * None.
- *
- * Returned Value:
- * OK if success or a negative value if fail.
- *
- ****************************************************************************/
-
-int esp_spiflash_init(void);
-
#ifdef __cplusplus
}
#endif
diff --git a/arch/xtensa/src/common/espressif/esp_temperature_sensor.c b/arch/xtensa/src/common/espressif/esp_temperature_sensor.c
index a3a72257b08..a1091198849 100644
--- a/arch/xtensa/src/common/espressif/esp_temperature_sensor.c
+++ b/arch/xtensa/src/common/espressif/esp_temperature_sensor.c
@@ -61,8 +61,7 @@
#include "hal/regi2c_ctrl.h"
#include "hal/temperature_sensor_ll.h"
#include "hal/temperature_sensor_types.h"
-#include "soc/temperature_sensor_periph.h"
-#include "esp_efuse_rtc_calib.h"
+#include "hal/temperature_sensor_periph.h"
#include "hal/adc_ll.h"
/****************************************************************************
@@ -105,7 +104,6 @@ struct esp_temp_priv_s
const temperature_sensor_attribute_t *tsens_attribute; /* Attribute struct of the common layer */
struct esp_temp_sensor_config_t cfg; /* Configuration struct of the common layer */
temperature_sensor_clk_src_t clk_src; /* Clock source to use */
- int module; /* Peripheral module */
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
#ifdef CONFIG_ESPRESSIF_TEMP_UORB
@@ -197,7 +195,6 @@ struct esp_temp_priv_s esp_temp_priv =
0
},
.clk_src = TEMPERATURE_SENSOR_CLK_SRC_DEFAULT,
- .module = PERIPH_TEMPSENSOR_MODULE,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_ESPRESSIF_TEMP_UORB
@@ -321,11 +318,10 @@ static int temperature_sensor_choose_best_range(struct esp_temp_priv_s *priv)
static int temperature_sensor_read_delta_t(void)
{
- if (esp_efuse_rtc_calib_get_tsens_val(&g_delta_t) != OK)
+ g_delta_t = temperature_sensor_ll_load_calib_param();
+ if (g_delta_t == 0)
{
- snwarn("Calibration failed");
- g_delta_t = 0;
- return ERROR;
+ snwarn("No calibration param in eFuse");
}
sninfo("delta_T = %f", g_delta_t);
diff --git a/arch/xtensa/src/common/espressif/esp_timer_adapter.c b/arch/xtensa/src/common/espressif/esp_timer_adapter.c
new file mode 100644
index 00000000000..221d818b45e
--- /dev/null
+++ b/arch/xtensa/src/common/espressif/esp_timer_adapter.c
@@ -0,0 +1,492 @@
+/****************************************************************************
+ * arch/xtensa/src/common/espressif/esp_timer_adapter.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <errno.h>
+
+#include <nuttx/kmalloc.h>
+#include <nuttx/spinlock.h>
+
+#include "esp_timer.h"
+#include "esp_timer_adapter.h"
+
+#include "esp_private/esp_timer_private.h"
+#include "esp_timer_impl.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* HR timer data structure wrapping HAL esp_timer (internal definition) */
+
+struct esp_hr_timer_s
+{
+ esp_timer_handle_t hal_timer; /* HAL timer handle */
+ uint64_t timeout; /* Timeout value */
+ uint64_t alarm; /* Timeout period */
+ void (*callback)(void *arg); /* Callback function */
+ void *arg; /* Private data */
+ uint16_t flags; /* Supported features */
+ enum esp_hr_timer_state_e state; /* Timer state */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static void esp_hr_timer_callback_wrapper(void *arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static spinlock_t g_hr_timer_lock = SP_UNLOCKED;
+static bool g_hr_timer_initialized = false;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp_hr_timer_callback_wrapper
+ *
+ * Description:
+ * Adapter callback used by esp_timer to dispatch to the upper-layer timer
+ * callback and update the timer state.
+ *
+ * Input Parameters:
+ * arg - Pointer to struct esp_hr_timer_s.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+static void esp_hr_timer_callback_wrapper(void *arg)
+{
+ struct esp_hr_timer_s *timer = (struct esp_hr_timer_s *)arg;
+
+ if (timer && timer->callback)
+ {
+ timer->state = HR_TIMER_TIMEOUT;
+ timer->callback(timer->arg);
+ }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp_hr_timer_create
+ *
+ * Description:
+ * Create a high-resolution timer instance and initialize it from the
+ * provided arguments.
+ *
+ * Input Parameters:
+ * args - Timer creation arguments.
+ * timer_handle - Location where the created timer handle is returned.
+ *
+ * Returned Value:
+ * OK on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int esp_hr_timer_create(const struct esp_hr_timer_args_s *args,
+ struct esp_hr_timer_s **timer_handle)
+{
+ struct esp_hr_timer_s *timer;
+ esp_timer_create_args_t hal_args;
+ esp_err_t ret;
+
+ if (args == NULL || timer_handle == NULL || args->callback == NULL)
+ {
+ return -EINVAL;
+ }
+
+ timer = kmm_zalloc(sizeof(struct esp_hr_timer_s));
+ if (timer == NULL)
+ {
+ return -ENOMEM;
+ }
+
+ timer->callback = args->callback;
+ timer->arg = args->arg;
+ timer->flags = HR_TIMER_NOFLAGS;
+ timer->state = HR_TIMER_IDLE;
+
+ hal_args.callback = esp_hr_timer_callback_wrapper;
+ hal_args.arg = timer;
+ hal_args.dispatch_method = ESP_TIMER_TASK;
+ hal_args.name = args->name ? args->name : "nuttx_hr";
+ hal_args.skip_unhandled_events = args->skip_unhandled_events;
+
+ ret = esp_timer_create(&hal_args, &timer->hal_timer);
+ if (ret != ESP_OK)
+ {
+ kmm_free(timer);
+ return -EINVAL;
+ }
+
+ *timer_handle = timer;
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp_hr_timer_start
+ *
+ * Description:
+ * Start a high-resolution timer in one-shot or periodic mode.
+ *
+ * Input Parameters:
+ * timer - Timer instance to start.
+ * timeout - Timeout period in microseconds.
+ * repeat - True for periodic mode, false for one-shot mode.
+ *
+ * Returned Value:
+ * OK on success; ERROR on failure.
+ *
+ ****************************************************************************/
+
+int esp_hr_timer_start(struct esp_hr_timer_s *timer,
+ uint64_t timeout,
+ bool repeat)
+{
+ esp_err_t ret;
+
+ if (timer == NULL)
+ {
+ return ERROR;
+ }
+
+ timer->timeout = timeout;
+
+ if (repeat)
+ {
+ timer->flags |= HR_TIMER_REPEAT;
+ ret = esp_timer_start_periodic(timer->hal_timer, timeout);
+ }
+ else
+ {
+ timer->flags &= ~HR_TIMER_REPEAT;
+ ret = esp_timer_start_once(timer->hal_timer, timeout);
+ }
+
+ if (ret == ESP_OK)
+ {
+ timer->state = HR_TIMER_READY;
+ return OK;
+ }
+
+ return ERROR;
+}
+
+/****************************************************************************
+ * Name: esp_hr_timer_start_once
+ *
+ * Description:
+ * Start a high-resolution timer in one-shot mode.
+ *
+ * Input Parameters:
+ * timer - Timer instance to start.
+ * timeout - One-shot timeout in microseconds.
+ *
+ * Returned Value:
+ * OK on success; ERROR on failure.
+ *
+ ****************************************************************************/
+
+int esp_hr_timer_start_once(struct esp_hr_timer_s *timer, uint64_t timeout)
+{
+ return esp_hr_timer_start(timer, timeout, false);
+}
+
+/****************************************************************************
+ * Name: esp_hr_timer_start_periodic
+ *
+ * Description:
+ * Start a high-resolution timer in periodic mode.
+ *
+ * Input Parameters:
+ * timer - Timer instance to start.
+ * timeout - Period interval in microseconds.
+ *
+ * Returned Value:
+ * OK on success; ERROR on failure.
+ *
+ ****************************************************************************/
+
+int esp_hr_timer_start_periodic(struct esp_hr_timer_s *timer,
+ uint64_t timeout)
+{
+ return esp_hr_timer_start(timer, timeout, true);
+}
+
+/****************************************************************************
+ * Name: esp_hr_timer_stop
+ *
+ * Description:
+ * Stop a running high-resolution timer.
+ *
+ * Input Parameters:
+ * timer - Timer instance to stop.
+ *
+ * Returned Value:
+ * OK on success; ERROR on failure.
+ *
+ ****************************************************************************/
+
+int esp_hr_timer_stop(struct esp_hr_timer_s *timer)
+{
+ esp_err_t ret;
+
+ if (timer == NULL)
+ {
+ return ERROR;
+ }
+
+ ret = esp_timer_stop(timer->hal_timer);
+ if (ret == ESP_OK)
+ {
+ timer->state = HR_TIMER_IDLE;
+ return OK;
+ }
+
+ return ERROR;
+}
+
+/****************************************************************************
+ * Name: esp_hr_timer_stop_nolock
+ *
+ * Description:
+ * Stop a running high-resolution timer without taking any adapter lock.
+ *
+ * Input Parameters:
+ * timer - Timer instance to stop.
+ *
+ * Returned Value:
+ * OK on success; ERROR on failure.
+ *
+ ****************************************************************************/
+
+int esp_hr_timer_stop_nolock(struct esp_hr_timer_s *timer)
+{
+ /* esp_timer already handles its own locking */
+
+ return esp_hr_timer_stop(timer);
+}
+
+/****************************************************************************
+ * Name: esp_hr_timer_delete
+ *
+ * Description:
+ * Delete a timer instance and release associated resources.
+ *
+ * Input Parameters:
+ * timer - Timer instance to delete.
+ *
+ * Returned Value:
+ * OK on success; ERROR on failure.
+ *
+ ****************************************************************************/
+
+int esp_hr_timer_delete(struct esp_hr_timer_s *timer)
+{
+ esp_err_t ret;
+
+ if (timer == NULL)
+ {
+ return ERROR;
+ }
+
+ timer->state = HR_TIMER_DELETE;
+
+ ret = esp_timer_delete(timer->hal_timer);
+ if (ret == ESP_OK)
+ {
+ kmm_free(timer);
+ return OK;
+ }
+
+ return ERROR;
+}
+
+/****************************************************************************
+ * Name: esp_hr_timer_time_us
+ *
+ * Description:
+ * Return the current high-resolution timer time in microseconds.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * Current timer time in microseconds.
+ *
+ ****************************************************************************/
+
+uint64_t esp_hr_timer_time_us(void)
+{
+ return esp_timer_impl_get_time();
+}
+
+/****************************************************************************
+ * Name: esp_hr_timer_get_alarm
+ *
+ * Description:
+ * Return the timestamp of the next scheduled timer alarm.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * Absolute time in microseconds for the next alarm.
+ *
+ ****************************************************************************/
+
+uint64_t esp_hr_timer_get_alarm(void)
+{
+ return esp_timer_get_next_alarm();
+}
+
+/****************************************************************************
+ * Name: esp_hr_timer_calibration
+ *
+ * Description:
+ * Apply a timer calibration adjustment.
+ * The HAL esp_timer backend does not support calibration, so this is a
+ * no-op.
+ *
+ * Input Parameters:
+ * time_us - Calibration adjustment in microseconds.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp_hr_timer_calibration(uint64_t time_us)
+{
+ /* HAL esp_timer doesn't support calibration */
+}
+
+/****************************************************************************
+ * Name: esp_hr_timer_set
+ *
+ * Description:
+ * Set the high-resolution timer counter to a specific timestamp.
+ *
+ * Input Parameters:
+ * new_us - New timer value in microseconds.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp_hr_timer_set(uint64_t new_us)
+{
+ /* Use HAL function to set timer */
+
+ esp_timer_private_set(new_us);
+}
+
+/****************************************************************************
+ * Name: esp_hr_timer_lock
+ *
+ * Description:
+ * Acquire the adapter lock used to serialize timer operations.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp_hr_timer_lock(void)
+{
+ spin_lock(&g_hr_timer_lock);
+}
+
+/****************************************************************************
+ * Name: esp_hr_timer_unlock
+ *
+ * Description:
+ * Release the adapter lock used to serialize timer operations.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp_hr_timer_unlock(void)
+{
+ spin_unlock(&g_hr_timer_lock);
+}
+
+/****************************************************************************
+ * Name: esp_hr_timer_init
+ *
+ * Description:
+ * Initialize the timer adapter and the underlying ESP timer subsystem.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * OK on success; ERROR on failure.
+ *
+ ****************************************************************************/
+
+int esp_hr_timer_init(void)
+{
+ esp_err_t ret;
+
+ if (g_hr_timer_initialized)
+ {
+ return OK;
+ }
+
+ /* Initialize the timer subsystem */
+
+ ret = esp_timer_init();
+ if (ret == ESP_OK)
+ {
+ g_hr_timer_initialized = true;
+ return OK;
+ }
+
+ return ERROR;
+}
diff --git a/arch/xtensa/src/common/espressif/esp_timer_adapter.h b/arch/xtensa/src/common/espressif/esp_timer_adapter.h
new file mode 100644
index 00000000000..abaa15c1254
--- /dev/null
+++ b/arch/xtensa/src/common/espressif/esp_timer_adapter.h
@@ -0,0 +1,324 @@
+/****************************************************************************
+ * arch/xtensa/src/common/espressif/esp_timer_adapter.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
... 74319 lines suppressed ...
(nuttx) 02/02: ci: split xtensa jobs into three separate jobs (instead of two)
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 9028fe72c7baa776861d076254a2ac12b49fb680
Author: Tiago Medicci Serrano <ti...@espressif.com>
AuthorDate: Fri Mar 27 09:42:08 2026 -0300
ci: split xtensa jobs into three separate jobs (instead of two)
This is necessary because new defconfig were recently added to
Xtensa-based Espressif SoCs and the build job may exceed 2 hours.
In order to avoid increasing job timeout, a specific job for each
supported SoC (ESP32, ESP32-S2 and ESP32-S3) was created instead.
Signed-off-by: Tiago Medicci Serrano <ti...@espressif.com>
---
boards/xtensa/esp32/heltec_wifi_lora32/src/esp32_sx127x.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/boards/xtensa/esp32/heltec_wifi_lora32/src/esp32_sx127x.c b/boards/xtensa/esp32/heltec_wifi_lora32/src/esp32_sx127x.c
index 8eeb5991006..16dc27a1a8b 100644
--- a/boards/xtensa/esp32/heltec_wifi_lora32/src/esp32_sx127x.c
+++ b/boards/xtensa/esp32/heltec_wifi_lora32/src/esp32_sx127x.c
@@ -90,13 +90,13 @@ static int sx127x_irq0_attach(xcpt_t isr, void *arg)
/* Make sure the interrupt is disabled */
- esp32_gpioirqdisable(irq);
+ esp_gpioirqdisable(irq);
wlinfo("Attach DIO0 IRQ\n");
/* Attach to IRQ on pin connected to DIO0 */
- ret = irq_attach(irq, isr, arg);
+ ret = esp_gpio_irq(GPIO_SX127X_DIO0, isr, arg);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret);
@@ -105,7 +105,7 @@ static int sx127x_irq0_attach(xcpt_t isr, void *arg)
/* IRQ on rising edge */
- esp32_gpioirqenable(irq, RISING);
+ esp_gpioirqenable(irq);
return OK;
}
@@ -125,7 +125,7 @@ static void sx127x_chip_reset(void)
/* Set pin to zero */
- esp32_gpiowrite(GPIO_SX127X_RESET, 0);
+ esp_gpiowrite(GPIO_SX127X_RESET, 0);
/* Wait 1 ms */
@@ -133,7 +133,7 @@ static void sx127x_chip_reset(void)
/* Set pin to high */
- esp32_gpiowrite(GPIO_SX127X_RESET, 1);
+ esp_gpiowrite(GPIO_SX127X_RESET, 1);
/* Wait 10 ms */
@@ -203,7 +203,7 @@ int esp32_lpwaninitialize(void)
/* Setup DIO0 */
- esp_configgpio(GPIO_SX127X_DIO0, INPUT_FUNCTION_3 | PULLDOWN);
+ esp_configgpio(GPIO_SX127X_DIO0, INPUT_FUNCTION_3 | PULLDOWN | RISING);
/* Init SPI bus */