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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2021/02/01 09:07:20 UTC

[GitHub] [incubator-nuttx] btashton commented on issue #2786: arch/risc-v/src/rv32im/riscv_syscall.S have bogus nops

btashton commented on issue #2786:
URL: https://github.com/apache/incubator-nuttx/issues/2786#issuecomment-770698076


   I believe that you are correct from the ISA
   ```
   ECALL and EBREAK cause the receiving privilege mode’s epc register to be set to the address of the ECALL or EBREAK instruction itself, not the address of the following instruction. As ECALL and EBREAK cause synchronous exceptions, they are not considered to retire, and should not increment the minstret CSR.
   ```
   
   I also looked and this also aligns with my assembly I wrote for testing a custom RISCV core.


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