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Posted to commits@nuttx.apache.org by ag...@apache.org on 2020/10/19 15:50:57 UTC
[incubator-nuttx] branch master updated: tiva/cc13x0: Fix nxstyle
errors
This is an automated email from the ASF dual-hosted git repository.
aguettouche pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new f8a3736 tiva/cc13x0: Fix nxstyle errors
f8a3736 is described below
commit f8a3736b5c7441b9f7cea4f8978b88553ae7b6b4
Author: Nathan Hartman <59...@users.noreply.github.com>
AuthorDate: Mon Oct 19 09:58:05 2020 -0400
tiva/cc13x0: Fix nxstyle errors
arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h,
arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_smph.h,
arch/arm/src/tiva/hardware/cc13x0/cc13x0_ccfg.h,
arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi.h,
arch/arm/src/tiva/hardware/cc13x0/cc13x0_memorymap.h,
arch/arm/src/tiva/hardware/cc13x0/cc13x0_smph.h:
* Fix nxstyle errors.
---
.../arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h | 38 ++++++++--------
.../arm/src/tiva/hardware/cc13x0/cc13x0_aux_smph.h | 3 +-
arch/arm/src/tiva/hardware/cc13x0/cc13x0_ccfg.h | 6 ++-
arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi.h | 4 +-
.../src/tiva/hardware/cc13x0/cc13x0_memorymap.h | 50 +++++++++++-----------
arch/arm/src/tiva/hardware/cc13x0/cc13x0_smph.h | 3 +-
6 files changed, 58 insertions(+), 46 deletions(-)
diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h
index 0eef8d1..6eec285 100644
--- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h
+++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h
@@ -1,10 +1,11 @@
-/********************************************************************************************************************
+/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gn...@nuttx.org>
*
- * Technical content derives from a TI header file that has a compatible BSD license:
+ * Technical content derives from a TI header file that has a compatible
+ * BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,24 +37,24 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ********************************************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI4_AUX_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI4_AUX_H
-/********************************************************************************************************************
+/****************************************************************************
* Included Files
- ********************************************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
#include "hardware/tiva_ddi.h"
-/********************************************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ********************************************************************************************************************/
+ ****************************************************************************/
-/* ADI3 AUX Register Offsets ****************************************************************************************/
+/* ADI3 AUX Register Offsets ************************************************/
#define TIVA_ADI4_AUX_MUX0_OFFSET 0x0000
#define TIVA_ADI4_AUX_MUX1_OFFSET 0x0001
@@ -67,7 +68,7 @@
#define TIVA_ADI4_AUX_ADCREF0_OFFSET 0x000a /* ADC Reference 0 */
#define TIVA_ADI4_AUX_ADCREF1_OFFSET 0x000b /* ADC Reference 1 */
-/* ADI3 AUX Register Addresses **************************************************************************************/
+/* ADI3 AUX Register Addresses **********************************************/
#define TIVA_ADI4_AUX_MUX0 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_MUX0_OFFSET)
#define TIVA_ADI4_AUX_MUX1 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_MUX1_OFFSET)
@@ -81,7 +82,9 @@
#define TIVA_ADI4_AUX_ADCREF0 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ADCREF0_OFFSET)
#define TIVA_ADI4_AUX_ADCREF1 (TIVA_AUX_ADI4_BASE + TIVA_ADI4_AUX_ADCREF1_OFFSET)
-/* Offsets may also be used in conjunction with access as described in cc13x0_ddi.h */
+/* Offsets may also be used in conjunction with access as described in
+ * cc13x0_ddi.h
+ */
#define TIVA_ADI4_AUX_DIR (TIVA_AUX_ADI4_BASE + TIVA_DDI_DIR_OFFSET)
#define TIVA_ADI4_AUX_SET (TIVA_AUX_ADI4_BASE + TIVA_DDI_SET_OFFSET)
@@ -90,7 +93,7 @@
#define TIVA_ADI4_AUX_MASK8B (TIVA_AUX_ADI4_BASE + TIVA_DDI_MASK8B_OFFSET)
#define TIVA_ADI4_AUX_MASK16B (TIVA_AUX_ADI4_BASE + TIVA_DDI_MASK16B_OFFSET)
-/* ADI3 AUX Register Bitfield Definitions ***************************************************************************/
+/* ADI3 AUX Register Bitfield Definitions ***********************************/
/* TIVA_ADI4_AUX_MUX0 */
@@ -168,17 +171,17 @@
/* TIVA_ADI4_AUX_COMP */
-#define ADI4_AUX_COMP_COMPA_EN (1 << 1) /* Bit 1: COMPA enable */
-#define ADI4_AUX_COMP_COMPB_EN (1 << 2) /* Bit 2: COMPB enable */
-#define ADI4_AUX_COMP_COMPB_TRIM_SHIFT (3) /* Bits 3-5 */
+#define ADI4_AUX_COMP_COMPA_EN (1 << 1) /* Bit 1: COMPA enable */
+#define ADI4_AUX_COMP_COMPB_EN (1 << 2) /* Bit 2: COMPB enable */
+#define ADI4_AUX_COMP_COMPB_TRIM_SHIFT (3) /* Bits 3-5 */
#define ADI4_AUX_COMP_COMPB_TRIM_MASK (7 << ADI4_AUX_COMP_COMPB_TRIM_SHIFT)
# define ADI4_AUX_COMP_COMPB_TRIM(n) ((uint32_t)(n) << ADI4_AUX_COMP_COMPB_TRIM_SHIFT)
# define ADI4_AUX_COMP_COMPB_TRIM_DIV1 (0 << ADI4_AUX_COMP_COMPB_TRIM_SHIFT) /* No reference division */
# define ADI4_AUX_COMP_COMPB_TRIM_DIV2 (1 << ADI4_AUX_COMP_COMPB_TRIM_SHIFT) /* Divide reference by 2 */
# define ADI4_AUX_COMP_COMPB_TRIM_DIV3 (3 << ADI4_AUX_COMP_COMPB_TRIM_SHIFT) /* Divide reference by 3 */
# define ADI4_AUX_COMP_COMPB_TRIM_DIV4 (7 << ADI4_AUX_COMP_COMPB_TRIM_SHIFT) /* Divide reference by 4 */
-#define ADI4_AUX_COMP_COMPA_REF_CURR_EN (1 << 6) /* Bit 6: Enables 2uA IPTAT current from ISRC to COMPA reference */
-#define ADI4_AUX_COMP_COMPA_REF_RES_EN (1 << 7) /* Bit 7: Enables 400kohm resistance from COMPA reference */
+#define ADI4_AUX_COMP_COMPA_REF_CURR_EN (1 << 6) /* Bit 6: Enables 2uA IPTAT current from ISRC to COMPA reference */
+#define ADI4_AUX_COMP_COMPA_REF_RES_EN (1 << 7) /* Bit 7: Enables 400kohm resistance from COMPA reference */
/* TIVA_ADI4_AUX_MUX4 */
@@ -217,7 +220,7 @@
# define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_2p73_MS (13 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 16384 clocks = 2.73ms */
# define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_5p46_MS (14 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 32768 clocks = 5.46ms */
# define ADI4_AUX_ADC0_SMPL_CYCLE_EXP_10p9_MS (15 << ADI4_AUX_ADC0_SMPL_CYCLE_EXP_SHIFT) /* 65536 clocks = 10.9ms */
-#define ADI4_AUX_ADC0_SMPL_MODE (1 << 7) /* Bit 7: ADC Sampling mode */
+#define ADI4_AUX_ADC0_SMPL_MODE (1 << 7) /* Bit 7: ADC Sampling mode */
# define ADI4_AUX_ADC0_SMPL_MODE_SYNCH (0)
# define ADI4_AUX_ADC0_SMPL_MODE_ASYNCH ADI4_AUX_ADC0_SMPL_MODE
@@ -235,7 +238,6 @@
#define ADI4_AUX_ADCREF0_IOMUX (1 << 5) /* Bit 5 */
#define ADI4_AUX_ADCREF0_REF_ON_IDLE (1 << 6) /* Bit 6: Enable ADCREF in IDLE state */
-
/* TIVA_ADI4_AUX_ADCREF1 */
#define ADI4_AUX_ADCREF1_VTRIM_SHIFT (0) /* Bits 0-5: Trim output voltage of ADC fixed
diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_smph.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_smph.h
index 54bec0b..8776683 100644
--- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_smph.h
+++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_smph.h
@@ -4,7 +4,8 @@
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gn...@nuttx.org>
*
- * Technical content derives from a TI header file that has a compatible BSD license:
+ * Technical content derives from a TI header file that has a compatible
+ * BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ccfg.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ccfg.h
index 6298007..0f6f08e 100644
--- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ccfg.h
+++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ccfg.h
@@ -4,7 +4,8 @@
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gn...@nuttx.org>
*
- * Technical content derives from a TI header file that has a compatible BSD license:
+ * Technical content derives from a TI header file that has a compatible
+ * BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -221,8 +222,11 @@
#define CCFG_FREQ_OFFSET_HF_COMP_P0_MASK (0xffff << CCFG_FREQ_OFFSET_HF_COMP_P0_SHIFT)
/* TIVA_CCFG_IEEE_MAC_0 (32-bit value) */
+
/* TIVA_CCFG_IEEE_MAC_1 (32-bit value) */
+
/* TIVA_CCFG_IEEE_BLE_0 (32-bit value) */
+
/* TIVA_CCFG_IEEE_BLE_1 (32-bit value) */
/* TIVA_CCFG_BL_CONFIG */
diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi.h
index 7cd8e24..263131c 100644
--- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi.h
+++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi.h
@@ -4,7 +4,8 @@
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gn...@nuttx.org>
*
- * Technical content derives from a TI header file that has a compatible BSD license:
+ * Technical content derives from a TI header file that has a compatible
+ * BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -234,6 +235,7 @@
#define TIVA_DDI_MASK16B_OFFSET 0x0200 /* Offset for 16-bit masked access */
/* DDI Register Addresses ***************************************************/
+
/* Register base addresses depend on that base address of the master, e.g.
* TIVA_AUX_DDI0_OSC_BASE.
*/
diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_memorymap.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_memorymap.h
index bc9f170..594fadb 100644
--- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_memorymap.h
+++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_memorymap.h
@@ -1,55 +1,57 @@
-/******************************************************************************
+/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_memorymap.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
*
- * Technical content derives from a TI header file that has a compatible BSD license:
+ * Technical content derives from a TI header file that has a compatible
+ * BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * modification, are permitted provided that the following conditions are
+ * met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
+ * 2) Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
*
* 3) Neither the name NuttX nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_C13X0_C13X0_MEMORYMAP_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_C13X0_C13X0_MEMORYMAP_H
-/******************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ******************************************************************************/
+ ****************************************************************************/
-/******************************************************************************
+/****************************************************************************
*
* The following are defines for the base address of the memories and
* peripherals on the CPU_MMAP interface
*
- ******************************************************************************/
+ ****************************************************************************/
#define TIVA_FLASHMEM_BASE 0x00000000 /* FLASHMEM */
#define TIVA_BROM_BASE 0x10000000 /* BROM */
diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_smph.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_smph.h
index ce03aea..85863cd 100644
--- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_smph.h
+++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_smph.h
@@ -4,7 +4,8 @@
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gn...@nuttx.org>
*
- * Technical content derives from a TI header file that has a compatible BSD license:
+ * Technical content derives from a TI header file that has a compatible
+ * BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.