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Posted to commits@mynewt.apache.org by we...@apache.org on 2016/12/28 21:43:09 UTC
[5/5] incubator-mynewt-core git commit: MYNEWT-524 Initial support
for nrf52840pdk
MYNEWT-524 Initial support for nrf52840pdk
This commit is the initial support for the nrf52840 pdk. I did some basic
ble testing with a test app (bletest) and it appears to be working. There
was no additional MCU added as the peripherals are close to the nrf52832.
No testing was done on any gpio outside the old 0 - 31 range.
Some changes were made that could affect the nrf52832 as well although
I doubt anything that changed with this commit would have any impact.
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/afecb4cd
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/afecb4cd
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/afecb4cd
Branch: refs/heads/develop
Commit: afecb4cdb3ce655760230b6bcc1f72d3be7c8ec4
Parents: 12b5170
Author: William San Filippo <wi...@runtime.io>
Authored: Wed Dec 28 13:40:41 2016 -0800
Committer: William San Filippo <wi...@runtime.io>
Committed: Wed Dec 28 13:42:59 2016 -0800
----------------------------------------------------------------------
hw/bsp/nrf52840pdk/boot-nrf52840aa.ld | 26 +
hw/bsp/nrf52840pdk/bsp.yml | 62 +
hw/bsp/nrf52840pdk/include/bsp/boards.h | 19 +
hw/bsp/nrf52840pdk/include/bsp/bsp.h | 53 +
hw/bsp/nrf52840pdk/include/bsp/cmsis_nvic.h | 29 +
hw/bsp/nrf52840pdk/nrf52840aa.ld | 26 +
hw/bsp/nrf52840pdk/nrf52840pdk_debug.sh | 46 +
hw/bsp/nrf52840pdk/nrf52840pdk_download.sh | 40 +
hw/bsp/nrf52840pdk/nrf52840pdk_no_boot.ld | 191 +
hw/bsp/nrf52840pdk/pkg.yml | 94 +
hw/bsp/nrf52840pdk/split-nrf52840pdk.ld | 204 +
.../src/arch/cortex_m4/gcc_startup_nrf52840.s | 312 +
.../arch/cortex_m4/gcc_startup_nrf52_split.s | 151 +
hw/bsp/nrf52840pdk/src/hal_bsp.c | 204 +
hw/bsp/nrf52840pdk/src/sbrk.c | 59 +
hw/bsp/nrf52840pdk/syscfg.yml | 103 +
hw/mcu/nordic/nrf52xxx/include/mcu/cortex_m4.h | 5 +
hw/mcu/nordic/nrf52xxx/include/mcu/mcu.h | 6 +-
hw/mcu/nordic/nrf52xxx/src/hal_flash.c | 2 -
hw/mcu/nordic/nrf52xxx/src/hal_gpio.c | 62 +-
hw/mcu/nordic/nrf52xxx/src/hal_i2c.c | 2 -
hw/mcu/nordic/nrf52xxx/src/hal_os_tick.c | 2 +-
hw/mcu/nordic/nrf52xxx/src/hal_spi.c | 2 +-
hw/mcu/nordic/nrf52xxx/src/hal_timer.c | 3 +-
hw/mcu/nordic/nrf52xxx/src/hal_watchdog.c | 3 +-
hw/mcu/nordic/nrf52xxx/src/nrf52_hw_id.c | 4 +-
hw/mcu/nordic/nrf52xxx/src/system_nrf52.c | 175 +-
.../components/device/nrf.h | 25 +-
.../components/device/nrf51_to_nrf52840.h | 567 +
.../components/device/nrf52840.h | 2417 +++
.../components/device/nrf52840_bitfields.h | 14633 +++++++++++++++++
.../components/device/nrf52840_peripherals.h | 240 +
.../components/device/nrf52_to_nrf52840.h | 88 +
.../components/toolchain/system_nrf52840.c | 209 +
.../components/toolchain/system_nrf52840.h | 69 +
35 files changed, 20099 insertions(+), 34 deletions(-)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/boot-nrf52840aa.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/boot-nrf52840aa.ld b/hw/bsp/nrf52840pdk/boot-nrf52840aa.ld
new file mode 100755
index 0000000..f484162
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/boot-nrf52840aa.ld
@@ -0,0 +1,26 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x8000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000
+}
+
+/* The bootloader does not contain an image header */
+_imghdr_size = 0x0;
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/bsp.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/bsp.yml b/hw/bsp/nrf52840pdk/bsp.yml
new file mode 100644
index 0000000..16f878b
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/bsp.yml
@@ -0,0 +1,62 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+bsp.arch: cortex_m4
+bsp.compiler: compiler/arm-none-eabi-m4
+bsp.linkerscript:
+ - "hw/bsp/nrf52840pdk/nrf52840aa.ld"
+ - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+bsp.linkerscript.BOOT_LOADER.OVERWRITE:
+ - "hw/bsp/nrf52840pdk/boot-nrf52840aa.ld"
+ - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+bsp.part2linkerscript: "hw/bsp/nrf52840pdk/split-nrf52840pdk.ld"
+bsp.downloadscript: "hw/bsp/nrf52840pdk/nrf52840pdk_download.sh"
+bsp.debugscript: "hw/bsp/nrf52840pdk/nrf52840pdk_debug.sh"
+
+bsp.flash_map:
+ areas:
+ # System areas.
+ FLASH_AREA_BOOTLOADER:
+ device: 0
+ offset: 0x00000000
+ size: 32kB
+ FLASH_AREA_IMAGE_0:
+ device: 0
+ offset: 0x0000c000
+ size: 472kB
+ FLASH_AREA_IMAGE_1:
+ device: 0
+ offset: 0x00082000
+ size: 472kB
+ FLASH_AREA_IMAGE_SCRATCH:
+ device: 0
+ offset: 0x000f8000
+ size: 16kB
+
+ # User areas.
+ FLASH_AREA_REBOOT_LOG:
+ user_id: 0
+ device: 0
+ offset: 0x00008000
+ size: 16kB
+ FLASH_AREA_NFFS:
+ user_id: 1
+ device: 0
+ offset: 0x000fc000
+ size: 16kB
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/include/bsp/boards.h
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/include/bsp/boards.h b/hw/bsp/nrf52840pdk/include/bsp/boards.h
new file mode 100644
index 0000000..560c31f
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/include/bsp/boards.h
@@ -0,0 +1,19 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/include/bsp/bsp.h
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/include/bsp/bsp.h b/hw/bsp/nrf52840pdk/include/bsp/bsp.h
new file mode 100644
index 0000000..930ee80
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/include/bsp/bsp.h
@@ -0,0 +1,53 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef H_BSP_H
+#define H_BSP_H
+
+#include <inttypes.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define special stackos sections */
+#define sec_data_core __attribute__((section(".data.core")))
+#define sec_bss_core __attribute__((section(".bss.core")))
+#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+/* More convenient section placement macros. */
+#define bssnz_t sec_bss_nz_core
+
+extern uint8_t _ram_start;
+#define RAM_SIZE 0x40000
+
+/* LED pins */
+#define LED_BLINK_PIN (13)
+#define LED_2 (14)
+
+/* UART info */
+#define CONSOLE_UART "uart0"
+
+#define NFFS_AREA_MAX (8)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_BSP_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/include/bsp/cmsis_nvic.h
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/include/bsp/cmsis_nvic.h b/hw/bsp/nrf52840pdk/include/bsp/cmsis_nvic.h
new file mode 100644
index 0000000..51b6eb6
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/include/bsp/cmsis_nvic.h
@@ -0,0 +1,29 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include <stdint.h>
+
+#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "nrf52840.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_Relocate(void);
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/nrf52840aa.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/nrf52840aa.ld b/hw/bsp/nrf52840pdk/nrf52840aa.ld
new file mode 100755
index 0000000..5928d93
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/nrf52840aa.ld
@@ -0,0 +1,26 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x0000c000, LENGTH = 0x76000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000
+}
+
+/* This linker script is used for images and thus contains an image header */
+_imghdr_size = 0x20;
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/nrf52840pdk_debug.sh
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/nrf52840pdk_debug.sh b/hw/bsp/nrf52840pdk/nrf52840pdk_debug.sh
new file mode 100755
index 0000000..c9ce6d9
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/nrf52840pdk_debug.sh
@@ -0,0 +1,46 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - RESET set if target should be reset when attaching
+# - NO_GDB set if we should not start gdb to debug
+#
+
+. $CORE_PATH/hw/scripts/jlink.sh
+
+FILE_NAME=$BIN_BASENAME.elf
+
+if [ $# -gt 2 ]; then
+ SPLIT_ELF_NAME=$3.elf
+ # TODO -- this magic number 0x82000 is the location of the second image
+ # slot. we should either get this from a flash map file or somehow learn
+ # this from the image itself
+ EXTRA_GDB_CMDS="add-symbol-file $SPLIT_ELF_NAME 0xc000 -readnow"
+fi
+
+JLINK_DEV="nRF52"
+
+jlink_debug
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/nrf52840pdk_download.sh
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/nrf52840pdk_download.sh b/hw/bsp/nrf52840pdk/nrf52840pdk_download.sh
new file mode 100755
index 0000000..08d45b4
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/nrf52840pdk_download.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+
+. $CORE_PATH/hw/scripts/jlink.sh
+
+if [ "$MFG_IMAGE" ]; then
+ FLASH_OFFSET=0x0
+fi
+
+JLINK_DEV="nRF52"
+
+common_file_to_load
+jlink_load
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/nrf52840pdk_no_boot.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/nrf52840pdk_no_boot.ld b/hw/bsp/nrf52840pdk/nrf52840pdk_no_boot.ld
new file mode 100755
index 0000000..8ae27ec
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/nrf52840pdk_no_boot.ld
@@ -0,0 +1,191 @@
+/* Linker script for Nordic Semiconductor nRF5 devices
+ *
+ * Version: Sourcery G++ 4.5-1
+ * Support: https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __bssnz_start__
+ * __bssnz_end__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ __isr_vector_start = .;
+ KEEP(*(.isr_vector))
+ __isr_vector_end = .;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ *(.eh_frame*)
+ . = ALIGN(4);
+ } > FLASH
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ . = ALIGN(4);
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .vector_relocation :
+ {
+ . = ALIGN(4);
+ __vector_tbl_reloc__ = .;
+ . = . + (__isr_vector_end - __isr_vector_start);
+ . = ALIGN(4);
+ } > RAM
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ *(.preinit_array)
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ *(SORT(.init_array.*))
+ *(.init_array)
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ *(SORT(.fini_array.*))
+ *(.fini_array)
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ *(.jcr)
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ } > RAM
+
+ /* Non-zeroed BSS. This section is similar to BSS, with the following
+ * caveat:
+ * 1. It does not get zeroed at init-time.
+ */
+ .bssnz :
+ {
+ . = ALIGN(4);
+ __bssnz_start__ = .;
+ *(.bss.core.nz*)
+ . = ALIGN(4);
+ __bssnz_end__ = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ /* Heap starts after BSS */
+ __HeapBase = .;
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Top of head is the bottom of the stack */
+ __HeapLimit = __StackLimit;
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack")
+}
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/pkg.yml b/hw/bsp/nrf52840pdk/pkg.yml
new file mode 100644
index 0000000..b0e599c
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/pkg.yml
@@ -0,0 +1,94 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/nrf52840pdk
+pkg.type: bsp
+pkg.description: BSP definition for the Nordic nRF52840 PDK (PCA 10056).
+pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - nrf52840
+ - nrf52840pdk
+
+pkg.cflags:
+ # Nordic SDK files require these defines.
+ - '-DADC_ENABLED=0'
+ - '-DCLOCK_ENABLED=1'
+ - '-DCOMP_ENABLED=1'
+ - '-DEGU_ENABLED=0'
+ - '-DGPIOTE_ENABLED=1'
+ - '-DI2S_ENABLED=1'
+ - '-DLPCOMP_ENABLED=1'
+ - '-DNRF52840_XXAA'
+ - '-DPDM_ENABLED=0'
+ - '-DPERIPHERAL_RESOURCE_SHARING_ENABLED=1'
+ - '-DPWM0_ENABLED=1'
+ - '-DPWM1_ENABLED=0'
+ - '-DPWM2_ENABLED=0'
+ - '-DQDEC_ENABLED=1'
+ - '-DRNG_ENABLED=1'
+ - '-DRTC0_ENABLED=0'
+ - '-DRTC1_ENABLED=0'
+ - '-DRTC2_ENABLED=0'
+ - '-DSAADC_ENABLED=1'
+ - '-DSPI_MASTER_0_ENABLE=1'
+ - '-DSPI0_CONFIG_MISO_PIN=25'
+ - '-DSPI0_CONFIG_MOSI_PIN=24'
+ - '-DSPI0_CONFIG_SCK_PIN=23'
+ - '-DSPI0_ENABLED=1'
+ - '-DSPI0_USE_EASY_DMA=1'
+ - '-DSPI1_ENABLED=0'
+ - '-DSPI2_ENABLED=0'
+ - '-DSPIS0_CONFIG_MISO_PIN=25'
+ - '-DSPIS0_CONFIG_MOSI_PIN=24'
+ - '-DSPIS0_CONFIG_SCK_PIN=23'
+ - '-DSPIS0_ENABLED=1'
+ - '-DSPIS1_CONFIG_MISO_PIN=4'
+ - '-DSPIS1_CONFIG_MOSI_PIN=3'
+ - '-DSPIS1_CONFIG_SCK_PIN=2'
+ - '-DSPIS1_ENABLED=0'
+ - '-DSPIS2_ENABLED=0'
+ - '-DTIMER0_ENABLED=1'
+ - '-DTIMER1_ENABLED=0'
+ - '-DTIMER2_ENABLED=0'
+ - '-DTIMER3_ENABLED=0'
+ - '-DTIMER4_ENABLED=0'
+ - '-DTWI0_CONFIG_SCL=27'
+ - '-DTWI0_CONFIG_SDA=26'
+ - '-DTWI0_ENABLED=1'
+ - '-DTWI1_ENABLED=1'
+ - '-DTWIS0_ENABLED=1'
+ - '-DTWIS1_ENABLED=0'
+ - '-DUART0_ENABLED=1'
+ - '-DWDT_ENABLED=1'
+
+pkg.deps:
+ - boot/bootutil
+ - hw/mcu/nordic/nrf52xxx
+ - libc/baselibc
+ - sys/flash_map
+
+pkg.deps.BLE_DEVICE:
+ - hw/drivers/nimble/nrf52
+
+pkg.deps.UART_0:
+ - hw/drivers/uart/uart_hal
+
+pkg.deps.UART_1:
+ - hw/drivers/uart/uart_bitbang
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/split-nrf52840pdk.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/split-nrf52840pdk.ld b/hw/bsp/nrf52840pdk/split-nrf52840pdk.ld
new file mode 100755
index 0000000..1985aa1
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/split-nrf52840pdk.ld
@@ -0,0 +1,204 @@
+/* Linker script for Nordic Semiconductor nRF5 devices
+ *
+ * Version: Sourcery G++ 4.5-1
+ * Support: https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00082000, LENGTH = 0x76000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __bssnz_start__
+ * __bssnz_end__
+ */
+ENTRY(Reset_Handler_split)
+
+SECTIONS
+{
+ .imghdr (NOLOAD):
+ {
+ . = . + 0x20;
+ } > FLASH
+
+ .text :
+ {
+ __split_isr_vector_start = .;
+ KEEP(*(.isr_vector_split))
+ __split_isr_vector_end = .;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ *(.eh_frame*)
+ . = ALIGN(4);
+ } > FLASH
+
+
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ . = ALIGN(4);
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ /* save RAM used by the split image. This assumes that
+ * the loader uses all the RAM up to its HeapBase */
+ .loader_ram_contents :
+ {
+ _loader_ram_start = .;
+
+ /* this symbol comes from the loader linker */
+ . = . + (ABSOLUTE(__HeapBase_loader) - _loader_ram_start);
+ _loader_ram_end = .;
+ } > RAM
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ *(.preinit_array)
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ *(SORT(.init_array.*))
+ *(.init_array)
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ *(SORT(.fini_array.*))
+ *(.fini_array)
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ *(.jcr)
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ } > RAM
+
+ /* Non-zeroed BSS. This section is similar to BSS, with the following two
+ * caveats:
+ * 1. It does not get zeroed at init-time.
+ */
+ .bssnz :
+ {
+ . = ALIGN(4);
+ __bssnz_start__ = .;
+ *(.bss.core.nz*)
+ . = ALIGN(4);
+ __bssnz_end__ = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ /* Heap starts after BSS */
+ __HeapBase = .;
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ _ram_start = ORIGIN(RAM);
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Top of head is the bottom of the stack */
+ __HeapLimit = __StackLimit;
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack")
+}
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/src/arch/cortex_m4/gcc_startup_nrf52840.s
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/src/arch/cortex_m4/gcc_startup_nrf52840.s b/hw/bsp/nrf52840pdk/src/arch/cortex_m4/gcc_startup_nrf52840.s
new file mode 100755
index 0000000..a7a9c96
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/src/arch/cortex_m4/gcc_startup_nrf52840.s
@@ -0,0 +1,312 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv7e-m
+
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemoryManagement_Handler
+ .long BusFault_Handler
+ .long UsageFault_Handler
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long POWER_CLOCK_IRQHandler
+ .long RADIO_IRQHandler
+ .long UARTE0_UART0_IRQHandler
+ .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ .long NFCT_IRQHandler
+ .long GPIOTE_IRQHandler
+ .long SAADC_IRQHandler
+ .long TIMER0_IRQHandler
+ .long TIMER1_IRQHandler
+ .long TIMER2_IRQHandler
+ .long RTC0_IRQHandler
+ .long TEMP_IRQHandler
+ .long RNG_IRQHandler
+ .long ECB_IRQHandler
+ .long CCM_AAR_IRQHandler
+ .long WDT_IRQHandler
+ .long RTC1_IRQHandler
+ .long QDEC_IRQHandler
+ .long COMP_LPCOMP_IRQHandler
+ .long SWI0_EGU0_IRQHandler
+ .long SWI1_EGU1_IRQHandler
+ .long SWI2_EGU2_IRQHandler
+ .long SWI3_EGU3_IRQHandler
+ .long SWI4_EGU4_IRQHandler
+ .long SWI5_EGU5_IRQHandler
+ .long TIMER3_IRQHandler
+ .long TIMER4_IRQHandler
+ .long PWM0_IRQHandler
+ .long PDM_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long MWU_IRQHandler
+ .long PWM1_IRQHandler
+ .long PWM2_IRQHandler
+ .long SPIM2_SPIS2_SPI2_IRQHandler
+ .long RTC2_IRQHandler
+ .long I2S_IRQHandler
+ .long FPU_IRQHandler
+ .long USBD_IRQHandler
+ .long UARTE1_IRQHandler
+ .long QSPI_IRQHandler
+ .long CRYPTOCELL_IRQHandler
+ .long SPIM3_IRQHandler
+ .long 0 /*Reserved */
+ .long PWM3_IRQHandler
+
+
+ .size __isr_vector, . - __isr_vector
+
+/* Reset Handler */
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ .fnstart
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+
+.LC0:
+
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler,.-Reset_Handler
+
+ .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+
+ .weak MemoryManagement_Handler
+ .type MemoryManagement_Handler, %function
+MemoryManagement_Handler:
+ B .
+ .size MemoryManagement_Handler, . - MemoryManagement_Handler
+
+
+ .weak BusFault_Handler
+ .type BusFault_Handler, %function
+BusFault_Handler:
+ B .
+ .size BusFault_Handler, . - BusFault_Handler
+
+
+ .weak UsageFault_Handler
+ .type UsageFault_Handler, %function
+UsageFault_Handler:
+ B .
+ .size UsageFault_Handler, . - UsageFault_Handler
+
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+
+ .weak DebugMon_Handler
+ .type DebugMon_Handler, %function
+DebugMon_Handler:
+ b .
+ .size DebugMon_Handler, . - DebugMon_Handler
+
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ POWER_CLOCK_IRQHandler
+ IRQ RADIO_IRQHandler
+ IRQ UARTE0_UART0_IRQHandler
+ IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ IRQ NFCT_IRQHandler
+ IRQ GPIOTE_IRQHandler
+ IRQ SAADC_IRQHandler
+ IRQ TIMER0_IRQHandler
+ IRQ TIMER1_IRQHandler
+ IRQ TIMER2_IRQHandler
+ IRQ RTC0_IRQHandler
+ IRQ TEMP_IRQHandler
+ IRQ RNG_IRQHandler
+ IRQ ECB_IRQHandler
+ IRQ CCM_AAR_IRQHandler
+ IRQ WDT_IRQHandler
+ IRQ RTC1_IRQHandler
+ IRQ QDEC_IRQHandler
+ IRQ COMP_LPCOMP_IRQHandler
+ IRQ SWI0_EGU0_IRQHandler
+ IRQ SWI1_EGU1_IRQHandler
+ IRQ SWI2_EGU2_IRQHandler
+ IRQ SWI3_EGU3_IRQHandler
+ IRQ SWI4_EGU4_IRQHandler
+ IRQ SWI5_EGU5_IRQHandler
+ IRQ TIMER3_IRQHandler
+ IRQ TIMER4_IRQHandler
+ IRQ PWM0_IRQHandler
+ IRQ PDM_IRQHandler
+ IRQ MWU_IRQHandler
+ IRQ PWM1_IRQHandler
+ IRQ PWM2_IRQHandler
+ IRQ SPIM2_SPIS2_SPI2_IRQHandler
+ IRQ RTC2_IRQHandler
+ IRQ I2S_IRQHandler
+ IRQ FPU_IRQHandler
+ IRQ USBD_IRQHandler
+ IRQ UARTE1_IRQHandler
+ IRQ QSPI_IRQHandler
+ IRQ CRYPTOCELL_IRQHandler
+ IRQ SPIM3_IRQHandler
+ IRQ PWM3_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/src/arch/cortex_m4/gcc_startup_nrf52_split.s
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/src/arch/cortex_m4/gcc_startup_nrf52_split.s b/hw/bsp/nrf52840pdk/src/arch/cortex_m4/gcc_startup_nrf52_split.s
new file mode 100755
index 0000000..7d42423
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/src/arch/cortex_m4/gcc_startup_nrf52_split.s
@@ -0,0 +1,151 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv7e-m
+
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector_split
+ .align 2
+ .globl __isr_vector_split
+__isr_vector_split:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler_split /* Reset Handler */
+
+ .size __isr_vector_split, . - __isr_vector_split
+
+/* Reset Handler */
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler_split
+ .type Reset_Handler_split, %function
+Reset_Handler_split:
+ .fnstart
+
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+
+.LC0:
+ ldr r1, =__etext_loader
+ ldr r2, =__data_start___loader
+ ldr r3, =__data_end___loader
+
+ subs r3, r2
+ ble .LC2
+
+.LC3:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC3
+.LC2:
+
+ subs r0, r0
+ ldr r2, =__bss_start___loader
+ ldr r3, =__bss_end___loader
+
+ subs r3, r2
+ ble .LC4
+
+.LC5:
+ subs r3, 4
+ str r0, [r2,r3]
+ bgt .LC5
+.LC4:
+
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler_split,.-Reset_Handler_split
+
+ .section ".text"
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/src/hal_bsp.c b/hw/bsp/nrf52840pdk/src/hal_bsp.c
new file mode 100644
index 0000000..e53d53b
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/src/hal_bsp.c
@@ -0,0 +1,204 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <assert.h>
+#include <nrf52840.h>
+#include "os/os_cputime.h"
+#include "syscfg/syscfg.h"
+#include "sysflash/sysflash.h"
+#include "flash_map/flash_map.h"
+#include "hal/hal_bsp.h"
+#include "hal/hal_flash.h"
+#include "hal/hal_spi.h"
+#include "hal/hal_watchdog.h"
+#include "hal/hal_i2c.h"
+#include "mcu/nrf52_hal.h"
+#include "uart/uart.h"
+#include "uart_hal/uart_hal.h"
+#include "os/os_dev.h"
+#include "bsp.h"
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+static const struct nrf52_uart_cfg os_bsp_uart0_cfg = {
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+};
+#endif
+
+#if MYNEWT_VAL(UART_1)
+static struct uart_dev os_bsp_bitbang_uart1;
+static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
+ .ubc_rxpin = MYNEWT_VAL(UART_1_PIN_TX),
+ .ubc_txpin = MYNEWT_VAL(UART_1_PIN_RX),
+ .ubc_cputimer_freq = MYNEWT_VAL(CLOCK_FREQ),
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+/*
+ * NOTE: Our HAL expects that the SS pin, if used, is treated as a gpio line
+ * and is handled outside the SPI routines.
+ */
+static const struct nrf52_hal_spi_cfg os_bsp_spi0m_cfg = {
+ .sck_pin = 45,
+ .mosi_pin = 46,
+ .miso_pin = 47,
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_SLAVE)
+static const struct nrf52_hal_spi_cfg os_bsp_spi0s_cfg = {
+ .sck_pin = 45,
+ .mosi_pin = 46,
+ .miso_pin = 47,
+ .ss_pin = 44,
+};
+#endif
+
+#if MYNEWT_VAL(I2C_0)
+static const struct nrf52_hal_i2c_cfg hal_i2c_cfg = {
+ .scl_pin = 27,
+ .sda_pin = 26,
+ .i2c_frequency = 100 /* 100 kHz */
+};
+#endif
+
+/*
+ * What memory to include in coredump.
+ */
+static const struct hal_bsp_mem_dump dump_cfg[] = {
+ [0] = {
+ .hbmd_start = &_ram_start,
+ .hbmd_size = RAM_SIZE
+ }
+};
+
+const struct hal_flash *
+hal_bsp_flash_dev(uint8_t id)
+{
+ /*
+ * Internal flash mapped to id 0.
+ */
+ if (id != 0) {
+ return NULL;
+ }
+ return &nrf52k_flash_dev;
+}
+
+const struct hal_bsp_mem_dump *
+hal_bsp_core_dump(int *area_cnt)
+{
+ *area_cnt = sizeof(dump_cfg) / sizeof(dump_cfg[0]);
+ return dump_cfg;
+}
+
+int
+hal_bsp_power_state(int state)
+{
+ return (0);
+}
+
+/**
+ * Returns the configured priority for the given interrupt. If no priority
+ * configured, return the priority passed in
+ *
+ * @param irq_num
+ * @param pri
+ *
+ * @return uint32_t
+ */
+uint32_t
+hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
+{
+ uint32_t cfg_pri;
+
+ switch (irq_num) {
+ /* Radio gets highest priority */
+ case RADIO_IRQn:
+ cfg_pri = 0;
+ break;
+ default:
+ cfg_pri = pri;
+ }
+ return cfg_pri;
+}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+#if MYNEWT_VAL(TIMER_0)
+ rc = hal_timer_init(0, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_1)
+ rc = hal_timer_init(1, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_2)
+ rc = hal_timer_init(2, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_3)
+ rc = hal_timer_init(3, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_4)
+ rc = hal_timer_init(4, NULL);
+ assert(rc == 0);
+#endif
+
+ /* Set cputime to count at 1 usec increments */
+ rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
+ assert(rc == 0);
+
+#if MYNEWT_VAL(I2C_0)
+ rc = hal_i2c_init(0, (void *)&hal_i2c_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+ rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(SPI_0_SLAVE)
+ rc = hal_spi_init(0, (void *)&os_bsp_spi0s_cfg, HAL_SPI_TYPE_SLAVE);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_1)
+ rc = os_dev_create((struct os_dev *) &os_bsp_bitbang_uart1, "uart1",
+ OS_DEV_INIT_PRIMARY, 0, uart_bitbang_init, (void *)&os_bsp_uart1_cfg);
+ assert(rc == 0);
+#endif
+
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/src/sbrk.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/src/sbrk.c b/hw/bsp/nrf52840pdk/src/sbrk.c
new file mode 100644
index 0000000..5df43c9
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/src/sbrk.c
@@ -0,0 +1,59 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <hal/hal_bsp.h>
+
+/* put these in the data section so they are not cleared by _start */
+static char *sbrkBase __attribute__ ((section (".data")));
+static char *sbrkLimit __attribute__ ((section (".data")));
+static char *brk __attribute__ ((section (".data")));
+
+void
+_sbrkInit(char *base, char *limit) {
+ sbrkBase = base;
+ sbrkLimit = limit;
+ brk = base;
+}
+
+void *
+_sbrk(int incr)
+{
+ void *prev_brk;
+
+ if (incr < 0) {
+ /* Returning memory to the heap. */
+ incr = -incr;
+ if (brk - incr < sbrkBase) {
+ prev_brk = (void *)-1;
+ } else {
+ prev_brk = brk;
+ brk -= incr;
+ }
+ } else {
+ /* Allocating memory from the heap. */
+ if (sbrkLimit - brk >= incr) {
+ prev_brk = brk;
+ brk += incr;
+ } else {
+ prev_brk = (void *)-1;
+ }
+ }
+
+ return prev_brk;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/bsp/nrf52840pdk/syscfg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52840pdk/syscfg.yml b/hw/bsp/nrf52840pdk/syscfg.yml
new file mode 100644
index 0000000..d6701eb
--- /dev/null
+++ b/hw/bsp/nrf52840pdk/syscfg.yml
@@ -0,0 +1,103 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Package: hw/bsp/nrf52840pdk
+
+syscfg.defs:
+ BSP_NRF52840:
+ description: 'TBD'
+ value: 1
+
+ CLOCK_FREQ:
+ description: 'TBD'
+ value: 1000000
+ XTAL_32768:
+ description: 'TBD'
+ value: 1
+ UART_0:
+ description: 'TBD'
+ value: 1
+ UART_0_PIN_TX:
+ description: 'TBD'
+ value: 6
+ UART_0_PIN_RX:
+ description: 'TBD'
+ value: 8
+ UART_0_PIN_RTS:
+ description: 'TBD'
+ value: 5
+ UART_0_PIN_CTS:
+ description: 'TBD'
+ value: 7
+
+ UART_1:
+ description: 'Bitbanger UART'
+ value: 0
+
+ SPI_0_MASTER:
+ description: 'SPI 0 master'
+ value: 0
+ restrictions:
+ - "!SPI_0_SLAVE"
+ SPI_0_MASTER_SS_PIN:
+ description: 'SPI 0 (master) SS pin number.'
+ value: 44
+ SPI_1_MASTER:
+ description: 'SPI 1 master'
+ value: 0
+ restrictions:
+ - "!SPI_1_SLAVE"
+ SPI_1_MASTER_SS_PIN:
+ description: 'SPI 1 (master) SS pin number.'
+ value: -1
+ SPI_0_SLAVE:
+ description: 'SPI 0 slave'
+ value: 0
+ restrictions:
+ - "!SPI_0_MASTER"
+ SPI_1_SLAVE:
+ description: 'SPI 1 slave'
+ value: 0
+ restrictions:
+ - "!SPI_1_MASTER"
+
+ TIMER_0:
+ description: 'NRF52840 Timer 0'
+ value: 1
+ TIMER_1:
+ description: 'NRF52840 Timer 1'
+ value: 0
+ TIMER_2:
+ description: 'NRF52840 Timer 2'
+ value: 0
+ TIMER_3:
+ description: 'NRF52840 Timer 3'
+ value: 0
+ TIMER_4:
+ description: 'NRF52840 Timer 4'
+ value: 0
+
+ I2C_0:
+ description: 'NRF52840 I2C (TWI) interface 0'
+ value: '0'
+
+syscfg.vals:
+ CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
+ REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG
+ NFFS_FLASH_AREA: FLASH_AREA_NFFS
+ COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/mcu/nordic/nrf52xxx/include/mcu/cortex_m4.h
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf52xxx/include/mcu/cortex_m4.h b/hw/mcu/nordic/nrf52xxx/include/mcu/cortex_m4.h
index 66fa7fe..61de685 100644
--- a/hw/mcu/nordic/nrf52xxx/include/mcu/cortex_m4.h
+++ b/hw/mcu/nordic/nrf52xxx/include/mcu/cortex_m4.h
@@ -21,7 +21,12 @@
#define __MCU_CORTEX_M4_H__
#include "syscfg/syscfg.h"
+
+#ifdef NRF52840_XXAA
+#include "nrf52840.h"
+#else
#include "nrf52.h"
+#endif
#ifdef __cplusplus
extern "C" {
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/mcu/nordic/nrf52xxx/include/mcu/mcu.h
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf52xxx/include/mcu/mcu.h b/hw/mcu/nordic/nrf52xxx/include/mcu/mcu.h
index 24b5981..9886d2b 100644
--- a/hw/mcu/nordic/nrf52xxx/include/mcu/mcu.h
+++ b/hw/mcu/nordic/nrf52xxx/include/mcu/mcu.h
@@ -25,9 +25,13 @@ extern "C" {
#endif
/*
- * Defines for naming GPIOs.
+ * Defines for naming GPIOs. NOTE: the nordic chip docs use numeric labels for
+ * ports. Port A corresponds to Port 0, B to 1, etc. The nrf52832 has only one
+ * port and thus uses pins 0 - 31. The nrf52840 has two ports but Port 1 only
+ * has 16 pins.
*/
#define MCU_GPIO_PORTA(pin) ((0 * 16) + (pin))
+#define MCU_GPIO_PORTB(pin) ((1 * 16) + (pin))
#ifdef __cplusplus
}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/mcu/nordic/nrf52xxx/src/hal_flash.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf52xxx/src/hal_flash.c b/hw/mcu/nordic/nrf52xxx/src/hal_flash.c
index c727581..6627cdf 100644
--- a/hw/mcu/nordic/nrf52xxx/src/hal_flash.c
+++ b/hw/mcu/nordic/nrf52xxx/src/hal_flash.c
@@ -19,10 +19,8 @@
#include <string.h>
#include <assert.h>
-
#include "nrf.h"
#include "mcu/nrf52_hal.h"
-
#include <hal/hal_flash_int.h>
#define NRF52K_FLASH_SECTOR_SZ 4096
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/mcu/nordic/nrf52xxx/src/hal_gpio.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf52xxx/src/hal_gpio.c b/hw/mcu/nordic/nrf52xxx/src/hal_gpio.c
index 979eb15..b1abef2 100644
--- a/hw/mcu/nordic/nrf52xxx/src/hal_gpio.c
+++ b/hw/mcu/nordic/nrf52xxx/src/hal_gpio.c
@@ -20,8 +20,7 @@
#include "hal/hal_gpio.h"
#include "bsp/cmsis_nvic.h"
#include <stdlib.h>
-#include "nrf52.h"
-#include "nrf52_bitfields.h"
+#include "nrf.h"
#include <assert.h>
/* XXX:
@@ -31,8 +30,33 @@
*
*/
-/* GPIO pin mapping */
+/*
+ * GPIO pin mapping
+ *
+ * The logical GPIO pin numbers (0 to N) are mapped to ports in the following
+ * manner:
+ * pins 0 - 31: Port 0
+ * pins 32 - 48: Port 1.
+ *
+ * The nrf52832 has only one port with 32 pins. The nrf52840 has 48 pins and
+ * uses two ports.
+ *
+ * NOTE: in order to save code space, there is no checking done to see if the
+ * user specifies a pin that is not used by the processor. If an invalid pin
+ * number is used unexpected and/or erroneous behavior will result.
+ */
+#ifdef NRF52
+#define HAL_GPIO_PORT(pin) (NRF_P0)
#define HAL_GPIO_MASK(pin) (1 << pin)
+#define HAL_GPIOTE_PIN_MASK GPIOTE_CONFIG_PSEL_Msk
+#endif
+
+#ifdef NRF52840_XXAA
+#define HAL_GPIO_INDEX(pin) ((pin) & 0x1F)
+#define HAL_GPIO_PORT(pin) ((pin) > 31 ? NRF_P1 : NRF_P0)
+#define HAL_GPIO_MASK(pin) (1 << HAL_GPIO_INDEX(pin))
+#define HAL_GPIOTE_PIN_MASK (0x3FUL << GPIOTE_CONFIG_PSEL_Pos)
+#endif
/* GPIO interrupts */
#define HAL_GPIO_MAX_IRQ 8
@@ -59,6 +83,7 @@ int
hal_gpio_init_in(int pin, hal_gpio_pull_t pull)
{
uint32_t conf;
+ NRF_GPIO_Type *port;
switch (pull) {
case HAL_GPIO_PULL_UP:
@@ -73,8 +98,9 @@ hal_gpio_init_in(int pin, hal_gpio_pull_t pull)
break;
}
- NRF_P0->PIN_CNF[pin] = conf;
- NRF_P0->DIRCLR = HAL_GPIO_MASK(pin);
+ port = HAL_GPIO_PORT(pin);
+ port->PIN_CNF[pin] = conf;
+ port->DIRCLR = HAL_GPIO_MASK(pin);
return 0;
}
@@ -93,13 +119,17 @@ hal_gpio_init_in(int pin, hal_gpio_pull_t pull)
int
hal_gpio_init_out(int pin, int val)
{
+ NRF_GPIO_Type *port;
+
+ port = HAL_GPIO_PORT(pin);
if (val) {
- NRF_P0->OUTSET = HAL_GPIO_MASK(pin);
+ port->OUTSET = HAL_GPIO_MASK(pin);
} else {
- NRF_P0->OUTCLR = HAL_GPIO_MASK(pin);
+ port->OUTCLR = HAL_GPIO_MASK(pin);
}
- NRF_P0->PIN_CNF[pin] = GPIO_PIN_CNF_DIR_Output;
- NRF_P0->DIRSET = HAL_GPIO_MASK(pin);
+ port->PIN_CNF[pin] = GPIO_PIN_CNF_DIR_Output;
+ port->DIRSET = HAL_GPIO_MASK(pin);
+
return 0;
}
@@ -114,10 +144,13 @@ hal_gpio_init_out(int pin, int val)
void
hal_gpio_write(int pin, int val)
{
+ NRF_GPIO_Type *port;
+
+ port = HAL_GPIO_PORT(pin);
if (val) {
- NRF_P0->OUTSET = HAL_GPIO_MASK(pin);
+ port->OUTSET = HAL_GPIO_MASK(pin);
} else {
- NRF_P0->OUTCLR = HAL_GPIO_MASK(pin);
+ port->OUTCLR = HAL_GPIO_MASK(pin);
}
}
@@ -133,7 +166,10 @@ hal_gpio_write(int pin, int val)
int
hal_gpio_read(int pin)
{
- return ((NRF_P0->IN & HAL_GPIO_MASK(pin)) != 0);
+ NRF_GPIO_Type *port;
+
+ port = HAL_GPIO_PORT(pin);
+ return ((port->IN & HAL_GPIO_MASK(pin)) != 0);
}
/**
@@ -219,7 +255,7 @@ hal_gpio_find_pin(int pin)
for (i = 0; i < HAL_GPIO_MAX_IRQ; i++) {
if (hal_gpio_irqs[i].func &&
- (NRF_GPIOTE->CONFIG[i] & GPIOTE_CONFIG_PSEL_Msk) == pin) {
+ (NRF_GPIOTE->CONFIG[i] & HAL_GPIOTE_PIN_MASK) == pin) {
return i;
}
}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/mcu/nordic/nrf52xxx/src/hal_i2c.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf52xxx/src/hal_i2c.c b/hw/mcu/nordic/nrf52xxx/src/hal_i2c.c
index a520f33..e300a5a 100644
--- a/hw/mcu/nordic/nrf52xxx/src/hal_i2c.c
+++ b/hw/mcu/nordic/nrf52xxx/src/hal_i2c.c
@@ -21,9 +21,7 @@
#include <errno.h>
#include <limits.h>
#include <assert.h>
-
#include <os/os_time.h>
-
#include "syscfg/syscfg.h"
#include <hal/hal_i2c.h>
#include <hal/hal_gpio.h>
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/mcu/nordic/nrf52xxx/src/hal_os_tick.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf52xxx/src/hal_os_tick.c b/hw/mcu/nordic/nrf52xxx/src/hal_os_tick.c
index 3e8c7de..67a5bcb 100644
--- a/hw/mcu/nordic/nrf52xxx/src/hal_os_tick.c
+++ b/hw/mcu/nordic/nrf52xxx/src/hal_os_tick.c
@@ -20,7 +20,7 @@
#include <os/os.h>
#include "syscfg/syscfg.h"
#include "hal/hal_os_tick.h"
-#include "nrf52_bitfields.h"
+#include "nrf.h"
#include "bsp/cmsis_nvic.h"
#if MYNEWT_VAL(XTAL_32768)
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/mcu/nordic/nrf52xxx/src/hal_spi.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf52xxx/src/hal_spi.c b/hw/mcu/nordic/nrf52xxx/src/hal_spi.c
index ed43b01..8df7074 100644
--- a/hw/mcu/nordic/nrf52xxx/src/hal_spi.c
+++ b/hw/mcu/nordic/nrf52xxx/src/hal_spi.c
@@ -23,7 +23,7 @@
#include <bsp/cmsis_nvic.h>
#include <hal/hal_spi.h>
#include "mcu/nrf52_hal.h"
-#include "nrf52_bitfields.h"
+#include "nrf.h"
#ifndef min
#define min(a, b) ((a)<(b)?(a):(b))
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/mcu/nordic/nrf52xxx/src/hal_timer.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf52xxx/src/hal_timer.c b/hw/mcu/nordic/nrf52xxx/src/hal_timer.c
index 396ba45..c721903 100644
--- a/hw/mcu/nordic/nrf52xxx/src/hal_timer.c
+++ b/hw/mcu/nordic/nrf52xxx/src/hal_timer.c
@@ -24,8 +24,7 @@
#include "syscfg/syscfg.h"
#include "bsp/cmsis_nvic.h"
#include "hal/hal_timer.h"
-#include "nrf52.h"
-#include "nrf52_bitfields.h"
+#include "nrf.h"
#include "mcu/nrf52_hal.h"
/* IRQ prototype */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/mcu/nordic/nrf52xxx/src/hal_watchdog.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf52xxx/src/hal_watchdog.c b/hw/mcu/nordic/nrf52xxx/src/hal_watchdog.c
index 90ed8f2..e0f457f 100644
--- a/hw/mcu/nordic/nrf52xxx/src/hal_watchdog.c
+++ b/hw/mcu/nordic/nrf52xxx/src/hal_watchdog.c
@@ -20,8 +20,7 @@
#include <assert.h>
#include "hal/hal_watchdog.h"
#include "bsp/cmsis_nvic.h"
-#include "nrf52.h"
-#include "nrf52_bitfields.h"
+#include "nrf.h"
static void
nrf52_hal_wdt_default_handler(void)
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/mcu/nordic/nrf52xxx/src/nrf52_hw_id.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf52xxx/src/nrf52_hw_id.c b/hw/mcu/nordic/nrf52xxx/src/nrf52_hw_id.c
index 3cb7fa6..1a42f6b 100644
--- a/hw/mcu/nordic/nrf52xxx/src/nrf52_hw_id.c
+++ b/hw/mcu/nordic/nrf52xxx/src/nrf52_hw_id.c
@@ -19,10 +19,8 @@
#include <inttypes.h>
#include <string.h>
-
#include <hal/hal_bsp.h>
-
-#include "nrf52.h"
+#include "nrf.h"
#ifndef min
#define min(a, b) ((a)<(b)?(a):(b))
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/mcu/nordic/nrf52xxx/src/system_nrf52.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf52xxx/src/system_nrf52.c b/hw/mcu/nordic/nrf52xxx/src/system_nrf52.c
index ab24c21..424fc35 100644
--- a/hw/mcu/nordic/nrf52xxx/src/system_nrf52.c
+++ b/hw/mcu/nordic/nrf52xxx/src/system_nrf52.c
@@ -32,12 +32,28 @@
#include <stdbool.h>
#include "bsp/cmsis_nvic.h"
#include "nrf.h"
+
+#ifdef NRF52840_XXAA
+#include "system_nrf52840.h"
+#endif
+
+#ifdef NRF52
#include "system_nrf52.h"
+#endif
/*lint ++flb "Enter library region" */
#define __SYSTEM_CLOCK_64M (64000000UL)
+#ifdef NRF52840_XXAA
+static bool errata_36(void);
+static bool errata_98(void);
+static bool errata_103(void);
+static bool errata_115(void);
+static bool errata_120(void);
+#endif
+
+#ifdef NRF52
static bool errata_16(void);
static bool errata_31(void);
static bool errata_32(void);
@@ -46,7 +62,7 @@ static bool errata_37(void);
static bool errata_57(void);
static bool errata_66(void);
static bool errata_108(void);
-
+#endif
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
@@ -63,6 +79,7 @@ void SystemCoreClockUpdate(void)
void SystemInit(void)
{
+#ifdef NRF52
/* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/ */
if (errata_16()){
@@ -131,7 +148,7 @@ void SystemInit(void)
if (errata_108()){
*(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F;
}
-
+
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
@@ -193,13 +210,109 @@ void SystemInit(void)
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
+#endif
+
+#ifdef NRF52840_XXAA
+ /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/ */
+ if (errata_36()){
+ NRF_CLOCK->EVENTS_DONE = 0;
+ NRF_CLOCK->EVENTS_CTTO = 0;
+ NRF_CLOCK->CTIV = 0;
+ }
+ /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/ */
+ if (errata_98()){
+ *(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
+ }
+
+ /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/ */
+ if (errata_103()){
+ NRF_CCM->MAXPACKETSIZE = 0xFBul;
+ }
+
+ /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/ */
+ if (errata_115()){
+ *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
+ }
+
+ /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
+ for your device located at https://infocenter.nordicsemi.com/ */
+ if (errata_120()){
+ *(volatile uint32_t *)0x40029640ul = 0x200ul;
+ }
+
+ /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
+ * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
+ * operations are not used in your code. */
+ #if (__FPU_USED == 1)
+ SCB->CPACR |= (3UL << 20) | (3UL << 22);
+ __DSB();
+ __ISB();
+ #endif
+
+ /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
+ two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
+ normal GPIOs. */
+ #if defined (CONFIG_NFCT_PINS_AS_GPIOS)
+ if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NVIC_SystemReset();
+ }
+ #endif
+
+ /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
+ defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
+ reserved for PinReset and not available as normal GPIO. */
+ #if defined (CONFIG_GPIO_AS_PINRESET)
+ if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+ ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_UICR->PSELRESET[0] = 18;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_UICR->PSELRESET[1] = 18;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ NVIC_SystemReset();
+ }
+ #endif
+
+ /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
+ Specification to see which one). */
+ #if defined (ENABLE_SWO)
+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+ NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+ NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ #endif
+
+ /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
+ Specification to see which ones). */
+ #if defined (ENABLE_TRACE)
+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+ NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+ NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ #endif
+#endif
SystemCoreClockUpdate();
NVIC_Relocate();
}
-
+#ifdef NRF52
static bool errata_16(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){
@@ -306,6 +419,62 @@ static bool errata_108(void)
return false;
}
+#endif
+#ifdef NRF52840_XXAA
+static bool errata_36(void)
+{
+ if ((*(uint32_t *)0x10000130ul == 0x8ul) &&
+ (*(uint32_t *)0x10000134ul == 0x0ul)) {
+ return true;
+ }
+
+ return false;
+}
+
+
+static bool errata_98(void)
+{
+ if ((*(uint32_t *)0x10000130ul == 0x8ul) &&
+ (*(uint32_t *)0x10000134ul == 0x0ul)) {
+ return true;
+ }
+
+ return false;
+}
+
+
+static bool errata_103(void)
+{
+ if ((*(uint32_t *)0x10000130ul == 0x8ul) &&
+ (*(uint32_t *)0x10000134ul == 0x0ul)) {
+ return true;
+ }
+
+ return false;
+}
+
+
+static bool errata_115(void)
+{
+ if ((*(uint32_t *)0x10000130ul == 0x8ul) &&
+ (*(uint32_t *)0x10000134ul == 0x0ul)) {
+ return true;
+ }
+
+ return false;
+}
+
+
+static bool errata_120(void)
+{
+ if ((*(uint32_t *)0x10000130ul == 0x8ul) &&
+ (*(uint32_t *)0x10000134ul == 0x0ul)) {
+ return true;
+ }
+
+ return false;
+}
+#endif
/*lint --flb "Leave library region" */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/device/nrf.h
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/device/nrf.h b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/device/nrf.h
index 031d4ab..fff0b0f 100644
--- a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/device/nrf.h
+++ b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/device/nrf.h
@@ -39,6 +39,18 @@ extern "C" {
#define MDK_MAJOR_VERSION 8
#define MDK_MINOR_VERSION 5
#define MDK_MICRO_VERSION 0
+/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */
+#if defined (NRF52)
+ #ifndef NRF52832_XXAA
+ #define NRF52832_XXAA
+ #endif
+#endif
+
+/* Define NRF52_SERIES for common use in nRF52 series devices. */
+#if defined (NRF52832_XXAA) || defined (NRF52840_XXAA)
+ #define NRF52_SERIES
+#endif
+
#if defined(_WIN32)
/* Do not include nrf51 specific files when building for PC host */
@@ -48,19 +60,24 @@ extern "C" {
/* Do not include nrf51 specific files when building for PC host */
#else
- /* Family selection for family includes. */
+ /* Device selection for device includes. */
#if defined (NRF51)
#include "nrf51.h"
#include "nrf51_bitfields.h"
#include "nrf51_deprecated.h"
- #elif defined (NRF52)
+ #elif defined (NRF52840_XXAA)
+ #include "nrf52840.h"
+ #include "nrf52840_bitfields.h"
+ #include "nrf51_to_nrf52840.h"
+ #include "nrf52_to_nrf52840.h"
+ #elif defined (NRF52832_XXAA)
#include "nrf52.h"
#include "nrf52_bitfields.h"
#include "nrf51_to_nrf52.h"
#include "nrf52_name_change.h"
#else
- #error "Device family must be defined. See nrf.h."
- #endif /* NRF51, NRF52 */
+ #error "Device must be defined. See nrf.h."
+ #endif /* NRF51, NRF52832_XXAA, NRF52840_XXAA */
#include "compiler_abstraction.h"