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Posted to commits@mynewt.apache.org by je...@apache.org on 2021/02/01 07:15:43 UTC
[mynewt-core] branch master updated (69fcf3e -> 730cb4a)
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git.
from 69fcf3e Merge pull request #2458 from vikrant-proxy/tinycrypt-update
new c4fd789 bsp/nucleo-f103rb: Use HSE instead of HSI
new 5bc7c10 stm32/hal_spi: Fix alternate function for STM32F0 SPI_1
new 730cb4a bsp/black_vet6: Fix spiflash sector size
The 3 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
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Summary of changes:
hw/bsp/black_vet6/syscfg.yml | 2 +-
hw/bsp/nucleo-f103rb/syscfg.yml | 6 +++---
hw/mcu/stm/stm32_common/src/hal_spi.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
[mynewt-core] 01/03: bsp/nucleo-f103rb: Use HSE instead of HSI
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit c4fd789a70adca4948f9cb9ee237f84060f4f2fd
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Thu Jan 21 13:09:41 2021 +0100
bsp/nucleo-f103rb: Use HSE instead of HSI
Nucleo board have 8MHz clock generated by on-board
st-link debugger.
This clock has higher accuracy then internal HSI.
Changing from HSI to HSE (both 8MHz) results in:
- System clock increased from 64MHz to 72MHz (maximum)
- Peripherals can operate on higher baud rates.
- Greater stability of system clock that may impact USB
transfers.
---
hw/bsp/nucleo-f103rb/syscfg.yml | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/bsp/nucleo-f103rb/syscfg.yml b/hw/bsp/nucleo-f103rb/syscfg.yml
index 742ec83..01c18bc 100644
--- a/hw/bsp/nucleo-f103rb/syscfg.yml
+++ b/hw/bsp/nucleo-f103rb/syscfg.yml
@@ -28,9 +28,9 @@ syscfg.vals:
NFFS_FLASH_AREA: FLASH_AREA_NFFS
COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
STM32_CLOCK_HSI: 1
- STM32_CLOCK_HSE: 0
- STM32_CLOCK_HSE_BYPASS: 0
- STM32_CLOCK_PLL_MUL: 'RCC_PLL_MUL16'
+ STM32_CLOCK_HSE: 1
+ STM32_CLOCK_HSE_BYPASS: 1
+ STM32_CLOCK_PLL_MUL: 'RCC_PLL_MUL9'
STM32_CLOCK_PREDIV: 'RCC_HSE_PREDIV_DIV1'
STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV2'
[mynewt-core] 03/03: bsp/black_vet6: Fix spiflash sector size
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 730cb4a1f3a67d4f15c01c767466863f9eb5fe13
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Mon Jan 25 12:47:09 2021 +0100
bsp/black_vet6: Fix spiflash sector size
SPIFLASH_SECTOR_SIZE was set to invalid value
preventing SPI flash usage with default settings.
---
hw/bsp/black_vet6/syscfg.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/bsp/black_vet6/syscfg.yml b/hw/bsp/black_vet6/syscfg.yml
index b0cb4f1..c7e719c 100644
--- a/hw/bsp/black_vet6/syscfg.yml
+++ b/hw/bsp/black_vet6/syscfg.yml
@@ -57,7 +57,7 @@ syscfg.vals:
SPIFLASH_MEMORY_TYPE: 0x40
SPIFLASH_MEMORY_CAPACITY: 0x15
SPIFLASH_SECTOR_COUNT: 512
- SPIFLASH_SECTOR_SIZE: 4094
+ SPIFLASH_SECTOR_SIZE: 4096
SPIFLASH_PAGE_SIZE: 256
SPIFLASH_TBP1_TYPICAL: 20
[mynewt-core] 02/03: stm32/hal_spi: Fix alternate function for
STM32F0 SPI_1
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 5bc7c103fb3b00e24e42ab428ef44ec9eb0c38ee
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Fri Jan 22 14:47:00 2021 +0100
stm32/hal_spi: Fix alternate function for STM32F0 SPI_1
Alternate function for SPI2 for STM32F0xx is 0 like
for STM32L0xx and not 5 as for all other MCU's
---
hw/mcu/stm/stm32_common/src/hal_spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mcu/stm/stm32_common/src/hal_spi.c b/hw/mcu/stm/stm32_common/src/hal_spi.c
index 636cde0..9f0222d 100644
--- a/hw/mcu/stm/stm32_common/src/hal_spi.c
+++ b/hw/mcu/stm/stm32_common/src/hal_spi.c
@@ -618,7 +618,7 @@ hal_spi_config(int spi_num, struct hal_spi_settings *settings)
case 1:
__HAL_RCC_SPI2_CLK_ENABLE();
#if !MYNEWT_VAL(MCU_STM32F1)
- #if !MYNEWT_VAL(MCU_STM32L0)
+ #if !MYNEWT_VAL(MCU_STM32L0) && !MYNEWT_VAL(MCU_STM32F0)
gpio.Alternate = GPIO_AF5_SPI2;
#else
gpio.Alternate = GPIO_AF0_SPI2;