[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6117: arch/risc-v/riscv_misaligned: Implement float load/store support

[GitBox <gi...@apache.org>]

xiaoxiang781216 commented on code in PR #6117:
URL: https://github.com/apache/incubator-nuttx/pull/6117#discussion_r855422282


##########
arch/risc-v/src/common/riscv_misaligned.c:
##########
@@ -329,17 +329,92 @@ static bool decode_insn_compressed(uintptr_t *regs, riscv_insn_ctx_t *ctx)
         ctx->len  = 4;
         break;
 
-#  ifdef CONFIG_ARCH_RV32
+#  ifdef CONFIG_ARCH_FPU
+#    ifdef CONFIG_ARCH_RV32
       case INSN_C_FLW:
+
+        /* flw share the same encoding layout with lw */
+
+        imm = insn.lw.imm2 << 2 | insn.lw.imm53 << 3 | insn.lw.imm6 << 6;
+        ctx->dest = (uint8_t *)&regs[REG_F8 + insn.lw.rd];
+        ctx->src  = (uint8_t *)regs[REG_X8 + insn.lw.rs1] + imm;
+        ctx->len  = 4;
+        break;
+
       case INSN_C_FLWSP:
+
+        /* flwsp share the same encoding layout with lwsp */
+
+        imm = insn.lwsp.imm42 << 2 | insn.lwsp.imm5 << 5 |
+              insn.lwsp.imm76 << 6;
+        ctx->dest = (uint8_t *)&regs[REG_F0 + insn.lwsp.rd];
+        ctx->src  = (uint8_t *)regs[REG_SP] + imm;
+        ctx->len  = 4;
+        break;
+
       case INSN_C_FSW:
+
+        /* fsw share the same encoding layout with swsp */

Review Comment:
   swsp->sw?



##########
arch/risc-v/src/common/riscv_misaligned.c:
##########
@@ -329,17 +329,92 @@ static bool decode_insn_compressed(uintptr_t *regs, riscv_insn_ctx_t *ctx)
         ctx->len  = 4;
         break;
 
-#  ifdef CONFIG_ARCH_RV32
+#  ifdef CONFIG_ARCH_FPU
+#    ifdef CONFIG_ARCH_RV32
       case INSN_C_FLW:
+
+        /* flw share the same encoding layout with lw */
+
+        imm = insn.lw.imm2 << 2 | insn.lw.imm53 << 3 | insn.lw.imm6 << 6;
+        ctx->dest = (uint8_t *)&regs[REG_F8 + insn.lw.rd];
+        ctx->src  = (uint8_t *)regs[REG_X8 + insn.lw.rs1] + imm;
+        ctx->len  = 4;
+        break;
+
       case INSN_C_FLWSP:
+
+        /* flwsp share the same encoding layout with lwsp */
+
+        imm = insn.lwsp.imm42 << 2 | insn.lwsp.imm5 << 5 |
+              insn.lwsp.imm76 << 6;
+        ctx->dest = (uint8_t *)&regs[REG_F0 + insn.lwsp.rd];
+        ctx->src  = (uint8_t *)regs[REG_SP] + imm;
+        ctx->len  = 4;
+        break;
+
       case INSN_C_FSW:
+
+        /* fsw share the same encoding layout with swsp */
+
+        imm = insn.sw.imm2 << 2 | insn.sw.imm53 << 3 | insn.sw.imm6 << 6;
+        ctx->dest = (uint8_t *)regs[REG_X8 + insn.sw.rs1] + imm;
+        ctx->src  = (uint8_t *)&regs[REG_F8 + insn.sd.rs2];
+        ctx->len  = 4;
+        break;
+
       case INSN_C_FSWSP:
-#  endif
+
+        /* fswsp share the same encoding layout with fswsp */

Review Comment:
   fswsp->swsp



-- 
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.

To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org

For queries about this service, please contact Infrastructure at:
users@infra.apache.org