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Posted to commits@nuttx.apache.org by ac...@apache.org on 2020/06/17 16:17:51 UTC
[incubator-nuttx] branch master updated (8013f66 -> 67ab8eb)
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 8013f66 boards/arm/imxrt/imxrt1060-evk: Remove deprecated lvgl configs
new fa97e21 stm32l4: clocking fixes (would hang for MSI@48MHz on STM32L476)
new b7d1858 stm32l4: add I2C timings for 48 MHz SYSCLK
new 67ab8eb style fixes
The 3 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/arm/src/stm32l4/stm32l4_i2c.c | 39 +++++++++++++++++++++++++++++-----
arch/arm/src/stm32l4/stm32l4x6xx_rcc.c | 38 +++++++++++++++++++++------------
2 files changed, 58 insertions(+), 19 deletions(-)
[incubator-nuttx] 02/03: stm32l4: add I2C timings for 48 MHz SYSCLK
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit b7d18585dc337eb6ade58bc02479ec3d0e6c8e45
Author: Matias Nitsche <mn...@dc.uba.ar>
AuthorDate: Sun Jun 7 15:12:51 2020 -0300
stm32l4: add I2C timings for 48 MHz SYSCLK
---
arch/arm/src/stm32l4/stm32l4_i2c.c | 39 +++++++++++++++++++++++++++++++++-----
1 file changed, 34 insertions(+), 5 deletions(-)
diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c
index 9ebc7e3..4b9dc0a 100644
--- a/arch/arm/src/stm32l4/stm32l4_i2c.c
+++ b/arch/arm/src/stm32l4/stm32l4_i2c.c
@@ -1288,11 +1288,11 @@ static void stm32l4_i2c_setclock(FAR struct stm32l4_i2c_priv_s *priv,
{
int i2cclk_mhz;
uint32_t pe;
- uint8_t presc;
- uint8_t scl_delay;
- uint8_t sda_delay;
- uint8_t scl_h_period;
- uint8_t scl_l_period;
+ uint8_t presc = 0;
+ uint8_t scl_delay = 0;
+ uint8_t sda_delay = 0;
+ uint8_t scl_h_period = 0;
+ uint8_t scl_l_period = 0;
if (frequency != priv->frequency)
{
@@ -1306,6 +1306,8 @@ static void stm32l4_i2c_setclock(FAR struct stm32l4_i2c_priv_s *priv,
#if defined(STM32L4_I2C_USE_HSI16) || (STM32L4_PCLK1_FREQUENCY == 16000000)
i2cclk_mhz = 16;
+#elif STM32L4_PCLK1_FREQUENCY == 48000000
+ i2cclk_mhz = 48;
#elif STM32L4_PCLK1_FREQUENCY == 80000000
i2cclk_mhz = 80;
#elif STM32L4_PCLK1_FREQUENCY == 120000000
@@ -1457,6 +1459,33 @@ static void stm32l4_i2c_setclock(FAR struct stm32l4_i2c_priv_s *priv,
scl_l_period = 162;
}
}
+ else if (i2cclk_mhz == 48)
+ {
+ if (frequency == 100000)
+ {
+ presc = 2;
+ scl_delay = 10;
+ sda_delay = 0;
+ scl_h_period = 62;
+ scl_l_period = 85;
+ }
+ else if (frequency == 400000)
+ {
+ presc = 1;
+ scl_delay = 8;
+ sda_delay = 0;
+ scl_h_period = 12;
+ scl_l_period = 33;
+ }
+ else if (frequency == 1000000)
+ {
+ presc = 0;
+ scl_delay = 5;
+ sda_delay = 0;
+ scl_h_period = 8;
+ scl_l_period = 22;
+ }
+ }
else
{
DEBUGPANIC();
[incubator-nuttx] 01/03: stm32l4: clocking fixes (would hang for
MSI@48MHz on STM32L476)
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit fa97e216e4d9125d262e6a722f3471f6e173d87c
Author: Matias Nitsche <mn...@dc.uba.ar>
AuthorDate: Sun Jun 7 15:11:58 2020 -0300
stm32l4: clocking fixes (would hang for MSI@48MHz on STM32L476)
---
arch/arm/src/stm32l4/stm32l4x6xx_rcc.c | 44 +++++++++++++++++++++-------------
1 file changed, 27 insertions(+), 17 deletions(-)
diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
index bffdaa2..01dc280 100644
--- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
+++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
@@ -723,25 +723,34 @@ static void stm32l4_stdclockconfig(void)
}
}
- /* Enable MSI and choosing frequency */
+ /* Choose MSI frequency */
regval = getreg32(STM32L4_RCC_CR);
regval &= ~RCC_CR_MSIRANGE_MASK;
- regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION | RCC_CR_MSIRGSEL);
+ regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSIRGSEL);
putreg32(regval, STM32L4_RCC_CR);
- /* Wait until the MSI is ready (or until a timeout elapsed) */
+ if (!(regval & RCC_CR_MSION))
+ {
+ /* Enable MSI */
- for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
- {
- /* Check if the MSIRDY flag is the set in the CR */
+ regval = getreg32(STM32L4_RCC_CR);
+ regval |= RCC_CR_MSION;
+ putreg32(regval, STM32L4_RCC_CR);
- if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0)
- {
- /* If so, then break-out with timeout > 0 */
+ /* Wait until the MSI is ready (or until a timeout elapsed) */
- break;
- }
+ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
+ {
+ /* Check if the MSIRDY flag is the set in the CR */
+
+ if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0)
+ {
+ /* If so, then break-out with timeout > 0 */
+
+ break;
+ }
+ }
}
#elif defined(STM32L4_BOARD_USEHSE)
@@ -777,24 +786,25 @@ static void stm32l4_stdclockconfig(void)
if (timeout > 0)
{
- /* Ensure Power control is enabled before modifying it. */
-
- stm32l4_pwr_enableclk(true);
-
if (STM32L4_SYSCLK_FREQUENCY > 24000000ul)
{
/* Select regulator voltage output Scale 1 mode to support system
* frequencies up to 168 MHz.
*/
+ /* TODO: this seems to hang on STM32L476, at least for MSI@48MHz */
+#if 0
+ stm32l4_pwr_enableclk(true);
stm32_pwr_setvos(1);
- }
+#endif
+ }
else
{
/* Select regulator voltage output Scale 2 mode for
* frequencies below 24 MHz
*/
+ stm32l4_pwr_enableclk(true);
stm32_pwr_setvos(2);
}
@@ -828,6 +838,7 @@ static void stm32l4_stdclockconfig(void)
putreg32(regval, STM32L4_RCC_CFGR);
#endif
+#ifndef STM32L4_BOARD_NOPLL
/* Set the PLL source and main divider */
regval = getreg32(STM32L4_RCC_PLLCFG);
@@ -864,7 +875,6 @@ static void stm32l4_stdclockconfig(void)
regval |= RCC_PLLCFG_PLLSRC_HSE;
#endif
-#ifndef STM32L4_BOARD_NOPLL
/* Use the main PLL as SYSCLK, so enable it first */
putreg32(regval, STM32L4_RCC_PLLCFG);
[incubator-nuttx] 03/03: style fixes
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 67ab8ebb5f4b2e174619d9798f0769db5b3e00e3
Author: Matias Nitsche <mn...@dc.uba.ar>
AuthorDate: Mon Jun 15 21:14:43 2020 -0300
style fixes
---
arch/arm/src/stm32l4/stm32l4_i2c.c | 52 +++++++++++++++++-----------------
arch/arm/src/stm32l4/stm32l4x6xx_rcc.c | 32 ++++++++++-----------
2 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c
index 4b9dc0a..f9d824f 100644
--- a/arch/arm/src/stm32l4/stm32l4_i2c.c
+++ b/arch/arm/src/stm32l4/stm32l4_i2c.c
@@ -1460,32 +1460,32 @@ static void stm32l4_i2c_setclock(FAR struct stm32l4_i2c_priv_s *priv,
}
}
else if (i2cclk_mhz == 48)
- {
- if (frequency == 100000)
- {
- presc = 2;
- scl_delay = 10;
- sda_delay = 0;
- scl_h_period = 62;
- scl_l_period = 85;
- }
- else if (frequency == 400000)
- {
- presc = 1;
- scl_delay = 8;
- sda_delay = 0;
- scl_h_period = 12;
- scl_l_period = 33;
- }
- else if (frequency == 1000000)
- {
- presc = 0;
- scl_delay = 5;
- sda_delay = 0;
- scl_h_period = 8;
- scl_l_period = 22;
- }
- }
+ {
+ if (frequency == 100000)
+ {
+ presc = 2;
+ scl_delay = 10;
+ sda_delay = 0;
+ scl_h_period = 62;
+ scl_l_period = 85;
+ }
+ else if (frequency == 400000)
+ {
+ presc = 1;
+ scl_delay = 8;
+ sda_delay = 0;
+ scl_h_period = 12;
+ scl_l_period = 33;
+ }
+ else if (frequency == 1000000)
+ {
+ presc = 0;
+ scl_delay = 5;
+ sda_delay = 0;
+ scl_h_period = 8;
+ scl_l_period = 22;
+ }
+ }
else
{
DEBUGPANIC();
diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
index 01dc280..546b720 100644
--- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
+++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
@@ -731,26 +731,26 @@ static void stm32l4_stdclockconfig(void)
putreg32(regval, STM32L4_RCC_CR);
if (!(regval & RCC_CR_MSION))
- {
- /* Enable MSI */
+ {
+ /* Enable MSI */
- regval = getreg32(STM32L4_RCC_CR);
- regval |= RCC_CR_MSION;
- putreg32(regval, STM32L4_RCC_CR);
+ regval = getreg32(STM32L4_RCC_CR);
+ regval |= RCC_CR_MSION;
+ putreg32(regval, STM32L4_RCC_CR);
- /* Wait until the MSI is ready (or until a timeout elapsed) */
+ /* Wait until the MSI is ready (or until a timeout elapsed) */
- for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
- {
- /* Check if the MSIRDY flag is the set in the CR */
+ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
+ {
+ /* Check if the MSIRDY flag is the set in the CR */
- if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0)
- {
- /* If so, then break-out with timeout > 0 */
+ if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0)
+ {
+ /* If so, then break-out with timeout > 0 */
- break;
- }
- }
+ break;
+ }
+ }
}
#elif defined(STM32L4_BOARD_USEHSE)
@@ -797,7 +797,7 @@ static void stm32l4_stdclockconfig(void)
stm32l4_pwr_enableclk(true);
stm32_pwr_setvos(1);
#endif
- }
+ }
else
{
/* Select regulator voltage output Scale 2 mode for