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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/01/19 08:32:43 UTC
[GitHub] [incubator-nuttx] pussuw opened a new pull request #5273: Sv39 MMU driver
pussuw opened a new pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273
## Summary
Adds a MMU driver for RISC-V (Sv39 implemented). The driver is generic and should be easily extensible to support other SvXX implementations as well.
## Impact
None (yet), as the driver is not utilized by any target.
## Testing
Tested by creating a target with CONFIG_BUILD_PROTECTED and mapping the user space to MMU.
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[GitHub] [incubator-nuttx] no1wudi commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
no1wudi commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787549779
##########
File path: arch/risc-v/src/common/riscv_mmu.c
##########
@@ -0,0 +1,129 @@
+/****************************************************************************
+ * arch/risc-v/src/rv64gc/riscv_mmu.c
Review comment:
Great, and we can develop the driver for sv32/sv48 on qemu rv32/rv64 in future.
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[GitHub] [incubator-nuttx] pussuw commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
pussuw commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787993364
##########
File path: arch/risc-v/src/common/riscv_mmu.h
##########
@@ -97,26 +102,65 @@
*
****************************************************************************/
-static inline void mmu_enable(uintptr_t pgbase, uint16_t asid)
+static inline uintptr_t satp_reg(uintptr_t pgbase, uint16_t asid)
Review comment:
Sure!
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[GitHub] [incubator-nuttx] no1wudi commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
no1wudi commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787559047
##########
File path: arch/risc-v/src/common/riscv_mmu.h
##########
@@ -0,0 +1,306 @@
+/****************************************************************************
+ * arch/risc-v/src/rv64gc/riscv_mmu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+#define ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+
+#if (__riscv_xlen != 64)
+#error "This MMU implementation is for xlen 64"
+#endif
+
+/* RV64 page size */
+
+#define RV_MMU_PAGE_SHIFT (12)
+#define RV_MMU_PAGE_SIZE (1 << RV_MMU_PAGE_SHIFT) /* 4K pages */
+
+/* Amount of page table levels */
+
+#define RV_MMU_PT_LEVELS (ARCH_PGT_MAX_LEVELS)
+
+/* Supervisor Address Translation and Protection (satp) */
+
+#define SATP_PPN_SHIFT (0)
+#define SATP_PPN_MASK (((1ul << 44) - 1) << SATP_PPN_SHIFT)
+#define SATP_ASID_SHIFT (44)
+#define SATP_ASID_MASK (((1ul << 16) - 1) << SATP_ASID_SHIFT)
+#define SATP_MODE_SHIFT (60)
+#define SATP_MODE_MASK (((1ul << 4) - 1) << SATP_MODE_SHIFT)
+
+/* Modes, 1-7 and 10-15 are reserved */
+
+#define SATP_MODE_BARE (0ul)
+#define SATP_MODE_SV39 (8ul)
+#define SATP_MODE_SV48 (9ul)
+
+/* satp address to PPN translation */
+
+#define SATP_ADDR_TO_PPN(_addr) ((_addr) >> RV_MMU_PAGE_SHIFT)
+
+/* Common Page Table Entry (PTE) bits */
+
+#define PTE_VALID (1 << 0) /* PTE is valid */
+#define PTE_R (1 << 1) /* Page is readable */
+#define PTE_W (1 << 2) /* Page is writable */
+#define PTE_X (1 << 3) /* Page is executable */
+#define PTE_U (1 << 4) /* Page is a user mode page */
+#define PTE_G (1 << 5) /* Page is a global mapping */
+#define PTE_A (1 << 6) /* Page has been accessed */
+#define PTE_D (1 << 7) /* Page is dirty */
+
+/* Check if leaf PTE entry or not (if X/W/R are set it is) */
+
+#define PTE_LEAF_MASK (7 << 1)
+
+/* Flags for user page tables */
+
+#define MMU_UPGT_FLAGS (0)
+
+/* Flags for user FLASH (RX) and user RAM (RW) */
+
+#define MMU_UTEXT_FLAGS (PTE_R | PTE_X | PTE_U)
+#define MMU_UDATA_FLAGS (PTE_R | PTE_W | PTE_U)
+
+/* SvX definitions, only Sv39 is currently supported, but it should be
+ * trivial to extend the driver to support other SvX implementations
+ *
+ * Sv39 has:
+ * - 4K page size
+ * - 3 page table levels
+ * - 9-bit VPN width
+ */
+
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+#define RV_MMU_PTE_PADDR_SHIFT (10)
+#define RV_MMU_PTE_PPN_MASK ((1 << RV_MMU_PTE_PADDR_SHIFT) - 1)
+#define RV_MMU_PTE_PPN_SHIFT (2)
+#define RV_MMU_VPN_WIDTH (9)
+#define RV_MMU_VPN_MASK ((1 << RV_MMU_VPN_WIDTH) - 1)
+#define RV_MMU_VADDR_SHIFT(_n) (RV_MMU_PAGE_SHIFT + RV_MMU_VPN_WIDTH * \
+ (RV_MMU_PT_LEVELS - (_n)))
+#define RV_MMU_SATP_MODE (SATP_MODE_SV39)
+#define RV_MMU_L1_PAGE_SIZE (0x40000000) /* 1G */
+#define RV_MMU_L2_PAGE_SIZE (0x200000) /* 2M */
+#define RV_MMU_L3_PAGE_SIZE (0x1000) /* 4K */
+#else
+#error "Unsupported RISC-V MMU implementation selected"
+#endif /* CONFIG_ARCH_MMU_TYPE_SV39 */
+
+/****************************************************************************
+ * Name: satp_reg
+ *
+ * Description:
+ * Utility function to build satp register value for input parameters
+ *
+ * Input Parameters:
+ * pgbase - The physical base address of the translation table base
+ * asid - Address space identifier. This can be used to identify different
+ * address spaces. It is not necessary to use this, nor is it necessary
+ * for the RISC-V implementation to implement such bits. This means in
+ * practice that the value should not be used in this generic driver.
+ *
+ ****************************************************************************/
+
+static inline uint64_t satp_reg(uint64_t pgbase, uint16_t asid)
+{
+ uint64_t reg;
+ reg = ((RV_MMU_SATP_MODE << SATP_MODE_SHIFT) & SATP_MODE_MASK);
+ reg |= (((uint64_t)asid << SATP_ASID_SHIFT) & SATP_ASID_MASK);
+ reg |= ((SATP_ADDR_TO_PPN(pgbase) << SATP_PPN_SHIFT) & SATP_PPN_MASK);
+ return reg;
+}
+
+/****************************************************************************
+ * Name: mmu_write_satp
+ *
+ * Description:
+ * Write satp
+ *
+ * Input Parameters:
+ * reg - satp value
+ *
+ ****************************************************************************/
+
+static inline void mmu_write_satp(uint64_t reg)
Review comment:
Pointer type represent to register width on NuttX at least:
```
/* Integer types capable of holding object pointers
* As a general rule, the size of size_t should be the same as the size of
* uintptr_t: 32-bits on a machine with 32-bit addressing but 64-bits on a
* machine with 64-bit addressing.
*/
typedef _ssize_t intptr_t;
typedef _size_t uintptr_t;
```
##########
File path: arch/risc-v/src/common/riscv_mmu.h
##########
@@ -0,0 +1,306 @@
+/****************************************************************************
+ * arch/risc-v/src/rv64gc/riscv_mmu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+#define ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+
+#if (__riscv_xlen != 64)
+#error "This MMU implementation is for xlen 64"
+#endif
+
+/* RV64 page size */
+
+#define RV_MMU_PAGE_SHIFT (12)
+#define RV_MMU_PAGE_SIZE (1 << RV_MMU_PAGE_SHIFT) /* 4K pages */
+
+/* Amount of page table levels */
+
+#define RV_MMU_PT_LEVELS (ARCH_PGT_MAX_LEVELS)
+
+/* Supervisor Address Translation and Protection (satp) */
+
+#define SATP_PPN_SHIFT (0)
+#define SATP_PPN_MASK (((1ul << 44) - 1) << SATP_PPN_SHIFT)
+#define SATP_ASID_SHIFT (44)
+#define SATP_ASID_MASK (((1ul << 16) - 1) << SATP_ASID_SHIFT)
+#define SATP_MODE_SHIFT (60)
+#define SATP_MODE_MASK (((1ul << 4) - 1) << SATP_MODE_SHIFT)
+
+/* Modes, 1-7 and 10-15 are reserved */
+
+#define SATP_MODE_BARE (0ul)
+#define SATP_MODE_SV39 (8ul)
+#define SATP_MODE_SV48 (9ul)
+
+/* satp address to PPN translation */
+
+#define SATP_ADDR_TO_PPN(_addr) ((_addr) >> RV_MMU_PAGE_SHIFT)
+
+/* Common Page Table Entry (PTE) bits */
+
+#define PTE_VALID (1 << 0) /* PTE is valid */
+#define PTE_R (1 << 1) /* Page is readable */
+#define PTE_W (1 << 2) /* Page is writable */
+#define PTE_X (1 << 3) /* Page is executable */
+#define PTE_U (1 << 4) /* Page is a user mode page */
+#define PTE_G (1 << 5) /* Page is a global mapping */
+#define PTE_A (1 << 6) /* Page has been accessed */
+#define PTE_D (1 << 7) /* Page is dirty */
+
+/* Check if leaf PTE entry or not (if X/W/R are set it is) */
+
+#define PTE_LEAF_MASK (7 << 1)
+
+/* Flags for user page tables */
+
+#define MMU_UPGT_FLAGS (0)
+
+/* Flags for user FLASH (RX) and user RAM (RW) */
+
+#define MMU_UTEXT_FLAGS (PTE_R | PTE_X | PTE_U)
+#define MMU_UDATA_FLAGS (PTE_R | PTE_W | PTE_U)
+
+/* SvX definitions, only Sv39 is currently supported, but it should be
+ * trivial to extend the driver to support other SvX implementations
+ *
+ * Sv39 has:
+ * - 4K page size
+ * - 3 page table levels
+ * - 9-bit VPN width
+ */
+
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+#define RV_MMU_PTE_PADDR_SHIFT (10)
+#define RV_MMU_PTE_PPN_MASK ((1 << RV_MMU_PTE_PADDR_SHIFT) - 1)
+#define RV_MMU_PTE_PPN_SHIFT (2)
+#define RV_MMU_VPN_WIDTH (9)
+#define RV_MMU_VPN_MASK ((1 << RV_MMU_VPN_WIDTH) - 1)
+#define RV_MMU_VADDR_SHIFT(_n) (RV_MMU_PAGE_SHIFT + RV_MMU_VPN_WIDTH * \
+ (RV_MMU_PT_LEVELS - (_n)))
+#define RV_MMU_SATP_MODE (SATP_MODE_SV39)
+#define RV_MMU_L1_PAGE_SIZE (0x40000000) /* 1G */
+#define RV_MMU_L2_PAGE_SIZE (0x200000) /* 2M */
+#define RV_MMU_L3_PAGE_SIZE (0x1000) /* 4K */
+#else
+#error "Unsupported RISC-V MMU implementation selected"
+#endif /* CONFIG_ARCH_MMU_TYPE_SV39 */
+
+/****************************************************************************
+ * Name: satp_reg
+ *
+ * Description:
+ * Utility function to build satp register value for input parameters
+ *
+ * Input Parameters:
+ * pgbase - The physical base address of the translation table base
+ * asid - Address space identifier. This can be used to identify different
+ * address spaces. It is not necessary to use this, nor is it necessary
+ * for the RISC-V implementation to implement such bits. This means in
+ * practice that the value should not be used in this generic driver.
+ *
+ ****************************************************************************/
+
+static inline uint64_t satp_reg(uint64_t pgbase, uint16_t asid)
+{
+ uint64_t reg;
+ reg = ((RV_MMU_SATP_MODE << SATP_MODE_SHIFT) & SATP_MODE_MASK);
+ reg |= (((uint64_t)asid << SATP_ASID_SHIFT) & SATP_ASID_MASK);
+ reg |= ((SATP_ADDR_TO_PPN(pgbase) << SATP_PPN_SHIFT) & SATP_PPN_MASK);
+ return reg;
+}
+
+/****************************************************************************
+ * Name: mmu_write_satp
+ *
+ * Description:
+ * Write satp
+ *
+ * Input Parameters:
+ * reg - satp value
+ *
+ ****************************************************************************/
+
+static inline void mmu_write_satp(uint64_t reg)
Review comment:
Pointer type represent to register width on NuttX:
```
/* Integer types capable of holding object pointers
* As a general rule, the size of size_t should be the same as the size of
* uintptr_t: 32-bits on a machine with 32-bit addressing but 64-bits on a
* machine with 64-bit addressing.
*/
typedef _ssize_t intptr_t;
typedef _size_t uintptr_t;
```
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[GitHub] [incubator-nuttx] pussuw commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
pussuw commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r788410574
##########
File path: arch/risc-v/include/arch.h
##########
@@ -62,6 +62,12 @@ uint32_t up_gethartid(void);
#endif
+/* Provide the maximum amount of page table levels per MMU type */
+
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+#define ARCH_PGT_MAX_LEVELS (3)
Review comment:
It will eventually be needed elsewhere too. I'm implementing `CONFIG_BUILD_KERNEL` for RISC-V / MPFS target.
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[GitHub] [incubator-nuttx] no1wudi commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
no1wudi commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787529195
##########
File path: arch/risc-v/src/common/riscv_mmu.h
##########
@@ -0,0 +1,306 @@
+/****************************************************************************
+ * arch/risc-v/src/rv64gc/riscv_mmu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+#define ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+
+#if (__riscv_xlen != 64)
+#error "This MMU implementation is for xlen 64"
+#endif
+
+/* RV64 page size */
+
+#define RV_MMU_PAGE_SHIFT (12)
+#define RV_MMU_PAGE_SIZE (1 << RV_MMU_PAGE_SHIFT) /* 4K pages */
+
+/* Amount of page table levels */
+
+#define RV_MMU_PT_LEVELS (ARCH_PGT_MAX_LEVELS)
+
+/* Supervisor Address Translation and Protection (satp) */
+
+#define SATP_PPN_SHIFT (0)
+#define SATP_PPN_MASK (((1ul << 44) - 1) << SATP_PPN_SHIFT)
+#define SATP_ASID_SHIFT (44)
+#define SATP_ASID_MASK (((1ul << 16) - 1) << SATP_ASID_SHIFT)
+#define SATP_MODE_SHIFT (60)
+#define SATP_MODE_MASK (((1ul << 4) - 1) << SATP_MODE_SHIFT)
+
+/* Modes, 1-7 and 10-15 are reserved */
+
+#define SATP_MODE_BARE (0ul)
+#define SATP_MODE_SV39 (8ul)
+#define SATP_MODE_SV48 (9ul)
+
+/* satp address to PPN translation */
+
+#define SATP_ADDR_TO_PPN(_addr) ((_addr) >> RV_MMU_PAGE_SHIFT)
+
+/* Common Page Table Entry (PTE) bits */
+
+#define PTE_VALID (1 << 0) /* PTE is valid */
+#define PTE_R (1 << 1) /* Page is readable */
+#define PTE_W (1 << 2) /* Page is writable */
+#define PTE_X (1 << 3) /* Page is executable */
+#define PTE_U (1 << 4) /* Page is a user mode page */
+#define PTE_G (1 << 5) /* Page is a global mapping */
+#define PTE_A (1 << 6) /* Page has been accessed */
+#define PTE_D (1 << 7) /* Page is dirty */
+
+/* Check if leaf PTE entry or not (if X/W/R are set it is) */
+
+#define PTE_LEAF_MASK (7 << 1)
+
+/* Flags for user page tables */
+
+#define MMU_UPGT_FLAGS (0)
+
+/* Flags for user FLASH (RX) and user RAM (RW) */
+
+#define MMU_UTEXT_FLAGS (PTE_R | PTE_X | PTE_U)
+#define MMU_UDATA_FLAGS (PTE_R | PTE_W | PTE_U)
+
+/* SvX definitions, only Sv39 is currently supported, but it should be
+ * trivial to extend the driver to support other SvX implementations
+ *
+ * Sv39 has:
+ * - 4K page size
+ * - 3 page table levels
+ * - 9-bit VPN width
+ */
+
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+#define RV_MMU_PTE_PADDR_SHIFT (10)
+#define RV_MMU_PTE_PPN_MASK ((1 << RV_MMU_PTE_PADDR_SHIFT) - 1)
+#define RV_MMU_PTE_PPN_SHIFT (2)
+#define RV_MMU_VPN_WIDTH (9)
+#define RV_MMU_VPN_MASK ((1 << RV_MMU_VPN_WIDTH) - 1)
+#define RV_MMU_VADDR_SHIFT(_n) (RV_MMU_PAGE_SHIFT + RV_MMU_VPN_WIDTH * \
+ (RV_MMU_PT_LEVELS - (_n)))
+#define RV_MMU_SATP_MODE (SATP_MODE_SV39)
+#define RV_MMU_L1_PAGE_SIZE (0x40000000) /* 1G */
+#define RV_MMU_L2_PAGE_SIZE (0x200000) /* 2M */
+#define RV_MMU_L3_PAGE_SIZE (0x1000) /* 4K */
+#else
+#error "Unsupported RISC-V MMU implementation selected"
+#endif /* CONFIG_ARCH_MMU_TYPE_SV39 */
+
+/****************************************************************************
+ * Name: satp_reg
+ *
+ * Description:
+ * Utility function to build satp register value for input parameters
+ *
+ * Input Parameters:
+ * pgbase - The physical base address of the translation table base
+ * asid - Address space identifier. This can be used to identify different
+ * address spaces. It is not necessary to use this, nor is it necessary
+ * for the RISC-V implementation to implement such bits. This means in
+ * practice that the value should not be used in this generic driver.
+ *
+ ****************************************************************************/
+
+static inline uint64_t satp_reg(uint64_t pgbase, uint16_t asid)
+{
+ uint64_t reg;
+ reg = ((RV_MMU_SATP_MODE << SATP_MODE_SHIFT) & SATP_MODE_MASK);
+ reg |= (((uint64_t)asid << SATP_ASID_SHIFT) & SATP_ASID_MASK);
+ reg |= ((SATP_ADDR_TO_PPN(pgbase) << SATP_PPN_SHIFT) & SATP_PPN_MASK);
+ return reg;
+}
+
+/****************************************************************************
+ * Name: mmu_write_satp
+ *
+ * Description:
+ * Write satp
+ *
+ * Input Parameters:
+ * reg - satp value
+ *
+ ****************************************************************************/
+
+static inline void mmu_write_satp(uint64_t reg)
Review comment:
Use uintptr_t to represent register width value.
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[GitHub] [incubator-nuttx] pussuw commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
pussuw commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787544145
##########
File path: arch/risc-v/src/common/riscv_mmu.h
##########
@@ -0,0 +1,306 @@
+/****************************************************************************
+ * arch/risc-v/src/rv64gc/riscv_mmu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+#define ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+
+#if (__riscv_xlen != 64)
+#error "This MMU implementation is for xlen 64"
+#endif
+
+/* RV64 page size */
+
+#define RV_MMU_PAGE_SHIFT (12)
+#define RV_MMU_PAGE_SIZE (1 << RV_MMU_PAGE_SHIFT) /* 4K pages */
+
+/* Amount of page table levels */
+
+#define RV_MMU_PT_LEVELS (ARCH_PGT_MAX_LEVELS)
+
+/* Supervisor Address Translation and Protection (satp) */
+
+#define SATP_PPN_SHIFT (0)
+#define SATP_PPN_MASK (((1ul << 44) - 1) << SATP_PPN_SHIFT)
+#define SATP_ASID_SHIFT (44)
+#define SATP_ASID_MASK (((1ul << 16) - 1) << SATP_ASID_SHIFT)
+#define SATP_MODE_SHIFT (60)
+#define SATP_MODE_MASK (((1ul << 4) - 1) << SATP_MODE_SHIFT)
+
+/* Modes, 1-7 and 10-15 are reserved */
+
+#define SATP_MODE_BARE (0ul)
+#define SATP_MODE_SV39 (8ul)
+#define SATP_MODE_SV48 (9ul)
+
+/* satp address to PPN translation */
+
+#define SATP_ADDR_TO_PPN(_addr) ((_addr) >> RV_MMU_PAGE_SHIFT)
+
+/* Common Page Table Entry (PTE) bits */
+
+#define PTE_VALID (1 << 0) /* PTE is valid */
+#define PTE_R (1 << 1) /* Page is readable */
+#define PTE_W (1 << 2) /* Page is writable */
+#define PTE_X (1 << 3) /* Page is executable */
+#define PTE_U (1 << 4) /* Page is a user mode page */
+#define PTE_G (1 << 5) /* Page is a global mapping */
+#define PTE_A (1 << 6) /* Page has been accessed */
+#define PTE_D (1 << 7) /* Page is dirty */
+
+/* Check if leaf PTE entry or not (if X/W/R are set it is) */
+
+#define PTE_LEAF_MASK (7 << 1)
+
+/* Flags for user page tables */
+
+#define MMU_UPGT_FLAGS (0)
+
+/* Flags for user FLASH (RX) and user RAM (RW) */
+
+#define MMU_UTEXT_FLAGS (PTE_R | PTE_X | PTE_U)
+#define MMU_UDATA_FLAGS (PTE_R | PTE_W | PTE_U)
+
+/* SvX definitions, only Sv39 is currently supported, but it should be
+ * trivial to extend the driver to support other SvX implementations
+ *
+ * Sv39 has:
+ * - 4K page size
+ * - 3 page table levels
+ * - 9-bit VPN width
+ */
+
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+#define RV_MMU_PTE_PADDR_SHIFT (10)
+#define RV_MMU_PTE_PPN_MASK ((1 << RV_MMU_PTE_PADDR_SHIFT) - 1)
+#define RV_MMU_PTE_PPN_SHIFT (2)
+#define RV_MMU_VPN_WIDTH (9)
+#define RV_MMU_VPN_MASK ((1 << RV_MMU_VPN_WIDTH) - 1)
+#define RV_MMU_VADDR_SHIFT(_n) (RV_MMU_PAGE_SHIFT + RV_MMU_VPN_WIDTH * \
+ (RV_MMU_PT_LEVELS - (_n)))
+#define RV_MMU_SATP_MODE (SATP_MODE_SV39)
+#define RV_MMU_L1_PAGE_SIZE (0x40000000) /* 1G */
+#define RV_MMU_L2_PAGE_SIZE (0x200000) /* 2M */
+#define RV_MMU_L3_PAGE_SIZE (0x1000) /* 4K */
+#else
+#error "Unsupported RISC-V MMU implementation selected"
+#endif /* CONFIG_ARCH_MMU_TYPE_SV39 */
+
+/****************************************************************************
+ * Name: satp_reg
+ *
+ * Description:
+ * Utility function to build satp register value for input parameters
+ *
+ * Input Parameters:
+ * pgbase - The physical base address of the translation table base
+ * asid - Address space identifier. This can be used to identify different
+ * address spaces. It is not necessary to use this, nor is it necessary
+ * for the RISC-V implementation to implement such bits. This means in
+ * practice that the value should not be used in this generic driver.
+ *
+ ****************************************************************************/
+
+static inline uint64_t satp_reg(uint64_t pgbase, uint16_t asid)
+{
+ uint64_t reg;
+ reg = ((RV_MMU_SATP_MODE << SATP_MODE_SHIFT) & SATP_MODE_MASK);
+ reg |= (((uint64_t)asid << SATP_ASID_SHIFT) & SATP_ASID_MASK);
+ reg |= ((SATP_ADDR_TO_PPN(pgbase) << SATP_PPN_SHIFT) & SATP_PPN_MASK);
+ return reg;
+}
+
+/****************************************************************************
+ * Name: mmu_write_satp
+ *
+ * Description:
+ * Write satp
+ *
+ * Input Parameters:
+ * reg - satp value
+ *
+ ****************************************************************************/
+
+static inline void mmu_write_satp(uint64_t reg)
Review comment:
uintptr_t does not quite represent a CPU registers width. Quote from the C standard is as follows:
The following type designates an unsigned integer type with the property that any valid
pointer to void can be converted to this type, then converted back to pointer to void,
and the result will compare equal to the original pointer:
uintptr_t
I can create an abstract register type (dependent on __riscv_xlen which tells the architecture specific register size) if that is acceptable ?
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r788463435
##########
File path: arch/risc-v/include/arch.h
##########
@@ -62,6 +62,12 @@ uint32_t up_gethartid(void);
#endif
+/* Provide the maximum amount of page table levels per MMU type */
+
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+#define ARCH_PGT_MAX_LEVELS (3)
Review comment:
It normally doesn't need to expose so detailed info outside arch, how about we move the macro to mmu.h until you really need it?
##########
File path: arch/risc-v/include/arch.h
##########
@@ -62,6 +62,12 @@ uint32_t up_gethartid(void);
#endif
+/* Provide the maximum amount of page table levels per MMU type */
+
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+#define ARCH_PGT_MAX_LEVELS (3)
Review comment:
It normally doesn't need to expose so detailed info outside arch, how about we move the macro to riscv_mmu.h until you really need it?
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[GitHub] [incubator-nuttx] no1wudi commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
no1wudi commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787530497
##########
File path: arch/risc-v/src/common/riscv_mmu.c
##########
@@ -0,0 +1,129 @@
+/****************************************************************************
+ * arch/risc-v/src/rv64gc/riscv_mmu.c
Review comment:
Change rv64gc to common and, how about rename this file to riscv_mmu_sv39.c ?
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[GitHub] [incubator-nuttx] pussuw commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
pussuw commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787540564
##########
File path: arch/risc-v/src/common/riscv_mmu.c
##########
@@ -0,0 +1,129 @@
+/****************************************************************************
+ * arch/risc-v/src/rv64gc/riscv_mmu.c
Review comment:
Ah my bad, missed this. Will fix the path.
However, I would like to keep the current name, as the driver framework is generic and is designed to work with any SvXX implementation (although Sv39 is the only one implemented now).
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787967724
##########
File path: arch/risc-v/src/common/riscv_mmu.h
##########
@@ -97,26 +102,65 @@
*
****************************************************************************/
-static inline void mmu_enable(uintptr_t pgbase, uint16_t asid)
+static inline uintptr_t satp_reg(uintptr_t pgbase, uint16_t asid)
Review comment:
should we add prefix mmu_stap_reg
##########
File path: arch/risc-v/src/common/riscv_mmu.c
##########
@@ -43,6 +43,13 @@
* Private Data
****************************************************************************/
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+static const size_t m_pgt_sizes[] =
Review comment:
m_gpt_sizes to g_gpt_sizes
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r788598350
##########
File path: arch/risc-v/include/arch.h
##########
@@ -62,6 +62,12 @@ uint32_t up_gethartid(void);
#endif
+/* Provide the maximum amount of page table levels per MMU type */
+
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+#define ARCH_PGT_MAX_LEVELS (3)
Review comment:
Sure, let's wait you new patch.
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[GitHub] [incubator-nuttx] pussuw commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
pussuw commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787568784
##########
File path: arch/risc-v/src/common/riscv_mmu.h
##########
@@ -0,0 +1,306 @@
+/****************************************************************************
+ * arch/risc-v/src/rv64gc/riscv_mmu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+#define ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+
+#if (__riscv_xlen != 64)
+#error "This MMU implementation is for xlen 64"
+#endif
+
+/* RV64 page size */
+
+#define RV_MMU_PAGE_SHIFT (12)
+#define RV_MMU_PAGE_SIZE (1 << RV_MMU_PAGE_SHIFT) /* 4K pages */
+
+/* Amount of page table levels */
+
+#define RV_MMU_PT_LEVELS (ARCH_PGT_MAX_LEVELS)
+
+/* Supervisor Address Translation and Protection (satp) */
+
+#define SATP_PPN_SHIFT (0)
+#define SATP_PPN_MASK (((1ul << 44) - 1) << SATP_PPN_SHIFT)
+#define SATP_ASID_SHIFT (44)
+#define SATP_ASID_MASK (((1ul << 16) - 1) << SATP_ASID_SHIFT)
+#define SATP_MODE_SHIFT (60)
+#define SATP_MODE_MASK (((1ul << 4) - 1) << SATP_MODE_SHIFT)
+
+/* Modes, 1-7 and 10-15 are reserved */
+
+#define SATP_MODE_BARE (0ul)
+#define SATP_MODE_SV39 (8ul)
+#define SATP_MODE_SV48 (9ul)
+
+/* satp address to PPN translation */
+
+#define SATP_ADDR_TO_PPN(_addr) ((_addr) >> RV_MMU_PAGE_SHIFT)
+
+/* Common Page Table Entry (PTE) bits */
+
+#define PTE_VALID (1 << 0) /* PTE is valid */
+#define PTE_R (1 << 1) /* Page is readable */
+#define PTE_W (1 << 2) /* Page is writable */
+#define PTE_X (1 << 3) /* Page is executable */
+#define PTE_U (1 << 4) /* Page is a user mode page */
+#define PTE_G (1 << 5) /* Page is a global mapping */
+#define PTE_A (1 << 6) /* Page has been accessed */
+#define PTE_D (1 << 7) /* Page is dirty */
+
+/* Check if leaf PTE entry or not (if X/W/R are set it is) */
+
+#define PTE_LEAF_MASK (7 << 1)
+
+/* Flags for user page tables */
+
+#define MMU_UPGT_FLAGS (0)
+
+/* Flags for user FLASH (RX) and user RAM (RW) */
+
+#define MMU_UTEXT_FLAGS (PTE_R | PTE_X | PTE_U)
+#define MMU_UDATA_FLAGS (PTE_R | PTE_W | PTE_U)
+
+/* SvX definitions, only Sv39 is currently supported, but it should be
+ * trivial to extend the driver to support other SvX implementations
+ *
+ * Sv39 has:
+ * - 4K page size
+ * - 3 page table levels
+ * - 9-bit VPN width
+ */
+
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+#define RV_MMU_PTE_PADDR_SHIFT (10)
+#define RV_MMU_PTE_PPN_MASK ((1 << RV_MMU_PTE_PADDR_SHIFT) - 1)
+#define RV_MMU_PTE_PPN_SHIFT (2)
+#define RV_MMU_VPN_WIDTH (9)
+#define RV_MMU_VPN_MASK ((1 << RV_MMU_VPN_WIDTH) - 1)
+#define RV_MMU_VADDR_SHIFT(_n) (RV_MMU_PAGE_SHIFT + RV_MMU_VPN_WIDTH * \
+ (RV_MMU_PT_LEVELS - (_n)))
+#define RV_MMU_SATP_MODE (SATP_MODE_SV39)
+#define RV_MMU_L1_PAGE_SIZE (0x40000000) /* 1G */
+#define RV_MMU_L2_PAGE_SIZE (0x200000) /* 2M */
+#define RV_MMU_L3_PAGE_SIZE (0x1000) /* 4K */
+#else
+#error "Unsupported RISC-V MMU implementation selected"
+#endif /* CONFIG_ARCH_MMU_TYPE_SV39 */
+
+/****************************************************************************
+ * Name: satp_reg
+ *
+ * Description:
+ * Utility function to build satp register value for input parameters
+ *
+ * Input Parameters:
+ * pgbase - The physical base address of the translation table base
+ * asid - Address space identifier. This can be used to identify different
+ * address spaces. It is not necessary to use this, nor is it necessary
+ * for the RISC-V implementation to implement such bits. This means in
+ * practice that the value should not be used in this generic driver.
+ *
+ ****************************************************************************/
+
+static inline uint64_t satp_reg(uint64_t pgbase, uint16_t asid)
+{
+ uint64_t reg;
+ reg = ((RV_MMU_SATP_MODE << SATP_MODE_SHIFT) & SATP_MODE_MASK);
+ reg |= (((uint64_t)asid << SATP_ASID_SHIFT) & SATP_ASID_MASK);
+ reg |= ((SATP_ADDR_TO_PPN(pgbase) << SATP_PPN_SHIFT) & SATP_PPN_MASK);
+ return reg;
+}
+
+/****************************************************************************
+ * Name: mmu_write_satp
+ *
+ * Description:
+ * Write satp
+ *
+ * Input Parameters:
+ * reg - satp value
+ *
+ ****************************************************************************/
+
+static inline void mmu_write_satp(uint64_t reg)
Review comment:
Ok, will change.
Should I change the address parameters given to e.g.
void mmu_ln_setentry(uint32_t ptlevel, uint64_t lnvaddr, uint64_t paddr,
uint64_t vaddr, uint32_t mmuflags);
To uintptr type as well ?
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[GitHub] [incubator-nuttx] no1wudi commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
no1wudi commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787559047
##########
File path: arch/risc-v/src/common/riscv_mmu.h
##########
@@ -0,0 +1,306 @@
+/****************************************************************************
+ * arch/risc-v/src/rv64gc/riscv_mmu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+#define ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+
+#if (__riscv_xlen != 64)
+#error "This MMU implementation is for xlen 64"
+#endif
+
+/* RV64 page size */
+
+#define RV_MMU_PAGE_SHIFT (12)
+#define RV_MMU_PAGE_SIZE (1 << RV_MMU_PAGE_SHIFT) /* 4K pages */
+
+/* Amount of page table levels */
+
+#define RV_MMU_PT_LEVELS (ARCH_PGT_MAX_LEVELS)
+
+/* Supervisor Address Translation and Protection (satp) */
+
+#define SATP_PPN_SHIFT (0)
+#define SATP_PPN_MASK (((1ul << 44) - 1) << SATP_PPN_SHIFT)
+#define SATP_ASID_SHIFT (44)
+#define SATP_ASID_MASK (((1ul << 16) - 1) << SATP_ASID_SHIFT)
+#define SATP_MODE_SHIFT (60)
+#define SATP_MODE_MASK (((1ul << 4) - 1) << SATP_MODE_SHIFT)
+
+/* Modes, 1-7 and 10-15 are reserved */
+
+#define SATP_MODE_BARE (0ul)
+#define SATP_MODE_SV39 (8ul)
+#define SATP_MODE_SV48 (9ul)
+
+/* satp address to PPN translation */
+
+#define SATP_ADDR_TO_PPN(_addr) ((_addr) >> RV_MMU_PAGE_SHIFT)
+
+/* Common Page Table Entry (PTE) bits */
+
+#define PTE_VALID (1 << 0) /* PTE is valid */
+#define PTE_R (1 << 1) /* Page is readable */
+#define PTE_W (1 << 2) /* Page is writable */
+#define PTE_X (1 << 3) /* Page is executable */
+#define PTE_U (1 << 4) /* Page is a user mode page */
+#define PTE_G (1 << 5) /* Page is a global mapping */
+#define PTE_A (1 << 6) /* Page has been accessed */
+#define PTE_D (1 << 7) /* Page is dirty */
+
+/* Check if leaf PTE entry or not (if X/W/R are set it is) */
+
+#define PTE_LEAF_MASK (7 << 1)
+
+/* Flags for user page tables */
+
+#define MMU_UPGT_FLAGS (0)
+
+/* Flags for user FLASH (RX) and user RAM (RW) */
+
+#define MMU_UTEXT_FLAGS (PTE_R | PTE_X | PTE_U)
+#define MMU_UDATA_FLAGS (PTE_R | PTE_W | PTE_U)
+
+/* SvX definitions, only Sv39 is currently supported, but it should be
+ * trivial to extend the driver to support other SvX implementations
+ *
+ * Sv39 has:
+ * - 4K page size
+ * - 3 page table levels
+ * - 9-bit VPN width
+ */
+
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+#define RV_MMU_PTE_PADDR_SHIFT (10)
+#define RV_MMU_PTE_PPN_MASK ((1 << RV_MMU_PTE_PADDR_SHIFT) - 1)
+#define RV_MMU_PTE_PPN_SHIFT (2)
+#define RV_MMU_VPN_WIDTH (9)
+#define RV_MMU_VPN_MASK ((1 << RV_MMU_VPN_WIDTH) - 1)
+#define RV_MMU_VADDR_SHIFT(_n) (RV_MMU_PAGE_SHIFT + RV_MMU_VPN_WIDTH * \
+ (RV_MMU_PT_LEVELS - (_n)))
+#define RV_MMU_SATP_MODE (SATP_MODE_SV39)
+#define RV_MMU_L1_PAGE_SIZE (0x40000000) /* 1G */
+#define RV_MMU_L2_PAGE_SIZE (0x200000) /* 2M */
+#define RV_MMU_L3_PAGE_SIZE (0x1000) /* 4K */
+#else
+#error "Unsupported RISC-V MMU implementation selected"
+#endif /* CONFIG_ARCH_MMU_TYPE_SV39 */
+
+/****************************************************************************
+ * Name: satp_reg
+ *
+ * Description:
+ * Utility function to build satp register value for input parameters
+ *
+ * Input Parameters:
+ * pgbase - The physical base address of the translation table base
+ * asid - Address space identifier. This can be used to identify different
+ * address spaces. It is not necessary to use this, nor is it necessary
+ * for the RISC-V implementation to implement such bits. This means in
+ * practice that the value should not be used in this generic driver.
+ *
+ ****************************************************************************/
+
+static inline uint64_t satp_reg(uint64_t pgbase, uint16_t asid)
+{
+ uint64_t reg;
+ reg = ((RV_MMU_SATP_MODE << SATP_MODE_SHIFT) & SATP_MODE_MASK);
+ reg |= (((uint64_t)asid << SATP_ASID_SHIFT) & SATP_ASID_MASK);
+ reg |= ((SATP_ADDR_TO_PPN(pgbase) << SATP_PPN_SHIFT) & SATP_PPN_MASK);
+ return reg;
+}
+
+/****************************************************************************
+ * Name: mmu_write_satp
+ *
+ * Description:
+ * Write satp
+ *
+ * Input Parameters:
+ * reg - satp value
+ *
+ ****************************************************************************/
+
+static inline void mmu_write_satp(uint64_t reg)
Review comment:
Pointer type represent to register with usually on NuttX at least:
```
/* Integer types capable of holding object pointers
* As a general rule, the size of size_t should be the same as the size of
* uintptr_t: 32-bits on a machine with 32-bit addressing but 64-bits on a
* machine with 64-bit addressing.
*/
typedef _ssize_t intptr_t;
typedef _size_t uintptr_t;
```
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[GitHub] [incubator-nuttx] pussuw commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
pussuw commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r788488468
##########
File path: arch/risc-v/include/arch.h
##########
@@ -62,6 +62,12 @@ uint32_t up_gethartid(void);
#endif
+/* Provide the maximum amount of page table levels per MMU type */
+
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+#define ARCH_PGT_MAX_LEVELS (3)
Review comment:
No problem, I can move it for now and present this later here.
However at some point the amount of page table levels will be needed by this file as well, as the group_addrenv_s structure will be presented here (and it will need the page table amount).
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[GitHub] [incubator-nuttx] pussuw commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
pussuw commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787994806
##########
File path: arch/risc-v/src/common/riscv_mmu.c
##########
@@ -43,6 +43,13 @@
* Private Data
****************************************************************************/
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+static const size_t m_pgt_sizes[] =
Review comment:
Sorry, old habit... Will fix.
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[GitHub] [incubator-nuttx] no1wudi commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
no1wudi commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787559047
##########
File path: arch/risc-v/src/common/riscv_mmu.h
##########
@@ -0,0 +1,306 @@
+/****************************************************************************
+ * arch/risc-v/src/rv64gc/riscv_mmu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+#define ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+
+#if (__riscv_xlen != 64)
+#error "This MMU implementation is for xlen 64"
+#endif
+
+/* RV64 page size */
+
+#define RV_MMU_PAGE_SHIFT (12)
+#define RV_MMU_PAGE_SIZE (1 << RV_MMU_PAGE_SHIFT) /* 4K pages */
+
+/* Amount of page table levels */
+
+#define RV_MMU_PT_LEVELS (ARCH_PGT_MAX_LEVELS)
+
+/* Supervisor Address Translation and Protection (satp) */
+
+#define SATP_PPN_SHIFT (0)
+#define SATP_PPN_MASK (((1ul << 44) - 1) << SATP_PPN_SHIFT)
+#define SATP_ASID_SHIFT (44)
+#define SATP_ASID_MASK (((1ul << 16) - 1) << SATP_ASID_SHIFT)
+#define SATP_MODE_SHIFT (60)
+#define SATP_MODE_MASK (((1ul << 4) - 1) << SATP_MODE_SHIFT)
+
+/* Modes, 1-7 and 10-15 are reserved */
+
+#define SATP_MODE_BARE (0ul)
+#define SATP_MODE_SV39 (8ul)
+#define SATP_MODE_SV48 (9ul)
+
+/* satp address to PPN translation */
+
+#define SATP_ADDR_TO_PPN(_addr) ((_addr) >> RV_MMU_PAGE_SHIFT)
+
+/* Common Page Table Entry (PTE) bits */
+
+#define PTE_VALID (1 << 0) /* PTE is valid */
+#define PTE_R (1 << 1) /* Page is readable */
+#define PTE_W (1 << 2) /* Page is writable */
+#define PTE_X (1 << 3) /* Page is executable */
+#define PTE_U (1 << 4) /* Page is a user mode page */
+#define PTE_G (1 << 5) /* Page is a global mapping */
+#define PTE_A (1 << 6) /* Page has been accessed */
+#define PTE_D (1 << 7) /* Page is dirty */
+
+/* Check if leaf PTE entry or not (if X/W/R are set it is) */
+
+#define PTE_LEAF_MASK (7 << 1)
+
+/* Flags for user page tables */
+
+#define MMU_UPGT_FLAGS (0)
+
+/* Flags for user FLASH (RX) and user RAM (RW) */
+
+#define MMU_UTEXT_FLAGS (PTE_R | PTE_X | PTE_U)
+#define MMU_UDATA_FLAGS (PTE_R | PTE_W | PTE_U)
+
+/* SvX definitions, only Sv39 is currently supported, but it should be
+ * trivial to extend the driver to support other SvX implementations
+ *
+ * Sv39 has:
+ * - 4K page size
+ * - 3 page table levels
+ * - 9-bit VPN width
+ */
+
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+#define RV_MMU_PTE_PADDR_SHIFT (10)
+#define RV_MMU_PTE_PPN_MASK ((1 << RV_MMU_PTE_PADDR_SHIFT) - 1)
+#define RV_MMU_PTE_PPN_SHIFT (2)
+#define RV_MMU_VPN_WIDTH (9)
+#define RV_MMU_VPN_MASK ((1 << RV_MMU_VPN_WIDTH) - 1)
+#define RV_MMU_VADDR_SHIFT(_n) (RV_MMU_PAGE_SHIFT + RV_MMU_VPN_WIDTH * \
+ (RV_MMU_PT_LEVELS - (_n)))
+#define RV_MMU_SATP_MODE (SATP_MODE_SV39)
+#define RV_MMU_L1_PAGE_SIZE (0x40000000) /* 1G */
+#define RV_MMU_L2_PAGE_SIZE (0x200000) /* 2M */
+#define RV_MMU_L3_PAGE_SIZE (0x1000) /* 4K */
+#else
+#error "Unsupported RISC-V MMU implementation selected"
+#endif /* CONFIG_ARCH_MMU_TYPE_SV39 */
+
+/****************************************************************************
+ * Name: satp_reg
+ *
+ * Description:
+ * Utility function to build satp register value for input parameters
+ *
+ * Input Parameters:
+ * pgbase - The physical base address of the translation table base
+ * asid - Address space identifier. This can be used to identify different
+ * address spaces. It is not necessary to use this, nor is it necessary
+ * for the RISC-V implementation to implement such bits. This means in
+ * practice that the value should not be used in this generic driver.
+ *
+ ****************************************************************************/
+
+static inline uint64_t satp_reg(uint64_t pgbase, uint16_t asid)
+{
+ uint64_t reg;
+ reg = ((RV_MMU_SATP_MODE << SATP_MODE_SHIFT) & SATP_MODE_MASK);
+ reg |= (((uint64_t)asid << SATP_ASID_SHIFT) & SATP_ASID_MASK);
+ reg |= ((SATP_ADDR_TO_PPN(pgbase) << SATP_PPN_SHIFT) & SATP_PPN_MASK);
+ return reg;
+}
+
+/****************************************************************************
+ * Name: mmu_write_satp
+ *
+ * Description:
+ * Write satp
+ *
+ * Input Parameters:
+ * reg - satp value
+ *
+ ****************************************************************************/
+
+static inline void mmu_write_satp(uint64_t reg)
Review comment:
Pointer type represent to register width usually and on NuttX:
```
/* Integer types capable of holding object pointers
* As a general rule, the size of size_t should be the same as the size of
* uintptr_t: 32-bits on a machine with 32-bit addressing but 64-bits on a
* machine with 64-bit addressing.
*/
typedef _ssize_t intptr_t;
typedef _size_t uintptr_t;
```
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[GitHub] [incubator-nuttx] no1wudi commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
no1wudi commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787573680
##########
File path: arch/risc-v/src/common/riscv_mmu.h
##########
@@ -0,0 +1,306 @@
+/****************************************************************************
+ * arch/risc-v/src/rv64gc/riscv_mmu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+#define ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+
+#if (__riscv_xlen != 64)
+#error "This MMU implementation is for xlen 64"
+#endif
+
+/* RV64 page size */
+
+#define RV_MMU_PAGE_SHIFT (12)
+#define RV_MMU_PAGE_SIZE (1 << RV_MMU_PAGE_SHIFT) /* 4K pages */
+
+/* Amount of page table levels */
+
+#define RV_MMU_PT_LEVELS (ARCH_PGT_MAX_LEVELS)
+
+/* Supervisor Address Translation and Protection (satp) */
+
+#define SATP_PPN_SHIFT (0)
+#define SATP_PPN_MASK (((1ul << 44) - 1) << SATP_PPN_SHIFT)
+#define SATP_ASID_SHIFT (44)
+#define SATP_ASID_MASK (((1ul << 16) - 1) << SATP_ASID_SHIFT)
+#define SATP_MODE_SHIFT (60)
+#define SATP_MODE_MASK (((1ul << 4) - 1) << SATP_MODE_SHIFT)
+
+/* Modes, 1-7 and 10-15 are reserved */
+
+#define SATP_MODE_BARE (0ul)
+#define SATP_MODE_SV39 (8ul)
+#define SATP_MODE_SV48 (9ul)
+
+/* satp address to PPN translation */
+
+#define SATP_ADDR_TO_PPN(_addr) ((_addr) >> RV_MMU_PAGE_SHIFT)
+
+/* Common Page Table Entry (PTE) bits */
+
+#define PTE_VALID (1 << 0) /* PTE is valid */
+#define PTE_R (1 << 1) /* Page is readable */
+#define PTE_W (1 << 2) /* Page is writable */
+#define PTE_X (1 << 3) /* Page is executable */
+#define PTE_U (1 << 4) /* Page is a user mode page */
+#define PTE_G (1 << 5) /* Page is a global mapping */
+#define PTE_A (1 << 6) /* Page has been accessed */
+#define PTE_D (1 << 7) /* Page is dirty */
+
+/* Check if leaf PTE entry or not (if X/W/R are set it is) */
+
+#define PTE_LEAF_MASK (7 << 1)
+
+/* Flags for user page tables */
+
+#define MMU_UPGT_FLAGS (0)
+
+/* Flags for user FLASH (RX) and user RAM (RW) */
+
+#define MMU_UTEXT_FLAGS (PTE_R | PTE_X | PTE_U)
+#define MMU_UDATA_FLAGS (PTE_R | PTE_W | PTE_U)
+
+/* SvX definitions, only Sv39 is currently supported, but it should be
+ * trivial to extend the driver to support other SvX implementations
+ *
+ * Sv39 has:
+ * - 4K page size
+ * - 3 page table levels
+ * - 9-bit VPN width
+ */
+
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+#define RV_MMU_PTE_PADDR_SHIFT (10)
+#define RV_MMU_PTE_PPN_MASK ((1 << RV_MMU_PTE_PADDR_SHIFT) - 1)
+#define RV_MMU_PTE_PPN_SHIFT (2)
+#define RV_MMU_VPN_WIDTH (9)
+#define RV_MMU_VPN_MASK ((1 << RV_MMU_VPN_WIDTH) - 1)
+#define RV_MMU_VADDR_SHIFT(_n) (RV_MMU_PAGE_SHIFT + RV_MMU_VPN_WIDTH * \
+ (RV_MMU_PT_LEVELS - (_n)))
+#define RV_MMU_SATP_MODE (SATP_MODE_SV39)
+#define RV_MMU_L1_PAGE_SIZE (0x40000000) /* 1G */
+#define RV_MMU_L2_PAGE_SIZE (0x200000) /* 2M */
+#define RV_MMU_L3_PAGE_SIZE (0x1000) /* 4K */
+#else
+#error "Unsupported RISC-V MMU implementation selected"
+#endif /* CONFIG_ARCH_MMU_TYPE_SV39 */
+
+/****************************************************************************
+ * Name: satp_reg
+ *
+ * Description:
+ * Utility function to build satp register value for input parameters
+ *
+ * Input Parameters:
+ * pgbase - The physical base address of the translation table base
+ * asid - Address space identifier. This can be used to identify different
+ * address spaces. It is not necessary to use this, nor is it necessary
+ * for the RISC-V implementation to implement such bits. This means in
+ * practice that the value should not be used in this generic driver.
+ *
+ ****************************************************************************/
+
+static inline uint64_t satp_reg(uint64_t pgbase, uint16_t asid)
+{
+ uint64_t reg;
+ reg = ((RV_MMU_SATP_MODE << SATP_MODE_SHIFT) & SATP_MODE_MASK);
+ reg |= (((uint64_t)asid << SATP_ASID_SHIFT) & SATP_ASID_MASK);
+ reg |= ((SATP_ADDR_TO_PPN(pgbase) << SATP_PPN_SHIFT) & SATP_PPN_MASK);
+ return reg;
+}
+
+/****************************************************************************
+ * Name: mmu_write_satp
+ *
+ * Description:
+ * Write satp
+ *
+ * Input Parameters:
+ * reg - satp value
+ *
+ ****************************************************************************/
+
+static inline void mmu_write_satp(uint64_t reg)
Review comment:
Yes, if this function will support Sv32 also, all address parameters should change to uintptr_t.
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[GitHub] [incubator-nuttx] xiaoxiang781216 merged pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 merged pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273
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[GitHub] [incubator-nuttx] pussuw commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
pussuw commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787576120
##########
File path: arch/risc-v/src/common/riscv_mmu.h
##########
@@ -0,0 +1,306 @@
+/****************************************************************************
+ * arch/risc-v/src/rv64gc/riscv_mmu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+#define ___ARCH_RISC_V_SRC_RV64GC_RISCV_MMU_H_
+
+#if (__riscv_xlen != 64)
+#error "This MMU implementation is for xlen 64"
+#endif
+
+/* RV64 page size */
+
+#define RV_MMU_PAGE_SHIFT (12)
+#define RV_MMU_PAGE_SIZE (1 << RV_MMU_PAGE_SHIFT) /* 4K pages */
+
+/* Amount of page table levels */
+
+#define RV_MMU_PT_LEVELS (ARCH_PGT_MAX_LEVELS)
+
+/* Supervisor Address Translation and Protection (satp) */
+
+#define SATP_PPN_SHIFT (0)
+#define SATP_PPN_MASK (((1ul << 44) - 1) << SATP_PPN_SHIFT)
+#define SATP_ASID_SHIFT (44)
+#define SATP_ASID_MASK (((1ul << 16) - 1) << SATP_ASID_SHIFT)
+#define SATP_MODE_SHIFT (60)
+#define SATP_MODE_MASK (((1ul << 4) - 1) << SATP_MODE_SHIFT)
+
+/* Modes, 1-7 and 10-15 are reserved */
+
+#define SATP_MODE_BARE (0ul)
+#define SATP_MODE_SV39 (8ul)
+#define SATP_MODE_SV48 (9ul)
+
+/* satp address to PPN translation */
+
+#define SATP_ADDR_TO_PPN(_addr) ((_addr) >> RV_MMU_PAGE_SHIFT)
+
+/* Common Page Table Entry (PTE) bits */
+
+#define PTE_VALID (1 << 0) /* PTE is valid */
+#define PTE_R (1 << 1) /* Page is readable */
+#define PTE_W (1 << 2) /* Page is writable */
+#define PTE_X (1 << 3) /* Page is executable */
+#define PTE_U (1 << 4) /* Page is a user mode page */
+#define PTE_G (1 << 5) /* Page is a global mapping */
+#define PTE_A (1 << 6) /* Page has been accessed */
+#define PTE_D (1 << 7) /* Page is dirty */
+
+/* Check if leaf PTE entry or not (if X/W/R are set it is) */
+
+#define PTE_LEAF_MASK (7 << 1)
+
+/* Flags for user page tables */
+
+#define MMU_UPGT_FLAGS (0)
+
+/* Flags for user FLASH (RX) and user RAM (RW) */
+
+#define MMU_UTEXT_FLAGS (PTE_R | PTE_X | PTE_U)
+#define MMU_UDATA_FLAGS (PTE_R | PTE_W | PTE_U)
+
+/* SvX definitions, only Sv39 is currently supported, but it should be
+ * trivial to extend the driver to support other SvX implementations
+ *
+ * Sv39 has:
+ * - 4K page size
+ * - 3 page table levels
+ * - 9-bit VPN width
+ */
+
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+#define RV_MMU_PTE_PADDR_SHIFT (10)
+#define RV_MMU_PTE_PPN_MASK ((1 << RV_MMU_PTE_PADDR_SHIFT) - 1)
+#define RV_MMU_PTE_PPN_SHIFT (2)
+#define RV_MMU_VPN_WIDTH (9)
+#define RV_MMU_VPN_MASK ((1 << RV_MMU_VPN_WIDTH) - 1)
+#define RV_MMU_VADDR_SHIFT(_n) (RV_MMU_PAGE_SHIFT + RV_MMU_VPN_WIDTH * \
+ (RV_MMU_PT_LEVELS - (_n)))
+#define RV_MMU_SATP_MODE (SATP_MODE_SV39)
+#define RV_MMU_L1_PAGE_SIZE (0x40000000) /* 1G */
+#define RV_MMU_L2_PAGE_SIZE (0x200000) /* 2M */
+#define RV_MMU_L3_PAGE_SIZE (0x1000) /* 4K */
+#else
+#error "Unsupported RISC-V MMU implementation selected"
+#endif /* CONFIG_ARCH_MMU_TYPE_SV39 */
+
+/****************************************************************************
+ * Name: satp_reg
+ *
+ * Description:
+ * Utility function to build satp register value for input parameters
+ *
+ * Input Parameters:
+ * pgbase - The physical base address of the translation table base
+ * asid - Address space identifier. This can be used to identify different
+ * address spaces. It is not necessary to use this, nor is it necessary
+ * for the RISC-V implementation to implement such bits. This means in
+ * practice that the value should not be used in this generic driver.
+ *
+ ****************************************************************************/
+
+static inline uint64_t satp_reg(uint64_t pgbase, uint16_t asid)
+{
+ uint64_t reg;
+ reg = ((RV_MMU_SATP_MODE << SATP_MODE_SHIFT) & SATP_MODE_MASK);
+ reg |= (((uint64_t)asid << SATP_ASID_SHIFT) & SATP_ASID_MASK);
+ reg |= ((SATP_ADDR_TO_PPN(pgbase) << SATP_PPN_SHIFT) & SATP_PPN_MASK);
+ return reg;
+}
+
+/****************************************************************************
+ * Name: mmu_write_satp
+ *
+ * Description:
+ * Write satp
+ *
+ * Input Parameters:
+ * reg - satp value
+ *
+ ****************************************************************************/
+
+static inline void mmu_write_satp(uint64_t reg)
Review comment:
Thanks, will re-factor the arguments
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[GitHub] [incubator-nuttx] no1wudi commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
no1wudi commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r788304484
##########
File path: arch/risc-v/include/arch.h
##########
@@ -62,6 +62,12 @@ uint32_t up_gethartid(void);
#endif
+/* Provide the maximum amount of page table levels per MMU type */
+
+#ifdef CONFIG_ARCH_MMU_TYPE_SV39
+#define ARCH_PGT_MAX_LEVELS (3)
Review comment:
Move this to riscv_mmu.h? It's seems only used in mmu driver.
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[GitHub] [incubator-nuttx] no1wudi commented on a change in pull request #5273: Sv39 MMU driver
Posted by GitBox <gi...@apache.org>.
no1wudi commented on a change in pull request #5273:
URL: https://github.com/apache/incubator-nuttx/pull/5273#discussion_r787549779
##########
File path: arch/risc-v/src/common/riscv_mmu.c
##########
@@ -0,0 +1,129 @@
+/****************************************************************************
+ * arch/risc-v/src/rv64gc/riscv_mmu.c
Review comment:
Great, and we can develop and test the driver for sv32/sv48 on qemu rv32/rv64 in future.
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