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Posted to commits@mynewt.apache.org by GitBox <gi...@apache.org> on 2020/08/27 11:57:13 UTC
[GitHub] [mynewt-core] kasjer commented on a change in pull request #2282: Add initial support for Nordic nRF5340
kasjer commented on a change in pull request #2282:
URL: https://github.com/apache/mynewt-core/pull/2282#discussion_r478282550
##########
File path: hw/bus/drivers/i2c_nrf5340/include/bus/drivers/i2c_nrf5340.h
##########
@@ -0,0 +1,69 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef HW_BUS_DRIVERS_I2C_NRF5340_H_
+#define HW_BUS_DRIVERS_I2C_NRF5340_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include "os/os_dev.h"
+#include "bus/drivers/i2c_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Initialize os_dev as I2C bus device using nRF5340 TWIM peripheral
+ *
+ * This can be passed as a parameter to os_dev_create() when creating os_dev
+ * object for I2C device, however it's recommended to create devices using helper
+ * like bus_i2c_hal_dev_create().
+ *
+ * @param node Node device object
+ * @param arg Node configuration struct (struct bus_node_cfg)
+ */
+int
+bus_i2c_nrf5340_dev_init_func(struct os_dev *odev, void *arg);
Review comment:
return value not explained
##########
File path: hw/mcu/nordic/nrf5340_net/src/hal_watchdog.c
##########
@@ -0,0 +1,78 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <os/mynewt.h>
+#include <hal/hal_watchdog.h>
+#include <mcu/cmsis_nvic.h>
+#include <nrf.h>
+
+static void
+nrf5340_net_hal_wdt_default_handler(void)
+{
+ assert(0);
+}
+
+/**@brief WDT interrupt handler. */
+static void
+nrf5340_net_wdt_irq_handler(void)
+{
+ os_trace_isr_enter();
+ if (NRF_WDT_NS->INTENSET & WDT_INTENSET_TIMEOUT_Msk) {
+ NRF_WDT_NS->EVENTS_TIMEOUT = 0;
+ nrf5340_net_hal_wdt_default_handler();
+ }
+ os_trace_isr_exit();
+}
+
+int
+hal_watchdog_init(uint32_t expire_msecs)
+{
+ uint64_t expiration;
+
+ NRF_WDT_NS->CONFIG = WDT_CONFIG_SLEEP_Msk;
+
+ /* Convert msec timeout to counts of a 32768 crystal */
+ expiration = ((uint64_t)expire_msecs * 32768) / 1000;
+ NRF_WDT_NS->CRV = (uint32_t)expiration;
+
+ NRF_WDT_NS->CRV = (expire_msecs * 32) + ((expire_msecs * 96) / 125);
+
+ NVIC_SetVector(WDT_IRQn, (uint32_t) nrf5340_net_wdt_irq_handler);
+ NVIC_SetPriority(WDT_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
+ NVIC_ClearPendingIRQ(WDT_IRQn);
+ NVIC_EnableIRQ(WDT_IRQn);
+ NRF_WDT_NS->RREN |= 0x1;
+
+ return (0);
Review comment:
other place in this PR does not use (0)
##########
File path: hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
##########
@@ -0,0 +1,243 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <os/os.h>
+#include <ipc_nrf5340/ipc_nrf5340.h>
+#include <nrfx.h>
+
+/* TODO for now this allows only for 1-1 connection */
+
+#define IPC_MAX_CHANS MYNEWT_VAL(IPC_NRF5340_CHANNELS)
+#define IPC_BUF_SIZE (MYNEWT_VAL(IPC_NRF5340_BUF_SZ) + 1)
+
+struct ipc_channel {
+ ipc_nrf5340_recv_cb cb;
+ void *user_data;
+};
+
+struct ipc_shm {
+ volatile uint16_t head;
+ volatile uint16_t tail;
+ uint8_t buf[IPC_BUF_SIZE];
+};
+
+static struct ipc_channel ipcs[IPC_MAX_CHANS];
+
+#if MYNEWT_VAL(BSP_NRF5340)
+static struct ipc_shm __attribute__((section (".ipc"))) shms[IPC_MAX_CHANS];
+#elif MYNEWT_VAL(BSP_NRF5340_NET)
+static struct ipc_shm *shms = (void *)0x20000400;
+#else
+#error "Unsupported CPU"
+#endif
+
+static uint16_t
+ipc_nrf5340_shm_get_data_length(uint16_t head, uint16_t tail)
+{
+ if (head >= tail) {
+ return head - tail;
+ }
+
+ return IPC_BUF_SIZE - (tail - head);
+}
+
+static void
+ipc_nrf5340_shm_write(struct ipc_shm *shm, const void *data, uint16_t data_len)
+{
+ uint16_t head = shm->head;
+ uint16_t tail = shm->tail;
+ uint16_t len;
+
+ if (data_len == 0) {
+ return;
+ }
+
+ /* check if full */
+ assert((head + 1) != tail);
+ assert(data_len + ipc_nrf5340_shm_get_data_length(head, tail) < IPC_BUF_SIZE);
+
+ len = min(data_len, IPC_BUF_SIZE - head);
+ memcpy(shm->buf + head, data, len);
+
+ /* copy second fragment */
+ if (data_len > len) {
+ memcpy(shm->buf, data + len, data_len - len);
+ }
+
+ head += data_len;
+ head %= IPC_BUF_SIZE;
+
+ shm->head = head;
+}
+
+static uint16_t
+ipc_nrf5340_shm_read(struct ipc_shm *shm, void *buf, struct os_mbuf *om,
+ uint16_t len)
+{
+ uint16_t head = shm->head;
+ uint16_t tail = shm->tail;
+ uint16_t frag_len;
+
+ len = min(ipc_nrf5340_shm_get_data_length(head, tail), len);
+ if (len == 0) {
+ return 0;
+ }
+
+ if (buf || om) {
+ if (head >= tail) {
+ if (buf) {
+ memcpy(buf, shm->buf + tail, len);
+ } else {
+ os_mbuf_append(om, shm->buf + tail, len);
+ }
+ } else {
+ /* in this case we may need to copy two fragments */
+ frag_len = min(len, IPC_BUF_SIZE - tail);
+ if (buf) {
+ memcpy(buf, shm->buf + tail, frag_len);
+ } else {
+ os_mbuf_append(om, shm->buf + tail, frag_len);
+ }
+
+ if (frag_len < len) {
+ assert(tail + frag_len == IPC_BUF_SIZE);
+ assert(len - frag_len <= head);
+ if (buf) {
+ memcpy(buf + frag_len, shm->buf, len - frag_len);
+ } else {
+ os_mbuf_append(om, shm->buf, len - frag_len);
+ }
+ }
+ }
+ }
+
+ tail += len;
+ tail %= IPC_BUF_SIZE;
+
+ shm->tail = tail;
+
+ return len;
+}
+
+static void
+ipc_nrf5340_isr(void)
+{
+ uint32_t irq_pend;
+ int i;
+
+ os_trace_isr_enter();
+
+ irq_pend = NRF_IPC->INTPEND;
+
+ for (i = 0; i < IPC_MAX_CHANS; i++) {
+ if (irq_pend & (0x1UL << i)) {
+ NRF_IPC->EVENTS_RECEIVE[i] = 0;
+ assert(ipcs[i].cb);
+ ipcs[i].cb(i, ipcs[i].user_data);
+ }
+ }
+
+ os_trace_isr_exit();
+}
+
+void
+ipc_nrf5340_init(void)
+{
+#if MYNEWT_VAL(BSP_NRF5340)
+ /* Make sure network core if off when we set up IPC */
+ NRF_RESET_S->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Hold;
+ memset(shms, 0, sizeof(shms));
+#endif
+
+ NVIC_SetVector(IPC_IRQn, (uint32_t)ipc_nrf5340_isr);
+ NVIC_EnableIRQ(IPC_IRQn);
+
+#if MYNEWT_VAL(BSP_NRF5340)
+ /* this allows netcore to access appcore RAM */
+ NRF_SPU_S->EXTDOMAIN[0].PERM = SPU_EXTDOMAIN_PERM_SECATTR_Secure << SPU_EXTDOMAIN_PERM_SECATTR_Pos;
+
+ /* Start Network Core */
+ NRF_RESET_S->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Release;
+#endif
+}
+
+void
+ipc_nrf5340_recv(int channel, ipc_nrf5340_recv_cb cb, void *user_data)
+{
+ assert(channel < IPC_MAX_CHANS);
+
+ if (cb) {
+ ipcs[channel].cb = cb;
+ ipcs[channel].user_data = user_data;
+ NRF_IPC->RECEIVE_CNF[channel] = (0x1UL << channel);
+ NRF_IPC->INTENSET = (0x1UL << channel);
+ } else {
+ NRF_IPC->INTENCLR = (0x1UL << channel);
+ NRF_IPC->RECEIVE_CNF[channel] = (0x0UL << channel);
Review comment:
shifting 0 does not seem to do much
##########
File path: hw/mcu/nordic/nrf5340/include/mcu/nrf5340_hal.h
##########
@@ -0,0 +1,85 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef _NRF5340_HAL_H_
+#define _NRF5340_HAL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Helper functions to enable/disable interrupts. */
+#define __HAL_DISABLE_INTERRUPTS(x) \
+ do { \
+ x = __get_PRIMASK(); \
+ __disable_irq(); \
+ } while (0)
+
+#define __HAL_ENABLE_INTERRUPTS(x) \
+ do { \
+ if (!x) { \
+ __enable_irq(); \
+ } \
+ } while (0)
+
+struct nrf5340_uart_cfg {
+ int8_t suc_pin_tx; /* pins for IO */
+ int8_t suc_pin_rx;
+ int8_t suc_pin_rts;
+ int8_t suc_pin_cts;
+};
+const struct nrf5340_uart_cfg *bsp_uart_config(void);
+
+struct hal_flash;
+extern const struct hal_flash nrf5340_flash_dev;
+
+/* SPI configuration (used for both master and slave) */
+struct nrf5340_hal_spi_cfg {
+ uint8_t sck_pin;
Review comment:
why pins are of different type then uart's?
##########
File path: hw/mcu/nordic/nrf5340_net/src/hal_uart.c
##########
@@ -0,0 +1,347 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <os/mynewt.h>
+#include <hal/hal_uart.h>
+#include <mcu/cmsis_nvic.h>
+#include <bsp/bsp.h>
+#include <nrf.h>
+#include <mcu/nrf5340_net_hal.h>
+
+#if MYNEWT_VAL(UART_0)
+#endif
+
+#define UARTE_INT_ENDTX UARTE_INTEN_ENDTX_Msk
+#define UARTE_INT_ENDRX UARTE_INTEN_ENDRX_Msk
+#define UARTE_CONFIG_PARITY UARTE_CONFIG_PARITY_Msk
+#define UARTE_CONFIG_HWFC UARTE_CONFIG_HWFC_Msk
+#define UARTE_ENABLE UARTE_ENABLE_ENABLE_Enabled
+#define UARTE_DISABLE UARTE_ENABLE_ENABLE_Disabled
+
+struct hal_uart {
+ uint8_t u_open : 1;
+ uint8_t u_rx_stall : 1;
+ volatile uint8_t u_tx_started : 1;
+
+ uint8_t u_rx_buf;
+ uint8_t u_tx_buf[8];
+
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+};
+
+static struct hal_uart uart0;
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ if (port != 0 || uart0.u_open) {
+ return -1;
+ }
+
+ uart0.u_rx_func = rx_func;
+ uart0.u_tx_func = tx_func;
+ uart0.u_tx_done = tx_done;
+ uart0.u_func_arg = arg;
+
+ return 0;
+}
+
+static int
+hal_uart_tx_fill_buf(struct hal_uart *u)
+{
+ int data;
+ int i;
+
+ for (i = 0; i < sizeof(u->u_tx_buf); i++) {
+ data = u->u_tx_func(u->u_func_arg);
+ if (data < 0) {
+ break;
+ }
+ u->u_tx_buf[i] = data;
+ }
+ return i;
+}
+
+void
+hal_uart_start_tx(int port)
+{
+ int sr;
+ int rc;
+
+ if (port != 0) {
+ return;
+ }
+
+ __HAL_DISABLE_INTERRUPTS(sr);
+ if (uart0.u_tx_started == 0) {
+ rc = hal_uart_tx_fill_buf(&uart0);
+ if (rc > 0) {
+ NRF_UARTE0_NS->INTENSET = UARTE_INT_ENDTX;
+ NRF_UARTE0_NS->TXD.PTR = (uint32_t)&uart0.u_tx_buf;
+ NRF_UARTE0_NS->TXD.MAXCNT = rc;
+ NRF_UARTE0_NS->TASKS_STARTTX = 1;
+ uart0.u_tx_started = 1;
+ }
+ }
+ __HAL_ENABLE_INTERRUPTS(sr);
+}
+
+void
+hal_uart_start_rx(int port)
+{
+ int sr;
+ int rc;
+
+ if (port != 0) {
+ return;
+ }
+
+ if (uart0.u_rx_stall) {
+ __HAL_DISABLE_INTERRUPTS(sr);
+ rc = uart0.u_rx_func(uart0.u_func_arg, uart0.u_rx_buf);
+ if (rc == 0) {
+ uart0.u_rx_stall = 0;
+ NRF_UARTE0_NS->TASKS_STARTRX = 1;
+ }
+
+ __HAL_ENABLE_INTERRUPTS(sr);
+ }
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t data)
+{
+ if (port != 0 || !uart0.u_open) {
+ return;
+ }
+
+ /* If we have started, wait until the current uart dma buffer is done */
+ if (uart0.u_tx_started) {
+ while (NRF_UARTE0_NS->EVENTS_ENDTX == 0) {
+ /* Wait here until the dma is finished */
+ }
+ }
+
+ NRF_UARTE0_NS->EVENTS_ENDTX = 0;
+ NRF_UARTE0_NS->TXD.PTR = (uint32_t)&data;
+ NRF_UARTE0_NS->TXD.MAXCNT = 1;
+ NRF_UARTE0_NS->TASKS_STARTTX = 1;
+
+ while (NRF_UARTE0_NS->EVENTS_ENDTX == 0) {
+ /* Wait till done */
+ }
+
+ /* Stop the uart */
+ NRF_UARTE0_NS->TASKS_STOPTX = 1;
+}
+
+static void
+uart0_irq_handler(void)
+{
+ int rc;
+
+ os_trace_isr_enter();
+
+ if (NRF_UARTE0_NS->EVENTS_ENDTX) {
+ NRF_UARTE0_NS->EVENTS_ENDTX = 0;
+ rc = hal_uart_tx_fill_buf(&uart0);
+ if (rc > 0) {
+ NRF_UARTE0_NS->TXD.PTR = (uint32_t)uart0.u_tx_buf;
+ NRF_UARTE0_NS->TXD.MAXCNT = rc;
+ NRF_UARTE0_NS->TASKS_STARTTX = 1;
+ } else {
+ if (uart0.u_tx_done) {
+ uart0.u_tx_done(uart0.u_func_arg);
+ }
+ NRF_UARTE0_NS->INTENCLR = UARTE_INT_ENDTX;
+ NRF_UARTE0_NS->TASKS_STOPTX = 1;
+ uart0.u_tx_started = 0;
+ }
+ }
+ if (NRF_UARTE0_NS->EVENTS_ENDRX) {
+ NRF_UARTE0_NS->EVENTS_ENDRX = 0;
+ rc = uart0.u_rx_func(uart0.u_func_arg, uart0.u_rx_buf);
+ if (rc < 0) {
+ uart0.u_rx_stall = 1;
+ } else {
+ NRF_UARTE0_NS->TASKS_STARTRX = 1;
+ }
+ }
+ os_trace_isr_exit();
+}
+
+static uint32_t
+hal_uart_baudrate(int baudrate)
+{
+ switch (baudrate) {
+ case 1200:
+ return UARTE_BAUDRATE_BAUDRATE_Baud1200;
+ case 2400:
+ return UARTE_BAUDRATE_BAUDRATE_Baud2400;
+ case 4800:
+ return UARTE_BAUDRATE_BAUDRATE_Baud4800;
+ case 9600:
+ return UARTE_BAUDRATE_BAUDRATE_Baud9600;
+ case 14400:
+ return UARTE_BAUDRATE_BAUDRATE_Baud14400;
+ case 19200:
+ return UARTE_BAUDRATE_BAUDRATE_Baud19200;
+ case 28800:
+ return UARTE_BAUDRATE_BAUDRATE_Baud28800;
+ case 38400:
+ return UARTE_BAUDRATE_BAUDRATE_Baud38400;
+ case 56000:
+ return UARTE_BAUDRATE_BAUDRATE_Baud56000;
+ case 57600:
+ return UARTE_BAUDRATE_BAUDRATE_Baud57600;
+ case 76800:
+ return UARTE_BAUDRATE_BAUDRATE_Baud76800;
+ case 115200:
+ return UARTE_BAUDRATE_BAUDRATE_Baud115200;
+ case 230400:
+ return UARTE_BAUDRATE_BAUDRATE_Baud230400;
+ case 250000:
+ return UARTE_BAUDRATE_BAUDRATE_Baud250000;
+ case 460800:
+ return UARTE_BAUDRATE_BAUDRATE_Baud460800;
+ case 921600:
+ return UARTE_BAUDRATE_BAUDRATE_Baud921600;
+ case 1000000:
+ return UARTE_BAUDRATE_BAUDRATE_Baud1M;
+ default:
+ return 0;
+ }
+}
+
+int
+hal_uart_init(int port, void *arg)
+{
+ struct nrf5340_net_uart_cfg *cfg = arg;
+
+ if (port != 0) {
+ return -1;
+ }
+
+ NRF_UARTE0_NS->PSEL.TXD = cfg->suc_pin_tx;
+ NRF_UARTE0_NS->PSEL.RXD = cfg->suc_pin_rx;
+ NRF_UARTE0_NS->PSEL.RTS = cfg->suc_pin_rts;
+ NRF_UARTE0_NS->PSEL.CTS = cfg->suc_pin_cts;
+
+ NVIC_SetVector(SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn,
+ (uint32_t)uart0_irq_handler);
+
+ return 0;
+}
+
+int
+hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
+ enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
+{
+ uint32_t cfg_reg = 0;
+ uint32_t baud_reg;
+
+ if (port != 0 || uart0.u_open) {
+ return -1;
+ }
+
+ /*
+ * pin config
+ * UART config
+ * nvic config
+ * enable uart
+ */
+ if (databits != 8) {
+ return -1;
+ }
+ if (stopbits != 1) {
+ return -1;
+ }
+
+ switch (parity) {
+ case HAL_UART_PARITY_NONE:
+ break;
+ case HAL_UART_PARITY_ODD:
+ return -1;
Review comment:
Odd parity is supported by this chip
##########
File path: hw/mcu/nordic/nrf5340/src/nrf5340_hw_id.c
##########
@@ -0,0 +1,43 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <hal/hal_bsp.h>
+#include <nrf.h>
+#include <os/os.h>
+
+int
+hal_bsp_hw_id_len(void)
+{
+ return sizeof(NRF_FICR_S->INFO.DEVICEID);
+}
+
+/*
+ * These values are generated at random.
+ * DEVICEID
+ */
+int
+hal_bsp_hw_id(uint8_t *id, int max_len)
+{
+ max_len = min(sizeof(NRF_FICR_S->INFO.DEVICEID), max_len);
+
+ memcpy(id, (void *) &NRF_FICR_S->INFO.DEVICEID, max_len);
Review comment:
space after cast
##########
File path: hw/mcu/nordic/nrf5340/src/hal_watchdog.c
##########
@@ -0,0 +1,78 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <os/mynewt.h>
+#include <hal/hal_watchdog.h>
+#include <mcu/cmsis_nvic.h>
+#include <nrf.h>
+
+static void
+nrf5340_hal_wdt_default_handler(void)
+{
+ assert(0);
+}
+
+/**@brief WDT interrupt handler. */
+static void
+nrf5340_wdt_irq_handler(void)
+{
+ os_trace_isr_enter();
+ if (NRF_WDT0_S->INTENSET & WDT_INTENSET_TIMEOUT_Msk) {
+ NRF_WDT0_S->EVENTS_TIMEOUT = 0;
+ nrf5340_hal_wdt_default_handler();
+ }
+ os_trace_isr_exit();
+}
+
+int
+hal_watchdog_init(uint32_t expire_msecs)
+{
+ uint64_t expiration;
+
+ NRF_WDT0_S->CONFIG = WDT_CONFIG_SLEEP_Msk;
+
+ /* Convert msec timeout to counts of a 32768 crystal */
+ expiration = ((uint64_t)expire_msecs * 32768) / 1000;
+ NRF_WDT0_S->CRV = (uint32_t)expiration;
+
+ NRF_WDT0_S->CRV = (expire_msecs * 32) + ((expire_msecs * 96) / 125);
+
+ NVIC_SetVector(WDT0_IRQn, (uint32_t) nrf5340_wdt_irq_handler);
+ NVIC_SetPriority(WDT0_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
+ NVIC_ClearPendingIRQ(WDT0_IRQn);
+ NVIC_EnableIRQ(WDT0_IRQn);
+ NRF_WDT0_S->RREN |= 0x1;
+
+ return (0);
Review comment:
**(0)** not so common in this PR
##########
File path: hw/mcu/nordic/nrf5340_net/include/mcu/cmsis_nvic.h
##########
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef _CMSIS_NVIC_H_
+#define _CMSIS_NVIC_H_
+
+#include <stdint.h>
+#include <nrf.h>
+
+#define NVIC_NUM_VECTORS (16 + 20) /* CORE + MCU Peripherals */
Review comment:
where this number (20) come from?
##########
File path: hw/mcu/nordic/nrf5340/include/mcu/cmsis_nvic.h
##########
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef _CMSIS_NVIC_H_
+#define _CMSIS_NVIC_H_
+
+#include <stdint.h>
+#include <nrf.h>
+
+#define NVIC_NUM_VECTORS (16 + 39) /* CORE + MCU Peripherals */
Review comment:
Are you sure 39 is correct number?
##########
File path: hw/mcu/nordic/nrf5340_net/src/hal_watchdog.c
##########
@@ -0,0 +1,78 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <os/mynewt.h>
+#include <hal/hal_watchdog.h>
+#include <mcu/cmsis_nvic.h>
+#include <nrf.h>
+
+static void
+nrf5340_net_hal_wdt_default_handler(void)
+{
+ assert(0);
+}
+
+/**@brief WDT interrupt handler. */
+static void
+nrf5340_net_wdt_irq_handler(void)
+{
+ os_trace_isr_enter();
+ if (NRF_WDT_NS->INTENSET & WDT_INTENSET_TIMEOUT_Msk) {
+ NRF_WDT_NS->EVENTS_TIMEOUT = 0;
+ nrf5340_net_hal_wdt_default_handler();
+ }
+ os_trace_isr_exit();
+}
+
+int
+hal_watchdog_init(uint32_t expire_msecs)
+{
+ uint64_t expiration;
+
+ NRF_WDT_NS->CONFIG = WDT_CONFIG_SLEEP_Msk;
+
+ /* Convert msec timeout to counts of a 32768 crystal */
+ expiration = ((uint64_t)expire_msecs * 32768) / 1000;
+ NRF_WDT_NS->CRV = (uint32_t)expiration;
+
+ NRF_WDT_NS->CRV = (expire_msecs * 32) + ((expire_msecs * 96) / 125);
+
+ NVIC_SetVector(WDT_IRQn, (uint32_t) nrf5340_net_wdt_irq_handler);
Review comment:
cast used few lines above does not have space
##########
File path: hw/bsp/nordic_pca10095/nordic_pca10095_debug.sh
##########
@@ -0,0 +1,46 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - RESET set if target should be reset when attaching
+# - NO_GDB set if we should not start gdb to debug
+#
+
+. $CORE_PATH/hw/scripts/jlink.sh
+
+FILE_NAME=$BIN_BASENAME.elf
+
+if [ $# -gt 2 ]; then
+ SPLIT_ELF_NAME=$3.elf
+ # TODO -- this magic number 0x82000 is the location of the second image
Review comment:
Comment is strange, magic number is nowhere to be seen
##########
File path: hw/drivers/ipc_nrf5340/include/ipc_nrf5340/ipc_nrf5340.h
##########
@@ -0,0 +1,37 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef _HW_DRIVERS_IPC_NRF5340_H
+#define _HW_DRIVERS_IPC_NRF5340_H
+
+#include <stdint.h>
+
+typedef void (*ipc_nrf5340_recv_cb)(int channel, void *user_data);
+
+void ipc_nrf5340_init(void);
Review comment:
Doxygen in this header would not hurt
##########
File path: hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
##########
@@ -0,0 +1,243 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <os/os.h>
+#include <ipc_nrf5340/ipc_nrf5340.h>
+#include <nrfx.h>
+
+/* TODO for now this allows only for 1-1 connection */
Review comment:
For TODO I would specify what needs to be done.
It here is no intention to do anything about it, maybe NOTE would do.
##########
File path: hw/drivers/ipc_nrf5340/include/ipc_nrf5340/ipc_nrf5340.h
##########
@@ -0,0 +1,37 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef _HW_DRIVERS_IPC_NRF5340_H
+#define _HW_DRIVERS_IPC_NRF5340_H
+
+#include <stdint.h>
+
+typedef void (*ipc_nrf5340_recv_cb)(int channel, void *user_data);
+
+void ipc_nrf5340_init(void);
+void ipc_nrf5340_recv(int channel, ipc_nrf5340_recv_cb cb, void *user_data);
+void ipc_nrf5340_send(int channel, const void *data, uint16_t len);
+
+/* should be used only from ipc_nrf5340_recv_cb context */
+uint16_t ipc_nrf5340_read(int channel, void *data, uint16_t len);
+uint16_t ipc_nrf5340_read_om(int channel, struct os_mbuf *om, uint16_t len);
+uint16_t ipc_nrf5340_len(int channel);
Review comment:
**_available** instead of **_len** seems more common
##########
File path: hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
##########
@@ -0,0 +1,243 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <os/os.h>
+#include <ipc_nrf5340/ipc_nrf5340.h>
+#include <nrfx.h>
+
+/* TODO for now this allows only for 1-1 connection */
+
+#define IPC_MAX_CHANS MYNEWT_VAL(IPC_NRF5340_CHANNELS)
+#define IPC_BUF_SIZE (MYNEWT_VAL(IPC_NRF5340_BUF_SZ) + 1)
+
+struct ipc_channel {
+ ipc_nrf5340_recv_cb cb;
+ void *user_data;
+};
+
+struct ipc_shm {
+ volatile uint16_t head;
+ volatile uint16_t tail;
+ uint8_t buf[IPC_BUF_SIZE];
+};
+
+static struct ipc_channel ipcs[IPC_MAX_CHANS];
+
+#if MYNEWT_VAL(BSP_NRF5340)
+static struct ipc_shm __attribute__((section (".ipc"))) shms[IPC_MAX_CHANS];
+#elif MYNEWT_VAL(BSP_NRF5340_NET)
+static struct ipc_shm *shms = (void *)0x20000400;
+#else
+#error "Unsupported CPU"
+#endif
+
+static uint16_t
+ipc_nrf5340_shm_get_data_length(uint16_t head, uint16_t tail)
+{
+ if (head >= tail) {
+ return head - tail;
+ }
+
+ return IPC_BUF_SIZE - (tail - head);
+}
+
+static void
+ipc_nrf5340_shm_write(struct ipc_shm *shm, const void *data, uint16_t data_len)
+{
+ uint16_t head = shm->head;
+ uint16_t tail = shm->tail;
+ uint16_t len;
+
+ if (data_len == 0) {
+ return;
+ }
+
+ /* check if full */
+ assert((head + 1) != tail);
+ assert(data_len + ipc_nrf5340_shm_get_data_length(head, tail) < IPC_BUF_SIZE);
Review comment:
If those asserts are a way to halt execution when write can't be performed. First one could be removed since it is also covered by second check.
If on the other hand they are here for development sake to assert what are conditions (and could be later removed by NDEBUG) then function will fail when Mynewt finally adopt convention that assert no code when NDEBUG is defined.
##########
File path: hw/mcu/nordic/nrf5340/src/hal_uart.c
##########
@@ -0,0 +1,459 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <os/mynewt.h>
+#include <hal/hal_uart.h>
+#include <mcu/cmsis_nvic.h>
+#include <bsp/bsp.h>
+#include <nrf.h>
+#include <mcu/nrf5340_hal.h>
+
+#define UARTE_INT_ENDTX UARTE_INTEN_ENDTX_Msk
+#define UARTE_INT_ENDRX UARTE_INTEN_ENDRX_Msk
+#define UARTE_CONFIG_PARITY UARTE_CONFIG_PARITY_Msk
+#define UARTE_CONFIG_HWFC UARTE_CONFIG_HWFC_Msk
+#define UARTE_ENABLE UARTE_ENABLE_ENABLE_Enabled
+#define UARTE_DISABLE UARTE_ENABLE_ENABLE_Disabled
+
+struct hal_uart {
+ uint8_t u_open : 1;
+ uint8_t u_rx_stall : 1;
+ uint8_t u_tx_started : 1;
+ uint8_t u_rx_buf;
+ uint8_t u_tx_buf[8];
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+
+ NRF_UARTE_Type *nrf_uart;
+ uint32_t handler;
+ IRQn_Type irqn;
+};
+
+
+#if MYNEWT_VAL(UART_0)
+static struct hal_uart uart0;
+#endif
+#if MYNEWT_VAL(UART_1)
+static struct hal_uart uart1;
+#endif
+#if MYNEWT_VAL(UART_2)
+static struct hal_uart uart2;
+#endif
+#if MYNEWT_VAL(UART_3)
+static struct hal_uart uart3;
+#endif
+
+static struct hal_uart *
+hal_uart_get(int port)
+{
+ switch (port) {
+ #if MYNEWT_VAL(UART_0)
+ case 0:
+ return &uart0;
+ #endif
+ #if MYNEWT_VAL(UART_1)
+ case 1:
+ return &uart1;
+ #endif
+ #if MYNEWT_VAL(UART_2)
+ case 2:
+ return &uart2;
+ #endif
+ #if MYNEWT_VAL(UART_3)
+ case 3:
+ return &uart3;
+ #endif
+ default:
+ return NULL;
+ }
+}
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ struct hal_uart *u = hal_uart_get(port);
+
+ if (!u || u->u_open) {
+ return -1;
+ }
+ u->u_rx_func = rx_func;
+ u->u_tx_func = tx_func;
+ u->u_tx_done = tx_done;
+ u->u_func_arg = arg;
+
+ return 0;
+}
+
+static int
+hal_uart_tx_fill_buf(struct hal_uart *u)
+{
+ int data;
+ int i;
+
+ for (i = 0; i < sizeof(u->u_tx_buf); i++) {
+ data = u->u_tx_func(u->u_func_arg);
+ if (data < 0) {
+ break;
+ }
+ u->u_tx_buf[i] = data;
+ }
+ return i;
+}
+
+void
+hal_uart_start_tx(int port)
+{
+ struct hal_uart *u = hal_uart_get(port);
+ int sr;
+ int rc;
+
+ if (!u) {
+ return;
+ }
+
+ __HAL_DISABLE_INTERRUPTS(sr);
+ if (u->u_tx_started == 0) {
+ rc = hal_uart_tx_fill_buf(u);
+ if (rc > 0) {
+ u->nrf_uart->INTENSET = UARTE_INT_ENDTX;
+ u->nrf_uart->TXD.PTR = (uint32_t)&u->u_tx_buf;
+ u->nrf_uart->TXD.MAXCNT = rc;
+ u->nrf_uart->TASKS_STARTTX = 1;
+ u->u_tx_started = 1;
+ }
+ }
+ __HAL_ENABLE_INTERRUPTS(sr);
+}
+
+void
+hal_uart_start_rx(int port)
+{
+ struct hal_uart *u = hal_uart_get(port);
+ int sr;
+ int rc;
+
+ if (!u) {
+ return;
+ }
+
+ if (u->u_rx_stall) {
+ __HAL_DISABLE_INTERRUPTS(sr);
+ rc = u->u_rx_func(u->u_func_arg, u->u_rx_buf);
+ if (rc == 0) {
+ u->u_rx_stall = 0;
+ u->nrf_uart->TASKS_STARTRX = 1;
+ }
+
+ __HAL_ENABLE_INTERRUPTS(sr);
+ }
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t data)
+{
+ struct hal_uart *u = hal_uart_get(port);
+
+ if (!u || !u->u_open) {
+ return;
+ }
+
+ /* If we have started, wait until the current uart dma buffer is done */
+ if (u->u_tx_started) {
+ while (u->nrf_uart->EVENTS_ENDTX == 0) {
+ /* Wait here until the dma is finished */
+ }
+ }
+
+ u->nrf_uart->EVENTS_ENDTX = 0;
+ u->nrf_uart->TXD.PTR = (uint32_t)&data;
+ u->nrf_uart->TXD.MAXCNT = 1;
+ u->nrf_uart->TASKS_STARTTX = 1;
+
+ while (u->nrf_uart->EVENTS_ENDTX == 0) {
+ /* Wait till done */
+ }
+
+ /* Stop the uart */
+ u->nrf_uart->TASKS_STOPTX = 1;
+}
+
+#if MYNEWT_VAL(UART_0) || MYNEWT_VAL(UART_1) || MYNEWT_VAL(UART_2) || MYNEWT_VAL(UART_3)
+static void
+uart_irq_handler(struct hal_uart *u)
+{
+ NRF_UARTE_Type *nrf_uart = u->nrf_uart;
+ int rc;
+
+ os_trace_isr_enter();
+
+ if (nrf_uart->EVENTS_ENDTX) {
+ nrf_uart->EVENTS_ENDTX = 0;
+ rc = hal_uart_tx_fill_buf(u);
+ if (rc > 0) {
+ nrf_uart->TXD.PTR = (uint32_t)&u->u_tx_buf;
+ nrf_uart->TXD.MAXCNT = rc;
+ nrf_uart->TASKS_STARTTX = 1;
+ } else {
+ if (u->u_tx_done) {
+ u->u_tx_done(u->u_func_arg);
+ }
+ nrf_uart->INTENCLR = UARTE_INT_ENDTX;
+ nrf_uart->TASKS_STOPTX = 1;
+ u->u_tx_started = 0;
+ }
+ }
+ if (nrf_uart->EVENTS_ENDRX) {
+ nrf_uart->EVENTS_ENDRX = 0;
+ rc = u->u_rx_func(u->u_func_arg, u->u_rx_buf);
+ if (rc < 0) {
+ u->u_rx_stall = 1;
+ } else {
+ nrf_uart->TASKS_STARTRX = 1;
+ }
+ }
+ os_trace_isr_exit();
+}
+#endif
+
+#if MYNEWT_VAL(UART_0)
+static void
+uart0_irq_handler(void)
+{
+ uart_irq_handler(&uart0);
+}
+#endif
+
+#if MYNEWT_VAL(UART_1)
+static void
+uart1_irq_handler(void)
+{
+ uart_irq_handler(&uart1);
+}
+#endif
+
+#if MYNEWT_VAL(UART_2)
+static void
+uart2_irq_handler(void)
+{
+ uart_irq_handler(&uart2);
+}
+#endif
+
+#if MYNEWT_VAL(UART_3)
+static void
+uart3_irq_handler(void)
+{
+ uart_irq_handler(&uart3);
+}
+#endif
+
+static uint32_t
+hal_uart_baudrate(int baudrate)
+{
+ switch (baudrate) {
+ case 1200:
+ return UARTE_BAUDRATE_BAUDRATE_Baud1200;
+ case 2400:
+ return UARTE_BAUDRATE_BAUDRATE_Baud2400;
+ case 4800:
+ return UARTE_BAUDRATE_BAUDRATE_Baud4800;
+ case 9600:
+ return UARTE_BAUDRATE_BAUDRATE_Baud9600;
+ case 14400:
+ return UARTE_BAUDRATE_BAUDRATE_Baud14400;
+ case 19200:
+ return UARTE_BAUDRATE_BAUDRATE_Baud19200;
+ case 28800:
+ return UARTE_BAUDRATE_BAUDRATE_Baud28800;
+ case 38400:
+ return UARTE_BAUDRATE_BAUDRATE_Baud38400;
+ case 56000:
+ return UARTE_BAUDRATE_BAUDRATE_Baud56000;
+ case 57600:
+ return UARTE_BAUDRATE_BAUDRATE_Baud57600;
+ case 76800:
+ return UARTE_BAUDRATE_BAUDRATE_Baud76800;
+ case 115200:
+ return UARTE_BAUDRATE_BAUDRATE_Baud115200;
+ case 230400:
+ return UARTE_BAUDRATE_BAUDRATE_Baud230400;
+ case 250000:
+ return UARTE_BAUDRATE_BAUDRATE_Baud250000;
+ case 460800:
+ return UARTE_BAUDRATE_BAUDRATE_Baud460800;
+ case 921600:
+ return UARTE_BAUDRATE_BAUDRATE_Baud921600;
+ case 1000000:
+ return UARTE_BAUDRATE_BAUDRATE_Baud1M;
+ default:
+ return 0;
+ }
+}
+
+int
+hal_uart_init(int port, void *arg)
+{
+ struct hal_uart *u = hal_uart_get(port);
+ struct nrf5340_uart_cfg *cfg = arg;
+
+ if (!u) {
+ return -1;
+ }
+
+ switch (port) {
+ #if MYNEWT_VAL(UART_0)
+ case 0:
+ u->nrf_uart = NRF_UARTE0_S;
+ u->handler = (uint32_t)uart0_irq_handler;
+ u->irqn = SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn;
+ break;
+ #endif
+ #if MYNEWT_VAL(UART_1)
+ case 1:
+ u->nrf_uart = NRF_UARTE1_S;
+ u->handler = (uint32_t)uart1_irq_handler;
+ u->irqn = SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn;
+ break;
+ #endif
+ #if MYNEWT_VAL(UART_2)
+ case 2:
+ u->nrf_uart = NRF_UARTE2_S;
+ u->handler = (uint32_t)uart2_irq_handler;
+ u->irqn = SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn;
+ break;
+ #endif
+ #if MYNEWT_VAL(UART_3)
+ case 3:
+ u->nrf_uart = NRF_UARTE3_S;
+ u->handler = (uint32_t)uart3_irq_handler;
+ u->irqn = SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn;
+ break;
+ #endif
+ default:
+ assert(false);
+ }
+
+ u->nrf_uart->PSEL.TXD = cfg->suc_pin_tx;
+ u->nrf_uart->PSEL.RXD = cfg->suc_pin_rx;
+ u->nrf_uart->PSEL.RTS = cfg->suc_pin_rts;
+ u->nrf_uart->PSEL.CTS = cfg->suc_pin_cts;
+
+ NVIC_SetVector(u->irqn, u->handler);
+
+ return 0;
+}
+
+int
+hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
+ enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
+{
+ struct hal_uart *u = hal_uart_get(port);
+ uint32_t cfg_reg = 0;
+ uint32_t baud_reg;
+
+ if (!u || u->u_open) {
+ return -1;
+ }
+
+ /*
+ * pin config
+ * UART config
+ * nvic config
+ * enable uart
+ */
+ if (databits != 8) {
+ return -1;
+ }
+ if (stopbits != 1) {
+ return -1;
+ }
+
+ switch (parity) {
+ case HAL_UART_PARITY_NONE:
+ break;
+ case HAL_UART_PARITY_ODD:
Review comment:
Odd parity is supported by this chip I think.
##########
File path: hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
##########
@@ -0,0 +1,243 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <os/os.h>
+#include <ipc_nrf5340/ipc_nrf5340.h>
+#include <nrfx.h>
+
+/* TODO for now this allows only for 1-1 connection */
+
+#define IPC_MAX_CHANS MYNEWT_VAL(IPC_NRF5340_CHANNELS)
+#define IPC_BUF_SIZE (MYNEWT_VAL(IPC_NRF5340_BUF_SZ) + 1)
+
+struct ipc_channel {
+ ipc_nrf5340_recv_cb cb;
+ void *user_data;
+};
+
+struct ipc_shm {
+ volatile uint16_t head;
+ volatile uint16_t tail;
+ uint8_t buf[IPC_BUF_SIZE];
+};
+
+static struct ipc_channel ipcs[IPC_MAX_CHANS];
+
+#if MYNEWT_VAL(BSP_NRF5340)
+static struct ipc_shm __attribute__((section (".ipc"))) shms[IPC_MAX_CHANS];
+#elif MYNEWT_VAL(BSP_NRF5340_NET)
+static struct ipc_shm *shms = (void *)0x20000400;
+#else
Review comment:
This conditional definition could be avoided if following things were added to linker scripts:
**hw/bsp/nordic_pca10095_net/nrf5340_net.ld**
```
MEMORY
{
FLASH (rx) : ORIGIN = 0x01008000, LENGTH = 0x19000
RAM (rwx) : ORIGIN = 0x21000000, LENGTH = 0x10000
IPC (rw) : ORIGIN = 0x20000400, LENGTH = 0x1000
}
```
and **hw/mcu/nordic/nrf5340_net/nrf5340_net.ld**
```
.ipc (NOLOAD):
{
*(.ipc)
} > IPC
```
It also generates slightly sorter code with GCC.
##########
File path: hw/mcu/nordic/nrf5340_net/include/mcu/mcu.h
##########
@@ -0,0 +1,55 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef _MCU_H_
+#define _MCU_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Defines for naming GPIOs. NOTE: the nordic chip docs use numeric labels for
+ * ports. Port A corresponds to Port 0, B to 1, etc. The nrf5340 has two ports
+ * but Port 1 only has 16 pins.
+ */
+#define MCU_GPIO_PORTA(pin) ((0 * 16) + (pin))
+#define MCU_GPIO_PORTB(pin) ((1 * 16) + (pin))
+
+//TODO
Review comment:
Is there anything to do here?
##########
File path: hw/mcu/nordic/nrf5340_net/src/hal_os_tick.c
##########
@@ -0,0 +1,210 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <os/mynewt.h>
+#include <hal/hal_os_tick.h>
+#include <nrf.h>
+#include <mcu/cmsis_nvic.h>
+
+/* The OS scheduler requires a low-frequency timer. */
+#if MYNEWT_VAL(OS_SCHEDULING) && !MYNEWT_VAL(MCU_LFCLK_SOURCE)
+ #error The OS scheduler requires a low-frequency timer; configure MCU_LFCLK_SOURCE
+#endif
+
+#define RTC_FREQ 32768 /* in Hz */
+#define OS_TICK_TIMER NRF_RTC1_NS
+#define OS_TICK_IRQ RTC1_IRQn
+#define OS_TICK_CMPREG 3 /* generate timer interrupt */
Review comment:
This comment is very mysterious.
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